1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 #include "umc_v8_7.h" 29 30 #include "hdp/hdp_5_0_0_offset.h" 31 #include "hdp/hdp_5_0_0_sh_mask.h" 32 #include "athub/athub_2_0_0_sh_mask.h" 33 #include "athub/athub_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_sh_mask.h" 36 #include "oss/osssys_5_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 40 #include "soc15.h" 41 #include "soc15d.h" 42 #include "soc15_common.h" 43 44 #include "nbio_v2_3.h" 45 46 #include "gfxhub_v2_0.h" 47 #include "gfxhub_v2_1.h" 48 #include "mmhub_v2_0.h" 49 #include "mmhub_v2_3.h" 50 #include "athub_v2_0.h" 51 #include "athub_v2_1.h" 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 61 struct amdgpu_irq_src *src, 62 unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 return 0; 66 } 67 68 static int 69 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 70 struct amdgpu_irq_src *src, unsigned type, 71 enum amdgpu_interrupt_state state) 72 { 73 switch (state) { 74 case AMDGPU_IRQ_STATE_DISABLE: 75 /* MM HUB */ 76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 77 /* GFX HUB */ 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 83 /* GFX HUB */ 84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 85 break; 86 default: 87 break; 88 } 89 90 return 0; 91 } 92 93 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 94 struct amdgpu_irq_src *source, 95 struct amdgpu_iv_entry *entry) 96 { 97 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 98 uint32_t status = 0; 99 u64 addr; 100 101 addr = (u64)entry->src_data[0] << 12; 102 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 103 104 if (!amdgpu_sriov_vf(adev)) { 105 /* 106 * Issue a dummy read to wait for the status register to 107 * be updated to avoid reading an incorrect value due to 108 * the new fast GRBM interface. 109 */ 110 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 111 (adev->asic_type < CHIP_SIENNA_CICHLID)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 } 117 118 if (printk_ratelimit()) { 119 struct amdgpu_task_info task_info; 120 121 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 122 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 126 "for process %s pid %d thread %s pid %d)\n", 127 entry->vmid_src ? "mmhub" : "gfxhub", 128 entry->src_id, entry->ring_id, entry->vmid, 129 entry->pasid, task_info.process_name, task_info.tgid, 130 task_info.task_name, task_info.pid); 131 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 132 addr, entry->client_id); 133 if (!amdgpu_sriov_vf(adev)) 134 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 135 } 136 137 return 0; 138 } 139 140 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 141 .set = gmc_v10_0_vm_fault_interrupt_state, 142 .process = gmc_v10_0_process_interrupt, 143 }; 144 145 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 146 .set = gmc_v10_0_ecc_interrupt_state, 147 .process = amdgpu_umc_process_ecc_irq, 148 }; 149 150 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 151 { 152 adev->gmc.vm_fault.num_types = 1; 153 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 154 155 if (!amdgpu_sriov_vf(adev)) { 156 adev->gmc.ecc_irq.num_types = 1; 157 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 158 } 159 } 160 161 /** 162 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 163 * 164 * @adev: amdgpu_device pointer 165 * @vmhub: vmhub type 166 * 167 */ 168 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 169 uint32_t vmhub) 170 { 171 return ((vmhub == AMDGPU_MMHUB_0 || 172 vmhub == AMDGPU_MMHUB_1) && 173 (!amdgpu_sriov_vf(adev))); 174 } 175 176 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 177 struct amdgpu_device *adev, 178 uint8_t vmid, uint16_t *p_pasid) 179 { 180 uint32_t value; 181 182 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 183 + vmid); 184 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 185 186 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 187 } 188 189 /* 190 * GART 191 * VMID 0 is the physical GPU addresses as used by the kernel. 192 * VMIDs 1-15 are used for userspace clients and are handled 193 * by the amdgpu vm/hsa code. 194 */ 195 196 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 197 unsigned int vmhub, uint32_t flush_type) 198 { 199 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 200 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 201 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 202 u32 tmp; 203 /* Use register 17 for GART */ 204 const unsigned eng = 17; 205 unsigned int i; 206 207 spin_lock(&adev->gmc.invalidate_lock); 208 /* 209 * It may lose gpuvm invalidate acknowldege state across power-gating 210 * off cycle, add semaphore acquire before invalidation and semaphore 211 * release after invalidation to avoid entering power gated state 212 * to WA the Issue 213 */ 214 215 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 216 if (use_semaphore) { 217 for (i = 0; i < adev->usec_timeout; i++) { 218 /* a read return value of 1 means semaphore acuqire */ 219 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 220 hub->eng_distance * eng); 221 if (tmp & 0x1) 222 break; 223 udelay(1); 224 } 225 226 if (i >= adev->usec_timeout) 227 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 228 } 229 230 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 231 232 /* 233 * Issue a dummy read to wait for the ACK register to be cleared 234 * to avoid a false ACK due to the new fast GRBM interface. 235 */ 236 if ((vmhub == AMDGPU_GFXHUB_0) && 237 (adev->asic_type < CHIP_SIENNA_CICHLID)) 238 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); 239 240 /* Wait for ACK with a delay.*/ 241 for (i = 0; i < adev->usec_timeout; i++) { 242 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 243 hub->eng_distance * eng); 244 tmp &= 1 << vmid; 245 if (tmp) 246 break; 247 248 udelay(1); 249 } 250 251 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 252 if (use_semaphore) 253 /* 254 * add semaphore release after invalidation, 255 * write with 0 means semaphore release 256 */ 257 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 258 hub->eng_distance * eng, 0); 259 260 spin_unlock(&adev->gmc.invalidate_lock); 261 262 if (i < adev->usec_timeout) 263 return; 264 265 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 266 } 267 268 /** 269 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 270 * 271 * @adev: amdgpu_device pointer 272 * @vmid: vm instance to flush 273 * 274 * Flush the TLB for the requested page table. 275 */ 276 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 277 uint32_t vmhub, uint32_t flush_type) 278 { 279 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 280 struct dma_fence *fence; 281 struct amdgpu_job *job; 282 283 int r; 284 285 /* flush hdp cache */ 286 adev->nbio.funcs->hdp_flush(adev, NULL); 287 288 /* For SRIOV run time, driver shouldn't access the register through MMIO 289 * Directly use kiq to do the vm invalidation instead 290 */ 291 if (adev->gfx.kiq.ring.sched.ready && 292 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 293 down_read_trylock(&adev->reset_sem)) { 294 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 295 const unsigned eng = 17; 296 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 297 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 298 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 299 300 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 301 1 << vmid); 302 303 up_read(&adev->reset_sem); 304 return; 305 } 306 307 mutex_lock(&adev->mman.gtt_window_lock); 308 309 if (vmhub == AMDGPU_MMHUB_0) { 310 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 311 mutex_unlock(&adev->mman.gtt_window_lock); 312 return; 313 } 314 315 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 316 317 if (!adev->mman.buffer_funcs_enabled || 318 !adev->ib_pool_ready || 319 amdgpu_in_reset(adev) || 320 ring->sched.ready == false) { 321 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 322 mutex_unlock(&adev->mman.gtt_window_lock); 323 return; 324 } 325 326 /* The SDMA on Navi has a bug which can theoretically result in memory 327 * corruption if an invalidation happens at the same time as an VA 328 * translation. Avoid this by doing the invalidation from the SDMA 329 * itself. 330 */ 331 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 332 &job); 333 if (r) 334 goto error_alloc; 335 336 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 337 job->vm_needs_flush = true; 338 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 339 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 340 r = amdgpu_job_submit(job, &adev->mman.entity, 341 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 342 if (r) 343 goto error_submit; 344 345 mutex_unlock(&adev->mman.gtt_window_lock); 346 347 dma_fence_wait(fence, false); 348 dma_fence_put(fence); 349 350 return; 351 352 error_submit: 353 amdgpu_job_free(job); 354 355 error_alloc: 356 mutex_unlock(&adev->mman.gtt_window_lock); 357 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 358 } 359 360 /** 361 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 362 * 363 * @adev: amdgpu_device pointer 364 * @pasid: pasid to be flush 365 * 366 * Flush the TLB for the requested pasid. 367 */ 368 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 369 uint16_t pasid, uint32_t flush_type, 370 bool all_hub) 371 { 372 int vmid, i; 373 signed long r; 374 uint32_t seq; 375 uint16_t queried_pasid; 376 bool ret; 377 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 378 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 379 380 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 381 spin_lock(&adev->gfx.kiq.ring_lock); 382 /* 2 dwords flush + 8 dwords fence */ 383 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 384 kiq->pmf->kiq_invalidate_tlbs(ring, 385 pasid, flush_type, all_hub); 386 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 387 if (r) { 388 amdgpu_ring_undo(ring); 389 spin_unlock(&adev->gfx.kiq.ring_lock); 390 return -ETIME; 391 } 392 393 amdgpu_ring_commit(ring); 394 spin_unlock(&adev->gfx.kiq.ring_lock); 395 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 396 if (r < 1) { 397 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 398 return -ETIME; 399 } 400 401 return 0; 402 } 403 404 for (vmid = 1; vmid < 16; vmid++) { 405 406 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 407 &queried_pasid); 408 if (ret && queried_pasid == pasid) { 409 if (all_hub) { 410 for (i = 0; i < adev->num_vmhubs; i++) 411 gmc_v10_0_flush_gpu_tlb(adev, vmid, 412 i, flush_type); 413 } else { 414 gmc_v10_0_flush_gpu_tlb(adev, vmid, 415 AMDGPU_GFXHUB_0, flush_type); 416 } 417 break; 418 } 419 } 420 421 return 0; 422 } 423 424 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 425 unsigned vmid, uint64_t pd_addr) 426 { 427 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 428 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 429 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 430 unsigned eng = ring->vm_inv_eng; 431 432 /* 433 * It may lose gpuvm invalidate acknowldege state across power-gating 434 * off cycle, add semaphore acquire before invalidation and semaphore 435 * release after invalidation to avoid entering power gated state 436 * to WA the Issue 437 */ 438 439 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 440 if (use_semaphore) 441 /* a read return value of 1 means semaphore acuqire */ 442 amdgpu_ring_emit_reg_wait(ring, 443 hub->vm_inv_eng0_sem + 444 hub->eng_distance * eng, 0x1, 0x1); 445 446 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 447 (hub->ctx_addr_distance * vmid), 448 lower_32_bits(pd_addr)); 449 450 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 451 (hub->ctx_addr_distance * vmid), 452 upper_32_bits(pd_addr)); 453 454 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 455 hub->eng_distance * eng, 456 hub->vm_inv_eng0_ack + 457 hub->eng_distance * eng, 458 req, 1 << vmid); 459 460 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 461 if (use_semaphore) 462 /* 463 * add semaphore release after invalidation, 464 * write with 0 means semaphore release 465 */ 466 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 467 hub->eng_distance * eng, 0); 468 469 return pd_addr; 470 } 471 472 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 473 unsigned pasid) 474 { 475 struct amdgpu_device *adev = ring->adev; 476 uint32_t reg; 477 478 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 479 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 480 else 481 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 482 483 amdgpu_ring_emit_wreg(ring, reg, pasid); 484 } 485 486 /* 487 * PTE format on NAVI 10: 488 * 63:59 reserved 489 * 58 reserved and for sienna_cichlid is used for MALL noalloc 490 * 57 reserved 491 * 56 F 492 * 55 L 493 * 54 reserved 494 * 53:52 SW 495 * 51 T 496 * 50:48 mtype 497 * 47:12 4k physical page base address 498 * 11:7 fragment 499 * 6 write 500 * 5 read 501 * 4 exe 502 * 3 Z 503 * 2 snooped 504 * 1 system 505 * 0 valid 506 * 507 * PDE format on NAVI 10: 508 * 63:59 block fragment size 509 * 58:55 reserved 510 * 54 P 511 * 53:48 reserved 512 * 47:6 physical base address of PD or PTE 513 * 5:3 reserved 514 * 2 C 515 * 1 system 516 * 0 valid 517 */ 518 519 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 520 { 521 switch (flags) { 522 case AMDGPU_VM_MTYPE_DEFAULT: 523 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 524 case AMDGPU_VM_MTYPE_NC: 525 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 526 case AMDGPU_VM_MTYPE_WC: 527 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 528 case AMDGPU_VM_MTYPE_CC: 529 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 530 case AMDGPU_VM_MTYPE_UC: 531 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 532 default: 533 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 534 } 535 } 536 537 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 538 uint64_t *addr, uint64_t *flags) 539 { 540 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 541 *addr = adev->vm_manager.vram_base_offset + *addr - 542 adev->gmc.vram_start; 543 BUG_ON(*addr & 0xFFFF00000000003FULL); 544 545 if (!adev->gmc.translate_further) 546 return; 547 548 if (level == AMDGPU_VM_PDB1) { 549 /* Set the block fragment size */ 550 if (!(*flags & AMDGPU_PDE_PTE)) 551 *flags |= AMDGPU_PDE_BFS(0x9); 552 553 } else if (level == AMDGPU_VM_PDB0) { 554 if (*flags & AMDGPU_PDE_PTE) 555 *flags &= ~AMDGPU_PDE_PTE; 556 else 557 *flags |= AMDGPU_PTE_TF; 558 } 559 } 560 561 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 562 struct amdgpu_bo_va_mapping *mapping, 563 uint64_t *flags) 564 { 565 *flags &= ~AMDGPU_PTE_EXECUTABLE; 566 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 567 568 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 569 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 570 571 if (mapping->flags & AMDGPU_PTE_PRT) { 572 *flags |= AMDGPU_PTE_PRT; 573 *flags |= AMDGPU_PTE_SNOOPED; 574 *flags |= AMDGPU_PTE_LOG; 575 *flags |= AMDGPU_PTE_SYSTEM; 576 *flags &= ~AMDGPU_PTE_VALID; 577 } 578 } 579 580 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 581 { 582 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 583 unsigned size; 584 585 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 586 size = AMDGPU_VBIOS_VGA_ALLOCATION; 587 } else { 588 u32 viewport; 589 u32 pitch; 590 591 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 592 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 593 size = (REG_GET_FIELD(viewport, 594 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 595 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 596 4); 597 } 598 599 return size; 600 } 601 602 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 603 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 604 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 605 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 606 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 607 .map_mtype = gmc_v10_0_map_mtype, 608 .get_vm_pde = gmc_v10_0_get_vm_pde, 609 .get_vm_pte = gmc_v10_0_get_vm_pte, 610 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 611 }; 612 613 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 614 { 615 if (adev->gmc.gmc_funcs == NULL) 616 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 617 } 618 619 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 620 { 621 switch (adev->asic_type) { 622 case CHIP_SIENNA_CICHLID: 623 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 624 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 625 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 626 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 627 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 628 adev->umc.funcs = &umc_v8_7_funcs; 629 break; 630 default: 631 break; 632 } 633 } 634 635 636 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 637 { 638 switch (adev->asic_type) { 639 case CHIP_VANGOGH: 640 adev->mmhub.funcs = &mmhub_v2_3_funcs; 641 break; 642 default: 643 adev->mmhub.funcs = &mmhub_v2_0_funcs; 644 break; 645 } 646 } 647 648 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 649 { 650 switch (adev->asic_type) { 651 case CHIP_SIENNA_CICHLID: 652 case CHIP_NAVY_FLOUNDER: 653 case CHIP_VANGOGH: 654 case CHIP_DIMGREY_CAVEFISH: 655 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 656 break; 657 default: 658 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 659 break; 660 } 661 } 662 663 664 static int gmc_v10_0_early_init(void *handle) 665 { 666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 667 668 gmc_v10_0_set_mmhub_funcs(adev); 669 gmc_v10_0_set_gfxhub_funcs(adev); 670 gmc_v10_0_set_gmc_funcs(adev); 671 gmc_v10_0_set_irq_funcs(adev); 672 gmc_v10_0_set_umc_funcs(adev); 673 674 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 675 adev->gmc.shared_aperture_end = 676 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 677 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 678 adev->gmc.private_aperture_end = 679 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 680 681 return 0; 682 } 683 684 static int gmc_v10_0_late_init(void *handle) 685 { 686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687 int r; 688 689 amdgpu_bo_late_init(adev); 690 691 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 692 if (r) 693 return r; 694 695 r = amdgpu_gmc_ras_late_init(adev); 696 if (r) 697 return r; 698 699 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 700 } 701 702 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 703 struct amdgpu_gmc *mc) 704 { 705 u64 base = 0; 706 707 base = adev->gfxhub.funcs->get_fb_location(adev); 708 709 /* add the xgmi offset of the physical node */ 710 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 711 712 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 713 amdgpu_gmc_gart_location(adev, mc); 714 715 /* base offset of vram pages */ 716 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 717 718 /* add the xgmi offset of the physical node */ 719 adev->vm_manager.vram_base_offset += 720 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 721 } 722 723 /** 724 * gmc_v10_0_mc_init - initialize the memory controller driver params 725 * 726 * @adev: amdgpu_device pointer 727 * 728 * Look up the amount of vram, vram width, and decide how to place 729 * vram and gart within the GPU's physical address space. 730 * Returns 0 for success. 731 */ 732 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 733 { 734 int r; 735 736 /* size in MB on si */ 737 adev->gmc.mc_vram_size = 738 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 739 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 740 741 if (!(adev->flags & AMD_IS_APU)) { 742 r = amdgpu_device_resize_fb_bar(adev); 743 if (r) 744 return r; 745 } 746 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 747 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 748 749 #ifdef CONFIG_X86_64 750 if (adev->flags & AMD_IS_APU) { 751 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 752 adev->gmc.aper_size = adev->gmc.real_vram_size; 753 } 754 #endif 755 756 /* In case the PCI BAR is larger than the actual amount of vram */ 757 adev->gmc.visible_vram_size = adev->gmc.aper_size; 758 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 759 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 760 761 /* set the gart size */ 762 if (amdgpu_gart_size == -1) { 763 switch (adev->asic_type) { 764 case CHIP_NAVI10: 765 case CHIP_NAVI14: 766 case CHIP_NAVI12: 767 case CHIP_SIENNA_CICHLID: 768 case CHIP_NAVY_FLOUNDER: 769 case CHIP_VANGOGH: 770 case CHIP_DIMGREY_CAVEFISH: 771 default: 772 adev->gmc.gart_size = 512ULL << 20; 773 break; 774 } 775 } else 776 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 777 778 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 779 780 return 0; 781 } 782 783 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 784 { 785 int r; 786 787 if (adev->gart.bo) { 788 WARN(1, "NAVI10 PCIE GART already initialized\n"); 789 return 0; 790 } 791 792 /* Initialize common gart structure */ 793 r = amdgpu_gart_init(adev); 794 if (r) 795 return r; 796 797 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 798 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 799 AMDGPU_PTE_EXECUTABLE; 800 801 return amdgpu_gart_table_vram_alloc(adev); 802 } 803 804 static int gmc_v10_0_sw_init(void *handle) 805 { 806 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 807 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 808 809 adev->gfxhub.funcs->init(adev); 810 811 adev->mmhub.funcs->init(adev); 812 813 spin_lock_init(&adev->gmc.invalidate_lock); 814 815 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 816 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 817 adev->gmc.vram_width = 64; 818 } else if (amdgpu_emu_mode == 1) { 819 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 820 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 821 } else { 822 r = amdgpu_atomfirmware_get_vram_info(adev, 823 &vram_width, &vram_type, &vram_vendor); 824 adev->gmc.vram_width = vram_width; 825 826 adev->gmc.vram_type = vram_type; 827 adev->gmc.vram_vendor = vram_vendor; 828 } 829 830 switch (adev->asic_type) { 831 case CHIP_NAVI10: 832 case CHIP_NAVI14: 833 case CHIP_NAVI12: 834 case CHIP_SIENNA_CICHLID: 835 case CHIP_NAVY_FLOUNDER: 836 case CHIP_VANGOGH: 837 case CHIP_DIMGREY_CAVEFISH: 838 adev->num_vmhubs = 2; 839 /* 840 * To fulfill 4-level page support, 841 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 842 * block size 512 (9bit) 843 */ 844 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 845 break; 846 default: 847 break; 848 } 849 850 /* This interrupt is VMC page fault.*/ 851 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 852 VMC_1_0__SRCID__VM_FAULT, 853 &adev->gmc.vm_fault); 854 855 if (r) 856 return r; 857 858 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 859 UTCL2_1_0__SRCID__FAULT, 860 &adev->gmc.vm_fault); 861 if (r) 862 return r; 863 864 if (!amdgpu_sriov_vf(adev)) { 865 /* interrupt sent to DF. */ 866 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 867 &adev->gmc.ecc_irq); 868 if (r) 869 return r; 870 } 871 872 /* 873 * Set the internal MC address mask This is the max address of the GPU's 874 * internal address space. 875 */ 876 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 877 878 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 879 if (r) { 880 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 881 return r; 882 } 883 884 if (adev->gmc.xgmi.supported) { 885 r = adev->gfxhub.funcs->get_xgmi_info(adev); 886 if (r) 887 return r; 888 } 889 890 r = gmc_v10_0_mc_init(adev); 891 if (r) 892 return r; 893 894 amdgpu_gmc_get_vbios_allocations(adev); 895 896 /* Memory manager */ 897 r = amdgpu_bo_init(adev); 898 if (r) 899 return r; 900 901 r = gmc_v10_0_gart_init(adev); 902 if (r) 903 return r; 904 905 /* 906 * number of VMs 907 * VMID 0 is reserved for System 908 * amdgpu graphics/compute will use VMIDs 1-7 909 * amdkfd will use VMIDs 8-15 910 */ 911 adev->vm_manager.first_kfd_vmid = 8; 912 913 amdgpu_vm_manager_init(adev); 914 915 return 0; 916 } 917 918 /** 919 * gmc_v8_0_gart_fini - vm fini callback 920 * 921 * @adev: amdgpu_device pointer 922 * 923 * Tears down the driver GART/VM setup (CIK). 924 */ 925 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 926 { 927 amdgpu_gart_table_vram_free(adev); 928 amdgpu_gart_fini(adev); 929 } 930 931 static int gmc_v10_0_sw_fini(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 amdgpu_vm_manager_fini(adev); 936 gmc_v10_0_gart_fini(adev); 937 amdgpu_gem_force_release(adev); 938 amdgpu_bo_fini(adev); 939 940 return 0; 941 } 942 943 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 944 { 945 switch (adev->asic_type) { 946 case CHIP_NAVI10: 947 case CHIP_NAVI14: 948 case CHIP_NAVI12: 949 case CHIP_SIENNA_CICHLID: 950 case CHIP_NAVY_FLOUNDER: 951 case CHIP_VANGOGH: 952 case CHIP_DIMGREY_CAVEFISH: 953 break; 954 default: 955 break; 956 } 957 } 958 959 /** 960 * gmc_v10_0_gart_enable - gart enable 961 * 962 * @adev: amdgpu_device pointer 963 */ 964 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 965 { 966 int r; 967 bool value; 968 u32 tmp; 969 970 if (adev->gart.bo == NULL) { 971 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 972 return -EINVAL; 973 } 974 975 r = amdgpu_gart_table_vram_pin(adev); 976 if (r) 977 return r; 978 979 r = adev->gfxhub.funcs->gart_enable(adev); 980 if (r) 981 return r; 982 983 r = adev->mmhub.funcs->gart_enable(adev); 984 if (r) 985 return r; 986 987 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 988 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 989 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 990 991 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 992 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 993 994 /* Flush HDP after it is initialized */ 995 adev->nbio.funcs->hdp_flush(adev, NULL); 996 997 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 998 false : true; 999 1000 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1001 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1002 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1003 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1004 1005 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1006 (unsigned)(adev->gmc.gart_size >> 20), 1007 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1008 1009 adev->gart.ready = true; 1010 1011 return 0; 1012 } 1013 1014 static int gmc_v10_0_hw_init(void *handle) 1015 { 1016 int r; 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 1019 /* The sequence of these two function calls matters.*/ 1020 gmc_v10_0_init_golden_registers(adev); 1021 1022 r = gmc_v10_0_gart_enable(adev); 1023 if (r) 1024 return r; 1025 1026 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1027 adev->umc.funcs->init_registers(adev); 1028 1029 return 0; 1030 } 1031 1032 /** 1033 * gmc_v10_0_gart_disable - gart disable 1034 * 1035 * @adev: amdgpu_device pointer 1036 * 1037 * This disables all VM page table. 1038 */ 1039 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1040 { 1041 adev->gfxhub.funcs->gart_disable(adev); 1042 adev->mmhub.funcs->gart_disable(adev); 1043 amdgpu_gart_table_vram_unpin(adev); 1044 } 1045 1046 static int gmc_v10_0_hw_fini(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 1050 if (amdgpu_sriov_vf(adev)) { 1051 /* full access mode, so don't touch any GMC register */ 1052 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1053 return 0; 1054 } 1055 1056 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1057 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1058 gmc_v10_0_gart_disable(adev); 1059 1060 return 0; 1061 } 1062 1063 static int gmc_v10_0_suspend(void *handle) 1064 { 1065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1066 1067 gmc_v10_0_hw_fini(adev); 1068 1069 return 0; 1070 } 1071 1072 static int gmc_v10_0_resume(void *handle) 1073 { 1074 int r; 1075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1076 1077 r = gmc_v10_0_hw_init(adev); 1078 if (r) 1079 return r; 1080 1081 amdgpu_vmid_reset_all(adev); 1082 1083 return 0; 1084 } 1085 1086 static bool gmc_v10_0_is_idle(void *handle) 1087 { 1088 /* MC is always ready in GMC v10.*/ 1089 return true; 1090 } 1091 1092 static int gmc_v10_0_wait_for_idle(void *handle) 1093 { 1094 /* There is no need to wait for MC idle in GMC v10.*/ 1095 return 0; 1096 } 1097 1098 static int gmc_v10_0_soft_reset(void *handle) 1099 { 1100 return 0; 1101 } 1102 1103 static int gmc_v10_0_set_clockgating_state(void *handle, 1104 enum amd_clockgating_state state) 1105 { 1106 int r; 1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1108 1109 r = adev->mmhub.funcs->set_clockgating(adev, state); 1110 if (r) 1111 return r; 1112 1113 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1114 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1115 return athub_v2_1_set_clockgating(adev, state); 1116 else 1117 return athub_v2_0_set_clockgating(adev, state); 1118 } 1119 1120 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1121 { 1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1123 1124 adev->mmhub.funcs->get_clockgating(adev, flags); 1125 1126 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1127 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1128 athub_v2_1_get_clockgating(adev, flags); 1129 else 1130 athub_v2_0_get_clockgating(adev, flags); 1131 } 1132 1133 static int gmc_v10_0_set_powergating_state(void *handle, 1134 enum amd_powergating_state state) 1135 { 1136 return 0; 1137 } 1138 1139 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1140 .name = "gmc_v10_0", 1141 .early_init = gmc_v10_0_early_init, 1142 .late_init = gmc_v10_0_late_init, 1143 .sw_init = gmc_v10_0_sw_init, 1144 .sw_fini = gmc_v10_0_sw_fini, 1145 .hw_init = gmc_v10_0_hw_init, 1146 .hw_fini = gmc_v10_0_hw_fini, 1147 .suspend = gmc_v10_0_suspend, 1148 .resume = gmc_v10_0_resume, 1149 .is_idle = gmc_v10_0_is_idle, 1150 .wait_for_idle = gmc_v10_0_wait_for_idle, 1151 .soft_reset = gmc_v10_0_soft_reset, 1152 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1153 .set_powergating_state = gmc_v10_0_set_powergating_state, 1154 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1155 }; 1156 1157 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1158 { 1159 .type = AMD_IP_BLOCK_TYPE_GMC, 1160 .major = 10, 1161 .minor = 0, 1162 .rev = 0, 1163 .funcs = &gmc_v10_0_ip_funcs, 1164 }; 1165