1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 29 #include "hdp/hdp_5_0_0_offset.h" 30 #include "hdp/hdp_5_0_0_sh_mask.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "mmhub/mmhub_2_0_0_sh_mask.h" 33 #include "dcn/dcn_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_sh_mask.h" 35 #include "oss/osssys_5_0_0_offset.h" 36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 37 #include "navi10_enum.h" 38 39 #include "soc15.h" 40 #include "soc15_common.h" 41 42 #include "nbio_v2_3.h" 43 44 #include "gfxhub_v2_0.h" 45 #include "mmhub_v2_0.h" 46 #include "athub_v2_0.h" 47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/ 48 #define AMDGPU_NUM_OF_VMIDS 8 49 50 #if 0 51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 52 { 53 /* TODO add golden setting for hdp */ 54 }; 55 #endif 56 57 static int 58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 59 struct amdgpu_irq_src *src, unsigned type, 60 enum amdgpu_interrupt_state state) 61 { 62 struct amdgpu_vmhub *hub; 63 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; 64 65 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 66 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 67 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 68 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 69 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 70 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 71 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 72 73 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 74 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 75 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 76 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 77 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 78 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 80 81 switch (state) { 82 case AMDGPU_IRQ_STATE_DISABLE: 83 /* MM HUB */ 84 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 85 for (i = 0; i < 16; i++) { 86 reg = hub->vm_context0_cntl + i; 87 tmp = RREG32(reg); 88 tmp &= ~bits[AMDGPU_MMHUB_0]; 89 WREG32(reg, tmp); 90 } 91 92 /* GFX HUB */ 93 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 94 for (i = 0; i < 16; i++) { 95 reg = hub->vm_context0_cntl + i; 96 tmp = RREG32(reg); 97 tmp &= ~bits[AMDGPU_GFXHUB_0]; 98 WREG32(reg, tmp); 99 } 100 break; 101 case AMDGPU_IRQ_STATE_ENABLE: 102 /* MM HUB */ 103 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 104 for (i = 0; i < 16; i++) { 105 reg = hub->vm_context0_cntl + i; 106 tmp = RREG32(reg); 107 tmp |= bits[AMDGPU_MMHUB_0]; 108 WREG32(reg, tmp); 109 } 110 111 /* GFX HUB */ 112 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 113 for (i = 0; i < 16; i++) { 114 reg = hub->vm_context0_cntl + i; 115 tmp = RREG32(reg); 116 tmp |= bits[AMDGPU_GFXHUB_0]; 117 WREG32(reg, tmp); 118 } 119 break; 120 default: 121 break; 122 } 123 124 return 0; 125 } 126 127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 128 struct amdgpu_irq_src *source, 129 struct amdgpu_iv_entry *entry) 130 { 131 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 132 uint32_t status = 0; 133 u64 addr; 134 135 addr = (u64)entry->src_data[0] << 12; 136 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 137 138 if (!amdgpu_sriov_vf(adev)) { 139 /* 140 * Issue a dummy read to wait for the status register to 141 * be updated to avoid reading an incorrect value due to 142 * the new fast GRBM interface. 143 */ 144 if (entry->vmid_src == AMDGPU_GFXHUB_0) 145 RREG32(hub->vm_l2_pro_fault_status); 146 147 status = RREG32(hub->vm_l2_pro_fault_status); 148 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 149 } 150 151 if (printk_ratelimit()) { 152 struct amdgpu_task_info task_info; 153 154 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 155 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 156 157 dev_err(adev->dev, 158 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 159 "for process %s pid %d thread %s pid %d)\n", 160 entry->vmid_src ? "mmhub" : "gfxhub", 161 entry->src_id, entry->ring_id, entry->vmid, 162 entry->pasid, task_info.process_name, task_info.tgid, 163 task_info.task_name, task_info.pid); 164 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 165 addr, entry->client_id); 166 if (!amdgpu_sriov_vf(adev)) { 167 dev_err(adev->dev, 168 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 169 status); 170 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 171 REG_GET_FIELD(status, 172 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 173 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 174 REG_GET_FIELD(status, 175 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 176 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 177 REG_GET_FIELD(status, 178 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 179 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 180 REG_GET_FIELD(status, 181 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 182 dev_err(adev->dev, "\t RW: 0x%lx\n", 183 REG_GET_FIELD(status, 184 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 185 } 186 } 187 188 return 0; 189 } 190 191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 192 .set = gmc_v10_0_vm_fault_interrupt_state, 193 .process = gmc_v10_0_process_interrupt, 194 }; 195 196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 197 { 198 adev->gmc.vm_fault.num_types = 1; 199 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 200 } 201 202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, 203 uint32_t flush_type) 204 { 205 u32 req = 0; 206 207 /* invalidate using legacy mode on vmid*/ 208 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 209 PER_VMID_INVALIDATE_REQ, 1 << vmid); 210 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 211 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 212 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 213 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 215 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 217 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 218 219 return req; 220 } 221 222 /* 223 * GART 224 * VMID 0 is the physical GPU addresses as used by the kernel. 225 * VMIDs 1-15 are used for userspace clients and are handled 226 * by the amdgpu vm/hsa code. 227 */ 228 229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 230 unsigned int vmhub, uint32_t flush_type) 231 { 232 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 233 u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type); 234 /* Use register 17 for GART */ 235 const unsigned eng = 17; 236 unsigned int i; 237 238 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 239 240 /* 241 * Issue a dummy read to wait for the ACK register to be cleared 242 * to avoid a false ACK due to the new fast GRBM interface. 243 */ 244 if (vmhub == AMDGPU_GFXHUB_0) 245 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 246 247 /* Wait for ACK with a delay.*/ 248 for (i = 0; i < adev->usec_timeout; i++) { 249 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 250 tmp &= 1 << vmid; 251 if (tmp) 252 break; 253 254 udelay(1); 255 } 256 257 if (i < adev->usec_timeout) 258 return; 259 260 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 261 } 262 263 /** 264 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 265 * 266 * @adev: amdgpu_device pointer 267 * @vmid: vm instance to flush 268 * 269 * Flush the TLB for the requested page table. 270 */ 271 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 272 uint32_t vmhub, uint32_t flush_type) 273 { 274 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 275 struct dma_fence *fence; 276 struct amdgpu_job *job; 277 278 int r; 279 280 /* flush hdp cache */ 281 adev->nbio.funcs->hdp_flush(adev, NULL); 282 283 mutex_lock(&adev->mman.gtt_window_lock); 284 285 if (vmhub == AMDGPU_MMHUB_0) { 286 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 287 mutex_unlock(&adev->mman.gtt_window_lock); 288 return; 289 } 290 291 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 292 293 if (!adev->mman.buffer_funcs_enabled || 294 !adev->ib_pool_ready || 295 adev->in_gpu_reset) { 296 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 297 mutex_unlock(&adev->mman.gtt_window_lock); 298 return; 299 } 300 301 /* The SDMA on Navi has a bug which can theoretically result in memory 302 * corruption if an invalidation happens at the same time as an VA 303 * translation. Avoid this by doing the invalidation from the SDMA 304 * itself. 305 */ 306 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job); 307 if (r) 308 goto error_alloc; 309 310 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 311 job->vm_needs_flush = true; 312 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 313 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 314 r = amdgpu_job_submit(job, &adev->mman.entity, 315 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 316 if (r) 317 goto error_submit; 318 319 mutex_unlock(&adev->mman.gtt_window_lock); 320 321 dma_fence_wait(fence, false); 322 dma_fence_put(fence); 323 324 return; 325 326 error_submit: 327 amdgpu_job_free(job); 328 329 error_alloc: 330 mutex_unlock(&adev->mman.gtt_window_lock); 331 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 332 } 333 334 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 335 unsigned vmid, uint64_t pd_addr) 336 { 337 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 338 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); 339 unsigned eng = ring->vm_inv_eng; 340 341 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 342 lower_32_bits(pd_addr)); 343 344 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 345 upper_32_bits(pd_addr)); 346 347 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 348 hub->vm_inv_eng0_ack + eng, 349 req, 1 << vmid); 350 351 return pd_addr; 352 } 353 354 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 355 unsigned pasid) 356 { 357 struct amdgpu_device *adev = ring->adev; 358 uint32_t reg; 359 360 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 361 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 362 else 363 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 364 365 amdgpu_ring_emit_wreg(ring, reg, pasid); 366 } 367 368 /* 369 * PTE format on NAVI 10: 370 * 63:59 reserved 371 * 58:57 reserved 372 * 56 F 373 * 55 L 374 * 54 reserved 375 * 53:52 SW 376 * 51 T 377 * 50:48 mtype 378 * 47:12 4k physical page base address 379 * 11:7 fragment 380 * 6 write 381 * 5 read 382 * 4 exe 383 * 3 Z 384 * 2 snooped 385 * 1 system 386 * 0 valid 387 * 388 * PDE format on NAVI 10: 389 * 63:59 block fragment size 390 * 58:55 reserved 391 * 54 P 392 * 53:48 reserved 393 * 47:6 physical base address of PD or PTE 394 * 5:3 reserved 395 * 2 C 396 * 1 system 397 * 0 valid 398 */ 399 400 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 401 { 402 switch (flags) { 403 case AMDGPU_VM_MTYPE_DEFAULT: 404 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 405 case AMDGPU_VM_MTYPE_NC: 406 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 407 case AMDGPU_VM_MTYPE_WC: 408 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 409 case AMDGPU_VM_MTYPE_CC: 410 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 411 case AMDGPU_VM_MTYPE_UC: 412 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 413 default: 414 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 415 } 416 } 417 418 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 419 uint64_t *addr, uint64_t *flags) 420 { 421 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 422 *addr = adev->vm_manager.vram_base_offset + *addr - 423 adev->gmc.vram_start; 424 BUG_ON(*addr & 0xFFFF00000000003FULL); 425 426 if (!adev->gmc.translate_further) 427 return; 428 429 if (level == AMDGPU_VM_PDB1) { 430 /* Set the block fragment size */ 431 if (!(*flags & AMDGPU_PDE_PTE)) 432 *flags |= AMDGPU_PDE_BFS(0x9); 433 434 } else if (level == AMDGPU_VM_PDB0) { 435 if (*flags & AMDGPU_PDE_PTE) 436 *flags &= ~AMDGPU_PDE_PTE; 437 else 438 *flags |= AMDGPU_PTE_TF; 439 } 440 } 441 442 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 443 struct amdgpu_bo_va_mapping *mapping, 444 uint64_t *flags) 445 { 446 *flags &= ~AMDGPU_PTE_EXECUTABLE; 447 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 448 449 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 450 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 451 452 if (mapping->flags & AMDGPU_PTE_PRT) { 453 *flags |= AMDGPU_PTE_PRT; 454 *flags |= AMDGPU_PTE_SNOOPED; 455 *flags |= AMDGPU_PTE_LOG; 456 *flags |= AMDGPU_PTE_SYSTEM; 457 *flags &= ~AMDGPU_PTE_VALID; 458 } 459 } 460 461 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 462 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 463 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 464 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 465 .map_mtype = gmc_v10_0_map_mtype, 466 .get_vm_pde = gmc_v10_0_get_vm_pde, 467 .get_vm_pte = gmc_v10_0_get_vm_pte 468 }; 469 470 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 471 { 472 if (adev->gmc.gmc_funcs == NULL) 473 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 474 } 475 476 static int gmc_v10_0_early_init(void *handle) 477 { 478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 479 480 gmc_v10_0_set_gmc_funcs(adev); 481 gmc_v10_0_set_irq_funcs(adev); 482 483 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 484 adev->gmc.shared_aperture_end = 485 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 486 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 487 adev->gmc.private_aperture_end = 488 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 489 490 return 0; 491 } 492 493 static int gmc_v10_0_late_init(void *handle) 494 { 495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 496 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; 497 unsigned i; 498 499 for(i = 0; i < adev->num_rings; ++i) { 500 struct amdgpu_ring *ring = adev->rings[i]; 501 unsigned vmhub = ring->funcs->vmhub; 502 503 ring->vm_inv_eng = vm_inv_eng[vmhub]++; 504 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n", 505 ring->idx, ring->name, ring->vm_inv_eng, 506 ring->funcs->vmhub); 507 } 508 509 /* Engine 17 is used for GART flushes */ 510 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 511 BUG_ON(vm_inv_eng[i] > 17); 512 513 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 514 } 515 516 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 517 struct amdgpu_gmc *mc) 518 { 519 u64 base = 0; 520 521 base = gfxhub_v2_0_get_fb_location(adev); 522 523 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 524 amdgpu_gmc_gart_location(adev, mc); 525 526 /* base offset of vram pages */ 527 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); 528 } 529 530 /** 531 * gmc_v10_0_mc_init - initialize the memory controller driver params 532 * 533 * @adev: amdgpu_device pointer 534 * 535 * Look up the amount of vram, vram width, and decide how to place 536 * vram and gart within the GPU's physical address space. 537 * Returns 0 for success. 538 */ 539 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 540 { 541 /* Could aper size report 0 ? */ 542 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 543 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 544 545 /* size in MB on si */ 546 adev->gmc.mc_vram_size = 547 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 548 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 549 adev->gmc.visible_vram_size = adev->gmc.aper_size; 550 551 /* In case the PCI BAR is larger than the actual amount of vram */ 552 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 553 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 554 555 /* set the gart size */ 556 if (amdgpu_gart_size == -1) { 557 switch (adev->asic_type) { 558 case CHIP_NAVI10: 559 case CHIP_NAVI14: 560 case CHIP_NAVI12: 561 default: 562 adev->gmc.gart_size = 512ULL << 20; 563 break; 564 } 565 } else 566 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 567 568 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 569 570 return 0; 571 } 572 573 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 574 { 575 int r; 576 577 if (adev->gart.bo) { 578 WARN(1, "NAVI10 PCIE GART already initialized\n"); 579 return 0; 580 } 581 582 /* Initialize common gart structure */ 583 r = amdgpu_gart_init(adev); 584 if (r) 585 return r; 586 587 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 588 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 589 AMDGPU_PTE_EXECUTABLE; 590 591 return amdgpu_gart_table_vram_alloc(adev); 592 } 593 594 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 595 { 596 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 597 unsigned size; 598 599 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 600 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 601 } else { 602 u32 viewport; 603 u32 pitch; 604 605 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 606 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 607 size = (REG_GET_FIELD(viewport, 608 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 609 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 610 4); 611 } 612 /* return 0 if the pre-OS buffer uses up most of vram */ 613 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { 614 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \ 615 be aware of gart table overwrite\n"); 616 return 0; 617 } 618 619 return size; 620 } 621 622 623 624 static int gmc_v10_0_sw_init(void *handle) 625 { 626 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 628 629 gfxhub_v2_0_init(adev); 630 mmhub_v2_0_init(adev); 631 632 spin_lock_init(&adev->gmc.invalidate_lock); 633 634 r = amdgpu_atomfirmware_get_vram_info(adev, 635 &vram_width, &vram_type, &vram_vendor); 636 if (!amdgpu_emu_mode) 637 adev->gmc.vram_width = vram_width; 638 else 639 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 640 641 adev->gmc.vram_type = vram_type; 642 adev->gmc.vram_vendor = vram_vendor; 643 switch (adev->asic_type) { 644 case CHIP_NAVI10: 645 case CHIP_NAVI14: 646 case CHIP_NAVI12: 647 adev->num_vmhubs = 2; 648 /* 649 * To fulfill 4-level page support, 650 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 651 * block size 512 (9bit) 652 */ 653 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 654 break; 655 default: 656 break; 657 } 658 659 /* This interrupt is VMC page fault.*/ 660 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 661 VMC_1_0__SRCID__VM_FAULT, 662 &adev->gmc.vm_fault); 663 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 664 UTCL2_1_0__SRCID__FAULT, 665 &adev->gmc.vm_fault); 666 if (r) 667 return r; 668 669 /* 670 * Set the internal MC address mask This is the max address of the GPU's 671 * internal address space. 672 */ 673 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 674 675 /* 676 * Reserve 8M stolen memory for navi10 like vega10 677 * TODO: will check if it's really needed on asic. 678 */ 679 if (amdgpu_emu_mode == 1) 680 adev->gmc.stolen_size = 0; 681 else 682 adev->gmc.stolen_size = 9 * 1024 *1024; 683 684 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 685 if (r) { 686 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 687 return r; 688 } 689 690 r = gmc_v10_0_mc_init(adev); 691 if (r) 692 return r; 693 694 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); 695 696 /* Memory manager */ 697 r = amdgpu_bo_init(adev); 698 if (r) 699 return r; 700 701 r = gmc_v10_0_gart_init(adev); 702 if (r) 703 return r; 704 705 /* 706 * number of VMs 707 * VMID 0 is reserved for System 708 * amdgpu graphics/compute will use VMIDs 1-7 709 * amdkfd will use VMIDs 8-15 710 */ 711 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 712 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 713 714 amdgpu_vm_manager_init(adev); 715 716 return 0; 717 } 718 719 /** 720 * gmc_v8_0_gart_fini - vm fini callback 721 * 722 * @adev: amdgpu_device pointer 723 * 724 * Tears down the driver GART/VM setup (CIK). 725 */ 726 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 727 { 728 amdgpu_gart_table_vram_free(adev); 729 amdgpu_gart_fini(adev); 730 } 731 732 static int gmc_v10_0_sw_fini(void *handle) 733 { 734 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 735 736 amdgpu_vm_manager_fini(adev); 737 gmc_v10_0_gart_fini(adev); 738 amdgpu_gem_force_release(adev); 739 amdgpu_bo_fini(adev); 740 741 return 0; 742 } 743 744 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 745 { 746 switch (adev->asic_type) { 747 case CHIP_NAVI10: 748 case CHIP_NAVI14: 749 case CHIP_NAVI12: 750 break; 751 default: 752 break; 753 } 754 } 755 756 /** 757 * gmc_v10_0_gart_enable - gart enable 758 * 759 * @adev: amdgpu_device pointer 760 */ 761 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 762 { 763 int r; 764 bool value; 765 u32 tmp; 766 767 if (adev->gart.bo == NULL) { 768 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 769 return -EINVAL; 770 } 771 772 r = amdgpu_gart_table_vram_pin(adev); 773 if (r) 774 return r; 775 776 r = gfxhub_v2_0_gart_enable(adev); 777 if (r) 778 return r; 779 780 r = mmhub_v2_0_gart_enable(adev); 781 if (r) 782 return r; 783 784 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 785 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 786 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 787 788 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 789 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 790 791 /* Flush HDP after it is initialized */ 792 adev->nbio.funcs->hdp_flush(adev, NULL); 793 794 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 795 false : true; 796 797 gfxhub_v2_0_set_fault_enable_default(adev, value); 798 mmhub_v2_0_set_fault_enable_default(adev, value); 799 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 800 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 801 802 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 803 (unsigned)(adev->gmc.gart_size >> 20), 804 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 805 806 adev->gart.ready = true; 807 808 return 0; 809 } 810 811 static int gmc_v10_0_hw_init(void *handle) 812 { 813 int r; 814 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 815 816 /* The sequence of these two function calls matters.*/ 817 gmc_v10_0_init_golden_registers(adev); 818 819 r = gmc_v10_0_gart_enable(adev); 820 if (r) 821 return r; 822 823 return 0; 824 } 825 826 /** 827 * gmc_v10_0_gart_disable - gart disable 828 * 829 * @adev: amdgpu_device pointer 830 * 831 * This disables all VM page table. 832 */ 833 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 834 { 835 gfxhub_v2_0_gart_disable(adev); 836 mmhub_v2_0_gart_disable(adev); 837 amdgpu_gart_table_vram_unpin(adev); 838 } 839 840 static int gmc_v10_0_hw_fini(void *handle) 841 { 842 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 843 844 if (amdgpu_sriov_vf(adev)) { 845 /* full access mode, so don't touch any GMC register */ 846 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 847 return 0; 848 } 849 850 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 851 gmc_v10_0_gart_disable(adev); 852 853 return 0; 854 } 855 856 static int gmc_v10_0_suspend(void *handle) 857 { 858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 859 860 gmc_v10_0_hw_fini(adev); 861 862 return 0; 863 } 864 865 static int gmc_v10_0_resume(void *handle) 866 { 867 int r; 868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 869 870 r = gmc_v10_0_hw_init(adev); 871 if (r) 872 return r; 873 874 amdgpu_vmid_reset_all(adev); 875 876 return 0; 877 } 878 879 static bool gmc_v10_0_is_idle(void *handle) 880 { 881 /* MC is always ready in GMC v10.*/ 882 return true; 883 } 884 885 static int gmc_v10_0_wait_for_idle(void *handle) 886 { 887 /* There is no need to wait for MC idle in GMC v10.*/ 888 return 0; 889 } 890 891 static int gmc_v10_0_soft_reset(void *handle) 892 { 893 return 0; 894 } 895 896 static int gmc_v10_0_set_clockgating_state(void *handle, 897 enum amd_clockgating_state state) 898 { 899 int r; 900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 901 902 r = mmhub_v2_0_set_clockgating(adev, state); 903 if (r) 904 return r; 905 906 return athub_v2_0_set_clockgating(adev, state); 907 } 908 909 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 910 { 911 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 912 913 mmhub_v2_0_get_clockgating(adev, flags); 914 915 athub_v2_0_get_clockgating(adev, flags); 916 } 917 918 static int gmc_v10_0_set_powergating_state(void *handle, 919 enum amd_powergating_state state) 920 { 921 return 0; 922 } 923 924 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 925 .name = "gmc_v10_0", 926 .early_init = gmc_v10_0_early_init, 927 .late_init = gmc_v10_0_late_init, 928 .sw_init = gmc_v10_0_sw_init, 929 .sw_fini = gmc_v10_0_sw_fini, 930 .hw_init = gmc_v10_0_hw_init, 931 .hw_fini = gmc_v10_0_hw_fini, 932 .suspend = gmc_v10_0_suspend, 933 .resume = gmc_v10_0_resume, 934 .is_idle = gmc_v10_0_is_idle, 935 .wait_for_idle = gmc_v10_0_wait_for_idle, 936 .soft_reset = gmc_v10_0_soft_reset, 937 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 938 .set_powergating_state = gmc_v10_0_set_powergating_state, 939 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 940 }; 941 942 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 943 { 944 .type = AMD_IP_BLOCK_TYPE_GMC, 945 .major = 10, 946 .minor = 0, 947 .rev = 0, 948 .funcs = &gmc_v10_0_ip_funcs, 949 }; 950