1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
25 #include "amdgpu.h"
26 #include "amdgpu_atomfirmware.h"
27 #include "gmc_v10_0.h"
28 
29 #include "hdp/hdp_5_0_0_offset.h"
30 #include "hdp/hdp_5_0_0_sh_mask.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
33 #include "athub/athub_2_0_0_sh_mask.h"
34 #include "athub/athub_2_0_0_offset.h"
35 #include "dcn/dcn_2_0_0_offset.h"
36 #include "dcn/dcn_2_0_0_sh_mask.h"
37 #include "oss/osssys_5_0_0_offset.h"
38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39 #include "navi10_enum.h"
40 
41 #include "soc15.h"
42 #include "soc15d.h"
43 #include "soc15_common.h"
44 
45 #include "nbio_v2_3.h"
46 
47 #include "gfxhub_v2_0.h"
48 #include "mmhub_v2_0.h"
49 #include "athub_v2_0.h"
50 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
51 #define AMDGPU_NUM_OF_VMIDS			8
52 
53 #if 0
54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
55 {
56 	/* TODO add golden setting for hdp */
57 };
58 #endif
59 
60 static int
61 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
62 				   struct amdgpu_irq_src *src, unsigned type,
63 				   enum amdgpu_interrupt_state state)
64 {
65 	struct amdgpu_vmhub *hub;
66 	u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
67 
68 	bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
69 		GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
70 		GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 		GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
72 		GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
73 		GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 		GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
75 
76 	bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
77 		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
78 		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
80 		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
81 		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
82 		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
83 
84 	switch (state) {
85 	case AMDGPU_IRQ_STATE_DISABLE:
86 		/* MM HUB */
87 		hub = &adev->vmhub[AMDGPU_MMHUB_0];
88 		for (i = 0; i < 16; i++) {
89 			reg = hub->vm_context0_cntl + i;
90 			tmp = RREG32(reg);
91 			tmp &= ~bits[AMDGPU_MMHUB_0];
92 			WREG32(reg, tmp);
93 		}
94 
95 		/* GFX HUB */
96 		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
97 		for (i = 0; i < 16; i++) {
98 			reg = hub->vm_context0_cntl + i;
99 			tmp = RREG32(reg);
100 			tmp &= ~bits[AMDGPU_GFXHUB_0];
101 			WREG32(reg, tmp);
102 		}
103 		break;
104 	case AMDGPU_IRQ_STATE_ENABLE:
105 		/* MM HUB */
106 		hub = &adev->vmhub[AMDGPU_MMHUB_0];
107 		for (i = 0; i < 16; i++) {
108 			reg = hub->vm_context0_cntl + i;
109 			tmp = RREG32(reg);
110 			tmp |= bits[AMDGPU_MMHUB_0];
111 			WREG32(reg, tmp);
112 		}
113 
114 		/* GFX HUB */
115 		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
116 		for (i = 0; i < 16; i++) {
117 			reg = hub->vm_context0_cntl + i;
118 			tmp = RREG32(reg);
119 			tmp |= bits[AMDGPU_GFXHUB_0];
120 			WREG32(reg, tmp);
121 		}
122 		break;
123 	default:
124 		break;
125 	}
126 
127 	return 0;
128 }
129 
130 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
131 				       struct amdgpu_irq_src *source,
132 				       struct amdgpu_iv_entry *entry)
133 {
134 	struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
135 	uint32_t status = 0;
136 	u64 addr;
137 
138 	addr = (u64)entry->src_data[0] << 12;
139 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
140 
141 	if (!amdgpu_sriov_vf(adev)) {
142 		/*
143 		 * Issue a dummy read to wait for the status register to
144 		 * be updated to avoid reading an incorrect value due to
145 		 * the new fast GRBM interface.
146 		 */
147 		if (entry->vmid_src == AMDGPU_GFXHUB_0)
148 			RREG32(hub->vm_l2_pro_fault_status);
149 
150 		status = RREG32(hub->vm_l2_pro_fault_status);
151 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
152 	}
153 
154 	if (printk_ratelimit()) {
155 		struct amdgpu_task_info task_info;
156 
157 		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
158 		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
159 
160 		dev_err(adev->dev,
161 			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
162 			"for process %s pid %d thread %s pid %d)\n",
163 			entry->vmid_src ? "mmhub" : "gfxhub",
164 			entry->src_id, entry->ring_id, entry->vmid,
165 			entry->pasid, task_info.process_name, task_info.tgid,
166 			task_info.task_name, task_info.pid);
167 		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
168 			addr, entry->client_id);
169 		if (!amdgpu_sriov_vf(adev)) {
170 			dev_err(adev->dev,
171 				"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
172 				status);
173 			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
174 				REG_GET_FIELD(status,
175 				GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
176 			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
177 				REG_GET_FIELD(status,
178 				GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
179 			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
180 				REG_GET_FIELD(status,
181 				GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
182 			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
183 				REG_GET_FIELD(status,
184 				GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
185 			dev_err(adev->dev, "\t RW: 0x%lx\n",
186 				REG_GET_FIELD(status,
187 				GCVM_L2_PROTECTION_FAULT_STATUS, RW));
188 		}
189 	}
190 
191 	return 0;
192 }
193 
194 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
195 	.set = gmc_v10_0_vm_fault_interrupt_state,
196 	.process = gmc_v10_0_process_interrupt,
197 };
198 
199 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
200 {
201 	adev->gmc.vm_fault.num_types = 1;
202 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
203 }
204 
205 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
206 					     uint32_t flush_type)
207 {
208 	u32 req = 0;
209 
210 	/* invalidate using legacy mode on vmid*/
211 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
212 			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
213 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
214 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
215 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
216 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
217 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
218 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
219 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
220 			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
221 
222 	return req;
223 }
224 
225 /**
226  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
227  *
228  * @adev: amdgpu_device pointer
229  * @vmhub: vmhub type
230  *
231  */
232 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
233 				       uint32_t vmhub)
234 {
235 	return ((vmhub == AMDGPU_MMHUB_0 ||
236 		 vmhub == AMDGPU_MMHUB_1) &&
237 		(!amdgpu_sriov_vf(adev)));
238 }
239 
240 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
241 					struct amdgpu_device *adev,
242 					uint8_t vmid, uint16_t *p_pasid)
243 {
244 	uint32_t value;
245 
246 	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
247 		     + vmid);
248 	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
249 
250 	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
251 }
252 
253 /*
254  * GART
255  * VMID 0 is the physical GPU addresses as used by the kernel.
256  * VMIDs 1-15 are used for userspace clients and are handled
257  * by the amdgpu vm/hsa code.
258  */
259 
260 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
261 				   unsigned int vmhub, uint32_t flush_type)
262 {
263 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
264 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
265 	u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
266 	u32 tmp;
267 	/* Use register 17 for GART */
268 	const unsigned eng = 17;
269 	unsigned int i;
270 
271 	spin_lock(&adev->gmc.invalidate_lock);
272 	/*
273 	 * It may lose gpuvm invalidate acknowldege state across power-gating
274 	 * off cycle, add semaphore acquire before invalidation and semaphore
275 	 * release after invalidation to avoid entering power gated state
276 	 * to WA the Issue
277 	 */
278 
279 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
280 	if (use_semaphore) {
281 		for (i = 0; i < adev->usec_timeout; i++) {
282 			/* a read return value of 1 means semaphore acuqire */
283 			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
284 			if (tmp & 0x1)
285 				break;
286 			udelay(1);
287 		}
288 
289 		if (i >= adev->usec_timeout)
290 			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
291 	}
292 
293 	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
294 
295 	/*
296 	 * Issue a dummy read to wait for the ACK register to be cleared
297 	 * to avoid a false ACK due to the new fast GRBM interface.
298 	 */
299 	if (vmhub == AMDGPU_GFXHUB_0)
300 		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
301 
302 	/* Wait for ACK with a delay.*/
303 	for (i = 0; i < adev->usec_timeout; i++) {
304 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
305 		tmp &= 1 << vmid;
306 		if (tmp)
307 			break;
308 
309 		udelay(1);
310 	}
311 
312 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
313 	if (use_semaphore)
314 		/*
315 		 * add semaphore release after invalidation,
316 		 * write with 0 means semaphore release
317 		 */
318 		WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
319 
320 	spin_unlock(&adev->gmc.invalidate_lock);
321 
322 	if (i < adev->usec_timeout)
323 		return;
324 
325 	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
326 }
327 
328 /**
329  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
330  *
331  * @adev: amdgpu_device pointer
332  * @vmid: vm instance to flush
333  *
334  * Flush the TLB for the requested page table.
335  */
336 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
337 					uint32_t vmhub, uint32_t flush_type)
338 {
339 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
340 	struct dma_fence *fence;
341 	struct amdgpu_job *job;
342 
343 	int r;
344 
345 	/* flush hdp cache */
346 	adev->nbio.funcs->hdp_flush(adev, NULL);
347 
348 	mutex_lock(&adev->mman.gtt_window_lock);
349 
350 	if (vmhub == AMDGPU_MMHUB_0) {
351 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
352 		mutex_unlock(&adev->mman.gtt_window_lock);
353 		return;
354 	}
355 
356 	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
357 
358 	if (!adev->mman.buffer_funcs_enabled ||
359 	    !adev->ib_pool_ready ||
360 	    adev->in_gpu_reset ||
361 	    ring->sched.ready == false) {
362 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
363 		mutex_unlock(&adev->mman.gtt_window_lock);
364 		return;
365 	}
366 
367 	/* The SDMA on Navi has a bug which can theoretically result in memory
368 	 * corruption if an invalidation happens at the same time as an VA
369 	 * translation. Avoid this by doing the invalidation from the SDMA
370 	 * itself.
371 	 */
372 	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job);
373 	if (r)
374 		goto error_alloc;
375 
376 	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
377 	job->vm_needs_flush = true;
378 	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
379 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
380 	r = amdgpu_job_submit(job, &adev->mman.entity,
381 			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
382 	if (r)
383 		goto error_submit;
384 
385 	mutex_unlock(&adev->mman.gtt_window_lock);
386 
387 	dma_fence_wait(fence, false);
388 	dma_fence_put(fence);
389 
390 	return;
391 
392 error_submit:
393 	amdgpu_job_free(job);
394 
395 error_alloc:
396 	mutex_unlock(&adev->mman.gtt_window_lock);
397 	DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
398 }
399 
400 /**
401  * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
402  *
403  * @adev: amdgpu_device pointer
404  * @pasid: pasid to be flush
405  *
406  * Flush the TLB for the requested pasid.
407  */
408 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
409 					uint16_t pasid, uint32_t flush_type,
410 					bool all_hub)
411 {
412 	int vmid, i;
413 	signed long r;
414 	uint32_t seq;
415 	uint16_t queried_pasid;
416 	bool ret;
417 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
418 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
419 
420 	if (amdgpu_emu_mode == 0 && ring->sched.ready) {
421 		spin_lock(&adev->gfx.kiq.ring_lock);
422 		/* 2 dwords flush + 8 dwords fence */
423 		amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
424 		kiq->pmf->kiq_invalidate_tlbs(ring,
425 					pasid, flush_type, all_hub);
426 		amdgpu_fence_emit_polling(ring, &seq);
427 		amdgpu_ring_commit(ring);
428 		spin_unlock(&adev->gfx.kiq.ring_lock);
429 		r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
430 		if (r < 1) {
431 			DRM_ERROR("wait for kiq fence error: %ld.\n", r);
432 			return -ETIME;
433 		}
434 
435 		return 0;
436 	}
437 
438 	for (vmid = 1; vmid < 16; vmid++) {
439 
440 		ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
441 				&queried_pasid);
442 		if (ret	&& queried_pasid == pasid) {
443 			if (all_hub) {
444 				for (i = 0; i < adev->num_vmhubs; i++)
445 					gmc_v10_0_flush_gpu_tlb(adev, vmid,
446 							i, flush_type);
447 			} else {
448 				gmc_v10_0_flush_gpu_tlb(adev, vmid,
449 						AMDGPU_GFXHUB_0, flush_type);
450 			}
451 			break;
452 		}
453 	}
454 
455 	return 0;
456 }
457 
458 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
459 					     unsigned vmid, uint64_t pd_addr)
460 {
461 	bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
462 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
463 	uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
464 	unsigned eng = ring->vm_inv_eng;
465 
466 	/*
467 	 * It may lose gpuvm invalidate acknowldege state across power-gating
468 	 * off cycle, add semaphore acquire before invalidation and semaphore
469 	 * release after invalidation to avoid entering power gated state
470 	 * to WA the Issue
471 	 */
472 
473 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
474 	if (use_semaphore)
475 		/* a read return value of 1 means semaphore acuqire */
476 		amdgpu_ring_emit_reg_wait(ring,
477 					  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
478 
479 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
480 			      lower_32_bits(pd_addr));
481 
482 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
483 			      upper_32_bits(pd_addr));
484 
485 	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
486 					    hub->vm_inv_eng0_ack + eng,
487 					    req, 1 << vmid);
488 
489 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
490 	if (use_semaphore)
491 		/*
492 		 * add semaphore release after invalidation,
493 		 * write with 0 means semaphore release
494 		 */
495 		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
496 
497 	return pd_addr;
498 }
499 
500 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
501 					 unsigned pasid)
502 {
503 	struct amdgpu_device *adev = ring->adev;
504 	uint32_t reg;
505 
506 	if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
507 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
508 	else
509 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
510 
511 	amdgpu_ring_emit_wreg(ring, reg, pasid);
512 }
513 
514 /*
515  * PTE format on NAVI 10:
516  * 63:59 reserved
517  * 58:57 reserved
518  * 56 F
519  * 55 L
520  * 54 reserved
521  * 53:52 SW
522  * 51 T
523  * 50:48 mtype
524  * 47:12 4k physical page base address
525  * 11:7 fragment
526  * 6 write
527  * 5 read
528  * 4 exe
529  * 3 Z
530  * 2 snooped
531  * 1 system
532  * 0 valid
533  *
534  * PDE format on NAVI 10:
535  * 63:59 block fragment size
536  * 58:55 reserved
537  * 54 P
538  * 53:48 reserved
539  * 47:6 physical base address of PD or PTE
540  * 5:3 reserved
541  * 2 C
542  * 1 system
543  * 0 valid
544  */
545 
546 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
547 {
548 	switch (flags) {
549 	case AMDGPU_VM_MTYPE_DEFAULT:
550 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
551 	case AMDGPU_VM_MTYPE_NC:
552 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
553 	case AMDGPU_VM_MTYPE_WC:
554 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
555 	case AMDGPU_VM_MTYPE_CC:
556 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
557 	case AMDGPU_VM_MTYPE_UC:
558 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
559 	default:
560 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
561 	}
562 }
563 
564 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
565 				 uint64_t *addr, uint64_t *flags)
566 {
567 	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
568 		*addr = adev->vm_manager.vram_base_offset + *addr -
569 			adev->gmc.vram_start;
570 	BUG_ON(*addr & 0xFFFF00000000003FULL);
571 
572 	if (!adev->gmc.translate_further)
573 		return;
574 
575 	if (level == AMDGPU_VM_PDB1) {
576 		/* Set the block fragment size */
577 		if (!(*flags & AMDGPU_PDE_PTE))
578 			*flags |= AMDGPU_PDE_BFS(0x9);
579 
580 	} else if (level == AMDGPU_VM_PDB0) {
581 		if (*flags & AMDGPU_PDE_PTE)
582 			*flags &= ~AMDGPU_PDE_PTE;
583 		else
584 			*flags |= AMDGPU_PTE_TF;
585 	}
586 }
587 
588 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
589 				 struct amdgpu_bo_va_mapping *mapping,
590 				 uint64_t *flags)
591 {
592 	*flags &= ~AMDGPU_PTE_EXECUTABLE;
593 	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
594 
595 	*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
596 	*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
597 
598 	if (mapping->flags & AMDGPU_PTE_PRT) {
599 		*flags |= AMDGPU_PTE_PRT;
600 		*flags |= AMDGPU_PTE_SNOOPED;
601 		*flags |= AMDGPU_PTE_LOG;
602 		*flags |= AMDGPU_PTE_SYSTEM;
603 		*flags &= ~AMDGPU_PTE_VALID;
604 	}
605 }
606 
607 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
608 	.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
609 	.flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
610 	.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
611 	.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
612 	.map_mtype = gmc_v10_0_map_mtype,
613 	.get_vm_pde = gmc_v10_0_get_vm_pde,
614 	.get_vm_pte = gmc_v10_0_get_vm_pte
615 };
616 
617 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
618 {
619 	if (adev->gmc.gmc_funcs == NULL)
620 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
621 }
622 
623 static int gmc_v10_0_early_init(void *handle)
624 {
625 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626 
627 	gmc_v10_0_set_gmc_funcs(adev);
628 	gmc_v10_0_set_irq_funcs(adev);
629 
630 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
631 	adev->gmc.shared_aperture_end =
632 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
633 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
634 	adev->gmc.private_aperture_end =
635 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
636 
637 	return 0;
638 }
639 
640 static int gmc_v10_0_late_init(void *handle)
641 {
642 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
643 	int r;
644 
645 	amdgpu_bo_late_init(adev);
646 
647 	r = amdgpu_gmc_allocate_vm_inv_eng(adev);
648 	if (r)
649 		return r;
650 
651 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
652 }
653 
654 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
655 					struct amdgpu_gmc *mc)
656 {
657 	u64 base = 0;
658 
659 	base = gfxhub_v2_0_get_fb_location(adev);
660 
661 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
662 	amdgpu_gmc_gart_location(adev, mc);
663 
664 	/* base offset of vram pages */
665 	adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
666 }
667 
668 /**
669  * gmc_v10_0_mc_init - initialize the memory controller driver params
670  *
671  * @adev: amdgpu_device pointer
672  *
673  * Look up the amount of vram, vram width, and decide how to place
674  * vram and gart within the GPU's physical address space.
675  * Returns 0 for success.
676  */
677 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
678 {
679 	/* Could aper size report 0 ? */
680 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
681 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
682 
683 	/* size in MB on si */
684 	adev->gmc.mc_vram_size =
685 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
686 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
687 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
688 
689 	/* In case the PCI BAR is larger than the actual amount of vram */
690 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
691 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
692 
693 	/* set the gart size */
694 	if (amdgpu_gart_size == -1) {
695 		switch (adev->asic_type) {
696 		case CHIP_NAVI10:
697 		case CHIP_NAVI14:
698 		case CHIP_NAVI12:
699 		default:
700 			adev->gmc.gart_size = 512ULL << 20;
701 			break;
702 		}
703 	} else
704 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
705 
706 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
707 
708 	return 0;
709 }
710 
711 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
712 {
713 	int r;
714 
715 	if (adev->gart.bo) {
716 		WARN(1, "NAVI10 PCIE GART already initialized\n");
717 		return 0;
718 	}
719 
720 	/* Initialize common gart structure */
721 	r = amdgpu_gart_init(adev);
722 	if (r)
723 		return r;
724 
725 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
726 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
727 				 AMDGPU_PTE_EXECUTABLE;
728 
729 	return amdgpu_gart_table_vram_alloc(adev);
730 }
731 
732 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
733 {
734 	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
735 	unsigned size;
736 
737 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
738 		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
739 	} else {
740 		u32 viewport;
741 		u32 pitch;
742 
743 		viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
744 		pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
745 		size = (REG_GET_FIELD(viewport,
746 					HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
747 				REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
748 				4);
749 	}
750 	/* return 0 if the pre-OS buffer uses up most of vram */
751 	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
752 		DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
753 				be aware of gart table overwrite\n");
754 		return 0;
755 	}
756 
757 	return size;
758 }
759 
760 
761 
762 static int gmc_v10_0_sw_init(void *handle)
763 {
764 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
765 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
766 
767 	gfxhub_v2_0_init(adev);
768 	mmhub_v2_0_init(adev);
769 
770 	spin_lock_init(&adev->gmc.invalidate_lock);
771 
772 	r = amdgpu_atomfirmware_get_vram_info(adev,
773 		&vram_width, &vram_type, &vram_vendor);
774 	if (!amdgpu_emu_mode)
775 		adev->gmc.vram_width = vram_width;
776 	else
777 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
778 
779 	adev->gmc.vram_type = vram_type;
780 	adev->gmc.vram_vendor = vram_vendor;
781 	switch (adev->asic_type) {
782 	case CHIP_NAVI10:
783 	case CHIP_NAVI14:
784 	case CHIP_NAVI12:
785 		adev->num_vmhubs = 2;
786 		/*
787 		 * To fulfill 4-level page support,
788 		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
789 		 * block size 512 (9bit)
790 		 */
791 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
792 		break;
793 	default:
794 		break;
795 	}
796 
797 	/* This interrupt is VMC page fault.*/
798 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
799 			      VMC_1_0__SRCID__VM_FAULT,
800 			      &adev->gmc.vm_fault);
801 
802 	if (r)
803 		return r;
804 
805 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
806 			      UTCL2_1_0__SRCID__FAULT,
807 			      &adev->gmc.vm_fault);
808 	if (r)
809 		return r;
810 
811 	/*
812 	 * Set the internal MC address mask This is the max address of the GPU's
813 	 * internal address space.
814 	 */
815 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
816 
817 	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
818 	if (r) {
819 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
820 		return r;
821 	}
822 
823 	r = gmc_v10_0_mc_init(adev);
824 	if (r)
825 		return r;
826 
827 	adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
828 
829 	/* Memory manager */
830 	r = amdgpu_bo_init(adev);
831 	if (r)
832 		return r;
833 
834 	r = gmc_v10_0_gart_init(adev);
835 	if (r)
836 		return r;
837 
838 	/*
839 	 * number of VMs
840 	 * VMID 0 is reserved for System
841 	 * amdgpu graphics/compute will use VMIDs 1-7
842 	 * amdkfd will use VMIDs 8-15
843 	 */
844 	adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
845 	adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
846 
847 	amdgpu_vm_manager_init(adev);
848 
849 	return 0;
850 }
851 
852 /**
853  * gmc_v8_0_gart_fini - vm fini callback
854  *
855  * @adev: amdgpu_device pointer
856  *
857  * Tears down the driver GART/VM setup (CIK).
858  */
859 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
860 {
861 	amdgpu_gart_table_vram_free(adev);
862 	amdgpu_gart_fini(adev);
863 }
864 
865 static int gmc_v10_0_sw_fini(void *handle)
866 {
867 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
868 
869 	amdgpu_vm_manager_fini(adev);
870 	gmc_v10_0_gart_fini(adev);
871 	amdgpu_gem_force_release(adev);
872 	amdgpu_bo_fini(adev);
873 
874 	return 0;
875 }
876 
877 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
878 {
879 	switch (adev->asic_type) {
880 	case CHIP_NAVI10:
881 	case CHIP_NAVI14:
882 	case CHIP_NAVI12:
883 		break;
884 	default:
885 		break;
886 	}
887 }
888 
889 /**
890  * gmc_v10_0_gart_enable - gart enable
891  *
892  * @adev: amdgpu_device pointer
893  */
894 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
895 {
896 	int r;
897 	bool value;
898 	u32 tmp;
899 
900 	if (adev->gart.bo == NULL) {
901 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
902 		return -EINVAL;
903 	}
904 
905 	r = amdgpu_gart_table_vram_pin(adev);
906 	if (r)
907 		return r;
908 
909 	r = gfxhub_v2_0_gart_enable(adev);
910 	if (r)
911 		return r;
912 
913 	r = mmhub_v2_0_gart_enable(adev);
914 	if (r)
915 		return r;
916 
917 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
918 	tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
919 	WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
920 
921 	tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
922 	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
923 
924 	/* Flush HDP after it is initialized */
925 	adev->nbio.funcs->hdp_flush(adev, NULL);
926 
927 	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
928 		false : true;
929 
930 	gfxhub_v2_0_set_fault_enable_default(adev, value);
931 	mmhub_v2_0_set_fault_enable_default(adev, value);
932 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
933 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
934 
935 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
936 		 (unsigned)(adev->gmc.gart_size >> 20),
937 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
938 
939 	adev->gart.ready = true;
940 
941 	return 0;
942 }
943 
944 static int gmc_v10_0_hw_init(void *handle)
945 {
946 	int r;
947 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
948 
949 	/* The sequence of these two function calls matters.*/
950 	gmc_v10_0_init_golden_registers(adev);
951 
952 	r = gmc_v10_0_gart_enable(adev);
953 	if (r)
954 		return r;
955 
956 	return 0;
957 }
958 
959 /**
960  * gmc_v10_0_gart_disable - gart disable
961  *
962  * @adev: amdgpu_device pointer
963  *
964  * This disables all VM page table.
965  */
966 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
967 {
968 	gfxhub_v2_0_gart_disable(adev);
969 	mmhub_v2_0_gart_disable(adev);
970 	amdgpu_gart_table_vram_unpin(adev);
971 }
972 
973 static int gmc_v10_0_hw_fini(void *handle)
974 {
975 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
976 
977 	if (amdgpu_sriov_vf(adev)) {
978 		/* full access mode, so don't touch any GMC register */
979 		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
980 		return 0;
981 	}
982 
983 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
984 	gmc_v10_0_gart_disable(adev);
985 
986 	return 0;
987 }
988 
989 static int gmc_v10_0_suspend(void *handle)
990 {
991 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
992 
993 	gmc_v10_0_hw_fini(adev);
994 
995 	return 0;
996 }
997 
998 static int gmc_v10_0_resume(void *handle)
999 {
1000 	int r;
1001 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 
1003 	r = gmc_v10_0_hw_init(adev);
1004 	if (r)
1005 		return r;
1006 
1007 	amdgpu_vmid_reset_all(adev);
1008 
1009 	return 0;
1010 }
1011 
1012 static bool gmc_v10_0_is_idle(void *handle)
1013 {
1014 	/* MC is always ready in GMC v10.*/
1015 	return true;
1016 }
1017 
1018 static int gmc_v10_0_wait_for_idle(void *handle)
1019 {
1020 	/* There is no need to wait for MC idle in GMC v10.*/
1021 	return 0;
1022 }
1023 
1024 static int gmc_v10_0_soft_reset(void *handle)
1025 {
1026 	return 0;
1027 }
1028 
1029 static int gmc_v10_0_set_clockgating_state(void *handle,
1030 					   enum amd_clockgating_state state)
1031 {
1032 	int r;
1033 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034 
1035 	r = mmhub_v2_0_set_clockgating(adev, state);
1036 	if (r)
1037 		return r;
1038 
1039 	return athub_v2_0_set_clockgating(adev, state);
1040 }
1041 
1042 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1043 {
1044 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045 
1046 	mmhub_v2_0_get_clockgating(adev, flags);
1047 
1048 	athub_v2_0_get_clockgating(adev, flags);
1049 }
1050 
1051 static int gmc_v10_0_set_powergating_state(void *handle,
1052 					   enum amd_powergating_state state)
1053 {
1054 	return 0;
1055 }
1056 
1057 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1058 	.name = "gmc_v10_0",
1059 	.early_init = gmc_v10_0_early_init,
1060 	.late_init = gmc_v10_0_late_init,
1061 	.sw_init = gmc_v10_0_sw_init,
1062 	.sw_fini = gmc_v10_0_sw_fini,
1063 	.hw_init = gmc_v10_0_hw_init,
1064 	.hw_fini = gmc_v10_0_hw_fini,
1065 	.suspend = gmc_v10_0_suspend,
1066 	.resume = gmc_v10_0_resume,
1067 	.is_idle = gmc_v10_0_is_idle,
1068 	.wait_for_idle = gmc_v10_0_wait_for_idle,
1069 	.soft_reset = gmc_v10_0_soft_reset,
1070 	.set_clockgating_state = gmc_v10_0_set_clockgating_state,
1071 	.set_powergating_state = gmc_v10_0_set_powergating_state,
1072 	.get_clockgating_state = gmc_v10_0_get_clockgating_state,
1073 };
1074 
1075 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1076 {
1077 	.type = AMD_IP_BLOCK_TYPE_GMC,
1078 	.major = 10,
1079 	.minor = 0,
1080 	.rev = 0,
1081 	.funcs = &gmc_v10_0_ip_funcs,
1082 };
1083