1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 29 #include "hdp/hdp_5_0_0_offset.h" 30 #include "hdp/hdp_5_0_0_sh_mask.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "mmhub/mmhub_2_0_0_sh_mask.h" 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "athub_v2_0.h" 50 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/ 51 #define AMDGPU_NUM_OF_VMIDS 8 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int 61 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 62 struct amdgpu_irq_src *src, unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 struct amdgpu_vmhub *hub; 66 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; 67 68 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 69 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 70 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 71 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 72 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 73 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 74 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 75 76 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 77 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 78 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 80 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 81 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 82 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 83 84 switch (state) { 85 case AMDGPU_IRQ_STATE_DISABLE: 86 /* MM HUB */ 87 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 88 for (i = 0; i < 16; i++) { 89 reg = hub->vm_context0_cntl + i; 90 tmp = RREG32(reg); 91 tmp &= ~bits[AMDGPU_MMHUB_0]; 92 WREG32(reg, tmp); 93 } 94 95 /* GFX HUB */ 96 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 97 for (i = 0; i < 16; i++) { 98 reg = hub->vm_context0_cntl + i; 99 tmp = RREG32(reg); 100 tmp &= ~bits[AMDGPU_GFXHUB_0]; 101 WREG32(reg, tmp); 102 } 103 break; 104 case AMDGPU_IRQ_STATE_ENABLE: 105 /* MM HUB */ 106 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 107 for (i = 0; i < 16; i++) { 108 reg = hub->vm_context0_cntl + i; 109 tmp = RREG32(reg); 110 tmp |= bits[AMDGPU_MMHUB_0]; 111 WREG32(reg, tmp); 112 } 113 114 /* GFX HUB */ 115 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 116 for (i = 0; i < 16; i++) { 117 reg = hub->vm_context0_cntl + i; 118 tmp = RREG32(reg); 119 tmp |= bits[AMDGPU_GFXHUB_0]; 120 WREG32(reg, tmp); 121 } 122 break; 123 default: 124 break; 125 } 126 127 return 0; 128 } 129 130 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 131 struct amdgpu_irq_src *source, 132 struct amdgpu_iv_entry *entry) 133 { 134 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 135 uint32_t status = 0; 136 u64 addr; 137 138 addr = (u64)entry->src_data[0] << 12; 139 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 140 141 if (!amdgpu_sriov_vf(adev)) { 142 /* 143 * Issue a dummy read to wait for the status register to 144 * be updated to avoid reading an incorrect value due to 145 * the new fast GRBM interface. 146 */ 147 if (entry->vmid_src == AMDGPU_GFXHUB_0) 148 RREG32(hub->vm_l2_pro_fault_status); 149 150 status = RREG32(hub->vm_l2_pro_fault_status); 151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 152 } 153 154 if (printk_ratelimit()) { 155 struct amdgpu_task_info task_info; 156 157 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 158 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 159 160 dev_err(adev->dev, 161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 162 "for process %s pid %d thread %s pid %d)\n", 163 entry->vmid_src ? "mmhub" : "gfxhub", 164 entry->src_id, entry->ring_id, entry->vmid, 165 entry->pasid, task_info.process_name, task_info.tgid, 166 task_info.task_name, task_info.pid); 167 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 168 addr, entry->client_id); 169 if (!amdgpu_sriov_vf(adev)) { 170 dev_err(adev->dev, 171 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 172 status); 173 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 174 REG_GET_FIELD(status, 175 GCVM_L2_PROTECTION_FAULT_STATUS, CID)); 176 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 177 REG_GET_FIELD(status, 178 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 179 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 180 REG_GET_FIELD(status, 181 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 182 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 183 REG_GET_FIELD(status, 184 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 185 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 186 REG_GET_FIELD(status, 187 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 188 dev_err(adev->dev, "\t RW: 0x%lx\n", 189 REG_GET_FIELD(status, 190 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 191 } 192 } 193 194 return 0; 195 } 196 197 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 198 .set = gmc_v10_0_vm_fault_interrupt_state, 199 .process = gmc_v10_0_process_interrupt, 200 }; 201 202 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 203 { 204 adev->gmc.vm_fault.num_types = 1; 205 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 206 } 207 208 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, 209 uint32_t flush_type) 210 { 211 u32 req = 0; 212 213 /* invalidate using legacy mode on vmid*/ 214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 215 PER_VMID_INVALIDATE_REQ, 1 << vmid); 216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 217 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 218 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 219 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 220 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 221 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 222 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 223 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 224 225 return req; 226 } 227 228 /** 229 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 230 * 231 * @adev: amdgpu_device pointer 232 * @vmhub: vmhub type 233 * 234 */ 235 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 236 uint32_t vmhub) 237 { 238 return ((vmhub == AMDGPU_MMHUB_0 || 239 vmhub == AMDGPU_MMHUB_1) && 240 (!amdgpu_sriov_vf(adev))); 241 } 242 243 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 244 struct amdgpu_device *adev, 245 uint8_t vmid, uint16_t *p_pasid) 246 { 247 uint32_t value; 248 249 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 250 + vmid); 251 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 252 253 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 254 } 255 256 /* 257 * GART 258 * VMID 0 is the physical GPU addresses as used by the kernel. 259 * VMIDs 1-15 are used for userspace clients and are handled 260 * by the amdgpu vm/hsa code. 261 */ 262 263 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 264 unsigned int vmhub, uint32_t flush_type) 265 { 266 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 267 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 268 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type); 269 u32 tmp; 270 /* Use register 17 for GART */ 271 const unsigned eng = 17; 272 unsigned int i; 273 274 spin_lock(&adev->gmc.invalidate_lock); 275 /* 276 * It may lose gpuvm invalidate acknowldege state across power-gating 277 * off cycle, add semaphore acquire before invalidation and semaphore 278 * release after invalidation to avoid entering power gated state 279 * to WA the Issue 280 */ 281 282 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 283 if (use_semaphore) { 284 for (i = 0; i < adev->usec_timeout; i++) { 285 /* a read return value of 1 means semaphore acuqire */ 286 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); 287 if (tmp & 0x1) 288 break; 289 udelay(1); 290 } 291 292 if (i >= adev->usec_timeout) 293 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 294 } 295 296 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req); 297 298 /* 299 * Issue a dummy read to wait for the ACK register to be cleared 300 * to avoid a false ACK due to the new fast GRBM interface. 301 */ 302 if (vmhub == AMDGPU_GFXHUB_0) 303 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 304 305 /* Wait for ACK with a delay.*/ 306 for (i = 0; i < adev->usec_timeout; i++) { 307 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 308 tmp &= 1 << vmid; 309 if (tmp) 310 break; 311 312 udelay(1); 313 } 314 315 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 316 if (use_semaphore) 317 /* 318 * add semaphore release after invalidation, 319 * write with 0 means semaphore release 320 */ 321 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0); 322 323 spin_unlock(&adev->gmc.invalidate_lock); 324 325 if (i < adev->usec_timeout) 326 return; 327 328 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 329 } 330 331 /** 332 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 333 * 334 * @adev: amdgpu_device pointer 335 * @vmid: vm instance to flush 336 * 337 * Flush the TLB for the requested page table. 338 */ 339 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 340 uint32_t vmhub, uint32_t flush_type) 341 { 342 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 343 struct dma_fence *fence; 344 struct amdgpu_job *job; 345 346 int r; 347 348 /* flush hdp cache */ 349 adev->nbio.funcs->hdp_flush(adev, NULL); 350 351 mutex_lock(&adev->mman.gtt_window_lock); 352 353 if (vmhub == AMDGPU_MMHUB_0) { 354 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 355 mutex_unlock(&adev->mman.gtt_window_lock); 356 return; 357 } 358 359 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 360 361 if (!adev->mman.buffer_funcs_enabled || 362 !adev->ib_pool_ready || 363 adev->in_gpu_reset || 364 ring->sched.ready == false) { 365 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 366 mutex_unlock(&adev->mman.gtt_window_lock); 367 return; 368 } 369 370 /* The SDMA on Navi has a bug which can theoretically result in memory 371 * corruption if an invalidation happens at the same time as an VA 372 * translation. Avoid this by doing the invalidation from the SDMA 373 * itself. 374 */ 375 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_VM, &job); 376 if (r) 377 goto error_alloc; 378 379 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 380 job->vm_needs_flush = true; 381 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 382 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 383 r = amdgpu_job_submit(job, &adev->mman.entity, 384 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 385 if (r) 386 goto error_submit; 387 388 mutex_unlock(&adev->mman.gtt_window_lock); 389 390 dma_fence_wait(fence, false); 391 dma_fence_put(fence); 392 393 return; 394 395 error_submit: 396 amdgpu_job_free(job); 397 398 error_alloc: 399 mutex_unlock(&adev->mman.gtt_window_lock); 400 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 401 } 402 403 /** 404 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 405 * 406 * @adev: amdgpu_device pointer 407 * @pasid: pasid to be flush 408 * 409 * Flush the TLB for the requested pasid. 410 */ 411 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 412 uint16_t pasid, uint32_t flush_type, 413 bool all_hub) 414 { 415 int vmid, i; 416 signed long r; 417 uint32_t seq; 418 uint16_t queried_pasid; 419 bool ret; 420 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 421 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 422 423 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 424 spin_lock(&adev->gfx.kiq.ring_lock); 425 /* 2 dwords flush + 8 dwords fence */ 426 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 427 kiq->pmf->kiq_invalidate_tlbs(ring, 428 pasid, flush_type, all_hub); 429 amdgpu_fence_emit_polling(ring, &seq); 430 amdgpu_ring_commit(ring); 431 spin_unlock(&adev->gfx.kiq.ring_lock); 432 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 433 if (r < 1) { 434 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 435 return -ETIME; 436 } 437 438 return 0; 439 } 440 441 for (vmid = 1; vmid < 16; vmid++) { 442 443 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 444 &queried_pasid); 445 if (ret && queried_pasid == pasid) { 446 if (all_hub) { 447 for (i = 0; i < adev->num_vmhubs; i++) 448 gmc_v10_0_flush_gpu_tlb(adev, vmid, 449 i, flush_type); 450 } else { 451 gmc_v10_0_flush_gpu_tlb(adev, vmid, 452 AMDGPU_GFXHUB_0, flush_type); 453 } 454 break; 455 } 456 } 457 458 return 0; 459 } 460 461 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 462 unsigned vmid, uint64_t pd_addr) 463 { 464 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 465 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 466 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); 467 unsigned eng = ring->vm_inv_eng; 468 469 /* 470 * It may lose gpuvm invalidate acknowldege state across power-gating 471 * off cycle, add semaphore acquire before invalidation and semaphore 472 * release after invalidation to avoid entering power gated state 473 * to WA the Issue 474 */ 475 476 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 477 if (use_semaphore) 478 /* a read return value of 1 means semaphore acuqire */ 479 amdgpu_ring_emit_reg_wait(ring, 480 hub->vm_inv_eng0_sem + eng, 0x1, 0x1); 481 482 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 483 lower_32_bits(pd_addr)); 484 485 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 486 upper_32_bits(pd_addr)); 487 488 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 489 hub->vm_inv_eng0_ack + eng, 490 req, 1 << vmid); 491 492 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 493 if (use_semaphore) 494 /* 495 * add semaphore release after invalidation, 496 * write with 0 means semaphore release 497 */ 498 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); 499 500 return pd_addr; 501 } 502 503 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 504 unsigned pasid) 505 { 506 struct amdgpu_device *adev = ring->adev; 507 uint32_t reg; 508 509 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 510 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 511 else 512 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 513 514 amdgpu_ring_emit_wreg(ring, reg, pasid); 515 } 516 517 /* 518 * PTE format on NAVI 10: 519 * 63:59 reserved 520 * 58:57 reserved 521 * 56 F 522 * 55 L 523 * 54 reserved 524 * 53:52 SW 525 * 51 T 526 * 50:48 mtype 527 * 47:12 4k physical page base address 528 * 11:7 fragment 529 * 6 write 530 * 5 read 531 * 4 exe 532 * 3 Z 533 * 2 snooped 534 * 1 system 535 * 0 valid 536 * 537 * PDE format on NAVI 10: 538 * 63:59 block fragment size 539 * 58:55 reserved 540 * 54 P 541 * 53:48 reserved 542 * 47:6 physical base address of PD or PTE 543 * 5:3 reserved 544 * 2 C 545 * 1 system 546 * 0 valid 547 */ 548 549 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 550 { 551 switch (flags) { 552 case AMDGPU_VM_MTYPE_DEFAULT: 553 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 554 case AMDGPU_VM_MTYPE_NC: 555 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 556 case AMDGPU_VM_MTYPE_WC: 557 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 558 case AMDGPU_VM_MTYPE_CC: 559 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 560 case AMDGPU_VM_MTYPE_UC: 561 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 562 default: 563 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 564 } 565 } 566 567 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 568 uint64_t *addr, uint64_t *flags) 569 { 570 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 571 *addr = adev->vm_manager.vram_base_offset + *addr - 572 adev->gmc.vram_start; 573 BUG_ON(*addr & 0xFFFF00000000003FULL); 574 575 if (!adev->gmc.translate_further) 576 return; 577 578 if (level == AMDGPU_VM_PDB1) { 579 /* Set the block fragment size */ 580 if (!(*flags & AMDGPU_PDE_PTE)) 581 *flags |= AMDGPU_PDE_BFS(0x9); 582 583 } else if (level == AMDGPU_VM_PDB0) { 584 if (*flags & AMDGPU_PDE_PTE) 585 *flags &= ~AMDGPU_PDE_PTE; 586 else 587 *flags |= AMDGPU_PTE_TF; 588 } 589 } 590 591 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 592 struct amdgpu_bo_va_mapping *mapping, 593 uint64_t *flags) 594 { 595 *flags &= ~AMDGPU_PTE_EXECUTABLE; 596 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 597 598 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 599 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 600 601 if (mapping->flags & AMDGPU_PTE_PRT) { 602 *flags |= AMDGPU_PTE_PRT; 603 *flags |= AMDGPU_PTE_SNOOPED; 604 *flags |= AMDGPU_PTE_LOG; 605 *flags |= AMDGPU_PTE_SYSTEM; 606 *flags &= ~AMDGPU_PTE_VALID; 607 } 608 } 609 610 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 611 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 612 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 613 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 614 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 615 .map_mtype = gmc_v10_0_map_mtype, 616 .get_vm_pde = gmc_v10_0_get_vm_pde, 617 .get_vm_pte = gmc_v10_0_get_vm_pte 618 }; 619 620 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 621 { 622 if (adev->gmc.gmc_funcs == NULL) 623 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 624 } 625 626 static int gmc_v10_0_early_init(void *handle) 627 { 628 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 629 630 gmc_v10_0_set_gmc_funcs(adev); 631 gmc_v10_0_set_irq_funcs(adev); 632 633 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 634 adev->gmc.shared_aperture_end = 635 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 636 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 637 adev->gmc.private_aperture_end = 638 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 639 640 return 0; 641 } 642 643 static int gmc_v10_0_late_init(void *handle) 644 { 645 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 646 int r; 647 648 amdgpu_bo_late_init(adev); 649 650 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 651 if (r) 652 return r; 653 654 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 655 } 656 657 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 658 struct amdgpu_gmc *mc) 659 { 660 u64 base = 0; 661 662 base = gfxhub_v2_0_get_fb_location(adev); 663 664 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 665 amdgpu_gmc_gart_location(adev, mc); 666 667 /* base offset of vram pages */ 668 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); 669 } 670 671 /** 672 * gmc_v10_0_mc_init - initialize the memory controller driver params 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * Look up the amount of vram, vram width, and decide how to place 677 * vram and gart within the GPU's physical address space. 678 * Returns 0 for success. 679 */ 680 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 681 { 682 /* Could aper size report 0 ? */ 683 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 684 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 685 686 /* size in MB on si */ 687 adev->gmc.mc_vram_size = 688 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 689 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 690 adev->gmc.visible_vram_size = adev->gmc.aper_size; 691 692 /* In case the PCI BAR is larger than the actual amount of vram */ 693 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 694 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 695 696 /* set the gart size */ 697 if (amdgpu_gart_size == -1) { 698 switch (adev->asic_type) { 699 case CHIP_NAVI10: 700 case CHIP_NAVI14: 701 case CHIP_NAVI12: 702 default: 703 adev->gmc.gart_size = 512ULL << 20; 704 break; 705 } 706 } else 707 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 708 709 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 710 711 return 0; 712 } 713 714 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 715 { 716 int r; 717 718 if (adev->gart.bo) { 719 WARN(1, "NAVI10 PCIE GART already initialized\n"); 720 return 0; 721 } 722 723 /* Initialize common gart structure */ 724 r = amdgpu_gart_init(adev); 725 if (r) 726 return r; 727 728 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 729 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 730 AMDGPU_PTE_EXECUTABLE; 731 732 return amdgpu_gart_table_vram_alloc(adev); 733 } 734 735 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 736 { 737 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 738 unsigned size; 739 740 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 741 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 742 } else { 743 u32 viewport; 744 u32 pitch; 745 746 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 747 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 748 size = (REG_GET_FIELD(viewport, 749 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 750 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 751 4); 752 } 753 /* return 0 if the pre-OS buffer uses up most of vram */ 754 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { 755 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \ 756 be aware of gart table overwrite\n"); 757 return 0; 758 } 759 760 return size; 761 } 762 763 764 765 static int gmc_v10_0_sw_init(void *handle) 766 { 767 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 769 770 gfxhub_v2_0_init(adev); 771 mmhub_v2_0_init(adev); 772 773 spin_lock_init(&adev->gmc.invalidate_lock); 774 775 r = amdgpu_atomfirmware_get_vram_info(adev, 776 &vram_width, &vram_type, &vram_vendor); 777 if (!amdgpu_emu_mode) 778 adev->gmc.vram_width = vram_width; 779 else 780 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 781 782 adev->gmc.vram_type = vram_type; 783 adev->gmc.vram_vendor = vram_vendor; 784 switch (adev->asic_type) { 785 case CHIP_NAVI10: 786 case CHIP_NAVI14: 787 case CHIP_NAVI12: 788 adev->num_vmhubs = 2; 789 /* 790 * To fulfill 4-level page support, 791 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 792 * block size 512 (9bit) 793 */ 794 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 795 break; 796 default: 797 break; 798 } 799 800 /* This interrupt is VMC page fault.*/ 801 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 802 VMC_1_0__SRCID__VM_FAULT, 803 &adev->gmc.vm_fault); 804 805 if (r) 806 return r; 807 808 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 809 UTCL2_1_0__SRCID__FAULT, 810 &adev->gmc.vm_fault); 811 if (r) 812 return r; 813 814 /* 815 * Set the internal MC address mask This is the max address of the GPU's 816 * internal address space. 817 */ 818 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 819 820 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 821 if (r) { 822 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 823 return r; 824 } 825 826 r = gmc_v10_0_mc_init(adev); 827 if (r) 828 return r; 829 830 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); 831 832 /* Memory manager */ 833 r = amdgpu_bo_init(adev); 834 if (r) 835 return r; 836 837 r = gmc_v10_0_gart_init(adev); 838 if (r) 839 return r; 840 841 /* 842 * number of VMs 843 * VMID 0 is reserved for System 844 * amdgpu graphics/compute will use VMIDs 1-7 845 * amdkfd will use VMIDs 8-15 846 */ 847 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 848 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 849 850 amdgpu_vm_manager_init(adev); 851 852 return 0; 853 } 854 855 /** 856 * gmc_v8_0_gart_fini - vm fini callback 857 * 858 * @adev: amdgpu_device pointer 859 * 860 * Tears down the driver GART/VM setup (CIK). 861 */ 862 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 863 { 864 amdgpu_gart_table_vram_free(adev); 865 amdgpu_gart_fini(adev); 866 } 867 868 static int gmc_v10_0_sw_fini(void *handle) 869 { 870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 871 872 amdgpu_vm_manager_fini(adev); 873 gmc_v10_0_gart_fini(adev); 874 amdgpu_gem_force_release(adev); 875 amdgpu_bo_fini(adev); 876 877 return 0; 878 } 879 880 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 881 { 882 switch (adev->asic_type) { 883 case CHIP_NAVI10: 884 case CHIP_NAVI14: 885 case CHIP_NAVI12: 886 break; 887 default: 888 break; 889 } 890 } 891 892 /** 893 * gmc_v10_0_gart_enable - gart enable 894 * 895 * @adev: amdgpu_device pointer 896 */ 897 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 898 { 899 int r; 900 bool value; 901 u32 tmp; 902 903 if (adev->gart.bo == NULL) { 904 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 905 return -EINVAL; 906 } 907 908 r = amdgpu_gart_table_vram_pin(adev); 909 if (r) 910 return r; 911 912 r = gfxhub_v2_0_gart_enable(adev); 913 if (r) 914 return r; 915 916 r = mmhub_v2_0_gart_enable(adev); 917 if (r) 918 return r; 919 920 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 921 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 922 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 923 924 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 925 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 926 927 /* Flush HDP after it is initialized */ 928 adev->nbio.funcs->hdp_flush(adev, NULL); 929 930 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 931 false : true; 932 933 gfxhub_v2_0_set_fault_enable_default(adev, value); 934 mmhub_v2_0_set_fault_enable_default(adev, value); 935 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 936 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 937 938 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 939 (unsigned)(adev->gmc.gart_size >> 20), 940 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 941 942 adev->gart.ready = true; 943 944 return 0; 945 } 946 947 static int gmc_v10_0_hw_init(void *handle) 948 { 949 int r; 950 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 951 952 /* The sequence of these two function calls matters.*/ 953 gmc_v10_0_init_golden_registers(adev); 954 955 r = gmc_v10_0_gart_enable(adev); 956 if (r) 957 return r; 958 959 return 0; 960 } 961 962 /** 963 * gmc_v10_0_gart_disable - gart disable 964 * 965 * @adev: amdgpu_device pointer 966 * 967 * This disables all VM page table. 968 */ 969 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 970 { 971 gfxhub_v2_0_gart_disable(adev); 972 mmhub_v2_0_gart_disable(adev); 973 amdgpu_gart_table_vram_unpin(adev); 974 } 975 976 static int gmc_v10_0_hw_fini(void *handle) 977 { 978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 979 980 if (amdgpu_sriov_vf(adev)) { 981 /* full access mode, so don't touch any GMC register */ 982 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 983 return 0; 984 } 985 986 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 987 gmc_v10_0_gart_disable(adev); 988 989 return 0; 990 } 991 992 static int gmc_v10_0_suspend(void *handle) 993 { 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995 996 gmc_v10_0_hw_fini(adev); 997 998 return 0; 999 } 1000 1001 static int gmc_v10_0_resume(void *handle) 1002 { 1003 int r; 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005 1006 r = gmc_v10_0_hw_init(adev); 1007 if (r) 1008 return r; 1009 1010 amdgpu_vmid_reset_all(adev); 1011 1012 return 0; 1013 } 1014 1015 static bool gmc_v10_0_is_idle(void *handle) 1016 { 1017 /* MC is always ready in GMC v10.*/ 1018 return true; 1019 } 1020 1021 static int gmc_v10_0_wait_for_idle(void *handle) 1022 { 1023 /* There is no need to wait for MC idle in GMC v10.*/ 1024 return 0; 1025 } 1026 1027 static int gmc_v10_0_soft_reset(void *handle) 1028 { 1029 return 0; 1030 } 1031 1032 static int gmc_v10_0_set_clockgating_state(void *handle, 1033 enum amd_clockgating_state state) 1034 { 1035 int r; 1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1037 1038 r = mmhub_v2_0_set_clockgating(adev, state); 1039 if (r) 1040 return r; 1041 1042 return athub_v2_0_set_clockgating(adev, state); 1043 } 1044 1045 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1046 { 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1048 1049 mmhub_v2_0_get_clockgating(adev, flags); 1050 1051 athub_v2_0_get_clockgating(adev, flags); 1052 } 1053 1054 static int gmc_v10_0_set_powergating_state(void *handle, 1055 enum amd_powergating_state state) 1056 { 1057 return 0; 1058 } 1059 1060 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1061 .name = "gmc_v10_0", 1062 .early_init = gmc_v10_0_early_init, 1063 .late_init = gmc_v10_0_late_init, 1064 .sw_init = gmc_v10_0_sw_init, 1065 .sw_fini = gmc_v10_0_sw_fini, 1066 .hw_init = gmc_v10_0_hw_init, 1067 .hw_fini = gmc_v10_0_hw_fini, 1068 .suspend = gmc_v10_0_suspend, 1069 .resume = gmc_v10_0_resume, 1070 .is_idle = gmc_v10_0_is_idle, 1071 .wait_for_idle = gmc_v10_0_wait_for_idle, 1072 .soft_reset = gmc_v10_0_soft_reset, 1073 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1074 .set_powergating_state = gmc_v10_0_set_powergating_state, 1075 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1076 }; 1077 1078 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1079 { 1080 .type = AMD_IP_BLOCK_TYPE_GMC, 1081 .major = 10, 1082 .minor = 0, 1083 .rev = 0, 1084 .funcs = &gmc_v10_0_ip_funcs, 1085 }; 1086