1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 #include "umc_v8_7.h" 29 30 #include "athub/athub_2_0_0_sh_mask.h" 31 #include "athub/athub_2_0_0_offset.h" 32 #include "dcn/dcn_2_0_0_offset.h" 33 #include "dcn/dcn_2_0_0_sh_mask.h" 34 #include "oss/osssys_5_0_0_offset.h" 35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 #include "navi10_enum.h" 37 38 #include "soc15.h" 39 #include "soc15d.h" 40 #include "soc15_common.h" 41 42 #include "nbio_v2_3.h" 43 44 #include "gfxhub_v2_0.h" 45 #include "gfxhub_v2_1.h" 46 #include "mmhub_v2_0.h" 47 #include "mmhub_v2_3.h" 48 #include "athub_v2_0.h" 49 #include "athub_v2_1.h" 50 51 #include "amdgpu_reset.h" 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 61 struct amdgpu_irq_src *src, 62 unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 return 0; 66 } 67 68 static int 69 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 70 struct amdgpu_irq_src *src, unsigned type, 71 enum amdgpu_interrupt_state state) 72 { 73 switch (state) { 74 case AMDGPU_IRQ_STATE_DISABLE: 75 /* MM HUB */ 76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 77 /* GFX HUB */ 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 83 /* GFX HUB */ 84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 85 break; 86 default: 87 break; 88 } 89 90 return 0; 91 } 92 93 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 94 struct amdgpu_irq_src *source, 95 struct amdgpu_iv_entry *entry) 96 { 97 bool retry_fault = !!(entry->src_data[1] & 0x80); 98 bool write_fault = !!(entry->src_data[1] & 0x20); 99 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 100 struct amdgpu_task_info task_info; 101 uint32_t status = 0; 102 u64 addr; 103 104 addr = (u64)entry->src_data[0] << 12; 105 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 106 107 if (retry_fault) { 108 /* Returning 1 here also prevents sending the IV to the KFD */ 109 110 /* Process it onyl if it's the first fault for this address */ 111 if (entry->ih != &adev->irq.ih_soft && 112 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 113 entry->timestamp)) 114 return 1; 115 116 /* Delegate it to a different ring if the hardware hasn't 117 * already done it. 118 */ 119 if (entry->ih == &adev->irq.ih) { 120 amdgpu_irq_delegate(adev, entry, 8); 121 return 1; 122 } 123 124 /* Try to handle the recoverable page faults by filling page 125 * tables 126 */ 127 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 128 return 1; 129 } 130 131 if (!amdgpu_sriov_vf(adev)) { 132 /* 133 * Issue a dummy read to wait for the status register to 134 * be updated to avoid reading an incorrect value due to 135 * the new fast GRBM interface. 136 */ 137 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 138 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 139 RREG32(hub->vm_l2_pro_fault_status); 140 141 status = RREG32(hub->vm_l2_pro_fault_status); 142 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 143 } 144 145 if (!printk_ratelimit()) 146 return 0; 147 148 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 149 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 150 151 dev_err(adev->dev, 152 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 153 "for process %s pid %d thread %s pid %d)\n", 154 entry->vmid_src ? "mmhub" : "gfxhub", 155 entry->src_id, entry->ring_id, entry->vmid, 156 entry->pasid, task_info.process_name, task_info.tgid, 157 task_info.task_name, task_info.pid); 158 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 159 addr, entry->client_id, 160 soc15_ih_clientid_name[entry->client_id]); 161 162 if (!amdgpu_sriov_vf(adev)) 163 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 164 status); 165 166 return 0; 167 } 168 169 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 170 .set = gmc_v10_0_vm_fault_interrupt_state, 171 .process = gmc_v10_0_process_interrupt, 172 }; 173 174 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 175 .set = gmc_v10_0_ecc_interrupt_state, 176 .process = amdgpu_umc_process_ecc_irq, 177 }; 178 179 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 180 { 181 adev->gmc.vm_fault.num_types = 1; 182 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 183 184 if (!amdgpu_sriov_vf(adev)) { 185 adev->gmc.ecc_irq.num_types = 1; 186 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 187 } 188 } 189 190 /** 191 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 192 * 193 * @adev: amdgpu_device pointer 194 * @vmhub: vmhub type 195 * 196 */ 197 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 198 uint32_t vmhub) 199 { 200 return ((vmhub == AMDGPU_MMHUB_0 || 201 vmhub == AMDGPU_MMHUB_1) && 202 (!amdgpu_sriov_vf(adev))); 203 } 204 205 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 206 struct amdgpu_device *adev, 207 uint8_t vmid, uint16_t *p_pasid) 208 { 209 uint32_t value; 210 211 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 212 + vmid); 213 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 214 215 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 216 } 217 218 /* 219 * GART 220 * VMID 0 is the physical GPU addresses as used by the kernel. 221 * VMIDs 1-15 are used for userspace clients and are handled 222 * by the amdgpu vm/hsa code. 223 */ 224 225 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 226 unsigned int vmhub, uint32_t flush_type) 227 { 228 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 229 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 230 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 231 u32 tmp; 232 /* Use register 17 for GART */ 233 const unsigned eng = 17; 234 unsigned int i; 235 unsigned char hub_ip = 0; 236 237 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? 238 GC_HWIP : MMHUB_HWIP; 239 240 spin_lock(&adev->gmc.invalidate_lock); 241 /* 242 * It may lose gpuvm invalidate acknowldege state across power-gating 243 * off cycle, add semaphore acquire before invalidation and semaphore 244 * release after invalidation to avoid entering power gated state 245 * to WA the Issue 246 */ 247 248 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 249 if (use_semaphore) { 250 for (i = 0; i < adev->usec_timeout; i++) { 251 /* a read return value of 1 means semaphore acuqire */ 252 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 253 hub->eng_distance * eng, hub_ip); 254 255 if (tmp & 0x1) 256 break; 257 udelay(1); 258 } 259 260 if (i >= adev->usec_timeout) 261 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 262 } 263 264 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 265 hub->eng_distance * eng, 266 inv_req, hub_ip); 267 268 /* 269 * Issue a dummy read to wait for the ACK register to be cleared 270 * to avoid a false ACK due to the new fast GRBM interface. 271 */ 272 if ((vmhub == AMDGPU_GFXHUB_0) && 273 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 274 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 275 hub->eng_distance * eng, hub_ip); 276 277 /* Wait for ACK with a delay.*/ 278 for (i = 0; i < adev->usec_timeout; i++) { 279 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 280 hub->eng_distance * eng, hub_ip); 281 282 tmp &= 1 << vmid; 283 if (tmp) 284 break; 285 286 udelay(1); 287 } 288 289 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 290 if (use_semaphore) 291 /* 292 * add semaphore release after invalidation, 293 * write with 0 means semaphore release 294 */ 295 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 296 hub->eng_distance * eng, 0, hub_ip); 297 298 spin_unlock(&adev->gmc.invalidate_lock); 299 300 if (i < adev->usec_timeout) 301 return; 302 303 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); 304 } 305 306 /** 307 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 308 * 309 * @adev: amdgpu_device pointer 310 * @vmid: vm instance to flush 311 * @vmhub: vmhub type 312 * @flush_type: the flush type 313 * 314 * Flush the TLB for the requested page table. 315 */ 316 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 317 uint32_t vmhub, uint32_t flush_type) 318 { 319 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 320 struct dma_fence *fence; 321 struct amdgpu_job *job; 322 323 int r; 324 325 /* flush hdp cache */ 326 adev->hdp.funcs->flush_hdp(adev, NULL); 327 328 /* For SRIOV run time, driver shouldn't access the register through MMIO 329 * Directly use kiq to do the vm invalidation instead 330 */ 331 if (adev->gfx.kiq.ring.sched.ready && 332 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 333 down_read_trylock(&adev->reset_domain->sem)) { 334 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 335 const unsigned eng = 17; 336 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 337 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 338 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 339 340 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 341 1 << vmid); 342 343 up_read(&adev->reset_domain->sem); 344 return; 345 } 346 347 mutex_lock(&adev->mman.gtt_window_lock); 348 349 if (vmhub == AMDGPU_MMHUB_0) { 350 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 351 mutex_unlock(&adev->mman.gtt_window_lock); 352 return; 353 } 354 355 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 356 357 if (!adev->mman.buffer_funcs_enabled || 358 !adev->ib_pool_ready || 359 amdgpu_in_reset(adev) || 360 ring->sched.ready == false) { 361 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 362 mutex_unlock(&adev->mman.gtt_window_lock); 363 return; 364 } 365 366 /* The SDMA on Navi has a bug which can theoretically result in memory 367 * corruption if an invalidation happens at the same time as an VA 368 * translation. Avoid this by doing the invalidation from the SDMA 369 * itself. 370 */ 371 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 372 &job); 373 if (r) 374 goto error_alloc; 375 376 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 377 job->vm_needs_flush = true; 378 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 379 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 380 r = amdgpu_job_submit(job, &adev->mman.entity, 381 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 382 if (r) 383 goto error_submit; 384 385 mutex_unlock(&adev->mman.gtt_window_lock); 386 387 dma_fence_wait(fence, false); 388 dma_fence_put(fence); 389 390 return; 391 392 error_submit: 393 amdgpu_job_free(job); 394 395 error_alloc: 396 mutex_unlock(&adev->mman.gtt_window_lock); 397 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 398 } 399 400 /** 401 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 402 * 403 * @adev: amdgpu_device pointer 404 * @pasid: pasid to be flush 405 * @flush_type: the flush type 406 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 407 * 408 * Flush the TLB for the requested pasid. 409 */ 410 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 411 uint16_t pasid, uint32_t flush_type, 412 bool all_hub) 413 { 414 int vmid, i; 415 signed long r; 416 uint32_t seq; 417 uint16_t queried_pasid; 418 bool ret; 419 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 420 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 421 422 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 423 spin_lock(&adev->gfx.kiq.ring_lock); 424 /* 2 dwords flush + 8 dwords fence */ 425 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 426 kiq->pmf->kiq_invalidate_tlbs(ring, 427 pasid, flush_type, all_hub); 428 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 429 if (r) { 430 amdgpu_ring_undo(ring); 431 spin_unlock(&adev->gfx.kiq.ring_lock); 432 return -ETIME; 433 } 434 435 amdgpu_ring_commit(ring); 436 spin_unlock(&adev->gfx.kiq.ring_lock); 437 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 438 if (r < 1) { 439 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 440 return -ETIME; 441 } 442 443 return 0; 444 } 445 446 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 447 448 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 449 &queried_pasid); 450 if (ret && queried_pasid == pasid) { 451 if (all_hub) { 452 for (i = 0; i < adev->num_vmhubs; i++) 453 gmc_v10_0_flush_gpu_tlb(adev, vmid, 454 i, flush_type); 455 } else { 456 gmc_v10_0_flush_gpu_tlb(adev, vmid, 457 AMDGPU_GFXHUB_0, flush_type); 458 } 459 break; 460 } 461 } 462 463 return 0; 464 } 465 466 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 467 unsigned vmid, uint64_t pd_addr) 468 { 469 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 470 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 471 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 472 unsigned eng = ring->vm_inv_eng; 473 474 /* 475 * It may lose gpuvm invalidate acknowldege state across power-gating 476 * off cycle, add semaphore acquire before invalidation and semaphore 477 * release after invalidation to avoid entering power gated state 478 * to WA the Issue 479 */ 480 481 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 482 if (use_semaphore) 483 /* a read return value of 1 means semaphore acuqire */ 484 amdgpu_ring_emit_reg_wait(ring, 485 hub->vm_inv_eng0_sem + 486 hub->eng_distance * eng, 0x1, 0x1); 487 488 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 489 (hub->ctx_addr_distance * vmid), 490 lower_32_bits(pd_addr)); 491 492 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 493 (hub->ctx_addr_distance * vmid), 494 upper_32_bits(pd_addr)); 495 496 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 497 hub->eng_distance * eng, 498 hub->vm_inv_eng0_ack + 499 hub->eng_distance * eng, 500 req, 1 << vmid); 501 502 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 503 if (use_semaphore) 504 /* 505 * add semaphore release after invalidation, 506 * write with 0 means semaphore release 507 */ 508 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 509 hub->eng_distance * eng, 0); 510 511 return pd_addr; 512 } 513 514 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 515 unsigned pasid) 516 { 517 struct amdgpu_device *adev = ring->adev; 518 uint32_t reg; 519 520 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 521 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 522 else 523 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 524 525 amdgpu_ring_emit_wreg(ring, reg, pasid); 526 } 527 528 /* 529 * PTE format on NAVI 10: 530 * 63:59 reserved 531 * 58 reserved and for sienna_cichlid is used for MALL noalloc 532 * 57 reserved 533 * 56 F 534 * 55 L 535 * 54 reserved 536 * 53:52 SW 537 * 51 T 538 * 50:48 mtype 539 * 47:12 4k physical page base address 540 * 11:7 fragment 541 * 6 write 542 * 5 read 543 * 4 exe 544 * 3 Z 545 * 2 snooped 546 * 1 system 547 * 0 valid 548 * 549 * PDE format on NAVI 10: 550 * 63:59 block fragment size 551 * 58:55 reserved 552 * 54 P 553 * 53:48 reserved 554 * 47:6 physical base address of PD or PTE 555 * 5:3 reserved 556 * 2 C 557 * 1 system 558 * 0 valid 559 */ 560 561 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 562 { 563 switch (flags) { 564 case AMDGPU_VM_MTYPE_DEFAULT: 565 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 566 case AMDGPU_VM_MTYPE_NC: 567 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 568 case AMDGPU_VM_MTYPE_WC: 569 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 570 case AMDGPU_VM_MTYPE_CC: 571 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 572 case AMDGPU_VM_MTYPE_UC: 573 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 574 default: 575 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 576 } 577 } 578 579 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 580 uint64_t *addr, uint64_t *flags) 581 { 582 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 583 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 584 BUG_ON(*addr & 0xFFFF00000000003FULL); 585 586 if (!adev->gmc.translate_further) 587 return; 588 589 if (level == AMDGPU_VM_PDB1) { 590 /* Set the block fragment size */ 591 if (!(*flags & AMDGPU_PDE_PTE)) 592 *flags |= AMDGPU_PDE_BFS(0x9); 593 594 } else if (level == AMDGPU_VM_PDB0) { 595 if (*flags & AMDGPU_PDE_PTE) 596 *flags &= ~AMDGPU_PDE_PTE; 597 else 598 *flags |= AMDGPU_PTE_TF; 599 } 600 } 601 602 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 603 struct amdgpu_bo_va_mapping *mapping, 604 uint64_t *flags) 605 { 606 *flags &= ~AMDGPU_PTE_EXECUTABLE; 607 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 608 609 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 610 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 611 612 if (mapping->flags & AMDGPU_PTE_PRT) { 613 *flags |= AMDGPU_PTE_PRT; 614 *flags |= AMDGPU_PTE_SNOOPED; 615 *flags |= AMDGPU_PTE_LOG; 616 *flags |= AMDGPU_PTE_SYSTEM; 617 *flags &= ~AMDGPU_PTE_VALID; 618 } 619 } 620 621 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 622 { 623 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 624 unsigned size; 625 626 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 627 size = AMDGPU_VBIOS_VGA_ALLOCATION; 628 } else { 629 u32 viewport; 630 u32 pitch; 631 632 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 633 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 634 size = (REG_GET_FIELD(viewport, 635 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 636 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 637 4); 638 } 639 640 return size; 641 } 642 643 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 644 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 645 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 646 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 647 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 648 .map_mtype = gmc_v10_0_map_mtype, 649 .get_vm_pde = gmc_v10_0_get_vm_pde, 650 .get_vm_pte = gmc_v10_0_get_vm_pte, 651 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 652 }; 653 654 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 655 { 656 if (adev->gmc.gmc_funcs == NULL) 657 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 658 } 659 660 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 661 { 662 switch (adev->ip_versions[UMC_HWIP][0]) { 663 case IP_VERSION(8, 7, 0): 664 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 665 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 666 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 667 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 668 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 669 adev->umc.ras_funcs = &umc_v8_7_ras_funcs; 670 break; 671 default: 672 break; 673 } 674 } 675 676 677 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 678 { 679 switch (adev->ip_versions[MMHUB_HWIP][0]) { 680 case IP_VERSION(2, 3, 0): 681 case IP_VERSION(2, 4, 0): 682 adev->mmhub.funcs = &mmhub_v2_3_funcs; 683 break; 684 default: 685 adev->mmhub.funcs = &mmhub_v2_0_funcs; 686 break; 687 } 688 } 689 690 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 691 { 692 switch (adev->ip_versions[GC_HWIP][0]) { 693 case IP_VERSION(10, 3, 0): 694 case IP_VERSION(10, 3, 2): 695 case IP_VERSION(10, 3, 1): 696 case IP_VERSION(10, 3, 4): 697 case IP_VERSION(10, 3, 5): 698 case IP_VERSION(10, 3, 3): 699 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 700 break; 701 default: 702 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 703 break; 704 } 705 } 706 707 708 static int gmc_v10_0_early_init(void *handle) 709 { 710 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 711 712 gmc_v10_0_set_mmhub_funcs(adev); 713 gmc_v10_0_set_gfxhub_funcs(adev); 714 gmc_v10_0_set_gmc_funcs(adev); 715 gmc_v10_0_set_irq_funcs(adev); 716 gmc_v10_0_set_umc_funcs(adev); 717 718 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 719 adev->gmc.shared_aperture_end = 720 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 721 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 722 adev->gmc.private_aperture_end = 723 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 724 725 return 0; 726 } 727 728 static int gmc_v10_0_late_init(void *handle) 729 { 730 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 731 int r; 732 733 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 734 if (r) 735 return r; 736 737 r = amdgpu_gmc_ras_late_init(adev); 738 if (r) 739 return r; 740 741 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 742 } 743 744 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 745 struct amdgpu_gmc *mc) 746 { 747 u64 base = 0; 748 749 base = adev->gfxhub.funcs->get_fb_location(adev); 750 751 /* add the xgmi offset of the physical node */ 752 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 753 754 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 755 amdgpu_gmc_gart_location(adev, mc); 756 amdgpu_gmc_agp_location(adev, mc); 757 758 /* base offset of vram pages */ 759 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 760 761 /* add the xgmi offset of the physical node */ 762 adev->vm_manager.vram_base_offset += 763 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 764 } 765 766 /** 767 * gmc_v10_0_mc_init - initialize the memory controller driver params 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Look up the amount of vram, vram width, and decide how to place 772 * vram and gart within the GPU's physical address space. 773 * Returns 0 for success. 774 */ 775 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 776 { 777 int r; 778 779 /* size in MB on si */ 780 adev->gmc.mc_vram_size = 781 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 782 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 783 784 if (!(adev->flags & AMD_IS_APU)) { 785 r = amdgpu_device_resize_fb_bar(adev); 786 if (r) 787 return r; 788 } 789 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 790 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 791 792 #ifdef CONFIG_X86_64 793 if (adev->flags & AMD_IS_APU) { 794 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 795 adev->gmc.aper_size = adev->gmc.real_vram_size; 796 } 797 #endif 798 799 /* In case the PCI BAR is larger than the actual amount of vram */ 800 adev->gmc.visible_vram_size = adev->gmc.aper_size; 801 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 802 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 803 804 /* set the gart size */ 805 if (amdgpu_gart_size == -1) 806 adev->gmc.gart_size = 512ULL << 20; 807 else 808 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 809 810 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 811 812 return 0; 813 } 814 815 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 816 { 817 int r; 818 819 if (adev->gart.bo) { 820 WARN(1, "NAVI10 PCIE GART already initialized\n"); 821 return 0; 822 } 823 824 /* Initialize common gart structure */ 825 r = amdgpu_gart_init(adev); 826 if (r) 827 return r; 828 829 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 830 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 831 AMDGPU_PTE_EXECUTABLE; 832 833 return amdgpu_gart_table_vram_alloc(adev); 834 } 835 836 static int gmc_v10_0_sw_init(void *handle) 837 { 838 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 839 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 840 841 adev->gfxhub.funcs->init(adev); 842 843 adev->mmhub.funcs->init(adev); 844 845 spin_lock_init(&adev->gmc.invalidate_lock); 846 847 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 848 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 849 adev->gmc.vram_width = 64; 850 } else if (amdgpu_emu_mode == 1) { 851 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 852 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 853 } else { 854 r = amdgpu_atomfirmware_get_vram_info(adev, 855 &vram_width, &vram_type, &vram_vendor); 856 adev->gmc.vram_width = vram_width; 857 858 adev->gmc.vram_type = vram_type; 859 adev->gmc.vram_vendor = vram_vendor; 860 } 861 862 switch (adev->ip_versions[GC_HWIP][0]) { 863 case IP_VERSION(10, 1, 10): 864 case IP_VERSION(10, 1, 1): 865 case IP_VERSION(10, 1, 2): 866 case IP_VERSION(10, 1, 3): 867 case IP_VERSION(10, 3, 0): 868 case IP_VERSION(10, 3, 2): 869 case IP_VERSION(10, 3, 1): 870 case IP_VERSION(10, 3, 4): 871 case IP_VERSION(10, 3, 5): 872 case IP_VERSION(10, 3, 3): 873 adev->num_vmhubs = 2; 874 /* 875 * To fulfill 4-level page support, 876 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 877 * block size 512 (9bit) 878 */ 879 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 880 break; 881 default: 882 break; 883 } 884 885 /* This interrupt is VMC page fault.*/ 886 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 887 VMC_1_0__SRCID__VM_FAULT, 888 &adev->gmc.vm_fault); 889 890 if (r) 891 return r; 892 893 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 894 UTCL2_1_0__SRCID__FAULT, 895 &adev->gmc.vm_fault); 896 if (r) 897 return r; 898 899 if (!amdgpu_sriov_vf(adev)) { 900 /* interrupt sent to DF. */ 901 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 902 &adev->gmc.ecc_irq); 903 if (r) 904 return r; 905 } 906 907 /* 908 * Set the internal MC address mask This is the max address of the GPU's 909 * internal address space. 910 */ 911 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 912 913 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 914 if (r) { 915 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 916 return r; 917 } 918 919 r = gmc_v10_0_mc_init(adev); 920 if (r) 921 return r; 922 923 amdgpu_gmc_get_vbios_allocations(adev); 924 amdgpu_gmc_get_reserved_allocation(adev); 925 926 /* Memory manager */ 927 r = amdgpu_bo_init(adev); 928 if (r) 929 return r; 930 931 r = gmc_v10_0_gart_init(adev); 932 if (r) 933 return r; 934 935 /* 936 * number of VMs 937 * VMID 0 is reserved for System 938 * amdgpu graphics/compute will use VMIDs 1-7 939 * amdkfd will use VMIDs 8-15 940 */ 941 adev->vm_manager.first_kfd_vmid = 8; 942 943 amdgpu_vm_manager_init(adev); 944 945 return 0; 946 } 947 948 /** 949 * gmc_v10_0_gart_fini - vm fini callback 950 * 951 * @adev: amdgpu_device pointer 952 * 953 * Tears down the driver GART/VM setup (CIK). 954 */ 955 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 956 { 957 amdgpu_gart_table_vram_free(adev); 958 } 959 960 static int gmc_v10_0_sw_fini(void *handle) 961 { 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 amdgpu_vm_manager_fini(adev); 965 gmc_v10_0_gart_fini(adev); 966 amdgpu_gem_force_release(adev); 967 amdgpu_bo_fini(adev); 968 969 return 0; 970 } 971 972 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 973 { 974 } 975 976 /** 977 * gmc_v10_0_gart_enable - gart enable 978 * 979 * @adev: amdgpu_device pointer 980 */ 981 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 982 { 983 int r; 984 bool value; 985 986 if (adev->gart.bo == NULL) { 987 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 988 return -EINVAL; 989 } 990 991 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 992 goto skip_pin_bo; 993 994 r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 995 if (r) 996 return r; 997 998 skip_pin_bo: 999 r = adev->gfxhub.funcs->gart_enable(adev); 1000 if (r) 1001 return r; 1002 1003 r = adev->mmhub.funcs->gart_enable(adev); 1004 if (r) 1005 return r; 1006 1007 adev->hdp.funcs->init_registers(adev); 1008 1009 /* Flush HDP after it is initialized */ 1010 adev->hdp.funcs->flush_hdp(adev, NULL); 1011 1012 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1013 false : true; 1014 1015 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1016 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1017 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1018 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1019 1020 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1021 (unsigned)(adev->gmc.gart_size >> 20), 1022 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1023 1024 adev->gart.ready = true; 1025 1026 return 0; 1027 } 1028 1029 static int gmc_v10_0_hw_init(void *handle) 1030 { 1031 int r; 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 1034 /* The sequence of these two function calls matters.*/ 1035 gmc_v10_0_init_golden_registers(adev); 1036 1037 /* 1038 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1039 * register setup within GMC, or else system hang when harvesting SA. 1040 */ 1041 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1042 adev->gfxhub.funcs->utcl2_harvest(adev); 1043 1044 r = gmc_v10_0_gart_enable(adev); 1045 if (r) 1046 return r; 1047 1048 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1049 adev->umc.funcs->init_registers(adev); 1050 1051 return 0; 1052 } 1053 1054 /** 1055 * gmc_v10_0_gart_disable - gart disable 1056 * 1057 * @adev: amdgpu_device pointer 1058 * 1059 * This disables all VM page table. 1060 */ 1061 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1062 { 1063 adev->gfxhub.funcs->gart_disable(adev); 1064 adev->mmhub.funcs->gart_disable(adev); 1065 } 1066 1067 static int gmc_v10_0_hw_fini(void *handle) 1068 { 1069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1070 1071 gmc_v10_0_gart_disable(adev); 1072 1073 if (amdgpu_sriov_vf(adev)) { 1074 /* full access mode, so don't touch any GMC register */ 1075 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1076 return 0; 1077 } 1078 1079 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1080 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1081 1082 return 0; 1083 } 1084 1085 static int gmc_v10_0_suspend(void *handle) 1086 { 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 gmc_v10_0_hw_fini(adev); 1090 1091 return 0; 1092 } 1093 1094 static int gmc_v10_0_resume(void *handle) 1095 { 1096 int r; 1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1098 1099 r = gmc_v10_0_hw_init(adev); 1100 if (r) 1101 return r; 1102 1103 amdgpu_vmid_reset_all(adev); 1104 1105 return 0; 1106 } 1107 1108 static bool gmc_v10_0_is_idle(void *handle) 1109 { 1110 /* MC is always ready in GMC v10.*/ 1111 return true; 1112 } 1113 1114 static int gmc_v10_0_wait_for_idle(void *handle) 1115 { 1116 /* There is no need to wait for MC idle in GMC v10.*/ 1117 return 0; 1118 } 1119 1120 static int gmc_v10_0_soft_reset(void *handle) 1121 { 1122 return 0; 1123 } 1124 1125 static int gmc_v10_0_set_clockgating_state(void *handle, 1126 enum amd_clockgating_state state) 1127 { 1128 int r; 1129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1130 1131 r = adev->mmhub.funcs->set_clockgating(adev, state); 1132 if (r) 1133 return r; 1134 1135 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1136 return athub_v2_1_set_clockgating(adev, state); 1137 else 1138 return athub_v2_0_set_clockgating(adev, state); 1139 } 1140 1141 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1142 { 1143 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1144 1145 adev->mmhub.funcs->get_clockgating(adev, flags); 1146 1147 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1148 athub_v2_1_get_clockgating(adev, flags); 1149 else 1150 athub_v2_0_get_clockgating(adev, flags); 1151 } 1152 1153 static int gmc_v10_0_set_powergating_state(void *handle, 1154 enum amd_powergating_state state) 1155 { 1156 return 0; 1157 } 1158 1159 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1160 .name = "gmc_v10_0", 1161 .early_init = gmc_v10_0_early_init, 1162 .late_init = gmc_v10_0_late_init, 1163 .sw_init = gmc_v10_0_sw_init, 1164 .sw_fini = gmc_v10_0_sw_fini, 1165 .hw_init = gmc_v10_0_hw_init, 1166 .hw_fini = gmc_v10_0_hw_fini, 1167 .suspend = gmc_v10_0_suspend, 1168 .resume = gmc_v10_0_resume, 1169 .is_idle = gmc_v10_0_is_idle, 1170 .wait_for_idle = gmc_v10_0_wait_for_idle, 1171 .soft_reset = gmc_v10_0_soft_reset, 1172 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1173 .set_powergating_state = gmc_v10_0_set_powergating_state, 1174 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1175 }; 1176 1177 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1178 { 1179 .type = AMD_IP_BLOCK_TYPE_GMC, 1180 .major = 10, 1181 .minor = 0, 1182 .rev = 0, 1183 .funcs = &gmc_v10_0_ip_funcs, 1184 }; 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