1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 29 #include "hdp/hdp_5_0_0_offset.h" 30 #include "hdp/hdp_5_0_0_sh_mask.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "mmhub/mmhub_2_0_0_sh_mask.h" 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "athub_v2_0.h" 50 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/ 51 #define AMDGPU_NUM_OF_VMIDS 8 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int 61 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 62 struct amdgpu_irq_src *src, unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 struct amdgpu_vmhub *hub; 66 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; 67 68 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 69 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 70 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 71 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 72 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 73 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 74 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 75 76 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 77 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 78 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 80 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 81 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 82 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 83 84 switch (state) { 85 case AMDGPU_IRQ_STATE_DISABLE: 86 /* MM HUB */ 87 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 88 for (i = 0; i < 16; i++) { 89 reg = hub->vm_context0_cntl + i; 90 tmp = RREG32(reg); 91 tmp &= ~bits[AMDGPU_MMHUB_0]; 92 WREG32(reg, tmp); 93 } 94 95 /* GFX HUB */ 96 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 97 for (i = 0; i < 16; i++) { 98 reg = hub->vm_context0_cntl + i; 99 tmp = RREG32(reg); 100 tmp &= ~bits[AMDGPU_GFXHUB_0]; 101 WREG32(reg, tmp); 102 } 103 break; 104 case AMDGPU_IRQ_STATE_ENABLE: 105 /* MM HUB */ 106 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 107 for (i = 0; i < 16; i++) { 108 reg = hub->vm_context0_cntl + i; 109 tmp = RREG32(reg); 110 tmp |= bits[AMDGPU_MMHUB_0]; 111 WREG32(reg, tmp); 112 } 113 114 /* GFX HUB */ 115 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 116 for (i = 0; i < 16; i++) { 117 reg = hub->vm_context0_cntl + i; 118 tmp = RREG32(reg); 119 tmp |= bits[AMDGPU_GFXHUB_0]; 120 WREG32(reg, tmp); 121 } 122 break; 123 default: 124 break; 125 } 126 127 return 0; 128 } 129 130 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 131 struct amdgpu_irq_src *source, 132 struct amdgpu_iv_entry *entry) 133 { 134 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 135 uint32_t status = 0; 136 u64 addr; 137 138 addr = (u64)entry->src_data[0] << 12; 139 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 140 141 if (!amdgpu_sriov_vf(adev)) { 142 /* 143 * Issue a dummy read to wait for the status register to 144 * be updated to avoid reading an incorrect value due to 145 * the new fast GRBM interface. 146 */ 147 if (entry->vmid_src == AMDGPU_GFXHUB_0) 148 RREG32(hub->vm_l2_pro_fault_status); 149 150 status = RREG32(hub->vm_l2_pro_fault_status); 151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 152 } 153 154 if (printk_ratelimit()) { 155 struct amdgpu_task_info task_info; 156 157 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 158 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 159 160 dev_err(adev->dev, 161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 162 "for process %s pid %d thread %s pid %d)\n", 163 entry->vmid_src ? "mmhub" : "gfxhub", 164 entry->src_id, entry->ring_id, entry->vmid, 165 entry->pasid, task_info.process_name, task_info.tgid, 166 task_info.task_name, task_info.pid); 167 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 168 addr, entry->client_id); 169 if (!amdgpu_sriov_vf(adev)) { 170 dev_err(adev->dev, 171 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 172 status); 173 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 174 REG_GET_FIELD(status, 175 GCVM_L2_PROTECTION_FAULT_STATUS, CID)); 176 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 177 REG_GET_FIELD(status, 178 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 179 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 180 REG_GET_FIELD(status, 181 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 182 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 183 REG_GET_FIELD(status, 184 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 185 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 186 REG_GET_FIELD(status, 187 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 188 dev_err(adev->dev, "\t RW: 0x%lx\n", 189 REG_GET_FIELD(status, 190 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 191 } 192 } 193 194 return 0; 195 } 196 197 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 198 .set = gmc_v10_0_vm_fault_interrupt_state, 199 .process = gmc_v10_0_process_interrupt, 200 }; 201 202 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 203 { 204 adev->gmc.vm_fault.num_types = 1; 205 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 206 } 207 208 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid, 209 uint32_t flush_type) 210 { 211 u32 req = 0; 212 213 /* invalidate using legacy mode on vmid*/ 214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 215 PER_VMID_INVALIDATE_REQ, 1 << vmid); 216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 217 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 218 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 219 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 220 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 221 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 222 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 223 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 224 225 return req; 226 } 227 228 /** 229 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 230 * 231 * @adev: amdgpu_device pointer 232 * @vmhub: vmhub type 233 * 234 */ 235 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 236 uint32_t vmhub) 237 { 238 return ((vmhub == AMDGPU_MMHUB_0 || 239 vmhub == AMDGPU_MMHUB_1) && 240 (!amdgpu_sriov_vf(adev))); 241 } 242 243 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 244 struct amdgpu_device *adev, 245 uint8_t vmid, uint16_t *p_pasid) 246 { 247 uint32_t value; 248 249 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 250 + vmid); 251 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 252 253 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 254 } 255 256 /* 257 * GART 258 * VMID 0 is the physical GPU addresses as used by the kernel. 259 * VMIDs 1-15 are used for userspace clients and are handled 260 * by the amdgpu vm/hsa code. 261 */ 262 263 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 264 unsigned int vmhub, uint32_t flush_type) 265 { 266 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 267 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 268 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type); 269 u32 tmp; 270 /* Use register 17 for GART */ 271 const unsigned eng = 17; 272 unsigned int i; 273 274 spin_lock(&adev->gmc.invalidate_lock); 275 /* 276 * It may lose gpuvm invalidate acknowldege state across power-gating 277 * off cycle, add semaphore acquire before invalidation and semaphore 278 * release after invalidation to avoid entering power gated state 279 * to WA the Issue 280 */ 281 282 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 283 if (use_semaphore) { 284 for (i = 0; i < adev->usec_timeout; i++) { 285 /* a read return value of 1 means semaphore acuqire */ 286 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng); 287 if (tmp & 0x1) 288 break; 289 udelay(1); 290 } 291 292 if (i >= adev->usec_timeout) 293 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 294 } 295 296 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req); 297 298 /* 299 * Issue a dummy read to wait for the ACK register to be cleared 300 * to avoid a false ACK due to the new fast GRBM interface. 301 */ 302 if (vmhub == AMDGPU_GFXHUB_0) 303 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng); 304 305 /* Wait for ACK with a delay.*/ 306 for (i = 0; i < adev->usec_timeout; i++) { 307 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 308 tmp &= 1 << vmid; 309 if (tmp) 310 break; 311 312 udelay(1); 313 } 314 315 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 316 if (use_semaphore) 317 /* 318 * add semaphore release after invalidation, 319 * write with 0 means semaphore release 320 */ 321 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0); 322 323 spin_unlock(&adev->gmc.invalidate_lock); 324 325 if (i < adev->usec_timeout) 326 return; 327 328 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 329 } 330 331 /** 332 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 333 * 334 * @adev: amdgpu_device pointer 335 * @vmid: vm instance to flush 336 * 337 * Flush the TLB for the requested page table. 338 */ 339 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 340 uint32_t vmhub, uint32_t flush_type) 341 { 342 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 343 struct dma_fence *fence; 344 struct amdgpu_job *job; 345 346 int r; 347 348 /* flush hdp cache */ 349 adev->nbio.funcs->hdp_flush(adev, NULL); 350 351 mutex_lock(&adev->mman.gtt_window_lock); 352 353 if (vmhub == AMDGPU_MMHUB_0) { 354 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 355 mutex_unlock(&adev->mman.gtt_window_lock); 356 return; 357 } 358 359 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 360 361 if (!adev->mman.buffer_funcs_enabled || 362 !adev->ib_pool_ready || 363 adev->in_gpu_reset || 364 ring->sched.ready == false) { 365 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 366 mutex_unlock(&adev->mman.gtt_window_lock); 367 return; 368 } 369 370 /* The SDMA on Navi has a bug which can theoretically result in memory 371 * corruption if an invalidation happens at the same time as an VA 372 * translation. Avoid this by doing the invalidation from the SDMA 373 * itself. 374 */ 375 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 376 &job); 377 if (r) 378 goto error_alloc; 379 380 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 381 job->vm_needs_flush = true; 382 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 383 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 384 r = amdgpu_job_submit(job, &adev->mman.entity, 385 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 386 if (r) 387 goto error_submit; 388 389 mutex_unlock(&adev->mman.gtt_window_lock); 390 391 dma_fence_wait(fence, false); 392 dma_fence_put(fence); 393 394 return; 395 396 error_submit: 397 amdgpu_job_free(job); 398 399 error_alloc: 400 mutex_unlock(&adev->mman.gtt_window_lock); 401 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 402 } 403 404 /** 405 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 406 * 407 * @adev: amdgpu_device pointer 408 * @pasid: pasid to be flush 409 * 410 * Flush the TLB for the requested pasid. 411 */ 412 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 413 uint16_t pasid, uint32_t flush_type, 414 bool all_hub) 415 { 416 int vmid, i; 417 signed long r; 418 uint32_t seq; 419 uint16_t queried_pasid; 420 bool ret; 421 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 422 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 423 424 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 425 spin_lock(&adev->gfx.kiq.ring_lock); 426 /* 2 dwords flush + 8 dwords fence */ 427 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 428 kiq->pmf->kiq_invalidate_tlbs(ring, 429 pasid, flush_type, all_hub); 430 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 431 if (r) { 432 amdgpu_ring_undo(ring); 433 spin_unlock(&adev->gfx.kiq.ring_lock); 434 return -ETIME; 435 } 436 437 amdgpu_ring_commit(ring); 438 spin_unlock(&adev->gfx.kiq.ring_lock); 439 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 440 if (r < 1) { 441 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 442 return -ETIME; 443 } 444 445 return 0; 446 } 447 448 for (vmid = 1; vmid < 16; vmid++) { 449 450 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 451 &queried_pasid); 452 if (ret && queried_pasid == pasid) { 453 if (all_hub) { 454 for (i = 0; i < adev->num_vmhubs; i++) 455 gmc_v10_0_flush_gpu_tlb(adev, vmid, 456 i, flush_type); 457 } else { 458 gmc_v10_0_flush_gpu_tlb(adev, vmid, 459 AMDGPU_GFXHUB_0, flush_type); 460 } 461 break; 462 } 463 } 464 465 return 0; 466 } 467 468 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 469 unsigned vmid, uint64_t pd_addr) 470 { 471 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 472 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 473 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0); 474 unsigned eng = ring->vm_inv_eng; 475 476 /* 477 * It may lose gpuvm invalidate acknowldege state across power-gating 478 * off cycle, add semaphore acquire before invalidation and semaphore 479 * release after invalidation to avoid entering power gated state 480 * to WA the Issue 481 */ 482 483 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 484 if (use_semaphore) 485 /* a read return value of 1 means semaphore acuqire */ 486 amdgpu_ring_emit_reg_wait(ring, 487 hub->vm_inv_eng0_sem + eng, 0x1, 0x1); 488 489 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 490 lower_32_bits(pd_addr)); 491 492 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 493 upper_32_bits(pd_addr)); 494 495 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 496 hub->vm_inv_eng0_ack + eng, 497 req, 1 << vmid); 498 499 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 500 if (use_semaphore) 501 /* 502 * add semaphore release after invalidation, 503 * write with 0 means semaphore release 504 */ 505 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0); 506 507 return pd_addr; 508 } 509 510 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 511 unsigned pasid) 512 { 513 struct amdgpu_device *adev = ring->adev; 514 uint32_t reg; 515 516 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 517 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 518 else 519 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 520 521 amdgpu_ring_emit_wreg(ring, reg, pasid); 522 } 523 524 /* 525 * PTE format on NAVI 10: 526 * 63:59 reserved 527 * 58:57 reserved 528 * 56 F 529 * 55 L 530 * 54 reserved 531 * 53:52 SW 532 * 51 T 533 * 50:48 mtype 534 * 47:12 4k physical page base address 535 * 11:7 fragment 536 * 6 write 537 * 5 read 538 * 4 exe 539 * 3 Z 540 * 2 snooped 541 * 1 system 542 * 0 valid 543 * 544 * PDE format on NAVI 10: 545 * 63:59 block fragment size 546 * 58:55 reserved 547 * 54 P 548 * 53:48 reserved 549 * 47:6 physical base address of PD or PTE 550 * 5:3 reserved 551 * 2 C 552 * 1 system 553 * 0 valid 554 */ 555 556 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 557 { 558 switch (flags) { 559 case AMDGPU_VM_MTYPE_DEFAULT: 560 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 561 case AMDGPU_VM_MTYPE_NC: 562 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 563 case AMDGPU_VM_MTYPE_WC: 564 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 565 case AMDGPU_VM_MTYPE_CC: 566 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 567 case AMDGPU_VM_MTYPE_UC: 568 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 569 default: 570 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 571 } 572 } 573 574 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 575 uint64_t *addr, uint64_t *flags) 576 { 577 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 578 *addr = adev->vm_manager.vram_base_offset + *addr - 579 adev->gmc.vram_start; 580 BUG_ON(*addr & 0xFFFF00000000003FULL); 581 582 if (!adev->gmc.translate_further) 583 return; 584 585 if (level == AMDGPU_VM_PDB1) { 586 /* Set the block fragment size */ 587 if (!(*flags & AMDGPU_PDE_PTE)) 588 *flags |= AMDGPU_PDE_BFS(0x9); 589 590 } else if (level == AMDGPU_VM_PDB0) { 591 if (*flags & AMDGPU_PDE_PTE) 592 *flags &= ~AMDGPU_PDE_PTE; 593 else 594 *flags |= AMDGPU_PTE_TF; 595 } 596 } 597 598 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 599 struct amdgpu_bo_va_mapping *mapping, 600 uint64_t *flags) 601 { 602 *flags &= ~AMDGPU_PTE_EXECUTABLE; 603 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 604 605 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 606 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 607 608 if (mapping->flags & AMDGPU_PTE_PRT) { 609 *flags |= AMDGPU_PTE_PRT; 610 *flags |= AMDGPU_PTE_SNOOPED; 611 *flags |= AMDGPU_PTE_LOG; 612 *flags |= AMDGPU_PTE_SYSTEM; 613 *flags &= ~AMDGPU_PTE_VALID; 614 } 615 } 616 617 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 618 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 619 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 620 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 621 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 622 .map_mtype = gmc_v10_0_map_mtype, 623 .get_vm_pde = gmc_v10_0_get_vm_pde, 624 .get_vm_pte = gmc_v10_0_get_vm_pte 625 }; 626 627 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 628 { 629 if (adev->gmc.gmc_funcs == NULL) 630 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 631 } 632 633 static int gmc_v10_0_early_init(void *handle) 634 { 635 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 636 637 gmc_v10_0_set_gmc_funcs(adev); 638 gmc_v10_0_set_irq_funcs(adev); 639 640 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 641 adev->gmc.shared_aperture_end = 642 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 643 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 644 adev->gmc.private_aperture_end = 645 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 646 647 return 0; 648 } 649 650 static int gmc_v10_0_late_init(void *handle) 651 { 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 int r; 654 655 amdgpu_bo_late_init(adev); 656 657 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 658 if (r) 659 return r; 660 661 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 662 } 663 664 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 665 struct amdgpu_gmc *mc) 666 { 667 u64 base = 0; 668 669 base = gfxhub_v2_0_get_fb_location(adev); 670 671 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 672 amdgpu_gmc_gart_location(adev, mc); 673 674 /* base offset of vram pages */ 675 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); 676 } 677 678 /** 679 * gmc_v10_0_mc_init - initialize the memory controller driver params 680 * 681 * @adev: amdgpu_device pointer 682 * 683 * Look up the amount of vram, vram width, and decide how to place 684 * vram and gart within the GPU's physical address space. 685 * Returns 0 for success. 686 */ 687 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 688 { 689 int r; 690 691 /* size in MB on si */ 692 adev->gmc.mc_vram_size = 693 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 694 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 695 696 if (!(adev->flags & AMD_IS_APU)) { 697 r = amdgpu_device_resize_fb_bar(adev); 698 if (r) 699 return r; 700 } 701 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 702 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 703 704 /* In case the PCI BAR is larger than the actual amount of vram */ 705 adev->gmc.visible_vram_size = adev->gmc.aper_size; 706 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 707 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 708 709 /* set the gart size */ 710 if (amdgpu_gart_size == -1) { 711 switch (adev->asic_type) { 712 case CHIP_NAVI10: 713 case CHIP_NAVI14: 714 case CHIP_NAVI12: 715 default: 716 adev->gmc.gart_size = 512ULL << 20; 717 break; 718 } 719 } else 720 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 721 722 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 723 724 return 0; 725 } 726 727 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 728 { 729 int r; 730 731 if (adev->gart.bo) { 732 WARN(1, "NAVI10 PCIE GART already initialized\n"); 733 return 0; 734 } 735 736 /* Initialize common gart structure */ 737 r = amdgpu_gart_init(adev); 738 if (r) 739 return r; 740 741 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 742 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 743 AMDGPU_PTE_EXECUTABLE; 744 745 return amdgpu_gart_table_vram_alloc(adev); 746 } 747 748 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 749 { 750 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 751 unsigned size; 752 753 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 754 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 755 } else { 756 u32 viewport; 757 u32 pitch; 758 759 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 760 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 761 size = (REG_GET_FIELD(viewport, 762 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 763 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 764 4); 765 } 766 /* return 0 if the pre-OS buffer uses up most of vram */ 767 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) { 768 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \ 769 be aware of gart table overwrite\n"); 770 return 0; 771 } 772 773 return size; 774 } 775 776 777 778 static int gmc_v10_0_sw_init(void *handle) 779 { 780 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 782 783 gfxhub_v2_0_init(adev); 784 mmhub_v2_0_init(adev); 785 786 spin_lock_init(&adev->gmc.invalidate_lock); 787 788 r = amdgpu_atomfirmware_get_vram_info(adev, 789 &vram_width, &vram_type, &vram_vendor); 790 if (!amdgpu_emu_mode) 791 adev->gmc.vram_width = vram_width; 792 else 793 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 794 795 adev->gmc.vram_type = vram_type; 796 adev->gmc.vram_vendor = vram_vendor; 797 switch (adev->asic_type) { 798 case CHIP_NAVI10: 799 case CHIP_NAVI14: 800 case CHIP_NAVI12: 801 adev->num_vmhubs = 2; 802 /* 803 * To fulfill 4-level page support, 804 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 805 * block size 512 (9bit) 806 */ 807 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 808 break; 809 default: 810 break; 811 } 812 813 /* This interrupt is VMC page fault.*/ 814 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 815 VMC_1_0__SRCID__VM_FAULT, 816 &adev->gmc.vm_fault); 817 818 if (r) 819 return r; 820 821 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 822 UTCL2_1_0__SRCID__FAULT, 823 &adev->gmc.vm_fault); 824 if (r) 825 return r; 826 827 /* 828 * Set the internal MC address mask This is the max address of the GPU's 829 * internal address space. 830 */ 831 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 832 833 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 834 if (r) { 835 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 836 return r; 837 } 838 839 r = gmc_v10_0_mc_init(adev); 840 if (r) 841 return r; 842 843 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev); 844 845 /* Memory manager */ 846 r = amdgpu_bo_init(adev); 847 if (r) 848 return r; 849 850 r = gmc_v10_0_gart_init(adev); 851 if (r) 852 return r; 853 854 /* 855 * number of VMs 856 * VMID 0 is reserved for System 857 * amdgpu graphics/compute will use VMIDs 1-7 858 * amdkfd will use VMIDs 8-15 859 */ 860 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 861 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 862 863 amdgpu_vm_manager_init(adev); 864 865 return 0; 866 } 867 868 /** 869 * gmc_v8_0_gart_fini - vm fini callback 870 * 871 * @adev: amdgpu_device pointer 872 * 873 * Tears down the driver GART/VM setup (CIK). 874 */ 875 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 876 { 877 amdgpu_gart_table_vram_free(adev); 878 amdgpu_gart_fini(adev); 879 } 880 881 static int gmc_v10_0_sw_fini(void *handle) 882 { 883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 884 885 amdgpu_vm_manager_fini(adev); 886 gmc_v10_0_gart_fini(adev); 887 amdgpu_gem_force_release(adev); 888 amdgpu_bo_fini(adev); 889 890 return 0; 891 } 892 893 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 894 { 895 switch (adev->asic_type) { 896 case CHIP_NAVI10: 897 case CHIP_NAVI14: 898 case CHIP_NAVI12: 899 break; 900 default: 901 break; 902 } 903 } 904 905 /** 906 * gmc_v10_0_gart_enable - gart enable 907 * 908 * @adev: amdgpu_device pointer 909 */ 910 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 911 { 912 int r; 913 bool value; 914 u32 tmp; 915 916 if (adev->gart.bo == NULL) { 917 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 918 return -EINVAL; 919 } 920 921 r = amdgpu_gart_table_vram_pin(adev); 922 if (r) 923 return r; 924 925 r = gfxhub_v2_0_gart_enable(adev); 926 if (r) 927 return r; 928 929 r = mmhub_v2_0_gart_enable(adev); 930 if (r) 931 return r; 932 933 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 934 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 935 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 936 937 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 938 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 939 940 /* Flush HDP after it is initialized */ 941 adev->nbio.funcs->hdp_flush(adev, NULL); 942 943 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 944 false : true; 945 946 gfxhub_v2_0_set_fault_enable_default(adev, value); 947 mmhub_v2_0_set_fault_enable_default(adev, value); 948 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 949 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 950 951 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 952 (unsigned)(adev->gmc.gart_size >> 20), 953 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 954 955 adev->gart.ready = true; 956 957 return 0; 958 } 959 960 static int gmc_v10_0_hw_init(void *handle) 961 { 962 int r; 963 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 964 965 /* The sequence of these two function calls matters.*/ 966 gmc_v10_0_init_golden_registers(adev); 967 968 r = gmc_v10_0_gart_enable(adev); 969 if (r) 970 return r; 971 972 return 0; 973 } 974 975 /** 976 * gmc_v10_0_gart_disable - gart disable 977 * 978 * @adev: amdgpu_device pointer 979 * 980 * This disables all VM page table. 981 */ 982 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 983 { 984 gfxhub_v2_0_gart_disable(adev); 985 mmhub_v2_0_gart_disable(adev); 986 amdgpu_gart_table_vram_unpin(adev); 987 } 988 989 static int gmc_v10_0_hw_fini(void *handle) 990 { 991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 992 993 if (amdgpu_sriov_vf(adev)) { 994 /* full access mode, so don't touch any GMC register */ 995 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 996 return 0; 997 } 998 999 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1000 gmc_v10_0_gart_disable(adev); 1001 1002 return 0; 1003 } 1004 1005 static int gmc_v10_0_suspend(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 gmc_v10_0_hw_fini(adev); 1010 1011 return 0; 1012 } 1013 1014 static int gmc_v10_0_resume(void *handle) 1015 { 1016 int r; 1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018 1019 r = gmc_v10_0_hw_init(adev); 1020 if (r) 1021 return r; 1022 1023 amdgpu_vmid_reset_all(adev); 1024 1025 return 0; 1026 } 1027 1028 static bool gmc_v10_0_is_idle(void *handle) 1029 { 1030 /* MC is always ready in GMC v10.*/ 1031 return true; 1032 } 1033 1034 static int gmc_v10_0_wait_for_idle(void *handle) 1035 { 1036 /* There is no need to wait for MC idle in GMC v10.*/ 1037 return 0; 1038 } 1039 1040 static int gmc_v10_0_soft_reset(void *handle) 1041 { 1042 return 0; 1043 } 1044 1045 static int gmc_v10_0_set_clockgating_state(void *handle, 1046 enum amd_clockgating_state state) 1047 { 1048 int r; 1049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1050 1051 r = mmhub_v2_0_set_clockgating(adev, state); 1052 if (r) 1053 return r; 1054 1055 return athub_v2_0_set_clockgating(adev, state); 1056 } 1057 1058 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1059 { 1060 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1061 1062 mmhub_v2_0_get_clockgating(adev, flags); 1063 1064 athub_v2_0_get_clockgating(adev, flags); 1065 } 1066 1067 static int gmc_v10_0_set_powergating_state(void *handle, 1068 enum amd_powergating_state state) 1069 { 1070 return 0; 1071 } 1072 1073 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1074 .name = "gmc_v10_0", 1075 .early_init = gmc_v10_0_early_init, 1076 .late_init = gmc_v10_0_late_init, 1077 .sw_init = gmc_v10_0_sw_init, 1078 .sw_fini = gmc_v10_0_sw_fini, 1079 .hw_init = gmc_v10_0_hw_init, 1080 .hw_fini = gmc_v10_0_hw_fini, 1081 .suspend = gmc_v10_0_suspend, 1082 .resume = gmc_v10_0_resume, 1083 .is_idle = gmc_v10_0_is_idle, 1084 .wait_for_idle = gmc_v10_0_wait_for_idle, 1085 .soft_reset = gmc_v10_0_soft_reset, 1086 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1087 .set_powergating_state = gmc_v10_0_set_powergating_state, 1088 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1089 }; 1090 1091 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1092 { 1093 .type = AMD_IP_BLOCK_TYPE_GMC, 1094 .major = 10, 1095 .minor = 0, 1096 .rev = 0, 1097 .funcs = &gmc_v10_0_ip_funcs, 1098 }; 1099