1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 #include "umc_v8_7.h" 29 30 #include "hdp/hdp_5_0_0_offset.h" 31 #include "hdp/hdp_5_0_0_sh_mask.h" 32 #include "athub/athub_2_0_0_sh_mask.h" 33 #include "athub/athub_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_sh_mask.h" 36 #include "oss/osssys_5_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 40 #include "soc15.h" 41 #include "soc15d.h" 42 #include "soc15_common.h" 43 44 #include "nbio_v2_3.h" 45 46 #include "gfxhub_v2_0.h" 47 #include "gfxhub_v2_1.h" 48 #include "mmhub_v2_0.h" 49 #include "mmhub_v2_3.h" 50 #include "athub_v2_0.h" 51 #include "athub_v2_1.h" 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 61 struct amdgpu_irq_src *src, 62 unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 return 0; 66 } 67 68 static int 69 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 70 struct amdgpu_irq_src *src, unsigned type, 71 enum amdgpu_interrupt_state state) 72 { 73 switch (state) { 74 case AMDGPU_IRQ_STATE_DISABLE: 75 /* MM HUB */ 76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 77 /* GFX HUB */ 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 83 /* GFX HUB */ 84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 85 break; 86 default: 87 break; 88 } 89 90 return 0; 91 } 92 93 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 94 struct amdgpu_irq_src *source, 95 struct amdgpu_iv_entry *entry) 96 { 97 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 98 uint32_t status = 0; 99 u64 addr; 100 101 addr = (u64)entry->src_data[0] << 12; 102 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 103 104 if (!amdgpu_sriov_vf(adev)) { 105 /* 106 * Issue a dummy read to wait for the status register to 107 * be updated to avoid reading an incorrect value due to 108 * the new fast GRBM interface. 109 */ 110 if (entry->vmid_src == AMDGPU_GFXHUB_0) 111 RREG32(hub->vm_l2_pro_fault_status); 112 113 status = RREG32(hub->vm_l2_pro_fault_status); 114 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 115 } 116 117 if (printk_ratelimit()) { 118 struct amdgpu_task_info task_info; 119 120 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 121 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 122 123 dev_err(adev->dev, 124 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 125 "for process %s pid %d thread %s pid %d)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, 128 entry->pasid, task_info.process_name, task_info.tgid, 129 task_info.task_name, task_info.pid); 130 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 131 addr, entry->client_id); 132 if (!amdgpu_sriov_vf(adev)) 133 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 134 } 135 136 return 0; 137 } 138 139 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 140 .set = gmc_v10_0_vm_fault_interrupt_state, 141 .process = gmc_v10_0_process_interrupt, 142 }; 143 144 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 145 .set = gmc_v10_0_ecc_interrupt_state, 146 .process = amdgpu_umc_process_ecc_irq, 147 }; 148 149 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 150 { 151 adev->gmc.vm_fault.num_types = 1; 152 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 153 154 if (!amdgpu_sriov_vf(adev)) { 155 adev->gmc.ecc_irq.num_types = 1; 156 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 157 } 158 } 159 160 /** 161 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 162 * 163 * @adev: amdgpu_device pointer 164 * @vmhub: vmhub type 165 * 166 */ 167 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 168 uint32_t vmhub) 169 { 170 return ((vmhub == AMDGPU_MMHUB_0 || 171 vmhub == AMDGPU_MMHUB_1) && 172 (!amdgpu_sriov_vf(adev))); 173 } 174 175 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 176 struct amdgpu_device *adev, 177 uint8_t vmid, uint16_t *p_pasid) 178 { 179 uint32_t value; 180 181 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 182 + vmid); 183 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 184 185 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 186 } 187 188 /* 189 * GART 190 * VMID 0 is the physical GPU addresses as used by the kernel. 191 * VMIDs 1-15 are used for userspace clients and are handled 192 * by the amdgpu vm/hsa code. 193 */ 194 195 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 196 unsigned int vmhub, uint32_t flush_type) 197 { 198 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 199 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 200 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 201 u32 tmp; 202 /* Use register 17 for GART */ 203 const unsigned eng = 17; 204 unsigned int i; 205 206 spin_lock(&adev->gmc.invalidate_lock); 207 /* 208 * It may lose gpuvm invalidate acknowldege state across power-gating 209 * off cycle, add semaphore acquire before invalidation and semaphore 210 * release after invalidation to avoid entering power gated state 211 * to WA the Issue 212 */ 213 214 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 215 if (use_semaphore) { 216 for (i = 0; i < adev->usec_timeout; i++) { 217 /* a read return value of 1 means semaphore acuqire */ 218 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 219 hub->eng_distance * eng); 220 if (tmp & 0x1) 221 break; 222 udelay(1); 223 } 224 225 if (i >= adev->usec_timeout) 226 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 227 } 228 229 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 230 231 /* 232 * Issue a dummy read to wait for the ACK register to be cleared 233 * to avoid a false ACK due to the new fast GRBM interface. 234 */ 235 if (vmhub == AMDGPU_GFXHUB_0) 236 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); 237 238 /* Wait for ACK with a delay.*/ 239 for (i = 0; i < adev->usec_timeout; i++) { 240 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 241 hub->eng_distance * eng); 242 tmp &= 1 << vmid; 243 if (tmp) 244 break; 245 246 udelay(1); 247 } 248 249 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 250 if (use_semaphore) 251 /* 252 * add semaphore release after invalidation, 253 * write with 0 means semaphore release 254 */ 255 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 256 hub->eng_distance * eng, 0); 257 258 spin_unlock(&adev->gmc.invalidate_lock); 259 260 if (i < adev->usec_timeout) 261 return; 262 263 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 264 } 265 266 /** 267 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 268 * 269 * @adev: amdgpu_device pointer 270 * @vmid: vm instance to flush 271 * 272 * Flush the TLB for the requested page table. 273 */ 274 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 275 uint32_t vmhub, uint32_t flush_type) 276 { 277 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 278 struct dma_fence *fence; 279 struct amdgpu_job *job; 280 281 int r; 282 283 /* flush hdp cache */ 284 adev->nbio.funcs->hdp_flush(adev, NULL); 285 286 /* For SRIOV run time, driver shouldn't access the register through MMIO 287 * Directly use kiq to do the vm invalidation instead 288 */ 289 if (adev->gfx.kiq.ring.sched.ready && 290 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 291 down_read_trylock(&adev->reset_sem)) { 292 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 293 const unsigned eng = 17; 294 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 295 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 296 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 297 298 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 299 1 << vmid); 300 301 up_read(&adev->reset_sem); 302 return; 303 } 304 305 mutex_lock(&adev->mman.gtt_window_lock); 306 307 if (vmhub == AMDGPU_MMHUB_0) { 308 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 309 mutex_unlock(&adev->mman.gtt_window_lock); 310 return; 311 } 312 313 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 314 315 if (!adev->mman.buffer_funcs_enabled || 316 !adev->ib_pool_ready || 317 amdgpu_in_reset(adev) || 318 ring->sched.ready == false) { 319 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 320 mutex_unlock(&adev->mman.gtt_window_lock); 321 return; 322 } 323 324 /* The SDMA on Navi has a bug which can theoretically result in memory 325 * corruption if an invalidation happens at the same time as an VA 326 * translation. Avoid this by doing the invalidation from the SDMA 327 * itself. 328 */ 329 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 330 &job); 331 if (r) 332 goto error_alloc; 333 334 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 335 job->vm_needs_flush = true; 336 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 337 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 338 r = amdgpu_job_submit(job, &adev->mman.entity, 339 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 340 if (r) 341 goto error_submit; 342 343 mutex_unlock(&adev->mman.gtt_window_lock); 344 345 dma_fence_wait(fence, false); 346 dma_fence_put(fence); 347 348 return; 349 350 error_submit: 351 amdgpu_job_free(job); 352 353 error_alloc: 354 mutex_unlock(&adev->mman.gtt_window_lock); 355 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 356 } 357 358 /** 359 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 360 * 361 * @adev: amdgpu_device pointer 362 * @pasid: pasid to be flush 363 * 364 * Flush the TLB for the requested pasid. 365 */ 366 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 367 uint16_t pasid, uint32_t flush_type, 368 bool all_hub) 369 { 370 int vmid, i; 371 signed long r; 372 uint32_t seq; 373 uint16_t queried_pasid; 374 bool ret; 375 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 376 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 377 378 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 379 spin_lock(&adev->gfx.kiq.ring_lock); 380 /* 2 dwords flush + 8 dwords fence */ 381 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 382 kiq->pmf->kiq_invalidate_tlbs(ring, 383 pasid, flush_type, all_hub); 384 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 385 if (r) { 386 amdgpu_ring_undo(ring); 387 spin_unlock(&adev->gfx.kiq.ring_lock); 388 return -ETIME; 389 } 390 391 amdgpu_ring_commit(ring); 392 spin_unlock(&adev->gfx.kiq.ring_lock); 393 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 394 if (r < 1) { 395 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 396 return -ETIME; 397 } 398 399 return 0; 400 } 401 402 for (vmid = 1; vmid < 16; vmid++) { 403 404 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 405 &queried_pasid); 406 if (ret && queried_pasid == pasid) { 407 if (all_hub) { 408 for (i = 0; i < adev->num_vmhubs; i++) 409 gmc_v10_0_flush_gpu_tlb(adev, vmid, 410 i, flush_type); 411 } else { 412 gmc_v10_0_flush_gpu_tlb(adev, vmid, 413 AMDGPU_GFXHUB_0, flush_type); 414 } 415 break; 416 } 417 } 418 419 return 0; 420 } 421 422 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 423 unsigned vmid, uint64_t pd_addr) 424 { 425 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 426 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 427 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 428 unsigned eng = ring->vm_inv_eng; 429 430 /* 431 * It may lose gpuvm invalidate acknowldege state across power-gating 432 * off cycle, add semaphore acquire before invalidation and semaphore 433 * release after invalidation to avoid entering power gated state 434 * to WA the Issue 435 */ 436 437 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 438 if (use_semaphore) 439 /* a read return value of 1 means semaphore acuqire */ 440 amdgpu_ring_emit_reg_wait(ring, 441 hub->vm_inv_eng0_sem + 442 hub->eng_distance * eng, 0x1, 0x1); 443 444 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 445 (hub->ctx_addr_distance * vmid), 446 lower_32_bits(pd_addr)); 447 448 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 449 (hub->ctx_addr_distance * vmid), 450 upper_32_bits(pd_addr)); 451 452 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 453 hub->eng_distance * eng, 454 hub->vm_inv_eng0_ack + 455 hub->eng_distance * eng, 456 req, 1 << vmid); 457 458 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 459 if (use_semaphore) 460 /* 461 * add semaphore release after invalidation, 462 * write with 0 means semaphore release 463 */ 464 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 465 hub->eng_distance * eng, 0); 466 467 return pd_addr; 468 } 469 470 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 471 unsigned pasid) 472 { 473 struct amdgpu_device *adev = ring->adev; 474 uint32_t reg; 475 476 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 477 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 478 else 479 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 480 481 amdgpu_ring_emit_wreg(ring, reg, pasid); 482 } 483 484 /* 485 * PTE format on NAVI 10: 486 * 63:59 reserved 487 * 58:57 reserved 488 * 56 F 489 * 55 L 490 * 54 reserved 491 * 53:52 SW 492 * 51 T 493 * 50:48 mtype 494 * 47:12 4k physical page base address 495 * 11:7 fragment 496 * 6 write 497 * 5 read 498 * 4 exe 499 * 3 Z 500 * 2 snooped 501 * 1 system 502 * 0 valid 503 * 504 * PDE format on NAVI 10: 505 * 63:59 block fragment size 506 * 58:55 reserved 507 * 54 P 508 * 53:48 reserved 509 * 47:6 physical base address of PD or PTE 510 * 5:3 reserved 511 * 2 C 512 * 1 system 513 * 0 valid 514 */ 515 516 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 517 { 518 switch (flags) { 519 case AMDGPU_VM_MTYPE_DEFAULT: 520 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 521 case AMDGPU_VM_MTYPE_NC: 522 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 523 case AMDGPU_VM_MTYPE_WC: 524 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 525 case AMDGPU_VM_MTYPE_CC: 526 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 527 case AMDGPU_VM_MTYPE_UC: 528 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 529 default: 530 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 531 } 532 } 533 534 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 535 uint64_t *addr, uint64_t *flags) 536 { 537 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 538 *addr = adev->vm_manager.vram_base_offset + *addr - 539 adev->gmc.vram_start; 540 BUG_ON(*addr & 0xFFFF00000000003FULL); 541 542 if (!adev->gmc.translate_further) 543 return; 544 545 if (level == AMDGPU_VM_PDB1) { 546 /* Set the block fragment size */ 547 if (!(*flags & AMDGPU_PDE_PTE)) 548 *flags |= AMDGPU_PDE_BFS(0x9); 549 550 } else if (level == AMDGPU_VM_PDB0) { 551 if (*flags & AMDGPU_PDE_PTE) 552 *flags &= ~AMDGPU_PDE_PTE; 553 else 554 *flags |= AMDGPU_PTE_TF; 555 } 556 } 557 558 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 559 struct amdgpu_bo_va_mapping *mapping, 560 uint64_t *flags) 561 { 562 *flags &= ~AMDGPU_PTE_EXECUTABLE; 563 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 564 565 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 566 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 567 568 if (mapping->flags & AMDGPU_PTE_PRT) { 569 *flags |= AMDGPU_PTE_PRT; 570 *flags |= AMDGPU_PTE_SNOOPED; 571 *flags |= AMDGPU_PTE_LOG; 572 *flags |= AMDGPU_PTE_SYSTEM; 573 *flags &= ~AMDGPU_PTE_VALID; 574 } 575 } 576 577 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 578 { 579 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 580 unsigned size; 581 582 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 583 size = AMDGPU_VBIOS_VGA_ALLOCATION; 584 } else { 585 u32 viewport; 586 u32 pitch; 587 588 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 589 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 590 size = (REG_GET_FIELD(viewport, 591 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 592 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 593 4); 594 } 595 596 return size; 597 } 598 599 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 600 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 601 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 602 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 603 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 604 .map_mtype = gmc_v10_0_map_mtype, 605 .get_vm_pde = gmc_v10_0_get_vm_pde, 606 .get_vm_pte = gmc_v10_0_get_vm_pte, 607 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 608 }; 609 610 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 611 { 612 if (adev->gmc.gmc_funcs == NULL) 613 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 614 } 615 616 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 617 { 618 switch (adev->asic_type) { 619 case CHIP_SIENNA_CICHLID: 620 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 621 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 622 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 623 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 624 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 625 adev->umc.funcs = &umc_v8_7_funcs; 626 break; 627 default: 628 break; 629 } 630 } 631 632 633 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 634 { 635 switch (adev->asic_type) { 636 case CHIP_VANGOGH: 637 adev->mmhub.funcs = &mmhub_v2_3_funcs; 638 break; 639 default: 640 adev->mmhub.funcs = &mmhub_v2_0_funcs; 641 break; 642 } 643 } 644 645 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 646 { 647 switch (adev->asic_type) { 648 case CHIP_SIENNA_CICHLID: 649 case CHIP_NAVY_FLOUNDER: 650 case CHIP_VANGOGH: 651 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 652 break; 653 default: 654 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 655 break; 656 } 657 } 658 659 660 static int gmc_v10_0_early_init(void *handle) 661 { 662 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 663 664 gmc_v10_0_set_mmhub_funcs(adev); 665 gmc_v10_0_set_gfxhub_funcs(adev); 666 gmc_v10_0_set_gmc_funcs(adev); 667 gmc_v10_0_set_irq_funcs(adev); 668 gmc_v10_0_set_umc_funcs(adev); 669 670 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 671 adev->gmc.shared_aperture_end = 672 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 673 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 674 adev->gmc.private_aperture_end = 675 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 676 677 return 0; 678 } 679 680 static int gmc_v10_0_late_init(void *handle) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 int r; 684 685 amdgpu_bo_late_init(adev); 686 687 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 688 if (r) 689 return r; 690 691 r = amdgpu_gmc_ras_late_init(adev); 692 if (r) 693 return r; 694 695 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 696 } 697 698 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 699 struct amdgpu_gmc *mc) 700 { 701 u64 base = 0; 702 703 base = adev->gfxhub.funcs->get_fb_location(adev); 704 705 /* add the xgmi offset of the physical node */ 706 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 707 708 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 709 amdgpu_gmc_gart_location(adev, mc); 710 711 /* base offset of vram pages */ 712 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 713 714 /* add the xgmi offset of the physical node */ 715 adev->vm_manager.vram_base_offset += 716 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 717 } 718 719 /** 720 * gmc_v10_0_mc_init - initialize the memory controller driver params 721 * 722 * @adev: amdgpu_device pointer 723 * 724 * Look up the amount of vram, vram width, and decide how to place 725 * vram and gart within the GPU's physical address space. 726 * Returns 0 for success. 727 */ 728 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 729 { 730 int r; 731 732 /* size in MB on si */ 733 adev->gmc.mc_vram_size = 734 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 735 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 736 737 if (!(adev->flags & AMD_IS_APU)) { 738 r = amdgpu_device_resize_fb_bar(adev); 739 if (r) 740 return r; 741 } 742 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 743 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 744 745 #ifdef CONFIG_X86_64 746 if (adev->flags & AMD_IS_APU) { 747 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 748 adev->gmc.aper_size = adev->gmc.real_vram_size; 749 } 750 #endif 751 752 /* In case the PCI BAR is larger than the actual amount of vram */ 753 adev->gmc.visible_vram_size = adev->gmc.aper_size; 754 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 755 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 756 757 /* set the gart size */ 758 if (amdgpu_gart_size == -1) { 759 switch (adev->asic_type) { 760 case CHIP_NAVI10: 761 case CHIP_NAVI14: 762 case CHIP_NAVI12: 763 case CHIP_SIENNA_CICHLID: 764 case CHIP_NAVY_FLOUNDER: 765 case CHIP_VANGOGH: 766 default: 767 adev->gmc.gart_size = 512ULL << 20; 768 break; 769 } 770 } else 771 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 772 773 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 774 775 return 0; 776 } 777 778 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 779 { 780 int r; 781 782 if (adev->gart.bo) { 783 WARN(1, "NAVI10 PCIE GART already initialized\n"); 784 return 0; 785 } 786 787 /* Initialize common gart structure */ 788 r = amdgpu_gart_init(adev); 789 if (r) 790 return r; 791 792 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 793 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 794 AMDGPU_PTE_EXECUTABLE; 795 796 return amdgpu_gart_table_vram_alloc(adev); 797 } 798 799 static int gmc_v10_0_sw_init(void *handle) 800 { 801 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 803 804 adev->gfxhub.funcs->init(adev); 805 806 adev->mmhub.funcs->init(adev); 807 808 spin_lock_init(&adev->gmc.invalidate_lock); 809 810 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 811 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 812 adev->gmc.vram_width = 64; 813 } else if (amdgpu_emu_mode == 1) { 814 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 815 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 816 } else { 817 r = amdgpu_atomfirmware_get_vram_info(adev, 818 &vram_width, &vram_type, &vram_vendor); 819 adev->gmc.vram_width = vram_width; 820 821 adev->gmc.vram_type = vram_type; 822 adev->gmc.vram_vendor = vram_vendor; 823 } 824 825 switch (adev->asic_type) { 826 case CHIP_NAVI10: 827 case CHIP_NAVI14: 828 case CHIP_NAVI12: 829 case CHIP_SIENNA_CICHLID: 830 case CHIP_NAVY_FLOUNDER: 831 case CHIP_VANGOGH: 832 adev->num_vmhubs = 2; 833 /* 834 * To fulfill 4-level page support, 835 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 836 * block size 512 (9bit) 837 */ 838 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 839 break; 840 default: 841 break; 842 } 843 844 /* This interrupt is VMC page fault.*/ 845 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 846 VMC_1_0__SRCID__VM_FAULT, 847 &adev->gmc.vm_fault); 848 849 if (r) 850 return r; 851 852 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 853 UTCL2_1_0__SRCID__FAULT, 854 &adev->gmc.vm_fault); 855 if (r) 856 return r; 857 858 if (!amdgpu_sriov_vf(adev)) { 859 /* interrupt sent to DF. */ 860 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 861 &adev->gmc.ecc_irq); 862 if (r) 863 return r; 864 } 865 866 /* 867 * Set the internal MC address mask This is the max address of the GPU's 868 * internal address space. 869 */ 870 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 871 872 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 873 if (r) { 874 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 875 return r; 876 } 877 878 if (adev->gmc.xgmi.supported) { 879 r = adev->gfxhub.funcs->get_xgmi_info(adev); 880 if (r) 881 return r; 882 } 883 884 r = gmc_v10_0_mc_init(adev); 885 if (r) 886 return r; 887 888 amdgpu_gmc_get_vbios_allocations(adev); 889 890 /* Memory manager */ 891 r = amdgpu_bo_init(adev); 892 if (r) 893 return r; 894 895 r = gmc_v10_0_gart_init(adev); 896 if (r) 897 return r; 898 899 /* 900 * number of VMs 901 * VMID 0 is reserved for System 902 * amdgpu graphics/compute will use VMIDs 1-7 903 * amdkfd will use VMIDs 8-15 904 */ 905 adev->vm_manager.first_kfd_vmid = 8; 906 907 amdgpu_vm_manager_init(adev); 908 909 return 0; 910 } 911 912 /** 913 * gmc_v8_0_gart_fini - vm fini callback 914 * 915 * @adev: amdgpu_device pointer 916 * 917 * Tears down the driver GART/VM setup (CIK). 918 */ 919 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 920 { 921 amdgpu_gart_table_vram_free(adev); 922 amdgpu_gart_fini(adev); 923 } 924 925 static int gmc_v10_0_sw_fini(void *handle) 926 { 927 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 928 929 amdgpu_vm_manager_fini(adev); 930 gmc_v10_0_gart_fini(adev); 931 amdgpu_gem_force_release(adev); 932 amdgpu_bo_fini(adev); 933 934 return 0; 935 } 936 937 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 938 { 939 switch (adev->asic_type) { 940 case CHIP_NAVI10: 941 case CHIP_NAVI14: 942 case CHIP_NAVI12: 943 case CHIP_SIENNA_CICHLID: 944 case CHIP_NAVY_FLOUNDER: 945 case CHIP_VANGOGH: 946 break; 947 default: 948 break; 949 } 950 } 951 952 /** 953 * gmc_v10_0_gart_enable - gart enable 954 * 955 * @adev: amdgpu_device pointer 956 */ 957 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 958 { 959 int r; 960 bool value; 961 u32 tmp; 962 963 if (adev->gart.bo == NULL) { 964 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 965 return -EINVAL; 966 } 967 968 r = amdgpu_gart_table_vram_pin(adev); 969 if (r) 970 return r; 971 972 r = adev->gfxhub.funcs->gart_enable(adev); 973 if (r) 974 return r; 975 976 r = adev->mmhub.funcs->gart_enable(adev); 977 if (r) 978 return r; 979 980 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 981 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 982 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 983 984 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 985 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 986 987 /* Flush HDP after it is initialized */ 988 adev->nbio.funcs->hdp_flush(adev, NULL); 989 990 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 991 false : true; 992 993 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 994 adev->mmhub.funcs->set_fault_enable_default(adev, value); 995 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 996 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 997 998 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 999 (unsigned)(adev->gmc.gart_size >> 20), 1000 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1001 1002 adev->gart.ready = true; 1003 1004 return 0; 1005 } 1006 1007 static int gmc_v10_0_hw_init(void *handle) 1008 { 1009 int r; 1010 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1011 1012 /* The sequence of these two function calls matters.*/ 1013 gmc_v10_0_init_golden_registers(adev); 1014 1015 r = gmc_v10_0_gart_enable(adev); 1016 if (r) 1017 return r; 1018 1019 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1020 adev->umc.funcs->init_registers(adev); 1021 1022 return 0; 1023 } 1024 1025 /** 1026 * gmc_v10_0_gart_disable - gart disable 1027 * 1028 * @adev: amdgpu_device pointer 1029 * 1030 * This disables all VM page table. 1031 */ 1032 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1033 { 1034 adev->gfxhub.funcs->gart_disable(adev); 1035 adev->mmhub.funcs->gart_disable(adev); 1036 amdgpu_gart_table_vram_unpin(adev); 1037 } 1038 1039 static int gmc_v10_0_hw_fini(void *handle) 1040 { 1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1042 1043 if (amdgpu_sriov_vf(adev)) { 1044 /* full access mode, so don't touch any GMC register */ 1045 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1046 return 0; 1047 } 1048 1049 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1050 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1051 gmc_v10_0_gart_disable(adev); 1052 1053 return 0; 1054 } 1055 1056 static int gmc_v10_0_suspend(void *handle) 1057 { 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 gmc_v10_0_hw_fini(adev); 1061 1062 return 0; 1063 } 1064 1065 static int gmc_v10_0_resume(void *handle) 1066 { 1067 int r; 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1069 1070 r = gmc_v10_0_hw_init(adev); 1071 if (r) 1072 return r; 1073 1074 amdgpu_vmid_reset_all(adev); 1075 1076 return 0; 1077 } 1078 1079 static bool gmc_v10_0_is_idle(void *handle) 1080 { 1081 /* MC is always ready in GMC v10.*/ 1082 return true; 1083 } 1084 1085 static int gmc_v10_0_wait_for_idle(void *handle) 1086 { 1087 /* There is no need to wait for MC idle in GMC v10.*/ 1088 return 0; 1089 } 1090 1091 static int gmc_v10_0_soft_reset(void *handle) 1092 { 1093 return 0; 1094 } 1095 1096 static int gmc_v10_0_set_clockgating_state(void *handle, 1097 enum amd_clockgating_state state) 1098 { 1099 int r; 1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1101 1102 r = adev->mmhub.funcs->set_clockgating(adev, state); 1103 if (r) 1104 return r; 1105 1106 if (adev->asic_type == CHIP_SIENNA_CICHLID || 1107 adev->asic_type == CHIP_NAVY_FLOUNDER) 1108 return athub_v2_1_set_clockgating(adev, state); 1109 else 1110 return athub_v2_0_set_clockgating(adev, state); 1111 } 1112 1113 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1114 { 1115 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1116 1117 adev->mmhub.funcs->get_clockgating(adev, flags); 1118 1119 if (adev->asic_type == CHIP_SIENNA_CICHLID || 1120 adev->asic_type == CHIP_NAVY_FLOUNDER) 1121 athub_v2_1_get_clockgating(adev, flags); 1122 else 1123 athub_v2_0_get_clockgating(adev, flags); 1124 } 1125 1126 static int gmc_v10_0_set_powergating_state(void *handle, 1127 enum amd_powergating_state state) 1128 { 1129 return 0; 1130 } 1131 1132 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1133 .name = "gmc_v10_0", 1134 .early_init = gmc_v10_0_early_init, 1135 .late_init = gmc_v10_0_late_init, 1136 .sw_init = gmc_v10_0_sw_init, 1137 .sw_fini = gmc_v10_0_sw_fini, 1138 .hw_init = gmc_v10_0_hw_init, 1139 .hw_fini = gmc_v10_0_hw_fini, 1140 .suspend = gmc_v10_0_suspend, 1141 .resume = gmc_v10_0_resume, 1142 .is_idle = gmc_v10_0_is_idle, 1143 .wait_for_idle = gmc_v10_0_wait_for_idle, 1144 .soft_reset = gmc_v10_0_soft_reset, 1145 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1146 .set_powergating_state = gmc_v10_0_set_powergating_state, 1147 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1148 }; 1149 1150 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1151 { 1152 .type = AMD_IP_BLOCK_TYPE_GMC, 1153 .major = 10, 1154 .minor = 0, 1155 .rev = 0, 1156 .funcs = &gmc_v10_0_ip_funcs, 1157 }; 1158