1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 #include "umc_v8_7.h" 29 30 #include "hdp/hdp_5_0_0_offset.h" 31 #include "hdp/hdp_5_0_0_sh_mask.h" 32 #include "athub/athub_2_0_0_sh_mask.h" 33 #include "athub/athub_2_0_0_offset.h" 34 #include "dcn/dcn_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_sh_mask.h" 36 #include "oss/osssys_5_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 40 #include "soc15.h" 41 #include "soc15d.h" 42 #include "soc15_common.h" 43 44 #include "nbio_v2_3.h" 45 46 #include "gfxhub_v2_0.h" 47 #include "gfxhub_v2_1.h" 48 #include "mmhub_v2_0.h" 49 #include "mmhub_v2_3.h" 50 #include "athub_v2_0.h" 51 #include "athub_v2_1.h" 52 53 #if 0 54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 55 { 56 /* TODO add golden setting for hdp */ 57 }; 58 #endif 59 60 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 61 struct amdgpu_irq_src *src, 62 unsigned type, 63 enum amdgpu_interrupt_state state) 64 { 65 return 0; 66 } 67 68 static int 69 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 70 struct amdgpu_irq_src *src, unsigned type, 71 enum amdgpu_interrupt_state state) 72 { 73 switch (state) { 74 case AMDGPU_IRQ_STATE_DISABLE: 75 /* MM HUB */ 76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 77 /* GFX HUB */ 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 83 /* GFX HUB */ 84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 85 break; 86 default: 87 break; 88 } 89 90 return 0; 91 } 92 93 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 94 struct amdgpu_irq_src *source, 95 struct amdgpu_iv_entry *entry) 96 { 97 bool retry_fault = !!(entry->src_data[1] & 0x80); 98 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 99 struct amdgpu_task_info task_info; 100 uint32_t status = 0; 101 u64 addr; 102 103 addr = (u64)entry->src_data[0] << 12; 104 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 105 106 if (retry_fault) { 107 /* Returning 1 here also prevents sending the IV to the KFD */ 108 109 /* Process it onyl if it's the first fault for this address */ 110 if (entry->ih != &adev->irq.ih_soft && 111 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 112 entry->timestamp)) 113 return 1; 114 115 /* Delegate it to a different ring if the hardware hasn't 116 * already done it. 117 */ 118 if (in_interrupt()) { 119 amdgpu_irq_delegate(adev, entry, 8); 120 return 1; 121 } 122 123 /* Try to handle the recoverable page faults by filling page 124 * tables 125 */ 126 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 127 return 1; 128 } 129 130 if (!amdgpu_sriov_vf(adev)) { 131 /* 132 * Issue a dummy read to wait for the status register to 133 * be updated to avoid reading an incorrect value due to 134 * the new fast GRBM interface. 135 */ 136 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 137 (adev->asic_type < CHIP_SIENNA_CICHLID)) 138 RREG32(hub->vm_l2_pro_fault_status); 139 140 status = RREG32(hub->vm_l2_pro_fault_status); 141 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 142 } 143 144 if (!printk_ratelimit()) 145 return 0; 146 147 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 148 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 149 150 dev_err(adev->dev, 151 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 152 "for process %s pid %d thread %s pid %d)\n", 153 entry->vmid_src ? "mmhub" : "gfxhub", 154 entry->src_id, entry->ring_id, entry->vmid, 155 entry->pasid, task_info.process_name, task_info.tgid, 156 task_info.task_name, task_info.pid); 157 dev_err(adev->dev, " in page starting at address 0x%012llx from client %d\n", 158 addr, entry->client_id); 159 160 if (!amdgpu_sriov_vf(adev)) 161 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 162 status); 163 164 return 0; 165 } 166 167 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 168 .set = gmc_v10_0_vm_fault_interrupt_state, 169 .process = gmc_v10_0_process_interrupt, 170 }; 171 172 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 173 .set = gmc_v10_0_ecc_interrupt_state, 174 .process = amdgpu_umc_process_ecc_irq, 175 }; 176 177 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 178 { 179 adev->gmc.vm_fault.num_types = 1; 180 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 181 182 if (!amdgpu_sriov_vf(adev)) { 183 adev->gmc.ecc_irq.num_types = 1; 184 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 185 } 186 } 187 188 /** 189 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 190 * 191 * @adev: amdgpu_device pointer 192 * @vmhub: vmhub type 193 * 194 */ 195 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 196 uint32_t vmhub) 197 { 198 return ((vmhub == AMDGPU_MMHUB_0 || 199 vmhub == AMDGPU_MMHUB_1) && 200 (!amdgpu_sriov_vf(adev))); 201 } 202 203 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 204 struct amdgpu_device *adev, 205 uint8_t vmid, uint16_t *p_pasid) 206 { 207 uint32_t value; 208 209 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 210 + vmid); 211 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 212 213 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 214 } 215 216 /* 217 * GART 218 * VMID 0 is the physical GPU addresses as used by the kernel. 219 * VMIDs 1-15 are used for userspace clients and are handled 220 * by the amdgpu vm/hsa code. 221 */ 222 223 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 224 unsigned int vmhub, uint32_t flush_type) 225 { 226 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 227 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 228 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 229 u32 tmp; 230 /* Use register 17 for GART */ 231 const unsigned eng = 17; 232 unsigned int i; 233 234 spin_lock(&adev->gmc.invalidate_lock); 235 /* 236 * It may lose gpuvm invalidate acknowldege state across power-gating 237 * off cycle, add semaphore acquire before invalidation and semaphore 238 * release after invalidation to avoid entering power gated state 239 * to WA the Issue 240 */ 241 242 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 243 if (use_semaphore) { 244 for (i = 0; i < adev->usec_timeout; i++) { 245 /* a read return value of 1 means semaphore acuqire */ 246 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 247 hub->eng_distance * eng); 248 if (tmp & 0x1) 249 break; 250 udelay(1); 251 } 252 253 if (i >= adev->usec_timeout) 254 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 255 } 256 257 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 258 259 /* 260 * Issue a dummy read to wait for the ACK register to be cleared 261 * to avoid a false ACK due to the new fast GRBM interface. 262 */ 263 if ((vmhub == AMDGPU_GFXHUB_0) && 264 (adev->asic_type < CHIP_SIENNA_CICHLID)) 265 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); 266 267 /* Wait for ACK with a delay.*/ 268 for (i = 0; i < adev->usec_timeout; i++) { 269 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 270 hub->eng_distance * eng); 271 tmp &= 1 << vmid; 272 if (tmp) 273 break; 274 275 udelay(1); 276 } 277 278 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 279 if (use_semaphore) 280 /* 281 * add semaphore release after invalidation, 282 * write with 0 means semaphore release 283 */ 284 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 285 hub->eng_distance * eng, 0); 286 287 spin_unlock(&adev->gmc.invalidate_lock); 288 289 if (i < adev->usec_timeout) 290 return; 291 292 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 293 } 294 295 /** 296 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 297 * 298 * @adev: amdgpu_device pointer 299 * @vmid: vm instance to flush 300 * 301 * Flush the TLB for the requested page table. 302 */ 303 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 304 uint32_t vmhub, uint32_t flush_type) 305 { 306 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 307 struct dma_fence *fence; 308 struct amdgpu_job *job; 309 310 int r; 311 312 /* flush hdp cache */ 313 adev->nbio.funcs->hdp_flush(adev, NULL); 314 315 /* For SRIOV run time, driver shouldn't access the register through MMIO 316 * Directly use kiq to do the vm invalidation instead 317 */ 318 if (adev->gfx.kiq.ring.sched.ready && 319 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 320 down_read_trylock(&adev->reset_sem)) { 321 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 322 const unsigned eng = 17; 323 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 324 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 325 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 326 327 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 328 1 << vmid); 329 330 up_read(&adev->reset_sem); 331 return; 332 } 333 334 mutex_lock(&adev->mman.gtt_window_lock); 335 336 if (vmhub == AMDGPU_MMHUB_0) { 337 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 338 mutex_unlock(&adev->mman.gtt_window_lock); 339 return; 340 } 341 342 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 343 344 if (!adev->mman.buffer_funcs_enabled || 345 !adev->ib_pool_ready || 346 amdgpu_in_reset(adev) || 347 ring->sched.ready == false) { 348 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 349 mutex_unlock(&adev->mman.gtt_window_lock); 350 return; 351 } 352 353 /* The SDMA on Navi has a bug which can theoretically result in memory 354 * corruption if an invalidation happens at the same time as an VA 355 * translation. Avoid this by doing the invalidation from the SDMA 356 * itself. 357 */ 358 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 359 &job); 360 if (r) 361 goto error_alloc; 362 363 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 364 job->vm_needs_flush = true; 365 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 366 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 367 r = amdgpu_job_submit(job, &adev->mman.entity, 368 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 369 if (r) 370 goto error_submit; 371 372 mutex_unlock(&adev->mman.gtt_window_lock); 373 374 dma_fence_wait(fence, false); 375 dma_fence_put(fence); 376 377 return; 378 379 error_submit: 380 amdgpu_job_free(job); 381 382 error_alloc: 383 mutex_unlock(&adev->mman.gtt_window_lock); 384 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 385 } 386 387 /** 388 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 389 * 390 * @adev: amdgpu_device pointer 391 * @pasid: pasid to be flush 392 * 393 * Flush the TLB for the requested pasid. 394 */ 395 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 396 uint16_t pasid, uint32_t flush_type, 397 bool all_hub) 398 { 399 int vmid, i; 400 signed long r; 401 uint32_t seq; 402 uint16_t queried_pasid; 403 bool ret; 404 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 405 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 406 407 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 408 spin_lock(&adev->gfx.kiq.ring_lock); 409 /* 2 dwords flush + 8 dwords fence */ 410 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 411 kiq->pmf->kiq_invalidate_tlbs(ring, 412 pasid, flush_type, all_hub); 413 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 414 if (r) { 415 amdgpu_ring_undo(ring); 416 spin_unlock(&adev->gfx.kiq.ring_lock); 417 return -ETIME; 418 } 419 420 amdgpu_ring_commit(ring); 421 spin_unlock(&adev->gfx.kiq.ring_lock); 422 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 423 if (r < 1) { 424 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 425 return -ETIME; 426 } 427 428 return 0; 429 } 430 431 for (vmid = 1; vmid < 16; vmid++) { 432 433 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 434 &queried_pasid); 435 if (ret && queried_pasid == pasid) { 436 if (all_hub) { 437 for (i = 0; i < adev->num_vmhubs; i++) 438 gmc_v10_0_flush_gpu_tlb(adev, vmid, 439 i, flush_type); 440 } else { 441 gmc_v10_0_flush_gpu_tlb(adev, vmid, 442 AMDGPU_GFXHUB_0, flush_type); 443 } 444 break; 445 } 446 } 447 448 return 0; 449 } 450 451 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 452 unsigned vmid, uint64_t pd_addr) 453 { 454 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 455 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 456 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 457 unsigned eng = ring->vm_inv_eng; 458 459 /* 460 * It may lose gpuvm invalidate acknowldege state across power-gating 461 * off cycle, add semaphore acquire before invalidation and semaphore 462 * release after invalidation to avoid entering power gated state 463 * to WA the Issue 464 */ 465 466 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 467 if (use_semaphore) 468 /* a read return value of 1 means semaphore acuqire */ 469 amdgpu_ring_emit_reg_wait(ring, 470 hub->vm_inv_eng0_sem + 471 hub->eng_distance * eng, 0x1, 0x1); 472 473 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 474 (hub->ctx_addr_distance * vmid), 475 lower_32_bits(pd_addr)); 476 477 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 478 (hub->ctx_addr_distance * vmid), 479 upper_32_bits(pd_addr)); 480 481 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 482 hub->eng_distance * eng, 483 hub->vm_inv_eng0_ack + 484 hub->eng_distance * eng, 485 req, 1 << vmid); 486 487 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 488 if (use_semaphore) 489 /* 490 * add semaphore release after invalidation, 491 * write with 0 means semaphore release 492 */ 493 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 494 hub->eng_distance * eng, 0); 495 496 return pd_addr; 497 } 498 499 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 500 unsigned pasid) 501 { 502 struct amdgpu_device *adev = ring->adev; 503 uint32_t reg; 504 505 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 506 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 507 else 508 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 509 510 amdgpu_ring_emit_wreg(ring, reg, pasid); 511 } 512 513 /* 514 * PTE format on NAVI 10: 515 * 63:59 reserved 516 * 58 reserved and for sienna_cichlid is used for MALL noalloc 517 * 57 reserved 518 * 56 F 519 * 55 L 520 * 54 reserved 521 * 53:52 SW 522 * 51 T 523 * 50:48 mtype 524 * 47:12 4k physical page base address 525 * 11:7 fragment 526 * 6 write 527 * 5 read 528 * 4 exe 529 * 3 Z 530 * 2 snooped 531 * 1 system 532 * 0 valid 533 * 534 * PDE format on NAVI 10: 535 * 63:59 block fragment size 536 * 58:55 reserved 537 * 54 P 538 * 53:48 reserved 539 * 47:6 physical base address of PD or PTE 540 * 5:3 reserved 541 * 2 C 542 * 1 system 543 * 0 valid 544 */ 545 546 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 547 { 548 switch (flags) { 549 case AMDGPU_VM_MTYPE_DEFAULT: 550 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 551 case AMDGPU_VM_MTYPE_NC: 552 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 553 case AMDGPU_VM_MTYPE_WC: 554 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 555 case AMDGPU_VM_MTYPE_CC: 556 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 557 case AMDGPU_VM_MTYPE_UC: 558 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 559 default: 560 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 561 } 562 } 563 564 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 565 uint64_t *addr, uint64_t *flags) 566 { 567 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 568 *addr = adev->vm_manager.vram_base_offset + *addr - 569 adev->gmc.vram_start; 570 BUG_ON(*addr & 0xFFFF00000000003FULL); 571 572 if (!adev->gmc.translate_further) 573 return; 574 575 if (level == AMDGPU_VM_PDB1) { 576 /* Set the block fragment size */ 577 if (!(*flags & AMDGPU_PDE_PTE)) 578 *flags |= AMDGPU_PDE_BFS(0x9); 579 580 } else if (level == AMDGPU_VM_PDB0) { 581 if (*flags & AMDGPU_PDE_PTE) 582 *flags &= ~AMDGPU_PDE_PTE; 583 else 584 *flags |= AMDGPU_PTE_TF; 585 } 586 } 587 588 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 589 struct amdgpu_bo_va_mapping *mapping, 590 uint64_t *flags) 591 { 592 *flags &= ~AMDGPU_PTE_EXECUTABLE; 593 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 594 595 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 596 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 597 598 if (mapping->flags & AMDGPU_PTE_PRT) { 599 *flags |= AMDGPU_PTE_PRT; 600 *flags |= AMDGPU_PTE_SNOOPED; 601 *flags |= AMDGPU_PTE_LOG; 602 *flags |= AMDGPU_PTE_SYSTEM; 603 *flags &= ~AMDGPU_PTE_VALID; 604 } 605 } 606 607 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 608 { 609 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 610 unsigned size; 611 612 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 613 size = AMDGPU_VBIOS_VGA_ALLOCATION; 614 } else { 615 u32 viewport; 616 u32 pitch; 617 618 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 619 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 620 size = (REG_GET_FIELD(viewport, 621 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 622 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 623 4); 624 } 625 626 return size; 627 } 628 629 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 630 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 631 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 632 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 633 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 634 .map_mtype = gmc_v10_0_map_mtype, 635 .get_vm_pde = gmc_v10_0_get_vm_pde, 636 .get_vm_pte = gmc_v10_0_get_vm_pte, 637 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 638 }; 639 640 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 641 { 642 if (adev->gmc.gmc_funcs == NULL) 643 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 644 } 645 646 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 647 { 648 switch (adev->asic_type) { 649 case CHIP_SIENNA_CICHLID: 650 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 651 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 652 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 653 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 654 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 655 adev->umc.funcs = &umc_v8_7_funcs; 656 break; 657 default: 658 break; 659 } 660 } 661 662 663 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 664 { 665 switch (adev->asic_type) { 666 case CHIP_VANGOGH: 667 adev->mmhub.funcs = &mmhub_v2_3_funcs; 668 break; 669 default: 670 adev->mmhub.funcs = &mmhub_v2_0_funcs; 671 break; 672 } 673 } 674 675 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 676 { 677 switch (adev->asic_type) { 678 case CHIP_SIENNA_CICHLID: 679 case CHIP_NAVY_FLOUNDER: 680 case CHIP_VANGOGH: 681 case CHIP_DIMGREY_CAVEFISH: 682 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 683 break; 684 default: 685 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 686 break; 687 } 688 } 689 690 691 static int gmc_v10_0_early_init(void *handle) 692 { 693 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 694 695 gmc_v10_0_set_mmhub_funcs(adev); 696 gmc_v10_0_set_gfxhub_funcs(adev); 697 gmc_v10_0_set_gmc_funcs(adev); 698 gmc_v10_0_set_irq_funcs(adev); 699 gmc_v10_0_set_umc_funcs(adev); 700 701 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 702 adev->gmc.shared_aperture_end = 703 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 704 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 705 adev->gmc.private_aperture_end = 706 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 707 708 return 0; 709 } 710 711 static int gmc_v10_0_late_init(void *handle) 712 { 713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 714 int r; 715 716 amdgpu_bo_late_init(adev); 717 718 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 719 if (r) 720 return r; 721 722 r = amdgpu_gmc_ras_late_init(adev); 723 if (r) 724 return r; 725 726 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 727 } 728 729 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 730 struct amdgpu_gmc *mc) 731 { 732 u64 base = 0; 733 734 base = adev->gfxhub.funcs->get_fb_location(adev); 735 736 /* add the xgmi offset of the physical node */ 737 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 738 739 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 740 amdgpu_gmc_gart_location(adev, mc); 741 742 /* base offset of vram pages */ 743 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 744 745 /* add the xgmi offset of the physical node */ 746 adev->vm_manager.vram_base_offset += 747 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 748 } 749 750 /** 751 * gmc_v10_0_mc_init - initialize the memory controller driver params 752 * 753 * @adev: amdgpu_device pointer 754 * 755 * Look up the amount of vram, vram width, and decide how to place 756 * vram and gart within the GPU's physical address space. 757 * Returns 0 for success. 758 */ 759 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 760 { 761 int r; 762 763 /* size in MB on si */ 764 adev->gmc.mc_vram_size = 765 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 766 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 767 768 if (!(adev->flags & AMD_IS_APU)) { 769 r = amdgpu_device_resize_fb_bar(adev); 770 if (r) 771 return r; 772 } 773 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 774 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 775 776 #ifdef CONFIG_X86_64 777 if (adev->flags & AMD_IS_APU) { 778 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 779 adev->gmc.aper_size = adev->gmc.real_vram_size; 780 } 781 #endif 782 783 /* In case the PCI BAR is larger than the actual amount of vram */ 784 adev->gmc.visible_vram_size = adev->gmc.aper_size; 785 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 786 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 787 788 /* set the gart size */ 789 if (amdgpu_gart_size == -1) { 790 switch (adev->asic_type) { 791 case CHIP_NAVI10: 792 case CHIP_NAVI14: 793 case CHIP_NAVI12: 794 case CHIP_SIENNA_CICHLID: 795 case CHIP_NAVY_FLOUNDER: 796 case CHIP_VANGOGH: 797 case CHIP_DIMGREY_CAVEFISH: 798 default: 799 adev->gmc.gart_size = 512ULL << 20; 800 break; 801 } 802 } else 803 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 804 805 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 806 807 return 0; 808 } 809 810 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 811 { 812 int r; 813 814 if (adev->gart.bo) { 815 WARN(1, "NAVI10 PCIE GART already initialized\n"); 816 return 0; 817 } 818 819 /* Initialize common gart structure */ 820 r = amdgpu_gart_init(adev); 821 if (r) 822 return r; 823 824 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 825 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 826 AMDGPU_PTE_EXECUTABLE; 827 828 return amdgpu_gart_table_vram_alloc(adev); 829 } 830 831 static int gmc_v10_0_sw_init(void *handle) 832 { 833 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 835 836 adev->gfxhub.funcs->init(adev); 837 838 adev->mmhub.funcs->init(adev); 839 840 spin_lock_init(&adev->gmc.invalidate_lock); 841 842 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 843 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 844 adev->gmc.vram_width = 64; 845 } else if (amdgpu_emu_mode == 1) { 846 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 847 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 848 } else { 849 r = amdgpu_atomfirmware_get_vram_info(adev, 850 &vram_width, &vram_type, &vram_vendor); 851 adev->gmc.vram_width = vram_width; 852 853 adev->gmc.vram_type = vram_type; 854 adev->gmc.vram_vendor = vram_vendor; 855 } 856 857 switch (adev->asic_type) { 858 case CHIP_NAVI10: 859 case CHIP_NAVI14: 860 case CHIP_NAVI12: 861 case CHIP_SIENNA_CICHLID: 862 case CHIP_NAVY_FLOUNDER: 863 case CHIP_VANGOGH: 864 case CHIP_DIMGREY_CAVEFISH: 865 adev->num_vmhubs = 2; 866 /* 867 * To fulfill 4-level page support, 868 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 869 * block size 512 (9bit) 870 */ 871 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 872 break; 873 default: 874 break; 875 } 876 877 /* This interrupt is VMC page fault.*/ 878 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 879 VMC_1_0__SRCID__VM_FAULT, 880 &adev->gmc.vm_fault); 881 882 if (r) 883 return r; 884 885 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 886 UTCL2_1_0__SRCID__FAULT, 887 &adev->gmc.vm_fault); 888 if (r) 889 return r; 890 891 if (!amdgpu_sriov_vf(adev)) { 892 /* interrupt sent to DF. */ 893 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 894 &adev->gmc.ecc_irq); 895 if (r) 896 return r; 897 } 898 899 /* 900 * Set the internal MC address mask This is the max address of the GPU's 901 * internal address space. 902 */ 903 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 904 905 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 906 if (r) { 907 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 908 return r; 909 } 910 911 if (adev->gmc.xgmi.supported) { 912 r = adev->gfxhub.funcs->get_xgmi_info(adev); 913 if (r) 914 return r; 915 } 916 917 r = gmc_v10_0_mc_init(adev); 918 if (r) 919 return r; 920 921 amdgpu_gmc_get_vbios_allocations(adev); 922 923 /* Memory manager */ 924 r = amdgpu_bo_init(adev); 925 if (r) 926 return r; 927 928 r = gmc_v10_0_gart_init(adev); 929 if (r) 930 return r; 931 932 /* 933 * number of VMs 934 * VMID 0 is reserved for System 935 * amdgpu graphics/compute will use VMIDs 1-7 936 * amdkfd will use VMIDs 8-15 937 */ 938 adev->vm_manager.first_kfd_vmid = 8; 939 940 amdgpu_vm_manager_init(adev); 941 942 return 0; 943 } 944 945 /** 946 * gmc_v8_0_gart_fini - vm fini callback 947 * 948 * @adev: amdgpu_device pointer 949 * 950 * Tears down the driver GART/VM setup (CIK). 951 */ 952 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 953 { 954 amdgpu_gart_table_vram_free(adev); 955 amdgpu_gart_fini(adev); 956 } 957 958 static int gmc_v10_0_sw_fini(void *handle) 959 { 960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 962 amdgpu_vm_manager_fini(adev); 963 gmc_v10_0_gart_fini(adev); 964 amdgpu_gem_force_release(adev); 965 amdgpu_bo_fini(adev); 966 967 return 0; 968 } 969 970 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 971 { 972 switch (adev->asic_type) { 973 case CHIP_NAVI10: 974 case CHIP_NAVI14: 975 case CHIP_NAVI12: 976 case CHIP_SIENNA_CICHLID: 977 case CHIP_NAVY_FLOUNDER: 978 case CHIP_VANGOGH: 979 case CHIP_DIMGREY_CAVEFISH: 980 break; 981 default: 982 break; 983 } 984 } 985 986 /** 987 * gmc_v10_0_gart_enable - gart enable 988 * 989 * @adev: amdgpu_device pointer 990 */ 991 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 992 { 993 int r; 994 bool value; 995 u32 tmp; 996 997 if (adev->gart.bo == NULL) { 998 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 999 return -EINVAL; 1000 } 1001 1002 r = amdgpu_gart_table_vram_pin(adev); 1003 if (r) 1004 return r; 1005 1006 r = adev->gfxhub.funcs->gart_enable(adev); 1007 if (r) 1008 return r; 1009 1010 r = adev->mmhub.funcs->gart_enable(adev); 1011 if (r) 1012 return r; 1013 1014 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 1015 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 1016 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 1017 1018 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1019 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1020 1021 /* Flush HDP after it is initialized */ 1022 adev->nbio.funcs->hdp_flush(adev, NULL); 1023 1024 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1025 false : true; 1026 1027 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1028 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1029 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1030 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1031 1032 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1033 (unsigned)(adev->gmc.gart_size >> 20), 1034 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1035 1036 adev->gart.ready = true; 1037 1038 return 0; 1039 } 1040 1041 static int gmc_v10_0_hw_init(void *handle) 1042 { 1043 int r; 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 1046 /* The sequence of these two function calls matters.*/ 1047 gmc_v10_0_init_golden_registers(adev); 1048 1049 r = gmc_v10_0_gart_enable(adev); 1050 if (r) 1051 return r; 1052 1053 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1054 adev->umc.funcs->init_registers(adev); 1055 1056 return 0; 1057 } 1058 1059 /** 1060 * gmc_v10_0_gart_disable - gart disable 1061 * 1062 * @adev: amdgpu_device pointer 1063 * 1064 * This disables all VM page table. 1065 */ 1066 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1067 { 1068 adev->gfxhub.funcs->gart_disable(adev); 1069 adev->mmhub.funcs->gart_disable(adev); 1070 amdgpu_gart_table_vram_unpin(adev); 1071 } 1072 1073 static int gmc_v10_0_hw_fini(void *handle) 1074 { 1075 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1076 1077 if (amdgpu_sriov_vf(adev)) { 1078 /* full access mode, so don't touch any GMC register */ 1079 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1080 return 0; 1081 } 1082 1083 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1084 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1085 gmc_v10_0_gart_disable(adev); 1086 1087 return 0; 1088 } 1089 1090 static int gmc_v10_0_suspend(void *handle) 1091 { 1092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1093 1094 gmc_v10_0_hw_fini(adev); 1095 1096 return 0; 1097 } 1098 1099 static int gmc_v10_0_resume(void *handle) 1100 { 1101 int r; 1102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1103 1104 r = gmc_v10_0_hw_init(adev); 1105 if (r) 1106 return r; 1107 1108 amdgpu_vmid_reset_all(adev); 1109 1110 return 0; 1111 } 1112 1113 static bool gmc_v10_0_is_idle(void *handle) 1114 { 1115 /* MC is always ready in GMC v10.*/ 1116 return true; 1117 } 1118 1119 static int gmc_v10_0_wait_for_idle(void *handle) 1120 { 1121 /* There is no need to wait for MC idle in GMC v10.*/ 1122 return 0; 1123 } 1124 1125 static int gmc_v10_0_soft_reset(void *handle) 1126 { 1127 return 0; 1128 } 1129 1130 static int gmc_v10_0_set_clockgating_state(void *handle, 1131 enum amd_clockgating_state state) 1132 { 1133 int r; 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 r = adev->mmhub.funcs->set_clockgating(adev, state); 1137 if (r) 1138 return r; 1139 1140 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1141 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1142 return athub_v2_1_set_clockgating(adev, state); 1143 else 1144 return athub_v2_0_set_clockgating(adev, state); 1145 } 1146 1147 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1148 { 1149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1150 1151 adev->mmhub.funcs->get_clockgating(adev, flags); 1152 1153 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1154 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1155 athub_v2_1_get_clockgating(adev, flags); 1156 else 1157 athub_v2_0_get_clockgating(adev, flags); 1158 } 1159 1160 static int gmc_v10_0_set_powergating_state(void *handle, 1161 enum amd_powergating_state state) 1162 { 1163 return 0; 1164 } 1165 1166 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1167 .name = "gmc_v10_0", 1168 .early_init = gmc_v10_0_early_init, 1169 .late_init = gmc_v10_0_late_init, 1170 .sw_init = gmc_v10_0_sw_init, 1171 .sw_fini = gmc_v10_0_sw_fini, 1172 .hw_init = gmc_v10_0_hw_init, 1173 .hw_fini = gmc_v10_0_hw_fini, 1174 .suspend = gmc_v10_0_suspend, 1175 .resume = gmc_v10_0_resume, 1176 .is_idle = gmc_v10_0_is_idle, 1177 .wait_for_idle = gmc_v10_0_wait_for_idle, 1178 .soft_reset = gmc_v10_0_soft_reset, 1179 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1180 .set_powergating_state = gmc_v10_0_set_powergating_state, 1181 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1182 }; 1183 1184 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1185 { 1186 .type = AMD_IP_BLOCK_TYPE_GMC, 1187 .major = 10, 1188 .minor = 0, 1189 .rev = 0, 1190 .funcs = &gmc_v10_0_ip_funcs, 1191 }; 1192