1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 #include "amdgpu_reset.h" 55 56 #if 0 57 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 58 { 59 /* TODO add golden setting for hdp */ 60 }; 61 #endif 62 63 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, 65 unsigned type, 66 enum amdgpu_interrupt_state state) 67 { 68 return 0; 69 } 70 71 static int 72 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 73 struct amdgpu_irq_src *src, unsigned type, 74 enum amdgpu_interrupt_state state) 75 { 76 switch (state) { 77 case AMDGPU_IRQ_STATE_DISABLE: 78 /* MM HUB */ 79 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 80 /* GFX HUB */ 81 /* This works because this interrupt is only 82 * enabled at init/resume and disabled in 83 * fini/suspend, so the overall state doesn't 84 * change over the course of suspend/resume. 85 */ 86 if (!adev->in_s0ix) 87 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 88 break; 89 case AMDGPU_IRQ_STATE_ENABLE: 90 /* MM HUB */ 91 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 92 /* GFX HUB */ 93 /* This works because this interrupt is only 94 * enabled at init/resume and disabled in 95 * fini/suspend, so the overall state doesn't 96 * change over the course of suspend/resume. 97 */ 98 if (!adev->in_s0ix) 99 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 100 break; 101 default: 102 break; 103 } 104 105 return 0; 106 } 107 108 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 109 struct amdgpu_irq_src *source, 110 struct amdgpu_iv_entry *entry) 111 { 112 bool retry_fault = !!(entry->src_data[1] & 0x80); 113 bool write_fault = !!(entry->src_data[1] & 0x20); 114 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 115 struct amdgpu_task_info task_info; 116 uint32_t status = 0; 117 u64 addr; 118 119 addr = (u64)entry->src_data[0] << 12; 120 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 121 122 if (retry_fault) { 123 /* Returning 1 here also prevents sending the IV to the KFD */ 124 125 /* Process it onyl if it's the first fault for this address */ 126 if (entry->ih != &adev->irq.ih_soft && 127 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 128 entry->timestamp)) 129 return 1; 130 131 /* Delegate it to a different ring if the hardware hasn't 132 * already done it. 133 */ 134 if (entry->ih == &adev->irq.ih) { 135 amdgpu_irq_delegate(adev, entry, 8); 136 return 1; 137 } 138 139 /* Try to handle the recoverable page faults by filling page 140 * tables 141 */ 142 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 143 return 1; 144 } 145 146 if (!amdgpu_sriov_vf(adev)) { 147 /* 148 * Issue a dummy read to wait for the status register to 149 * be updated to avoid reading an incorrect value due to 150 * the new fast GRBM interface. 151 */ 152 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 153 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 154 RREG32(hub->vm_l2_pro_fault_status); 155 156 status = RREG32(hub->vm_l2_pro_fault_status); 157 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 158 } 159 160 if (!printk_ratelimit()) 161 return 0; 162 163 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 164 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 165 166 dev_err(adev->dev, 167 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 168 "for process %s pid %d thread %s pid %d)\n", 169 entry->vmid_src ? "mmhub" : "gfxhub", 170 entry->src_id, entry->ring_id, entry->vmid, 171 entry->pasid, task_info.process_name, task_info.tgid, 172 task_info.task_name, task_info.pid); 173 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 174 addr, entry->client_id, 175 soc15_ih_clientid_name[entry->client_id]); 176 177 if (!amdgpu_sriov_vf(adev)) 178 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 179 status); 180 181 return 0; 182 } 183 184 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 185 .set = gmc_v10_0_vm_fault_interrupt_state, 186 .process = gmc_v10_0_process_interrupt, 187 }; 188 189 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 190 .set = gmc_v10_0_ecc_interrupt_state, 191 .process = amdgpu_umc_process_ecc_irq, 192 }; 193 194 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 195 { 196 adev->gmc.vm_fault.num_types = 1; 197 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 198 199 if (!amdgpu_sriov_vf(adev)) { 200 adev->gmc.ecc_irq.num_types = 1; 201 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 202 } 203 } 204 205 /** 206 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 207 * 208 * @adev: amdgpu_device pointer 209 * @vmhub: vmhub type 210 * 211 */ 212 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 213 uint32_t vmhub) 214 { 215 return ((vmhub == AMDGPU_MMHUB_0 || 216 vmhub == AMDGPU_MMHUB_1) && 217 (!amdgpu_sriov_vf(adev))); 218 } 219 220 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 221 struct amdgpu_device *adev, 222 uint8_t vmid, uint16_t *p_pasid) 223 { 224 uint32_t value; 225 226 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 227 + vmid); 228 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 229 230 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 231 } 232 233 /* 234 * GART 235 * VMID 0 is the physical GPU addresses as used by the kernel. 236 * VMIDs 1-15 are used for userspace clients and are handled 237 * by the amdgpu vm/hsa code. 238 */ 239 240 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 241 unsigned int vmhub, uint32_t flush_type) 242 { 243 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 244 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 245 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 246 u32 tmp; 247 /* Use register 17 for GART */ 248 const unsigned eng = 17; 249 unsigned int i; 250 unsigned char hub_ip = 0; 251 252 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ? 253 GC_HWIP : MMHUB_HWIP; 254 255 spin_lock(&adev->gmc.invalidate_lock); 256 /* 257 * It may lose gpuvm invalidate acknowldege state across power-gating 258 * off cycle, add semaphore acquire before invalidation and semaphore 259 * release after invalidation to avoid entering power gated state 260 * to WA the Issue 261 */ 262 263 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 264 if (use_semaphore) { 265 for (i = 0; i < adev->usec_timeout; i++) { 266 /* a read return value of 1 means semaphore acuqire */ 267 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 268 hub->eng_distance * eng, hub_ip); 269 270 if (tmp & 0x1) 271 break; 272 udelay(1); 273 } 274 275 if (i >= adev->usec_timeout) 276 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 277 } 278 279 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 280 hub->eng_distance * eng, 281 inv_req, hub_ip); 282 283 /* 284 * Issue a dummy read to wait for the ACK register to be cleared 285 * to avoid a false ACK due to the new fast GRBM interface. 286 */ 287 if ((vmhub == AMDGPU_GFXHUB_0) && 288 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) 289 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 290 hub->eng_distance * eng, hub_ip); 291 292 /* Wait for ACK with a delay.*/ 293 for (i = 0; i < adev->usec_timeout; i++) { 294 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 295 hub->eng_distance * eng, hub_ip); 296 297 tmp &= 1 << vmid; 298 if (tmp) 299 break; 300 301 udelay(1); 302 } 303 304 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 305 if (use_semaphore) 306 /* 307 * add semaphore release after invalidation, 308 * write with 0 means semaphore release 309 */ 310 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 311 hub->eng_distance * eng, 0, hub_ip); 312 313 spin_unlock(&adev->gmc.invalidate_lock); 314 315 if (i < adev->usec_timeout) 316 return; 317 318 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); 319 } 320 321 /** 322 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 323 * 324 * @adev: amdgpu_device pointer 325 * @vmid: vm instance to flush 326 * @vmhub: vmhub type 327 * @flush_type: the flush type 328 * 329 * Flush the TLB for the requested page table. 330 */ 331 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 332 uint32_t vmhub, uint32_t flush_type) 333 { 334 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 335 struct dma_fence *fence; 336 struct amdgpu_job *job; 337 338 int r; 339 340 /* flush hdp cache */ 341 adev->hdp.funcs->flush_hdp(adev, NULL); 342 343 /* For SRIOV run time, driver shouldn't access the register through MMIO 344 * Directly use kiq to do the vm invalidation instead 345 */ 346 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 347 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 348 down_read_trylock(&adev->reset_domain->sem)) { 349 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 350 const unsigned eng = 17; 351 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 352 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 353 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 354 355 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 356 1 << vmid); 357 358 up_read(&adev->reset_domain->sem); 359 return; 360 } 361 362 mutex_lock(&adev->mman.gtt_window_lock); 363 364 if (vmhub == AMDGPU_MMHUB_0) { 365 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 366 mutex_unlock(&adev->mman.gtt_window_lock); 367 return; 368 } 369 370 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 371 372 if (!adev->mman.buffer_funcs_enabled || 373 !adev->ib_pool_ready || 374 amdgpu_in_reset(adev) || 375 ring->sched.ready == false) { 376 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 377 mutex_unlock(&adev->mman.gtt_window_lock); 378 return; 379 } 380 381 /* The SDMA on Navi has a bug which can theoretically result in memory 382 * corruption if an invalidation happens at the same time as an VA 383 * translation. Avoid this by doing the invalidation from the SDMA 384 * itself. 385 */ 386 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.entity, 387 AMDGPU_FENCE_OWNER_UNDEFINED, 388 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 389 &job); 390 if (r) 391 goto error_alloc; 392 393 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 394 job->vm_needs_flush = true; 395 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 396 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 397 fence = amdgpu_job_submit(job); 398 399 mutex_unlock(&adev->mman.gtt_window_lock); 400 401 dma_fence_wait(fence, false); 402 dma_fence_put(fence); 403 404 return; 405 406 error_alloc: 407 mutex_unlock(&adev->mman.gtt_window_lock); 408 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 409 } 410 411 /** 412 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 413 * 414 * @adev: amdgpu_device pointer 415 * @pasid: pasid to be flush 416 * @flush_type: the flush type 417 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 418 * 419 * Flush the TLB for the requested pasid. 420 */ 421 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 422 uint16_t pasid, uint32_t flush_type, 423 bool all_hub) 424 { 425 int vmid, i; 426 signed long r; 427 uint32_t seq; 428 uint16_t queried_pasid; 429 bool ret; 430 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 431 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 432 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 433 434 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 435 spin_lock(&adev->gfx.kiq.ring_lock); 436 /* 2 dwords flush + 8 dwords fence */ 437 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 438 kiq->pmf->kiq_invalidate_tlbs(ring, 439 pasid, flush_type, all_hub); 440 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 441 if (r) { 442 amdgpu_ring_undo(ring); 443 spin_unlock(&adev->gfx.kiq.ring_lock); 444 return -ETIME; 445 } 446 447 amdgpu_ring_commit(ring); 448 spin_unlock(&adev->gfx.kiq.ring_lock); 449 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 450 if (r < 1) { 451 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 452 return -ETIME; 453 } 454 455 return 0; 456 } 457 458 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 459 460 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 461 &queried_pasid); 462 if (ret && queried_pasid == pasid) { 463 if (all_hub) { 464 for (i = 0; i < adev->num_vmhubs; i++) 465 gmc_v10_0_flush_gpu_tlb(adev, vmid, 466 i, flush_type); 467 } else { 468 gmc_v10_0_flush_gpu_tlb(adev, vmid, 469 AMDGPU_GFXHUB_0, flush_type); 470 } 471 if (!adev->enable_mes) 472 break; 473 } 474 } 475 476 return 0; 477 } 478 479 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 480 unsigned vmid, uint64_t pd_addr) 481 { 482 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 483 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 484 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 485 unsigned eng = ring->vm_inv_eng; 486 487 /* 488 * It may lose gpuvm invalidate acknowldege state across power-gating 489 * off cycle, add semaphore acquire before invalidation and semaphore 490 * release after invalidation to avoid entering power gated state 491 * to WA the Issue 492 */ 493 494 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 495 if (use_semaphore) 496 /* a read return value of 1 means semaphore acuqire */ 497 amdgpu_ring_emit_reg_wait(ring, 498 hub->vm_inv_eng0_sem + 499 hub->eng_distance * eng, 0x1, 0x1); 500 501 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 502 (hub->ctx_addr_distance * vmid), 503 lower_32_bits(pd_addr)); 504 505 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 506 (hub->ctx_addr_distance * vmid), 507 upper_32_bits(pd_addr)); 508 509 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 510 hub->eng_distance * eng, 511 hub->vm_inv_eng0_ack + 512 hub->eng_distance * eng, 513 req, 1 << vmid); 514 515 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 516 if (use_semaphore) 517 /* 518 * add semaphore release after invalidation, 519 * write with 0 means semaphore release 520 */ 521 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 522 hub->eng_distance * eng, 0); 523 524 return pd_addr; 525 } 526 527 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 528 unsigned pasid) 529 { 530 struct amdgpu_device *adev = ring->adev; 531 uint32_t reg; 532 533 /* MES fw manages IH_VMID_x_LUT updating */ 534 if (ring->is_mes_queue) 535 return; 536 537 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 538 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 539 else 540 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 541 542 amdgpu_ring_emit_wreg(ring, reg, pasid); 543 } 544 545 /* 546 * PTE format on NAVI 10: 547 * 63:59 reserved 548 * 58 reserved and for sienna_cichlid is used for MALL noalloc 549 * 57 reserved 550 * 56 F 551 * 55 L 552 * 54 reserved 553 * 53:52 SW 554 * 51 T 555 * 50:48 mtype 556 * 47:12 4k physical page base address 557 * 11:7 fragment 558 * 6 write 559 * 5 read 560 * 4 exe 561 * 3 Z 562 * 2 snooped 563 * 1 system 564 * 0 valid 565 * 566 * PDE format on NAVI 10: 567 * 63:59 block fragment size 568 * 58:55 reserved 569 * 54 P 570 * 53:48 reserved 571 * 47:6 physical base address of PD or PTE 572 * 5:3 reserved 573 * 2 C 574 * 1 system 575 * 0 valid 576 */ 577 578 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 579 { 580 switch (flags) { 581 case AMDGPU_VM_MTYPE_DEFAULT: 582 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 583 case AMDGPU_VM_MTYPE_NC: 584 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 585 case AMDGPU_VM_MTYPE_WC: 586 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 587 case AMDGPU_VM_MTYPE_CC: 588 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 589 case AMDGPU_VM_MTYPE_UC: 590 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 591 default: 592 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 593 } 594 } 595 596 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 597 uint64_t *addr, uint64_t *flags) 598 { 599 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 600 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 601 BUG_ON(*addr & 0xFFFF00000000003FULL); 602 603 if (!adev->gmc.translate_further) 604 return; 605 606 if (level == AMDGPU_VM_PDB1) { 607 /* Set the block fragment size */ 608 if (!(*flags & AMDGPU_PDE_PTE)) 609 *flags |= AMDGPU_PDE_BFS(0x9); 610 611 } else if (level == AMDGPU_VM_PDB0) { 612 if (*flags & AMDGPU_PDE_PTE) 613 *flags &= ~AMDGPU_PDE_PTE; 614 else 615 *flags |= AMDGPU_PTE_TF; 616 } 617 } 618 619 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 620 struct amdgpu_bo_va_mapping *mapping, 621 uint64_t *flags) 622 { 623 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 624 625 *flags &= ~AMDGPU_PTE_EXECUTABLE; 626 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 627 628 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 629 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 630 631 *flags &= ~AMDGPU_PTE_NOALLOC; 632 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 633 634 if (mapping->flags & AMDGPU_PTE_PRT) { 635 *flags |= AMDGPU_PTE_PRT; 636 *flags |= AMDGPU_PTE_SNOOPED; 637 *flags |= AMDGPU_PTE_LOG; 638 *flags |= AMDGPU_PTE_SYSTEM; 639 *flags &= ~AMDGPU_PTE_VALID; 640 } 641 642 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 643 AMDGPU_GEM_CREATE_UNCACHED)) 644 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 645 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 646 } 647 648 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 649 { 650 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 651 unsigned size; 652 653 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 654 size = AMDGPU_VBIOS_VGA_ALLOCATION; 655 } else { 656 u32 viewport; 657 u32 pitch; 658 659 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 660 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 661 size = (REG_GET_FIELD(viewport, 662 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 663 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 664 4); 665 } 666 667 return size; 668 } 669 670 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 671 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 672 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 673 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 674 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 675 .map_mtype = gmc_v10_0_map_mtype, 676 .get_vm_pde = gmc_v10_0_get_vm_pde, 677 .get_vm_pte = gmc_v10_0_get_vm_pte, 678 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 679 }; 680 681 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 682 { 683 if (adev->gmc.gmc_funcs == NULL) 684 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 685 } 686 687 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 688 { 689 switch (adev->ip_versions[UMC_HWIP][0]) { 690 case IP_VERSION(8, 7, 0): 691 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 692 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 693 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 694 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 695 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 696 adev->umc.ras = &umc_v8_7_ras; 697 break; 698 default: 699 break; 700 } 701 if (adev->umc.ras) { 702 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); 703 704 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); 705 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; 706 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 707 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; 708 709 /* If don't define special ras_late_init function, use default ras_late_init */ 710 if (!adev->umc.ras->ras_block.ras_late_init) 711 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; 712 713 /* If not defined special ras_cb function, use default ras_cb */ 714 if (!adev->umc.ras->ras_block.ras_cb) 715 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; 716 } 717 } 718 719 720 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 721 { 722 switch (adev->ip_versions[MMHUB_HWIP][0]) { 723 case IP_VERSION(2, 3, 0): 724 case IP_VERSION(2, 4, 0): 725 case IP_VERSION(2, 4, 1): 726 adev->mmhub.funcs = &mmhub_v2_3_funcs; 727 break; 728 default: 729 adev->mmhub.funcs = &mmhub_v2_0_funcs; 730 break; 731 } 732 } 733 734 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 735 { 736 switch (adev->ip_versions[GC_HWIP][0]) { 737 case IP_VERSION(10, 3, 0): 738 case IP_VERSION(10, 3, 2): 739 case IP_VERSION(10, 3, 1): 740 case IP_VERSION(10, 3, 4): 741 case IP_VERSION(10, 3, 5): 742 case IP_VERSION(10, 3, 6): 743 case IP_VERSION(10, 3, 3): 744 case IP_VERSION(10, 3, 7): 745 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 746 break; 747 default: 748 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 749 break; 750 } 751 } 752 753 754 static int gmc_v10_0_early_init(void *handle) 755 { 756 int r; 757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758 759 gmc_v10_0_set_mmhub_funcs(adev); 760 gmc_v10_0_set_gfxhub_funcs(adev); 761 gmc_v10_0_set_gmc_funcs(adev); 762 gmc_v10_0_set_irq_funcs(adev); 763 gmc_v10_0_set_umc_funcs(adev); 764 765 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 766 adev->gmc.shared_aperture_end = 767 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 768 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 769 adev->gmc.private_aperture_end = 770 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 771 772 r = amdgpu_gmc_ras_early_init(adev); 773 if (r) 774 return r; 775 776 return 0; 777 } 778 779 static int gmc_v10_0_late_init(void *handle) 780 { 781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 782 int r; 783 784 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 785 if (r) 786 return r; 787 788 r = amdgpu_gmc_ras_late_init(adev); 789 if (r) 790 return r; 791 792 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 793 } 794 795 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 796 struct amdgpu_gmc *mc) 797 { 798 u64 base = 0; 799 800 base = adev->gfxhub.funcs->get_fb_location(adev); 801 802 /* add the xgmi offset of the physical node */ 803 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 804 805 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 806 amdgpu_gmc_gart_location(adev, mc); 807 amdgpu_gmc_agp_location(adev, mc); 808 809 /* base offset of vram pages */ 810 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 811 812 /* add the xgmi offset of the physical node */ 813 adev->vm_manager.vram_base_offset += 814 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 815 } 816 817 /** 818 * gmc_v10_0_mc_init - initialize the memory controller driver params 819 * 820 * @adev: amdgpu_device pointer 821 * 822 * Look up the amount of vram, vram width, and decide how to place 823 * vram and gart within the GPU's physical address space. 824 * Returns 0 for success. 825 */ 826 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 827 { 828 int r; 829 830 /* size in MB on si */ 831 adev->gmc.mc_vram_size = 832 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 833 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 834 835 if (!(adev->flags & AMD_IS_APU)) { 836 r = amdgpu_device_resize_fb_bar(adev); 837 if (r) 838 return r; 839 } 840 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 841 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 842 843 #ifdef CONFIG_X86_64 844 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 845 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 846 adev->gmc.aper_size = adev->gmc.real_vram_size; 847 } 848 #endif 849 850 adev->gmc.visible_vram_size = adev->gmc.aper_size; 851 852 /* set the gart size */ 853 if (amdgpu_gart_size == -1) { 854 switch (adev->ip_versions[GC_HWIP][0]) { 855 default: 856 adev->gmc.gart_size = 512ULL << 20; 857 break; 858 case IP_VERSION(10, 3, 1): /* DCE SG support */ 859 case IP_VERSION(10, 3, 3): /* DCE SG support */ 860 case IP_VERSION(10, 3, 6): /* DCE SG support */ 861 case IP_VERSION(10, 3, 7): /* DCE SG support */ 862 adev->gmc.gart_size = 1024ULL << 20; 863 break; 864 } 865 } else { 866 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 867 } 868 869 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 870 871 return 0; 872 } 873 874 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 875 { 876 int r; 877 878 if (adev->gart.bo) { 879 WARN(1, "NAVI10 PCIE GART already initialized\n"); 880 return 0; 881 } 882 883 /* Initialize common gart structure */ 884 r = amdgpu_gart_init(adev); 885 if (r) 886 return r; 887 888 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 889 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 890 AMDGPU_PTE_EXECUTABLE; 891 892 return amdgpu_gart_table_vram_alloc(adev); 893 } 894 895 static int gmc_v10_0_sw_init(void *handle) 896 { 897 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 899 900 adev->gfxhub.funcs->init(adev); 901 902 adev->mmhub.funcs->init(adev); 903 904 spin_lock_init(&adev->gmc.invalidate_lock); 905 906 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 907 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 908 adev->gmc.vram_width = 64; 909 } else if (amdgpu_emu_mode == 1) { 910 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 911 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 912 } else { 913 r = amdgpu_atomfirmware_get_vram_info(adev, 914 &vram_width, &vram_type, &vram_vendor); 915 adev->gmc.vram_width = vram_width; 916 917 adev->gmc.vram_type = vram_type; 918 adev->gmc.vram_vendor = vram_vendor; 919 } 920 921 switch (adev->ip_versions[GC_HWIP][0]) { 922 case IP_VERSION(10, 3, 0): 923 adev->gmc.mall_size = 128 * 1024 * 1024; 924 break; 925 case IP_VERSION(10, 3, 2): 926 adev->gmc.mall_size = 96 * 1024 * 1024; 927 break; 928 case IP_VERSION(10, 3, 4): 929 adev->gmc.mall_size = 32 * 1024 * 1024; 930 break; 931 case IP_VERSION(10, 3, 5): 932 adev->gmc.mall_size = 16 * 1024 * 1024; 933 break; 934 default: 935 adev->gmc.mall_size = 0; 936 break; 937 } 938 939 switch (adev->ip_versions[GC_HWIP][0]) { 940 case IP_VERSION(10, 1, 10): 941 case IP_VERSION(10, 1, 1): 942 case IP_VERSION(10, 1, 2): 943 case IP_VERSION(10, 1, 3): 944 case IP_VERSION(10, 1, 4): 945 case IP_VERSION(10, 3, 0): 946 case IP_VERSION(10, 3, 2): 947 case IP_VERSION(10, 3, 1): 948 case IP_VERSION(10, 3, 4): 949 case IP_VERSION(10, 3, 5): 950 case IP_VERSION(10, 3, 6): 951 case IP_VERSION(10, 3, 3): 952 case IP_VERSION(10, 3, 7): 953 adev->num_vmhubs = 2; 954 /* 955 * To fulfill 4-level page support, 956 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 957 * block size 512 (9bit) 958 */ 959 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 960 break; 961 default: 962 break; 963 } 964 965 /* This interrupt is VMC page fault.*/ 966 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 967 VMC_1_0__SRCID__VM_FAULT, 968 &adev->gmc.vm_fault); 969 970 if (r) 971 return r; 972 973 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 974 UTCL2_1_0__SRCID__FAULT, 975 &adev->gmc.vm_fault); 976 if (r) 977 return r; 978 979 if (!amdgpu_sriov_vf(adev)) { 980 /* interrupt sent to DF. */ 981 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 982 &adev->gmc.ecc_irq); 983 if (r) 984 return r; 985 } 986 987 /* 988 * Set the internal MC address mask This is the max address of the GPU's 989 * internal address space. 990 */ 991 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 992 993 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 994 if (r) { 995 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 996 return r; 997 } 998 999 adev->need_swiotlb = drm_need_swiotlb(44); 1000 1001 r = gmc_v10_0_mc_init(adev); 1002 if (r) 1003 return r; 1004 1005 amdgpu_gmc_get_vbios_allocations(adev); 1006 1007 /* Memory manager */ 1008 r = amdgpu_bo_init(adev); 1009 if (r) 1010 return r; 1011 1012 r = gmc_v10_0_gart_init(adev); 1013 if (r) 1014 return r; 1015 1016 /* 1017 * number of VMs 1018 * VMID 0 is reserved for System 1019 * amdgpu graphics/compute will use VMIDs 1-7 1020 * amdkfd will use VMIDs 8-15 1021 */ 1022 adev->vm_manager.first_kfd_vmid = 8; 1023 1024 amdgpu_vm_manager_init(adev); 1025 1026 return 0; 1027 } 1028 1029 /** 1030 * gmc_v10_0_gart_fini - vm fini callback 1031 * 1032 * @adev: amdgpu_device pointer 1033 * 1034 * Tears down the driver GART/VM setup (CIK). 1035 */ 1036 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 1037 { 1038 amdgpu_gart_table_vram_free(adev); 1039 } 1040 1041 static int gmc_v10_0_sw_fini(void *handle) 1042 { 1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1044 1045 amdgpu_vm_manager_fini(adev); 1046 gmc_v10_0_gart_fini(adev); 1047 amdgpu_gem_force_release(adev); 1048 amdgpu_bo_fini(adev); 1049 1050 return 0; 1051 } 1052 1053 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 1054 { 1055 } 1056 1057 /** 1058 * gmc_v10_0_gart_enable - gart enable 1059 * 1060 * @adev: amdgpu_device pointer 1061 */ 1062 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 1063 { 1064 int r; 1065 bool value; 1066 1067 if (adev->gart.bo == NULL) { 1068 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1069 return -EINVAL; 1070 } 1071 1072 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1073 1074 if (!adev->in_s0ix) { 1075 r = adev->gfxhub.funcs->gart_enable(adev); 1076 if (r) 1077 return r; 1078 } 1079 1080 r = adev->mmhub.funcs->gart_enable(adev); 1081 if (r) 1082 return r; 1083 1084 adev->hdp.funcs->init_registers(adev); 1085 1086 /* Flush HDP after it is initialized */ 1087 adev->hdp.funcs->flush_hdp(adev, NULL); 1088 1089 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1090 false : true; 1091 1092 if (!adev->in_s0ix) 1093 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1094 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1095 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1096 if (!adev->in_s0ix) 1097 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1098 1099 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1100 (unsigned)(adev->gmc.gart_size >> 20), 1101 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1102 1103 return 0; 1104 } 1105 1106 static int gmc_v10_0_hw_init(void *handle) 1107 { 1108 int r; 1109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1110 1111 /* The sequence of these two function calls matters.*/ 1112 gmc_v10_0_init_golden_registers(adev); 1113 1114 /* 1115 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1116 * register setup within GMC, or else system hang when harvesting SA. 1117 */ 1118 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1119 adev->gfxhub.funcs->utcl2_harvest(adev); 1120 1121 r = gmc_v10_0_gart_enable(adev); 1122 if (r) 1123 return r; 1124 1125 if (amdgpu_emu_mode == 1) { 1126 r = amdgpu_gmc_vram_checking(adev); 1127 if (r) 1128 return r; 1129 } 1130 1131 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1132 adev->umc.funcs->init_registers(adev); 1133 1134 return 0; 1135 } 1136 1137 /** 1138 * gmc_v10_0_gart_disable - gart disable 1139 * 1140 * @adev: amdgpu_device pointer 1141 * 1142 * This disables all VM page table. 1143 */ 1144 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1145 { 1146 if (!adev->in_s0ix) 1147 adev->gfxhub.funcs->gart_disable(adev); 1148 adev->mmhub.funcs->gart_disable(adev); 1149 } 1150 1151 static int gmc_v10_0_hw_fini(void *handle) 1152 { 1153 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1154 1155 gmc_v10_0_gart_disable(adev); 1156 1157 if (amdgpu_sriov_vf(adev)) { 1158 /* full access mode, so don't touch any GMC register */ 1159 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1160 return 0; 1161 } 1162 1163 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1164 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1165 1166 return 0; 1167 } 1168 1169 static int gmc_v10_0_suspend(void *handle) 1170 { 1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1172 1173 gmc_v10_0_hw_fini(adev); 1174 1175 return 0; 1176 } 1177 1178 static int gmc_v10_0_resume(void *handle) 1179 { 1180 int r; 1181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1182 1183 r = gmc_v10_0_hw_init(adev); 1184 if (r) 1185 return r; 1186 1187 amdgpu_vmid_reset_all(adev); 1188 1189 return 0; 1190 } 1191 1192 static bool gmc_v10_0_is_idle(void *handle) 1193 { 1194 /* MC is always ready in GMC v10.*/ 1195 return true; 1196 } 1197 1198 static int gmc_v10_0_wait_for_idle(void *handle) 1199 { 1200 /* There is no need to wait for MC idle in GMC v10.*/ 1201 return 0; 1202 } 1203 1204 static int gmc_v10_0_soft_reset(void *handle) 1205 { 1206 return 0; 1207 } 1208 1209 static int gmc_v10_0_set_clockgating_state(void *handle, 1210 enum amd_clockgating_state state) 1211 { 1212 int r; 1213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214 1215 /* 1216 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1217 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1218 * seen any issue on the DF 3.0.2 series platform. 1219 */ 1220 if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) { 1221 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1222 return 0; 1223 } 1224 1225 r = adev->mmhub.funcs->set_clockgating(adev, state); 1226 if (r) 1227 return r; 1228 1229 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1230 return athub_v2_1_set_clockgating(adev, state); 1231 else 1232 return athub_v2_0_set_clockgating(adev, state); 1233 } 1234 1235 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 1239 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) || 1240 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4)) 1241 return; 1242 1243 adev->mmhub.funcs->get_clockgating(adev, flags); 1244 1245 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) 1246 athub_v2_1_get_clockgating(adev, flags); 1247 else 1248 athub_v2_0_get_clockgating(adev, flags); 1249 } 1250 1251 static int gmc_v10_0_set_powergating_state(void *handle, 1252 enum amd_powergating_state state) 1253 { 1254 return 0; 1255 } 1256 1257 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1258 .name = "gmc_v10_0", 1259 .early_init = gmc_v10_0_early_init, 1260 .late_init = gmc_v10_0_late_init, 1261 .sw_init = gmc_v10_0_sw_init, 1262 .sw_fini = gmc_v10_0_sw_fini, 1263 .hw_init = gmc_v10_0_hw_init, 1264 .hw_fini = gmc_v10_0_hw_fini, 1265 .suspend = gmc_v10_0_suspend, 1266 .resume = gmc_v10_0_resume, 1267 .is_idle = gmc_v10_0_is_idle, 1268 .wait_for_idle = gmc_v10_0_wait_for_idle, 1269 .soft_reset = gmc_v10_0_soft_reset, 1270 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1271 .set_powergating_state = gmc_v10_0_set_powergating_state, 1272 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1273 }; 1274 1275 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1276 { 1277 .type = AMD_IP_BLOCK_TYPE_GMC, 1278 .major = 10, 1279 .minor = 0, 1280 .rev = 0, 1281 .funcs = &gmc_v10_0_ip_funcs, 1282 }; 1283