1*2279b4e5STianci.Yin /* 2*2279b4e5STianci.Yin * Copyright 2021 Advanced Micro Devices, Inc. 3*2279b4e5STianci.Yin * 4*2279b4e5STianci.Yin * Permission is hereby granted, free of charge, to any person obtaining a 5*2279b4e5STianci.Yin * copy of this software and associated documentation files (the "Software"), 6*2279b4e5STianci.Yin * to deal in the Software without restriction, including without limitation 7*2279b4e5STianci.Yin * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*2279b4e5STianci.Yin * and/or sell copies of the Software, and to permit persons to whom the 9*2279b4e5STianci.Yin * Software is furnished to do so, subject to the following conditions: 10*2279b4e5STianci.Yin * 11*2279b4e5STianci.Yin * The above copyright notice and this permission notice shall be included in 12*2279b4e5STianci.Yin * all copies or substantial portions of the Software. 13*2279b4e5STianci.Yin * 14*2279b4e5STianci.Yin * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*2279b4e5STianci.Yin * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*2279b4e5STianci.Yin * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*2279b4e5STianci.Yin * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*2279b4e5STianci.Yin * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*2279b4e5STianci.Yin * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*2279b4e5STianci.Yin * OTHER DEALINGS IN THE SOFTWARE. 21*2279b4e5STianci.Yin * 22*2279b4e5STianci.Yin */ 23*2279b4e5STianci.Yin 24*2279b4e5STianci.Yin #include "amdgpu.h" 25*2279b4e5STianci.Yin #include "gfxhub_v3_0.h" 26*2279b4e5STianci.Yin 27*2279b4e5STianci.Yin #include "gc/gc_11_0_0_offset.h" 28*2279b4e5STianci.Yin #include "gc/gc_11_0_0_sh_mask.h" 29*2279b4e5STianci.Yin #include "navi10_enum.h" 30*2279b4e5STianci.Yin #include "soc15_common.h" 31*2279b4e5STianci.Yin 32*2279b4e5STianci.Yin #define regGCVM_L2_CNTL3_DEFAULT 0x80100007 33*2279b4e5STianci.Yin #define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 34*2279b4e5STianci.Yin #define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 35*2279b4e5STianci.Yin 36*2279b4e5STianci.Yin static const char *gfxhub_client_ids[] = { 37*2279b4e5STianci.Yin "CB/DB", 38*2279b4e5STianci.Yin "Reserved", 39*2279b4e5STianci.Yin "GE1", 40*2279b4e5STianci.Yin "GE2", 41*2279b4e5STianci.Yin "CPF", 42*2279b4e5STianci.Yin "CPC", 43*2279b4e5STianci.Yin "CPG", 44*2279b4e5STianci.Yin "RLC", 45*2279b4e5STianci.Yin "TCP", 46*2279b4e5STianci.Yin "SQC (inst)", 47*2279b4e5STianci.Yin "SQC (data)", 48*2279b4e5STianci.Yin "SQG", 49*2279b4e5STianci.Yin "Reserved", 50*2279b4e5STianci.Yin "SDMA0", 51*2279b4e5STianci.Yin "SDMA1", 52*2279b4e5STianci.Yin "GCR", 53*2279b4e5STianci.Yin "SDMA2", 54*2279b4e5STianci.Yin "SDMA3", 55*2279b4e5STianci.Yin }; 56*2279b4e5STianci.Yin 57*2279b4e5STianci.Yin static uint32_t gfxhub_v3_0_get_invalidate_req(unsigned int vmid, 58*2279b4e5STianci.Yin uint32_t flush_type) 59*2279b4e5STianci.Yin { 60*2279b4e5STianci.Yin u32 req = 0; 61*2279b4e5STianci.Yin 62*2279b4e5STianci.Yin /* invalidate using legacy mode on vmid*/ 63*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 64*2279b4e5STianci.Yin PER_VMID_INVALIDATE_REQ, 1 << vmid); 65*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 66*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 67*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 68*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 69*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 70*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 71*2279b4e5STianci.Yin req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 72*2279b4e5STianci.Yin CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 73*2279b4e5STianci.Yin 74*2279b4e5STianci.Yin return req; 75*2279b4e5STianci.Yin } 76*2279b4e5STianci.Yin 77*2279b4e5STianci.Yin static void 78*2279b4e5STianci.Yin gfxhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 79*2279b4e5STianci.Yin uint32_t status) 80*2279b4e5STianci.Yin { 81*2279b4e5STianci.Yin u32 cid = REG_GET_FIELD(status, 82*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, CID); 83*2279b4e5STianci.Yin 84*2279b4e5STianci.Yin dev_err(adev->dev, 85*2279b4e5STianci.Yin "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 86*2279b4e5STianci.Yin status); 87*2279b4e5STianci.Yin dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 88*2279b4e5STianci.Yin cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 89*2279b4e5STianci.Yin cid); 90*2279b4e5STianci.Yin dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 91*2279b4e5STianci.Yin REG_GET_FIELD(status, 92*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 93*2279b4e5STianci.Yin dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 94*2279b4e5STianci.Yin REG_GET_FIELD(status, 95*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 96*2279b4e5STianci.Yin dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 97*2279b4e5STianci.Yin REG_GET_FIELD(status, 98*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 99*2279b4e5STianci.Yin dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 100*2279b4e5STianci.Yin REG_GET_FIELD(status, 101*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 102*2279b4e5STianci.Yin dev_err(adev->dev, "\t RW: 0x%lx\n", 103*2279b4e5STianci.Yin REG_GET_FIELD(status, 104*2279b4e5STianci.Yin GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 105*2279b4e5STianci.Yin } 106*2279b4e5STianci.Yin 107*2279b4e5STianci.Yin static u64 gfxhub_v3_0_get_fb_location(struct amdgpu_device *adev) 108*2279b4e5STianci.Yin { 109*2279b4e5STianci.Yin u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); 110*2279b4e5STianci.Yin 111*2279b4e5STianci.Yin base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 112*2279b4e5STianci.Yin base <<= 24; 113*2279b4e5STianci.Yin 114*2279b4e5STianci.Yin return base; 115*2279b4e5STianci.Yin } 116*2279b4e5STianci.Yin 117*2279b4e5STianci.Yin static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev) 118*2279b4e5STianci.Yin { 119*2279b4e5STianci.Yin return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; 120*2279b4e5STianci.Yin } 121*2279b4e5STianci.Yin 122*2279b4e5STianci.Yin static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 123*2279b4e5STianci.Yin uint64_t page_table_base) 124*2279b4e5STianci.Yin { 125*2279b4e5STianci.Yin struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 126*2279b4e5STianci.Yin 127*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 128*2279b4e5STianci.Yin hub->ctx_addr_distance * vmid, 129*2279b4e5STianci.Yin lower_32_bits(page_table_base)); 130*2279b4e5STianci.Yin 131*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 132*2279b4e5STianci.Yin hub->ctx_addr_distance * vmid, 133*2279b4e5STianci.Yin upper_32_bits(page_table_base)); 134*2279b4e5STianci.Yin } 135*2279b4e5STianci.Yin 136*2279b4e5STianci.Yin static void gfxhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev) 137*2279b4e5STianci.Yin { 138*2279b4e5STianci.Yin uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 139*2279b4e5STianci.Yin 140*2279b4e5STianci.Yin gfxhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base); 141*2279b4e5STianci.Yin 142*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 143*2279b4e5STianci.Yin (u32)(adev->gmc.gart_start >> 12)); 144*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 145*2279b4e5STianci.Yin (u32)(adev->gmc.gart_start >> 44)); 146*2279b4e5STianci.Yin 147*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 148*2279b4e5STianci.Yin (u32)(adev->gmc.gart_end >> 12)); 149*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 150*2279b4e5STianci.Yin (u32)(adev->gmc.gart_end >> 44)); 151*2279b4e5STianci.Yin } 152*2279b4e5STianci.Yin 153*2279b4e5STianci.Yin static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev) 154*2279b4e5STianci.Yin { 155*2279b4e5STianci.Yin uint64_t value; 156*2279b4e5STianci.Yin 157*2279b4e5STianci.Yin /* Disable AGP. */ 158*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); 159*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0); 160*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF); 161*2279b4e5STianci.Yin 162*2279b4e5STianci.Yin /* Program the system aperture low logical page number. */ 163*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 164*2279b4e5STianci.Yin adev->gmc.vram_start >> 18); 165*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 166*2279b4e5STianci.Yin adev->gmc.vram_end >> 18); 167*2279b4e5STianci.Yin 168*2279b4e5STianci.Yin /* Set default page address. */ 169*2279b4e5STianci.Yin value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 170*2279b4e5STianci.Yin + adev->vm_manager.vram_base_offset; 171*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 172*2279b4e5STianci.Yin (u32)(value >> 12)); 173*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 174*2279b4e5STianci.Yin (u32)(value >> 44)); 175*2279b4e5STianci.Yin 176*2279b4e5STianci.Yin /* Program "protection fault". */ 177*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 178*2279b4e5STianci.Yin (u32)(adev->dummy_page_addr >> 12)); 179*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 180*2279b4e5STianci.Yin (u32)((u64)adev->dummy_page_addr >> 44)); 181*2279b4e5STianci.Yin 182*2279b4e5STianci.Yin WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 183*2279b4e5STianci.Yin ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 184*2279b4e5STianci.Yin } 185*2279b4e5STianci.Yin 186*2279b4e5STianci.Yin 187*2279b4e5STianci.Yin static void gfxhub_v3_0_init_tlb_regs(struct amdgpu_device *adev) 188*2279b4e5STianci.Yin { 189*2279b4e5STianci.Yin uint32_t tmp; 190*2279b4e5STianci.Yin 191*2279b4e5STianci.Yin /* Setup TLB control */ 192*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 193*2279b4e5STianci.Yin 194*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 195*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 196*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 197*2279b4e5STianci.Yin ENABLE_ADVANCED_DRIVER_MODEL, 1); 198*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 199*2279b4e5STianci.Yin SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 200*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 201*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 202*2279b4e5STianci.Yin MTYPE, MTYPE_UC); /* UC, uncached */ 203*2279b4e5STianci.Yin 204*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 205*2279b4e5STianci.Yin } 206*2279b4e5STianci.Yin 207*2279b4e5STianci.Yin static void gfxhub_v3_0_init_cache_regs(struct amdgpu_device *adev) 208*2279b4e5STianci.Yin { 209*2279b4e5STianci.Yin uint32_t tmp; 210*2279b4e5STianci.Yin 211*2279b4e5STianci.Yin /* These registers are not accessible to VF-SRIOV. 212*2279b4e5STianci.Yin * The PF will program them instead. 213*2279b4e5STianci.Yin */ 214*2279b4e5STianci.Yin if (amdgpu_sriov_vf(adev)) 215*2279b4e5STianci.Yin return; 216*2279b4e5STianci.Yin 217*2279b4e5STianci.Yin /* Setup L2 cache */ 218*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); 219*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 220*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 221*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222*2279b4e5STianci.Yin ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 223*2279b4e5STianci.Yin /* XXX for emulation, Refer to closed source code.*/ 224*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 225*2279b4e5STianci.Yin L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 226*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 227*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 228*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 229*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); 230*2279b4e5STianci.Yin 231*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); 232*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 233*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 234*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); 235*2279b4e5STianci.Yin 236*2279b4e5STianci.Yin tmp = regGCVM_L2_CNTL3_DEFAULT; 237*2279b4e5STianci.Yin if (adev->gmc.translate_further) { 238*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 239*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 240*2279b4e5STianci.Yin L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 241*2279b4e5STianci.Yin } else { 242*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 243*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 244*2279b4e5STianci.Yin L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 245*2279b4e5STianci.Yin } 246*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); 247*2279b4e5STianci.Yin 248*2279b4e5STianci.Yin tmp = regGCVM_L2_CNTL4_DEFAULT; 249*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 250*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 251*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); 252*2279b4e5STianci.Yin 253*2279b4e5STianci.Yin tmp = regGCVM_L2_CNTL5_DEFAULT; 254*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 255*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); 256*2279b4e5STianci.Yin } 257*2279b4e5STianci.Yin 258*2279b4e5STianci.Yin static void gfxhub_v3_0_enable_system_domain(struct amdgpu_device *adev) 259*2279b4e5STianci.Yin { 260*2279b4e5STianci.Yin uint32_t tmp; 261*2279b4e5STianci.Yin 262*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 263*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 264*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 265*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 266*2279b4e5STianci.Yin RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 267*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 268*2279b4e5STianci.Yin } 269*2279b4e5STianci.Yin 270*2279b4e5STianci.Yin static void gfxhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev) 271*2279b4e5STianci.Yin { 272*2279b4e5STianci.Yin /* These registers are not accessible to VF-SRIOV. 273*2279b4e5STianci.Yin * The PF will program them instead. 274*2279b4e5STianci.Yin */ 275*2279b4e5STianci.Yin if (amdgpu_sriov_vf(adev)) 276*2279b4e5STianci.Yin return; 277*2279b4e5STianci.Yin 278*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 279*2279b4e5STianci.Yin 0xFFFFFFFF); 280*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 281*2279b4e5STianci.Yin 0x0000000F); 282*2279b4e5STianci.Yin 283*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 284*2279b4e5STianci.Yin 0); 285*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 286*2279b4e5STianci.Yin 0); 287*2279b4e5STianci.Yin 288*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 289*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 290*2279b4e5STianci.Yin 291*2279b4e5STianci.Yin } 292*2279b4e5STianci.Yin 293*2279b4e5STianci.Yin static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev) 294*2279b4e5STianci.Yin { 295*2279b4e5STianci.Yin struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 296*2279b4e5STianci.Yin int i; 297*2279b4e5STianci.Yin uint32_t tmp; 298*2279b4e5STianci.Yin 299*2279b4e5STianci.Yin for (i = 0; i <= 14; i++) { 300*2279b4e5STianci.Yin tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); 301*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 302*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 303*2279b4e5STianci.Yin adev->vm_manager.num_level); 304*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 305*2279b4e5STianci.Yin RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 306*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 307*2279b4e5STianci.Yin DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 308*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 309*2279b4e5STianci.Yin PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 310*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 311*2279b4e5STianci.Yin VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 312*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 313*2279b4e5STianci.Yin READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 314*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 315*2279b4e5STianci.Yin WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 316*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 317*2279b4e5STianci.Yin EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 318*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 319*2279b4e5STianci.Yin PAGE_TABLE_BLOCK_SIZE, 320*2279b4e5STianci.Yin adev->vm_manager.block_size - 9); 321*2279b4e5STianci.Yin /* Send no-retry XNACK on fault to suppress VM fault storm. */ 322*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 323*2279b4e5STianci.Yin RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 324*2279b4e5STianci.Yin !amdgpu_noretry); 325*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, 326*2279b4e5STianci.Yin i * hub->ctx_distance, tmp); 327*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 328*2279b4e5STianci.Yin i * hub->ctx_addr_distance, 0); 329*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 330*2279b4e5STianci.Yin i * hub->ctx_addr_distance, 0); 331*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 332*2279b4e5STianci.Yin i * hub->ctx_addr_distance, 333*2279b4e5STianci.Yin lower_32_bits(adev->vm_manager.max_pfn - 1)); 334*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 335*2279b4e5STianci.Yin i * hub->ctx_addr_distance, 336*2279b4e5STianci.Yin upper_32_bits(adev->vm_manager.max_pfn - 1)); 337*2279b4e5STianci.Yin } 338*2279b4e5STianci.Yin } 339*2279b4e5STianci.Yin 340*2279b4e5STianci.Yin static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev) 341*2279b4e5STianci.Yin { 342*2279b4e5STianci.Yin struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 343*2279b4e5STianci.Yin unsigned i; 344*2279b4e5STianci.Yin 345*2279b4e5STianci.Yin for (i = 0 ; i < 18; ++i) { 346*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 347*2279b4e5STianci.Yin i * hub->eng_addr_distance, 0xffffffff); 348*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 349*2279b4e5STianci.Yin i * hub->eng_addr_distance, 0x1f); 350*2279b4e5STianci.Yin } 351*2279b4e5STianci.Yin } 352*2279b4e5STianci.Yin 353*2279b4e5STianci.Yin static int gfxhub_v3_0_gart_enable(struct amdgpu_device *adev) 354*2279b4e5STianci.Yin { 355*2279b4e5STianci.Yin if (amdgpu_sriov_vf(adev)) { 356*2279b4e5STianci.Yin /* 357*2279b4e5STianci.Yin * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 358*2279b4e5STianci.Yin * VF copy registers so vbios post doesn't program them, for 359*2279b4e5STianci.Yin * SRIOV driver need to program them 360*2279b4e5STianci.Yin */ 361*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 362*2279b4e5STianci.Yin adev->gmc.vram_start >> 24); 363*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 364*2279b4e5STianci.Yin adev->gmc.vram_end >> 24); 365*2279b4e5STianci.Yin } 366*2279b4e5STianci.Yin 367*2279b4e5STianci.Yin /* GART Enable. */ 368*2279b4e5STianci.Yin gfxhub_v3_0_init_gart_aperture_regs(adev); 369*2279b4e5STianci.Yin gfxhub_v3_0_init_system_aperture_regs(adev); 370*2279b4e5STianci.Yin gfxhub_v3_0_init_tlb_regs(adev); 371*2279b4e5STianci.Yin gfxhub_v3_0_init_cache_regs(adev); 372*2279b4e5STianci.Yin 373*2279b4e5STianci.Yin gfxhub_v3_0_enable_system_domain(adev); 374*2279b4e5STianci.Yin gfxhub_v3_0_disable_identity_aperture(adev); 375*2279b4e5STianci.Yin gfxhub_v3_0_setup_vmid_config(adev); 376*2279b4e5STianci.Yin gfxhub_v3_0_program_invalidation(adev); 377*2279b4e5STianci.Yin 378*2279b4e5STianci.Yin return 0; 379*2279b4e5STianci.Yin } 380*2279b4e5STianci.Yin 381*2279b4e5STianci.Yin static void gfxhub_v3_0_gart_disable(struct amdgpu_device *adev) 382*2279b4e5STianci.Yin { 383*2279b4e5STianci.Yin struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 384*2279b4e5STianci.Yin u32 tmp; 385*2279b4e5STianci.Yin u32 i; 386*2279b4e5STianci.Yin 387*2279b4e5STianci.Yin /* Disable all tables */ 388*2279b4e5STianci.Yin for (i = 0; i < 16; i++) 389*2279b4e5STianci.Yin WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 390*2279b4e5STianci.Yin i * hub->ctx_distance, 0); 391*2279b4e5STianci.Yin 392*2279b4e5STianci.Yin /* Setup TLB control */ 393*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 394*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 395*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 396*2279b4e5STianci.Yin ENABLE_ADVANCED_DRIVER_MODEL, 0); 397*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 398*2279b4e5STianci.Yin 399*2279b4e5STianci.Yin /* Setup L2 cache */ 400*2279b4e5STianci.Yin WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 401*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); 402*2279b4e5STianci.Yin } 403*2279b4e5STianci.Yin 404*2279b4e5STianci.Yin /** 405*2279b4e5STianci.Yin * gfxhub_v3_0_set_fault_enable_default - update GART/VM fault handling 406*2279b4e5STianci.Yin * 407*2279b4e5STianci.Yin * @adev: amdgpu_device pointer 408*2279b4e5STianci.Yin * @value: true redirects VM faults to the default page 409*2279b4e5STianci.Yin */ 410*2279b4e5STianci.Yin static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, 411*2279b4e5STianci.Yin bool value) 412*2279b4e5STianci.Yin { 413*2279b4e5STianci.Yin u32 tmp; 414*2279b4e5STianci.Yin 415*2279b4e5STianci.Yin /* These registers are not accessible to VF-SRIOV. 416*2279b4e5STianci.Yin * The PF will program them instead. 417*2279b4e5STianci.Yin */ 418*2279b4e5STianci.Yin if (amdgpu_sriov_vf(adev)) 419*2279b4e5STianci.Yin return; 420*2279b4e5STianci.Yin 421*2279b4e5STianci.Yin tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 422*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 423*2279b4e5STianci.Yin RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 425*2279b4e5STianci.Yin PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 426*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 427*2279b4e5STianci.Yin PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 428*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 429*2279b4e5STianci.Yin PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 430*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 431*2279b4e5STianci.Yin TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 432*2279b4e5STianci.Yin value); 433*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 434*2279b4e5STianci.Yin NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 436*2279b4e5STianci.Yin DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 438*2279b4e5STianci.Yin VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 440*2279b4e5STianci.Yin READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 441*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 442*2279b4e5STianci.Yin WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 443*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 444*2279b4e5STianci.Yin EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 445*2279b4e5STianci.Yin if (!value) { 446*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 447*2279b4e5STianci.Yin CRASH_ON_NO_RETRY_FAULT, 1); 448*2279b4e5STianci.Yin tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 449*2279b4e5STianci.Yin CRASH_ON_RETRY_FAULT, 1); 450*2279b4e5STianci.Yin } 451*2279b4e5STianci.Yin WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 452*2279b4e5STianci.Yin } 453*2279b4e5STianci.Yin 454*2279b4e5STianci.Yin static const struct amdgpu_vmhub_funcs gfxhub_v3_0_vmhub_funcs = { 455*2279b4e5STianci.Yin .print_l2_protection_fault_status = gfxhub_v3_0_print_l2_protection_fault_status, 456*2279b4e5STianci.Yin .get_invalidate_req = gfxhub_v3_0_get_invalidate_req, 457*2279b4e5STianci.Yin }; 458*2279b4e5STianci.Yin 459*2279b4e5STianci.Yin static void gfxhub_v3_0_init(struct amdgpu_device *adev) 460*2279b4e5STianci.Yin { 461*2279b4e5STianci.Yin struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 462*2279b4e5STianci.Yin 463*2279b4e5STianci.Yin hub->ctx0_ptb_addr_lo32 = 464*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, 465*2279b4e5STianci.Yin regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 466*2279b4e5STianci.Yin hub->ctx0_ptb_addr_hi32 = 467*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, 468*2279b4e5STianci.Yin regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 469*2279b4e5STianci.Yin hub->vm_inv_eng0_sem = 470*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM); 471*2279b4e5STianci.Yin hub->vm_inv_eng0_req = 472*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ); 473*2279b4e5STianci.Yin hub->vm_inv_eng0_ack = 474*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK); 475*2279b4e5STianci.Yin hub->vm_context0_cntl = 476*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 477*2279b4e5STianci.Yin hub->vm_l2_pro_fault_status = 478*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS); 479*2279b4e5STianci.Yin hub->vm_l2_pro_fault_cntl = 480*2279b4e5STianci.Yin SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 481*2279b4e5STianci.Yin 482*2279b4e5STianci.Yin hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; 483*2279b4e5STianci.Yin hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 484*2279b4e5STianci.Yin regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 485*2279b4e5STianci.Yin hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ - 486*2279b4e5STianci.Yin regGCVM_INVALIDATE_ENG0_REQ; 487*2279b4e5STianci.Yin hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 488*2279b4e5STianci.Yin regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 489*2279b4e5STianci.Yin 490*2279b4e5STianci.Yin hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 491*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 492*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 493*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 494*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 495*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 496*2279b4e5STianci.Yin GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 497*2279b4e5STianci.Yin 498*2279b4e5STianci.Yin hub->vmhub_funcs = &gfxhub_v3_0_vmhub_funcs; 499*2279b4e5STianci.Yin } 500*2279b4e5STianci.Yin 501*2279b4e5STianci.Yin const struct amdgpu_gfxhub_funcs gfxhub_v3_0_funcs = { 502*2279b4e5STianci.Yin .get_fb_location = gfxhub_v3_0_get_fb_location, 503*2279b4e5STianci.Yin .get_mc_fb_offset = gfxhub_v3_0_get_mc_fb_offset, 504*2279b4e5STianci.Yin .setup_vm_pt_regs = gfxhub_v3_0_setup_vm_pt_regs, 505*2279b4e5STianci.Yin .gart_enable = gfxhub_v3_0_gart_enable, 506*2279b4e5STianci.Yin .gart_disable = gfxhub_v3_0_gart_disable, 507*2279b4e5STianci.Yin .set_fault_enable_default = gfxhub_v3_0_set_fault_enable_default, 508*2279b4e5STianci.Yin .init = gfxhub_v3_0_init, 509*2279b4e5STianci.Yin }; 510