1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_0.h" 26 27 #include "gc/gc_10_1_0_offset.h" 28 #include "gc/gc_10_1_0_sh_mask.h" 29 #include "gc/gc_10_1_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 35 { 36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37 38 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39 base <<= 24; 40 41 return base; 42 } 43 44 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 45 { 46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47 } 48 49 static void gfxhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev) 50 { 51 uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); 52 53 54 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 55 lower_32_bits(value)); 56 57 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 58 upper_32_bits(value)); 59 } 60 61 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 62 { 63 gfxhub_v2_0_init_gart_pt_regs(adev); 64 65 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 66 (u32)(adev->gmc.gart_start >> 12)); 67 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 68 (u32)(adev->gmc.gart_start >> 44)); 69 70 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 71 (u32)(adev->gmc.gart_end >> 12)); 72 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 73 (u32)(adev->gmc.gart_end >> 44)); 74 } 75 76 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 77 { 78 uint64_t value; 79 80 /* Disable AGP. */ 81 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 82 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 83 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 84 85 /* Program the system aperture low logical page number. */ 86 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 87 adev->gmc.vram_start >> 18); 88 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 89 adev->gmc.vram_end >> 18); 90 91 /* Set default page address. */ 92 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 93 + adev->vm_manager.vram_base_offset; 94 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 95 (u32)(value >> 12)); 96 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 97 (u32)(value >> 44)); 98 99 /* Program "protection fault". */ 100 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 101 (u32)(adev->dummy_page_addr >> 12)); 102 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 103 (u32)((u64)adev->dummy_page_addr >> 44)); 104 105 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 106 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 107 } 108 109 110 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 111 { 112 uint32_t tmp; 113 114 /* Setup TLB control */ 115 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 116 117 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 118 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 119 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 120 ENABLE_ADVANCED_DRIVER_MODEL, 1); 121 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 122 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 123 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 124 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 125 MTYPE, MTYPE_UC); /* UC, uncached */ 126 127 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 128 } 129 130 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 131 { 132 uint32_t tmp; 133 134 /* Setup L2 cache */ 135 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 136 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 137 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 138 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 139 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 140 /* XXX for emulation, Refer to closed source code.*/ 141 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 142 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 143 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 144 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 145 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 146 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 147 148 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 149 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 150 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 151 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 152 153 tmp = mmGCVM_L2_CNTL3_DEFAULT; 154 if (adev->gmc.translate_further) { 155 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 156 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 157 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 158 } else { 159 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 160 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 161 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 162 } 163 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 164 165 tmp = mmGCVM_L2_CNTL4_DEFAULT; 166 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 167 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 168 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 169 } 170 171 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 172 { 173 uint32_t tmp; 174 175 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 176 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 177 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 178 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 179 } 180 181 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 182 { 183 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 184 0xFFFFFFFF); 185 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 186 0x0000000F); 187 188 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 189 0); 190 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 191 0); 192 193 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 194 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 195 196 } 197 198 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 199 { 200 int i; 201 uint32_t tmp; 202 203 for (i = 0; i <= 14; i++) { 204 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 205 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 206 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 207 adev->vm_manager.num_level); 208 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 209 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 210 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 211 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 212 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 213 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 214 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 215 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 216 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 217 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 218 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 219 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 220 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 221 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 222 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 223 PAGE_TABLE_BLOCK_SIZE, 224 adev->vm_manager.block_size - 9); 225 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 226 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 227 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 228 !amdgpu_noretry); 229 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); 230 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 231 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 232 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 233 lower_32_bits(adev->vm_manager.max_pfn - 1)); 234 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 235 upper_32_bits(adev->vm_manager.max_pfn - 1)); 236 } 237 } 238 239 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 240 { 241 unsigned i; 242 243 for (i = 0 ; i < 18; ++i) { 244 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 245 2 * i, 0xffffffff); 246 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 247 2 * i, 0x1f); 248 } 249 } 250 251 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 252 { 253 if (amdgpu_sriov_vf(adev)) { 254 /* 255 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 256 * VF copy registers so vbios post doesn't program them, for 257 * SRIOV driver need to program them 258 */ 259 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 260 adev->gmc.vram_start >> 24); 261 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 262 adev->gmc.vram_end >> 24); 263 } 264 265 /* GART Enable. */ 266 gfxhub_v2_0_init_gart_aperture_regs(adev); 267 gfxhub_v2_0_init_system_aperture_regs(adev); 268 gfxhub_v2_0_init_tlb_regs(adev); 269 gfxhub_v2_0_init_cache_regs(adev); 270 271 gfxhub_v2_0_enable_system_domain(adev); 272 gfxhub_v2_0_disable_identity_aperture(adev); 273 gfxhub_v2_0_setup_vmid_config(adev); 274 gfxhub_v2_0_program_invalidation(adev); 275 276 return 0; 277 } 278 279 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 280 { 281 u32 tmp; 282 u32 i; 283 284 /* Disable all tables */ 285 for (i = 0; i < 16; i++) 286 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); 287 288 /* Setup TLB control */ 289 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 290 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 291 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 292 ENABLE_ADVANCED_DRIVER_MODEL, 0); 293 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 294 295 /* Setup L2 cache */ 296 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 297 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 298 } 299 300 /** 301 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 302 * 303 * @adev: amdgpu_device pointer 304 * @value: true redirects VM faults to the default page 305 */ 306 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 307 bool value) 308 { 309 u32 tmp; 310 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 311 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 312 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 314 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 316 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 318 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 319 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 320 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 321 value); 322 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 323 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 324 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 325 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 326 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 327 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 328 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 329 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 330 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 331 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 332 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 333 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 334 if (!value) { 335 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 336 CRASH_ON_NO_RETRY_FAULT, 1); 337 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 338 CRASH_ON_RETRY_FAULT, 1); 339 } 340 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 341 } 342 343 void gfxhub_v2_0_init(struct amdgpu_device *adev) 344 { 345 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 346 347 hub->ctx0_ptb_addr_lo32 = 348 SOC15_REG_OFFSET(GC, 0, 349 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 350 hub->ctx0_ptb_addr_hi32 = 351 SOC15_REG_OFFSET(GC, 0, 352 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 353 hub->vm_inv_eng0_req = 354 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 355 hub->vm_inv_eng0_ack = 356 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 357 hub->vm_context0_cntl = 358 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 359 hub->vm_l2_pro_fault_status = 360 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 361 hub->vm_l2_pro_fault_cntl = 362 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 363 } 364