1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_0.h" 26 27 #include "gc/gc_10_1_0_offset.h" 28 #include "gc/gc_10_1_0_sh_mask.h" 29 #include "gc/gc_10_1_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 35 { 36 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37 38 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39 base <<= 24; 40 41 return base; 42 } 43 44 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 45 { 46 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47 } 48 49 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 50 uint64_t page_table_base) 51 { 52 /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */ 53 int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 54 - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 55 56 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 57 offset * vmid, lower_32_bits(page_table_base)); 58 59 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 60 offset * vmid, upper_32_bits(page_table_base)); 61 } 62 63 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 64 { 65 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 66 67 gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 68 69 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70 (u32)(adev->gmc.gart_start >> 12)); 71 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72 (u32)(adev->gmc.gart_start >> 44)); 73 74 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75 (u32)(adev->gmc.gart_end >> 12)); 76 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77 (u32)(adev->gmc.gart_end >> 44)); 78 } 79 80 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 81 { 82 uint64_t value; 83 84 /* Disable AGP. */ 85 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 86 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 87 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 88 89 /* Program the system aperture low logical page number. */ 90 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 91 adev->gmc.vram_start >> 18); 92 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 93 adev->gmc.vram_end >> 18); 94 95 /* Set default page address. */ 96 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 97 + adev->vm_manager.vram_base_offset; 98 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 99 (u32)(value >> 12)); 100 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 101 (u32)(value >> 44)); 102 103 /* Program "protection fault". */ 104 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 105 (u32)(adev->dummy_page_addr >> 12)); 106 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 107 (u32)((u64)adev->dummy_page_addr >> 44)); 108 109 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 110 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 111 } 112 113 114 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 115 { 116 uint32_t tmp; 117 118 /* Setup TLB control */ 119 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 120 121 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 122 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 123 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 124 ENABLE_ADVANCED_DRIVER_MODEL, 1); 125 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 126 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 127 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 128 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 129 MTYPE, MTYPE_UC); /* UC, uncached */ 130 131 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 132 } 133 134 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 135 { 136 uint32_t tmp; 137 138 /* Setup L2 cache */ 139 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 140 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 141 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 142 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 143 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 144 /* XXX for emulation, Refer to closed source code.*/ 145 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 146 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 147 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 148 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 149 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 150 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 151 152 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 153 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 154 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 155 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 156 157 tmp = mmGCVM_L2_CNTL3_DEFAULT; 158 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 159 160 tmp = mmGCVM_L2_CNTL4_DEFAULT; 161 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 162 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 163 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 164 } 165 166 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 167 { 168 uint32_t tmp; 169 170 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 171 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 172 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 173 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 174 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 175 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 176 } 177 178 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 179 { 180 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 181 0xFFFFFFFF); 182 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 183 0x0000000F); 184 185 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 186 0); 187 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 188 0); 189 190 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 191 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 192 193 } 194 195 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 196 { 197 int i; 198 uint32_t tmp; 199 200 for (i = 0; i <= 14; i++) { 201 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 202 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 203 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 204 adev->vm_manager.num_level); 205 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 206 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 207 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 208 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 209 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 210 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 211 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 212 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 213 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 214 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 215 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 216 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 217 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 218 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 219 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 220 PAGE_TABLE_BLOCK_SIZE, 221 adev->vm_manager.block_size - 9); 222 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 223 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 224 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 225 !amdgpu_noretry); 226 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); 227 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 228 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 229 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 230 lower_32_bits(adev->vm_manager.max_pfn - 1)); 231 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 232 upper_32_bits(adev->vm_manager.max_pfn - 1)); 233 } 234 } 235 236 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 237 { 238 unsigned i; 239 240 for (i = 0 ; i < 18; ++i) { 241 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 242 2 * i, 0xffffffff); 243 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 244 2 * i, 0x1f); 245 } 246 } 247 248 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 249 { 250 if (amdgpu_sriov_vf(adev)) { 251 /* 252 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 253 * VF copy registers so vbios post doesn't program them, for 254 * SRIOV driver need to program them 255 */ 256 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 257 adev->gmc.vram_start >> 24); 258 WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 259 adev->gmc.vram_end >> 24); 260 } 261 262 /* GART Enable. */ 263 gfxhub_v2_0_init_gart_aperture_regs(adev); 264 gfxhub_v2_0_init_system_aperture_regs(adev); 265 gfxhub_v2_0_init_tlb_regs(adev); 266 gfxhub_v2_0_init_cache_regs(adev); 267 268 gfxhub_v2_0_enable_system_domain(adev); 269 gfxhub_v2_0_disable_identity_aperture(adev); 270 gfxhub_v2_0_setup_vmid_config(adev); 271 gfxhub_v2_0_program_invalidation(adev); 272 273 return 0; 274 } 275 276 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 277 { 278 u32 tmp; 279 u32 i; 280 281 /* Disable all tables */ 282 for (i = 0; i < 16; i++) 283 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); 284 285 /* Setup TLB control */ 286 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 287 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 288 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 289 ENABLE_ADVANCED_DRIVER_MODEL, 0); 290 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 291 292 /* Setup L2 cache */ 293 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 294 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 295 } 296 297 /** 298 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 299 * 300 * @adev: amdgpu_device pointer 301 * @value: true redirects VM faults to the default page 302 */ 303 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 304 bool value) 305 { 306 u32 tmp; 307 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 308 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 309 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 310 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 311 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 312 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 313 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 314 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 315 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 316 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 317 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 318 value); 319 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 320 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 321 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 322 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 323 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 324 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 325 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 326 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 327 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 328 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 329 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 330 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 331 if (!value) { 332 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 333 CRASH_ON_NO_RETRY_FAULT, 1); 334 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 335 CRASH_ON_RETRY_FAULT, 1); 336 } 337 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 338 } 339 340 void gfxhub_v2_0_init(struct amdgpu_device *adev) 341 { 342 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 343 344 hub->ctx0_ptb_addr_lo32 = 345 SOC15_REG_OFFSET(GC, 0, 346 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 347 hub->ctx0_ptb_addr_hi32 = 348 SOC15_REG_OFFSET(GC, 0, 349 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 350 hub->vm_inv_eng0_req = 351 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 352 hub->vm_inv_eng0_ack = 353 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 354 hub->vm_context0_cntl = 355 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 356 hub->vm_l2_pro_fault_status = 357 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 358 hub->vm_l2_pro_fault_cntl = 359 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 360 } 361