1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_0.h" 26 27 #include "gc/gc_10_1_0_offset.h" 28 #include "gc/gc_10_1_0_sh_mask.h" 29 #include "gc/gc_10_1_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static const char *gfxhub_client_ids[] = { 35 "CB/DB", 36 "Reserved", 37 "GE1", 38 "GE2", 39 "CPF", 40 "CPC", 41 "CPG", 42 "RLC", 43 "TCP", 44 "SQC (inst)", 45 "SQC (data)", 46 "SQG", 47 "Reserved", 48 "SDMA0", 49 "SDMA1", 50 "GCR", 51 "SDMA2", 52 "SDMA3", 53 }; 54 55 static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid, 56 uint32_t flush_type) 57 { 58 u32 req = 0; 59 60 /* invalidate using legacy mode on vmid*/ 61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 62 PER_VMID_INVALIDATE_REQ, 1 << vmid); 63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 70 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 71 72 return req; 73 } 74 75 static void 76 gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 77 uint32_t status) 78 { 79 u32 cid = REG_GET_FIELD(status, 80 GCVM_L2_PROTECTION_FAULT_STATUS, CID); 81 82 dev_err(adev->dev, 83 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 84 status); 85 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 86 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 87 cid); 88 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 89 REG_GET_FIELD(status, 90 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 91 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 92 REG_GET_FIELD(status, 93 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 94 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 95 REG_GET_FIELD(status, 96 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 97 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 98 REG_GET_FIELD(status, 99 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 100 dev_err(adev->dev, "\t RW: 0x%lx\n", 101 REG_GET_FIELD(status, 102 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 103 } 104 105 u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 106 { 107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 108 109 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 110 base <<= 24; 111 112 return base; 113 } 114 115 u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 116 { 117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 118 } 119 120 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 121 uint64_t page_table_base) 122 { 123 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 124 125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 126 hub->ctx_addr_distance * vmid, 127 lower_32_bits(page_table_base)); 128 129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 130 hub->ctx_addr_distance * vmid, 131 upper_32_bits(page_table_base)); 132 } 133 134 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 135 { 136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 137 138 gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 139 140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 141 (u32)(adev->gmc.gart_start >> 12)); 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 143 (u32)(adev->gmc.gart_start >> 44)); 144 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 146 (u32)(adev->gmc.gart_end >> 12)); 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 148 (u32)(adev->gmc.gart_end >> 44)); 149 } 150 151 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 152 { 153 uint64_t value; 154 155 if (!amdgpu_sriov_vf(adev)) { 156 /* 157 * the new L1 policy will block SRIOV guest from writing 158 * these regs, and they will be programed at host. 159 * so skip programing these regs. 160 */ 161 /* Disable AGP. */ 162 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 163 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 164 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 165 166 /* Program the system aperture low logical page number. */ 167 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 168 adev->gmc.vram_start >> 18); 169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 170 adev->gmc.vram_end >> 18); 171 172 /* Set default page address. */ 173 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 174 + adev->vm_manager.vram_base_offset; 175 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 176 (u32)(value >> 12)); 177 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 178 (u32)(value >> 44)); 179 } 180 181 /* Program "protection fault". */ 182 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 183 (u32)(adev->dummy_page_addr >> 12)); 184 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 185 (u32)((u64)adev->dummy_page_addr >> 44)); 186 187 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 188 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 189 } 190 191 192 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 193 { 194 uint32_t tmp; 195 196 /* Setup TLB control */ 197 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 198 199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 201 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 202 ENABLE_ADVANCED_DRIVER_MODEL, 1); 203 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 204 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 205 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 206 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 207 MTYPE, MTYPE_UC); /* UC, uncached */ 208 209 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 210 } 211 212 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 213 { 214 uint32_t tmp; 215 216 /* These regs are not accessible for VF, PF will program these in SRIOV */ 217 if (amdgpu_sriov_vf(adev)) 218 return; 219 220 /* Setup L2 cache */ 221 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 222 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 225 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 226 /* XXX for emulation, Refer to closed source code.*/ 227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 228 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 232 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 233 234 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 237 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 238 239 tmp = mmGCVM_L2_CNTL3_DEFAULT; 240 if (adev->gmc.translate_further) { 241 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 242 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 243 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 244 } else { 245 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 247 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 248 } 249 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 250 251 tmp = mmGCVM_L2_CNTL4_DEFAULT; 252 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 253 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 254 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 255 256 tmp = mmGCVM_L2_CNTL5_DEFAULT; 257 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 258 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 259 } 260 261 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 262 { 263 uint32_t tmp; 264 265 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 266 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 267 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 268 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 269 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 270 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 271 } 272 273 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 274 { 275 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 276 0xFFFFFFFF); 277 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 278 0x0000000F); 279 280 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 281 0); 282 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 283 0); 284 285 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 286 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 287 288 } 289 290 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 291 { 292 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 293 int i; 294 uint32_t tmp; 295 296 for (i = 0; i <= 14; i++) { 297 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 300 adev->vm_manager.num_level); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 302 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 304 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 306 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 308 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 310 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 312 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 314 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 316 PAGE_TABLE_BLOCK_SIZE, 317 adev->vm_manager.block_size - 9); 318 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 319 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 320 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 321 !amdgpu_noretry); 322 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 323 i * hub->ctx_distance, tmp); 324 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 325 i * hub->ctx_addr_distance, 0); 326 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 327 i * hub->ctx_addr_distance, 0); 328 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 329 i * hub->ctx_addr_distance, 330 lower_32_bits(adev->vm_manager.max_pfn - 1)); 331 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 332 i * hub->ctx_addr_distance, 333 upper_32_bits(adev->vm_manager.max_pfn - 1)); 334 } 335 } 336 337 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 338 { 339 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 340 unsigned i; 341 342 for (i = 0 ; i < 18; ++i) { 343 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 344 i * hub->eng_addr_distance, 0xffffffff); 345 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 346 i * hub->eng_addr_distance, 0x1f); 347 } 348 } 349 350 int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 351 { 352 /* GART Enable. */ 353 gfxhub_v2_0_init_gart_aperture_regs(adev); 354 gfxhub_v2_0_init_system_aperture_regs(adev); 355 gfxhub_v2_0_init_tlb_regs(adev); 356 gfxhub_v2_0_init_cache_regs(adev); 357 358 gfxhub_v2_0_enable_system_domain(adev); 359 gfxhub_v2_0_disable_identity_aperture(adev); 360 gfxhub_v2_0_setup_vmid_config(adev); 361 gfxhub_v2_0_program_invalidation(adev); 362 363 return 0; 364 } 365 366 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 367 { 368 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 369 u32 tmp; 370 u32 i; 371 372 /* Disable all tables */ 373 for (i = 0; i < 16; i++) 374 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 375 i * hub->ctx_distance, 0); 376 377 /* Setup TLB control */ 378 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 379 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 380 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 381 ENABLE_ADVANCED_DRIVER_MODEL, 0); 382 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 383 384 if (!amdgpu_sriov_vf(adev)) { 385 /* Setup L2 cache */ 386 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 387 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 388 } 389 } 390 391 /** 392 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 393 * 394 * @adev: amdgpu_device pointer 395 * @value: true redirects VM faults to the default page 396 */ 397 void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 398 bool value) 399 { 400 u32 tmp; 401 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 402 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 403 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 405 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 406 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 407 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 408 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 409 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 410 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 411 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 412 value); 413 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 414 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 415 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 416 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 417 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 418 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 419 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 420 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 421 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 422 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 423 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 424 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 425 if (!value) { 426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 427 CRASH_ON_NO_RETRY_FAULT, 1); 428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 429 CRASH_ON_RETRY_FAULT, 1); 430 } 431 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 432 } 433 434 static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = { 435 .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status, 436 .get_invalidate_req = gfxhub_v2_0_get_invalidate_req, 437 }; 438 439 void gfxhub_v2_0_init(struct amdgpu_device *adev) 440 { 441 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 442 443 hub->ctx0_ptb_addr_lo32 = 444 SOC15_REG_OFFSET(GC, 0, 445 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 446 hub->ctx0_ptb_addr_hi32 = 447 SOC15_REG_OFFSET(GC, 0, 448 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 449 hub->vm_inv_eng0_sem = 450 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 451 hub->vm_inv_eng0_req = 452 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 453 hub->vm_inv_eng0_ack = 454 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 455 hub->vm_context0_cntl = 456 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 457 hub->vm_l2_pro_fault_status = 458 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 459 hub->vm_l2_pro_fault_cntl = 460 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 461 462 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 463 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 464 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 465 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 466 mmGCVM_INVALIDATE_ENG0_REQ; 467 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 468 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 469 470 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 471 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 477 478 hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs; 479 } 480