1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v2_0.h" 26 27 #include "gc/gc_10_1_0_offset.h" 28 #include "gc/gc_10_1_0_sh_mask.h" 29 #include "gc/gc_10_1_0_default.h" 30 #include "navi10_enum.h" 31 32 #include "soc15_common.h" 33 34 static const char *gfxhub_client_ids[] = { 35 "CB/DB", 36 "Reserved", 37 "GE1", 38 "GE2", 39 "CPF", 40 "CPC", 41 "CPG", 42 "RLC", 43 "TCP", 44 "SQC (inst)", 45 "SQC (data)", 46 "SQG", 47 "Reserved", 48 "SDMA0", 49 "SDMA1", 50 "GCR", 51 "SDMA2", 52 "SDMA3", 53 }; 54 55 static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid, 56 uint32_t flush_type) 57 { 58 u32 req = 0; 59 60 /* invalidate using legacy mode on vmid*/ 61 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 62 PER_VMID_INVALIDATE_REQ, 1 << vmid); 63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 69 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 70 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 71 72 return req; 73 } 74 75 static void 76 gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 77 uint32_t status) 78 { 79 u32 cid = REG_GET_FIELD(status, 80 GCVM_L2_PROTECTION_FAULT_STATUS, CID); 81 82 dev_err(adev->dev, 83 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 84 status); 85 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 86 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 87 cid); 88 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 89 REG_GET_FIELD(status, 90 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 91 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 92 REG_GET_FIELD(status, 93 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 94 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 95 REG_GET_FIELD(status, 96 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 97 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 98 REG_GET_FIELD(status, 99 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 100 dev_err(adev->dev, "\t RW: 0x%lx\n", 101 REG_GET_FIELD(status, 102 GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 103 } 104 105 static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 106 { 107 u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 108 109 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 110 base <<= 24; 111 112 return base; 113 } 114 115 static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 116 { 117 return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 118 } 119 120 static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 121 uint64_t page_table_base) 122 { 123 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 124 125 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 126 hub->ctx_addr_distance * vmid, 127 lower_32_bits(page_table_base)); 128 129 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 130 hub->ctx_addr_distance * vmid, 131 upper_32_bits(page_table_base)); 132 } 133 134 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 135 { 136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 137 138 gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 139 140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 141 (u32)(adev->gmc.gart_start >> 12)); 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 143 (u32)(adev->gmc.gart_start >> 44)); 144 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 146 (u32)(adev->gmc.gart_end >> 12)); 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 148 (u32)(adev->gmc.gart_end >> 44)); 149 } 150 151 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 152 { 153 uint64_t value; 154 155 if (!amdgpu_sriov_vf(adev)) { 156 /* Program the AGP BAR */ 157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 160 161 /* Program the system aperture low logical page number. */ 162 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 163 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 165 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 166 167 /* Set default page address. */ 168 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 170 (u32)(value >> 12)); 171 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 172 (u32)(value >> 44)); 173 } 174 175 /* Program "protection fault". */ 176 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 177 (u32)(adev->dummy_page_addr >> 12)); 178 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 179 (u32)((u64)adev->dummy_page_addr >> 44)); 180 181 WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 182 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 183 } 184 185 186 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 187 { 188 uint32_t tmp; 189 190 /* Setup TLB control */ 191 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 192 193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 194 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 196 ENABLE_ADVANCED_DRIVER_MODEL, 1); 197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 198 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 199 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 200 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 201 MTYPE, MTYPE_UC); /* UC, uncached */ 202 203 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 204 } 205 206 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 207 { 208 uint32_t tmp; 209 210 /* These regs are not accessible for VF, PF will program these in SRIOV */ 211 if (amdgpu_sriov_vf(adev)) 212 return; 213 214 /* Setup L2 cache */ 215 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 219 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 220 /* XXX for emulation, Refer to closed source code.*/ 221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 222 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 226 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 227 228 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 231 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 232 233 tmp = mmGCVM_L2_CNTL3_DEFAULT; 234 if (adev->gmc.translate_further) { 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 237 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 238 } else { 239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 241 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 242 } 243 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 244 245 tmp = mmGCVM_L2_CNTL4_DEFAULT; 246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 248 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 249 250 tmp = mmGCVM_L2_CNTL5_DEFAULT; 251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 252 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 253 } 254 255 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 256 { 257 uint32_t tmp; 258 259 tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 263 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 264 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 265 } 266 267 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 268 { 269 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 270 0xFFFFFFFF); 271 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 272 0x0000000F); 273 274 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 275 0); 276 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 277 0); 278 279 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 280 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 281 282 } 283 284 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 285 { 286 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 287 int i; 288 uint32_t tmp; 289 290 for (i = 0; i <= 14; i++) { 291 tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 292 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 293 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 294 adev->vm_manager.num_level); 295 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 296 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 297 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 298 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 300 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 302 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 304 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 306 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 308 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 310 PAGE_TABLE_BLOCK_SIZE, 311 adev->vm_manager.block_size - 9); 312 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 314 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 315 !adev->gmc.noretry); 316 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 317 i * hub->ctx_distance, tmp); 318 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 319 i * hub->ctx_addr_distance, 0); 320 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 321 i * hub->ctx_addr_distance, 0); 322 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 323 i * hub->ctx_addr_distance, 324 lower_32_bits(adev->vm_manager.max_pfn - 1)); 325 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 326 i * hub->ctx_addr_distance, 327 upper_32_bits(adev->vm_manager.max_pfn - 1)); 328 } 329 } 330 331 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 332 { 333 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 334 unsigned i; 335 336 for (i = 0 ; i < 18; ++i) { 337 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 338 i * hub->eng_addr_distance, 0xffffffff); 339 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 340 i * hub->eng_addr_distance, 0x1f); 341 } 342 } 343 344 static int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 345 { 346 /* GART Enable. */ 347 gfxhub_v2_0_init_gart_aperture_regs(adev); 348 gfxhub_v2_0_init_system_aperture_regs(adev); 349 gfxhub_v2_0_init_tlb_regs(adev); 350 gfxhub_v2_0_init_cache_regs(adev); 351 352 gfxhub_v2_0_enable_system_domain(adev); 353 gfxhub_v2_0_disable_identity_aperture(adev); 354 gfxhub_v2_0_setup_vmid_config(adev); 355 gfxhub_v2_0_program_invalidation(adev); 356 357 return 0; 358 } 359 360 static void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 361 { 362 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 363 u32 tmp; 364 u32 i; 365 366 /* Disable all tables */ 367 for (i = 0; i < 16; i++) 368 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 369 i * hub->ctx_distance, 0); 370 371 /* Setup TLB control */ 372 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 373 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 374 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 375 ENABLE_ADVANCED_DRIVER_MODEL, 0); 376 WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 377 378 if (!amdgpu_sriov_vf(adev)) { 379 /* Setup L2 cache */ 380 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 381 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 382 } 383 } 384 385 /** 386 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 387 * 388 * @adev: amdgpu_device pointer 389 * @value: true redirects VM faults to the default page 390 */ 391 static void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 392 bool value) 393 { 394 u32 tmp; 395 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 396 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 397 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 399 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 401 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 403 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 405 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 406 value); 407 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 408 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 409 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 410 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 411 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 412 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 413 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 414 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 415 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 416 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 417 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 418 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 419 if (!value) { 420 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 421 CRASH_ON_NO_RETRY_FAULT, 1); 422 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 423 CRASH_ON_RETRY_FAULT, 1); 424 } 425 WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 426 } 427 428 static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = { 429 .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status, 430 .get_invalidate_req = gfxhub_v2_0_get_invalidate_req, 431 }; 432 433 static void gfxhub_v2_0_init(struct amdgpu_device *adev) 434 { 435 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 436 437 hub->ctx0_ptb_addr_lo32 = 438 SOC15_REG_OFFSET(GC, 0, 439 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 440 hub->ctx0_ptb_addr_hi32 = 441 SOC15_REG_OFFSET(GC, 0, 442 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 443 hub->vm_inv_eng0_sem = 444 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 445 hub->vm_inv_eng0_req = 446 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 447 hub->vm_inv_eng0_ack = 448 SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 449 hub->vm_context0_cntl = 450 SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 451 hub->vm_l2_pro_fault_status = 452 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 453 hub->vm_l2_pro_fault_cntl = 454 SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 455 456 hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 457 hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 458 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 459 hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 460 mmGCVM_INVALIDATE_ENG0_REQ; 461 hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 462 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 463 464 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 465 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 466 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 467 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 468 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 469 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 470 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 471 472 hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs; 473 } 474 475 const struct amdgpu_gfxhub_funcs gfxhub_v2_0_funcs = { 476 .get_fb_location = gfxhub_v2_0_get_fb_location, 477 .get_mc_fb_offset = gfxhub_v2_0_get_mc_fb_offset, 478 .setup_vm_pt_regs = gfxhub_v2_0_setup_vm_pt_regs, 479 .gart_enable = gfxhub_v2_0_gart_enable, 480 .gart_disable = gfxhub_v2_0_gart_disable, 481 .set_fault_enable_default = gfxhub_v2_0_set_fault_enable_default, 482 .init = gfxhub_v2_0_init, 483 }; 484