1770b93e9SHawking Zhang /* 2770b93e9SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3770b93e9SHawking Zhang * 4770b93e9SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5770b93e9SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6770b93e9SHawking Zhang * to deal in the Software without restriction, including without limitation 7770b93e9SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8770b93e9SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9770b93e9SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10770b93e9SHawking Zhang * 11770b93e9SHawking Zhang * The above copyright notice and this permission notice shall be included in 12770b93e9SHawking Zhang * all copies or substantial portions of the Software. 13770b93e9SHawking Zhang * 14770b93e9SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15770b93e9SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16770b93e9SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17770b93e9SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18770b93e9SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19770b93e9SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20770b93e9SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21770b93e9SHawking Zhang * 22770b93e9SHawking Zhang */ 23770b93e9SHawking Zhang 24770b93e9SHawking Zhang #include "amdgpu.h" 25770b93e9SHawking Zhang #include "gfxhub_v2_0.h" 26770b93e9SHawking Zhang 27770b93e9SHawking Zhang #include "gc/gc_10_1_0_offset.h" 28770b93e9SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 29770b93e9SHawking Zhang #include "gc/gc_10_1_0_default.h" 30770b93e9SHawking Zhang #include "navi10_enum.h" 31770b93e9SHawking Zhang 32770b93e9SHawking Zhang #include "soc15_common.h" 33770b93e9SHawking Zhang 34770b93e9SHawking Zhang u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 35770b93e9SHawking Zhang { 36770b93e9SHawking Zhang u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37770b93e9SHawking Zhang 38770b93e9SHawking Zhang base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39770b93e9SHawking Zhang base <<= 24; 40770b93e9SHawking Zhang 41770b93e9SHawking Zhang return base; 42770b93e9SHawking Zhang } 43770b93e9SHawking Zhang 44770b93e9SHawking Zhang u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 45770b93e9SHawking Zhang { 46770b93e9SHawking Zhang return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47770b93e9SHawking Zhang } 48770b93e9SHawking Zhang 49286b789eSYong Zhao void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 50286b789eSYong Zhao uint64_t page_table_base) 51770b93e9SHawking Zhang { 52286b789eSYong Zhao /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */ 53286b789eSYong Zhao int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 54286b789eSYong Zhao - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 55770b93e9SHawking Zhang 56286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 57286b789eSYong Zhao offset * vmid, lower_32_bits(page_table_base)); 58770b93e9SHawking Zhang 59286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 60286b789eSYong Zhao offset * vmid, upper_32_bits(page_table_base)); 61770b93e9SHawking Zhang } 62770b93e9SHawking Zhang 63770b93e9SHawking Zhang static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 64770b93e9SHawking Zhang { 65286b789eSYong Zhao uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 66286b789eSYong Zhao 67286b789eSYong Zhao gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 68770b93e9SHawking Zhang 69770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 12)); 71770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 44)); 73770b93e9SHawking Zhang 74770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 12)); 76770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 44)); 78770b93e9SHawking Zhang } 79770b93e9SHawking Zhang 80770b93e9SHawking Zhang static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 81770b93e9SHawking Zhang { 82770b93e9SHawking Zhang uint64_t value; 83770b93e9SHawking Zhang 848a43cf88STiecheng Zhou if (!amdgpu_sriov_vf(adev)) { 858a43cf88STiecheng Zhou /* 868a43cf88STiecheng Zhou * the new L1 policy will block SRIOV guest from writing 878a43cf88STiecheng Zhou * these regs, and they will be programed at host. 888a43cf88STiecheng Zhou * so skip programing these regs. 898a43cf88STiecheng Zhou */ 90770b93e9SHawking Zhang /* Disable AGP. */ 91770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 92770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 93770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 94770b93e9SHawking Zhang 95770b93e9SHawking Zhang /* Program the system aperture low logical page number. */ 96770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 97770b93e9SHawking Zhang adev->gmc.vram_start >> 18); 98770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 99770b93e9SHawking Zhang adev->gmc.vram_end >> 18); 100770b93e9SHawking Zhang 101770b93e9SHawking Zhang /* Set default page address. */ 102770b93e9SHawking Zhang value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 103770b93e9SHawking Zhang + adev->vm_manager.vram_base_offset; 104770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 105770b93e9SHawking Zhang (u32)(value >> 12)); 106770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 107770b93e9SHawking Zhang (u32)(value >> 44)); 1088a43cf88STiecheng Zhou } 109770b93e9SHawking Zhang 110770b93e9SHawking Zhang /* Program "protection fault". */ 111770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 112770b93e9SHawking Zhang (u32)(adev->dummy_page_addr >> 12)); 113770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 114770b93e9SHawking Zhang (u32)((u64)adev->dummy_page_addr >> 44)); 115770b93e9SHawking Zhang 116770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 117770b93e9SHawking Zhang ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 118770b93e9SHawking Zhang } 119770b93e9SHawking Zhang 120770b93e9SHawking Zhang 121770b93e9SHawking Zhang static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 122770b93e9SHawking Zhang { 123770b93e9SHawking Zhang uint32_t tmp; 124770b93e9SHawking Zhang 125770b93e9SHawking Zhang /* Setup TLB control */ 126770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 127770b93e9SHawking Zhang 128770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 129770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 130770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 131770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 1); 132770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 133770b93e9SHawking Zhang SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 134770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 135770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 136770b93e9SHawking Zhang MTYPE, MTYPE_UC); /* UC, uncached */ 137770b93e9SHawking Zhang 138770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 139770b93e9SHawking Zhang } 140770b93e9SHawking Zhang 141770b93e9SHawking Zhang static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 142770b93e9SHawking Zhang { 143770b93e9SHawking Zhang uint32_t tmp; 144770b93e9SHawking Zhang 14575ddb640SRohit Khaire /* These regs are not accessible for VF, PF will program these in SRIOV */ 14675ddb640SRohit Khaire if (amdgpu_sriov_vf(adev)) 14775ddb640SRohit Khaire return; 14875ddb640SRohit Khaire 149770b93e9SHawking Zhang /* Setup L2 cache */ 150770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 151770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 152770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 1533ebab625SJack Xiao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 1543ebab625SJack Xiao ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 155770b93e9SHawking Zhang /* XXX for emulation, Refer to closed source code.*/ 156770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 157770b93e9SHawking Zhang L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 1588b7d6157SYong Zhao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 159770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 160770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 161770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 162770b93e9SHawking Zhang 163770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 164770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 165770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 166770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 167770b93e9SHawking Zhang 168770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL3_DEFAULT; 16946203a50SAlex Deucher if (adev->gmc.translate_further) { 17046203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 17146203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 17246203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 17346203a50SAlex Deucher } else { 17446203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 17546203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 17646203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 17746203a50SAlex Deucher } 178770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 179770b93e9SHawking Zhang 180770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL4_DEFAULT; 181770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 182770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 183770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 184770b93e9SHawking Zhang } 185770b93e9SHawking Zhang 186770b93e9SHawking Zhang static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 187770b93e9SHawking Zhang { 188770b93e9SHawking Zhang uint32_t tmp; 189770b93e9SHawking Zhang 190770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 191770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 192770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 1937cae7061SFelix Kuehling tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 1947cae7061SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 195770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 196770b93e9SHawking Zhang } 197770b93e9SHawking Zhang 198770b93e9SHawking Zhang static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 199770b93e9SHawking Zhang { 200770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 201770b93e9SHawking Zhang 0xFFFFFFFF); 202770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 203770b93e9SHawking Zhang 0x0000000F); 204770b93e9SHawking Zhang 205770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 206770b93e9SHawking Zhang 0); 207770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 208770b93e9SHawking Zhang 0); 209770b93e9SHawking Zhang 210770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 211770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 212770b93e9SHawking Zhang 213770b93e9SHawking Zhang } 214770b93e9SHawking Zhang 215770b93e9SHawking Zhang static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 216770b93e9SHawking Zhang { 217770b93e9SHawking Zhang int i; 218770b93e9SHawking Zhang uint32_t tmp; 219770b93e9SHawking Zhang 220770b93e9SHawking Zhang for (i = 0; i <= 14; i++) { 221770b93e9SHawking Zhang tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 222770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 223770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 224770b93e9SHawking Zhang adev->vm_manager.num_level); 225770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 226770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 227770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 228770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 229770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 230770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 231770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 232770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 233770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 234770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 235770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 236770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 237770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 238770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 239770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 240770b93e9SHawking Zhang PAGE_TABLE_BLOCK_SIZE, 241770b93e9SHawking Zhang adev->vm_manager.block_size - 9); 242770b93e9SHawking Zhang /* Send no-retry XNACK on fault to suppress VM fault storm. */ 243770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 24475ee6487SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 24575ee6487SFelix Kuehling !amdgpu_noretry); 246770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); 247770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 248770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 249770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 250770b93e9SHawking Zhang lower_32_bits(adev->vm_manager.max_pfn - 1)); 251770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 252770b93e9SHawking Zhang upper_32_bits(adev->vm_manager.max_pfn - 1)); 253770b93e9SHawking Zhang } 254770b93e9SHawking Zhang } 255770b93e9SHawking Zhang 256770b93e9SHawking Zhang static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 257770b93e9SHawking Zhang { 258770b93e9SHawking Zhang unsigned i; 259770b93e9SHawking Zhang 260770b93e9SHawking Zhang for (i = 0 ; i < 18; ++i) { 261770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 262770b93e9SHawking Zhang 2 * i, 0xffffffff); 263770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 264770b93e9SHawking Zhang 2 * i, 0x1f); 265770b93e9SHawking Zhang } 266770b93e9SHawking Zhang } 267770b93e9SHawking Zhang 268770b93e9SHawking Zhang int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 269770b93e9SHawking Zhang { 270770b93e9SHawking Zhang /* GART Enable. */ 271770b93e9SHawking Zhang gfxhub_v2_0_init_gart_aperture_regs(adev); 272770b93e9SHawking Zhang gfxhub_v2_0_init_system_aperture_regs(adev); 273770b93e9SHawking Zhang gfxhub_v2_0_init_tlb_regs(adev); 274770b93e9SHawking Zhang gfxhub_v2_0_init_cache_regs(adev); 275770b93e9SHawking Zhang 276770b93e9SHawking Zhang gfxhub_v2_0_enable_system_domain(adev); 277770b93e9SHawking Zhang gfxhub_v2_0_disable_identity_aperture(adev); 278770b93e9SHawking Zhang gfxhub_v2_0_setup_vmid_config(adev); 279770b93e9SHawking Zhang gfxhub_v2_0_program_invalidation(adev); 280770b93e9SHawking Zhang 281770b93e9SHawking Zhang return 0; 282770b93e9SHawking Zhang } 283770b93e9SHawking Zhang 284770b93e9SHawking Zhang void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 285770b93e9SHawking Zhang { 286770b93e9SHawking Zhang u32 tmp; 287770b93e9SHawking Zhang u32 i; 288770b93e9SHawking Zhang 289770b93e9SHawking Zhang /* Disable all tables */ 290770b93e9SHawking Zhang for (i = 0; i < 16; i++) 291770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); 292770b93e9SHawking Zhang 293770b93e9SHawking Zhang /* Setup TLB control */ 294770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 295770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 296770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 297770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 0); 298770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 299770b93e9SHawking Zhang 30075ddb640SRohit Khaire if (!amdgpu_sriov_vf(adev)) { 301770b93e9SHawking Zhang /* Setup L2 cache */ 302770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 303770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 304770b93e9SHawking Zhang } 30575ddb640SRohit Khaire } 306770b93e9SHawking Zhang 307770b93e9SHawking Zhang /** 308770b93e9SHawking Zhang * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 309770b93e9SHawking Zhang * 310770b93e9SHawking Zhang * @adev: amdgpu_device pointer 311770b93e9SHawking Zhang * @value: true redirects VM faults to the default page 312770b93e9SHawking Zhang */ 313770b93e9SHawking Zhang void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 314770b93e9SHawking Zhang bool value) 315770b93e9SHawking Zhang { 316770b93e9SHawking Zhang u32 tmp; 317770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 318770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 319770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 320770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 321770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 322770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 323770b93e9SHawking Zhang PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 324770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 325770b93e9SHawking Zhang PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 326770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 327770b93e9SHawking Zhang TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 328770b93e9SHawking Zhang value); 329770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 330770b93e9SHawking Zhang NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 331770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 332770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 333770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 334770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 335770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 336770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 337770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 338770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 339770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 340770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 341770b93e9SHawking Zhang if (!value) { 342770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 343770b93e9SHawking Zhang CRASH_ON_NO_RETRY_FAULT, 1); 344770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 345770b93e9SHawking Zhang CRASH_ON_RETRY_FAULT, 1); 346770b93e9SHawking Zhang } 347770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 348770b93e9SHawking Zhang } 349770b93e9SHawking Zhang 350770b93e9SHawking Zhang void gfxhub_v2_0_init(struct amdgpu_device *adev) 351770b93e9SHawking Zhang { 352a2d15ed7SLe Ma struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 353770b93e9SHawking Zhang 354770b93e9SHawking Zhang hub->ctx0_ptb_addr_lo32 = 355770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 356770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 357770b93e9SHawking Zhang hub->ctx0_ptb_addr_hi32 = 358770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 359770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 3606c2c8972Schangzhu hub->vm_inv_eng0_sem = 3616c2c8972Schangzhu SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 362770b93e9SHawking Zhang hub->vm_inv_eng0_req = 363770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 364770b93e9SHawking Zhang hub->vm_inv_eng0_ack = 365770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 366770b93e9SHawking Zhang hub->vm_context0_cntl = 367770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 368770b93e9SHawking Zhang hub->vm_l2_pro_fault_status = 369770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 370770b93e9SHawking Zhang hub->vm_l2_pro_fault_cntl = 371770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 372770b93e9SHawking Zhang } 373