1770b93e9SHawking Zhang /* 2770b93e9SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3770b93e9SHawking Zhang * 4770b93e9SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5770b93e9SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6770b93e9SHawking Zhang * to deal in the Software without restriction, including without limitation 7770b93e9SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8770b93e9SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9770b93e9SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10770b93e9SHawking Zhang * 11770b93e9SHawking Zhang * The above copyright notice and this permission notice shall be included in 12770b93e9SHawking Zhang * all copies or substantial portions of the Software. 13770b93e9SHawking Zhang * 14770b93e9SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15770b93e9SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16770b93e9SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17770b93e9SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18770b93e9SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19770b93e9SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20770b93e9SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21770b93e9SHawking Zhang * 22770b93e9SHawking Zhang */ 23770b93e9SHawking Zhang 24770b93e9SHawking Zhang #include "amdgpu.h" 25770b93e9SHawking Zhang #include "gfxhub_v2_0.h" 26770b93e9SHawking Zhang 27770b93e9SHawking Zhang #include "gc/gc_10_1_0_offset.h" 28770b93e9SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 29770b93e9SHawking Zhang #include "gc/gc_10_1_0_default.h" 30770b93e9SHawking Zhang #include "navi10_enum.h" 31770b93e9SHawking Zhang 32770b93e9SHawking Zhang #include "soc15_common.h" 33770b93e9SHawking Zhang 34770b93e9SHawking Zhang u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 35770b93e9SHawking Zhang { 36770b93e9SHawking Zhang u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37770b93e9SHawking Zhang 38770b93e9SHawking Zhang base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39770b93e9SHawking Zhang base <<= 24; 40770b93e9SHawking Zhang 41770b93e9SHawking Zhang return base; 42770b93e9SHawking Zhang } 43770b93e9SHawking Zhang 44770b93e9SHawking Zhang u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 45770b93e9SHawking Zhang { 46770b93e9SHawking Zhang return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47770b93e9SHawking Zhang } 48770b93e9SHawking Zhang 49770b93e9SHawking Zhang static void gfxhub_v2_0_init_gart_pt_regs(struct amdgpu_device *adev) 50770b93e9SHawking Zhang { 51770b93e9SHawking Zhang uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); 52770b93e9SHawking Zhang 53770b93e9SHawking Zhang 54770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 55770b93e9SHawking Zhang lower_32_bits(value)); 56770b93e9SHawking Zhang 57770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 58770b93e9SHawking Zhang upper_32_bits(value)); 59770b93e9SHawking Zhang } 60770b93e9SHawking Zhang 61770b93e9SHawking Zhang static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 62770b93e9SHawking Zhang { 63770b93e9SHawking Zhang gfxhub_v2_0_init_gart_pt_regs(adev); 64770b93e9SHawking Zhang 65770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 66770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 12)); 67770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 68770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 44)); 69770b93e9SHawking Zhang 70770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 71770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 12)); 72770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 73770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 44)); 74770b93e9SHawking Zhang } 75770b93e9SHawking Zhang 76770b93e9SHawking Zhang static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 77770b93e9SHawking Zhang { 78770b93e9SHawking Zhang uint64_t value; 79770b93e9SHawking Zhang 80770b93e9SHawking Zhang /* Disable AGP. */ 81770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 82770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 83770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 84770b93e9SHawking Zhang 85770b93e9SHawking Zhang /* Program the system aperture low logical page number. */ 86770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 87770b93e9SHawking Zhang adev->gmc.vram_start >> 18); 88770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 89770b93e9SHawking Zhang adev->gmc.vram_end >> 18); 90770b93e9SHawking Zhang 91770b93e9SHawking Zhang /* Set default page address. */ 92770b93e9SHawking Zhang value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 93770b93e9SHawking Zhang + adev->vm_manager.vram_base_offset; 94770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 95770b93e9SHawking Zhang (u32)(value >> 12)); 96770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 97770b93e9SHawking Zhang (u32)(value >> 44)); 98770b93e9SHawking Zhang 99770b93e9SHawking Zhang /* Program "protection fault". */ 100770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 101770b93e9SHawking Zhang (u32)(adev->dummy_page_addr >> 12)); 102770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 103770b93e9SHawking Zhang (u32)((u64)adev->dummy_page_addr >> 44)); 104770b93e9SHawking Zhang 105770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 106770b93e9SHawking Zhang ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 107770b93e9SHawking Zhang } 108770b93e9SHawking Zhang 109770b93e9SHawking Zhang 110770b93e9SHawking Zhang static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 111770b93e9SHawking Zhang { 112770b93e9SHawking Zhang uint32_t tmp; 113770b93e9SHawking Zhang 114770b93e9SHawking Zhang /* Setup TLB control */ 115770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 116770b93e9SHawking Zhang 117770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 118770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 119770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 120770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 1); 121770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 122770b93e9SHawking Zhang SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 123770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 124770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 125770b93e9SHawking Zhang MTYPE, MTYPE_UC); /* UC, uncached */ 126770b93e9SHawking Zhang 127770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 128770b93e9SHawking Zhang } 129770b93e9SHawking Zhang 130770b93e9SHawking Zhang static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 131770b93e9SHawking Zhang { 132770b93e9SHawking Zhang uint32_t tmp; 133770b93e9SHawking Zhang 134770b93e9SHawking Zhang /* Setup L2 cache */ 135770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 136770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 137770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 138770b93e9SHawking Zhang 139770b93e9SHawking Zhang /* XXX for emulation, Refer to closed source code.*/ 140770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 141770b93e9SHawking Zhang L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 142770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 143770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 144770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 145770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 146770b93e9SHawking Zhang 147770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 148770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 149770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 150770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 151770b93e9SHawking Zhang 152770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL3_DEFAULT; 153770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 154770b93e9SHawking Zhang 155770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL4_DEFAULT; 156770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 157770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 158770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 159770b93e9SHawking Zhang } 160770b93e9SHawking Zhang 161770b93e9SHawking Zhang static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 162770b93e9SHawking Zhang { 163770b93e9SHawking Zhang uint32_t tmp; 164770b93e9SHawking Zhang 165770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 166770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 167770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 168770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 169770b93e9SHawking Zhang } 170770b93e9SHawking Zhang 171770b93e9SHawking Zhang static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 172770b93e9SHawking Zhang { 173770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 174770b93e9SHawking Zhang 0xFFFFFFFF); 175770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 176770b93e9SHawking Zhang 0x0000000F); 177770b93e9SHawking Zhang 178770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 179770b93e9SHawking Zhang 0); 180770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 181770b93e9SHawking Zhang 0); 182770b93e9SHawking Zhang 183770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 184770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 185770b93e9SHawking Zhang 186770b93e9SHawking Zhang } 187770b93e9SHawking Zhang 188770b93e9SHawking Zhang static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 189770b93e9SHawking Zhang { 190770b93e9SHawking Zhang int i; 191770b93e9SHawking Zhang uint32_t tmp; 192770b93e9SHawking Zhang 193770b93e9SHawking Zhang for (i = 0; i <= 14; i++) { 194770b93e9SHawking Zhang tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 195770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 196770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 197770b93e9SHawking Zhang adev->vm_manager.num_level); 198770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 199770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 200770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 201770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 202770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 203770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 204770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 205770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 206770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 207770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 208770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 209770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 210770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 211770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 212770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 213770b93e9SHawking Zhang PAGE_TABLE_BLOCK_SIZE, 214770b93e9SHawking Zhang adev->vm_manager.block_size - 9); 215770b93e9SHawking Zhang /* Send no-retry XNACK on fault to suppress VM fault storm. */ 216770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 217770b93e9SHawking Zhang RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 218770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); 219770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 220770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 221770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 222770b93e9SHawking Zhang lower_32_bits(adev->vm_manager.max_pfn - 1)); 223770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 224770b93e9SHawking Zhang upper_32_bits(adev->vm_manager.max_pfn - 1)); 225770b93e9SHawking Zhang } 226770b93e9SHawking Zhang } 227770b93e9SHawking Zhang 228770b93e9SHawking Zhang static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 229770b93e9SHawking Zhang { 230770b93e9SHawking Zhang unsigned i; 231770b93e9SHawking Zhang 232770b93e9SHawking Zhang for (i = 0 ; i < 18; ++i) { 233770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 234770b93e9SHawking Zhang 2 * i, 0xffffffff); 235770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 236770b93e9SHawking Zhang 2 * i, 0x1f); 237770b93e9SHawking Zhang } 238770b93e9SHawking Zhang } 239770b93e9SHawking Zhang 240770b93e9SHawking Zhang int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 241770b93e9SHawking Zhang { 242770b93e9SHawking Zhang if (amdgpu_sriov_vf(adev)) { 243770b93e9SHawking Zhang /* 244770b93e9SHawking Zhang * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 245770b93e9SHawking Zhang * VF copy registers so vbios post doesn't program them, for 246770b93e9SHawking Zhang * SRIOV driver need to program them 247770b93e9SHawking Zhang */ 248770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, 249770b93e9SHawking Zhang adev->gmc.vram_start >> 24); 250770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, 251770b93e9SHawking Zhang adev->gmc.vram_end >> 24); 252770b93e9SHawking Zhang } 253770b93e9SHawking Zhang 254770b93e9SHawking Zhang /* GART Enable. */ 255770b93e9SHawking Zhang gfxhub_v2_0_init_gart_aperture_regs(adev); 256770b93e9SHawking Zhang gfxhub_v2_0_init_system_aperture_regs(adev); 257770b93e9SHawking Zhang gfxhub_v2_0_init_tlb_regs(adev); 258770b93e9SHawking Zhang gfxhub_v2_0_init_cache_regs(adev); 259770b93e9SHawking Zhang 260770b93e9SHawking Zhang gfxhub_v2_0_enable_system_domain(adev); 261770b93e9SHawking Zhang gfxhub_v2_0_disable_identity_aperture(adev); 262770b93e9SHawking Zhang gfxhub_v2_0_setup_vmid_config(adev); 263770b93e9SHawking Zhang gfxhub_v2_0_program_invalidation(adev); 264770b93e9SHawking Zhang 265770b93e9SHawking Zhang return 0; 266770b93e9SHawking Zhang } 267770b93e9SHawking Zhang 268770b93e9SHawking Zhang void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 269770b93e9SHawking Zhang { 270770b93e9SHawking Zhang u32 tmp; 271770b93e9SHawking Zhang u32 i; 272770b93e9SHawking Zhang 273770b93e9SHawking Zhang /* Disable all tables */ 274770b93e9SHawking Zhang for (i = 0; i < 16; i++) 275770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); 276770b93e9SHawking Zhang 277770b93e9SHawking Zhang /* Setup TLB control */ 278770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 279770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 280770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 281770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 0); 282770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 283770b93e9SHawking Zhang 284770b93e9SHawking Zhang /* Setup L2 cache */ 285770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 286770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 287770b93e9SHawking Zhang } 288770b93e9SHawking Zhang 289770b93e9SHawking Zhang /** 290770b93e9SHawking Zhang * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 291770b93e9SHawking Zhang * 292770b93e9SHawking Zhang * @adev: amdgpu_device pointer 293770b93e9SHawking Zhang * @value: true redirects VM faults to the default page 294770b93e9SHawking Zhang */ 295770b93e9SHawking Zhang void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 296770b93e9SHawking Zhang bool value) 297770b93e9SHawking Zhang { 298770b93e9SHawking Zhang u32 tmp; 299770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 300770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 301770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 302770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 303770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 304770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 305770b93e9SHawking Zhang PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 306770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 307770b93e9SHawking Zhang PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 308770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 309770b93e9SHawking Zhang TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 310770b93e9SHawking Zhang value); 311770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 312770b93e9SHawking Zhang NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 314770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 316770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 318770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 319770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 320770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 321770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 322770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 323770b93e9SHawking Zhang if (!value) { 324770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 325770b93e9SHawking Zhang CRASH_ON_NO_RETRY_FAULT, 1); 326770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 327770b93e9SHawking Zhang CRASH_ON_RETRY_FAULT, 1); 328770b93e9SHawking Zhang } 329770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 330770b93e9SHawking Zhang } 331770b93e9SHawking Zhang 332770b93e9SHawking Zhang void gfxhub_v2_0_init(struct amdgpu_device *adev) 333770b93e9SHawking Zhang { 334770b93e9SHawking Zhang struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; 335770b93e9SHawking Zhang 336770b93e9SHawking Zhang hub->ctx0_ptb_addr_lo32 = 337770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 338770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 339770b93e9SHawking Zhang hub->ctx0_ptb_addr_hi32 = 340770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 341770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 342770b93e9SHawking Zhang hub->vm_inv_eng0_req = 343770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 344770b93e9SHawking Zhang hub->vm_inv_eng0_ack = 345770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 346770b93e9SHawking Zhang hub->vm_context0_cntl = 347770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 348770b93e9SHawking Zhang hub->vm_l2_pro_fault_status = 349770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 350770b93e9SHawking Zhang hub->vm_l2_pro_fault_cntl = 351770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 352770b93e9SHawking Zhang } 353