1770b93e9SHawking Zhang /* 2770b93e9SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3770b93e9SHawking Zhang * 4770b93e9SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5770b93e9SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6770b93e9SHawking Zhang * to deal in the Software without restriction, including without limitation 7770b93e9SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8770b93e9SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9770b93e9SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10770b93e9SHawking Zhang * 11770b93e9SHawking Zhang * The above copyright notice and this permission notice shall be included in 12770b93e9SHawking Zhang * all copies or substantial portions of the Software. 13770b93e9SHawking Zhang * 14770b93e9SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15770b93e9SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16770b93e9SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17770b93e9SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18770b93e9SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19770b93e9SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20770b93e9SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21770b93e9SHawking Zhang * 22770b93e9SHawking Zhang */ 23770b93e9SHawking Zhang 24770b93e9SHawking Zhang #include "amdgpu.h" 25770b93e9SHawking Zhang #include "gfxhub_v2_0.h" 26770b93e9SHawking Zhang 27770b93e9SHawking Zhang #include "gc/gc_10_1_0_offset.h" 28770b93e9SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 29770b93e9SHawking Zhang #include "gc/gc_10_1_0_default.h" 30770b93e9SHawking Zhang #include "navi10_enum.h" 31770b93e9SHawking Zhang 32770b93e9SHawking Zhang #include "soc15_common.h" 33770b93e9SHawking Zhang 34770b93e9SHawking Zhang u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 35770b93e9SHawking Zhang { 36770b93e9SHawking Zhang u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 37770b93e9SHawking Zhang 38770b93e9SHawking Zhang base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 39770b93e9SHawking Zhang base <<= 24; 40770b93e9SHawking Zhang 41770b93e9SHawking Zhang return base; 42770b93e9SHawking Zhang } 43770b93e9SHawking Zhang 44770b93e9SHawking Zhang u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 45770b93e9SHawking Zhang { 46770b93e9SHawking Zhang return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 47770b93e9SHawking Zhang } 48770b93e9SHawking Zhang 49286b789eSYong Zhao void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 50286b789eSYong Zhao uint64_t page_table_base) 51770b93e9SHawking Zhang { 521e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 53770b93e9SHawking Zhang 54286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 551e40eebeSHuang Rui hub->ctx_addr_distance * vmid, 561e40eebeSHuang Rui lower_32_bits(page_table_base)); 57770b93e9SHawking Zhang 58286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 591e40eebeSHuang Rui hub->ctx_addr_distance * vmid, 601e40eebeSHuang Rui upper_32_bits(page_table_base)); 61770b93e9SHawking Zhang } 62770b93e9SHawking Zhang 63770b93e9SHawking Zhang static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 64770b93e9SHawking Zhang { 65286b789eSYong Zhao uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 66286b789eSYong Zhao 67286b789eSYong Zhao gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 68770b93e9SHawking Zhang 69770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 12)); 71770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 44)); 73770b93e9SHawking Zhang 74770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 12)); 76770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 44)); 78770b93e9SHawking Zhang } 79770b93e9SHawking Zhang 80770b93e9SHawking Zhang static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 81770b93e9SHawking Zhang { 82770b93e9SHawking Zhang uint64_t value; 83770b93e9SHawking Zhang 848a43cf88STiecheng Zhou if (!amdgpu_sriov_vf(adev)) { 858a43cf88STiecheng Zhou /* 868a43cf88STiecheng Zhou * the new L1 policy will block SRIOV guest from writing 878a43cf88STiecheng Zhou * these regs, and they will be programed at host. 888a43cf88STiecheng Zhou * so skip programing these regs. 898a43cf88STiecheng Zhou */ 90770b93e9SHawking Zhang /* Disable AGP. */ 91770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 92770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 93770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 94770b93e9SHawking Zhang 95770b93e9SHawking Zhang /* Program the system aperture low logical page number. */ 96770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 97770b93e9SHawking Zhang adev->gmc.vram_start >> 18); 98770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 99770b93e9SHawking Zhang adev->gmc.vram_end >> 18); 100770b93e9SHawking Zhang 101770b93e9SHawking Zhang /* Set default page address. */ 102770b93e9SHawking Zhang value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 103770b93e9SHawking Zhang + adev->vm_manager.vram_base_offset; 104770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 105770b93e9SHawking Zhang (u32)(value >> 12)); 106770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 107770b93e9SHawking Zhang (u32)(value >> 44)); 1088a43cf88STiecheng Zhou } 109770b93e9SHawking Zhang 110770b93e9SHawking Zhang /* Program "protection fault". */ 111770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 112770b93e9SHawking Zhang (u32)(adev->dummy_page_addr >> 12)); 113770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 114770b93e9SHawking Zhang (u32)((u64)adev->dummy_page_addr >> 44)); 115770b93e9SHawking Zhang 116770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 117770b93e9SHawking Zhang ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 118770b93e9SHawking Zhang } 119770b93e9SHawking Zhang 120770b93e9SHawking Zhang 121770b93e9SHawking Zhang static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 122770b93e9SHawking Zhang { 123770b93e9SHawking Zhang uint32_t tmp; 124770b93e9SHawking Zhang 125770b93e9SHawking Zhang /* Setup TLB control */ 126770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 127770b93e9SHawking Zhang 128770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 129770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 130770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 131770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 1); 132770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 133770b93e9SHawking Zhang SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 134770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 135770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 136770b93e9SHawking Zhang MTYPE, MTYPE_UC); /* UC, uncached */ 137770b93e9SHawking Zhang 138770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 139770b93e9SHawking Zhang } 140770b93e9SHawking Zhang 141770b93e9SHawking Zhang static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 142770b93e9SHawking Zhang { 143770b93e9SHawking Zhang uint32_t tmp; 144770b93e9SHawking Zhang 14575ddb640SRohit Khaire /* These regs are not accessible for VF, PF will program these in SRIOV */ 14675ddb640SRohit Khaire if (amdgpu_sriov_vf(adev)) 14775ddb640SRohit Khaire return; 14875ddb640SRohit Khaire 149770b93e9SHawking Zhang /* Setup L2 cache */ 150770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 151770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 152770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 1533ebab625SJack Xiao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 1543ebab625SJack Xiao ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 155770b93e9SHawking Zhang /* XXX for emulation, Refer to closed source code.*/ 156770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 157770b93e9SHawking Zhang L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 1588b7d6157SYong Zhao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 159770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 160770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 161770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 162770b93e9SHawking Zhang 163770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 164770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 165770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 166770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 167770b93e9SHawking Zhang 168770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL3_DEFAULT; 16946203a50SAlex Deucher if (adev->gmc.translate_further) { 17046203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 17146203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 17246203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 17346203a50SAlex Deucher } else { 17446203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 17546203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 17646203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 17746203a50SAlex Deucher } 178770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 179770b93e9SHawking Zhang 180770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL4_DEFAULT; 181770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 182770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 183770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 184ec683759SAlex Deucher 185ec683759SAlex Deucher tmp = mmGCVM_L2_CNTL5_DEFAULT; 186ec683759SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 187ec683759SAlex Deucher WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 188770b93e9SHawking Zhang } 189770b93e9SHawking Zhang 190770b93e9SHawking Zhang static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 191770b93e9SHawking Zhang { 192770b93e9SHawking Zhang uint32_t tmp; 193770b93e9SHawking Zhang 194770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 195770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 196770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 1977cae7061SFelix Kuehling tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 1987cae7061SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 199770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 200770b93e9SHawking Zhang } 201770b93e9SHawking Zhang 202770b93e9SHawking Zhang static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 203770b93e9SHawking Zhang { 204770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 205770b93e9SHawking Zhang 0xFFFFFFFF); 206770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 207770b93e9SHawking Zhang 0x0000000F); 208770b93e9SHawking Zhang 209770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 210770b93e9SHawking Zhang 0); 211770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 212770b93e9SHawking Zhang 0); 213770b93e9SHawking Zhang 214770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 215770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 216770b93e9SHawking Zhang 217770b93e9SHawking Zhang } 218770b93e9SHawking Zhang 219770b93e9SHawking Zhang static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 220770b93e9SHawking Zhang { 2211e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 222770b93e9SHawking Zhang int i; 223770b93e9SHawking Zhang uint32_t tmp; 224770b93e9SHawking Zhang 225770b93e9SHawking Zhang for (i = 0; i <= 14; i++) { 226770b93e9SHawking Zhang tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 227770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 228770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 229770b93e9SHawking Zhang adev->vm_manager.num_level); 230770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 231770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 232770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 233770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 234770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 235770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 236770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 237770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 238770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 239770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 240770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 241770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 242770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 243770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 244770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 245770b93e9SHawking Zhang PAGE_TABLE_BLOCK_SIZE, 246770b93e9SHawking Zhang adev->vm_manager.block_size - 9); 247770b93e9SHawking Zhang /* Send no-retry XNACK on fault to suppress VM fault storm. */ 248770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 24975ee6487SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 25075ee6487SFelix Kuehling !amdgpu_noretry); 2511e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 2521e40eebeSHuang Rui i * hub->ctx_distance, tmp); 2531e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 2541e40eebeSHuang Rui i * hub->ctx_addr_distance, 0); 2551e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 2561e40eebeSHuang Rui i * hub->ctx_addr_distance, 0); 2571e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 2581e40eebeSHuang Rui i * hub->ctx_addr_distance, 259770b93e9SHawking Zhang lower_32_bits(adev->vm_manager.max_pfn - 1)); 2601e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 2611e40eebeSHuang Rui i * hub->ctx_addr_distance, 262770b93e9SHawking Zhang upper_32_bits(adev->vm_manager.max_pfn - 1)); 263770b93e9SHawking Zhang } 264770b93e9SHawking Zhang } 265770b93e9SHawking Zhang 266770b93e9SHawking Zhang static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 267770b93e9SHawking Zhang { 2681e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 269770b93e9SHawking Zhang unsigned i; 270770b93e9SHawking Zhang 271770b93e9SHawking Zhang for (i = 0 ; i < 18; ++i) { 272770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 2731e40eebeSHuang Rui i * hub->eng_addr_distance, 0xffffffff); 274770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 2751e40eebeSHuang Rui i * hub->eng_addr_distance, 0x1f); 276770b93e9SHawking Zhang } 277770b93e9SHawking Zhang } 278770b93e9SHawking Zhang 279770b93e9SHawking Zhang int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 280770b93e9SHawking Zhang { 281770b93e9SHawking Zhang /* GART Enable. */ 282770b93e9SHawking Zhang gfxhub_v2_0_init_gart_aperture_regs(adev); 283770b93e9SHawking Zhang gfxhub_v2_0_init_system_aperture_regs(adev); 284770b93e9SHawking Zhang gfxhub_v2_0_init_tlb_regs(adev); 285770b93e9SHawking Zhang gfxhub_v2_0_init_cache_regs(adev); 286770b93e9SHawking Zhang 287770b93e9SHawking Zhang gfxhub_v2_0_enable_system_domain(adev); 288770b93e9SHawking Zhang gfxhub_v2_0_disable_identity_aperture(adev); 289770b93e9SHawking Zhang gfxhub_v2_0_setup_vmid_config(adev); 290770b93e9SHawking Zhang gfxhub_v2_0_program_invalidation(adev); 291770b93e9SHawking Zhang 292770b93e9SHawking Zhang return 0; 293770b93e9SHawking Zhang } 294770b93e9SHawking Zhang 295770b93e9SHawking Zhang void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 296770b93e9SHawking Zhang { 2971e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 298770b93e9SHawking Zhang u32 tmp; 299770b93e9SHawking Zhang u32 i; 300770b93e9SHawking Zhang 301770b93e9SHawking Zhang /* Disable all tables */ 302770b93e9SHawking Zhang for (i = 0; i < 16; i++) 3031e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 3041e40eebeSHuang Rui i * hub->ctx_distance, 0); 305770b93e9SHawking Zhang 306770b93e9SHawking Zhang /* Setup TLB control */ 307770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 308770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 309770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 310770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 0); 311770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 312770b93e9SHawking Zhang 31375ddb640SRohit Khaire if (!amdgpu_sriov_vf(adev)) { 314770b93e9SHawking Zhang /* Setup L2 cache */ 315770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 316770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 317770b93e9SHawking Zhang } 31875ddb640SRohit Khaire } 319770b93e9SHawking Zhang 320770b93e9SHawking Zhang /** 321770b93e9SHawking Zhang * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 322770b93e9SHawking Zhang * 323770b93e9SHawking Zhang * @adev: amdgpu_device pointer 324770b93e9SHawking Zhang * @value: true redirects VM faults to the default page 325770b93e9SHawking Zhang */ 326770b93e9SHawking Zhang void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 327770b93e9SHawking Zhang bool value) 328770b93e9SHawking Zhang { 329770b93e9SHawking Zhang u32 tmp; 330770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 331770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 332770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 333770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 334770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 335770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 336770b93e9SHawking Zhang PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 337770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 338770b93e9SHawking Zhang PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 339770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 340770b93e9SHawking Zhang TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 341770b93e9SHawking Zhang value); 342770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 343770b93e9SHawking Zhang NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 344770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 345770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 346770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 347770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 348770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 349770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 350770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 351770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 352770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 353770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 354770b93e9SHawking Zhang if (!value) { 355770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 356770b93e9SHawking Zhang CRASH_ON_NO_RETRY_FAULT, 1); 357770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 358770b93e9SHawking Zhang CRASH_ON_RETRY_FAULT, 1); 359770b93e9SHawking Zhang } 360770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 361770b93e9SHawking Zhang } 362770b93e9SHawking Zhang 363770b93e9SHawking Zhang void gfxhub_v2_0_init(struct amdgpu_device *adev) 364770b93e9SHawking Zhang { 365a2d15ed7SLe Ma struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 366770b93e9SHawking Zhang 367770b93e9SHawking Zhang hub->ctx0_ptb_addr_lo32 = 368770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 369770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 370770b93e9SHawking Zhang hub->ctx0_ptb_addr_hi32 = 371770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 372770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 3736c2c8972Schangzhu hub->vm_inv_eng0_sem = 3746c2c8972Schangzhu SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 375770b93e9SHawking Zhang hub->vm_inv_eng0_req = 376770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 377770b93e9SHawking Zhang hub->vm_inv_eng0_ack = 378770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 379770b93e9SHawking Zhang hub->vm_context0_cntl = 380770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 381770b93e9SHawking Zhang hub->vm_l2_pro_fault_status = 382770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 383770b93e9SHawking Zhang hub->vm_l2_pro_fault_cntl = 384770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 3851f9d56c3SHuang Rui 3861f9d56c3SHuang Rui hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 3871f9d56c3SHuang Rui hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 3881f9d56c3SHuang Rui mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 3891f9d56c3SHuang Rui hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 3901f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_REQ; 3911f9d56c3SHuang Rui hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 3921f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 3935befb6fcSHuang Rui 3945befb6fcSHuang Rui hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3955befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3965befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3975befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3985befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 3995befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4005befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 401770b93e9SHawking Zhang } 402