1770b93e9SHawking Zhang /* 2770b93e9SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3770b93e9SHawking Zhang * 4770b93e9SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5770b93e9SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6770b93e9SHawking Zhang * to deal in the Software without restriction, including without limitation 7770b93e9SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8770b93e9SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9770b93e9SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10770b93e9SHawking Zhang * 11770b93e9SHawking Zhang * The above copyright notice and this permission notice shall be included in 12770b93e9SHawking Zhang * all copies or substantial portions of the Software. 13770b93e9SHawking Zhang * 14770b93e9SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15770b93e9SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16770b93e9SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17770b93e9SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18770b93e9SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19770b93e9SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20770b93e9SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21770b93e9SHawking Zhang * 22770b93e9SHawking Zhang */ 23770b93e9SHawking Zhang 24770b93e9SHawking Zhang #include "amdgpu.h" 25770b93e9SHawking Zhang #include "gfxhub_v2_0.h" 26770b93e9SHawking Zhang 27770b93e9SHawking Zhang #include "gc/gc_10_1_0_offset.h" 28770b93e9SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 29770b93e9SHawking Zhang #include "gc/gc_10_1_0_default.h" 30770b93e9SHawking Zhang #include "navi10_enum.h" 31770b93e9SHawking Zhang 32770b93e9SHawking Zhang #include "soc15_common.h" 33770b93e9SHawking Zhang 342577db91SHuang Rui static void 352577db91SHuang Rui gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 362577db91SHuang Rui uint32_t status) 372577db91SHuang Rui { 382577db91SHuang Rui dev_err(adev->dev, 392577db91SHuang Rui "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 402577db91SHuang Rui status); 412577db91SHuang Rui dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n", 422577db91SHuang Rui REG_GET_FIELD(status, 432577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, CID)); 442577db91SHuang Rui dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 452577db91SHuang Rui REG_GET_FIELD(status, 462577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 472577db91SHuang Rui dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 482577db91SHuang Rui REG_GET_FIELD(status, 492577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 502577db91SHuang Rui dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 512577db91SHuang Rui REG_GET_FIELD(status, 522577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 532577db91SHuang Rui dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 542577db91SHuang Rui REG_GET_FIELD(status, 552577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 562577db91SHuang Rui dev_err(adev->dev, "\t RW: 0x%lx\n", 572577db91SHuang Rui REG_GET_FIELD(status, 582577db91SHuang Rui GCVM_L2_PROTECTION_FAULT_STATUS, RW)); 592577db91SHuang Rui } 602577db91SHuang Rui 61770b93e9SHawking Zhang u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev) 62770b93e9SHawking Zhang { 63770b93e9SHawking Zhang u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE); 64770b93e9SHawking Zhang 65770b93e9SHawking Zhang base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 66770b93e9SHawking Zhang base <<= 24; 67770b93e9SHawking Zhang 68770b93e9SHawking Zhang return base; 69770b93e9SHawking Zhang } 70770b93e9SHawking Zhang 71770b93e9SHawking Zhang u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev) 72770b93e9SHawking Zhang { 73770b93e9SHawking Zhang return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24; 74770b93e9SHawking Zhang } 75770b93e9SHawking Zhang 76286b789eSYong Zhao void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 77286b789eSYong Zhao uint64_t page_table_base) 78770b93e9SHawking Zhang { 791e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 80770b93e9SHawking Zhang 81286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 821e40eebeSHuang Rui hub->ctx_addr_distance * vmid, 831e40eebeSHuang Rui lower_32_bits(page_table_base)); 84770b93e9SHawking Zhang 85286b789eSYong Zhao WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 861e40eebeSHuang Rui hub->ctx_addr_distance * vmid, 871e40eebeSHuang Rui upper_32_bits(page_table_base)); 88770b93e9SHawking Zhang } 89770b93e9SHawking Zhang 90770b93e9SHawking Zhang static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) 91770b93e9SHawking Zhang { 92286b789eSYong Zhao uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 93286b789eSYong Zhao 94286b789eSYong Zhao gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); 95770b93e9SHawking Zhang 96770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 97770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 12)); 98770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 99770b93e9SHawking Zhang (u32)(adev->gmc.gart_start >> 44)); 100770b93e9SHawking Zhang 101770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 102770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 12)); 103770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 104770b93e9SHawking Zhang (u32)(adev->gmc.gart_end >> 44)); 105770b93e9SHawking Zhang } 106770b93e9SHawking Zhang 107770b93e9SHawking Zhang static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev) 108770b93e9SHawking Zhang { 109770b93e9SHawking Zhang uint64_t value; 110770b93e9SHawking Zhang 1118a43cf88STiecheng Zhou if (!amdgpu_sriov_vf(adev)) { 1128a43cf88STiecheng Zhou /* 1138a43cf88STiecheng Zhou * the new L1 policy will block SRIOV guest from writing 1148a43cf88STiecheng Zhou * these regs, and they will be programed at host. 1158a43cf88STiecheng Zhou * so skip programing these regs. 1168a43cf88STiecheng Zhou */ 117770b93e9SHawking Zhang /* Disable AGP. */ 118770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 119770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); 120770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); 121770b93e9SHawking Zhang 122770b93e9SHawking Zhang /* Program the system aperture low logical page number. */ 123770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 124770b93e9SHawking Zhang adev->gmc.vram_start >> 18); 125770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 126770b93e9SHawking Zhang adev->gmc.vram_end >> 18); 127770b93e9SHawking Zhang 128770b93e9SHawking Zhang /* Set default page address. */ 129770b93e9SHawking Zhang value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 130770b93e9SHawking Zhang + adev->vm_manager.vram_base_offset; 131770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 132770b93e9SHawking Zhang (u32)(value >> 12)); 133770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 134770b93e9SHawking Zhang (u32)(value >> 44)); 1358a43cf88STiecheng Zhou } 136770b93e9SHawking Zhang 137770b93e9SHawking Zhang /* Program "protection fault". */ 138770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 139770b93e9SHawking Zhang (u32)(adev->dummy_page_addr >> 12)); 140770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 141770b93e9SHawking Zhang (u32)((u64)adev->dummy_page_addr >> 44)); 142770b93e9SHawking Zhang 143770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 144770b93e9SHawking Zhang ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 145770b93e9SHawking Zhang } 146770b93e9SHawking Zhang 147770b93e9SHawking Zhang 148770b93e9SHawking Zhang static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev) 149770b93e9SHawking Zhang { 150770b93e9SHawking Zhang uint32_t tmp; 151770b93e9SHawking Zhang 152770b93e9SHawking Zhang /* Setup TLB control */ 153770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 154770b93e9SHawking Zhang 155770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 156770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 157770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 158770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 1); 159770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 160770b93e9SHawking Zhang SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 161770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 162770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 163770b93e9SHawking Zhang MTYPE, MTYPE_UC); /* UC, uncached */ 164770b93e9SHawking Zhang 165770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 166770b93e9SHawking Zhang } 167770b93e9SHawking Zhang 168770b93e9SHawking Zhang static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 169770b93e9SHawking Zhang { 170770b93e9SHawking Zhang uint32_t tmp; 171770b93e9SHawking Zhang 17275ddb640SRohit Khaire /* These regs are not accessible for VF, PF will program these in SRIOV */ 17375ddb640SRohit Khaire if (amdgpu_sriov_vf(adev)) 17475ddb640SRohit Khaire return; 17575ddb640SRohit Khaire 176770b93e9SHawking Zhang /* Setup L2 cache */ 177770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); 178770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 179770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 1803ebab625SJack Xiao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 1813ebab625SJack Xiao ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 182770b93e9SHawking Zhang /* XXX for emulation, Refer to closed source code.*/ 183770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 184770b93e9SHawking Zhang L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 1858b7d6157SYong Zhao tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 186770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 187770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 188770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp); 189770b93e9SHawking Zhang 190770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2); 191770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 192770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 193770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); 194770b93e9SHawking Zhang 195770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL3_DEFAULT; 19646203a50SAlex Deucher if (adev->gmc.translate_further) { 19746203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 19846203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 19946203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 20046203a50SAlex Deucher } else { 20146203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 20246203a50SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 20346203a50SAlex Deucher L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 20446203a50SAlex Deucher } 205770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); 206770b93e9SHawking Zhang 207770b93e9SHawking Zhang tmp = mmGCVM_L2_CNTL4_DEFAULT; 208770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 209770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 210770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp); 211ec683759SAlex Deucher 212ec683759SAlex Deucher tmp = mmGCVM_L2_CNTL5_DEFAULT; 213ec683759SAlex Deucher tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 214ec683759SAlex Deucher WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp); 215770b93e9SHawking Zhang } 216770b93e9SHawking Zhang 217770b93e9SHawking Zhang static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 218770b93e9SHawking Zhang { 219770b93e9SHawking Zhang uint32_t tmp; 220770b93e9SHawking Zhang 221770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL); 222770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 223770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 2247cae7061SFelix Kuehling tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 2257cae7061SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 226770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp); 227770b93e9SHawking Zhang } 228770b93e9SHawking Zhang 229770b93e9SHawking Zhang static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev) 230770b93e9SHawking Zhang { 231770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 232770b93e9SHawking Zhang 0xFFFFFFFF); 233770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 234770b93e9SHawking Zhang 0x0000000F); 235770b93e9SHawking Zhang 236770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 237770b93e9SHawking Zhang 0); 238770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 239770b93e9SHawking Zhang 0); 240770b93e9SHawking Zhang 241770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 242770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 243770b93e9SHawking Zhang 244770b93e9SHawking Zhang } 245770b93e9SHawking Zhang 246770b93e9SHawking Zhang static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 247770b93e9SHawking Zhang { 2481e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 249770b93e9SHawking Zhang int i; 250770b93e9SHawking Zhang uint32_t tmp; 251770b93e9SHawking Zhang 252770b93e9SHawking Zhang for (i = 0; i <= 14; i++) { 253770b93e9SHawking Zhang tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); 254770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 255770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 256770b93e9SHawking Zhang adev->vm_manager.num_level); 257770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 258770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 259770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 260770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 261770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 262770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 263770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 264770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 265770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 266770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 267770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 268770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 269770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 270770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 271770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 272770b93e9SHawking Zhang PAGE_TABLE_BLOCK_SIZE, 273770b93e9SHawking Zhang adev->vm_manager.block_size - 9); 274770b93e9SHawking Zhang /* Send no-retry XNACK on fault to suppress VM fault storm. */ 275770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 27675ee6487SFelix Kuehling RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 27775ee6487SFelix Kuehling !amdgpu_noretry); 2781e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 2791e40eebeSHuang Rui i * hub->ctx_distance, tmp); 2801e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 2811e40eebeSHuang Rui i * hub->ctx_addr_distance, 0); 2821e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 2831e40eebeSHuang Rui i * hub->ctx_addr_distance, 0); 2841e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 2851e40eebeSHuang Rui i * hub->ctx_addr_distance, 286770b93e9SHawking Zhang lower_32_bits(adev->vm_manager.max_pfn - 1)); 2871e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 2881e40eebeSHuang Rui i * hub->ctx_addr_distance, 289770b93e9SHawking Zhang upper_32_bits(adev->vm_manager.max_pfn - 1)); 290770b93e9SHawking Zhang } 291770b93e9SHawking Zhang } 292770b93e9SHawking Zhang 293770b93e9SHawking Zhang static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 294770b93e9SHawking Zhang { 2951e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 296770b93e9SHawking Zhang unsigned i; 297770b93e9SHawking Zhang 298770b93e9SHawking Zhang for (i = 0 ; i < 18; ++i) { 299770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 3001e40eebeSHuang Rui i * hub->eng_addr_distance, 0xffffffff); 301770b93e9SHawking Zhang WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 3021e40eebeSHuang Rui i * hub->eng_addr_distance, 0x1f); 303770b93e9SHawking Zhang } 304770b93e9SHawking Zhang } 305770b93e9SHawking Zhang 306770b93e9SHawking Zhang int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev) 307770b93e9SHawking Zhang { 308770b93e9SHawking Zhang /* GART Enable. */ 309770b93e9SHawking Zhang gfxhub_v2_0_init_gart_aperture_regs(adev); 310770b93e9SHawking Zhang gfxhub_v2_0_init_system_aperture_regs(adev); 311770b93e9SHawking Zhang gfxhub_v2_0_init_tlb_regs(adev); 312770b93e9SHawking Zhang gfxhub_v2_0_init_cache_regs(adev); 313770b93e9SHawking Zhang 314770b93e9SHawking Zhang gfxhub_v2_0_enable_system_domain(adev); 315770b93e9SHawking Zhang gfxhub_v2_0_disable_identity_aperture(adev); 316770b93e9SHawking Zhang gfxhub_v2_0_setup_vmid_config(adev); 317770b93e9SHawking Zhang gfxhub_v2_0_program_invalidation(adev); 318770b93e9SHawking Zhang 319770b93e9SHawking Zhang return 0; 320770b93e9SHawking Zhang } 321770b93e9SHawking Zhang 322770b93e9SHawking Zhang void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 323770b93e9SHawking Zhang { 3241e40eebeSHuang Rui struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 325770b93e9SHawking Zhang u32 tmp; 326770b93e9SHawking Zhang u32 i; 327770b93e9SHawking Zhang 328770b93e9SHawking Zhang /* Disable all tables */ 329770b93e9SHawking Zhang for (i = 0; i < 16; i++) 3301e40eebeSHuang Rui WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 3311e40eebeSHuang Rui i * hub->ctx_distance, 0); 332770b93e9SHawking Zhang 333770b93e9SHawking Zhang /* Setup TLB control */ 334770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL); 335770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 336770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 337770b93e9SHawking Zhang ENABLE_ADVANCED_DRIVER_MODEL, 0); 338770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp); 339770b93e9SHawking Zhang 34075ddb640SRohit Khaire if (!amdgpu_sriov_vf(adev)) { 341770b93e9SHawking Zhang /* Setup L2 cache */ 342770b93e9SHawking Zhang WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 343770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0); 344770b93e9SHawking Zhang } 34575ddb640SRohit Khaire } 346770b93e9SHawking Zhang 347770b93e9SHawking Zhang /** 348770b93e9SHawking Zhang * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling 349770b93e9SHawking Zhang * 350770b93e9SHawking Zhang * @adev: amdgpu_device pointer 351770b93e9SHawking Zhang * @value: true redirects VM faults to the default page 352770b93e9SHawking Zhang */ 353770b93e9SHawking Zhang void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, 354770b93e9SHawking Zhang bool value) 355770b93e9SHawking Zhang { 356770b93e9SHawking Zhang u32 tmp; 357770b93e9SHawking Zhang tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 358770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 359770b93e9SHawking Zhang RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 360770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 361770b93e9SHawking Zhang PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 362770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 363770b93e9SHawking Zhang PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 364770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 365770b93e9SHawking Zhang PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 366770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 367770b93e9SHawking Zhang TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 368770b93e9SHawking Zhang value); 369770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 370770b93e9SHawking Zhang NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 371770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 372770b93e9SHawking Zhang DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 373770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 374770b93e9SHawking Zhang VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 375770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 376770b93e9SHawking Zhang READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 377770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 378770b93e9SHawking Zhang WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 379770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 380770b93e9SHawking Zhang EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 381770b93e9SHawking Zhang if (!value) { 382770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 383770b93e9SHawking Zhang CRASH_ON_NO_RETRY_FAULT, 1); 384770b93e9SHawking Zhang tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 385770b93e9SHawking Zhang CRASH_ON_RETRY_FAULT, 1); 386770b93e9SHawking Zhang } 387770b93e9SHawking Zhang WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 388770b93e9SHawking Zhang } 389770b93e9SHawking Zhang 3902577db91SHuang Rui static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = { 3912577db91SHuang Rui .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status, 3922577db91SHuang Rui }; 3932577db91SHuang Rui 394770b93e9SHawking Zhang void gfxhub_v2_0_init(struct amdgpu_device *adev) 395770b93e9SHawking Zhang { 396a2d15ed7SLe Ma struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 397770b93e9SHawking Zhang 398770b93e9SHawking Zhang hub->ctx0_ptb_addr_lo32 = 399770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 400770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 401770b93e9SHawking Zhang hub->ctx0_ptb_addr_hi32 = 402770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, 403770b93e9SHawking Zhang mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 4046c2c8972Schangzhu hub->vm_inv_eng0_sem = 4056c2c8972Schangzhu SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM); 406770b93e9SHawking Zhang hub->vm_inv_eng0_req = 407770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ); 408770b93e9SHawking Zhang hub->vm_inv_eng0_ack = 409770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK); 410770b93e9SHawking Zhang hub->vm_context0_cntl = 411770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL); 412770b93e9SHawking Zhang hub->vm_l2_pro_fault_status = 413770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS); 414770b93e9SHawking Zhang hub->vm_l2_pro_fault_cntl = 415770b93e9SHawking Zhang SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL); 4161f9d56c3SHuang Rui 4171f9d56c3SHuang Rui hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL; 4181f9d56c3SHuang Rui hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 4191f9d56c3SHuang Rui mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 4201f9d56c3SHuang Rui hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ - 4211f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_REQ; 4221f9d56c3SHuang Rui hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 4231f9d56c3SHuang Rui mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 4245befb6fcSHuang Rui 4255befb6fcSHuang Rui hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4265befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4275befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4285befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4295befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4305befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 4315befb6fcSHuang Rui GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 4322577db91SHuang Rui 4332577db91SHuang Rui hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs; 434770b93e9SHawking Zhang } 435