1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_2.h" 25 #include "gfxhub_v1_1.h" 26 27 #include "gc/gc_9_4_3_offset.h" 28 #include "gc/gc_9_4_3_sh_mask.h" 29 #include "vega10_enum.h" 30 31 #include "soc15_common.h" 32 33 #define regVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regVM_L2_CNTL4_DEFAULT 0x000000c1 35 36 static u64 gfxhub_v1_2_get_mc_fb_offset(struct amdgpu_device *adev) 37 { 38 return (u64)RREG32_SOC15(GC, 0, regMC_VM_FB_OFFSET) << 24; 39 } 40 41 static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev, 42 uint32_t vmid, 43 uint64_t page_table_base) 44 { 45 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 46 int i; 47 48 for (i = 0; i < adev->gfx.num_xcd; i++) { 49 WREG32_SOC15_OFFSET(GC, i, 50 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 51 hub->ctx_addr_distance * vmid, 52 lower_32_bits(page_table_base)); 53 54 WREG32_SOC15_OFFSET(GC, i, 55 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 56 hub->ctx_addr_distance * vmid, 57 upper_32_bits(page_table_base)); 58 } 59 } 60 61 static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev) 62 { 63 uint64_t pt_base; 64 int i; 65 66 if (adev->gmc.pdb0_bo) 67 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 68 else 69 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 70 71 gfxhub_v1_2_setup_vm_pt_regs(adev, 0, pt_base); 72 73 /* If use GART for FB translation, vmid0 page table covers both 74 * vram and system memory (gart) 75 */ 76 for (i = 0; i < adev->gfx.num_xcd; i++) { 77 if (adev->gmc.pdb0_bo) { 78 WREG32_SOC15(GC, i, 79 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 80 (u32)(adev->gmc.fb_start >> 12)); 81 WREG32_SOC15(GC, i, 82 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 83 (u32)(adev->gmc.fb_start >> 44)); 84 85 WREG32_SOC15(GC, i, 86 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 87 (u32)(adev->gmc.gart_end >> 12)); 88 WREG32_SOC15(GC, i, 89 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 90 (u32)(adev->gmc.gart_end >> 44)); 91 } else { 92 WREG32_SOC15(GC, i, 93 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 94 (u32)(adev->gmc.gart_start >> 12)); 95 WREG32_SOC15(GC, i, 96 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 97 (u32)(adev->gmc.gart_start >> 44)); 98 99 WREG32_SOC15(GC, i, 100 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 101 (u32)(adev->gmc.gart_end >> 12)); 102 WREG32_SOC15(GC, i, 103 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 104 (u32)(adev->gmc.gart_end >> 44)); 105 } 106 } 107 } 108 109 static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev) 110 { 111 uint64_t value; 112 uint32_t tmp; 113 int i; 114 115 for (i = 0; i < adev->gfx.num_xcd; i++) { 116 /* Program the AGP BAR */ 117 WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BASE, 0); 118 WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 119 WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 120 121 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { 122 /* Program the system aperture low logical page number. */ 123 WREG32_SOC15_RLC(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 124 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 125 126 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 127 /* 128 * Raven2 has a HW issue that it is unable to use the 129 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. 130 * So here is the workaround that increase system 131 * aperture high address (add 1) to get rid of the VM 132 * fault and hardware hang. 133 */ 134 WREG32_SOC15_RLC(GC, i, 135 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 136 max((adev->gmc.fb_end >> 18) + 0x1, 137 adev->gmc.agp_end >> 18)); 138 else 139 WREG32_SOC15_RLC(GC, i, 140 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 141 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 142 143 /* Set default page address. */ 144 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 145 WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 146 (u32)(value >> 12)); 147 WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 148 (u32)(value >> 44)); 149 150 /* Program "protection fault". */ 151 WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 152 (u32)(adev->dummy_page_addr >> 12)); 153 WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 154 (u32)((u64)adev->dummy_page_addr >> 44)); 155 156 tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2); 157 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, 158 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 159 WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); 160 } 161 162 /* In the case squeezing vram into GART aperture, we don't use 163 * FB aperture and AGP aperture. Disable them. 164 */ 165 if (adev->gmc.pdb0_bo) { 166 WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_TOP, 0); 167 WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); 168 WREG32_SOC15(GC, i, regMC_VM_AGP_TOP, 0); 169 WREG32_SOC15(GC, i, regMC_VM_AGP_BOT, 0xFFFFFF); 170 WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); 171 WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); 172 } 173 } 174 } 175 176 static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev) 177 { 178 uint32_t tmp; 179 int i; 180 181 for (i = 0; i < adev->gfx.num_xcd; i++) { 182 /* Setup TLB control */ 183 tmp = RREG32_SOC15(GC, i, regMC_VM_MX_L1_TLB_CNTL); 184 185 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 186 ENABLE_L1_TLB, 1); 187 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 188 SYSTEM_ACCESS_MODE, 3); 189 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 190 ENABLE_ADVANCED_DRIVER_MODEL, 1); 191 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 192 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 193 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 194 MTYPE, MTYPE_UC);/* XXX for emulation. */ 195 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 196 197 WREG32_SOC15_RLC(GC, i, regMC_VM_MX_L1_TLB_CNTL, tmp); 198 } 199 } 200 201 static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) 202 { 203 uint32_t tmp; 204 int i; 205 206 for (i = 0; i < adev->gfx.num_xcd; i++) { 207 /* Setup L2 cache */ 208 tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL); 209 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 210 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 211 /* XXX for emulation, Refer to closed source code.*/ 212 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 213 0); 214 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 215 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 216 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 217 WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL, tmp); 218 219 tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL2); 220 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 221 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 222 WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL2, tmp); 223 224 tmp = regVM_L2_CNTL3_DEFAULT; 225 if (adev->gmc.translate_further) { 226 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 227 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 228 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 229 } else { 230 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 231 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 232 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 233 } 234 WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL3, tmp); 235 236 tmp = regVM_L2_CNTL4_DEFAULT; 237 if (adev->gmc.xgmi.connected_to_cpu) { 238 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 239 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 240 } else { 241 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 242 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 243 } 244 WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL4, tmp); 245 } 246 } 247 248 static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev) 249 { 250 uint32_t tmp; 251 int i; 252 253 for (i = 0; i < adev->gfx.num_xcd; i++) { 254 tmp = RREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL); 255 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 257 adev->gmc.vmid0_page_table_depth); 258 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, 259 adev->gmc.vmid0_page_table_block_size); 260 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 261 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 262 WREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL, tmp); 263 } 264 } 265 266 static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev) 267 { 268 int i; 269 270 for (i = 0; i < adev->gfx.num_xcd; i++) { 271 WREG32_SOC15(GC, i, 272 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 273 0XFFFFFFFF); 274 WREG32_SOC15(GC, i, 275 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 276 0x0000000F); 277 278 WREG32_SOC15(GC, i, 279 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 280 0); 281 WREG32_SOC15(GC, i, 282 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 283 0); 284 285 WREG32_SOC15(GC, i, 286 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 287 WREG32_SOC15(GC, i, 288 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 289 } 290 } 291 292 static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) 293 { 294 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 295 unsigned num_level, block_size; 296 uint32_t tmp; 297 int i, j; 298 299 num_level = adev->vm_manager.num_level; 300 block_size = adev->vm_manager.block_size; 301 if (adev->gmc.translate_further) 302 num_level -= 1; 303 else 304 block_size -= 9; 305 306 for (j = 0; j < adev->gfx.num_xcd; j++) { 307 for (i = 0; i <= 14; i++) { 308 tmp = RREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL, i); 309 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 310 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 311 num_level); 312 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 313 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 314 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 315 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 316 1); 317 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 318 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 319 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 320 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 321 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 322 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 323 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 324 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 325 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 326 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 327 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 328 PAGE_TABLE_BLOCK_SIZE, 329 block_size); 330 /* Send no-retry XNACK on fault to suppress VM fault storm. 331 * On Aldebaran, XNACK can be enabled in the SQ per-process. 332 * Retry faults need to be enabled for that to work. 333 */ 334 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 335 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 336 !adev->gmc.noretry || 337 adev->asic_type == CHIP_ALDEBARAN); 338 WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL, 339 i * hub->ctx_distance, tmp); 340 WREG32_SOC15_OFFSET(GC, j, 341 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 342 i * hub->ctx_addr_distance, 0); 343 WREG32_SOC15_OFFSET(GC, j, 344 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 345 i * hub->ctx_addr_distance, 0); 346 WREG32_SOC15_OFFSET(GC, j, 347 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 348 i * hub->ctx_addr_distance, 349 lower_32_bits(adev->vm_manager.max_pfn - 1)); 350 WREG32_SOC15_OFFSET(GC, j, 351 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 352 i * hub->ctx_addr_distance, 353 upper_32_bits(adev->vm_manager.max_pfn - 1)); 354 } 355 } 356 } 357 358 static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev) 359 { 360 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 361 unsigned i, j; 362 363 for (j = 0; j < adev->gfx.num_xcd; j++) { 364 for (i = 0 ; i < 18; ++i) { 365 WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 366 i * hub->eng_addr_distance, 0xffffffff); 367 WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 368 i * hub->eng_addr_distance, 0x1f); 369 } 370 } 371 } 372 373 static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev) 374 { 375 int i; 376 377 for (i = 0; i < adev->gfx.num_xcd; i++) { 378 if (amdgpu_sriov_vf(adev)) { 379 /* 380 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 381 * VF copy registers so vbios post doesn't program them, for 382 * SRIOV driver need to program them 383 */ 384 WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_BASE, 385 adev->gmc.vram_start >> 24); 386 WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_TOP, 387 adev->gmc.vram_end >> 24); 388 } 389 } 390 391 /* GART Enable. */ 392 gfxhub_v1_2_init_gart_aperture_regs(adev); 393 gfxhub_v1_2_init_system_aperture_regs(adev); 394 gfxhub_v1_2_init_tlb_regs(adev); 395 if (!amdgpu_sriov_vf(adev)) 396 gfxhub_v1_2_init_cache_regs(adev); 397 398 gfxhub_v1_2_enable_system_domain(adev); 399 if (!amdgpu_sriov_vf(adev)) 400 gfxhub_v1_2_disable_identity_aperture(adev); 401 gfxhub_v1_2_setup_vmid_config(adev); 402 gfxhub_v1_2_program_invalidation(adev); 403 404 return 0; 405 } 406 407 static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) 408 { 409 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 410 u32 tmp; 411 u32 i, j; 412 413 for (j = 0; j < adev->gfx.num_xcd; j++) { 414 /* Disable all tables */ 415 for (i = 0; i < 16; i++) 416 WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT0_CNTL, 417 i * hub->ctx_distance, 0); 418 419 /* Setup TLB control */ 420 tmp = RREG32_SOC15(GC, j, regMC_VM_MX_L1_TLB_CNTL); 421 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 422 tmp = REG_SET_FIELD(tmp, 423 MC_VM_MX_L1_TLB_CNTL, 424 ENABLE_ADVANCED_DRIVER_MODEL, 425 0); 426 WREG32_SOC15_RLC(GC, j, regMC_VM_MX_L1_TLB_CNTL, tmp); 427 428 /* Setup L2 cache */ 429 tmp = RREG32_SOC15(GC, j, regVM_L2_CNTL); 430 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 431 WREG32_SOC15(GC, j, regVM_L2_CNTL, tmp); 432 WREG32_SOC15(GC, j, regVM_L2_CNTL3, 0); 433 } 434 } 435 436 /** 437 * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling 438 * 439 * @adev: amdgpu_device pointer 440 * @value: true redirects VM faults to the default page 441 */ 442 static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, 443 bool value) 444 { 445 u32 tmp; 446 int i; 447 448 for (i = 0; i < adev->gfx.num_xcd; i++) { 449 tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL); 450 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 451 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 452 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 453 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 454 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 455 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 456 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 457 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 458 tmp = REG_SET_FIELD(tmp, 459 VM_L2_PROTECTION_FAULT_CNTL, 460 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 461 value); 462 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 463 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 464 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 465 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 466 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 467 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 468 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 469 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 470 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 471 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 472 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 473 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 474 if (!value) { 475 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 476 CRASH_ON_NO_RETRY_FAULT, 1); 477 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 478 CRASH_ON_RETRY_FAULT, 1); 479 } 480 WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp); 481 } 482 } 483 484 static void gfxhub_v1_2_init(struct amdgpu_device *adev) 485 { 486 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 487 488 hub->ctx0_ptb_addr_lo32 = 489 SOC15_REG_OFFSET(GC, 0, 490 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 491 hub->ctx0_ptb_addr_hi32 = 492 SOC15_REG_OFFSET(GC, 0, 493 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 494 hub->vm_inv_eng0_sem = 495 SOC15_REG_OFFSET(GC, 0, regVM_INVALIDATE_ENG0_SEM); 496 hub->vm_inv_eng0_req = 497 SOC15_REG_OFFSET(GC, 0, regVM_INVALIDATE_ENG0_REQ); 498 hub->vm_inv_eng0_ack = 499 SOC15_REG_OFFSET(GC, 0, regVM_INVALIDATE_ENG0_ACK); 500 hub->vm_context0_cntl = 501 SOC15_REG_OFFSET(GC, 0, regVM_CONTEXT0_CNTL); 502 hub->vm_l2_pro_fault_status = 503 SOC15_REG_OFFSET(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS); 504 hub->vm_l2_pro_fault_cntl = 505 SOC15_REG_OFFSET(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL); 506 507 hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL; 508 hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 509 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 510 hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ; 511 hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 512 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 513 } 514 515 516 const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = { 517 .get_mc_fb_offset = gfxhub_v1_2_get_mc_fb_offset, 518 .setup_vm_pt_regs = gfxhub_v1_2_setup_vm_pt_regs, 519 .gart_enable = gfxhub_v1_2_gart_enable, 520 .gart_disable = gfxhub_v1_2_gart_disable, 521 .set_fault_enable_default = gfxhub_v1_2_set_fault_enable_default, 522 .init = gfxhub_v1_2_init, 523 .get_xgmi_info = gfxhub_v1_1_get_xgmi_info, 524 }; 525