1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 26 #include "gc/gc_9_0_offset.h" 27 #include "gc/gc_9_0_sh_mask.h" 28 #include "gc/gc_9_0_default.h" 29 #include "vega10_enum.h" 30 31 #include "soc15_common.h" 32 33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 34 { 35 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 36 } 37 38 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 39 { 40 uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo); 41 42 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 43 lower_32_bits(value)); 44 45 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 46 upper_32_bits(value)); 47 } 48 49 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 50 { 51 gfxhub_v1_0_init_gart_pt_regs(adev); 52 53 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 54 (u32)(adev->gmc.gart_start >> 12)); 55 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 56 (u32)(adev->gmc.gart_start >> 44)); 57 58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 59 (u32)(adev->gmc.gart_end >> 12)); 60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 61 (u32)(adev->gmc.gart_end >> 44)); 62 } 63 64 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 65 { 66 uint64_t value; 67 68 /* Program the AGP BAR */ 69 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); 70 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 71 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 72 73 /* Program the system aperture low logical page number. */ 74 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 75 min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18); 76 77 if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8) 78 /* 79 * Raven2 has a HW issue that it is unable to use the vram which 80 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 81 * workaround that increase system aperture high address (add 1) 82 * to get rid of the VM fault and hardware hang. 83 */ 84 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 85 max((adev->gmc.vram_end >> 18) + 0x1, 86 adev->gmc.agp_end >> 18)); 87 else 88 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 89 max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18); 90 91 /* Set default page address. */ 92 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start 93 + adev->vm_manager.vram_base_offset; 94 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 95 (u32)(value >> 12)); 96 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 97 (u32)(value >> 44)); 98 99 /* Program "protection fault". */ 100 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 101 (u32)(adev->dummy_page_addr >> 12)); 102 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 103 (u32)((u64)adev->dummy_page_addr >> 44)); 104 105 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 106 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 107 } 108 109 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 110 { 111 uint32_t tmp; 112 113 /* Setup TLB control */ 114 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 115 116 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 118 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 119 ENABLE_ADVANCED_DRIVER_MODEL, 1); 120 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 121 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 122 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 124 MTYPE, MTYPE_UC);/* XXX for emulation. */ 125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 126 127 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 128 } 129 130 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 131 { 132 uint32_t tmp; 133 134 /* Setup L2 cache */ 135 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 136 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 137 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 138 /* XXX for emulation, Refer to closed source code.*/ 139 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 140 0); 141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 144 WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); 145 146 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 149 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); 150 151 tmp = mmVM_L2_CNTL3_DEFAULT; 152 if (adev->gmc.translate_further) { 153 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 155 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 156 } else { 157 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 158 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 159 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 160 } 161 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); 162 163 tmp = mmVM_L2_CNTL4_DEFAULT; 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 166 WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); 167 } 168 169 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 170 { 171 uint32_t tmp; 172 173 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 174 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 175 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 176 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 177 } 178 179 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 180 { 181 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 182 0XFFFFFFFF); 183 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 184 0x0000000F); 185 186 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 187 0); 188 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 189 0); 190 191 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 192 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 193 194 } 195 196 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 197 { 198 unsigned num_level, block_size; 199 uint32_t tmp; 200 int i; 201 202 num_level = adev->vm_manager.num_level; 203 block_size = adev->vm_manager.block_size; 204 if (adev->gmc.translate_further) 205 num_level -= 1; 206 else 207 block_size -= 9; 208 209 for (i = 0; i <= 14; i++) { 210 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 211 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 212 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 213 num_level); 214 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 215 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 216 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 217 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 218 1); 219 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 220 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 221 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 222 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 223 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 224 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 226 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 228 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 230 PAGE_TABLE_BLOCK_SIZE, 231 block_size); 232 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 234 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 235 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); 236 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 237 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 238 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 239 lower_32_bits(adev->vm_manager.max_pfn - 1)); 240 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 241 upper_32_bits(adev->vm_manager.max_pfn - 1)); 242 } 243 } 244 245 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 246 { 247 unsigned i; 248 249 for (i = 0 ; i < 18; ++i) { 250 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 251 2 * i, 0xffffffff); 252 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 253 2 * i, 0x1f); 254 } 255 } 256 257 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 258 { 259 if (amdgpu_sriov_vf(adev)) { 260 /* 261 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 262 * VF copy registers so vbios post doesn't program them, for 263 * SRIOV driver need to program them 264 */ 265 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 266 adev->gmc.vram_start >> 24); 267 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 268 adev->gmc.vram_end >> 24); 269 } 270 271 /* GART Enable. */ 272 gfxhub_v1_0_init_gart_aperture_regs(adev); 273 gfxhub_v1_0_init_system_aperture_regs(adev); 274 gfxhub_v1_0_init_tlb_regs(adev); 275 gfxhub_v1_0_init_cache_regs(adev); 276 277 gfxhub_v1_0_enable_system_domain(adev); 278 gfxhub_v1_0_disable_identity_aperture(adev); 279 gfxhub_v1_0_setup_vmid_config(adev); 280 gfxhub_v1_0_program_invalidation(adev); 281 282 return 0; 283 } 284 285 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 286 { 287 u32 tmp; 288 u32 i; 289 290 /* Disable all tables */ 291 for (i = 0; i < 16; i++) 292 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); 293 294 /* Setup TLB control */ 295 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 296 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 297 tmp = REG_SET_FIELD(tmp, 298 MC_VM_MX_L1_TLB_CNTL, 299 ENABLE_ADVANCED_DRIVER_MODEL, 300 0); 301 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 302 303 /* Setup L2 cache */ 304 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 305 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 306 } 307 308 /** 309 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 310 * 311 * @adev: amdgpu_device pointer 312 * @value: true redirects VM faults to the default page 313 */ 314 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 315 bool value) 316 { 317 u32 tmp; 318 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 319 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 320 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 321 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 322 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 323 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 324 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 325 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 326 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 327 tmp = REG_SET_FIELD(tmp, 328 VM_L2_PROTECTION_FAULT_CNTL, 329 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 330 value); 331 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 332 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 333 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 334 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 335 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 336 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 337 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 338 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 339 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 340 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 341 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 342 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 343 if (!value) { 344 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 345 CRASH_ON_NO_RETRY_FAULT, 1); 346 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 347 CRASH_ON_RETRY_FAULT, 1); 348 } 349 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 350 } 351 352 void gfxhub_v1_0_init(struct amdgpu_device *adev) 353 { 354 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; 355 356 hub->ctx0_ptb_addr_lo32 = 357 SOC15_REG_OFFSET(GC, 0, 358 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 359 hub->ctx0_ptb_addr_hi32 = 360 SOC15_REG_OFFSET(GC, 0, 361 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 362 hub->vm_inv_eng0_req = 363 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 364 hub->vm_inv_eng0_ack = 365 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 366 hub->vm_context0_cntl = 367 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 368 hub->vm_l2_pro_fault_status = 369 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 370 hub->vm_l2_pro_fault_cntl = 371 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 372 } 373