1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 #include "gfxhub_v1_1.h" 26 27 #include "gc/gc_9_0_offset.h" 28 #include "gc/gc_9_0_sh_mask.h" 29 #include "gc/gc_9_0_default.h" 30 #include "vega10_enum.h" 31 32 #include "soc15_common.h" 33 34 static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 35 { 36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 37 } 38 39 static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, 40 uint32_t vmid, 41 uint64_t page_table_base) 42 { 43 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 44 45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 46 hub->ctx_addr_distance * vmid, 47 lower_32_bits(page_table_base)); 48 49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 50 hub->ctx_addr_distance * vmid, 51 upper_32_bits(page_table_base)); 52 } 53 54 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 55 { 56 uint64_t pt_base; 57 58 if (adev->gmc.pdb0_bo) 59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 60 else 61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 62 63 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 64 65 /* If use GART for FB translation, vmid0 page table covers both 66 * vram and system memory (gart) 67 */ 68 if (adev->gmc.pdb0_bo) { 69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70 (u32)(adev->gmc.fb_start >> 12)); 71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72 (u32)(adev->gmc.fb_start >> 44)); 73 74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75 (u32)(adev->gmc.gart_end >> 12)); 76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77 (u32)(adev->gmc.gart_end >> 44)); 78 } else { 79 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 80 (u32)(adev->gmc.gart_start >> 12)); 81 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 82 (u32)(adev->gmc.gart_start >> 44)); 83 84 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 85 (u32)(adev->gmc.gart_end >> 12)); 86 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 87 (u32)(adev->gmc.gart_end >> 44)); 88 } 89 } 90 91 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 92 { 93 uint64_t value; 94 95 /* Program the AGP BAR */ 96 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); 97 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 98 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 99 100 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { 101 /* Program the system aperture low logical page number. */ 102 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 103 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 104 105 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 106 /* 107 * Raven2 has a HW issue that it is unable to use the 108 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. 109 * So here is the workaround that increase system 110 * aperture high address (add 1) to get rid of the VM 111 * fault and hardware hang. 112 */ 113 WREG32_SOC15_RLC(GC, 0, 114 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 115 max((adev->gmc.fb_end >> 18) + 0x1, 116 adev->gmc.agp_end >> 18)); 117 else 118 WREG32_SOC15_RLC( 119 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 120 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 121 122 /* Set default page address. */ 123 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 124 adev->vm_manager.vram_base_offset; 125 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 126 (u32)(value >> 12)); 127 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 128 (u32)(value >> 44)); 129 130 /* Program "protection fault". */ 131 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 132 (u32)(adev->dummy_page_addr >> 12)); 133 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 134 (u32)((u64)adev->dummy_page_addr >> 44)); 135 136 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 137 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 138 } 139 140 /* In the case squeezing vram into GART aperture, we don't use 141 * FB aperture and AGP aperture. Disable them. 142 */ 143 if (adev->gmc.pdb0_bo) { 144 if (adev->asic_type == CHIP_ALDEBARAN) { 145 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, adev->gmc.fb_end_original >> 24); 146 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, adev->gmc.fb_start_original >> 24); 147 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); 148 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF); 149 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, adev->gmc.fb_start_original >> 18); 150 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, adev->gmc.fb_end_original >> 18); 151 } else { 152 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0); 153 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); 154 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); 155 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF); 156 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); 157 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); 158 } 159 } 160 } 161 162 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 163 { 164 uint32_t tmp; 165 166 /* Setup TLB control */ 167 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 168 169 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 170 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 171 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 172 ENABLE_ADVANCED_DRIVER_MODEL, 1); 173 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 174 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 175 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 176 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 177 MTYPE, MTYPE_UC);/* XXX for emulation. */ 178 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 179 180 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 181 } 182 183 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 184 { 185 uint32_t tmp; 186 187 /* Setup L2 cache */ 188 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 189 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 191 /* XXX for emulation, Refer to closed source code.*/ 192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 193 0); 194 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 196 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 197 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); 198 199 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 200 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 202 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); 203 204 tmp = mmVM_L2_CNTL3_DEFAULT; 205 if (adev->gmc.translate_further) { 206 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 207 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 208 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 209 } else { 210 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 211 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 212 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 213 } 214 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); 215 216 tmp = mmVM_L2_CNTL4_DEFAULT; 217 if (adev->gmc.xgmi.connected_to_cpu) { 218 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 219 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 220 } else { 221 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 222 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 223 } 224 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); 225 } 226 227 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 228 { 229 uint32_t tmp; 230 231 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 232 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 234 adev->gmc.vmid0_page_table_depth); 235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, 236 adev->gmc.vmid0_page_table_block_size); 237 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 238 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 239 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 240 } 241 242 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 243 { 244 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 245 0XFFFFFFFF); 246 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 247 0x0000000F); 248 249 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 250 0); 251 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 252 0); 253 254 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 255 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 256 257 } 258 259 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 260 { 261 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 262 unsigned num_level, block_size; 263 uint32_t tmp; 264 int i; 265 266 num_level = adev->vm_manager.num_level; 267 block_size = adev->vm_manager.block_size; 268 if (adev->gmc.translate_further) 269 num_level -= 1; 270 else 271 block_size -= 9; 272 273 for (i = 0; i <= 14; i++) { 274 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 275 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 276 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 277 num_level); 278 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 279 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 280 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 281 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 282 1); 283 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 284 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 285 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 286 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 287 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 288 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 289 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 290 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 291 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 292 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 293 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 294 PAGE_TABLE_BLOCK_SIZE, 295 block_size); 296 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 297 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 298 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 299 !adev->gmc.noretry); 300 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, 301 i * hub->ctx_distance, tmp); 302 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 303 i * hub->ctx_addr_distance, 0); 304 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 305 i * hub->ctx_addr_distance, 0); 306 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 307 i * hub->ctx_addr_distance, 308 lower_32_bits(adev->vm_manager.max_pfn - 1)); 309 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 310 i * hub->ctx_addr_distance, 311 upper_32_bits(adev->vm_manager.max_pfn - 1)); 312 } 313 } 314 315 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 316 { 317 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 318 unsigned i; 319 320 for (i = 0 ; i < 18; ++i) { 321 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 322 i * hub->eng_addr_distance, 0xffffffff); 323 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 324 i * hub->eng_addr_distance, 0x1f); 325 } 326 } 327 328 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 329 { 330 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { 331 /* 332 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 333 * VF copy registers so vbios post doesn't program them, for 334 * SRIOV driver need to program them 335 */ 336 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, 337 adev->gmc.vram_start >> 24); 338 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, 339 adev->gmc.vram_end >> 24); 340 } 341 342 /* GART Enable. */ 343 gfxhub_v1_0_init_gart_aperture_regs(adev); 344 gfxhub_v1_0_init_system_aperture_regs(adev); 345 gfxhub_v1_0_init_tlb_regs(adev); 346 if (!amdgpu_sriov_vf(adev)) 347 gfxhub_v1_0_init_cache_regs(adev); 348 349 gfxhub_v1_0_enable_system_domain(adev); 350 if (!amdgpu_sriov_vf(adev)) 351 gfxhub_v1_0_disable_identity_aperture(adev); 352 gfxhub_v1_0_setup_vmid_config(adev); 353 gfxhub_v1_0_program_invalidation(adev); 354 355 return 0; 356 } 357 358 static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 359 { 360 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 361 u32 tmp; 362 u32 i; 363 364 /* Disable all tables */ 365 for (i = 0; i < 16; i++) 366 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, 367 i * hub->ctx_distance, 0); 368 369 /* Setup TLB control */ 370 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 371 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 372 tmp = REG_SET_FIELD(tmp, 373 MC_VM_MX_L1_TLB_CNTL, 374 ENABLE_ADVANCED_DRIVER_MODEL, 375 0); 376 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 377 378 /* Setup L2 cache */ 379 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 380 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 381 } 382 383 /** 384 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 385 * 386 * @adev: amdgpu_device pointer 387 * @value: true redirects VM faults to the default page 388 */ 389 static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 390 bool value) 391 { 392 u32 tmp; 393 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 395 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 397 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 399 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 401 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, 403 VM_L2_PROTECTION_FAULT_CNTL, 404 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 405 value); 406 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 407 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 408 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 409 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 410 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 411 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 412 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 413 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 414 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 415 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 416 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 417 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 418 if (!value) { 419 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 420 CRASH_ON_NO_RETRY_FAULT, 1); 421 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 422 CRASH_ON_RETRY_FAULT, 1); 423 } 424 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 425 } 426 427 static void gfxhub_v1_0_init(struct amdgpu_device *adev) 428 { 429 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 430 431 hub->ctx0_ptb_addr_lo32 = 432 SOC15_REG_OFFSET(GC, 0, 433 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 434 hub->ctx0_ptb_addr_hi32 = 435 SOC15_REG_OFFSET(GC, 0, 436 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 437 hub->vm_inv_eng0_sem = 438 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM); 439 hub->vm_inv_eng0_req = 440 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 441 hub->vm_inv_eng0_ack = 442 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 443 hub->vm_context0_cntl = 444 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 445 hub->vm_l2_pro_fault_status = 446 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 447 hub->vm_l2_pro_fault_cntl = 448 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 449 450 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; 451 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 452 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 453 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; 454 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 455 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 456 } 457 458 459 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { 460 .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset, 461 .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs, 462 .gart_enable = gfxhub_v1_0_gart_enable, 463 .gart_disable = gfxhub_v1_0_gart_disable, 464 .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default, 465 .init = gfxhub_v1_0_init, 466 .get_xgmi_info = gfxhub_v1_1_get_xgmi_info, 467 }; 468