1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 26 #include "vega10/soc15ip.h" 27 #include "vega10/GC/gc_9_0_offset.h" 28 #include "vega10/GC/gc_9_0_sh_mask.h" 29 #include "vega10/GC/gc_9_0_default.h" 30 #include "vega10/vega10_enum.h" 31 32 #include "soc15_common.h" 33 34 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 35 { 36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 37 } 38 39 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) 40 { 41 uint64_t value; 42 43 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); 44 value = adev->gart.table_addr - adev->mc.vram_start 45 + adev->vm_manager.vram_base_offset; 46 value &= 0x0000FFFFFFFFF000ULL; 47 value |= 0x1; /*valid bit*/ 48 49 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 50 lower_32_bits(value)); 51 52 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 53 upper_32_bits(value)); 54 } 55 56 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 57 { 58 gfxhub_v1_0_init_gart_pt_regs(adev); 59 60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 61 (u32)(adev->mc.gtt_start >> 12)); 62 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 63 (u32)(adev->mc.gtt_start >> 44)); 64 65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 66 (u32)(adev->mc.gtt_end >> 12)); 67 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 68 (u32)(adev->mc.gtt_end >> 44)); 69 } 70 71 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 72 { 73 uint64_t value; 74 75 /* Disable AGP. */ 76 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0); 77 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); 78 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF); 79 80 /* Program the system aperture low logical page number. */ 81 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 82 adev->mc.vram_start >> 18); 83 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 84 adev->mc.vram_end >> 18); 85 86 /* Set default page address. */ 87 value = adev->vram_scratch.gpu_addr - adev->mc.vram_start 88 + adev->vm_manager.vram_base_offset; 89 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 90 (u32)(value >> 12)); 91 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 92 (u32)(value >> 44)); 93 94 /* Program "protection fault". */ 95 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 96 (u32)(adev->dummy_page.addr >> 12)); 97 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 98 (u32)((u64)adev->dummy_page.addr >> 44)); 99 100 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 101 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 102 } 103 104 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 105 { 106 uint32_t tmp; 107 108 /* Setup TLB control */ 109 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 110 111 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 112 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 113 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 114 ENABLE_ADVANCED_DRIVER_MODEL, 1); 115 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 116 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 117 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 118 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 119 MTYPE, MTYPE_UC);/* XXX for emulation. */ 120 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 121 122 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 123 } 124 125 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 126 { 127 uint32_t tmp; 128 129 /* Setup L2 cache */ 130 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 131 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 132 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 133 /* XXX for emulation, Refer to closed source code.*/ 134 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 135 0); 136 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); 137 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 138 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 139 WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp); 140 141 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 142 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 144 WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); 145 146 tmp = mmVM_L2_CNTL3_DEFAULT; 147 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp); 148 149 tmp = mmVM_L2_CNTL4_DEFAULT; 150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 151 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 152 WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp); 153 } 154 155 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 156 { 157 uint32_t tmp; 158 159 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 160 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 161 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 162 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 163 } 164 165 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 166 { 167 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 168 0XFFFFFFFF); 169 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 170 0x0000000F); 171 172 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 173 0); 174 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 175 0); 176 177 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 178 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 179 180 } 181 182 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 183 { 184 int i; 185 uint32_t tmp; 186 187 for (i = 0; i <= 14; i++) { 188 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 189 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 190 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 191 adev->vm_manager.num_level); 192 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 193 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 194 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 195 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 196 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 197 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 198 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 199 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 200 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 201 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 203 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 205 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 206 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 207 PAGE_TABLE_BLOCK_SIZE, 208 adev->vm_manager.block_size - 9); 209 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp); 210 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 211 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 212 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 213 lower_32_bits(adev->vm_manager.max_pfn - 1)); 214 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 215 upper_32_bits(adev->vm_manager.max_pfn - 1)); 216 } 217 } 218 219 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 220 { 221 unsigned i; 222 223 for (i = 0 ; i < 18; ++i) { 224 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 225 2 * i, 0xffffffff); 226 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 227 2 * i, 0x1f); 228 } 229 } 230 231 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 232 { 233 if (amdgpu_sriov_vf(adev)) { 234 /* 235 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 236 * VF copy registers so vbios post doesn't program them, for 237 * SRIOV driver need to program them 238 */ 239 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 240 adev->mc.vram_start >> 24); 241 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 242 adev->mc.vram_end >> 24); 243 } 244 245 /* GART Enable. */ 246 gfxhub_v1_0_init_gart_aperture_regs(adev); 247 gfxhub_v1_0_init_system_aperture_regs(adev); 248 gfxhub_v1_0_init_tlb_regs(adev); 249 gfxhub_v1_0_init_cache_regs(adev); 250 251 gfxhub_v1_0_enable_system_domain(adev); 252 gfxhub_v1_0_disable_identity_aperture(adev); 253 gfxhub_v1_0_setup_vmid_config(adev); 254 gfxhub_v1_0_program_invalidation(adev); 255 256 return 0; 257 } 258 259 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 260 { 261 u32 tmp; 262 u32 i; 263 264 /* Disable all tables */ 265 for (i = 0; i < 16; i++) 266 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0); 267 268 /* Setup TLB control */ 269 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 270 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 271 tmp = REG_SET_FIELD(tmp, 272 MC_VM_MX_L1_TLB_CNTL, 273 ENABLE_ADVANCED_DRIVER_MODEL, 274 0); 275 WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 276 277 /* Setup L2 cache */ 278 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 279 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 280 } 281 282 /** 283 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 284 * 285 * @adev: amdgpu_device pointer 286 * @value: true redirects VM faults to the default page 287 */ 288 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 289 bool value) 290 { 291 u32 tmp; 292 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 293 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 294 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 295 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 296 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 297 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 298 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 299 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 300 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 301 tmp = REG_SET_FIELD(tmp, 302 VM_L2_PROTECTION_FAULT_CNTL, 303 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 304 value); 305 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 306 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 307 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 308 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 309 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 310 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 311 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 312 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 313 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 314 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 315 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 316 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 317 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 318 } 319 320 void gfxhub_v1_0_init(struct amdgpu_device *adev) 321 { 322 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; 323 324 hub->ctx0_ptb_addr_lo32 = 325 SOC15_REG_OFFSET(GC, 0, 326 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 327 hub->ctx0_ptb_addr_hi32 = 328 SOC15_REG_OFFSET(GC, 0, 329 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 330 hub->vm_inv_eng0_req = 331 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 332 hub->vm_inv_eng0_ack = 333 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 334 hub->vm_context0_cntl = 335 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 336 hub->vm_l2_pro_fault_status = 337 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 338 hub->vm_l2_pro_fault_cntl = 339 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 340 } 341