1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "amdgpu.h"
24 #include "gfxhub_v1_0.h"
25 #include "gfxhub_v1_1.h"
26 
27 #include "gc/gc_9_0_offset.h"
28 #include "gc/gc_9_0_sh_mask.h"
29 #include "gc/gc_9_0_default.h"
30 #include "vega10_enum.h"
31 
32 #include "soc15_common.h"
33 
34 static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
35 {
36 	return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
37 }
38 
39 static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
40 					 uint32_t vmid,
41 					 uint64_t page_table_base)
42 {
43 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
44 
45 	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
46 			    hub->ctx_addr_distance * vmid,
47 			    lower_32_bits(page_table_base));
48 
49 	WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
50 			    hub->ctx_addr_distance * vmid,
51 			    upper_32_bits(page_table_base));
52 }
53 
54 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
55 {
56 	uint64_t pt_base;
57 
58 	if (adev->gmc.pdb0_bo)
59 		pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
60 	else
61 		pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
62 
63 	gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
64 
65 	/* If use GART for FB translation, vmid0 page table covers both
66 	 * vram and system memory (gart)
67 	 */
68 	if (adev->gmc.pdb0_bo) {
69 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 				(u32)(adev->gmc.fb_start >> 12));
71 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 				(u32)(adev->gmc.fb_start >> 44));
73 
74 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 				(u32)(adev->gmc.gart_end >> 12));
76 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 				(u32)(adev->gmc.gart_end >> 44));
78 	} else {
79 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
80 				(u32)(adev->gmc.gart_start >> 12));
81 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
82 				(u32)(adev->gmc.gart_start >> 44));
83 
84 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
85 				(u32)(adev->gmc.gart_end >> 12));
86 		WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
87 				(u32)(adev->gmc.gart_end >> 44));
88 	}
89 }
90 
91 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
92 {
93 	uint64_t value;
94 
95 	/* Program the AGP BAR */
96 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
97 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
98 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
99 
100 	if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
101 		/* Program the system aperture low logical page number. */
102 		WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
103 			min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
104 
105 		if (adev->apu_flags & (AMD_APU_IS_RAVEN2 |
106 				       AMD_APU_IS_RENOIR |
107 				       AMD_APU_IS_GREEN_SARDINE))
108 		       /*
109 			* Raven2 has a HW issue that it is unable to use the
110 			* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
111 			* So here is the workaround that increase system
112 			* aperture high address (add 1) to get rid of the VM
113 			* fault and hardware hang.
114 			*/
115 			WREG32_SOC15_RLC(GC, 0,
116 					 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
117 					 max((adev->gmc.fb_end >> 18) + 0x1,
118 					     adev->gmc.agp_end >> 18));
119 		else
120 			WREG32_SOC15_RLC(
121 				GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
122 				max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
123 
124 		/* Set default page address. */
125 		value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
126 		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
127 			     (u32)(value >> 12));
128 		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
129 			     (u32)(value >> 44));
130 
131 		/* Program "protection fault". */
132 		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
133 			     (u32)(adev->dummy_page_addr >> 12));
134 		WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
135 			     (u32)((u64)adev->dummy_page_addr >> 44));
136 
137 		WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
138 			       ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
139 	}
140 
141 	/* In the case squeezing vram into GART aperture, we don't use
142 	 * FB aperture and AGP aperture. Disable them.
143 	 */
144 	if (adev->gmc.pdb0_bo) {
145 		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
146 		WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
147 		WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
148 		WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
149 		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
150 		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
151 	}
152 }
153 
154 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
155 {
156 	uint32_t tmp;
157 
158 	/* Setup TLB control */
159 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
160 
161 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
162 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
163 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
164 			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
165 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
166 			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
167 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
168 			    MTYPE, MTYPE_UC);/* XXX for emulation. */
169 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
170 
171 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
172 }
173 
174 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
175 {
176 	uint32_t tmp;
177 
178 	/* Setup L2 cache */
179 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
180 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
181 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
182 	/* XXX for emulation, Refer to closed source code.*/
183 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
184 			    0);
185 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
186 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
187 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
188 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
189 
190 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
191 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
192 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
193 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
194 
195 	tmp = mmVM_L2_CNTL3_DEFAULT;
196 	if (adev->gmc.translate_further) {
197 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
198 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
199 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
200 	} else {
201 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
202 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
203 				    L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
204 	}
205 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
206 
207 	tmp = mmVM_L2_CNTL4_DEFAULT;
208 	if (adev->gmc.xgmi.connected_to_cpu) {
209 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
210 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
211 	} else {
212 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
213 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
214 	}
215 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
216 }
217 
218 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
219 {
220 	uint32_t tmp;
221 
222 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
223 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
224 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
225 			adev->gmc.vmid0_page_table_depth);
226 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
227 			adev->gmc.vmid0_page_table_block_size);
228 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
229 			    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
230 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
231 }
232 
233 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
234 {
235 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
236 		     0XFFFFFFFF);
237 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
238 		     0x0000000F);
239 
240 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
241 		     0);
242 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
243 		     0);
244 
245 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
246 	WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
247 
248 }
249 
250 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
251 {
252 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
253 	unsigned int num_level, block_size;
254 	uint32_t tmp;
255 	int i;
256 
257 	num_level = adev->vm_manager.num_level;
258 	block_size = adev->vm_manager.block_size;
259 	if (adev->gmc.translate_further)
260 		num_level -= 1;
261 	else
262 		block_size -= 9;
263 
264 	for (i = 0; i <= 14; i++) {
265 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
266 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
267 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
268 				    num_level);
269 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
270 				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
271 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
272 				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
273 				    1);
274 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
275 				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
276 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
277 				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
278 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
279 				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
280 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
281 				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
282 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
283 				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
284 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
285 				    PAGE_TABLE_BLOCK_SIZE,
286 				    block_size);
287 		/* Send no-retry XNACK on fault to suppress VM fault storm.
288 		 * On Aldebaran, XNACK can be enabled in the SQ per-process.
289 		 * Retry faults need to be enabled for that to work.
290 		 */
291 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
292 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
293 				    !adev->gmc.noretry ||
294 				    adev->asic_type == CHIP_ALDEBARAN);
295 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
296 				    i * hub->ctx_distance, tmp);
297 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
298 				    i * hub->ctx_addr_distance, 0);
299 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
300 				    i * hub->ctx_addr_distance, 0);
301 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
302 				    i * hub->ctx_addr_distance,
303 				    lower_32_bits(adev->vm_manager.max_pfn - 1));
304 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
305 				    i * hub->ctx_addr_distance,
306 				    upper_32_bits(adev->vm_manager.max_pfn - 1));
307 	}
308 }
309 
310 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
311 {
312 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
313 	unsigned int i;
314 
315 	for (i = 0 ; i < 18; ++i) {
316 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
317 				    i * hub->eng_addr_distance, 0xffffffff);
318 		WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
319 				    i * hub->eng_addr_distance, 0x1f);
320 	}
321 }
322 
323 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
324 {
325 	/* GART Enable. */
326 	gfxhub_v1_0_init_gart_aperture_regs(adev);
327 	gfxhub_v1_0_init_system_aperture_regs(adev);
328 	gfxhub_v1_0_init_tlb_regs(adev);
329 	if (!amdgpu_sriov_vf(adev))
330 		gfxhub_v1_0_init_cache_regs(adev);
331 
332 	gfxhub_v1_0_enable_system_domain(adev);
333 	if (!amdgpu_sriov_vf(adev))
334 		gfxhub_v1_0_disable_identity_aperture(adev);
335 	gfxhub_v1_0_setup_vmid_config(adev);
336 	gfxhub_v1_0_program_invalidation(adev);
337 
338 	return 0;
339 }
340 
341 static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
342 {
343 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
344 	u32 tmp;
345 	u32 i;
346 
347 	/* Disable all tables */
348 	for (i = 0; i < 16; i++)
349 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
350 				    i * hub->ctx_distance, 0);
351 
352 	if (amdgpu_sriov_vf(adev))
353 		/* Avoid write to GMC registers */
354 		return;
355 
356 	/* Setup TLB control */
357 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
358 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
359 	tmp = REG_SET_FIELD(tmp,
360 				MC_VM_MX_L1_TLB_CNTL,
361 				ENABLE_ADVANCED_DRIVER_MODEL,
362 				0);
363 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
364 
365 	/* Setup L2 cache */
366 	WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
367 	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
368 }
369 
370 /**
371  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
372  *
373  * @adev: amdgpu_device pointer
374  * @value: true redirects VM faults to the default page
375  */
376 static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
377 						 bool value)
378 {
379 	u32 tmp;
380 
381 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
382 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
383 			RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
384 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
385 			PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
386 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
387 			PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
388 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
389 			PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
390 	tmp = REG_SET_FIELD(tmp,
391 			VM_L2_PROTECTION_FAULT_CNTL,
392 			TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
393 			value);
394 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
395 			NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
397 			DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
399 			VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
400 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
401 			READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
402 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
403 			WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
404 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
405 			EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
406 	if (!value) {
407 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
408 				CRASH_ON_NO_RETRY_FAULT, 1);
409 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
410 				CRASH_ON_RETRY_FAULT, 1);
411 	}
412 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
413 }
414 
415 static void gfxhub_v1_0_init(struct amdgpu_device *adev)
416 {
417 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
418 
419 	hub->ctx0_ptb_addr_lo32 =
420 		SOC15_REG_OFFSET(GC, 0,
421 				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
422 	hub->ctx0_ptb_addr_hi32 =
423 		SOC15_REG_OFFSET(GC, 0,
424 				 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
425 	hub->vm_inv_eng0_sem =
426 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
427 	hub->vm_inv_eng0_req =
428 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
429 	hub->vm_inv_eng0_ack =
430 		SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
431 	hub->vm_context0_cntl =
432 		SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
433 	hub->vm_l2_pro_fault_status =
434 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
435 	hub->vm_l2_pro_fault_cntl =
436 		SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
437 
438 	hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
439 	hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
440 		mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
441 	hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
442 	hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
443 		mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
444 }
445 
446 
447 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
448 	.get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
449 	.setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
450 	.gart_enable = gfxhub_v1_0_gart_enable,
451 	.gart_disable = gfxhub_v1_0_gart_disable,
452 	.set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
453 	.init = gfxhub_v1_0_init,
454 	.get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
455 };
456