1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "clearstate_gfx9.h" 33 #include "v9_structs.h" 34 35 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 36 37 #include "gc/gc_9_4_3_offset.h" 38 #include "gc/gc_9_4_3_sh_mask.h" 39 40 #include "gfx_v9_4_3.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 static const struct soc15_reg_golden golden_settings_gc_9_4_3[] = { 49 50 }; 51 52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 57 struct amdgpu_cu_info *cu_info); 58 59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 60 uint64_t queue_mask) 61 { 62 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 63 amdgpu_ring_write(kiq_ring, 64 PACKET3_SET_RESOURCES_VMID_MASK(0) | 65 /* vmid_mask:0* queue_type:0 (KIQ) */ 66 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 67 amdgpu_ring_write(kiq_ring, 68 lower_32_bits(queue_mask)); /* queue mask lo */ 69 amdgpu_ring_write(kiq_ring, 70 upper_32_bits(queue_mask)); /* queue mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 73 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 74 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 75 } 76 77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring) 79 { 80 struct amdgpu_device *adev = kiq_ring->adev; 81 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 82 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 83 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 84 85 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 86 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 87 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 88 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 89 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 90 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 91 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 92 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 93 /*queue_type: normal compute queue */ 94 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 95 /* alloc format: all_on_one_pipe */ 96 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 97 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 98 /* num_queues: must be 1 */ 99 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 100 amdgpu_ring_write(kiq_ring, 101 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 105 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 106 } 107 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 109 struct amdgpu_ring *ring, 110 enum amdgpu_unmap_queues_action action, 111 u64 gpu_addr, u64 seq) 112 { 113 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 114 115 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 116 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 117 PACKET3_UNMAP_QUEUES_ACTION(action) | 118 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 119 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 120 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 121 amdgpu_ring_write(kiq_ring, 122 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 123 124 if (action == PREEMPT_QUEUES_NO_UNMAP) { 125 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 126 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, seq); 128 } else { 129 amdgpu_ring_write(kiq_ring, 0); 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 } 133 } 134 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 u64 addr, 138 u64 seq) 139 { 140 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 141 142 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 143 amdgpu_ring_write(kiq_ring, 144 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 145 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 146 PACKET3_QUERY_STATUS_COMMAND(2)); 147 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 148 amdgpu_ring_write(kiq_ring, 149 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 150 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 155 } 156 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 158 uint16_t pasid, uint32_t flush_type, 159 bool all_hub) 160 { 161 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 162 amdgpu_ring_write(kiq_ring, 163 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 164 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 165 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 166 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 167 } 168 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 170 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 171 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 172 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 173 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 174 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 175 .set_resources_size = 8, 176 .map_queues_size = 7, 177 .unmap_queues_size = 6, 178 .query_status_size = 7, 179 .invalidate_tlbs_size = 2, 180 }; 181 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 183 { 184 int i; 185 for (i = 0; i < adev->gfx.num_xcd; i++) 186 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 187 } 188 189 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 190 { 191 192 } 193 194 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 195 bool wc, uint32_t reg, uint32_t val) 196 { 197 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 198 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 199 WRITE_DATA_DST_SEL(0) | 200 (wc ? WR_CONFIRM : 0)); 201 amdgpu_ring_write(ring, reg); 202 amdgpu_ring_write(ring, 0); 203 amdgpu_ring_write(ring, val); 204 } 205 206 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 207 int mem_space, int opt, uint32_t addr0, 208 uint32_t addr1, uint32_t ref, uint32_t mask, 209 uint32_t inv) 210 { 211 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 212 amdgpu_ring_write(ring, 213 /* memory (1) or register (0) */ 214 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 215 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 216 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 217 WAIT_REG_MEM_ENGINE(eng_sel))); 218 219 if (mem_space) 220 BUG_ON(addr0 & 0x3); /* Dword align */ 221 amdgpu_ring_write(ring, addr0); 222 amdgpu_ring_write(ring, addr1); 223 amdgpu_ring_write(ring, ref); 224 amdgpu_ring_write(ring, mask); 225 amdgpu_ring_write(ring, inv); /* poll interval */ 226 } 227 228 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 229 { 230 struct amdgpu_device *adev = ring->adev; 231 uint32_t tmp = 0; 232 unsigned i; 233 int r; 234 235 WREG32_SOC15(GC, 0, regSCRATCH_REG0, 0xCAFEDEAD); 236 r = amdgpu_ring_alloc(ring, 3); 237 if (r) 238 return r; 239 240 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 241 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0) - 242 PACKET3_SET_UCONFIG_REG_START); 243 amdgpu_ring_write(ring, 0xDEADBEEF); 244 amdgpu_ring_commit(ring); 245 246 for (i = 0; i < adev->usec_timeout; i++) { 247 tmp = RREG32_SOC15(GC, 0, regSCRATCH_REG0); 248 if (tmp == 0xDEADBEEF) 249 break; 250 udelay(1); 251 } 252 253 if (i >= adev->usec_timeout) 254 r = -ETIMEDOUT; 255 return r; 256 } 257 258 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 259 { 260 struct amdgpu_device *adev = ring->adev; 261 struct amdgpu_ib ib; 262 struct dma_fence *f = NULL; 263 264 unsigned index; 265 uint64_t gpu_addr; 266 uint32_t tmp; 267 long r; 268 269 r = amdgpu_device_wb_get(adev, &index); 270 if (r) 271 return r; 272 273 gpu_addr = adev->wb.gpu_addr + (index * 4); 274 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 275 memset(&ib, 0, sizeof(ib)); 276 r = amdgpu_ib_get(adev, NULL, 16, 277 AMDGPU_IB_POOL_DIRECT, &ib); 278 if (r) 279 goto err1; 280 281 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 282 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 283 ib.ptr[2] = lower_32_bits(gpu_addr); 284 ib.ptr[3] = upper_32_bits(gpu_addr); 285 ib.ptr[4] = 0xDEADBEEF; 286 ib.length_dw = 5; 287 288 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 289 if (r) 290 goto err2; 291 292 r = dma_fence_wait_timeout(f, false, timeout); 293 if (r == 0) { 294 r = -ETIMEDOUT; 295 goto err2; 296 } else if (r < 0) { 297 goto err2; 298 } 299 300 tmp = adev->wb.wb[index]; 301 if (tmp == 0xDEADBEEF) 302 r = 0; 303 else 304 r = -EINVAL; 305 306 err2: 307 amdgpu_ib_free(adev, &ib, NULL); 308 dma_fence_put(f); 309 err1: 310 amdgpu_device_wb_free(adev, index); 311 return r; 312 } 313 314 315 /* This value might differs per partition */ 316 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 317 { 318 uint64_t clock; 319 320 amdgpu_gfx_off_ctrl(adev, false); 321 mutex_lock(&adev->gfx.gpu_clock_mutex); 322 WREG32_SOC15(GC, 0, regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 323 clock = (uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_LSB) | 324 ((uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 325 mutex_unlock(&adev->gfx.gpu_clock_mutex); 326 amdgpu_gfx_off_ctrl(adev, true); 327 328 return clock; 329 } 330 331 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 332 { 333 amdgpu_ucode_release(&adev->gfx.pfp_fw); 334 amdgpu_ucode_release(&adev->gfx.me_fw); 335 amdgpu_ucode_release(&adev->gfx.ce_fw); 336 amdgpu_ucode_release(&adev->gfx.rlc_fw); 337 amdgpu_ucode_release(&adev->gfx.mec_fw); 338 amdgpu_ucode_release(&adev->gfx.mec2_fw); 339 340 kfree(adev->gfx.rlc.register_list_format); 341 } 342 343 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 344 const char *chip_name) 345 { 346 char fw_name[30]; 347 int err; 348 const struct rlc_firmware_header_v2_0 *rlc_hdr; 349 uint16_t version_major; 350 uint16_t version_minor; 351 352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 353 354 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 355 if (err) 356 goto out; 357 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 358 359 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 360 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 361 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 362 out: 363 if (err) 364 amdgpu_ucode_release(&adev->gfx.rlc_fw); 365 366 return err; 367 } 368 369 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 370 { 371 return true; 372 } 373 374 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 375 { 376 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 377 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 378 } 379 380 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 381 const char *chip_name) 382 { 383 char fw_name[30]; 384 int err; 385 386 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 387 388 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 389 if (err) 390 goto out; 391 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 392 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 393 394 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 395 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 396 397 gfx_v9_4_3_check_if_need_gfxoff(adev); 398 399 out: 400 if (err) 401 amdgpu_ucode_release(&adev->gfx.mec_fw); 402 return err; 403 } 404 405 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 406 { 407 const char *chip_name; 408 int r; 409 410 chip_name = "gc_9_4_3"; 411 412 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 413 if (r) 414 return r; 415 416 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 417 if (r) 418 return r; 419 420 return r; 421 } 422 423 static u32 gfx_v9_4_3_get_csb_size(struct amdgpu_device *adev) 424 { 425 u32 count = 0; 426 const struct cs_section_def *sect = NULL; 427 const struct cs_extent_def *ext = NULL; 428 429 /* begin clear state */ 430 count += 2; 431 /* context control state */ 432 count += 3; 433 434 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 435 for (ext = sect->section; ext->extent != NULL; ++ext) { 436 if (sect->id == SECT_CONTEXT) 437 count += 2 + ext->reg_count; 438 else 439 return 0; 440 } 441 } 442 443 /* end clear state */ 444 count += 2; 445 /* clear state */ 446 count += 2; 447 448 return count; 449 } 450 451 static void gfx_v9_4_3_get_csb_buffer(struct amdgpu_device *adev, 452 volatile u32 *buffer) 453 { 454 u32 count = 0, i; 455 const struct cs_section_def *sect = NULL; 456 const struct cs_extent_def *ext = NULL; 457 458 if (adev->gfx.rlc.cs_data == NULL) 459 return; 460 if (buffer == NULL) 461 return; 462 463 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 464 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 465 466 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 467 buffer[count++] = cpu_to_le32(0x80000000); 468 buffer[count++] = cpu_to_le32(0x80000000); 469 470 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 471 for (ext = sect->section; ext->extent != NULL; ++ext) { 472 if (sect->id == SECT_CONTEXT) { 473 buffer[count++] = 474 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 475 buffer[count++] = cpu_to_le32(ext->reg_index - 476 PACKET3_SET_CONTEXT_REG_START); 477 for (i = 0; i < ext->reg_count; i++) 478 buffer[count++] = cpu_to_le32(ext->extent[i]); 479 } else { 480 return; 481 } 482 } 483 } 484 485 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 486 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 487 488 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 489 buffer[count++] = cpu_to_le32(0); 490 } 491 492 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 493 { 494 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 495 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 496 } 497 498 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 499 { 500 int r, i; 501 u32 *hpd; 502 const __le32 *fw_data; 503 unsigned fw_size; 504 u32 *fw; 505 size_t mec_hpd_size; 506 507 const struct gfx_firmware_header_v1_0 *mec_hdr; 508 509 for (i = 0; i < adev->gfx.num_xcd; i++) 510 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 511 AMDGPU_MAX_COMPUTE_QUEUES); 512 513 /* take ownership of the relevant compute queues */ 514 amdgpu_gfx_compute_queue_acquire(adev); 515 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 516 if (mec_hpd_size) { 517 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 518 AMDGPU_GEM_DOMAIN_VRAM, 519 &adev->gfx.mec.hpd_eop_obj, 520 &adev->gfx.mec.hpd_eop_gpu_addr, 521 (void **)&hpd); 522 if (r) { 523 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 524 gfx_v9_4_3_mec_fini(adev); 525 return r; 526 } 527 528 if (amdgpu_emu_mode == 1) { 529 for (i = 0; i < mec_hpd_size / 4; i++) { 530 memset((void *)(hpd + i), 0, 4); 531 if (i % 50 == 0) 532 msleep(1); 533 } 534 } else { 535 memset(hpd, 0, mec_hpd_size); 536 } 537 538 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 539 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 540 } 541 542 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 543 544 fw_data = (const __le32 *) 545 (adev->gfx.mec_fw->data + 546 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 547 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 548 549 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 551 &adev->gfx.mec.mec_fw_obj, 552 &adev->gfx.mec.mec_fw_gpu_addr, 553 (void **)&fw); 554 if (r) { 555 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 556 gfx_v9_4_3_mec_fini(adev); 557 return r; 558 } 559 560 memcpy(fw, fw_data, fw_size); 561 562 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 563 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 564 565 return 0; 566 } 567 568 static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev, 569 u32 se_num, 570 u32 sh_num, 571 u32 instance, 572 int xcc_id) 573 { 574 u32 data; 575 576 if (instance == 0xffffffff) 577 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 578 INSTANCE_BROADCAST_WRITES, 1); 579 else 580 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 581 INSTANCE_INDEX, instance); 582 583 if (se_num == 0xffffffff) 584 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 585 SE_BROADCAST_WRITES, 1); 586 else 587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 588 589 if (sh_num == 0xffffffff) 590 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 591 SH_BROADCAST_WRITES, 1); 592 else 593 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 594 595 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, xcc_id, regGRBM_GFX_INDEX, data); 596 } 597 598 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 599 { 600 WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX, 601 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 602 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 603 (address << SQ_IND_INDEX__INDEX__SHIFT) | 604 (SQ_IND_INDEX__FORCE_READ_MASK)); 605 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 606 } 607 608 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 609 uint32_t wave, uint32_t thread, 610 uint32_t regno, uint32_t num, uint32_t *out) 611 { 612 WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX, 613 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 614 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 615 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 616 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 617 (SQ_IND_INDEX__FORCE_READ_MASK) | 618 (SQ_IND_INDEX__AUTO_INCR_MASK)); 619 while (num--) 620 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 621 } 622 623 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 624 uint32_t simd, uint32_t wave, 625 uint32_t *dst, int *no_fields) 626 { 627 /* type 1 wave data */ 628 dst[(*no_fields)++] = 1; 629 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 630 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 631 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 632 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 633 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 634 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 635 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 636 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 637 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 638 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 639 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 640 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 641 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 642 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 643 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 644 } 645 646 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 647 uint32_t wave, uint32_t start, 648 uint32_t size, uint32_t *dst) 649 { 650 wave_read_regs(adev, simd, wave, 0, 651 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 652 } 653 654 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 655 uint32_t wave, uint32_t thread, 656 uint32_t start, uint32_t size, 657 uint32_t *dst) 658 { 659 wave_read_regs(adev, simd, wave, thread, 660 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 661 } 662 663 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 664 u32 me, u32 pipe, u32 q, u32 vm) 665 { 666 soc15_grbm_select(adev, me, pipe, q, vm, 0); 667 } 668 669 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 670 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 671 .select_se_sh = &gfx_v9_4_3_select_se_sh, 672 .read_wave_data = &gfx_v9_4_3_read_wave_data, 673 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 674 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 675 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 676 }; 677 678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 679 { 680 u32 gb_addr_config; 681 682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 683 684 switch (adev->ip_versions[GC_HWIP][0]) { 685 case IP_VERSION(9, 4, 3): 686 adev->gfx.config.max_hw_contexts = 8; 687 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 688 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 689 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 690 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 691 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 692 break; 693 default: 694 BUG(); 695 break; 696 } 697 698 adev->gfx.config.gb_addr_config = gb_addr_config; 699 700 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 701 REG_GET_FIELD( 702 adev->gfx.config.gb_addr_config, 703 GB_ADDR_CONFIG, 704 NUM_PIPES); 705 706 adev->gfx.config.max_tile_pipes = 707 adev->gfx.config.gb_addr_config_fields.num_pipes; 708 709 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 710 REG_GET_FIELD( 711 adev->gfx.config.gb_addr_config, 712 GB_ADDR_CONFIG, 713 NUM_BANKS); 714 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 715 REG_GET_FIELD( 716 adev->gfx.config.gb_addr_config, 717 GB_ADDR_CONFIG, 718 MAX_COMPRESSED_FRAGS); 719 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 720 REG_GET_FIELD( 721 adev->gfx.config.gb_addr_config, 722 GB_ADDR_CONFIG, 723 NUM_RB_PER_SE); 724 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 725 REG_GET_FIELD( 726 adev->gfx.config.gb_addr_config, 727 GB_ADDR_CONFIG, 728 NUM_SHADER_ENGINES); 729 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 730 REG_GET_FIELD( 731 adev->gfx.config.gb_addr_config, 732 GB_ADDR_CONFIG, 733 PIPE_INTERLEAVE_SIZE)); 734 735 return 0; 736 } 737 738 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 739 int xcc_id, int mec, int pipe, int queue) 740 { 741 unsigned irq_type; 742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 743 unsigned int hw_prio; 744 745 ring = &adev->gfx.compute_ring[ring_id]; 746 747 /* mec0 is me1 */ 748 ring->xcc_id = xcc_id; 749 ring->me = mec + 1; 750 ring->pipe = pipe; 751 ring->queue = queue; 752 753 ring->ring_obj = NULL; 754 ring->use_doorbell = true; 755 if (xcc_id >= 1) 756 ring->doorbell_index = 757 (adev->doorbell_index.xcc1_mec_ring0_start + 758 ring_id - adev->gfx.num_compute_rings) << 1; 759 else 760 ring->doorbell_index = 761 (adev->doorbell_index.mec_ring0 + ring_id) << 1; 762 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 763 + (ring_id * GFX9_MEC_HPD_SIZE); 764 ring->vm_hub = AMDGPU_GFXHUB_0; 765 sprintf(ring->name, "comp_%d.%d.%d.%d", 766 ring->xcc_id, ring->me, ring->pipe, ring->queue); 767 768 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 769 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 770 + ring->pipe; 771 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 772 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 773 /* type-2 packets are deprecated on MEC, use type-3 instead */ 774 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 775 hw_prio, NULL); 776 } 777 778 static int gfx_v9_4_3_sw_init(void *handle) 779 { 780 int i, j, k, r, ring_id, xcc_id; 781 struct amdgpu_kiq *kiq; 782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 783 784 adev->gfx.mec.num_mec = 2; 785 adev->gfx.mec.num_pipe_per_mec = 4; 786 adev->gfx.mec.num_queue_per_pipe = 8; 787 788 /* EOP Event */ 789 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 790 if (r) 791 return r; 792 793 /* Privileged reg */ 794 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 795 &adev->gfx.priv_reg_irq); 796 if (r) 797 return r; 798 799 /* Privileged inst */ 800 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 801 &adev->gfx.priv_inst_irq); 802 if (r) 803 return r; 804 805 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 806 807 r = adev->gfx.rlc.funcs->init(adev); 808 if (r) { 809 DRM_ERROR("Failed to init rlc BOs!\n"); 810 return r; 811 } 812 813 r = gfx_v9_4_3_mec_init(adev); 814 if (r) { 815 DRM_ERROR("Failed to init MEC BOs!\n"); 816 return r; 817 } 818 819 /* set up the compute queues - allocate horizontally across pipes */ 820 ring_id = 0; 821 for (xcc_id = 0; xcc_id < adev->gfx.num_xcd; xcc_id++) { 822 823 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 824 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 825 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 826 k++) { 827 if (!amdgpu_gfx_is_mec_queue_enabled( 828 adev, xcc_id, i, k, j)) 829 continue; 830 831 r = gfx_v9_4_3_compute_ring_init(adev, 832 ring_id, 833 xcc_id, 834 i, k, j); 835 if (r) 836 return r; 837 838 ring_id++; 839 } 840 } 841 } 842 843 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 844 if (r) { 845 DRM_ERROR("Failed to init KIQ BOs!\n"); 846 return r; 847 } 848 849 kiq = &adev->gfx.kiq[xcc_id]; 850 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 851 if (r) 852 return r; 853 854 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 855 r = amdgpu_gfx_mqd_sw_init(adev, 856 sizeof(struct v9_mqd_allocation), xcc_id); 857 if (r) 858 return r; 859 } 860 861 r = gfx_v9_4_3_gpu_early_init(adev); 862 if (r) 863 return r; 864 865 return 0; 866 } 867 868 static int gfx_v9_4_3_sw_fini(void *handle) 869 { 870 int i; 871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 872 873 for (i = 0; i < adev->gfx.num_compute_rings * 874 adev->gfx.num_xcd; i++) 875 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 876 877 for (i = 0; i < adev->gfx.num_xcd; i++) { 878 amdgpu_gfx_mqd_sw_fini(adev, i); 879 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 880 amdgpu_gfx_kiq_fini(adev, i); 881 } 882 883 gfx_v9_4_3_mec_fini(adev); 884 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 885 gfx_v9_4_3_free_microcode(adev); 886 887 return 0; 888 } 889 890 static u32 gfx_v9_4_3_get_rb_active_bitmap(struct amdgpu_device *adev) 891 { 892 u32 data, mask; 893 894 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 895 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 896 897 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 898 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 899 900 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 901 adev->gfx.config.max_sh_per_se); 902 903 return (~data) & mask; 904 } 905 906 static void gfx_v9_4_3_setup_rb(struct amdgpu_device *adev, int xcc_id) 907 { 908 int i, j; 909 u32 data; 910 u32 active_rbs = 0; 911 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 912 adev->gfx.config.max_sh_per_se; 913 914 mutex_lock(&adev->grbm_idx_mutex); 915 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 916 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 917 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 918 data = gfx_v9_4_3_get_rb_active_bitmap(adev); 919 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 920 rb_bitmap_width_per_sh); 921 } 922 } 923 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 924 mutex_unlock(&adev->grbm_idx_mutex); 925 926 adev->gfx.config.backend_enable_mask = active_rbs; 927 adev->gfx.config.num_rbs = hweight32(active_rbs); 928 } 929 930 #define DEFAULT_SH_MEM_BASES (0x6000) 931 static void gfx_v9_4_3_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) 932 { 933 int i; 934 uint32_t sh_mem_config; 935 uint32_t sh_mem_bases; 936 937 /* 938 * Configure apertures: 939 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 940 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 941 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 942 */ 943 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 944 945 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 946 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 947 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 948 949 mutex_lock(&adev->srbm_mutex); 950 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 951 soc15_grbm_select(adev, 0, 0, 0, i, xcc_id); 952 /* CP and shaders */ 953 WREG32_SOC15_RLC(GC, xcc_id, regSH_MEM_CONFIG, sh_mem_config); 954 WREG32_SOC15_RLC(GC, xcc_id, regSH_MEM_BASES, sh_mem_bases); 955 } 956 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 957 mutex_unlock(&adev->srbm_mutex); 958 959 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 960 acccess. These should be enabled by FW for target VMIDs. */ 961 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 962 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_BASE, 2 * i, 0); 963 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_SIZE, 2 * i, 0); 964 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_GWS_VMID0, i, 0); 965 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_OA_VMID0, i, 0); 966 } 967 } 968 969 static void gfx_v9_4_3_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 970 { 971 int vmid; 972 973 /* 974 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 975 * access. Compute VMIDs should be enabled by FW for target VMIDs, 976 * the driver can enable them for graphics. VMID0 should maintain 977 * access so that HWS firmware can save/restore entries. 978 */ 979 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 980 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_BASE, 2 * vmid, 0); 981 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_SIZE, 2 * vmid, 0); 982 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_GWS_VMID0, vmid, 0); 983 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_OA_VMID0, vmid, 0); 984 } 985 } 986 987 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 988 { 989 u32 tmp; 990 int i, j; 991 992 for (i = 0; i < adev->gfx.num_xcd; i++) { 993 WREG32_FIELD15_PREREG(GC, i, GRBM_CNTL, READ_TIMEOUT, 0xff); 994 gfx_v9_4_3_setup_rb(adev, i); 995 } 996 997 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 998 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, regDB_DEBUG2); 999 1000 /* XXX SH_MEM regs */ 1001 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1002 mutex_lock(&adev->srbm_mutex); 1003 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1004 for (j = 0; j < adev->gfx.num_xcd; j++) { 1005 soc15_grbm_select(adev, 0, 0, 0, i, j); 1006 /* CP and shaders */ 1007 if (i == 0) { 1008 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1009 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1010 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1011 !!adev->gmc.noretry); 1012 WREG32_SOC15_RLC(GC, j, regSH_MEM_CONFIG, tmp); 1013 WREG32_SOC15_RLC(GC, j, regSH_MEM_BASES, 0); 1014 } else { 1015 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1016 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1017 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1018 !!adev->gmc.noretry); 1019 WREG32_SOC15_RLC(GC, j, regSH_MEM_CONFIG, tmp); 1020 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1021 (adev->gmc.private_aperture_start >> 48)); 1022 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1023 (adev->gmc.shared_aperture_start >> 48)); 1024 WREG32_SOC15_RLC(GC, j, regSH_MEM_BASES, tmp); 1025 } 1026 } 1027 } 1028 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1029 1030 mutex_unlock(&adev->srbm_mutex); 1031 1032 for (i = 0; i < adev->gfx.num_xcd; i++) { 1033 gfx_v9_4_3_init_compute_vmid(adev, i); 1034 gfx_v9_4_3_init_gds_vmid(adev, i); 1035 } 1036 } 1037 1038 static void gfx_v9_4_3_enable_save_restore_machine(struct amdgpu_device *adev, 1039 int xcc_id) 1040 { 1041 WREG32_FIELD15_PREREG(GC, xcc_id, RLC_SRM_CNTL, SRM_ENABLE, 1); 1042 } 1043 1044 static void gfx_v9_4_3_init_csb(struct amdgpu_device *adev, int xcc_id) 1045 { 1046 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1047 /* csib */ 1048 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_ADDR_HI), 1049 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1050 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_ADDR_LO), 1051 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1052 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_LENGTH), 1053 adev->gfx.rlc.clear_state_size); 1054 } 1055 1056 static void gfx_v9_4_3_init_pg(struct amdgpu_device *adev, int xcc_id) 1057 { 1058 gfx_v9_4_3_init_csb(adev, xcc_id); 1059 1060 /* 1061 * Rlc save restore list is workable since v2_1. 1062 * And it's needed by gfxoff feature. 1063 */ 1064 if (adev->gfx.rlc.is_rlc_v2_1) 1065 gfx_v9_4_3_enable_save_restore_machine(adev, xcc_id); 1066 1067 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1068 AMD_PG_SUPPORT_GFX_SMG | 1069 AMD_PG_SUPPORT_GFX_DMG | 1070 AMD_PG_SUPPORT_CP | 1071 AMD_PG_SUPPORT_GDS | 1072 AMD_PG_SUPPORT_RLC_SMU_HS)) { 1073 WREG32_SOC15(GC, 0, regRLC_JUMP_TABLE_RESTORE, 1074 adev->gfx.rlc.cp_table_gpu_addr >> 8); 1075 } 1076 } 1077 1078 void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1079 { 1080 uint32_t data; 1081 1082 data = RREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG); 1083 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1084 WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data); 1085 } 1086 1087 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1088 { 1089 uint32_t rlc_setting; 1090 1091 /* if RLC is not enabled, do nothing */ 1092 rlc_setting = RREG32_SOC15(GC, 0, regRLC_CNTL); 1093 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1094 return false; 1095 1096 return true; 1097 } 1098 1099 static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1100 { 1101 uint32_t data; 1102 unsigned i; 1103 1104 data = RLC_SAFE_MODE__CMD_MASK; 1105 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1106 WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data); 1107 1108 /* wait for RLC_SAFE_MODE */ 1109 for (i = 0; i < adev->usec_timeout; i++) { 1110 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1111 break; 1112 udelay(1); 1113 } 1114 } 1115 1116 static void gfx_v9_4_3_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 1117 { 1118 uint32_t data; 1119 1120 data = RLC_SAFE_MODE__CMD_MASK; 1121 WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data); 1122 } 1123 1124 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1125 { 1126 const struct cs_section_def *cs_data; 1127 int r; 1128 1129 adev->gfx.rlc.cs_data = gfx9_cs_data; 1130 1131 cs_data = adev->gfx.rlc.cs_data; 1132 1133 if (cs_data) { 1134 /* init clear state block */ 1135 r = amdgpu_gfx_rlc_init_csb(adev); 1136 if (r) 1137 return r; 1138 } 1139 1140 /* init spm vmid with 0xf */ 1141 if (adev->gfx.rlc.funcs->update_spm_vmid) 1142 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1143 1144 return 0; 1145 } 1146 1147 static void gfx_v9_4_3_wait_for_rlc_serdes(struct amdgpu_device *adev, 1148 int xcc_id) 1149 { 1150 u32 i, j, k; 1151 u32 mask; 1152 1153 mutex_lock(&adev->grbm_idx_mutex); 1154 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1155 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1156 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 1157 for (k = 0; k < adev->usec_timeout; k++) { 1158 if (RREG32_SOC15(GC, 0, regRLC_SERDES_CU_MASTER_BUSY) == 0) 1159 break; 1160 udelay(1); 1161 } 1162 if (k == adev->usec_timeout) { 1163 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 1164 0xffffffff, 0xffffffff, 1165 xcc_id); 1166 mutex_unlock(&adev->grbm_idx_mutex); 1167 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1168 i, j); 1169 return; 1170 } 1171 } 1172 } 1173 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 1174 mutex_unlock(&adev->grbm_idx_mutex); 1175 1176 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1177 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1178 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1179 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1180 for (k = 0; k < adev->usec_timeout; k++) { 1181 if ((RREG32_SOC15(GC, 0, regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1182 break; 1183 udelay(1); 1184 } 1185 } 1186 1187 static void gfx_v9_4_3_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1188 bool enable, int xcc_id) 1189 { 1190 u32 tmp; 1191 1192 /* These interrupts should be enabled to drive DS clock */ 1193 1194 tmp = RREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0); 1195 1196 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1197 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1198 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1199 1200 WREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0, tmp); 1201 } 1202 1203 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1204 { 1205 int i; 1206 1207 for (i = 0; i < adev->gfx.num_xcd; i++) { 1208 WREG32_FIELD15_PREREG(GC, i, RLC_CNTL, RLC_ENABLE_F32, 0); 1209 gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1210 gfx_v9_4_3_wait_for_rlc_serdes(adev, i); 1211 } 1212 } 1213 1214 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1215 { 1216 int i; 1217 1218 for (i = 0; i < adev->gfx.num_xcd; i++) { 1219 WREG32_FIELD15_PREREG(GC, i, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1220 udelay(50); 1221 WREG32_FIELD15_PREREG(GC, i, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1222 udelay(50); 1223 } 1224 } 1225 1226 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1227 { 1228 #ifdef AMDGPU_RLC_DEBUG_RETRY 1229 u32 rlc_ucode_ver; 1230 #endif 1231 int i; 1232 1233 for (i = 0; i < adev->gfx.num_xcd; i++) { 1234 WREG32_FIELD15_PREREG(GC, i, RLC_CNTL, RLC_ENABLE_F32, 1); 1235 udelay(50); 1236 1237 /* carrizo do enable cp interrupt after cp inited */ 1238 if (!(adev->flags & AMD_IS_APU)) { 1239 gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1240 udelay(50); 1241 } 1242 1243 #ifdef AMDGPU_RLC_DEBUG_RETRY 1244 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1245 rlc_ucode_ver = RREG32_SOC15(GC, i, regRLC_GPM_GENERAL_6); 1246 if (rlc_ucode_ver == 0x108) { 1247 dev_info(adev->dev, 1248 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1249 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1250 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1251 * default is 0x9C4 to create a 100us interval */ 1252 WREG32_SOC15(GC, i, regRLC_GPM_TIMER_INT_3, 0x9C4); 1253 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1254 * to disable the page fault retry interrupts, default is 1255 * 0x100 (256) */ 1256 WREG32_SOC15(GC, i, regRLC_GPM_GENERAL_12, 0x100); 1257 } 1258 #endif 1259 } 1260 } 1261 1262 static int gfx_v9_4_3_rlc_load_microcode(struct amdgpu_device *adev, int xcc_id) 1263 { 1264 const struct rlc_firmware_header_v2_0 *hdr; 1265 const __le32 *fw_data; 1266 unsigned i, fw_size; 1267 1268 if (!adev->gfx.rlc_fw) 1269 return -EINVAL; 1270 1271 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1272 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1273 1274 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1275 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1276 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1277 1278 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_ADDR, 1279 RLCG_UCODE_LOADING_START_ADDRESS); 1280 for (i = 0; i < fw_size; i++) { 1281 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1282 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1283 msleep(1); 1284 } 1285 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1286 } 1287 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1288 1289 return 0; 1290 } 1291 1292 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1293 { 1294 int r, i; 1295 1296 adev->gfx.rlc.funcs->stop(adev); 1297 1298 for (i = 0; i < adev->gfx.num_xcd; i++) { 1299 /* disable CG */ 1300 WREG32_SOC15(GC, i, regRLC_CGCG_CGLS_CTRL, 0); 1301 1302 gfx_v9_4_3_init_pg(adev, i); 1303 1304 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1305 /* legacy rlc firmware loading */ 1306 r = gfx_v9_4_3_rlc_load_microcode(adev, i); 1307 if (r) 1308 return r; 1309 } 1310 } 1311 1312 adev->gfx.rlc.funcs->start(adev); 1313 1314 return 0; 1315 } 1316 1317 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1318 unsigned vmid) 1319 { 1320 u32 reg, data; 1321 1322 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 1323 if (amdgpu_sriov_is_pp_one_vf(adev)) 1324 data = RREG32_NO_KIQ(reg); 1325 else 1326 data = RREG32(reg); 1327 1328 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1329 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1330 1331 if (amdgpu_sriov_is_pp_one_vf(adev)) 1332 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 1333 else 1334 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 1335 } 1336 1337 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1338 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1339 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1340 }; 1341 1342 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1343 uint32_t offset, 1344 struct soc15_reg_rlcg *entries, int arr_size) 1345 { 1346 int i; 1347 uint32_t reg; 1348 1349 if (!entries) 1350 return false; 1351 1352 for (i = 0; i < arr_size; i++) { 1353 const struct soc15_reg_rlcg *entry; 1354 1355 entry = &entries[i]; 1356 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 1357 if (offset == reg) 1358 return true; 1359 } 1360 1361 return false; 1362 } 1363 1364 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1365 { 1366 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1367 (void *)rlcg_access_gc_9_4_3, 1368 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1369 } 1370 1371 static void gfx_v9_4_3_cp_compute_enable(struct amdgpu_device *adev, 1372 bool enable, int xcc_id) 1373 { 1374 if (enable) { 1375 WREG32_SOC15_RLC(GC, xcc_id, regCP_MEC_CNTL, 0); 1376 } else { 1377 WREG32_SOC15_RLC(GC, xcc_id, regCP_MEC_CNTL, 1378 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1379 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1380 } 1381 udelay(50); 1382 } 1383 1384 static int gfx_v9_4_3_cp_compute_load_microcode(struct amdgpu_device *adev, 1385 int xcc_id) 1386 { 1387 const struct gfx_firmware_header_v1_0 *mec_hdr; 1388 const __le32 *fw_data; 1389 unsigned i; 1390 u32 tmp; 1391 u32 mec_ucode_addr_offset; 1392 u32 mec_ucode_data_offset; 1393 1394 if (!adev->gfx.mec_fw) 1395 return -EINVAL; 1396 1397 gfx_v9_4_3_cp_compute_enable(adev, false, xcc_id); 1398 1399 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1400 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1401 1402 fw_data = (const __le32 *) 1403 (adev->gfx.mec_fw->data + 1404 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1405 tmp = 0; 1406 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1407 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1408 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_CNTL, tmp); 1409 1410 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_LO, 1411 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1412 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_HI, 1413 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1414 1415 mec_ucode_addr_offset = 1416 SOC15_REG_OFFSET(GC, xcc_id, regCP_MEC_ME1_UCODE_ADDR); 1417 mec_ucode_data_offset = 1418 SOC15_REG_OFFSET(GC, xcc_id, regCP_MEC_ME1_UCODE_DATA); 1419 1420 /* MEC1 */ 1421 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1422 for (i = 0; i < mec_hdr->jt_size; i++) 1423 WREG32(mec_ucode_data_offset, 1424 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1425 1426 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1427 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1428 1429 return 0; 1430 } 1431 1432 /* KIQ functions */ 1433 static void gfx_v9_4_3_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1434 { 1435 uint32_t tmp; 1436 struct amdgpu_device *adev = ring->adev; 1437 1438 /* tell RLC which is KIQ queue */ 1439 tmp = RREG32_SOC15(GC, xcc_id, regRLC_CP_SCHEDULERS); 1440 tmp &= 0xffffff00; 1441 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1442 WREG32_SOC15_RLC(GC, xcc_id, regRLC_CP_SCHEDULERS, tmp); 1443 tmp |= 0x80; 1444 WREG32_SOC15_RLC(GC, xcc_id, regRLC_CP_SCHEDULERS, tmp); 1445 } 1446 1447 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1448 { 1449 struct amdgpu_device *adev = ring->adev; 1450 1451 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1452 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1453 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1454 mqd->cp_hqd_queue_priority = 1455 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1456 } 1457 } 1458 } 1459 1460 static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring) 1461 { 1462 struct amdgpu_device *adev = ring->adev; 1463 struct v9_mqd *mqd = ring->mqd_ptr; 1464 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1465 uint32_t tmp; 1466 1467 mqd->header = 0xC0310800; 1468 mqd->compute_pipelinestat_enable = 0x00000001; 1469 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1470 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1471 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1472 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1473 mqd->compute_misc_reserved = 0x00000003; 1474 1475 mqd->dynamic_cu_mask_addr_lo = 1476 lower_32_bits(ring->mqd_gpu_addr 1477 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1478 mqd->dynamic_cu_mask_addr_hi = 1479 upper_32_bits(ring->mqd_gpu_addr 1480 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1481 1482 eop_base_addr = ring->eop_gpu_addr >> 8; 1483 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1484 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1485 1486 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1487 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 1488 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1489 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1490 1491 mqd->cp_hqd_eop_control = tmp; 1492 1493 /* enable doorbell? */ 1494 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1495 1496 if (ring->use_doorbell) { 1497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1498 DOORBELL_OFFSET, ring->doorbell_index); 1499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1500 DOORBELL_EN, 1); 1501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1502 DOORBELL_SOURCE, 0); 1503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1504 DOORBELL_HIT, 0); 1505 } else { 1506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1507 DOORBELL_EN, 0); 1508 } 1509 1510 mqd->cp_hqd_pq_doorbell_control = tmp; 1511 1512 /* disable the queue if it's active */ 1513 ring->wptr = 0; 1514 mqd->cp_hqd_dequeue_request = 0; 1515 mqd->cp_hqd_pq_rptr = 0; 1516 mqd->cp_hqd_pq_wptr_lo = 0; 1517 mqd->cp_hqd_pq_wptr_hi = 0; 1518 1519 /* set the pointer to the MQD */ 1520 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1521 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1522 1523 /* set MQD vmid to 0 */ 1524 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1525 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1526 mqd->cp_mqd_control = tmp; 1527 1528 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1529 hqd_gpu_addr = ring->gpu_addr >> 8; 1530 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1531 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1532 1533 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1534 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 1535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1536 (order_base_2(ring->ring_size / 4) - 1)); 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1538 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1539 #ifdef __BIG_ENDIAN 1540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1541 #endif 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1546 mqd->cp_hqd_pq_control = tmp; 1547 1548 /* set the wb address whether it's enabled or not */ 1549 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1550 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1551 mqd->cp_hqd_pq_rptr_report_addr_hi = 1552 upper_32_bits(wb_gpu_addr) & 0xffff; 1553 1554 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1555 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1556 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1557 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1558 1559 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1560 ring->wptr = 0; 1561 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 1562 1563 /* set the vmid for the queue */ 1564 mqd->cp_hqd_vmid = 0; 1565 1566 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 1567 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1568 mqd->cp_hqd_persistent_state = tmp; 1569 1570 /* set MIN_IB_AVAIL_SIZE */ 1571 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 1572 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1573 mqd->cp_hqd_ib_control = tmp; 1574 1575 /* set static priority for a queue/ring */ 1576 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1577 mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM); 1578 1579 /* map_queues packet doesn't need activate the queue, 1580 * so only kiq need set this field. 1581 */ 1582 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1583 mqd->cp_hqd_active = 1; 1584 1585 return 0; 1586 } 1587 1588 static int gfx_v9_4_3_kiq_init_register(struct amdgpu_ring *ring, int xcc_id) 1589 { 1590 struct amdgpu_device *adev = ring->adev; 1591 struct v9_mqd *mqd = ring->mqd_ptr; 1592 int j; 1593 1594 /* disable wptr polling */ 1595 WREG32_FIELD15_PREREG(GC, xcc_id, CP_PQ_WPTR_POLL_CNTL, EN, 0); 1596 1597 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_BASE_ADDR, 1598 mqd->cp_hqd_eop_base_addr_lo); 1599 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_BASE_ADDR_HI, 1600 mqd->cp_hqd_eop_base_addr_hi); 1601 1602 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1603 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_CONTROL, 1604 mqd->cp_hqd_eop_control); 1605 1606 /* enable doorbell? */ 1607 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 1608 mqd->cp_hqd_pq_doorbell_control); 1609 1610 /* disable the queue if it's active */ 1611 if (RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1) { 1612 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1); 1613 for (j = 0; j < adev->usec_timeout; j++) { 1614 if (!(RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1)) 1615 break; 1616 udelay(1); 1617 } 1618 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1619 mqd->cp_hqd_dequeue_request); 1620 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR, 1621 mqd->cp_hqd_pq_rptr); 1622 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 1623 mqd->cp_hqd_pq_wptr_lo); 1624 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 1625 mqd->cp_hqd_pq_wptr_hi); 1626 } 1627 1628 /* set the pointer to the MQD */ 1629 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_BASE_ADDR, 1630 mqd->cp_mqd_base_addr_lo); 1631 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_BASE_ADDR_HI, 1632 mqd->cp_mqd_base_addr_hi); 1633 1634 /* set MQD vmid to 0 */ 1635 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_CONTROL, 1636 mqd->cp_mqd_control); 1637 1638 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1639 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_BASE, 1640 mqd->cp_hqd_pq_base_lo); 1641 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_BASE_HI, 1642 mqd->cp_hqd_pq_base_hi); 1643 1644 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1645 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_CONTROL, 1646 mqd->cp_hqd_pq_control); 1647 1648 /* set the wb address whether it's enabled or not */ 1649 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1650 mqd->cp_hqd_pq_rptr_report_addr_lo); 1651 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1652 mqd->cp_hqd_pq_rptr_report_addr_hi); 1653 1654 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1655 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_POLL_ADDR, 1656 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1657 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1658 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1659 1660 /* enable the doorbell if requested */ 1661 if (ring->use_doorbell) { 1662 WREG32_SOC15(GC, xcc_id, regCP_MEC_DOORBELL_RANGE_LOWER, 1663 (adev->doorbell_index.kiq * 2) << 2); 1664 WREG32_SOC15(GC, xcc_id, regCP_MEC_DOORBELL_RANGE_UPPER, 1665 (adev->doorbell_index.userqueue_end * 2) << 2); 1666 } 1667 1668 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 1669 mqd->cp_hqd_pq_doorbell_control); 1670 1671 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1672 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 1673 mqd->cp_hqd_pq_wptr_lo); 1674 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 1675 mqd->cp_hqd_pq_wptr_hi); 1676 1677 /* set the vmid for the queue */ 1678 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_VMID, mqd->cp_hqd_vmid); 1679 1680 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PERSISTENT_STATE, 1681 mqd->cp_hqd_persistent_state); 1682 1683 /* activate the queue */ 1684 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_ACTIVE, 1685 mqd->cp_hqd_active); 1686 1687 if (ring->use_doorbell) 1688 WREG32_FIELD15_PREREG(GC, xcc_id, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1689 1690 return 0; 1691 } 1692 1693 static int gfx_v9_4_3_kiq_fini_register(struct amdgpu_ring *ring, int xcc_id) 1694 { 1695 struct amdgpu_device *adev = ring->adev; 1696 int j; 1697 1698 /* disable the queue if it's active */ 1699 if (RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1) { 1700 1701 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1); 1702 1703 for (j = 0; j < adev->usec_timeout; j++) { 1704 if (!(RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1)) 1705 break; 1706 udelay(1); 1707 } 1708 1709 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1710 DRM_DEBUG("KIQ dequeue request failed.\n"); 1711 1712 /* Manual disable if dequeue request times out */ 1713 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_ACTIVE, 0); 1714 } 1715 1716 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1717 0); 1718 } 1719 1720 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_IQ_TIMER, 0); 1721 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_IB_CONTROL, 0); 1722 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PERSISTENT_STATE, 0); 1723 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1724 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1725 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR, 0); 1726 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 0); 1727 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 0); 1728 1729 return 0; 1730 } 1731 1732 static int gfx_v9_4_3_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1733 { 1734 struct amdgpu_device *adev = ring->adev; 1735 struct v9_mqd *mqd = ring->mqd_ptr; 1736 struct v9_mqd *tmp_mqd; 1737 1738 gfx_v9_4_3_kiq_setting(ring, xcc_id); 1739 1740 /* GPU could be in bad state during probe, driver trigger the reset 1741 * after load the SMU, in this case , the mqd is not be initialized. 1742 * driver need to re-init the mqd. 1743 * check mqd->cp_hqd_pq_control since this value should not be 0 1744 */ 1745 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1746 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1747 /* for GPU_RESET case , reset MQD to a clean status */ 1748 if (adev->gfx.kiq[xcc_id].mqd_backup) 1749 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1750 1751 /* reset ring buffer */ 1752 ring->wptr = 0; 1753 amdgpu_ring_clear_ring(ring); 1754 mutex_lock(&adev->srbm_mutex); 1755 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1756 gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1757 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1758 mutex_unlock(&adev->srbm_mutex); 1759 } else { 1760 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1761 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1762 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1763 mutex_lock(&adev->srbm_mutex); 1764 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1765 gfx_v9_4_3_mqd_init(ring); 1766 gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1767 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1768 mutex_unlock(&adev->srbm_mutex); 1769 1770 if (adev->gfx.kiq[xcc_id].mqd_backup) 1771 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1772 } 1773 1774 return 0; 1775 } 1776 1777 static int gfx_v9_4_3_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1778 { 1779 struct amdgpu_device *adev = ring->adev; 1780 struct v9_mqd *mqd = ring->mqd_ptr; 1781 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1782 struct v9_mqd *tmp_mqd; 1783 1784 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1785 * is not be initialized before 1786 */ 1787 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1788 1789 if (!tmp_mqd->cp_hqd_pq_control || 1790 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1791 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1792 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1793 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1794 mutex_lock(&adev->srbm_mutex); 1795 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1796 gfx_v9_4_3_mqd_init(ring); 1797 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1798 mutex_unlock(&adev->srbm_mutex); 1799 1800 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1801 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1802 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 1803 /* reset MQD to a clean status */ 1804 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1805 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1806 1807 /* reset ring buffer */ 1808 ring->wptr = 0; 1809 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1810 amdgpu_ring_clear_ring(ring); 1811 } else { 1812 amdgpu_ring_clear_ring(ring); 1813 } 1814 1815 return 0; 1816 } 1817 1818 static int gfx_v9_4_3_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1819 { 1820 struct amdgpu_ring *ring; 1821 int r; 1822 1823 ring = &adev->gfx.kiq[xcc_id].ring; 1824 1825 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1826 if (unlikely(r != 0)) 1827 return r; 1828 1829 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1830 if (unlikely(r != 0)) 1831 return r; 1832 1833 gfx_v9_4_3_kiq_init_queue(ring, xcc_id); 1834 amdgpu_bo_kunmap(ring->mqd_obj); 1835 ring->mqd_ptr = NULL; 1836 amdgpu_bo_unreserve(ring->mqd_obj); 1837 ring->sched.ready = true; 1838 return 0; 1839 } 1840 1841 static int gfx_v9_4_3_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1842 { 1843 struct amdgpu_ring *ring = NULL; 1844 int r = 0, i; 1845 1846 gfx_v9_4_3_cp_compute_enable(adev, true, xcc_id); 1847 1848 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1849 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1850 1851 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1852 if (unlikely(r != 0)) 1853 goto done; 1854 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1855 if (!r) { 1856 r = gfx_v9_4_3_kcq_init_queue(ring, xcc_id); 1857 amdgpu_bo_kunmap(ring->mqd_obj); 1858 ring->mqd_ptr = NULL; 1859 } 1860 amdgpu_bo_unreserve(ring->mqd_obj); 1861 if (r) 1862 goto done; 1863 } 1864 1865 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1866 done: 1867 return r; 1868 } 1869 1870 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1871 { 1872 int r, i, j; 1873 struct amdgpu_ring *ring; 1874 1875 for (i = 0; i < adev->gfx.num_xcd; i++) { 1876 gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1877 1878 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1879 gfx_v9_4_3_disable_gpa_mode(adev, i); 1880 1881 r = gfx_v9_4_3_cp_compute_load_microcode(adev, i); 1882 if (r) 1883 return r; 1884 } 1885 1886 r = gfx_v9_4_3_kiq_resume(adev, i); 1887 if (r) 1888 return r; 1889 1890 r = gfx_v9_4_3_kcq_resume(adev, i); 1891 if (r) 1892 return r; 1893 1894 /* skip ring test on slave kcq */ 1895 if (amdgpu_gfx_is_master_xcc(adev, i)) { 1896 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1897 ring = &adev->gfx.compute_ring[j + 1898 i * adev->gfx.num_compute_rings]; 1899 amdgpu_ring_test_helper(ring); 1900 } 1901 } 1902 1903 gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1904 } 1905 1906 return 0; 1907 } 1908 1909 static void gfx_v9_4_3_cp_enable(struct amdgpu_device *adev, bool enable, 1910 int xcc_id) 1911 { 1912 gfx_v9_4_3_cp_compute_enable(adev, enable, xcc_id); 1913 } 1914 1915 static int gfx_v9_4_3_hw_init(void *handle) 1916 { 1917 int r; 1918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1919 1920 gfx_v9_4_3_init_golden_registers(adev); 1921 1922 gfx_v9_4_3_constants_init(adev); 1923 1924 r = adev->gfx.rlc.funcs->resume(adev); 1925 if (r) 1926 return r; 1927 1928 r = gfx_v9_4_3_cp_resume(adev); 1929 if (r) 1930 return r; 1931 1932 return r; 1933 } 1934 1935 static int gfx_v9_4_3_hw_fini(void *handle) 1936 { 1937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1938 int i; 1939 1940 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 1941 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 1942 1943 for (i = 0; i < adev->gfx.num_xcd; i++) { 1944 if (amdgpu_gfx_disable_kcq(adev, i)) 1945 DRM_ERROR("XCD %d KCQ disable failed\n", i); 1946 1947 /* Use deinitialize sequence from CAIL when unbinding device 1948 * from driver, otherwise KIQ is hanging when binding back 1949 */ 1950 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1951 mutex_lock(&adev->srbm_mutex); 1952 soc15_grbm_select(adev, adev->gfx.kiq[i].ring.me, 1953 adev->gfx.kiq[i].ring.pipe, 1954 adev->gfx.kiq[i].ring.queue, 0, i); 1955 gfx_v9_4_3_kiq_fini_register(&adev->gfx.kiq[i].ring, i); 1956 soc15_grbm_select(adev, 0, 0, 0, 0, i); 1957 mutex_unlock(&adev->srbm_mutex); 1958 } 1959 1960 gfx_v9_4_3_cp_enable(adev, false, i); 1961 } 1962 1963 /* Skip suspend with A+A reset */ 1964 if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) { 1965 dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n"); 1966 return 0; 1967 } 1968 1969 adev->gfx.rlc.funcs->stop(adev); 1970 return 0; 1971 } 1972 1973 static int gfx_v9_4_3_suspend(void *handle) 1974 { 1975 return gfx_v9_4_3_hw_fini(handle); 1976 } 1977 1978 static int gfx_v9_4_3_resume(void *handle) 1979 { 1980 return gfx_v9_4_3_hw_init(handle); 1981 } 1982 1983 static bool gfx_v9_4_3_is_idle(void *handle) 1984 { 1985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1986 int i; 1987 1988 for (i = 0; i < adev->gfx.num_xcd; i++) { 1989 if (REG_GET_FIELD(RREG32_SOC15(GC, i, regGRBM_STATUS), 1990 GRBM_STATUS, GUI_ACTIVE)) 1991 return false; 1992 } 1993 return true; 1994 } 1995 1996 static int gfx_v9_4_3_wait_for_idle(void *handle) 1997 { 1998 unsigned i; 1999 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2000 2001 for (i = 0; i < adev->usec_timeout; i++) { 2002 if (gfx_v9_4_3_is_idle(handle)) 2003 return 0; 2004 udelay(1); 2005 } 2006 return -ETIMEDOUT; 2007 } 2008 2009 static int gfx_v9_4_3_soft_reset(void *handle) 2010 { 2011 u32 grbm_soft_reset = 0; 2012 u32 tmp; 2013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2014 2015 /* GRBM_STATUS */ 2016 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS); 2017 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2018 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2019 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2020 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2021 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2022 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2023 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2024 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2025 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2026 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2027 } 2028 2029 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2030 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2031 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2032 } 2033 2034 /* GRBM_STATUS2 */ 2035 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2); 2036 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2037 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2038 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2039 2040 2041 if (grbm_soft_reset) { 2042 /* stop the rlc */ 2043 adev->gfx.rlc.funcs->stop(adev); 2044 2045 /* Disable MEC parsing/prefetching */ 2046 gfx_v9_4_3_cp_compute_enable(adev, false, 0); 2047 2048 if (grbm_soft_reset) { 2049 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2050 tmp |= grbm_soft_reset; 2051 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2052 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 2053 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2054 2055 udelay(50); 2056 2057 tmp &= ~grbm_soft_reset; 2058 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 2059 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2060 } 2061 2062 /* Wait a little for things to settle down */ 2063 udelay(50); 2064 } 2065 return 0; 2066 } 2067 2068 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2069 uint32_t vmid, 2070 uint32_t gds_base, uint32_t gds_size, 2071 uint32_t gws_base, uint32_t gws_size, 2072 uint32_t oa_base, uint32_t oa_size) 2073 { 2074 struct amdgpu_device *adev = ring->adev; 2075 2076 /* GDS Base */ 2077 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2078 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 2079 gds_base); 2080 2081 /* GDS Size */ 2082 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2083 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 2084 gds_size); 2085 2086 /* GWS */ 2087 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2088 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 2089 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2090 2091 /* OA */ 2092 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2093 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 2094 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2095 } 2096 2097 static int gfx_v9_4_3_early_init(void *handle) 2098 { 2099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2100 2101 /* hardcode in emulation phase */ 2102 adev->gfx.num_xcd = 1; 2103 adev->gfx.num_xcc_per_xcp = 1; 2104 adev->gfx.partition_mode = AMDGPU_SPX_PARTITION_MODE; 2105 2106 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2107 AMDGPU_MAX_COMPUTE_RINGS); 2108 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2109 gfx_v9_4_3_set_ring_funcs(adev); 2110 gfx_v9_4_3_set_irq_funcs(adev); 2111 gfx_v9_4_3_set_gds_init(adev); 2112 gfx_v9_4_3_set_rlc_funcs(adev); 2113 2114 return gfx_v9_4_3_init_microcode(adev); 2115 } 2116 2117 static int gfx_v9_4_3_late_init(void *handle) 2118 { 2119 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2120 int r; 2121 2122 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2123 if (r) 2124 return r; 2125 2126 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2127 if (r) 2128 return r; 2129 2130 return 0; 2131 } 2132 2133 static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2134 bool enable, int xcc_id) 2135 { 2136 uint32_t data, def; 2137 2138 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2139 2140 /* It is disabled by HW by default */ 2141 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2142 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2143 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2144 2145 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2146 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2147 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2148 2149 /* only for Vega10 & Raven1 */ 2150 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 2151 2152 if (def != data) 2153 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2154 2155 /* MGLS is a global flag to control all MGLS in GFX */ 2156 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2157 /* 2 - RLC memory Light sleep */ 2158 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2159 def = data = RREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL); 2160 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2161 if (def != data) 2162 WREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL, data); 2163 } 2164 /* 3 - CP memory Light sleep */ 2165 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2166 def = data = RREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL); 2167 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2168 if (def != data) 2169 WREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL, data); 2170 } 2171 } 2172 } else { 2173 /* 1 - MGCG_OVERRIDE */ 2174 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2175 2176 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2177 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2178 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2179 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2180 2181 if (def != data) 2182 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2183 2184 /* 2 - disable MGLS in RLC */ 2185 data = RREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL); 2186 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2187 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2188 WREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL, data); 2189 } 2190 2191 /* 3 - disable MGLS in CP */ 2192 data = RREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL); 2193 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2194 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2195 WREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL, data); 2196 } 2197 } 2198 2199 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2200 } 2201 2202 static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2203 bool enable, int xcc_id) 2204 { 2205 uint32_t def, data; 2206 2207 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2208 2209 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2210 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2211 /* unset CGCG override */ 2212 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2213 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2214 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2215 else 2216 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2217 /* update CGCG and CGLS override bits */ 2218 if (def != data) 2219 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2220 2221 /* enable cgcg FSM(0x0000363F) */ 2222 def = RREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL); 2223 2224 if (adev->asic_type == CHIP_ARCTURUS) 2225 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2226 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2227 else 2228 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2229 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2230 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2231 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2232 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2233 if (def != data) 2234 WREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL, data); 2235 2236 /* set IDLE_POLL_COUNT(0x00900100) */ 2237 def = RREG32_SOC15(GC, xcc_id, regCP_RB_WPTR_POLL_CNTL); 2238 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2239 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2240 if (def != data) 2241 WREG32_SOC15(GC, xcc_id, regCP_RB_WPTR_POLL_CNTL, data); 2242 } else { 2243 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL); 2244 /* reset CGCG/CGLS bits */ 2245 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2246 /* disable cgcg and cgls in FSM */ 2247 if (def != data) 2248 WREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL, data); 2249 } 2250 2251 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2252 } 2253 2254 static int gfx_v9_4_3_update_gfx_clock_gating(struct amdgpu_device *adev, 2255 bool enable, int xcc_id) 2256 { 2257 if (enable) { 2258 /* CGCG/CGLS should be enabled after MGCG/MGLS 2259 * === MGCG + MGLS === 2260 */ 2261 gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2262 /* === CGCG + CGLS === */ 2263 gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2264 } else { 2265 /* CGCG/CGLS should be disabled before MGCG/MGLS 2266 * === CGCG + CGLS === 2267 */ 2268 gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2269 /* === MGCG + MGLS === */ 2270 gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2271 } 2272 return 0; 2273 } 2274 2275 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2276 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2277 .set_safe_mode = gfx_v9_4_3_set_safe_mode, 2278 .unset_safe_mode = gfx_v9_4_3_unset_safe_mode, 2279 .init = gfx_v9_4_3_rlc_init, 2280 .get_csb_size = gfx_v9_4_3_get_csb_size, 2281 .get_csb_buffer = gfx_v9_4_3_get_csb_buffer, 2282 .resume = gfx_v9_4_3_rlc_resume, 2283 .stop = gfx_v9_4_3_rlc_stop, 2284 .reset = gfx_v9_4_3_rlc_reset, 2285 .start = gfx_v9_4_3_rlc_start, 2286 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2287 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2288 }; 2289 2290 static int gfx_v9_4_3_set_powergating_state(void *handle, 2291 enum amd_powergating_state state) 2292 { 2293 return 0; 2294 } 2295 2296 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2297 enum amd_clockgating_state state) 2298 { 2299 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2300 int i; 2301 2302 if (amdgpu_sriov_vf(adev)) 2303 return 0; 2304 2305 switch (adev->ip_versions[GC_HWIP][0]) { 2306 case IP_VERSION(9, 4, 3): 2307 for (i = 0; i < adev->gfx.num_xcd; i++) 2308 gfx_v9_4_3_update_gfx_clock_gating(adev, 2309 state == AMD_CG_STATE_GATE, i); 2310 break; 2311 default: 2312 break; 2313 } 2314 return 0; 2315 } 2316 2317 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2318 { 2319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2320 int data; 2321 2322 if (amdgpu_sriov_vf(adev)) 2323 *flags = 0; 2324 2325 /* AMD_CG_SUPPORT_GFX_MGCG */ 2326 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGTT_MGCG_OVERRIDE)); 2327 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2328 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2329 2330 /* AMD_CG_SUPPORT_GFX_CGCG */ 2331 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGCG_CGLS_CTRL)); 2332 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2333 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2334 2335 /* AMD_CG_SUPPORT_GFX_CGLS */ 2336 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2337 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2338 2339 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2340 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_MEM_SLP_CNTL)); 2341 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2342 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2343 2344 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2345 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regCP_MEM_SLP_CNTL)); 2346 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2347 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2348 } 2349 2350 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2351 { 2352 struct amdgpu_device *adev = ring->adev; 2353 u32 ref_and_mask, reg_mem_engine; 2354 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2355 2356 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2357 switch (ring->me) { 2358 case 1: 2359 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2360 break; 2361 case 2: 2362 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2363 break; 2364 default: 2365 return; 2366 } 2367 reg_mem_engine = 0; 2368 } else { 2369 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2370 reg_mem_engine = 1; /* pfp */ 2371 } 2372 2373 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2374 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2375 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2376 ref_and_mask, ref_and_mask, 0x20); 2377 } 2378 2379 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2380 struct amdgpu_job *job, 2381 struct amdgpu_ib *ib, 2382 uint32_t flags) 2383 { 2384 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2385 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2386 2387 /* Currently, there is a high possibility to get wave ID mismatch 2388 * between ME and GDS, leading to a hw deadlock, because ME generates 2389 * different wave IDs than the GDS expects. This situation happens 2390 * randomly when at least 5 compute pipes use GDS ordered append. 2391 * The wave IDs generated by ME are also wrong after suspend/resume. 2392 * Those are probably bugs somewhere else in the kernel driver. 2393 * 2394 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2395 * GDS to 0 for this ring (me/pipe). 2396 */ 2397 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2398 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2399 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2400 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2401 } 2402 2403 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2404 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2405 amdgpu_ring_write(ring, 2406 #ifdef __BIG_ENDIAN 2407 (2 << 0) | 2408 #endif 2409 lower_32_bits(ib->gpu_addr)); 2410 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2411 amdgpu_ring_write(ring, control); 2412 } 2413 2414 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2415 u64 seq, unsigned flags) 2416 { 2417 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2418 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2419 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2420 2421 /* RELEASE_MEM - flush caches, send int */ 2422 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2423 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2424 EOP_TC_NC_ACTION_EN) : 2425 (EOP_TCL1_ACTION_EN | 2426 EOP_TC_ACTION_EN | 2427 EOP_TC_WB_ACTION_EN | 2428 EOP_TC_MD_ACTION_EN)) | 2429 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2430 EVENT_INDEX(5))); 2431 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2432 2433 /* 2434 * the address should be Qword aligned if 64bit write, Dword 2435 * aligned if only send 32bit data low (discard data high) 2436 */ 2437 if (write64bit) 2438 BUG_ON(addr & 0x7); 2439 else 2440 BUG_ON(addr & 0x3); 2441 amdgpu_ring_write(ring, lower_32_bits(addr)); 2442 amdgpu_ring_write(ring, upper_32_bits(addr)); 2443 amdgpu_ring_write(ring, lower_32_bits(seq)); 2444 amdgpu_ring_write(ring, upper_32_bits(seq)); 2445 amdgpu_ring_write(ring, 0); 2446 } 2447 2448 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2449 { 2450 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2451 uint32_t seq = ring->fence_drv.sync_seq; 2452 uint64_t addr = ring->fence_drv.gpu_addr; 2453 2454 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2455 lower_32_bits(addr), upper_32_bits(addr), 2456 seq, 0xffffffff, 4); 2457 } 2458 2459 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2460 unsigned vmid, uint64_t pd_addr) 2461 { 2462 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2463 } 2464 2465 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2466 { 2467 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2468 } 2469 2470 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2471 { 2472 u64 wptr; 2473 2474 /* XXX check if swapping is necessary on BE */ 2475 if (ring->use_doorbell) 2476 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2477 else 2478 BUG(); 2479 return wptr; 2480 } 2481 2482 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2483 { 2484 struct amdgpu_device *adev = ring->adev; 2485 2486 /* XXX check if swapping is necessary on BE */ 2487 if (ring->use_doorbell) { 2488 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2489 WDOORBELL64(ring->doorbell_index, ring->wptr); 2490 } else { 2491 BUG(); /* only DOORBELL method supported on gfx9 now */ 2492 } 2493 } 2494 2495 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2496 u64 seq, unsigned int flags) 2497 { 2498 struct amdgpu_device *adev = ring->adev; 2499 2500 /* we only allocate 32bit for each seq wb address */ 2501 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2502 2503 /* write fence seq to the "addr" */ 2504 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2505 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2506 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2507 amdgpu_ring_write(ring, lower_32_bits(addr)); 2508 amdgpu_ring_write(ring, upper_32_bits(addr)); 2509 amdgpu_ring_write(ring, lower_32_bits(seq)); 2510 2511 if (flags & AMDGPU_FENCE_FLAG_INT) { 2512 /* set register to trigger INT */ 2513 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2514 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2515 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2516 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 2517 amdgpu_ring_write(ring, 0); 2518 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2519 } 2520 } 2521 2522 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2523 uint32_t reg_val_offs) 2524 { 2525 struct amdgpu_device *adev = ring->adev; 2526 2527 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2528 amdgpu_ring_write(ring, 0 | /* src: register*/ 2529 (5 << 8) | /* dst: memory */ 2530 (1 << 20)); /* write confirm */ 2531 amdgpu_ring_write(ring, reg); 2532 amdgpu_ring_write(ring, 0); 2533 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2534 reg_val_offs * 4)); 2535 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2536 reg_val_offs * 4)); 2537 } 2538 2539 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2540 uint32_t val) 2541 { 2542 uint32_t cmd = 0; 2543 2544 switch (ring->funcs->type) { 2545 case AMDGPU_RING_TYPE_GFX: 2546 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2547 break; 2548 case AMDGPU_RING_TYPE_KIQ: 2549 cmd = (1 << 16); /* no inc addr */ 2550 break; 2551 default: 2552 cmd = WR_CONFIRM; 2553 break; 2554 } 2555 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2556 amdgpu_ring_write(ring, cmd); 2557 amdgpu_ring_write(ring, reg); 2558 amdgpu_ring_write(ring, 0); 2559 amdgpu_ring_write(ring, val); 2560 } 2561 2562 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2563 uint32_t val, uint32_t mask) 2564 { 2565 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2566 } 2567 2568 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2569 uint32_t reg0, uint32_t reg1, 2570 uint32_t ref, uint32_t mask) 2571 { 2572 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2573 ref, mask); 2574 } 2575 2576 static void gfx_v9_4_3_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 2577 int me, int pipe, 2578 enum amdgpu_interrupt_state state, 2579 int xcc_id) 2580 { 2581 u32 mec_int_cntl, mec_int_cntl_reg; 2582 2583 /* 2584 * amdgpu controls only the first MEC. That's why this function only 2585 * handles the setting of interrupts for this specific MEC. All other 2586 * pipes' interrupts are set by amdkfd. 2587 */ 2588 2589 if (me == 1) { 2590 switch (pipe) { 2591 case 0: 2592 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE0_INT_CNTL); 2593 break; 2594 case 1: 2595 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE1_INT_CNTL); 2596 break; 2597 case 2: 2598 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE2_INT_CNTL); 2599 break; 2600 case 3: 2601 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE3_INT_CNTL); 2602 break; 2603 default: 2604 DRM_DEBUG("invalid pipe %d\n", pipe); 2605 return; 2606 } 2607 } else { 2608 DRM_DEBUG("invalid me %d\n", me); 2609 return; 2610 } 2611 2612 switch (state) { 2613 case AMDGPU_IRQ_STATE_DISABLE: 2614 mec_int_cntl = RREG32(mec_int_cntl_reg); 2615 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2616 TIME_STAMP_INT_ENABLE, 0); 2617 WREG32(mec_int_cntl_reg, mec_int_cntl); 2618 break; 2619 case AMDGPU_IRQ_STATE_ENABLE: 2620 mec_int_cntl = RREG32(mec_int_cntl_reg); 2621 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2622 TIME_STAMP_INT_ENABLE, 1); 2623 WREG32(mec_int_cntl_reg, mec_int_cntl); 2624 break; 2625 default: 2626 break; 2627 } 2628 } 2629 2630 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2631 struct amdgpu_irq_src *source, 2632 unsigned type, 2633 enum amdgpu_interrupt_state state) 2634 { 2635 int i; 2636 2637 switch (state) { 2638 case AMDGPU_IRQ_STATE_DISABLE: 2639 case AMDGPU_IRQ_STATE_ENABLE: 2640 for (i = 0; i < adev->gfx.num_xcd; i++) 2641 WREG32_FIELD15_PREREG(GC, i, CP_INT_CNTL_RING0, 2642 PRIV_REG_INT_ENABLE, 2643 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2644 break; 2645 default: 2646 break; 2647 } 2648 2649 return 0; 2650 } 2651 2652 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2653 struct amdgpu_irq_src *source, 2654 unsigned type, 2655 enum amdgpu_interrupt_state state) 2656 { 2657 int i; 2658 2659 switch (state) { 2660 case AMDGPU_IRQ_STATE_DISABLE: 2661 case AMDGPU_IRQ_STATE_ENABLE: 2662 for (i = 0; i < adev->gfx.num_xcd; i++) 2663 WREG32_FIELD15_PREREG(GC, i, CP_INT_CNTL_RING0, 2664 PRIV_INSTR_INT_ENABLE, 2665 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2666 break; 2667 default: 2668 break; 2669 } 2670 2671 return 0; 2672 } 2673 2674 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2675 struct amdgpu_irq_src *src, 2676 unsigned type, 2677 enum amdgpu_interrupt_state state) 2678 { 2679 int i; 2680 for (i = 0; i < adev->gfx.num_xcd; i++) { 2681 switch (type) { 2682 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2683 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 0, state, i); 2684 break; 2685 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2686 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 1, state, i); 2687 break; 2688 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2689 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 2, state, i); 2690 break; 2691 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2692 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 3, state, i); 2693 break; 2694 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2695 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 0, state, i); 2696 break; 2697 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2698 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 1, state, i); 2699 break; 2700 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2701 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 2, state, i); 2702 break; 2703 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2704 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 3, state, i); 2705 break; 2706 default: 2707 break; 2708 } 2709 } 2710 2711 return 0; 2712 } 2713 2714 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2715 struct amdgpu_irq_src *source, 2716 struct amdgpu_iv_entry *entry) 2717 { 2718 int i; 2719 u8 me_id, pipe_id, queue_id; 2720 struct amdgpu_ring *ring; 2721 2722 DRM_DEBUG("IH: CP EOP\n"); 2723 me_id = (entry->ring_id & 0x0c) >> 2; 2724 pipe_id = (entry->ring_id & 0x03) >> 0; 2725 queue_id = (entry->ring_id & 0x70) >> 4; 2726 2727 switch (me_id) { 2728 case 0: 2729 case 1: 2730 case 2: 2731 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2732 ring = &adev->gfx.compute_ring[i]; 2733 /* Per-queue interrupt is supported for MEC starting from VI. 2734 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2735 */ 2736 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2737 amdgpu_fence_process(ring); 2738 } 2739 break; 2740 } 2741 return 0; 2742 } 2743 2744 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2745 struct amdgpu_iv_entry *entry) 2746 { 2747 u8 me_id, pipe_id, queue_id; 2748 struct amdgpu_ring *ring; 2749 int i; 2750 2751 me_id = (entry->ring_id & 0x0c) >> 2; 2752 pipe_id = (entry->ring_id & 0x03) >> 0; 2753 queue_id = (entry->ring_id & 0x70) >> 4; 2754 2755 switch (me_id) { 2756 case 0: 2757 case 1: 2758 case 2: 2759 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2760 ring = &adev->gfx.compute_ring[i]; 2761 if (ring->me == me_id && ring->pipe == pipe_id && 2762 ring->queue == queue_id) 2763 drm_sched_fault(&ring->sched); 2764 } 2765 break; 2766 } 2767 } 2768 2769 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2770 struct amdgpu_irq_src *source, 2771 struct amdgpu_iv_entry *entry) 2772 { 2773 DRM_ERROR("Illegal register access in command stream\n"); 2774 gfx_v9_4_3_fault(adev, entry); 2775 return 0; 2776 } 2777 2778 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2779 struct amdgpu_irq_src *source, 2780 struct amdgpu_iv_entry *entry) 2781 { 2782 DRM_ERROR("Illegal instruction in command stream\n"); 2783 gfx_v9_4_3_fault(adev, entry); 2784 return 0; 2785 } 2786 2787 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2788 { 2789 const unsigned int cp_coher_cntl = 2790 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2791 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2792 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2793 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2794 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2795 2796 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2797 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2798 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2799 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2800 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2801 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2802 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2803 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2804 } 2805 2806 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2807 uint32_t pipe, bool enable) 2808 { 2809 struct amdgpu_device *adev = ring->adev; 2810 uint32_t val; 2811 uint32_t wcl_cs_reg; 2812 2813 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2814 val = enable ? 0x1 : 0x7f; 2815 2816 switch (pipe) { 2817 case 0: 2818 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS0); 2819 break; 2820 case 1: 2821 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS1); 2822 break; 2823 case 2: 2824 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS2); 2825 break; 2826 case 3: 2827 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS3); 2828 break; 2829 default: 2830 DRM_DEBUG("invalid pipe %d\n", pipe); 2831 return; 2832 } 2833 2834 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2835 2836 } 2837 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2838 { 2839 struct amdgpu_device *adev = ring->adev; 2840 uint32_t val; 2841 int i; 2842 2843 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2844 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2845 * around 25% of gpu resources. 2846 */ 2847 val = enable ? 0x1f : 0x07ffffff; 2848 amdgpu_ring_emit_wreg(ring, 2849 SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_GFX), 2850 val); 2851 2852 /* Restrict waves for normal/low priority compute queues as well 2853 * to get best QoS for high priority compute jobs. 2854 * 2855 * amdgpu controls only 1st ME(0-3 CS pipes). 2856 */ 2857 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2858 if (i != ring->pipe) 2859 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 2860 2861 } 2862 } 2863 2864 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 2865 .name = "gfx_v9_4_3", 2866 .early_init = gfx_v9_4_3_early_init, 2867 .late_init = gfx_v9_4_3_late_init, 2868 .sw_init = gfx_v9_4_3_sw_init, 2869 .sw_fini = gfx_v9_4_3_sw_fini, 2870 .hw_init = gfx_v9_4_3_hw_init, 2871 .hw_fini = gfx_v9_4_3_hw_fini, 2872 .suspend = gfx_v9_4_3_suspend, 2873 .resume = gfx_v9_4_3_resume, 2874 .is_idle = gfx_v9_4_3_is_idle, 2875 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 2876 .soft_reset = gfx_v9_4_3_soft_reset, 2877 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 2878 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 2879 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 2880 }; 2881 2882 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 2883 .type = AMDGPU_RING_TYPE_COMPUTE, 2884 .align_mask = 0xff, 2885 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 2886 .support_64bit_ptrs = true, 2887 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 2888 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 2889 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 2890 .emit_frame_size = 2891 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 2892 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 2893 5 + /* hdp invalidate */ 2894 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 2895 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 2896 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2897 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 2898 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 2899 7 + /* gfx_v9_4_3_emit_mem_sync */ 2900 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 2901 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 2902 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 2903 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 2904 .emit_fence = gfx_v9_4_3_ring_emit_fence, 2905 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 2906 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 2907 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 2908 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 2909 .test_ring = gfx_v9_4_3_ring_test_ring, 2910 .test_ib = gfx_v9_4_3_ring_test_ib, 2911 .insert_nop = amdgpu_ring_insert_nop, 2912 .pad_ib = amdgpu_ring_generic_pad_ib, 2913 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 2914 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 2915 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 2916 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 2917 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 2918 }; 2919 2920 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 2921 .type = AMDGPU_RING_TYPE_KIQ, 2922 .align_mask = 0xff, 2923 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 2924 .support_64bit_ptrs = true, 2925 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 2926 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 2927 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 2928 .emit_frame_size = 2929 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 2930 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 2931 5 + /* hdp invalidate */ 2932 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 2933 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 2934 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2935 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 2936 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 2937 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 2938 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 2939 .test_ring = gfx_v9_4_3_ring_test_ring, 2940 .insert_nop = amdgpu_ring_insert_nop, 2941 .pad_ib = amdgpu_ring_generic_pad_ib, 2942 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 2943 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 2944 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 2945 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 2946 }; 2947 2948 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 2949 { 2950 int i, j; 2951 2952 for (i = 0; i < adev->gfx.num_xcd; i++) { 2953 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 2954 2955 for (j = 0; j < adev->gfx.num_compute_rings; j++) 2956 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 2957 = &gfx_v9_4_3_ring_funcs_compute; 2958 } 2959 } 2960 2961 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 2962 .set = gfx_v9_4_3_set_eop_interrupt_state, 2963 .process = gfx_v9_4_3_eop_irq, 2964 }; 2965 2966 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 2967 .set = gfx_v9_4_3_set_priv_reg_fault_state, 2968 .process = gfx_v9_4_3_priv_reg_irq, 2969 }; 2970 2971 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 2972 .set = gfx_v9_4_3_set_priv_inst_fault_state, 2973 .process = gfx_v9_4_3_priv_inst_irq, 2974 }; 2975 2976 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 2977 { 2978 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 2979 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 2980 2981 adev->gfx.priv_reg_irq.num_types = 1; 2982 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 2983 2984 adev->gfx.priv_inst_irq.num_types = 1; 2985 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 2986 } 2987 2988 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 2989 { 2990 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 2991 } 2992 2993 2994 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 2995 { 2996 /* init asci gds info */ 2997 switch (adev->ip_versions[GC_HWIP][0]) { 2998 case IP_VERSION(9, 4, 3): 2999 /* 9.4.3 removed all the GDS internal memory, 3000 * only support GWS opcode in kernel, like barrier 3001 * semaphore.etc */ 3002 adev->gds.gds_size = 0; 3003 break; 3004 default: 3005 adev->gds.gds_size = 0x10000; 3006 break; 3007 } 3008 3009 switch (adev->ip_versions[GC_HWIP][0]) { 3010 case IP_VERSION(9, 4, 3): 3011 /* deprecated for 9.4.3, no usage at all */ 3012 adev->gds.gds_compute_max_wave_id = 0; 3013 break; 3014 default: 3015 /* this really depends on the chip */ 3016 adev->gds.gds_compute_max_wave_id = 0x7ff; 3017 break; 3018 } 3019 3020 adev->gds.gws_size = 64; 3021 adev->gds.oa_size = 16; 3022 } 3023 3024 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3025 u32 bitmap) 3026 { 3027 u32 data; 3028 3029 if (!bitmap) 3030 return; 3031 3032 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3033 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3034 3035 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 3036 } 3037 3038 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 3039 { 3040 u32 data, mask; 3041 3042 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 3043 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 3044 3045 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3046 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3047 3048 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3049 3050 return (~data) & mask; 3051 } 3052 3053 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 3054 struct amdgpu_cu_info *cu_info) 3055 { 3056 int i, j, k, counter, active_cu_number = 0; 3057 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3058 unsigned disable_masks[4 * 4]; 3059 3060 if (!adev || !cu_info) 3061 return -EINVAL; 3062 3063 /* 3064 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 3065 */ 3066 if (adev->gfx.config.max_shader_engines * 3067 adev->gfx.config.max_sh_per_se > 16) 3068 return -EINVAL; 3069 3070 amdgpu_gfx_parse_disable_cu(disable_masks, 3071 adev->gfx.config.max_shader_engines, 3072 adev->gfx.config.max_sh_per_se); 3073 3074 mutex_lock(&adev->grbm_idx_mutex); 3075 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3076 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3077 mask = 1; 3078 ao_bitmap = 0; 3079 counter = 0; 3080 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, 0); 3081 gfx_v9_4_3_set_user_cu_inactive_bitmap( 3082 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 3083 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 3084 3085 /* 3086 * The bitmap(and ao_cu_bitmap) in cu_info structure is 3087 * 4x4 size array, and it's usually suitable for Vega 3088 * ASICs which has 4*2 SE/SH layout. 3089 * But for Arcturus, SE/SH layout is changed to 8*1. 3090 * To mostly reduce the impact, we make it compatible 3091 * with current bitmap array as below: 3092 * SE4,SH0 --> bitmap[0][1] 3093 * SE5,SH0 --> bitmap[1][1] 3094 * SE6,SH0 --> bitmap[2][1] 3095 * SE7,SH0 --> bitmap[3][1] 3096 */ 3097 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 3098 3099 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3100 if (bitmap & mask) { 3101 if (counter < adev->gfx.config.max_cu_per_sh) 3102 ao_bitmap |= mask; 3103 counter++; 3104 } 3105 mask <<= 1; 3106 } 3107 active_cu_number += counter; 3108 if (i < 2 && j < 2) 3109 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3110 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 3111 } 3112 } 3113 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3114 mutex_unlock(&adev->grbm_idx_mutex); 3115 3116 cu_info->number = active_cu_number; 3117 cu_info->ao_cu_mask = ao_cu_mask; 3118 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 3119 3120 return 0; 3121 } 3122 3123 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 3124 .type = AMD_IP_BLOCK_TYPE_GFX, 3125 .major = 9, 3126 .minor = 4, 3127 .rev = 0, 3128 .funcs = &gfx_v9_4_3_ip_funcs, 3129 }; 3130