1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 50 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 51 52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 57 struct amdgpu_cu_info *cu_info); 58 59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 60 uint64_t queue_mask) 61 { 62 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 63 amdgpu_ring_write(kiq_ring, 64 PACKET3_SET_RESOURCES_VMID_MASK(0) | 65 /* vmid_mask:0* queue_type:0 (KIQ) */ 66 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 67 amdgpu_ring_write(kiq_ring, 68 lower_32_bits(queue_mask)); /* queue mask lo */ 69 amdgpu_ring_write(kiq_ring, 70 upper_32_bits(queue_mask)); /* queue mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 73 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 74 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 75 } 76 77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring) 79 { 80 struct amdgpu_device *adev = kiq_ring->adev; 81 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 82 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 83 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 84 85 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 86 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 87 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 88 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 89 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 90 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 91 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 92 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 93 /*queue_type: normal compute queue */ 94 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 95 /* alloc format: all_on_one_pipe */ 96 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 97 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 98 /* num_queues: must be 1 */ 99 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 100 amdgpu_ring_write(kiq_ring, 101 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 105 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 106 } 107 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 109 struct amdgpu_ring *ring, 110 enum amdgpu_unmap_queues_action action, 111 u64 gpu_addr, u64 seq) 112 { 113 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 114 115 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 116 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 117 PACKET3_UNMAP_QUEUES_ACTION(action) | 118 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 119 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 120 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 121 amdgpu_ring_write(kiq_ring, 122 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 123 124 if (action == PREEMPT_QUEUES_NO_UNMAP) { 125 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 126 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, seq); 128 } else { 129 amdgpu_ring_write(kiq_ring, 0); 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 } 133 } 134 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 u64 addr, 138 u64 seq) 139 { 140 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 141 142 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 143 amdgpu_ring_write(kiq_ring, 144 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 145 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 146 PACKET3_QUERY_STATUS_COMMAND(2)); 147 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 148 amdgpu_ring_write(kiq_ring, 149 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 150 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 155 } 156 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 158 uint16_t pasid, uint32_t flush_type, 159 bool all_hub) 160 { 161 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 162 amdgpu_ring_write(kiq_ring, 163 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 164 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 165 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 166 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 167 } 168 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 170 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 171 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 172 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 173 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 174 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 175 .set_resources_size = 8, 176 .map_queues_size = 7, 177 .unmap_queues_size = 6, 178 .query_status_size = 7, 179 .invalidate_tlbs_size = 2, 180 }; 181 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 183 { 184 int i, num_xcc; 185 186 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 187 for (i = 0; i < num_xcc; i++) 188 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 189 } 190 191 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 192 { 193 int i, num_xcc, dev_inst; 194 195 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 196 for (i = 0; i < num_xcc; i++) { 197 dev_inst = GET_INST(GC, i); 198 199 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 200 GOLDEN_GB_ADDR_CONFIG); 201 /* Golden settings applied by driver for ASIC with rev_id 0 */ 202 if (adev->rev_id == 0) { 203 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 204 REDUCE_FIFO_DEPTH_BY_2, 2); 205 } 206 } 207 } 208 209 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 210 bool wc, uint32_t reg, uint32_t val) 211 { 212 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 213 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 214 WRITE_DATA_DST_SEL(0) | 215 (wc ? WR_CONFIRM : 0)); 216 amdgpu_ring_write(ring, reg); 217 amdgpu_ring_write(ring, 0); 218 amdgpu_ring_write(ring, val); 219 } 220 221 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 222 int mem_space, int opt, uint32_t addr0, 223 uint32_t addr1, uint32_t ref, uint32_t mask, 224 uint32_t inv) 225 { 226 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 227 amdgpu_ring_write(ring, 228 /* memory (1) or register (0) */ 229 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 230 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 231 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 232 WAIT_REG_MEM_ENGINE(eng_sel))); 233 234 if (mem_space) 235 BUG_ON(addr0 & 0x3); /* Dword align */ 236 amdgpu_ring_write(ring, addr0); 237 amdgpu_ring_write(ring, addr1); 238 amdgpu_ring_write(ring, ref); 239 amdgpu_ring_write(ring, mask); 240 amdgpu_ring_write(ring, inv); /* poll interval */ 241 } 242 243 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 244 { 245 uint32_t scratch_reg0_offset, xcc_offset; 246 struct amdgpu_device *adev = ring->adev; 247 uint32_t tmp = 0; 248 unsigned i; 249 int r; 250 251 /* Use register offset which is local to XCC in the packet */ 252 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 253 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 254 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 255 256 r = amdgpu_ring_alloc(ring, 3); 257 if (r) 258 return r; 259 260 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 261 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 262 amdgpu_ring_write(ring, 0xDEADBEEF); 263 amdgpu_ring_commit(ring); 264 265 for (i = 0; i < adev->usec_timeout; i++) { 266 tmp = RREG32(scratch_reg0_offset); 267 if (tmp == 0xDEADBEEF) 268 break; 269 udelay(1); 270 } 271 272 if (i >= adev->usec_timeout) 273 r = -ETIMEDOUT; 274 return r; 275 } 276 277 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 278 { 279 struct amdgpu_device *adev = ring->adev; 280 struct amdgpu_ib ib; 281 struct dma_fence *f = NULL; 282 283 unsigned index; 284 uint64_t gpu_addr; 285 uint32_t tmp; 286 long r; 287 288 r = amdgpu_device_wb_get(adev, &index); 289 if (r) 290 return r; 291 292 gpu_addr = adev->wb.gpu_addr + (index * 4); 293 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 294 memset(&ib, 0, sizeof(ib)); 295 r = amdgpu_ib_get(adev, NULL, 16, 296 AMDGPU_IB_POOL_DIRECT, &ib); 297 if (r) 298 goto err1; 299 300 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 301 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 302 ib.ptr[2] = lower_32_bits(gpu_addr); 303 ib.ptr[3] = upper_32_bits(gpu_addr); 304 ib.ptr[4] = 0xDEADBEEF; 305 ib.length_dw = 5; 306 307 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 308 if (r) 309 goto err2; 310 311 r = dma_fence_wait_timeout(f, false, timeout); 312 if (r == 0) { 313 r = -ETIMEDOUT; 314 goto err2; 315 } else if (r < 0) { 316 goto err2; 317 } 318 319 tmp = adev->wb.wb[index]; 320 if (tmp == 0xDEADBEEF) 321 r = 0; 322 else 323 r = -EINVAL; 324 325 err2: 326 amdgpu_ib_free(adev, &ib, NULL); 327 dma_fence_put(f); 328 err1: 329 amdgpu_device_wb_free(adev, index); 330 return r; 331 } 332 333 334 /* This value might differs per partition */ 335 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 336 { 337 uint64_t clock; 338 339 amdgpu_gfx_off_ctrl(adev, false); 340 mutex_lock(&adev->gfx.gpu_clock_mutex); 341 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 342 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 343 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 344 mutex_unlock(&adev->gfx.gpu_clock_mutex); 345 amdgpu_gfx_off_ctrl(adev, true); 346 347 return clock; 348 } 349 350 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 351 { 352 amdgpu_ucode_release(&adev->gfx.pfp_fw); 353 amdgpu_ucode_release(&adev->gfx.me_fw); 354 amdgpu_ucode_release(&adev->gfx.ce_fw); 355 amdgpu_ucode_release(&adev->gfx.rlc_fw); 356 amdgpu_ucode_release(&adev->gfx.mec_fw); 357 amdgpu_ucode_release(&adev->gfx.mec2_fw); 358 359 kfree(adev->gfx.rlc.register_list_format); 360 } 361 362 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 363 const char *chip_name) 364 { 365 char fw_name[30]; 366 int err; 367 const struct rlc_firmware_header_v2_0 *rlc_hdr; 368 uint16_t version_major; 369 uint16_t version_minor; 370 371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 372 373 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 374 if (err) 375 goto out; 376 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 377 378 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 379 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 380 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 381 out: 382 if (err) 383 amdgpu_ucode_release(&adev->gfx.rlc_fw); 384 385 return err; 386 } 387 388 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 389 { 390 return true; 391 } 392 393 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 394 { 395 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 396 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 397 } 398 399 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 400 const char *chip_name) 401 { 402 char fw_name[30]; 403 int err; 404 405 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 406 407 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 408 if (err) 409 goto out; 410 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 411 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 412 413 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 414 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 415 416 gfx_v9_4_3_check_if_need_gfxoff(adev); 417 418 out: 419 if (err) 420 amdgpu_ucode_release(&adev->gfx.mec_fw); 421 return err; 422 } 423 424 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 425 { 426 const char *chip_name; 427 int r; 428 429 chip_name = "gc_9_4_3"; 430 431 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 432 if (r) 433 return r; 434 435 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 436 if (r) 437 return r; 438 439 return r; 440 } 441 442 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 443 { 444 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 445 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 446 } 447 448 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 449 { 450 int r, i, num_xcc; 451 u32 *hpd; 452 const __le32 *fw_data; 453 unsigned fw_size; 454 u32 *fw; 455 size_t mec_hpd_size; 456 457 const struct gfx_firmware_header_v1_0 *mec_hdr; 458 459 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 460 for (i = 0; i < num_xcc; i++) 461 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 462 AMDGPU_MAX_COMPUTE_QUEUES); 463 464 /* take ownership of the relevant compute queues */ 465 amdgpu_gfx_compute_queue_acquire(adev); 466 mec_hpd_size = 467 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 468 if (mec_hpd_size) { 469 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 470 AMDGPU_GEM_DOMAIN_VRAM | 471 AMDGPU_GEM_DOMAIN_GTT, 472 &adev->gfx.mec.hpd_eop_obj, 473 &adev->gfx.mec.hpd_eop_gpu_addr, 474 (void **)&hpd); 475 if (r) { 476 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 477 gfx_v9_4_3_mec_fini(adev); 478 return r; 479 } 480 481 if (amdgpu_emu_mode == 1) { 482 for (i = 0; i < mec_hpd_size / 4; i++) { 483 memset((void *)(hpd + i), 0, 4); 484 if (i % 50 == 0) 485 msleep(1); 486 } 487 } else { 488 memset(hpd, 0, mec_hpd_size); 489 } 490 491 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 492 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 493 } 494 495 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 496 497 fw_data = (const __le32 *) 498 (adev->gfx.mec_fw->data + 499 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 500 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 501 502 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 504 &adev->gfx.mec.mec_fw_obj, 505 &adev->gfx.mec.mec_fw_gpu_addr, 506 (void **)&fw); 507 if (r) { 508 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 509 gfx_v9_4_3_mec_fini(adev); 510 return r; 511 } 512 513 memcpy(fw, fw_data, fw_size); 514 515 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 516 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 517 518 return 0; 519 } 520 521 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 522 u32 sh_num, u32 instance, int xcc_id) 523 { 524 u32 data; 525 526 if (instance == 0xffffffff) 527 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 528 INSTANCE_BROADCAST_WRITES, 1); 529 else 530 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 531 INSTANCE_INDEX, instance); 532 533 if (se_num == 0xffffffff) 534 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 535 SE_BROADCAST_WRITES, 1); 536 else 537 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 538 539 if (sh_num == 0xffffffff) 540 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 541 SH_BROADCAST_WRITES, 1); 542 else 543 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 544 545 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 546 } 547 548 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 549 { 550 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 551 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 552 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 553 (address << SQ_IND_INDEX__INDEX__SHIFT) | 554 (SQ_IND_INDEX__FORCE_READ_MASK)); 555 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 556 } 557 558 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 559 uint32_t wave, uint32_t thread, 560 uint32_t regno, uint32_t num, uint32_t *out) 561 { 562 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 563 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 564 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 565 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 566 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 567 (SQ_IND_INDEX__FORCE_READ_MASK) | 568 (SQ_IND_INDEX__AUTO_INCR_MASK)); 569 while (num--) 570 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 571 } 572 573 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 574 uint32_t xcc_id, uint32_t simd, uint32_t wave, 575 uint32_t *dst, int *no_fields) 576 { 577 /* type 1 wave data */ 578 dst[(*no_fields)++] = 1; 579 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 594 } 595 596 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 597 uint32_t wave, uint32_t start, 598 uint32_t size, uint32_t *dst) 599 { 600 wave_read_regs(adev, xcc_id, simd, wave, 0, 601 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 602 } 603 604 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 605 uint32_t wave, uint32_t thread, 606 uint32_t start, uint32_t size, 607 uint32_t *dst) 608 { 609 wave_read_regs(adev, xcc_id, simd, wave, thread, 610 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 611 } 612 613 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 614 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 615 { 616 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 617 } 618 619 620 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 621 int num_xccs_per_xcp) 622 { 623 int ret, i, num_xcc; 624 u32 tmp = 0, regval; 625 626 if (adev->psp.funcs) { 627 ret = psp_spatial_partition(&adev->psp, 628 NUM_XCC(adev->gfx.xcc_mask) / 629 num_xccs_per_xcp); 630 if (ret) 631 return ret; 632 } 633 634 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 635 636 for (i = 0; i < num_xcc; i++) { 637 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 638 num_xccs_per_xcp); 639 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 640 i % num_xccs_per_xcp); 641 regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL); 642 if (regval != tmp) 643 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 644 tmp); 645 } 646 647 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 648 649 return 0; 650 } 651 652 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 653 { 654 int xcc; 655 656 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 657 if (!xcc) { 658 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 659 return -EINVAL; 660 } 661 662 return xcc - 1; 663 } 664 665 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 666 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 667 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 668 .read_wave_data = &gfx_v9_4_3_read_wave_data, 669 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 670 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 671 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 672 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 673 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 674 }; 675 676 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 677 { 678 u32 gb_addr_config; 679 680 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 681 adev->gfx.ras = &gfx_v9_4_3_ras; 682 683 switch (adev->ip_versions[GC_HWIP][0]) { 684 case IP_VERSION(9, 4, 3): 685 adev->gfx.config.max_hw_contexts = 8; 686 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 687 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 688 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 689 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 690 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 691 break; 692 default: 693 BUG(); 694 break; 695 } 696 697 adev->gfx.config.gb_addr_config = gb_addr_config; 698 699 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 700 REG_GET_FIELD( 701 adev->gfx.config.gb_addr_config, 702 GB_ADDR_CONFIG, 703 NUM_PIPES); 704 705 adev->gfx.config.max_tile_pipes = 706 adev->gfx.config.gb_addr_config_fields.num_pipes; 707 708 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 709 REG_GET_FIELD( 710 adev->gfx.config.gb_addr_config, 711 GB_ADDR_CONFIG, 712 NUM_BANKS); 713 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 714 REG_GET_FIELD( 715 adev->gfx.config.gb_addr_config, 716 GB_ADDR_CONFIG, 717 MAX_COMPRESSED_FRAGS); 718 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 719 REG_GET_FIELD( 720 adev->gfx.config.gb_addr_config, 721 GB_ADDR_CONFIG, 722 NUM_RB_PER_SE); 723 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 724 REG_GET_FIELD( 725 adev->gfx.config.gb_addr_config, 726 GB_ADDR_CONFIG, 727 NUM_SHADER_ENGINES); 728 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 729 REG_GET_FIELD( 730 adev->gfx.config.gb_addr_config, 731 GB_ADDR_CONFIG, 732 PIPE_INTERLEAVE_SIZE)); 733 734 return 0; 735 } 736 737 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 738 int xcc_id, int mec, int pipe, int queue) 739 { 740 unsigned irq_type; 741 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 742 unsigned int hw_prio; 743 uint32_t xcc_doorbell_start; 744 745 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 746 ring_id]; 747 748 /* mec0 is me1 */ 749 ring->xcc_id = xcc_id; 750 ring->me = mec + 1; 751 ring->pipe = pipe; 752 ring->queue = queue; 753 754 ring->ring_obj = NULL; 755 ring->use_doorbell = true; 756 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 757 xcc_id * adev->doorbell_index.xcc_doorbell_range; 758 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 759 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 760 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 761 GFX9_MEC_HPD_SIZE; 762 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 763 sprintf(ring->name, "comp_%d.%d.%d.%d", 764 ring->xcc_id, ring->me, ring->pipe, ring->queue); 765 766 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 767 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 768 + ring->pipe; 769 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 770 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 771 /* type-2 packets are deprecated on MEC, use type-3 instead */ 772 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 773 hw_prio, NULL); 774 } 775 776 static int gfx_v9_4_3_sw_init(void *handle) 777 { 778 int i, j, k, r, ring_id, xcc_id, num_xcc; 779 struct amdgpu_kiq *kiq; 780 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 781 782 adev->gfx.mec.num_mec = 2; 783 adev->gfx.mec.num_pipe_per_mec = 4; 784 adev->gfx.mec.num_queue_per_pipe = 8; 785 786 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 787 788 /* EOP Event */ 789 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 790 if (r) 791 return r; 792 793 /* Privileged reg */ 794 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 795 &adev->gfx.priv_reg_irq); 796 if (r) 797 return r; 798 799 /* Privileged inst */ 800 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 801 &adev->gfx.priv_inst_irq); 802 if (r) 803 return r; 804 805 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 806 807 r = adev->gfx.rlc.funcs->init(adev); 808 if (r) { 809 DRM_ERROR("Failed to init rlc BOs!\n"); 810 return r; 811 } 812 813 r = gfx_v9_4_3_mec_init(adev); 814 if (r) { 815 DRM_ERROR("Failed to init MEC BOs!\n"); 816 return r; 817 } 818 819 /* set up the compute queues - allocate horizontally across pipes */ 820 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 821 ring_id = 0; 822 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 823 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 824 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 825 k++) { 826 if (!amdgpu_gfx_is_mec_queue_enabled( 827 adev, xcc_id, i, k, j)) 828 continue; 829 830 r = gfx_v9_4_3_compute_ring_init(adev, 831 ring_id, 832 xcc_id, 833 i, k, j); 834 if (r) 835 return r; 836 837 ring_id++; 838 } 839 } 840 } 841 842 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 843 if (r) { 844 DRM_ERROR("Failed to init KIQ BOs!\n"); 845 return r; 846 } 847 848 kiq = &adev->gfx.kiq[xcc_id]; 849 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 850 if (r) 851 return r; 852 853 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 854 r = amdgpu_gfx_mqd_sw_init(adev, 855 sizeof(struct v9_mqd_allocation), xcc_id); 856 if (r) 857 return r; 858 } 859 860 r = gfx_v9_4_3_gpu_early_init(adev); 861 if (r) 862 return r; 863 864 r = amdgpu_gfx_sysfs_init(adev); 865 if (r) 866 return r; 867 868 return amdgpu_gfx_ras_sw_init(adev); 869 } 870 871 static int gfx_v9_4_3_sw_fini(void *handle) 872 { 873 int i, num_xcc; 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 877 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 878 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 879 880 for (i = 0; i < num_xcc; i++) { 881 amdgpu_gfx_mqd_sw_fini(adev, i); 882 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 883 amdgpu_gfx_kiq_fini(adev, i); 884 } 885 886 gfx_v9_4_3_mec_fini(adev); 887 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 888 gfx_v9_4_3_free_microcode(adev); 889 amdgpu_gfx_sysfs_fini(adev); 890 891 return 0; 892 } 893 894 #define DEFAULT_SH_MEM_BASES (0x6000) 895 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 896 int xcc_id) 897 { 898 int i; 899 uint32_t sh_mem_config; 900 uint32_t sh_mem_bases; 901 902 /* 903 * Configure apertures: 904 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 905 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 906 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 907 */ 908 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 909 910 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 911 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 912 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 913 914 mutex_lock(&adev->srbm_mutex); 915 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 916 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 917 /* CP and shaders */ 918 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 919 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 920 } 921 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 922 mutex_unlock(&adev->srbm_mutex); 923 924 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 925 acccess. These should be enabled by FW for target VMIDs. */ 926 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 927 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 928 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 929 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 930 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 931 } 932 } 933 934 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 935 { 936 int vmid; 937 938 /* 939 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 940 * access. Compute VMIDs should be enabled by FW for target VMIDs, 941 * the driver can enable them for graphics. VMID0 should maintain 942 * access so that HWS firmware can save/restore entries. 943 */ 944 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 945 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 946 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 947 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 948 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 949 } 950 } 951 952 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 953 int xcc_id) 954 { 955 u32 tmp; 956 int i; 957 958 /* XXX SH_MEM regs */ 959 /* where to put LDS, scratch, GPUVM in FSA64 space */ 960 mutex_lock(&adev->srbm_mutex); 961 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 962 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 963 /* CP and shaders */ 964 if (i == 0) { 965 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 966 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 967 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 968 !!adev->gmc.noretry); 969 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 970 regSH_MEM_CONFIG, tmp); 971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 972 regSH_MEM_BASES, 0); 973 } else { 974 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 975 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 976 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 977 !!adev->gmc.noretry); 978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 979 regSH_MEM_CONFIG, tmp); 980 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 981 (adev->gmc.private_aperture_start >> 982 48)); 983 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 984 (adev->gmc.shared_aperture_start >> 985 48)); 986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 987 regSH_MEM_BASES, tmp); 988 } 989 } 990 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 991 992 mutex_unlock(&adev->srbm_mutex); 993 994 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 995 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 996 } 997 998 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 999 { 1000 int i, num_xcc; 1001 1002 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1003 1004 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1005 adev->gfx.config.db_debug2 = 1006 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1007 1008 for (i = 0; i < num_xcc; i++) 1009 gfx_v9_4_3_xcc_constants_init(adev, i); 1010 } 1011 1012 static void 1013 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1014 int xcc_id) 1015 { 1016 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1017 } 1018 1019 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1020 { 1021 /* 1022 * Rlc save restore list is workable since v2_1. 1023 * And it's needed by gfxoff feature. 1024 */ 1025 if (adev->gfx.rlc.is_rlc_v2_1) 1026 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1027 } 1028 1029 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1030 { 1031 uint32_t data; 1032 1033 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1034 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1035 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1036 } 1037 1038 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1039 { 1040 uint32_t rlc_setting; 1041 1042 /* if RLC is not enabled, do nothing */ 1043 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1044 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1045 return false; 1046 1047 return true; 1048 } 1049 1050 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1051 { 1052 uint32_t data; 1053 unsigned i; 1054 1055 data = RLC_SAFE_MODE__CMD_MASK; 1056 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1057 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1058 1059 /* wait for RLC_SAFE_MODE */ 1060 for (i = 0; i < adev->usec_timeout; i++) { 1061 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1062 break; 1063 udelay(1); 1064 } 1065 } 1066 1067 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1068 int xcc_id) 1069 { 1070 uint32_t data; 1071 1072 data = RLC_SAFE_MODE__CMD_MASK; 1073 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1074 } 1075 1076 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1077 { 1078 int xcc_id; 1079 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1080 1081 for (xcc_id = 0; xcc_id < AMDGPU_MAX_RLC_INSTANCES; xcc_id++) { 1082 if (((1 << xcc_id) & adev->gfx.xcc_mask) == 0) 1083 continue; 1084 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1085 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1086 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1087 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1088 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1089 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1090 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1091 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1092 } 1093 } 1094 1095 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1096 { 1097 /* init spm vmid with 0xf */ 1098 if (adev->gfx.rlc.funcs->update_spm_vmid) 1099 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1100 1101 return 0; 1102 } 1103 1104 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1105 int xcc_id) 1106 { 1107 u32 i, j, k; 1108 u32 mask; 1109 1110 mutex_lock(&adev->grbm_idx_mutex); 1111 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1112 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1113 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1114 xcc_id); 1115 for (k = 0; k < adev->usec_timeout; k++) { 1116 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1117 break; 1118 udelay(1); 1119 } 1120 if (k == adev->usec_timeout) { 1121 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1122 0xffffffff, 1123 0xffffffff, xcc_id); 1124 mutex_unlock(&adev->grbm_idx_mutex); 1125 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1126 i, j); 1127 return; 1128 } 1129 } 1130 } 1131 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1132 xcc_id); 1133 mutex_unlock(&adev->grbm_idx_mutex); 1134 1135 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1136 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1137 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1138 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1139 for (k = 0; k < adev->usec_timeout; k++) { 1140 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1141 break; 1142 udelay(1); 1143 } 1144 } 1145 1146 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1147 bool enable, int xcc_id) 1148 { 1149 u32 tmp; 1150 1151 /* These interrupts should be enabled to drive DS clock */ 1152 1153 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1154 1155 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1156 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1157 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1158 1159 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1160 } 1161 1162 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1163 { 1164 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1165 RLC_ENABLE_F32, 0); 1166 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1167 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1168 } 1169 1170 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1171 { 1172 int i, num_xcc; 1173 1174 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1175 for (i = 0; i < num_xcc; i++) 1176 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1177 } 1178 1179 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1180 { 1181 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1182 SOFT_RESET_RLC, 1); 1183 udelay(50); 1184 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1185 SOFT_RESET_RLC, 0); 1186 udelay(50); 1187 } 1188 1189 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1190 { 1191 int i, num_xcc; 1192 1193 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1194 for (i = 0; i < num_xcc; i++) 1195 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1196 } 1197 1198 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1199 { 1200 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1201 RLC_ENABLE_F32, 1); 1202 udelay(50); 1203 1204 /* carrizo do enable cp interrupt after cp inited */ 1205 if (!(adev->flags & AMD_IS_APU)) { 1206 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1207 udelay(50); 1208 } 1209 } 1210 1211 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1212 { 1213 #ifdef AMDGPU_RLC_DEBUG_RETRY 1214 u32 rlc_ucode_ver; 1215 #endif 1216 int i, num_xcc; 1217 1218 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1219 for (i = 0; i < num_xcc; i++) { 1220 gfx_v9_4_3_xcc_rlc_start(adev, i); 1221 #ifdef AMDGPU_RLC_DEBUG_RETRY 1222 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1223 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1224 if (rlc_ucode_ver == 0x108) { 1225 dev_info(adev->dev, 1226 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1227 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1228 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1229 * default is 0x9C4 to create a 100us interval */ 1230 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1231 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1232 * to disable the page fault retry interrupts, default is 1233 * 0x100 (256) */ 1234 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1235 } 1236 #endif 1237 } 1238 } 1239 1240 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1241 int xcc_id) 1242 { 1243 const struct rlc_firmware_header_v2_0 *hdr; 1244 const __le32 *fw_data; 1245 unsigned i, fw_size; 1246 1247 if (!adev->gfx.rlc_fw) 1248 return -EINVAL; 1249 1250 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1251 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1252 1253 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1254 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1255 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1256 1257 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1258 RLCG_UCODE_LOADING_START_ADDRESS); 1259 for (i = 0; i < fw_size; i++) { 1260 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1261 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1262 msleep(1); 1263 } 1264 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1265 } 1266 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1267 1268 return 0; 1269 } 1270 1271 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1272 { 1273 int r; 1274 1275 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1276 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1277 /* legacy rlc firmware loading */ 1278 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1279 if (r) 1280 return r; 1281 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1282 } 1283 1284 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1285 /* disable CG */ 1286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1287 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1288 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1289 1290 return 0; 1291 } 1292 1293 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1294 { 1295 int r, i, num_xcc; 1296 1297 if (amdgpu_sriov_vf(adev)) 1298 return 0; 1299 1300 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1301 for (i = 0; i < num_xcc; i++) { 1302 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1303 if (r) 1304 return r; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1311 unsigned vmid) 1312 { 1313 u32 reg, data; 1314 1315 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1316 if (amdgpu_sriov_is_pp_one_vf(adev)) 1317 data = RREG32_NO_KIQ(reg); 1318 else 1319 data = RREG32(reg); 1320 1321 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1322 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1323 1324 if (amdgpu_sriov_is_pp_one_vf(adev)) 1325 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1326 else 1327 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1328 } 1329 1330 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1331 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1332 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1333 }; 1334 1335 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1336 uint32_t offset, 1337 struct soc15_reg_rlcg *entries, int arr_size) 1338 { 1339 int i, inst; 1340 uint32_t reg; 1341 1342 if (!entries) 1343 return false; 1344 1345 for (i = 0; i < arr_size; i++) { 1346 const struct soc15_reg_rlcg *entry; 1347 1348 entry = &entries[i]; 1349 inst = adev->ip_map.logical_to_dev_inst ? 1350 adev->ip_map.logical_to_dev_inst( 1351 adev, entry->hwip, entry->instance) : 1352 entry->instance; 1353 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1354 entry->reg; 1355 if (offset == reg) 1356 return true; 1357 } 1358 1359 return false; 1360 } 1361 1362 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1363 { 1364 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1365 (void *)rlcg_access_gc_9_4_3, 1366 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1367 } 1368 1369 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1370 bool enable, int xcc_id) 1371 { 1372 if (enable) { 1373 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1374 } else { 1375 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1376 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1377 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1378 } 1379 udelay(50); 1380 } 1381 1382 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1383 int xcc_id) 1384 { 1385 const struct gfx_firmware_header_v1_0 *mec_hdr; 1386 const __le32 *fw_data; 1387 unsigned i; 1388 u32 tmp; 1389 u32 mec_ucode_addr_offset; 1390 u32 mec_ucode_data_offset; 1391 1392 if (!adev->gfx.mec_fw) 1393 return -EINVAL; 1394 1395 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1396 1397 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1398 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1399 1400 fw_data = (const __le32 *) 1401 (adev->gfx.mec_fw->data + 1402 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1403 tmp = 0; 1404 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1405 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1406 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1407 1408 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1409 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1410 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1411 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1412 1413 mec_ucode_addr_offset = 1414 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1415 mec_ucode_data_offset = 1416 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1417 1418 /* MEC1 */ 1419 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1420 for (i = 0; i < mec_hdr->jt_size; i++) 1421 WREG32(mec_ucode_data_offset, 1422 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1423 1424 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1425 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1426 1427 return 0; 1428 } 1429 1430 /* KIQ functions */ 1431 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1432 { 1433 uint32_t tmp; 1434 struct amdgpu_device *adev = ring->adev; 1435 1436 /* tell RLC which is KIQ queue */ 1437 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1438 tmp &= 0xffffff00; 1439 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1440 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1441 tmp |= 0x80; 1442 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1443 } 1444 1445 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1446 { 1447 struct amdgpu_device *adev = ring->adev; 1448 1449 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1450 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1451 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1452 mqd->cp_hqd_queue_priority = 1453 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1454 } 1455 } 1456 } 1457 1458 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1459 { 1460 struct amdgpu_device *adev = ring->adev; 1461 struct v9_mqd *mqd = ring->mqd_ptr; 1462 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1463 uint32_t tmp; 1464 1465 mqd->header = 0xC0310800; 1466 mqd->compute_pipelinestat_enable = 0x00000001; 1467 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1468 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1469 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1470 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1471 mqd->compute_misc_reserved = 0x00000003; 1472 1473 mqd->dynamic_cu_mask_addr_lo = 1474 lower_32_bits(ring->mqd_gpu_addr 1475 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1476 mqd->dynamic_cu_mask_addr_hi = 1477 upper_32_bits(ring->mqd_gpu_addr 1478 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1479 1480 eop_base_addr = ring->eop_gpu_addr >> 8; 1481 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1482 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1483 1484 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1485 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1486 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1487 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1488 1489 mqd->cp_hqd_eop_control = tmp; 1490 1491 /* enable doorbell? */ 1492 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1493 1494 if (ring->use_doorbell) { 1495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1496 DOORBELL_OFFSET, ring->doorbell_index); 1497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1498 DOORBELL_EN, 1); 1499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1500 DOORBELL_SOURCE, 0); 1501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1502 DOORBELL_HIT, 0); 1503 } else { 1504 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1505 DOORBELL_EN, 0); 1506 } 1507 1508 mqd->cp_hqd_pq_doorbell_control = tmp; 1509 1510 /* disable the queue if it's active */ 1511 ring->wptr = 0; 1512 mqd->cp_hqd_dequeue_request = 0; 1513 mqd->cp_hqd_pq_rptr = 0; 1514 mqd->cp_hqd_pq_wptr_lo = 0; 1515 mqd->cp_hqd_pq_wptr_hi = 0; 1516 1517 /* set the pointer to the MQD */ 1518 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1519 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1520 1521 /* set MQD vmid to 0 */ 1522 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1523 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1524 mqd->cp_mqd_control = tmp; 1525 1526 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1527 hqd_gpu_addr = ring->gpu_addr >> 8; 1528 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1529 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1530 1531 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1532 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1533 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1534 (order_base_2(ring->ring_size / 4) - 1)); 1535 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1536 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1537 #ifdef __BIG_ENDIAN 1538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1539 #endif 1540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1544 mqd->cp_hqd_pq_control = tmp; 1545 1546 /* set the wb address whether it's enabled or not */ 1547 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1548 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1549 mqd->cp_hqd_pq_rptr_report_addr_hi = 1550 upper_32_bits(wb_gpu_addr) & 0xffff; 1551 1552 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1553 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1554 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1555 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1556 1557 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1558 ring->wptr = 0; 1559 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1560 1561 /* set the vmid for the queue */ 1562 mqd->cp_hqd_vmid = 0; 1563 1564 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1565 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1566 mqd->cp_hqd_persistent_state = tmp; 1567 1568 /* set MIN_IB_AVAIL_SIZE */ 1569 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1570 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1571 mqd->cp_hqd_ib_control = tmp; 1572 1573 /* set static priority for a queue/ring */ 1574 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1575 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1576 1577 /* map_queues packet doesn't need activate the queue, 1578 * so only kiq need set this field. 1579 */ 1580 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1581 mqd->cp_hqd_active = 1; 1582 1583 return 0; 1584 } 1585 1586 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1587 int xcc_id) 1588 { 1589 struct amdgpu_device *adev = ring->adev; 1590 struct v9_mqd *mqd = ring->mqd_ptr; 1591 int j; 1592 1593 /* disable wptr polling */ 1594 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1595 1596 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1597 mqd->cp_hqd_eop_base_addr_lo); 1598 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1599 mqd->cp_hqd_eop_base_addr_hi); 1600 1601 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1602 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1603 mqd->cp_hqd_eop_control); 1604 1605 /* enable doorbell? */ 1606 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1607 mqd->cp_hqd_pq_doorbell_control); 1608 1609 /* disable the queue if it's active */ 1610 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1611 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1612 for (j = 0; j < adev->usec_timeout; j++) { 1613 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1614 break; 1615 udelay(1); 1616 } 1617 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1618 mqd->cp_hqd_dequeue_request); 1619 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1620 mqd->cp_hqd_pq_rptr); 1621 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1622 mqd->cp_hqd_pq_wptr_lo); 1623 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1624 mqd->cp_hqd_pq_wptr_hi); 1625 } 1626 1627 /* set the pointer to the MQD */ 1628 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1629 mqd->cp_mqd_base_addr_lo); 1630 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1631 mqd->cp_mqd_base_addr_hi); 1632 1633 /* set MQD vmid to 0 */ 1634 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1635 mqd->cp_mqd_control); 1636 1637 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1638 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1639 mqd->cp_hqd_pq_base_lo); 1640 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1641 mqd->cp_hqd_pq_base_hi); 1642 1643 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1644 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1645 mqd->cp_hqd_pq_control); 1646 1647 /* set the wb address whether it's enabled or not */ 1648 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1649 mqd->cp_hqd_pq_rptr_report_addr_lo); 1650 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1651 mqd->cp_hqd_pq_rptr_report_addr_hi); 1652 1653 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1654 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1655 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1656 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1657 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1658 1659 /* enable the doorbell if requested */ 1660 if (ring->use_doorbell) { 1661 WREG32_SOC15( 1662 GC, GET_INST(GC, xcc_id), 1663 regCP_MEC_DOORBELL_RANGE_LOWER, 1664 ((adev->doorbell_index.kiq + 1665 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1666 2) << 2); 1667 WREG32_SOC15( 1668 GC, GET_INST(GC, xcc_id), 1669 regCP_MEC_DOORBELL_RANGE_UPPER, 1670 ((adev->doorbell_index.userqueue_end + 1671 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1672 2) << 2); 1673 } 1674 1675 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1676 mqd->cp_hqd_pq_doorbell_control); 1677 1678 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1679 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1680 mqd->cp_hqd_pq_wptr_lo); 1681 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1682 mqd->cp_hqd_pq_wptr_hi); 1683 1684 /* set the vmid for the queue */ 1685 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1686 1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1688 mqd->cp_hqd_persistent_state); 1689 1690 /* activate the queue */ 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1692 mqd->cp_hqd_active); 1693 1694 if (ring->use_doorbell) 1695 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1696 1697 return 0; 1698 } 1699 1700 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1701 int xcc_id) 1702 { 1703 struct amdgpu_device *adev = ring->adev; 1704 int j; 1705 1706 /* disable the queue if it's active */ 1707 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1708 1709 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1710 1711 for (j = 0; j < adev->usec_timeout; j++) { 1712 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1713 break; 1714 udelay(1); 1715 } 1716 1717 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1718 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1719 1720 /* Manual disable if dequeue request times out */ 1721 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1722 } 1723 1724 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1725 0); 1726 } 1727 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0); 1731 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1736 1737 return 0; 1738 } 1739 1740 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1741 { 1742 struct amdgpu_device *adev = ring->adev; 1743 struct v9_mqd *mqd = ring->mqd_ptr; 1744 struct v9_mqd *tmp_mqd; 1745 1746 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1747 1748 /* GPU could be in bad state during probe, driver trigger the reset 1749 * after load the SMU, in this case , the mqd is not be initialized. 1750 * driver need to re-init the mqd. 1751 * check mqd->cp_hqd_pq_control since this value should not be 0 1752 */ 1753 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1754 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1755 /* for GPU_RESET case , reset MQD to a clean status */ 1756 if (adev->gfx.kiq[xcc_id].mqd_backup) 1757 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1758 1759 /* reset ring buffer */ 1760 ring->wptr = 0; 1761 amdgpu_ring_clear_ring(ring); 1762 mutex_lock(&adev->srbm_mutex); 1763 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1764 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1765 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1766 mutex_unlock(&adev->srbm_mutex); 1767 } else { 1768 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1769 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1770 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1771 mutex_lock(&adev->srbm_mutex); 1772 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1773 amdgpu_ring_clear_ring(ring); 1774 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1775 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1776 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1777 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1778 mutex_unlock(&adev->srbm_mutex); 1779 1780 if (adev->gfx.kiq[xcc_id].mqd_backup) 1781 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1788 { 1789 struct amdgpu_device *adev = ring->adev; 1790 struct v9_mqd *mqd = ring->mqd_ptr; 1791 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1792 struct v9_mqd *tmp_mqd; 1793 1794 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1795 * is not be initialized before 1796 */ 1797 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1798 1799 if (!tmp_mqd->cp_hqd_pq_control || 1800 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1801 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1802 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1803 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1804 mutex_lock(&adev->srbm_mutex); 1805 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1806 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1807 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1808 mutex_unlock(&adev->srbm_mutex); 1809 1810 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1811 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1812 } else { 1813 /* restore MQD to a clean status */ 1814 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1815 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1816 /* reset ring buffer */ 1817 ring->wptr = 0; 1818 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1819 amdgpu_ring_clear_ring(ring); 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1826 { 1827 struct amdgpu_ring *ring; 1828 int j; 1829 1830 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1831 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1832 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1833 mutex_lock(&adev->srbm_mutex); 1834 soc15_grbm_select(adev, ring->me, 1835 ring->pipe, 1836 ring->queue, 0, GET_INST(GC, xcc_id)); 1837 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1838 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1839 mutex_unlock(&adev->srbm_mutex); 1840 } 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1847 { 1848 struct amdgpu_ring *ring; 1849 int r; 1850 1851 ring = &adev->gfx.kiq[xcc_id].ring; 1852 1853 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1854 if (unlikely(r != 0)) 1855 return r; 1856 1857 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1858 if (unlikely(r != 0)) { 1859 amdgpu_bo_unreserve(ring->mqd_obj); 1860 return r; 1861 } 1862 1863 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1864 amdgpu_bo_kunmap(ring->mqd_obj); 1865 ring->mqd_ptr = NULL; 1866 amdgpu_bo_unreserve(ring->mqd_obj); 1867 return 0; 1868 } 1869 1870 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1871 { 1872 struct amdgpu_ring *ring = NULL; 1873 int r = 0, i; 1874 1875 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1876 1877 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1878 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1879 1880 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1881 if (unlikely(r != 0)) 1882 goto done; 1883 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1884 if (!r) { 1885 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1886 amdgpu_bo_kunmap(ring->mqd_obj); 1887 ring->mqd_ptr = NULL; 1888 } 1889 amdgpu_bo_unreserve(ring->mqd_obj); 1890 if (r) 1891 goto done; 1892 } 1893 1894 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1895 done: 1896 return r; 1897 } 1898 1899 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1900 { 1901 struct amdgpu_ring *ring; 1902 int r, j; 1903 1904 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1905 1906 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1907 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1908 1909 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1910 if (r) 1911 return r; 1912 } 1913 1914 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1915 if (r) 1916 return r; 1917 1918 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1919 if (r) 1920 return r; 1921 1922 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1923 ring = &adev->gfx.compute_ring 1924 [j + xcc_id * adev->gfx.num_compute_rings]; 1925 r = amdgpu_ring_test_helper(ring); 1926 if (r) 1927 return r; 1928 } 1929 1930 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1931 1932 return 0; 1933 } 1934 1935 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1936 { 1937 int r = 0, i, num_xcc; 1938 1939 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1940 AMDGPU_XCP_FL_NONE) == 1941 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1942 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1943 amdgpu_user_partt_mode); 1944 1945 if (r) 1946 return r; 1947 1948 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1949 for (i = 0; i < num_xcc; i++) { 1950 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1951 if (r) 1952 return r; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1959 int xcc_id) 1960 { 1961 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1962 } 1963 1964 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1965 { 1966 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1967 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1968 1969 if (amdgpu_sriov_vf(adev)) { 1970 /* must disable polling for SRIOV when hw finished, otherwise 1971 * CPC engine may still keep fetching WB address which is already 1972 * invalid after sw finished and trigger DMAR reading error in 1973 * hypervisor side. 1974 */ 1975 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1976 return; 1977 } 1978 1979 /* Use deinitialize sequence from CAIL when unbinding device 1980 * from driver, otherwise KIQ is hanging when binding back 1981 */ 1982 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1983 mutex_lock(&adev->srbm_mutex); 1984 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1985 adev->gfx.kiq[xcc_id].ring.pipe, 1986 adev->gfx.kiq[xcc_id].ring.queue, 0, 1987 GET_INST(GC, xcc_id)); 1988 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1989 xcc_id); 1990 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1991 mutex_unlock(&adev->srbm_mutex); 1992 } 1993 1994 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 1995 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 1996 } 1997 1998 static int gfx_v9_4_3_hw_init(void *handle) 1999 { 2000 int r; 2001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2002 2003 if (!amdgpu_sriov_vf(adev)) 2004 gfx_v9_4_3_init_golden_registers(adev); 2005 2006 gfx_v9_4_3_constants_init(adev); 2007 2008 r = adev->gfx.rlc.funcs->resume(adev); 2009 if (r) 2010 return r; 2011 2012 r = gfx_v9_4_3_cp_resume(adev); 2013 if (r) 2014 return r; 2015 2016 return r; 2017 } 2018 2019 static int gfx_v9_4_3_hw_fini(void *handle) 2020 { 2021 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2022 int i, num_xcc; 2023 2024 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2025 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2026 2027 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2028 for (i = 0; i < num_xcc; i++) { 2029 gfx_v9_4_3_xcc_fini(adev, i); 2030 } 2031 2032 return 0; 2033 } 2034 2035 static int gfx_v9_4_3_suspend(void *handle) 2036 { 2037 return gfx_v9_4_3_hw_fini(handle); 2038 } 2039 2040 static int gfx_v9_4_3_resume(void *handle) 2041 { 2042 return gfx_v9_4_3_hw_init(handle); 2043 } 2044 2045 static bool gfx_v9_4_3_is_idle(void *handle) 2046 { 2047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2048 int i, num_xcc; 2049 2050 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2051 for (i = 0; i < num_xcc; i++) { 2052 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2053 GRBM_STATUS, GUI_ACTIVE)) 2054 return false; 2055 } 2056 return true; 2057 } 2058 2059 static int gfx_v9_4_3_wait_for_idle(void *handle) 2060 { 2061 unsigned i; 2062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2063 2064 for (i = 0; i < adev->usec_timeout; i++) { 2065 if (gfx_v9_4_3_is_idle(handle)) 2066 return 0; 2067 udelay(1); 2068 } 2069 return -ETIMEDOUT; 2070 } 2071 2072 static int gfx_v9_4_3_soft_reset(void *handle) 2073 { 2074 u32 grbm_soft_reset = 0; 2075 u32 tmp; 2076 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2077 2078 /* GRBM_STATUS */ 2079 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2080 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2081 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2082 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2083 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2084 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2085 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2086 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2087 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2088 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2089 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2090 } 2091 2092 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2093 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2094 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2095 } 2096 2097 /* GRBM_STATUS2 */ 2098 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2099 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2100 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2101 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2102 2103 2104 if (grbm_soft_reset) { 2105 /* stop the rlc */ 2106 adev->gfx.rlc.funcs->stop(adev); 2107 2108 /* Disable MEC parsing/prefetching */ 2109 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2110 2111 if (grbm_soft_reset) { 2112 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2113 tmp |= grbm_soft_reset; 2114 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2115 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2116 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2117 2118 udelay(50); 2119 2120 tmp &= ~grbm_soft_reset; 2121 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2122 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2123 } 2124 2125 /* Wait a little for things to settle down */ 2126 udelay(50); 2127 } 2128 return 0; 2129 } 2130 2131 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2132 uint32_t vmid, 2133 uint32_t gds_base, uint32_t gds_size, 2134 uint32_t gws_base, uint32_t gws_size, 2135 uint32_t oa_base, uint32_t oa_size) 2136 { 2137 struct amdgpu_device *adev = ring->adev; 2138 2139 /* GDS Base */ 2140 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2141 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2142 gds_base); 2143 2144 /* GDS Size */ 2145 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2146 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2147 gds_size); 2148 2149 /* GWS */ 2150 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2151 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2152 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2153 2154 /* OA */ 2155 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2156 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2157 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2158 } 2159 2160 static int gfx_v9_4_3_early_init(void *handle) 2161 { 2162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2163 2164 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2165 AMDGPU_MAX_COMPUTE_RINGS); 2166 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2167 gfx_v9_4_3_set_ring_funcs(adev); 2168 gfx_v9_4_3_set_irq_funcs(adev); 2169 gfx_v9_4_3_set_gds_init(adev); 2170 gfx_v9_4_3_set_rlc_funcs(adev); 2171 2172 /* init rlcg reg access ctrl */ 2173 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2174 2175 return gfx_v9_4_3_init_microcode(adev); 2176 } 2177 2178 static int gfx_v9_4_3_late_init(void *handle) 2179 { 2180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2181 int r; 2182 2183 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2184 if (r) 2185 return r; 2186 2187 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2188 if (r) 2189 return r; 2190 2191 if (adev->gfx.ras && 2192 adev->gfx.ras->enable_watchdog_timer) 2193 adev->gfx.ras->enable_watchdog_timer(adev); 2194 2195 return 0; 2196 } 2197 2198 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2199 bool enable, int xcc_id) 2200 { 2201 uint32_t def, data; 2202 2203 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2204 return; 2205 2206 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2207 regRLC_CGTT_MGCG_OVERRIDE); 2208 2209 if (enable) 2210 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2211 else 2212 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2213 2214 if (def != data) 2215 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2216 regRLC_CGTT_MGCG_OVERRIDE, data); 2217 2218 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2219 2220 if (enable) 2221 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2222 else 2223 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2224 2225 if (def != data) 2226 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2227 } 2228 2229 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2230 bool enable, int xcc_id) 2231 { 2232 uint32_t def, data; 2233 2234 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2235 return; 2236 2237 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2238 regRLC_CGTT_MGCG_OVERRIDE); 2239 2240 if (enable) 2241 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2242 else 2243 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2244 2245 if (def != data) 2246 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2247 regRLC_CGTT_MGCG_OVERRIDE, data); 2248 } 2249 2250 static void 2251 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2252 bool enable, int xcc_id) 2253 { 2254 uint32_t data, def; 2255 2256 /* It is disabled by HW by default */ 2257 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2258 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2259 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2260 2261 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2262 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2263 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2264 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2265 2266 if (def != data) 2267 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2268 2269 /* MGLS is a global flag to control all MGLS in GFX */ 2270 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2271 /* 2 - RLC memory Light sleep */ 2272 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2273 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2274 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2275 if (def != data) 2276 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2277 } 2278 /* 3 - CP memory Light sleep */ 2279 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2280 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2281 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2282 if (def != data) 2283 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2284 } 2285 } 2286 } else { 2287 /* 1 - MGCG_OVERRIDE */ 2288 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2289 2290 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2291 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2292 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2293 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2294 2295 if (def != data) 2296 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2297 2298 /* 2 - disable MGLS in RLC */ 2299 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2300 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2301 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2302 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2303 } 2304 2305 /* 3 - disable MGLS in CP */ 2306 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2307 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2308 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2309 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2310 } 2311 } 2312 2313 } 2314 2315 static void 2316 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2317 bool enable, int xcc_id) 2318 { 2319 uint32_t def, data; 2320 2321 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2322 2323 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2324 /* unset CGCG override */ 2325 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2326 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2327 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2328 else 2329 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2330 /* update CGCG and CGLS override bits */ 2331 if (def != data) 2332 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2333 2334 /* enable cgcg FSM(0x0000363F) */ 2335 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2336 2337 data = (0x36 2338 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2339 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2340 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2341 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2342 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2343 if (def != data) 2344 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2345 2346 /* set IDLE_POLL_COUNT(0x00900100) */ 2347 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2348 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2349 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2350 if (def != data) 2351 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2352 } else { 2353 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2354 /* reset CGCG/CGLS bits */ 2355 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2356 /* disable cgcg and cgls in FSM */ 2357 if (def != data) 2358 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2359 } 2360 2361 } 2362 2363 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2364 bool enable, int xcc_id) 2365 { 2366 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2367 2368 if (enable) { 2369 /* FGCG */ 2370 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2371 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2372 2373 /* CGCG/CGLS should be enabled after MGCG/MGLS 2374 * === MGCG + MGLS === 2375 */ 2376 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2377 xcc_id); 2378 /* === CGCG + CGLS === */ 2379 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2380 xcc_id); 2381 } else { 2382 /* CGCG/CGLS should be disabled before MGCG/MGLS 2383 * === CGCG + CGLS === 2384 */ 2385 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2386 xcc_id); 2387 /* === MGCG + MGLS === */ 2388 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2389 xcc_id); 2390 2391 /* FGCG */ 2392 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2393 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2394 } 2395 2396 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2397 2398 return 0; 2399 } 2400 2401 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2402 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2403 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2404 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2405 .init = gfx_v9_4_3_rlc_init, 2406 .resume = gfx_v9_4_3_rlc_resume, 2407 .stop = gfx_v9_4_3_rlc_stop, 2408 .reset = gfx_v9_4_3_rlc_reset, 2409 .start = gfx_v9_4_3_rlc_start, 2410 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2411 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2412 }; 2413 2414 static int gfx_v9_4_3_set_powergating_state(void *handle, 2415 enum amd_powergating_state state) 2416 { 2417 return 0; 2418 } 2419 2420 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2421 enum amd_clockgating_state state) 2422 { 2423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2424 int i, num_xcc; 2425 2426 if (amdgpu_sriov_vf(adev)) 2427 return 0; 2428 2429 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2430 switch (adev->ip_versions[GC_HWIP][0]) { 2431 case IP_VERSION(9, 4, 3): 2432 for (i = 0; i < num_xcc; i++) 2433 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2434 adev, state == AMD_CG_STATE_GATE, i); 2435 break; 2436 default: 2437 break; 2438 } 2439 return 0; 2440 } 2441 2442 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2443 { 2444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2445 int data; 2446 2447 if (amdgpu_sriov_vf(adev)) 2448 *flags = 0; 2449 2450 /* AMD_CG_SUPPORT_GFX_MGCG */ 2451 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2452 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2453 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2454 2455 /* AMD_CG_SUPPORT_GFX_CGCG */ 2456 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2457 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2458 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2459 2460 /* AMD_CG_SUPPORT_GFX_CGLS */ 2461 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2462 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2463 2464 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2465 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2466 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2467 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2468 2469 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2470 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2471 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2472 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2473 } 2474 2475 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2476 { 2477 struct amdgpu_device *adev = ring->adev; 2478 u32 ref_and_mask, reg_mem_engine; 2479 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2480 2481 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2482 switch (ring->me) { 2483 case 1: 2484 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2485 break; 2486 case 2: 2487 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2488 break; 2489 default: 2490 return; 2491 } 2492 reg_mem_engine = 0; 2493 } else { 2494 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2495 reg_mem_engine = 1; /* pfp */ 2496 } 2497 2498 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2499 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2500 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2501 ref_and_mask, ref_and_mask, 0x20); 2502 } 2503 2504 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2505 struct amdgpu_job *job, 2506 struct amdgpu_ib *ib, 2507 uint32_t flags) 2508 { 2509 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2510 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2511 2512 /* Currently, there is a high possibility to get wave ID mismatch 2513 * between ME and GDS, leading to a hw deadlock, because ME generates 2514 * different wave IDs than the GDS expects. This situation happens 2515 * randomly when at least 5 compute pipes use GDS ordered append. 2516 * The wave IDs generated by ME are also wrong after suspend/resume. 2517 * Those are probably bugs somewhere else in the kernel driver. 2518 * 2519 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2520 * GDS to 0 for this ring (me/pipe). 2521 */ 2522 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2523 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2524 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2525 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2526 } 2527 2528 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2529 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2530 amdgpu_ring_write(ring, 2531 #ifdef __BIG_ENDIAN 2532 (2 << 0) | 2533 #endif 2534 lower_32_bits(ib->gpu_addr)); 2535 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2536 amdgpu_ring_write(ring, control); 2537 } 2538 2539 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2540 u64 seq, unsigned flags) 2541 { 2542 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2543 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2544 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2545 2546 /* RELEASE_MEM - flush caches, send int */ 2547 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2548 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2549 EOP_TC_NC_ACTION_EN) : 2550 (EOP_TCL1_ACTION_EN | 2551 EOP_TC_ACTION_EN | 2552 EOP_TC_WB_ACTION_EN | 2553 EOP_TC_MD_ACTION_EN)) | 2554 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2555 EVENT_INDEX(5))); 2556 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2557 2558 /* 2559 * the address should be Qword aligned if 64bit write, Dword 2560 * aligned if only send 32bit data low (discard data high) 2561 */ 2562 if (write64bit) 2563 BUG_ON(addr & 0x7); 2564 else 2565 BUG_ON(addr & 0x3); 2566 amdgpu_ring_write(ring, lower_32_bits(addr)); 2567 amdgpu_ring_write(ring, upper_32_bits(addr)); 2568 amdgpu_ring_write(ring, lower_32_bits(seq)); 2569 amdgpu_ring_write(ring, upper_32_bits(seq)); 2570 amdgpu_ring_write(ring, 0); 2571 } 2572 2573 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2574 { 2575 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2576 uint32_t seq = ring->fence_drv.sync_seq; 2577 uint64_t addr = ring->fence_drv.gpu_addr; 2578 2579 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2580 lower_32_bits(addr), upper_32_bits(addr), 2581 seq, 0xffffffff, 4); 2582 } 2583 2584 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2585 unsigned vmid, uint64_t pd_addr) 2586 { 2587 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2588 } 2589 2590 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2591 { 2592 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2593 } 2594 2595 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2596 { 2597 u64 wptr; 2598 2599 /* XXX check if swapping is necessary on BE */ 2600 if (ring->use_doorbell) 2601 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2602 else 2603 BUG(); 2604 return wptr; 2605 } 2606 2607 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2608 { 2609 struct amdgpu_device *adev = ring->adev; 2610 2611 /* XXX check if swapping is necessary on BE */ 2612 if (ring->use_doorbell) { 2613 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2614 WDOORBELL64(ring->doorbell_index, ring->wptr); 2615 } else { 2616 BUG(); /* only DOORBELL method supported on gfx9 now */ 2617 } 2618 } 2619 2620 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2621 u64 seq, unsigned int flags) 2622 { 2623 struct amdgpu_device *adev = ring->adev; 2624 2625 /* we only allocate 32bit for each seq wb address */ 2626 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2627 2628 /* write fence seq to the "addr" */ 2629 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2630 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2631 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2632 amdgpu_ring_write(ring, lower_32_bits(addr)); 2633 amdgpu_ring_write(ring, upper_32_bits(addr)); 2634 amdgpu_ring_write(ring, lower_32_bits(seq)); 2635 2636 if (flags & AMDGPU_FENCE_FLAG_INT) { 2637 /* set register to trigger INT */ 2638 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2639 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2640 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2641 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2642 amdgpu_ring_write(ring, 0); 2643 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2644 } 2645 } 2646 2647 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2648 uint32_t reg_val_offs) 2649 { 2650 struct amdgpu_device *adev = ring->adev; 2651 2652 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2653 amdgpu_ring_write(ring, 0 | /* src: register*/ 2654 (5 << 8) | /* dst: memory */ 2655 (1 << 20)); /* write confirm */ 2656 amdgpu_ring_write(ring, reg); 2657 amdgpu_ring_write(ring, 0); 2658 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2659 reg_val_offs * 4)); 2660 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2661 reg_val_offs * 4)); 2662 } 2663 2664 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2665 uint32_t val) 2666 { 2667 uint32_t cmd = 0; 2668 2669 switch (ring->funcs->type) { 2670 case AMDGPU_RING_TYPE_GFX: 2671 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2672 break; 2673 case AMDGPU_RING_TYPE_KIQ: 2674 cmd = (1 << 16); /* no inc addr */ 2675 break; 2676 default: 2677 cmd = WR_CONFIRM; 2678 break; 2679 } 2680 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2681 amdgpu_ring_write(ring, cmd); 2682 amdgpu_ring_write(ring, reg); 2683 amdgpu_ring_write(ring, 0); 2684 amdgpu_ring_write(ring, val); 2685 } 2686 2687 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2688 uint32_t val, uint32_t mask) 2689 { 2690 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2691 } 2692 2693 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2694 uint32_t reg0, uint32_t reg1, 2695 uint32_t ref, uint32_t mask) 2696 { 2697 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2698 ref, mask); 2699 } 2700 2701 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2702 struct amdgpu_device *adev, int me, int pipe, 2703 enum amdgpu_interrupt_state state, int xcc_id) 2704 { 2705 u32 mec_int_cntl, mec_int_cntl_reg; 2706 2707 /* 2708 * amdgpu controls only the first MEC. That's why this function only 2709 * handles the setting of interrupts for this specific MEC. All other 2710 * pipes' interrupts are set by amdkfd. 2711 */ 2712 2713 if (me == 1) { 2714 switch (pipe) { 2715 case 0: 2716 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2717 break; 2718 case 1: 2719 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2720 break; 2721 case 2: 2722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2723 break; 2724 case 3: 2725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2726 break; 2727 default: 2728 DRM_DEBUG("invalid pipe %d\n", pipe); 2729 return; 2730 } 2731 } else { 2732 DRM_DEBUG("invalid me %d\n", me); 2733 return; 2734 } 2735 2736 switch (state) { 2737 case AMDGPU_IRQ_STATE_DISABLE: 2738 mec_int_cntl = RREG32(mec_int_cntl_reg); 2739 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2740 TIME_STAMP_INT_ENABLE, 0); 2741 WREG32(mec_int_cntl_reg, mec_int_cntl); 2742 break; 2743 case AMDGPU_IRQ_STATE_ENABLE: 2744 mec_int_cntl = RREG32(mec_int_cntl_reg); 2745 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2746 TIME_STAMP_INT_ENABLE, 1); 2747 WREG32(mec_int_cntl_reg, mec_int_cntl); 2748 break; 2749 default: 2750 break; 2751 } 2752 } 2753 2754 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2755 struct amdgpu_irq_src *source, 2756 unsigned type, 2757 enum amdgpu_interrupt_state state) 2758 { 2759 int i, num_xcc; 2760 2761 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2762 switch (state) { 2763 case AMDGPU_IRQ_STATE_DISABLE: 2764 case AMDGPU_IRQ_STATE_ENABLE: 2765 for (i = 0; i < num_xcc; i++) 2766 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2767 PRIV_REG_INT_ENABLE, 2768 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2769 break; 2770 default: 2771 break; 2772 } 2773 2774 return 0; 2775 } 2776 2777 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2778 struct amdgpu_irq_src *source, 2779 unsigned type, 2780 enum amdgpu_interrupt_state state) 2781 { 2782 int i, num_xcc; 2783 2784 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2785 switch (state) { 2786 case AMDGPU_IRQ_STATE_DISABLE: 2787 case AMDGPU_IRQ_STATE_ENABLE: 2788 for (i = 0; i < num_xcc; i++) 2789 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2790 PRIV_INSTR_INT_ENABLE, 2791 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2792 break; 2793 default: 2794 break; 2795 } 2796 2797 return 0; 2798 } 2799 2800 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2801 struct amdgpu_irq_src *src, 2802 unsigned type, 2803 enum amdgpu_interrupt_state state) 2804 { 2805 int i, num_xcc; 2806 2807 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2808 for (i = 0; i < num_xcc; i++) { 2809 switch (type) { 2810 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2811 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2812 adev, 1, 0, state, i); 2813 break; 2814 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2815 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2816 adev, 1, 1, state, i); 2817 break; 2818 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2819 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2820 adev, 1, 2, state, i); 2821 break; 2822 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2823 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2824 adev, 1, 3, state, i); 2825 break; 2826 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2827 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2828 adev, 2, 0, state, i); 2829 break; 2830 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2831 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2832 adev, 2, 1, state, i); 2833 break; 2834 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2835 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2836 adev, 2, 2, state, i); 2837 break; 2838 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2839 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2840 adev, 2, 3, state, i); 2841 break; 2842 default: 2843 break; 2844 } 2845 } 2846 2847 return 0; 2848 } 2849 2850 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2851 struct amdgpu_irq_src *source, 2852 struct amdgpu_iv_entry *entry) 2853 { 2854 int i, xcc_id; 2855 u8 me_id, pipe_id, queue_id; 2856 struct amdgpu_ring *ring; 2857 2858 DRM_DEBUG("IH: CP EOP\n"); 2859 me_id = (entry->ring_id & 0x0c) >> 2; 2860 pipe_id = (entry->ring_id & 0x03) >> 0; 2861 queue_id = (entry->ring_id & 0x70) >> 4; 2862 2863 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2864 2865 if (xcc_id == -EINVAL) 2866 return -EINVAL; 2867 2868 switch (me_id) { 2869 case 0: 2870 case 1: 2871 case 2: 2872 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2873 ring = &adev->gfx.compute_ring 2874 [i + 2875 xcc_id * adev->gfx.num_compute_rings]; 2876 /* Per-queue interrupt is supported for MEC starting from VI. 2877 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2878 */ 2879 2880 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2881 amdgpu_fence_process(ring); 2882 } 2883 break; 2884 } 2885 return 0; 2886 } 2887 2888 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2889 struct amdgpu_iv_entry *entry) 2890 { 2891 u8 me_id, pipe_id, queue_id; 2892 struct amdgpu_ring *ring; 2893 int i, xcc_id; 2894 2895 me_id = (entry->ring_id & 0x0c) >> 2; 2896 pipe_id = (entry->ring_id & 0x03) >> 0; 2897 queue_id = (entry->ring_id & 0x70) >> 4; 2898 2899 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2900 2901 if (xcc_id == -EINVAL) 2902 return; 2903 2904 switch (me_id) { 2905 case 0: 2906 case 1: 2907 case 2: 2908 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2909 ring = &adev->gfx.compute_ring 2910 [i + 2911 xcc_id * adev->gfx.num_compute_rings]; 2912 if (ring->me == me_id && ring->pipe == pipe_id && 2913 ring->queue == queue_id) 2914 drm_sched_fault(&ring->sched); 2915 } 2916 break; 2917 } 2918 } 2919 2920 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2921 struct amdgpu_irq_src *source, 2922 struct amdgpu_iv_entry *entry) 2923 { 2924 DRM_ERROR("Illegal register access in command stream\n"); 2925 gfx_v9_4_3_fault(adev, entry); 2926 return 0; 2927 } 2928 2929 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2930 struct amdgpu_irq_src *source, 2931 struct amdgpu_iv_entry *entry) 2932 { 2933 DRM_ERROR("Illegal instruction in command stream\n"); 2934 gfx_v9_4_3_fault(adev, entry); 2935 return 0; 2936 } 2937 2938 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2939 { 2940 const unsigned int cp_coher_cntl = 2941 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2942 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2943 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2944 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2945 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2946 2947 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2948 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2949 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2950 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2951 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2952 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2953 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2954 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2955 } 2956 2957 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2958 uint32_t pipe, bool enable) 2959 { 2960 struct amdgpu_device *adev = ring->adev; 2961 uint32_t val; 2962 uint32_t wcl_cs_reg; 2963 2964 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2965 val = enable ? 0x1 : 0x7f; 2966 2967 switch (pipe) { 2968 case 0: 2969 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2970 break; 2971 case 1: 2972 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2973 break; 2974 case 2: 2975 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2976 break; 2977 case 3: 2978 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2979 break; 2980 default: 2981 DRM_DEBUG("invalid pipe %d\n", pipe); 2982 return; 2983 } 2984 2985 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2986 2987 } 2988 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2989 { 2990 struct amdgpu_device *adev = ring->adev; 2991 uint32_t val; 2992 int i; 2993 2994 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2995 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2996 * around 25% of gpu resources. 2997 */ 2998 val = enable ? 0x1f : 0x07ffffff; 2999 amdgpu_ring_emit_wreg(ring, 3000 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3001 val); 3002 3003 /* Restrict waves for normal/low priority compute queues as well 3004 * to get best QoS for high priority compute jobs. 3005 * 3006 * amdgpu controls only 1st ME(0-3 CS pipes). 3007 */ 3008 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3009 if (i != ring->pipe) 3010 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3011 3012 } 3013 } 3014 3015 enum amdgpu_gfx_cp_ras_mem_id { 3016 AMDGPU_GFX_CP_MEM1 = 1, 3017 AMDGPU_GFX_CP_MEM2, 3018 AMDGPU_GFX_CP_MEM3, 3019 AMDGPU_GFX_CP_MEM4, 3020 AMDGPU_GFX_CP_MEM5, 3021 }; 3022 3023 enum amdgpu_gfx_gcea_ras_mem_id { 3024 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3025 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3026 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3027 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3028 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3029 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3030 AMDGPU_GFX_GCEA_MAM_DMEM0, 3031 AMDGPU_GFX_GCEA_MAM_DMEM1, 3032 AMDGPU_GFX_GCEA_MAM_DMEM2, 3033 AMDGPU_GFX_GCEA_MAM_DMEM3, 3034 AMDGPU_GFX_GCEA_MAM_AMEM0, 3035 AMDGPU_GFX_GCEA_MAM_AMEM1, 3036 AMDGPU_GFX_GCEA_MAM_AMEM2, 3037 AMDGPU_GFX_GCEA_MAM_AMEM3, 3038 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3039 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3040 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3041 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3042 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3043 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3044 }; 3045 3046 enum amdgpu_gfx_gc_cane_ras_mem_id { 3047 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3048 }; 3049 3050 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3051 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3052 }; 3053 3054 enum amdgpu_gfx_gds_ras_mem_id { 3055 AMDGPU_GFX_GDS_MEM0 = 0, 3056 }; 3057 3058 enum amdgpu_gfx_lds_ras_mem_id { 3059 AMDGPU_GFX_LDS_BANK0 = 0, 3060 AMDGPU_GFX_LDS_BANK1, 3061 AMDGPU_GFX_LDS_BANK2, 3062 AMDGPU_GFX_LDS_BANK3, 3063 AMDGPU_GFX_LDS_BANK4, 3064 AMDGPU_GFX_LDS_BANK5, 3065 AMDGPU_GFX_LDS_BANK6, 3066 AMDGPU_GFX_LDS_BANK7, 3067 AMDGPU_GFX_LDS_BANK8, 3068 AMDGPU_GFX_LDS_BANK9, 3069 AMDGPU_GFX_LDS_BANK10, 3070 AMDGPU_GFX_LDS_BANK11, 3071 AMDGPU_GFX_LDS_BANK12, 3072 AMDGPU_GFX_LDS_BANK13, 3073 AMDGPU_GFX_LDS_BANK14, 3074 AMDGPU_GFX_LDS_BANK15, 3075 AMDGPU_GFX_LDS_BANK16, 3076 AMDGPU_GFX_LDS_BANK17, 3077 AMDGPU_GFX_LDS_BANK18, 3078 AMDGPU_GFX_LDS_BANK19, 3079 AMDGPU_GFX_LDS_BANK20, 3080 AMDGPU_GFX_LDS_BANK21, 3081 AMDGPU_GFX_LDS_BANK22, 3082 AMDGPU_GFX_LDS_BANK23, 3083 AMDGPU_GFX_LDS_BANK24, 3084 AMDGPU_GFX_LDS_BANK25, 3085 AMDGPU_GFX_LDS_BANK26, 3086 AMDGPU_GFX_LDS_BANK27, 3087 AMDGPU_GFX_LDS_BANK28, 3088 AMDGPU_GFX_LDS_BANK29, 3089 AMDGPU_GFX_LDS_BANK30, 3090 AMDGPU_GFX_LDS_BANK31, 3091 AMDGPU_GFX_LDS_SP_BUFFER_A, 3092 AMDGPU_GFX_LDS_SP_BUFFER_B, 3093 }; 3094 3095 enum amdgpu_gfx_rlc_ras_mem_id { 3096 AMDGPU_GFX_RLC_GPMF32 = 1, 3097 AMDGPU_GFX_RLC_RLCVF32, 3098 AMDGPU_GFX_RLC_SCRATCH, 3099 AMDGPU_GFX_RLC_SRM_ARAM, 3100 AMDGPU_GFX_RLC_SRM_DRAM, 3101 AMDGPU_GFX_RLC_TCTAG, 3102 AMDGPU_GFX_RLC_SPM_SE, 3103 AMDGPU_GFX_RLC_SPM_GRBMT, 3104 }; 3105 3106 enum amdgpu_gfx_sp_ras_mem_id { 3107 AMDGPU_GFX_SP_SIMDID0 = 0, 3108 }; 3109 3110 enum amdgpu_gfx_spi_ras_mem_id { 3111 AMDGPU_GFX_SPI_MEM0 = 0, 3112 AMDGPU_GFX_SPI_MEM1, 3113 AMDGPU_GFX_SPI_MEM2, 3114 AMDGPU_GFX_SPI_MEM3, 3115 }; 3116 3117 enum amdgpu_gfx_sqc_ras_mem_id { 3118 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3119 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3120 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3121 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3122 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3123 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3124 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3125 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3126 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3127 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3128 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3129 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3130 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3131 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3132 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3133 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3134 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3135 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3136 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3137 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3138 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3139 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3140 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3141 }; 3142 3143 enum amdgpu_gfx_sq_ras_mem_id { 3144 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3145 AMDGPU_GFX_SQ_SGPR_MEM1, 3146 AMDGPU_GFX_SQ_SGPR_MEM2, 3147 AMDGPU_GFX_SQ_SGPR_MEM3, 3148 }; 3149 3150 enum amdgpu_gfx_ta_ras_mem_id { 3151 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3152 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3153 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3154 AMDGPU_GFX_TA_FSX_LFIFO, 3155 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3156 }; 3157 3158 enum amdgpu_gfx_tcc_ras_mem_id { 3159 AMDGPU_GFX_TCC_MEM1 = 1, 3160 }; 3161 3162 enum amdgpu_gfx_tca_ras_mem_id { 3163 AMDGPU_GFX_TCA_MEM1 = 1, 3164 }; 3165 3166 enum amdgpu_gfx_tci_ras_mem_id { 3167 AMDGPU_GFX_TCIW_MEM = 1, 3168 }; 3169 3170 enum amdgpu_gfx_tcp_ras_mem_id { 3171 AMDGPU_GFX_TCP_LFIFO0 = 1, 3172 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3173 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3174 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3175 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3176 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3177 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3178 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3179 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3180 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3181 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3182 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3183 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3184 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3185 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3186 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3187 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3188 AMDGPU_GFX_TCP_VM_FIFO, 3189 AMDGPU_GFX_TCP_DB_TAGRAM0, 3190 AMDGPU_GFX_TCP_DB_TAGRAM1, 3191 AMDGPU_GFX_TCP_DB_TAGRAM2, 3192 AMDGPU_GFX_TCP_DB_TAGRAM3, 3193 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3194 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3195 AMDGPU_GFX_TCP_CMD_FIFO, 3196 }; 3197 3198 enum amdgpu_gfx_td_ras_mem_id { 3199 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3200 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3201 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3202 }; 3203 3204 enum amdgpu_gfx_tcx_ras_mem_id { 3205 AMDGPU_GFX_TCX_FIFOD0 = 0, 3206 AMDGPU_GFX_TCX_FIFOD1, 3207 AMDGPU_GFX_TCX_FIFOD2, 3208 AMDGPU_GFX_TCX_FIFOD3, 3209 AMDGPU_GFX_TCX_FIFOD4, 3210 AMDGPU_GFX_TCX_FIFOD5, 3211 AMDGPU_GFX_TCX_FIFOD6, 3212 AMDGPU_GFX_TCX_FIFOD7, 3213 AMDGPU_GFX_TCX_FIFOB0, 3214 AMDGPU_GFX_TCX_FIFOB1, 3215 AMDGPU_GFX_TCX_FIFOB2, 3216 AMDGPU_GFX_TCX_FIFOB3, 3217 AMDGPU_GFX_TCX_FIFOB4, 3218 AMDGPU_GFX_TCX_FIFOB5, 3219 AMDGPU_GFX_TCX_FIFOB6, 3220 AMDGPU_GFX_TCX_FIFOB7, 3221 AMDGPU_GFX_TCX_FIFOA0, 3222 AMDGPU_GFX_TCX_FIFOA1, 3223 AMDGPU_GFX_TCX_FIFOA2, 3224 AMDGPU_GFX_TCX_FIFOA3, 3225 AMDGPU_GFX_TCX_FIFOA4, 3226 AMDGPU_GFX_TCX_FIFOA5, 3227 AMDGPU_GFX_TCX_FIFOA6, 3228 AMDGPU_GFX_TCX_FIFOA7, 3229 AMDGPU_GFX_TCX_CFIFO0, 3230 AMDGPU_GFX_TCX_CFIFO1, 3231 AMDGPU_GFX_TCX_CFIFO2, 3232 AMDGPU_GFX_TCX_CFIFO3, 3233 AMDGPU_GFX_TCX_CFIFO4, 3234 AMDGPU_GFX_TCX_CFIFO5, 3235 AMDGPU_GFX_TCX_CFIFO6, 3236 AMDGPU_GFX_TCX_CFIFO7, 3237 AMDGPU_GFX_TCX_FIFO_ACKB0, 3238 AMDGPU_GFX_TCX_FIFO_ACKB1, 3239 AMDGPU_GFX_TCX_FIFO_ACKB2, 3240 AMDGPU_GFX_TCX_FIFO_ACKB3, 3241 AMDGPU_GFX_TCX_FIFO_ACKB4, 3242 AMDGPU_GFX_TCX_FIFO_ACKB5, 3243 AMDGPU_GFX_TCX_FIFO_ACKB6, 3244 AMDGPU_GFX_TCX_FIFO_ACKB7, 3245 AMDGPU_GFX_TCX_FIFO_ACKD0, 3246 AMDGPU_GFX_TCX_FIFO_ACKD1, 3247 AMDGPU_GFX_TCX_FIFO_ACKD2, 3248 AMDGPU_GFX_TCX_FIFO_ACKD3, 3249 AMDGPU_GFX_TCX_FIFO_ACKD4, 3250 AMDGPU_GFX_TCX_FIFO_ACKD5, 3251 AMDGPU_GFX_TCX_FIFO_ACKD6, 3252 AMDGPU_GFX_TCX_FIFO_ACKD7, 3253 AMDGPU_GFX_TCX_DST_FIFOA0, 3254 AMDGPU_GFX_TCX_DST_FIFOA1, 3255 AMDGPU_GFX_TCX_DST_FIFOA2, 3256 AMDGPU_GFX_TCX_DST_FIFOA3, 3257 AMDGPU_GFX_TCX_DST_FIFOA4, 3258 AMDGPU_GFX_TCX_DST_FIFOA5, 3259 AMDGPU_GFX_TCX_DST_FIFOA6, 3260 AMDGPU_GFX_TCX_DST_FIFOA7, 3261 AMDGPU_GFX_TCX_DST_FIFOB0, 3262 AMDGPU_GFX_TCX_DST_FIFOB1, 3263 AMDGPU_GFX_TCX_DST_FIFOB2, 3264 AMDGPU_GFX_TCX_DST_FIFOB3, 3265 AMDGPU_GFX_TCX_DST_FIFOB4, 3266 AMDGPU_GFX_TCX_DST_FIFOB5, 3267 AMDGPU_GFX_TCX_DST_FIFOB6, 3268 AMDGPU_GFX_TCX_DST_FIFOB7, 3269 AMDGPU_GFX_TCX_DST_FIFOD0, 3270 AMDGPU_GFX_TCX_DST_FIFOD1, 3271 AMDGPU_GFX_TCX_DST_FIFOD2, 3272 AMDGPU_GFX_TCX_DST_FIFOD3, 3273 AMDGPU_GFX_TCX_DST_FIFOD4, 3274 AMDGPU_GFX_TCX_DST_FIFOD5, 3275 AMDGPU_GFX_TCX_DST_FIFOD6, 3276 AMDGPU_GFX_TCX_DST_FIFOD7, 3277 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3278 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3279 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3280 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3285 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3286 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3287 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3288 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3293 }; 3294 3295 enum amdgpu_gfx_atc_l2_ras_mem_id { 3296 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3297 }; 3298 3299 enum amdgpu_gfx_utcl2_ras_mem_id { 3300 AMDGPU_GFX_UTCL2_MEM0 = 0, 3301 }; 3302 3303 enum amdgpu_gfx_vml2_ras_mem_id { 3304 AMDGPU_GFX_VML2_MEM0 = 0, 3305 }; 3306 3307 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3308 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3309 }; 3310 3311 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3312 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3313 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3314 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3315 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3316 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3317 }; 3318 3319 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3320 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3321 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3322 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3323 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3324 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3325 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3326 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3327 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3328 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3329 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3330 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3331 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3332 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3333 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3334 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3335 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3336 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3337 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3338 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3339 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3340 }; 3341 3342 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3343 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3344 }; 3345 3346 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3347 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3348 }; 3349 3350 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3351 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3352 }; 3353 3354 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3355 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3356 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3357 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3358 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3359 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3360 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3361 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3362 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3363 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3364 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3365 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3366 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3367 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3368 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3369 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3370 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3371 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3372 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3373 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3374 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3375 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3376 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3377 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3378 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3379 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3380 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3381 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3382 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3383 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3384 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3385 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3386 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3387 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3388 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3389 }; 3390 3391 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3392 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3393 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3394 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3395 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3396 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3397 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3398 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3399 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3400 }; 3401 3402 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3403 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3404 }; 3405 3406 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3407 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3408 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3409 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3410 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3411 }; 3412 3413 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3414 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3415 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3416 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3417 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3418 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3419 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3420 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3421 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3422 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3423 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3424 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3425 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3426 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3427 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3428 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3429 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3430 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3431 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3432 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3433 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3434 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3435 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3436 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3437 }; 3438 3439 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3440 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3441 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3442 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3443 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3444 }; 3445 3446 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3447 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3448 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3449 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3450 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3451 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3452 }; 3453 3454 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3455 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3456 }; 3457 3458 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3459 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3460 }; 3461 3462 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3463 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3464 }; 3465 3466 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3467 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3468 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3469 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3470 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3471 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3472 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3473 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3474 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3475 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3476 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3477 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3478 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3479 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3480 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3481 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3482 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3483 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3484 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3485 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3486 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3487 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3488 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3489 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3490 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3491 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3492 }; 3493 3494 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3495 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3496 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3497 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3498 }; 3499 3500 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3501 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3502 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3503 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3504 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3505 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3506 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3507 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3508 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3509 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3510 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3511 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3512 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3513 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3514 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3515 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3516 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3517 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3518 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3519 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3520 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3521 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3522 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3523 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3524 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3525 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3526 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3527 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3528 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3529 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3530 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3531 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3532 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3533 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3534 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3535 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3536 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3537 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3538 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3539 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3540 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3541 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3542 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3543 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3544 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3545 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3546 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3547 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3548 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3549 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3550 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3551 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3552 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3553 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3554 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3555 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3556 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3557 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3558 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3559 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3560 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3561 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3562 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3563 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3564 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3565 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3566 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3567 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3568 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3569 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3570 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3571 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3572 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3573 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3574 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3575 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3576 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3589 }; 3590 3591 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3592 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3593 }; 3594 3595 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3596 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3597 }; 3598 3599 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3600 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3601 }; 3602 3603 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3604 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3605 }; 3606 3607 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3608 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3609 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3610 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3630 }; 3631 3632 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3633 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3634 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3635 AMDGPU_GFX_RLC_MEM, 1}, 3636 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3637 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3638 AMDGPU_GFX_CP_MEM, 1}, 3639 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3640 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3641 AMDGPU_GFX_CP_MEM, 1}, 3642 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3643 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3644 AMDGPU_GFX_CP_MEM, 1}, 3645 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3646 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3647 AMDGPU_GFX_GDS_MEM, 1}, 3648 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3649 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3650 AMDGPU_GFX_GC_CANE_MEM, 1}, 3651 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3652 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3653 AMDGPU_GFX_SPI_MEM, 8}, 3654 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3655 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3656 AMDGPU_GFX_SP_MEM, 1}, 3657 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3658 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3659 AMDGPU_GFX_SP_MEM, 1}, 3660 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3661 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3662 AMDGPU_GFX_SQ_MEM, 8}, 3663 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3664 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3665 AMDGPU_GFX_SQC_MEM, 8}, 3666 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3667 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3668 AMDGPU_GFX_TCX_MEM, 1}, 3669 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3670 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3671 AMDGPU_GFX_TCC_MEM, 1}, 3672 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3673 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3674 AMDGPU_GFX_TA_MEM, 8}, 3675 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3676 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3677 AMDGPU_GFX_TCI_MEM, 1}, 3678 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3679 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3680 AMDGPU_GFX_TCP_MEM, 8}, 3681 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3682 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3683 AMDGPU_GFX_TD_MEM, 8}, 3684 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3685 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3686 AMDGPU_GFX_GCEA_MEM, 1}, 3687 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3688 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3689 AMDGPU_GFX_LDS_MEM, 1}, 3690 }; 3691 3692 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3693 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3694 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3695 AMDGPU_GFX_RLC_MEM, 1}, 3696 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3697 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3698 AMDGPU_GFX_CP_MEM, 1}, 3699 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3700 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3701 AMDGPU_GFX_CP_MEM, 1}, 3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3703 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3704 AMDGPU_GFX_CP_MEM, 1}, 3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3706 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3707 AMDGPU_GFX_GDS_MEM, 1}, 3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3709 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3710 AMDGPU_GFX_GC_CANE_MEM, 1}, 3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3712 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3713 AMDGPU_GFX_SPI_MEM, 8}, 3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3715 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3716 AMDGPU_GFX_SP_MEM, 1}, 3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3718 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3719 AMDGPU_GFX_SP_MEM, 1}, 3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3721 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3722 AMDGPU_GFX_SQ_MEM, 8}, 3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3724 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3725 AMDGPU_GFX_SQC_MEM, 8}, 3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3727 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3728 AMDGPU_GFX_TCX_MEM, 1}, 3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3730 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3731 AMDGPU_GFX_TCC_MEM, 1}, 3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3733 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3734 AMDGPU_GFX_TA_MEM, 8}, 3735 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3736 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3737 AMDGPU_GFX_TCI_MEM, 1}, 3738 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3739 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3740 AMDGPU_GFX_TCP_MEM, 8}, 3741 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3742 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3743 AMDGPU_GFX_TD_MEM, 8}, 3744 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3745 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3746 AMDGPU_GFX_TCA_MEM, 1}, 3747 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3748 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3749 AMDGPU_GFX_GCEA_MEM, 1}, 3750 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3751 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3752 AMDGPU_GFX_LDS_MEM, 1}, 3753 }; 3754 3755 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3756 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3757 }; 3758 3759 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3760 void *ras_error_status, int xcc_id) 3761 { 3762 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3763 unsigned long ce_count = 0, ue_count = 0; 3764 uint32_t i, j, k; 3765 3766 mutex_lock(&adev->grbm_idx_mutex); 3767 3768 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3769 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3770 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3771 /* no need to select if instance number is 1 */ 3772 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3773 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3774 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3775 3776 amdgpu_ras_inst_query_ras_error_count(adev, 3777 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3778 1, 3779 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3780 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3781 GET_INST(GC, xcc_id), 3782 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3783 &ce_count); 3784 3785 amdgpu_ras_inst_query_ras_error_count(adev, 3786 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3787 1, 3788 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3789 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3790 GET_INST(GC, xcc_id), 3791 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3792 &ue_count); 3793 } 3794 } 3795 } 3796 3797 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3798 xcc_id); 3799 mutex_unlock(&adev->grbm_idx_mutex); 3800 3801 /* the caller should make sure initialize value of 3802 * err_data->ue_count and err_data->ce_count 3803 */ 3804 err_data->ce_count += ce_count; 3805 err_data->ue_count += ue_count; 3806 } 3807 3808 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3809 void *ras_error_status, int xcc_id) 3810 { 3811 uint32_t i, j, k; 3812 3813 mutex_lock(&adev->grbm_idx_mutex); 3814 3815 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3816 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3817 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3818 /* no need to select if instance number is 1 */ 3819 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3820 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3821 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3822 3823 amdgpu_ras_inst_reset_ras_error_count(adev, 3824 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3825 1, 3826 GET_INST(GC, xcc_id)); 3827 3828 amdgpu_ras_inst_reset_ras_error_count(adev, 3829 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3830 1, 3831 GET_INST(GC, xcc_id)); 3832 } 3833 } 3834 } 3835 3836 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3837 xcc_id); 3838 mutex_unlock(&adev->grbm_idx_mutex); 3839 } 3840 3841 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3842 int xcc_id) 3843 { 3844 uint32_t i, j; 3845 uint32_t reg_value; 3846 3847 mutex_lock(&adev->grbm_idx_mutex); 3848 3849 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3850 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3851 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3852 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3853 regGCEA_ERR_STATUS); 3854 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3855 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3856 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3857 dev_warn(adev->dev, 3858 "GCEA err detected at instance: %d, status: 0x%x!\n", 3859 j, reg_value); 3860 } 3861 /* clear after read */ 3862 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3863 CLEAR_ERROR_STATUS, 0x1); 3864 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3865 reg_value); 3866 } 3867 } 3868 3869 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3870 xcc_id); 3871 mutex_unlock(&adev->grbm_idx_mutex); 3872 } 3873 3874 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3875 int xcc_id) 3876 { 3877 uint32_t data; 3878 3879 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3880 if (data) { 3881 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3882 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3883 } 3884 3885 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3886 if (data) { 3887 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3888 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3889 } 3890 3891 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3892 regVML2_WALKER_MEM_ECC_STATUS); 3893 if (data) { 3894 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3895 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3896 0x3); 3897 } 3898 } 3899 3900 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3901 uint32_t status, int xcc_id) 3902 { 3903 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3904 uint32_t i, simd, wave; 3905 uint32_t wave_status; 3906 uint32_t wave_pc_lo, wave_pc_hi; 3907 uint32_t wave_exec_lo, wave_exec_hi; 3908 uint32_t wave_inst_dw0, wave_inst_dw1; 3909 uint32_t wave_ib_sts; 3910 3911 for (i = 0; i < 32; i++) { 3912 if (!((i << 1) & status)) 3913 continue; 3914 3915 simd = i / cu_info->max_waves_per_simd; 3916 wave = i % cu_info->max_waves_per_simd; 3917 3918 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3919 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3920 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3921 wave_exec_lo = 3922 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3923 wave_exec_hi = 3924 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3925 wave_inst_dw0 = 3926 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3927 wave_inst_dw1 = 3928 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3929 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3930 3931 dev_info( 3932 adev->dev, 3933 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3934 simd, wave, wave_status, 3935 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3936 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3937 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3938 wave_ib_sts); 3939 } 3940 } 3941 3942 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3943 int xcc_id) 3944 { 3945 uint32_t se_idx, sh_idx, cu_idx; 3946 uint32_t status; 3947 3948 mutex_lock(&adev->grbm_idx_mutex); 3949 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3950 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3951 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3952 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3953 cu_idx, xcc_id); 3954 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3955 regSQ_TIMEOUT_STATUS); 3956 if (status != 0) { 3957 dev_info( 3958 adev->dev, 3959 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3960 se_idx, sh_idx, cu_idx); 3961 gfx_v9_4_3_log_cu_timeout_status( 3962 adev, status, xcc_id); 3963 } 3964 /* clear old status */ 3965 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3966 regSQ_TIMEOUT_STATUS, 0); 3967 } 3968 } 3969 } 3970 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3971 xcc_id); 3972 mutex_unlock(&adev->grbm_idx_mutex); 3973 } 3974 3975 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3976 void *ras_error_status, int xcc_id) 3977 { 3978 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3979 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3980 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3981 } 3982 3983 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3984 int xcc_id) 3985 { 3986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3987 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3988 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3989 } 3990 3991 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3992 int xcc_id) 3993 { 3994 uint32_t i, j; 3995 uint32_t value; 3996 3997 mutex_lock(&adev->grbm_idx_mutex); 3998 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3999 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 4000 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 4001 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 4002 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 4003 CLEAR_ERROR_STATUS, 0x1); 4004 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 4005 } 4006 } 4007 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4008 xcc_id); 4009 mutex_unlock(&adev->grbm_idx_mutex); 4010 } 4011 4012 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 4013 int xcc_id) 4014 { 4015 uint32_t se_idx, sh_idx, cu_idx; 4016 4017 mutex_lock(&adev->grbm_idx_mutex); 4018 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 4019 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 4020 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 4021 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 4022 cu_idx, xcc_id); 4023 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4024 regSQ_TIMEOUT_STATUS, 0); 4025 } 4026 } 4027 } 4028 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4029 xcc_id); 4030 mutex_unlock(&adev->grbm_idx_mutex); 4031 } 4032 4033 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4034 void *ras_error_status, int xcc_id) 4035 { 4036 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4037 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4038 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4039 } 4040 4041 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4042 void *ras_error_status, int xcc_id) 4043 { 4044 uint32_t i; 4045 uint32_t data; 4046 4047 data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4048 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4049 4050 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4051 (amdgpu_watchdog_timer.period < 1 || 4052 amdgpu_watchdog_timer.period > 0x23)) { 4053 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4054 amdgpu_watchdog_timer.period = 0x23; 4055 } 4056 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4057 amdgpu_watchdog_timer.period); 4058 4059 mutex_lock(&adev->grbm_idx_mutex); 4060 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4061 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4062 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4063 } 4064 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4065 xcc_id); 4066 mutex_unlock(&adev->grbm_idx_mutex); 4067 } 4068 4069 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4070 void *ras_error_status) 4071 { 4072 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4073 gfx_v9_4_3_inst_query_ras_err_count); 4074 } 4075 4076 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4077 { 4078 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4079 } 4080 4081 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4082 { 4083 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4084 } 4085 4086 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4087 { 4088 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4089 } 4090 4091 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4092 { 4093 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4094 } 4095 4096 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4097 .name = "gfx_v9_4_3", 4098 .early_init = gfx_v9_4_3_early_init, 4099 .late_init = gfx_v9_4_3_late_init, 4100 .sw_init = gfx_v9_4_3_sw_init, 4101 .sw_fini = gfx_v9_4_3_sw_fini, 4102 .hw_init = gfx_v9_4_3_hw_init, 4103 .hw_fini = gfx_v9_4_3_hw_fini, 4104 .suspend = gfx_v9_4_3_suspend, 4105 .resume = gfx_v9_4_3_resume, 4106 .is_idle = gfx_v9_4_3_is_idle, 4107 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4108 .soft_reset = gfx_v9_4_3_soft_reset, 4109 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4110 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4111 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4112 }; 4113 4114 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4115 .type = AMDGPU_RING_TYPE_COMPUTE, 4116 .align_mask = 0xff, 4117 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4118 .support_64bit_ptrs = true, 4119 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4120 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4121 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4122 .emit_frame_size = 4123 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4124 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4125 5 + /* hdp invalidate */ 4126 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4127 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4128 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4129 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4130 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4131 7 + /* gfx_v9_4_3_emit_mem_sync */ 4132 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4133 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4134 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4135 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4136 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4137 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4138 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4139 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4140 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4141 .test_ring = gfx_v9_4_3_ring_test_ring, 4142 .test_ib = gfx_v9_4_3_ring_test_ib, 4143 .insert_nop = amdgpu_ring_insert_nop, 4144 .pad_ib = amdgpu_ring_generic_pad_ib, 4145 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4146 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4147 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4148 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4149 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4150 }; 4151 4152 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4153 .type = AMDGPU_RING_TYPE_KIQ, 4154 .align_mask = 0xff, 4155 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4156 .support_64bit_ptrs = true, 4157 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4158 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4159 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4160 .emit_frame_size = 4161 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4162 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4163 5 + /* hdp invalidate */ 4164 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4165 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4166 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4167 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4168 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4169 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4170 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4171 .test_ring = gfx_v9_4_3_ring_test_ring, 4172 .insert_nop = amdgpu_ring_insert_nop, 4173 .pad_ib = amdgpu_ring_generic_pad_ib, 4174 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4175 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4176 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4177 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4178 }; 4179 4180 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4181 { 4182 int i, j, num_xcc; 4183 4184 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4185 for (i = 0; i < num_xcc; i++) { 4186 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4187 4188 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4189 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4190 = &gfx_v9_4_3_ring_funcs_compute; 4191 } 4192 } 4193 4194 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4195 .set = gfx_v9_4_3_set_eop_interrupt_state, 4196 .process = gfx_v9_4_3_eop_irq, 4197 }; 4198 4199 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4200 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4201 .process = gfx_v9_4_3_priv_reg_irq, 4202 }; 4203 4204 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4205 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4206 .process = gfx_v9_4_3_priv_inst_irq, 4207 }; 4208 4209 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4210 { 4211 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4212 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4213 4214 adev->gfx.priv_reg_irq.num_types = 1; 4215 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4216 4217 adev->gfx.priv_inst_irq.num_types = 1; 4218 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4219 } 4220 4221 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4222 { 4223 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4224 } 4225 4226 4227 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4228 { 4229 /* init asci gds info */ 4230 switch (adev->ip_versions[GC_HWIP][0]) { 4231 case IP_VERSION(9, 4, 3): 4232 /* 9.4.3 removed all the GDS internal memory, 4233 * only support GWS opcode in kernel, like barrier 4234 * semaphore.etc */ 4235 adev->gds.gds_size = 0; 4236 break; 4237 default: 4238 adev->gds.gds_size = 0x10000; 4239 break; 4240 } 4241 4242 switch (adev->ip_versions[GC_HWIP][0]) { 4243 case IP_VERSION(9, 4, 3): 4244 /* deprecated for 9.4.3, no usage at all */ 4245 adev->gds.gds_compute_max_wave_id = 0; 4246 break; 4247 default: 4248 /* this really depends on the chip */ 4249 adev->gds.gds_compute_max_wave_id = 0x7ff; 4250 break; 4251 } 4252 4253 adev->gds.gws_size = 64; 4254 adev->gds.oa_size = 16; 4255 } 4256 4257 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4258 u32 bitmap) 4259 { 4260 u32 data; 4261 4262 if (!bitmap) 4263 return; 4264 4265 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4266 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4267 4268 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4269 } 4270 4271 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4272 { 4273 u32 data, mask; 4274 4275 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4276 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4277 4278 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4279 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4280 4281 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4282 4283 return (~data) & mask; 4284 } 4285 4286 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4287 struct amdgpu_cu_info *cu_info) 4288 { 4289 int i, j, k, counter, active_cu_number = 0; 4290 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4291 unsigned disable_masks[4 * 4]; 4292 4293 if (!adev || !cu_info) 4294 return -EINVAL; 4295 4296 /* 4297 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4298 */ 4299 if (adev->gfx.config.max_shader_engines * 4300 adev->gfx.config.max_sh_per_se > 16) 4301 return -EINVAL; 4302 4303 amdgpu_gfx_parse_disable_cu(disable_masks, 4304 adev->gfx.config.max_shader_engines, 4305 adev->gfx.config.max_sh_per_se); 4306 4307 mutex_lock(&adev->grbm_idx_mutex); 4308 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4309 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4310 mask = 1; 4311 ao_bitmap = 0; 4312 counter = 0; 4313 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4314 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4315 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4316 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4317 4318 /* 4319 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4320 * 4x4 size array, and it's usually suitable for Vega 4321 * ASICs which has 4*2 SE/SH layout. 4322 * But for Arcturus, SE/SH layout is changed to 8*1. 4323 * To mostly reduce the impact, we make it compatible 4324 * with current bitmap array as below: 4325 * SE4,SH0 --> bitmap[0][1] 4326 * SE5,SH0 --> bitmap[1][1] 4327 * SE6,SH0 --> bitmap[2][1] 4328 * SE7,SH0 --> bitmap[3][1] 4329 */ 4330 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4331 4332 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4333 if (bitmap & mask) { 4334 if (counter < adev->gfx.config.max_cu_per_sh) 4335 ao_bitmap |= mask; 4336 counter++; 4337 } 4338 mask <<= 1; 4339 } 4340 active_cu_number += counter; 4341 if (i < 2 && j < 2) 4342 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4343 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4344 } 4345 } 4346 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4347 0); 4348 mutex_unlock(&adev->grbm_idx_mutex); 4349 4350 cu_info->number = active_cu_number; 4351 cu_info->ao_cu_mask = ao_cu_mask; 4352 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4353 4354 return 0; 4355 } 4356 4357 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4358 .type = AMD_IP_BLOCK_TYPE_GFX, 4359 .major = 9, 4360 .minor = 4, 4361 .rev = 0, 4362 .funcs = &gfx_v9_4_3_ip_funcs, 4363 }; 4364 4365 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4366 { 4367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4368 uint32_t tmp_mask; 4369 int i, r; 4370 4371 /* TODO : Initialize golden regs */ 4372 /* gfx_v9_4_3_init_golden_registers(adev); */ 4373 4374 tmp_mask = inst_mask; 4375 for_each_inst(i, tmp_mask) 4376 gfx_v9_4_3_xcc_constants_init(adev, i); 4377 4378 if (!amdgpu_sriov_vf(adev)) { 4379 tmp_mask = inst_mask; 4380 for_each_inst(i, tmp_mask) { 4381 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4382 if (r) 4383 return r; 4384 } 4385 } 4386 4387 tmp_mask = inst_mask; 4388 for_each_inst(i, tmp_mask) { 4389 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4390 if (r) 4391 return r; 4392 } 4393 4394 return 0; 4395 } 4396 4397 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4398 { 4399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4400 int i; 4401 4402 for_each_inst(i, inst_mask) 4403 gfx_v9_4_3_xcc_fini(adev, i); 4404 4405 return 0; 4406 } 4407 4408 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4409 .suspend = &gfx_v9_4_3_xcp_suspend, 4410 .resume = &gfx_v9_4_3_xcp_resume 4411 }; 4412 4413 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4414 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4415 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4416 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4417 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4418 }; 4419 4420 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4421 .ras_block = { 4422 .hw_ops = &gfx_v9_4_3_ras_ops, 4423 }, 4424 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4425 }; 4426