1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_xcp.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 #include "vega10_enum.h" 32 33 #include "clearstate_gfx9.h" 34 #include "v9_structs.h" 35 36 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 37 38 #include "gc/gc_9_4_3_offset.h" 39 #include "gc/gc_9_4_3_sh_mask.h" 40 41 #include "gfx_v9_4_3.h" 42 #include "amdgpu_xcp.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 46 47 #define GFX9_MEC_HPD_SIZE 4096 48 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 49 50 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 51 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 52 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 54 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 55 struct amdgpu_cu_info *cu_info); 56 57 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 58 uint64_t queue_mask) 59 { 60 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 61 amdgpu_ring_write(kiq_ring, 62 PACKET3_SET_RESOURCES_VMID_MASK(0) | 63 /* vmid_mask:0* queue_type:0 (KIQ) */ 64 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 65 amdgpu_ring_write(kiq_ring, 66 lower_32_bits(queue_mask)); /* queue mask lo */ 67 amdgpu_ring_write(kiq_ring, 68 upper_32_bits(queue_mask)); /* queue mask hi */ 69 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 70 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 72 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 73 } 74 75 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 76 struct amdgpu_ring *ring) 77 { 78 struct amdgpu_device *adev = kiq_ring->adev; 79 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 80 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 81 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 82 83 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 84 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 85 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 86 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 87 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 88 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 89 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 90 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 91 /*queue_type: normal compute queue */ 92 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 93 /* alloc format: all_on_one_pipe */ 94 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 95 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 96 /* num_queues: must be 1 */ 97 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 98 amdgpu_ring_write(kiq_ring, 99 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 100 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 101 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 104 } 105 106 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 107 struct amdgpu_ring *ring, 108 enum amdgpu_unmap_queues_action action, 109 u64 gpu_addr, u64 seq) 110 { 111 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 112 113 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 114 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 115 PACKET3_UNMAP_QUEUES_ACTION(action) | 116 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 117 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 118 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 119 amdgpu_ring_write(kiq_ring, 120 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 121 122 if (action == PREEMPT_QUEUES_NO_UNMAP) { 123 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 124 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 125 amdgpu_ring_write(kiq_ring, seq); 126 } else { 127 amdgpu_ring_write(kiq_ring, 0); 128 amdgpu_ring_write(kiq_ring, 0); 129 amdgpu_ring_write(kiq_ring, 0); 130 } 131 } 132 133 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 134 struct amdgpu_ring *ring, 135 u64 addr, 136 u64 seq) 137 { 138 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 139 140 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 141 amdgpu_ring_write(kiq_ring, 142 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 143 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 144 PACKET3_QUERY_STATUS_COMMAND(2)); 145 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 146 amdgpu_ring_write(kiq_ring, 147 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 148 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 149 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 150 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 153 } 154 155 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 156 uint16_t pasid, uint32_t flush_type, 157 bool all_hub) 158 { 159 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 160 amdgpu_ring_write(kiq_ring, 161 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 162 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 163 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 164 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 165 } 166 167 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 168 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 169 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 170 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 171 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 172 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 173 .set_resources_size = 8, 174 .map_queues_size = 7, 175 .unmap_queues_size = 6, 176 .query_status_size = 7, 177 .invalidate_tlbs_size = 2, 178 }; 179 180 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 181 { 182 int i, num_xcc; 183 184 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 185 for (i = 0; i < num_xcc; i++) 186 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 187 } 188 189 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 190 { 191 int i, num_xcc, dev_inst; 192 193 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 194 for (i = 0; i < num_xcc; i++) { 195 dev_inst = GET_INST(GC, i); 196 if (dev_inst >= 2) 197 WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4); 198 } 199 } 200 201 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 202 bool wc, uint32_t reg, uint32_t val) 203 { 204 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 205 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 206 WRITE_DATA_DST_SEL(0) | 207 (wc ? WR_CONFIRM : 0)); 208 amdgpu_ring_write(ring, reg); 209 amdgpu_ring_write(ring, 0); 210 amdgpu_ring_write(ring, val); 211 } 212 213 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 214 int mem_space, int opt, uint32_t addr0, 215 uint32_t addr1, uint32_t ref, uint32_t mask, 216 uint32_t inv) 217 { 218 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 219 amdgpu_ring_write(ring, 220 /* memory (1) or register (0) */ 221 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 222 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 223 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 224 WAIT_REG_MEM_ENGINE(eng_sel))); 225 226 if (mem_space) 227 BUG_ON(addr0 & 0x3); /* Dword align */ 228 amdgpu_ring_write(ring, addr0); 229 amdgpu_ring_write(ring, addr1); 230 amdgpu_ring_write(ring, ref); 231 amdgpu_ring_write(ring, mask); 232 amdgpu_ring_write(ring, inv); /* poll interval */ 233 } 234 235 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 236 { 237 uint32_t scratch_reg0_offset, xcc_offset; 238 struct amdgpu_device *adev = ring->adev; 239 uint32_t tmp = 0; 240 unsigned i; 241 int r; 242 243 /* Use register offset which is local to XCC in the packet */ 244 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 245 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 246 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 247 248 r = amdgpu_ring_alloc(ring, 3); 249 if (r) 250 return r; 251 252 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 253 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 254 amdgpu_ring_write(ring, 0xDEADBEEF); 255 amdgpu_ring_commit(ring); 256 257 for (i = 0; i < adev->usec_timeout; i++) { 258 tmp = RREG32(scratch_reg0_offset); 259 if (tmp == 0xDEADBEEF) 260 break; 261 udelay(1); 262 } 263 264 if (i >= adev->usec_timeout) 265 r = -ETIMEDOUT; 266 return r; 267 } 268 269 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 270 { 271 struct amdgpu_device *adev = ring->adev; 272 struct amdgpu_ib ib; 273 struct dma_fence *f = NULL; 274 275 unsigned index; 276 uint64_t gpu_addr; 277 uint32_t tmp; 278 long r; 279 280 r = amdgpu_device_wb_get(adev, &index); 281 if (r) 282 return r; 283 284 gpu_addr = adev->wb.gpu_addr + (index * 4); 285 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 286 memset(&ib, 0, sizeof(ib)); 287 r = amdgpu_ib_get(adev, NULL, 16, 288 AMDGPU_IB_POOL_DIRECT, &ib); 289 if (r) 290 goto err1; 291 292 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 293 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 294 ib.ptr[2] = lower_32_bits(gpu_addr); 295 ib.ptr[3] = upper_32_bits(gpu_addr); 296 ib.ptr[4] = 0xDEADBEEF; 297 ib.length_dw = 5; 298 299 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 300 if (r) 301 goto err2; 302 303 r = dma_fence_wait_timeout(f, false, timeout); 304 if (r == 0) { 305 r = -ETIMEDOUT; 306 goto err2; 307 } else if (r < 0) { 308 goto err2; 309 } 310 311 tmp = adev->wb.wb[index]; 312 if (tmp == 0xDEADBEEF) 313 r = 0; 314 else 315 r = -EINVAL; 316 317 err2: 318 amdgpu_ib_free(adev, &ib, NULL); 319 dma_fence_put(f); 320 err1: 321 amdgpu_device_wb_free(adev, index); 322 return r; 323 } 324 325 326 /* This value might differs per partition */ 327 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 328 { 329 uint64_t clock; 330 331 amdgpu_gfx_off_ctrl(adev, false); 332 mutex_lock(&adev->gfx.gpu_clock_mutex); 333 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 334 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 335 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 336 mutex_unlock(&adev->gfx.gpu_clock_mutex); 337 amdgpu_gfx_off_ctrl(adev, true); 338 339 return clock; 340 } 341 342 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 343 { 344 amdgpu_ucode_release(&adev->gfx.pfp_fw); 345 amdgpu_ucode_release(&adev->gfx.me_fw); 346 amdgpu_ucode_release(&adev->gfx.ce_fw); 347 amdgpu_ucode_release(&adev->gfx.rlc_fw); 348 amdgpu_ucode_release(&adev->gfx.mec_fw); 349 amdgpu_ucode_release(&adev->gfx.mec2_fw); 350 351 kfree(adev->gfx.rlc.register_list_format); 352 } 353 354 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 355 const char *chip_name) 356 { 357 char fw_name[30]; 358 int err; 359 const struct rlc_firmware_header_v2_0 *rlc_hdr; 360 uint16_t version_major; 361 uint16_t version_minor; 362 363 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 364 365 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 366 if (err) 367 goto out; 368 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 369 370 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 371 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 372 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 373 out: 374 if (err) 375 amdgpu_ucode_release(&adev->gfx.rlc_fw); 376 377 return err; 378 } 379 380 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 381 { 382 return true; 383 } 384 385 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 386 { 387 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 388 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 389 } 390 391 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 392 const char *chip_name) 393 { 394 char fw_name[30]; 395 int err; 396 397 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 398 399 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 400 if (err) 401 goto out; 402 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 403 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 404 405 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 406 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 407 408 gfx_v9_4_3_check_if_need_gfxoff(adev); 409 410 out: 411 if (err) 412 amdgpu_ucode_release(&adev->gfx.mec_fw); 413 return err; 414 } 415 416 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 417 { 418 const char *chip_name; 419 int r; 420 421 chip_name = "gc_9_4_3"; 422 423 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 424 if (r) 425 return r; 426 427 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 428 if (r) 429 return r; 430 431 return r; 432 } 433 434 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 435 { 436 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 437 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 438 } 439 440 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 441 { 442 int r, i, num_xcc; 443 u32 *hpd; 444 const __le32 *fw_data; 445 unsigned fw_size; 446 u32 *fw; 447 size_t mec_hpd_size; 448 449 const struct gfx_firmware_header_v1_0 *mec_hdr; 450 451 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 452 for (i = 0; i < num_xcc; i++) 453 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 454 AMDGPU_MAX_COMPUTE_QUEUES); 455 456 /* take ownership of the relevant compute queues */ 457 amdgpu_gfx_compute_queue_acquire(adev); 458 mec_hpd_size = 459 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 460 if (mec_hpd_size) { 461 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 462 AMDGPU_GEM_DOMAIN_VRAM, 463 &adev->gfx.mec.hpd_eop_obj, 464 &adev->gfx.mec.hpd_eop_gpu_addr, 465 (void **)&hpd); 466 if (r) { 467 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 468 gfx_v9_4_3_mec_fini(adev); 469 return r; 470 } 471 472 if (amdgpu_emu_mode == 1) { 473 for (i = 0; i < mec_hpd_size / 4; i++) { 474 memset((void *)(hpd + i), 0, 4); 475 if (i % 50 == 0) 476 msleep(1); 477 } 478 } else { 479 memset(hpd, 0, mec_hpd_size); 480 } 481 482 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 483 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 484 } 485 486 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 487 488 fw_data = (const __le32 *) 489 (adev->gfx.mec_fw->data + 490 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 491 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 492 493 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 494 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 495 &adev->gfx.mec.mec_fw_obj, 496 &adev->gfx.mec.mec_fw_gpu_addr, 497 (void **)&fw); 498 if (r) { 499 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 500 gfx_v9_4_3_mec_fini(adev); 501 return r; 502 } 503 504 memcpy(fw, fw_data, fw_size); 505 506 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 507 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 508 509 return 0; 510 } 511 512 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 513 u32 sh_num, u32 instance, int xcc_id) 514 { 515 u32 data; 516 517 if (instance == 0xffffffff) 518 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 519 INSTANCE_BROADCAST_WRITES, 1); 520 else 521 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 522 INSTANCE_INDEX, instance); 523 524 if (se_num == 0xffffffff) 525 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 526 SE_BROADCAST_WRITES, 1); 527 else 528 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 529 530 if (sh_num == 0xffffffff) 531 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 532 SH_BROADCAST_WRITES, 1); 533 else 534 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 535 536 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 537 } 538 539 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 540 { 541 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 542 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 543 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 544 (address << SQ_IND_INDEX__INDEX__SHIFT) | 545 (SQ_IND_INDEX__FORCE_READ_MASK)); 546 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 547 } 548 549 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 550 uint32_t wave, uint32_t thread, 551 uint32_t regno, uint32_t num, uint32_t *out) 552 { 553 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 554 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 555 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 556 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 557 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 558 (SQ_IND_INDEX__FORCE_READ_MASK) | 559 (SQ_IND_INDEX__AUTO_INCR_MASK)); 560 while (num--) 561 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 562 } 563 564 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 565 uint32_t xcc_id, uint32_t simd, uint32_t wave, 566 uint32_t *dst, int *no_fields) 567 { 568 /* type 1 wave data */ 569 dst[(*no_fields)++] = 1; 570 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 571 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 572 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 573 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 574 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 575 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 576 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 577 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 578 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 579 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 585 } 586 587 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 588 uint32_t wave, uint32_t start, 589 uint32_t size, uint32_t *dst) 590 { 591 wave_read_regs(adev, xcc_id, simd, wave, 0, 592 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 593 } 594 595 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 596 uint32_t wave, uint32_t thread, 597 uint32_t start, uint32_t size, 598 uint32_t *dst) 599 { 600 wave_read_regs(adev, xcc_id, simd, wave, thread, 601 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 602 } 603 604 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 605 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 606 { 607 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 608 } 609 static enum amdgpu_memory_partition 610 gfx_v9_4_3_query_memory_partition(struct amdgpu_device *adev) 611 { 612 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 613 614 if (adev->nbio.funcs->get_memory_partition_mode) 615 mode = adev->nbio.funcs->get_memory_partition_mode(adev); 616 617 return mode; 618 } 619 620 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 621 int num_xccs_per_xcp) 622 { 623 int i, num_xcc; 624 u32 tmp = 0; 625 626 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 627 628 for (i = 0; i < num_xcc; i++) { 629 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 630 num_xccs_per_xcp); 631 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 632 i % num_xccs_per_xcp); 633 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp); 634 } 635 636 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 637 638 return 0; 639 } 640 641 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 642 { 643 int xcc; 644 645 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 646 if (!xcc) { 647 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 648 return -EINVAL; 649 } 650 651 return xcc - 1; 652 } 653 654 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 655 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 656 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 657 .read_wave_data = &gfx_v9_4_3_read_wave_data, 658 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 659 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 660 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 661 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 662 .query_mem_partition_mode = &gfx_v9_4_3_query_memory_partition, 663 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 664 }; 665 666 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 667 { 668 u32 gb_addr_config; 669 670 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 671 672 switch (adev->ip_versions[GC_HWIP][0]) { 673 case IP_VERSION(9, 4, 3): 674 adev->gfx.config.max_hw_contexts = 8; 675 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 676 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 677 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 678 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 679 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 680 break; 681 default: 682 BUG(); 683 break; 684 } 685 686 adev->gfx.config.gb_addr_config = gb_addr_config; 687 688 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 689 REG_GET_FIELD( 690 adev->gfx.config.gb_addr_config, 691 GB_ADDR_CONFIG, 692 NUM_PIPES); 693 694 adev->gfx.config.max_tile_pipes = 695 adev->gfx.config.gb_addr_config_fields.num_pipes; 696 697 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 698 REG_GET_FIELD( 699 adev->gfx.config.gb_addr_config, 700 GB_ADDR_CONFIG, 701 NUM_BANKS); 702 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 703 REG_GET_FIELD( 704 adev->gfx.config.gb_addr_config, 705 GB_ADDR_CONFIG, 706 MAX_COMPRESSED_FRAGS); 707 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 708 REG_GET_FIELD( 709 adev->gfx.config.gb_addr_config, 710 GB_ADDR_CONFIG, 711 NUM_RB_PER_SE); 712 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 713 REG_GET_FIELD( 714 adev->gfx.config.gb_addr_config, 715 GB_ADDR_CONFIG, 716 NUM_SHADER_ENGINES); 717 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 718 REG_GET_FIELD( 719 adev->gfx.config.gb_addr_config, 720 GB_ADDR_CONFIG, 721 PIPE_INTERLEAVE_SIZE)); 722 723 return 0; 724 } 725 726 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 727 int xcc_id, int mec, int pipe, int queue) 728 { 729 unsigned irq_type; 730 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 731 unsigned int hw_prio; 732 uint32_t xcc_doorbell_start; 733 734 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 735 ring_id]; 736 737 /* mec0 is me1 */ 738 ring->xcc_id = xcc_id; 739 ring->me = mec + 1; 740 ring->pipe = pipe; 741 ring->queue = queue; 742 743 ring->ring_obj = NULL; 744 ring->use_doorbell = true; 745 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 746 xcc_id * adev->doorbell_index.xcc_doorbell_range; 747 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 748 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 749 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 750 GFX9_MEC_HPD_SIZE; 751 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 752 sprintf(ring->name, "comp_%d.%d.%d.%d", 753 ring->xcc_id, ring->me, ring->pipe, ring->queue); 754 755 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 756 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 757 + ring->pipe; 758 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 759 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 760 /* type-2 packets are deprecated on MEC, use type-3 instead */ 761 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 762 hw_prio, NULL); 763 } 764 765 static int gfx_v9_4_3_sw_init(void *handle) 766 { 767 int i, j, k, r, ring_id, xcc_id, num_xcc; 768 struct amdgpu_kiq *kiq; 769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 770 771 adev->gfx.mec.num_mec = 2; 772 adev->gfx.mec.num_pipe_per_mec = 4; 773 adev->gfx.mec.num_queue_per_pipe = 8; 774 775 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 776 777 /* EOP Event */ 778 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 779 if (r) 780 return r; 781 782 /* Privileged reg */ 783 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 784 &adev->gfx.priv_reg_irq); 785 if (r) 786 return r; 787 788 /* Privileged inst */ 789 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 790 &adev->gfx.priv_inst_irq); 791 if (r) 792 return r; 793 794 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 795 796 r = adev->gfx.rlc.funcs->init(adev); 797 if (r) { 798 DRM_ERROR("Failed to init rlc BOs!\n"); 799 return r; 800 } 801 802 r = gfx_v9_4_3_mec_init(adev); 803 if (r) { 804 DRM_ERROR("Failed to init MEC BOs!\n"); 805 return r; 806 } 807 808 /* set up the compute queues - allocate horizontally across pipes */ 809 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 810 ring_id = 0; 811 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 812 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 813 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 814 k++) { 815 if (!amdgpu_gfx_is_mec_queue_enabled( 816 adev, xcc_id, i, k, j)) 817 continue; 818 819 r = gfx_v9_4_3_compute_ring_init(adev, 820 ring_id, 821 xcc_id, 822 i, k, j); 823 if (r) 824 return r; 825 826 ring_id++; 827 } 828 } 829 } 830 831 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 832 if (r) { 833 DRM_ERROR("Failed to init KIQ BOs!\n"); 834 return r; 835 } 836 837 kiq = &adev->gfx.kiq[xcc_id]; 838 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 839 if (r) 840 return r; 841 842 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 843 r = amdgpu_gfx_mqd_sw_init(adev, 844 sizeof(struct v9_mqd_allocation), xcc_id); 845 if (r) 846 return r; 847 } 848 849 r = gfx_v9_4_3_gpu_early_init(adev); 850 if (r) 851 return r; 852 853 r = amdgpu_gfx_sysfs_init(adev); 854 if (r) 855 return r; 856 857 return 0; 858 } 859 860 static int gfx_v9_4_3_sw_fini(void *handle) 861 { 862 int i, num_xcc; 863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 864 865 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 866 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 867 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 868 869 for (i = 0; i < num_xcc; i++) { 870 amdgpu_gfx_mqd_sw_fini(adev, i); 871 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 872 amdgpu_gfx_kiq_fini(adev, i); 873 } 874 875 gfx_v9_4_3_mec_fini(adev); 876 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 877 gfx_v9_4_3_free_microcode(adev); 878 amdgpu_gfx_sysfs_fini(adev); 879 880 return 0; 881 } 882 883 #define DEFAULT_SH_MEM_BASES (0x6000) 884 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 885 int xcc_id) 886 { 887 int i; 888 uint32_t sh_mem_config; 889 uint32_t sh_mem_bases; 890 891 /* 892 * Configure apertures: 893 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 894 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 895 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 896 */ 897 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 898 899 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 900 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 901 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 902 903 mutex_lock(&adev->srbm_mutex); 904 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 905 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 906 /* CP and shaders */ 907 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 908 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 909 } 910 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 911 mutex_unlock(&adev->srbm_mutex); 912 913 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 914 acccess. These should be enabled by FW for target VMIDs. */ 915 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 916 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 917 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 918 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 919 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 920 } 921 } 922 923 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 924 { 925 int vmid; 926 927 /* 928 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 929 * access. Compute VMIDs should be enabled by FW for target VMIDs, 930 * the driver can enable them for graphics. VMID0 should maintain 931 * access so that HWS firmware can save/restore entries. 932 */ 933 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 934 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 935 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 936 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 937 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 938 } 939 } 940 941 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 942 int xcc_id) 943 { 944 u32 tmp; 945 int i; 946 947 /* XXX SH_MEM regs */ 948 /* where to put LDS, scratch, GPUVM in FSA64 space */ 949 mutex_lock(&adev->srbm_mutex); 950 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 951 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 952 /* CP and shaders */ 953 if (i == 0) { 954 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 955 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 956 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 957 !!adev->gmc.noretry); 958 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 959 regSH_MEM_CONFIG, tmp); 960 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 961 regSH_MEM_BASES, 0); 962 } else { 963 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 964 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 965 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 966 !!adev->gmc.noretry); 967 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 968 regSH_MEM_CONFIG, tmp); 969 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 970 (adev->gmc.private_aperture_start >> 971 48)); 972 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 973 (adev->gmc.shared_aperture_start >> 974 48)); 975 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 976 regSH_MEM_BASES, tmp); 977 } 978 } 979 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 980 981 mutex_unlock(&adev->srbm_mutex); 982 983 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 984 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 985 } 986 987 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 988 { 989 int i, num_xcc; 990 991 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 992 993 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 994 adev->gfx.config.db_debug2 = 995 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 996 997 for (i = 0; i < num_xcc; i++) 998 gfx_v9_4_3_xcc_constants_init(adev, i); 999 } 1000 1001 static void 1002 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1003 int xcc_id) 1004 { 1005 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1006 } 1007 1008 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1009 { 1010 /* 1011 * Rlc save restore list is workable since v2_1. 1012 * And it's needed by gfxoff feature. 1013 */ 1014 if (adev->gfx.rlc.is_rlc_v2_1) 1015 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1016 1017 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1018 AMD_PG_SUPPORT_GFX_SMG | 1019 AMD_PG_SUPPORT_GFX_DMG | 1020 AMD_PG_SUPPORT_CP | 1021 AMD_PG_SUPPORT_GDS | 1022 AMD_PG_SUPPORT_RLC_SMU_HS)) { 1023 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_JUMP_TABLE_RESTORE, 1024 adev->gfx.rlc.cp_table_gpu_addr >> 8); 1025 } 1026 } 1027 1028 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1029 { 1030 uint32_t data; 1031 1032 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1033 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1034 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1035 } 1036 1037 static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev, 1038 int xcc_id) 1039 { 1040 uint32_t tmp = 0; 1041 int num_xcc; 1042 1043 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1044 switch (num_xcc) { 1045 /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ 1046 case 1: 1047 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, 0x8); 1048 break; 1049 case 2: 1050 tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); 1051 tmp = tmp | (adev->gfx.num_xcc_per_xcp << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); 1052 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, tmp); 1053 1054 break; 1055 default: 1056 break; 1057 } 1058 } 1059 1060 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1061 { 1062 uint32_t rlc_setting; 1063 1064 /* if RLC is not enabled, do nothing */ 1065 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1066 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1067 return false; 1068 1069 return true; 1070 } 1071 1072 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1073 { 1074 uint32_t data; 1075 unsigned i; 1076 1077 data = RLC_SAFE_MODE__CMD_MASK; 1078 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1079 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1080 1081 /* wait for RLC_SAFE_MODE */ 1082 for (i = 0; i < adev->usec_timeout; i++) { 1083 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1084 break; 1085 udelay(1); 1086 } 1087 } 1088 1089 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1090 int xcc_id) 1091 { 1092 uint32_t data; 1093 1094 data = RLC_SAFE_MODE__CMD_MASK; 1095 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1096 } 1097 1098 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1099 { 1100 /* init spm vmid with 0xf */ 1101 if (adev->gfx.rlc.funcs->update_spm_vmid) 1102 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1103 1104 return 0; 1105 } 1106 1107 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1108 int xcc_id) 1109 { 1110 u32 i, j, k; 1111 u32 mask; 1112 1113 mutex_lock(&adev->grbm_idx_mutex); 1114 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1115 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1116 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1117 xcc_id); 1118 for (k = 0; k < adev->usec_timeout; k++) { 1119 if (RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1120 break; 1121 udelay(1); 1122 } 1123 if (k == adev->usec_timeout) { 1124 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1125 0xffffffff, 1126 0xffffffff, xcc_id); 1127 mutex_unlock(&adev->grbm_idx_mutex); 1128 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1129 i, j); 1130 return; 1131 } 1132 } 1133 } 1134 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1135 xcc_id); 1136 mutex_unlock(&adev->grbm_idx_mutex); 1137 1138 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1139 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1140 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1141 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1142 for (k = 0; k < adev->usec_timeout; k++) { 1143 if ((RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1144 break; 1145 udelay(1); 1146 } 1147 } 1148 1149 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1150 bool enable, int xcc_id) 1151 { 1152 u32 tmp; 1153 1154 /* These interrupts should be enabled to drive DS clock */ 1155 1156 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1157 1158 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1159 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1160 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1161 1162 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1163 } 1164 1165 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1166 { 1167 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1168 RLC_ENABLE_F32, 0); 1169 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1170 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1171 } 1172 1173 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1174 { 1175 int i, num_xcc; 1176 1177 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1178 for (i = 0; i < num_xcc; i++) 1179 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1180 } 1181 1182 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1183 { 1184 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1185 SOFT_RESET_RLC, 1); 1186 udelay(50); 1187 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1188 SOFT_RESET_RLC, 0); 1189 udelay(50); 1190 } 1191 1192 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1193 { 1194 int i, num_xcc; 1195 1196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1197 for (i = 0; i < num_xcc; i++) 1198 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1199 } 1200 1201 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1202 { 1203 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1204 RLC_ENABLE_F32, 1); 1205 udelay(50); 1206 1207 /* carrizo do enable cp interrupt after cp inited */ 1208 if (!(adev->flags & AMD_IS_APU)) { 1209 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1210 udelay(50); 1211 } 1212 } 1213 1214 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1215 { 1216 #ifdef AMDGPU_RLC_DEBUG_RETRY 1217 u32 rlc_ucode_ver; 1218 #endif 1219 int i, num_xcc; 1220 1221 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1222 for (i = 0; i < num_xcc; i++) { 1223 gfx_v9_4_3_xcc_rlc_start(adev, i); 1224 #ifdef AMDGPU_RLC_DEBUG_RETRY 1225 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1226 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1227 if (rlc_ucode_ver == 0x108) { 1228 dev_info(adev->dev, 1229 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1230 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1231 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1232 * default is 0x9C4 to create a 100us interval */ 1233 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1234 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1235 * to disable the page fault retry interrupts, default is 1236 * 0x100 (256) */ 1237 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1238 } 1239 #endif 1240 } 1241 } 1242 1243 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1244 int xcc_id) 1245 { 1246 const struct rlc_firmware_header_v2_0 *hdr; 1247 const __le32 *fw_data; 1248 unsigned i, fw_size; 1249 1250 if (!adev->gfx.rlc_fw) 1251 return -EINVAL; 1252 1253 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1254 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1255 1256 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1257 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1258 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1259 1260 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1261 RLCG_UCODE_LOADING_START_ADDRESS); 1262 for (i = 0; i < fw_size; i++) { 1263 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1264 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1265 msleep(1); 1266 } 1267 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1268 } 1269 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1270 1271 return 0; 1272 } 1273 1274 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1275 { 1276 int r; 1277 1278 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1279 1280 /* disable CG */ 1281 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1282 1283 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1284 1285 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1286 /* legacy rlc firmware loading */ 1287 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1288 if (r) 1289 return r; 1290 } 1291 1292 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1293 1294 return 0; 1295 } 1296 1297 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1298 { 1299 int r, i, num_xcc; 1300 1301 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1302 for (i = 0; i < num_xcc; i++) { 1303 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1304 if (r) 1305 return r; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1312 unsigned vmid) 1313 { 1314 u32 reg, data; 1315 1316 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1317 if (amdgpu_sriov_is_pp_one_vf(adev)) 1318 data = RREG32_NO_KIQ(reg); 1319 else 1320 data = RREG32(reg); 1321 1322 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1323 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1324 1325 if (amdgpu_sriov_is_pp_one_vf(adev)) 1326 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1327 else 1328 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1329 } 1330 1331 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1332 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1333 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1334 }; 1335 1336 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1337 uint32_t offset, 1338 struct soc15_reg_rlcg *entries, int arr_size) 1339 { 1340 int i, inst; 1341 uint32_t reg; 1342 1343 if (!entries) 1344 return false; 1345 1346 for (i = 0; i < arr_size; i++) { 1347 const struct soc15_reg_rlcg *entry; 1348 1349 entry = &entries[i]; 1350 inst = adev->ip_map.logical_to_dev_inst ? 1351 adev->ip_map.logical_to_dev_inst( 1352 adev, entry->hwip, entry->instance) : 1353 entry->instance; 1354 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1355 entry->reg; 1356 if (offset == reg) 1357 return true; 1358 } 1359 1360 return false; 1361 } 1362 1363 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1364 { 1365 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1366 (void *)rlcg_access_gc_9_4_3, 1367 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1368 } 1369 1370 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1371 bool enable, int xcc_id) 1372 { 1373 if (enable) { 1374 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1375 } else { 1376 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1377 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1378 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1379 } 1380 udelay(50); 1381 } 1382 1383 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1384 int xcc_id) 1385 { 1386 const struct gfx_firmware_header_v1_0 *mec_hdr; 1387 const __le32 *fw_data; 1388 unsigned i; 1389 u32 tmp; 1390 u32 mec_ucode_addr_offset; 1391 u32 mec_ucode_data_offset; 1392 1393 if (!adev->gfx.mec_fw) 1394 return -EINVAL; 1395 1396 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1397 1398 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1399 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1400 1401 fw_data = (const __le32 *) 1402 (adev->gfx.mec_fw->data + 1403 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1404 tmp = 0; 1405 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1406 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1407 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1408 1409 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1410 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1411 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1412 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1413 1414 mec_ucode_addr_offset = 1415 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1416 mec_ucode_data_offset = 1417 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1418 1419 /* MEC1 */ 1420 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1421 for (i = 0; i < mec_hdr->jt_size; i++) 1422 WREG32(mec_ucode_data_offset, 1423 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1424 1425 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1426 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1427 1428 return 0; 1429 } 1430 1431 /* KIQ functions */ 1432 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1433 { 1434 uint32_t tmp; 1435 struct amdgpu_device *adev = ring->adev; 1436 1437 /* tell RLC which is KIQ queue */ 1438 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1439 tmp &= 0xffffff00; 1440 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1441 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1442 tmp |= 0x80; 1443 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1444 } 1445 1446 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1447 { 1448 struct amdgpu_device *adev = ring->adev; 1449 1450 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1451 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1452 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1453 mqd->cp_hqd_queue_priority = 1454 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1455 } 1456 } 1457 } 1458 1459 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1460 { 1461 struct amdgpu_device *adev = ring->adev; 1462 struct v9_mqd *mqd = ring->mqd_ptr; 1463 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1464 uint32_t tmp; 1465 1466 mqd->header = 0xC0310800; 1467 mqd->compute_pipelinestat_enable = 0x00000001; 1468 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1469 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1470 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1471 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1472 mqd->compute_misc_reserved = 0x00000003; 1473 1474 mqd->dynamic_cu_mask_addr_lo = 1475 lower_32_bits(ring->mqd_gpu_addr 1476 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1477 mqd->dynamic_cu_mask_addr_hi = 1478 upper_32_bits(ring->mqd_gpu_addr 1479 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1480 1481 eop_base_addr = ring->eop_gpu_addr >> 8; 1482 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1483 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1484 1485 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1486 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1487 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1488 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1489 1490 mqd->cp_hqd_eop_control = tmp; 1491 1492 /* enable doorbell? */ 1493 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1494 1495 if (ring->use_doorbell) { 1496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1497 DOORBELL_OFFSET, ring->doorbell_index); 1498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1499 DOORBELL_EN, 1); 1500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1501 DOORBELL_SOURCE, 0); 1502 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1503 DOORBELL_HIT, 0); 1504 } else { 1505 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1506 DOORBELL_EN, 0); 1507 } 1508 1509 mqd->cp_hqd_pq_doorbell_control = tmp; 1510 1511 /* disable the queue if it's active */ 1512 ring->wptr = 0; 1513 mqd->cp_hqd_dequeue_request = 0; 1514 mqd->cp_hqd_pq_rptr = 0; 1515 mqd->cp_hqd_pq_wptr_lo = 0; 1516 mqd->cp_hqd_pq_wptr_hi = 0; 1517 1518 /* set the pointer to the MQD */ 1519 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1520 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1521 1522 /* set MQD vmid to 0 */ 1523 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1524 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1525 mqd->cp_mqd_control = tmp; 1526 1527 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1528 hqd_gpu_addr = ring->gpu_addr >> 8; 1529 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1530 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1531 1532 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1533 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1535 (order_base_2(ring->ring_size / 4) - 1)); 1536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1537 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1538 #ifdef __BIG_ENDIAN 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1540 #endif 1541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1543 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1545 mqd->cp_hqd_pq_control = tmp; 1546 1547 /* set the wb address whether it's enabled or not */ 1548 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1549 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1550 mqd->cp_hqd_pq_rptr_report_addr_hi = 1551 upper_32_bits(wb_gpu_addr) & 0xffff; 1552 1553 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1554 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1555 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1556 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1557 1558 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1559 ring->wptr = 0; 1560 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1561 1562 /* set the vmid for the queue */ 1563 mqd->cp_hqd_vmid = 0; 1564 1565 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1566 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1567 mqd->cp_hqd_persistent_state = tmp; 1568 1569 /* set MIN_IB_AVAIL_SIZE */ 1570 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1571 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1572 mqd->cp_hqd_ib_control = tmp; 1573 1574 /* set static priority for a queue/ring */ 1575 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1576 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1577 1578 /* map_queues packet doesn't need activate the queue, 1579 * so only kiq need set this field. 1580 */ 1581 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1582 mqd->cp_hqd_active = 1; 1583 1584 return 0; 1585 } 1586 1587 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1588 int xcc_id) 1589 { 1590 struct amdgpu_device *adev = ring->adev; 1591 struct v9_mqd *mqd = ring->mqd_ptr; 1592 int j; 1593 1594 /* disable wptr polling */ 1595 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1596 1597 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1598 mqd->cp_hqd_eop_base_addr_lo); 1599 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1600 mqd->cp_hqd_eop_base_addr_hi); 1601 1602 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1603 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1604 mqd->cp_hqd_eop_control); 1605 1606 /* enable doorbell? */ 1607 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1608 mqd->cp_hqd_pq_doorbell_control); 1609 1610 /* disable the queue if it's active */ 1611 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1612 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1613 for (j = 0; j < adev->usec_timeout; j++) { 1614 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1615 break; 1616 udelay(1); 1617 } 1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1619 mqd->cp_hqd_dequeue_request); 1620 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1621 mqd->cp_hqd_pq_rptr); 1622 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1623 mqd->cp_hqd_pq_wptr_lo); 1624 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1625 mqd->cp_hqd_pq_wptr_hi); 1626 } 1627 1628 /* set the pointer to the MQD */ 1629 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1630 mqd->cp_mqd_base_addr_lo); 1631 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1632 mqd->cp_mqd_base_addr_hi); 1633 1634 /* set MQD vmid to 0 */ 1635 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1636 mqd->cp_mqd_control); 1637 1638 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1639 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1640 mqd->cp_hqd_pq_base_lo); 1641 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1642 mqd->cp_hqd_pq_base_hi); 1643 1644 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1645 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1646 mqd->cp_hqd_pq_control); 1647 1648 /* set the wb address whether it's enabled or not */ 1649 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1650 mqd->cp_hqd_pq_rptr_report_addr_lo); 1651 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1652 mqd->cp_hqd_pq_rptr_report_addr_hi); 1653 1654 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1655 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1656 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1657 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1658 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1659 1660 /* enable the doorbell if requested */ 1661 if (ring->use_doorbell) { 1662 WREG32_SOC15( 1663 GC, GET_INST(GC, xcc_id), 1664 regCP_MEC_DOORBELL_RANGE_LOWER, 1665 ((adev->doorbell_index.kiq + 1666 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1667 2) << 2); 1668 WREG32_SOC15( 1669 GC, GET_INST(GC, xcc_id), 1670 regCP_MEC_DOORBELL_RANGE_UPPER, 1671 ((adev->doorbell_index.userqueue_end + 1672 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1673 2) << 2); 1674 } 1675 1676 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1677 mqd->cp_hqd_pq_doorbell_control); 1678 1679 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1680 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1681 mqd->cp_hqd_pq_wptr_lo); 1682 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1683 mqd->cp_hqd_pq_wptr_hi); 1684 1685 /* set the vmid for the queue */ 1686 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1687 1688 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1689 mqd->cp_hqd_persistent_state); 1690 1691 /* activate the queue */ 1692 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1693 mqd->cp_hqd_active); 1694 1695 if (ring->use_doorbell) 1696 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1697 1698 return 0; 1699 } 1700 1701 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1702 int xcc_id) 1703 { 1704 struct amdgpu_device *adev = ring->adev; 1705 int j; 1706 1707 /* disable the queue if it's active */ 1708 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1709 1710 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1711 1712 for (j = 0; j < adev->usec_timeout; j++) { 1713 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1714 break; 1715 udelay(1); 1716 } 1717 1718 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1719 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1720 1721 /* Manual disable if dequeue request times out */ 1722 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1723 } 1724 1725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1726 0); 1727 } 1728 1729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1731 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0); 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1737 1738 return 0; 1739 } 1740 1741 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1742 { 1743 struct amdgpu_device *adev = ring->adev; 1744 struct v9_mqd *mqd = ring->mqd_ptr; 1745 struct v9_mqd *tmp_mqd; 1746 1747 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1748 1749 /* GPU could be in bad state during probe, driver trigger the reset 1750 * after load the SMU, in this case , the mqd is not be initialized. 1751 * driver need to re-init the mqd. 1752 * check mqd->cp_hqd_pq_control since this value should not be 0 1753 */ 1754 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1755 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1756 /* for GPU_RESET case , reset MQD to a clean status */ 1757 if (adev->gfx.kiq[xcc_id].mqd_backup) 1758 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1759 1760 /* reset ring buffer */ 1761 ring->wptr = 0; 1762 amdgpu_ring_clear_ring(ring); 1763 mutex_lock(&adev->srbm_mutex); 1764 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1765 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1766 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1767 mutex_unlock(&adev->srbm_mutex); 1768 } else { 1769 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1770 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1771 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1772 mutex_lock(&adev->srbm_mutex); 1773 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1774 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1775 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1776 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1777 mutex_unlock(&adev->srbm_mutex); 1778 1779 if (adev->gfx.kiq[xcc_id].mqd_backup) 1780 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1787 { 1788 struct amdgpu_device *adev = ring->adev; 1789 struct v9_mqd *mqd = ring->mqd_ptr; 1790 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1791 struct v9_mqd *tmp_mqd; 1792 1793 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1794 * is not be initialized before 1795 */ 1796 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1797 1798 if (!tmp_mqd->cp_hqd_pq_control || 1799 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1800 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1801 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1802 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1803 mutex_lock(&adev->srbm_mutex); 1804 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1805 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1806 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1807 mutex_unlock(&adev->srbm_mutex); 1808 1809 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1810 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1811 } else { 1812 /* restore MQD to a clean status */ 1813 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1814 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1815 /* reset ring buffer */ 1816 ring->wptr = 0; 1817 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1818 amdgpu_ring_clear_ring(ring); 1819 } 1820 1821 return 0; 1822 } 1823 1824 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1825 { 1826 struct amdgpu_ring *ring; 1827 int j; 1828 1829 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1830 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1831 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1832 mutex_lock(&adev->srbm_mutex); 1833 soc15_grbm_select(adev, ring->me, 1834 ring->pipe, 1835 ring->queue, 0, GET_INST(GC, xcc_id)); 1836 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1837 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1838 mutex_unlock(&adev->srbm_mutex); 1839 } 1840 } 1841 1842 return 0; 1843 } 1844 1845 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1846 { 1847 struct amdgpu_ring *ring; 1848 int r; 1849 1850 ring = &adev->gfx.kiq[xcc_id].ring; 1851 1852 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1853 if (unlikely(r != 0)) 1854 return r; 1855 1856 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1857 if (unlikely(r != 0)) { 1858 amdgpu_bo_unreserve(ring->mqd_obj); 1859 return r; 1860 } 1861 1862 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1863 amdgpu_bo_kunmap(ring->mqd_obj); 1864 ring->mqd_ptr = NULL; 1865 amdgpu_bo_unreserve(ring->mqd_obj); 1866 ring->sched.ready = true; 1867 return 0; 1868 } 1869 1870 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1871 { 1872 struct amdgpu_ring *ring = NULL; 1873 int r = 0, i; 1874 1875 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1876 1877 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1878 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1879 1880 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1881 if (unlikely(r != 0)) 1882 goto done; 1883 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1884 if (!r) { 1885 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1886 amdgpu_bo_kunmap(ring->mqd_obj); 1887 ring->mqd_ptr = NULL; 1888 } 1889 amdgpu_bo_unreserve(ring->mqd_obj); 1890 if (r) 1891 goto done; 1892 } 1893 1894 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1895 done: 1896 return r; 1897 } 1898 1899 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1900 { 1901 struct amdgpu_ring *ring; 1902 int r, j; 1903 1904 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1905 1906 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1907 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1908 1909 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1910 if (r) 1911 return r; 1912 } 1913 1914 /* set the virtual and physical id based on partition_mode */ 1915 gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id); 1916 1917 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1918 if (r) 1919 return r; 1920 1921 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1922 if (r) 1923 return r; 1924 1925 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1926 ring = &adev->gfx.compute_ring 1927 [j + xcc_id * adev->gfx.num_compute_rings]; 1928 r = amdgpu_ring_test_helper(ring); 1929 if (r) 1930 return r; 1931 } 1932 1933 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1934 1935 return 0; 1936 } 1937 1938 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1939 { 1940 int r, i, num_xcc; 1941 1942 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr) == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1943 amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, amdgpu_user_partt_mode); 1944 1945 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1946 for (i = 0; i < num_xcc; i++) { 1947 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1948 if (r) 1949 return r; 1950 } 1951 1952 return 0; 1953 } 1954 1955 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1956 int xcc_id) 1957 { 1958 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1959 } 1960 1961 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1962 { 1963 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1964 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1965 1966 /* Use deinitialize sequence from CAIL when unbinding device 1967 * from driver, otherwise KIQ is hanging when binding back 1968 */ 1969 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1970 mutex_lock(&adev->srbm_mutex); 1971 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1972 adev->gfx.kiq[xcc_id].ring.pipe, 1973 adev->gfx.kiq[xcc_id].ring.queue, 0, 1974 GET_INST(GC, xcc_id)); 1975 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1976 xcc_id); 1977 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1978 mutex_unlock(&adev->srbm_mutex); 1979 } 1980 1981 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 1982 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 1983 1984 /* Skip suspend with A+A reset */ 1985 if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) { 1986 dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n"); 1987 return; 1988 } 1989 1990 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1991 } 1992 1993 static int gfx_v9_4_3_hw_init(void *handle) 1994 { 1995 int r; 1996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1997 1998 gfx_v9_4_3_init_golden_registers(adev); 1999 2000 gfx_v9_4_3_constants_init(adev); 2001 2002 r = adev->gfx.rlc.funcs->resume(adev); 2003 if (r) 2004 return r; 2005 2006 r = gfx_v9_4_3_cp_resume(adev); 2007 if (r) 2008 return r; 2009 2010 return r; 2011 } 2012 2013 static int gfx_v9_4_3_hw_fini(void *handle) 2014 { 2015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2016 int i, num_xcc; 2017 2018 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2019 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2020 2021 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2022 for (i = 0; i < num_xcc; i++) { 2023 gfx_v9_4_3_xcc_fini(adev, i); 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int gfx_v9_4_3_suspend(void *handle) 2030 { 2031 return gfx_v9_4_3_hw_fini(handle); 2032 } 2033 2034 static int gfx_v9_4_3_resume(void *handle) 2035 { 2036 return gfx_v9_4_3_hw_init(handle); 2037 } 2038 2039 static bool gfx_v9_4_3_is_idle(void *handle) 2040 { 2041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2042 int i, num_xcc; 2043 2044 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2045 for (i = 0; i < num_xcc; i++) { 2046 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2047 GRBM_STATUS, GUI_ACTIVE)) 2048 return false; 2049 } 2050 return true; 2051 } 2052 2053 static int gfx_v9_4_3_wait_for_idle(void *handle) 2054 { 2055 unsigned i; 2056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2057 2058 for (i = 0; i < adev->usec_timeout; i++) { 2059 if (gfx_v9_4_3_is_idle(handle)) 2060 return 0; 2061 udelay(1); 2062 } 2063 return -ETIMEDOUT; 2064 } 2065 2066 static int gfx_v9_4_3_soft_reset(void *handle) 2067 { 2068 u32 grbm_soft_reset = 0; 2069 u32 tmp; 2070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2071 2072 /* GRBM_STATUS */ 2073 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2074 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2075 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2076 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2077 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2078 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2079 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2080 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2081 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2082 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2083 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2084 } 2085 2086 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2087 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2088 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2089 } 2090 2091 /* GRBM_STATUS2 */ 2092 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2093 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2094 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2095 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2096 2097 2098 if (grbm_soft_reset) { 2099 /* stop the rlc */ 2100 adev->gfx.rlc.funcs->stop(adev); 2101 2102 /* Disable MEC parsing/prefetching */ 2103 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2104 2105 if (grbm_soft_reset) { 2106 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2107 tmp |= grbm_soft_reset; 2108 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2109 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2110 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2111 2112 udelay(50); 2113 2114 tmp &= ~grbm_soft_reset; 2115 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2116 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2117 } 2118 2119 /* Wait a little for things to settle down */ 2120 udelay(50); 2121 } 2122 return 0; 2123 } 2124 2125 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2126 uint32_t vmid, 2127 uint32_t gds_base, uint32_t gds_size, 2128 uint32_t gws_base, uint32_t gws_size, 2129 uint32_t oa_base, uint32_t oa_size) 2130 { 2131 struct amdgpu_device *adev = ring->adev; 2132 2133 /* GDS Base */ 2134 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2135 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2136 gds_base); 2137 2138 /* GDS Size */ 2139 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2140 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2141 gds_size); 2142 2143 /* GWS */ 2144 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2145 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2146 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2147 2148 /* OA */ 2149 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2150 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2151 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2152 } 2153 2154 static int gfx_v9_4_3_early_init(void *handle) 2155 { 2156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2157 int num_xcc; 2158 2159 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2160 2161 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2162 AMDGPU_MAX_COMPUTE_RINGS); 2163 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2164 gfx_v9_4_3_set_ring_funcs(adev); 2165 gfx_v9_4_3_set_irq_funcs(adev); 2166 gfx_v9_4_3_set_gds_init(adev); 2167 gfx_v9_4_3_set_rlc_funcs(adev); 2168 2169 return gfx_v9_4_3_init_microcode(adev); 2170 } 2171 2172 static int gfx_v9_4_3_late_init(void *handle) 2173 { 2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2175 int r; 2176 2177 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2178 if (r) 2179 return r; 2180 2181 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2182 if (r) 2183 return r; 2184 2185 return 0; 2186 } 2187 2188 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2189 bool enable, int xcc_id) 2190 { 2191 uint32_t def, data; 2192 2193 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2194 return; 2195 2196 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2197 regRLC_CGTT_MGCG_OVERRIDE); 2198 2199 if (enable) 2200 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2201 else 2202 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2203 2204 if (def != data) 2205 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2206 regRLC_CGTT_MGCG_OVERRIDE, data); 2207 2208 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2209 2210 if (enable) 2211 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2212 else 2213 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2214 2215 if (def != data) 2216 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2217 } 2218 2219 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2220 bool enable, int xcc_id) 2221 { 2222 uint32_t def, data; 2223 2224 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2225 return; 2226 2227 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2228 regRLC_CGTT_MGCG_OVERRIDE); 2229 2230 if (enable) 2231 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2232 else 2233 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2234 2235 if (def != data) 2236 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2237 regRLC_CGTT_MGCG_OVERRIDE, data); 2238 } 2239 2240 static void 2241 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2242 bool enable, int xcc_id) 2243 { 2244 uint32_t data, def; 2245 2246 /* It is disabled by HW by default */ 2247 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2248 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2249 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2250 2251 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2252 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2253 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2254 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2255 2256 if (def != data) 2257 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2258 2259 /* MGLS is a global flag to control all MGLS in GFX */ 2260 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2261 /* 2 - RLC memory Light sleep */ 2262 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2263 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2264 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2265 if (def != data) 2266 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2267 } 2268 /* 3 - CP memory Light sleep */ 2269 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2270 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2271 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2272 if (def != data) 2273 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2274 } 2275 } 2276 } else { 2277 /* 1 - MGCG_OVERRIDE */ 2278 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2279 2280 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2281 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2282 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2283 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2284 2285 if (def != data) 2286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2287 2288 /* 2 - disable MGLS in RLC */ 2289 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2290 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2291 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2292 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2293 } 2294 2295 /* 3 - disable MGLS in CP */ 2296 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2297 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2298 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2300 } 2301 } 2302 2303 } 2304 2305 static void 2306 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2307 bool enable, int xcc_id) 2308 { 2309 uint32_t def, data; 2310 2311 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2312 2313 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2314 /* unset CGCG override */ 2315 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2316 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2317 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2318 else 2319 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2320 /* update CGCG and CGLS override bits */ 2321 if (def != data) 2322 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2323 2324 /* enable cgcg FSM(0x0000363F) */ 2325 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2326 2327 data = (0x36 2328 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2329 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2330 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2331 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2332 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2333 if (def != data) 2334 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2335 2336 /* set IDLE_POLL_COUNT(0x00900100) */ 2337 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2338 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2339 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2340 if (def != data) 2341 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2342 } else { 2343 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2344 /* reset CGCG/CGLS bits */ 2345 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2346 /* disable cgcg and cgls in FSM */ 2347 if (def != data) 2348 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2349 } 2350 2351 } 2352 2353 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2354 bool enable, int xcc_id) 2355 { 2356 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2357 2358 if (enable) { 2359 /* FGCG */ 2360 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2361 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2362 2363 /* CGCG/CGLS should be enabled after MGCG/MGLS 2364 * === MGCG + MGLS === 2365 */ 2366 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2367 xcc_id); 2368 /* === CGCG + CGLS === */ 2369 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2370 xcc_id); 2371 } else { 2372 /* CGCG/CGLS should be disabled before MGCG/MGLS 2373 * === CGCG + CGLS === 2374 */ 2375 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2376 xcc_id); 2377 /* === MGCG + MGLS === */ 2378 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2379 xcc_id); 2380 2381 /* FGCG */ 2382 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2383 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2384 } 2385 2386 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2387 2388 return 0; 2389 } 2390 2391 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2392 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2393 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2394 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2395 .init = gfx_v9_4_3_rlc_init, 2396 .resume = gfx_v9_4_3_rlc_resume, 2397 .stop = gfx_v9_4_3_rlc_stop, 2398 .reset = gfx_v9_4_3_rlc_reset, 2399 .start = gfx_v9_4_3_rlc_start, 2400 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2401 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2402 }; 2403 2404 static int gfx_v9_4_3_set_powergating_state(void *handle, 2405 enum amd_powergating_state state) 2406 { 2407 return 0; 2408 } 2409 2410 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2411 enum amd_clockgating_state state) 2412 { 2413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2414 int i, num_xcc; 2415 2416 if (amdgpu_sriov_vf(adev)) 2417 return 0; 2418 2419 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2420 switch (adev->ip_versions[GC_HWIP][0]) { 2421 case IP_VERSION(9, 4, 3): 2422 for (i = 0; i < num_xcc; i++) 2423 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2424 adev, state == AMD_CG_STATE_GATE, i); 2425 break; 2426 default: 2427 break; 2428 } 2429 return 0; 2430 } 2431 2432 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2433 { 2434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2435 int data; 2436 2437 if (amdgpu_sriov_vf(adev)) 2438 *flags = 0; 2439 2440 /* AMD_CG_SUPPORT_GFX_MGCG */ 2441 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2442 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2443 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2444 2445 /* AMD_CG_SUPPORT_GFX_CGCG */ 2446 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2447 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2448 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2449 2450 /* AMD_CG_SUPPORT_GFX_CGLS */ 2451 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2452 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2453 2454 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2455 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2456 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2457 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2458 2459 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2460 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2461 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2462 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2463 } 2464 2465 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2466 { 2467 struct amdgpu_device *adev = ring->adev; 2468 u32 ref_and_mask, reg_mem_engine; 2469 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2470 2471 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2472 switch (ring->me) { 2473 case 1: 2474 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2475 break; 2476 case 2: 2477 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2478 break; 2479 default: 2480 return; 2481 } 2482 reg_mem_engine = 0; 2483 } else { 2484 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2485 reg_mem_engine = 1; /* pfp */ 2486 } 2487 2488 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2489 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2490 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2491 ref_and_mask, ref_and_mask, 0x20); 2492 } 2493 2494 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2495 struct amdgpu_job *job, 2496 struct amdgpu_ib *ib, 2497 uint32_t flags) 2498 { 2499 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2500 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2501 2502 /* Currently, there is a high possibility to get wave ID mismatch 2503 * between ME and GDS, leading to a hw deadlock, because ME generates 2504 * different wave IDs than the GDS expects. This situation happens 2505 * randomly when at least 5 compute pipes use GDS ordered append. 2506 * The wave IDs generated by ME are also wrong after suspend/resume. 2507 * Those are probably bugs somewhere else in the kernel driver. 2508 * 2509 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2510 * GDS to 0 for this ring (me/pipe). 2511 */ 2512 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2513 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2514 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2515 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2516 } 2517 2518 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2519 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2520 amdgpu_ring_write(ring, 2521 #ifdef __BIG_ENDIAN 2522 (2 << 0) | 2523 #endif 2524 lower_32_bits(ib->gpu_addr)); 2525 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2526 amdgpu_ring_write(ring, control); 2527 } 2528 2529 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2530 u64 seq, unsigned flags) 2531 { 2532 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2533 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2534 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2535 2536 /* RELEASE_MEM - flush caches, send int */ 2537 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2538 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2539 EOP_TC_NC_ACTION_EN) : 2540 (EOP_TCL1_ACTION_EN | 2541 EOP_TC_ACTION_EN | 2542 EOP_TC_WB_ACTION_EN | 2543 EOP_TC_MD_ACTION_EN)) | 2544 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2545 EVENT_INDEX(5))); 2546 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2547 2548 /* 2549 * the address should be Qword aligned if 64bit write, Dword 2550 * aligned if only send 32bit data low (discard data high) 2551 */ 2552 if (write64bit) 2553 BUG_ON(addr & 0x7); 2554 else 2555 BUG_ON(addr & 0x3); 2556 amdgpu_ring_write(ring, lower_32_bits(addr)); 2557 amdgpu_ring_write(ring, upper_32_bits(addr)); 2558 amdgpu_ring_write(ring, lower_32_bits(seq)); 2559 amdgpu_ring_write(ring, upper_32_bits(seq)); 2560 amdgpu_ring_write(ring, 0); 2561 } 2562 2563 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2564 { 2565 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2566 uint32_t seq = ring->fence_drv.sync_seq; 2567 uint64_t addr = ring->fence_drv.gpu_addr; 2568 2569 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2570 lower_32_bits(addr), upper_32_bits(addr), 2571 seq, 0xffffffff, 4); 2572 } 2573 2574 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2575 unsigned vmid, uint64_t pd_addr) 2576 { 2577 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2578 } 2579 2580 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2581 { 2582 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2583 } 2584 2585 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2586 { 2587 u64 wptr; 2588 2589 /* XXX check if swapping is necessary on BE */ 2590 if (ring->use_doorbell) 2591 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2592 else 2593 BUG(); 2594 return wptr; 2595 } 2596 2597 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2598 { 2599 struct amdgpu_device *adev = ring->adev; 2600 2601 /* XXX check if swapping is necessary on BE */ 2602 if (ring->use_doorbell) { 2603 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2604 WDOORBELL64(ring->doorbell_index, ring->wptr); 2605 } else { 2606 BUG(); /* only DOORBELL method supported on gfx9 now */ 2607 } 2608 } 2609 2610 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2611 u64 seq, unsigned int flags) 2612 { 2613 struct amdgpu_device *adev = ring->adev; 2614 2615 /* we only allocate 32bit for each seq wb address */ 2616 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2617 2618 /* write fence seq to the "addr" */ 2619 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2620 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2621 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2622 amdgpu_ring_write(ring, lower_32_bits(addr)); 2623 amdgpu_ring_write(ring, upper_32_bits(addr)); 2624 amdgpu_ring_write(ring, lower_32_bits(seq)); 2625 2626 if (flags & AMDGPU_FENCE_FLAG_INT) { 2627 /* set register to trigger INT */ 2628 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2629 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2630 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2631 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2632 amdgpu_ring_write(ring, 0); 2633 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2634 } 2635 } 2636 2637 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2638 uint32_t reg_val_offs) 2639 { 2640 struct amdgpu_device *adev = ring->adev; 2641 2642 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2643 amdgpu_ring_write(ring, 0 | /* src: register*/ 2644 (5 << 8) | /* dst: memory */ 2645 (1 << 20)); /* write confirm */ 2646 amdgpu_ring_write(ring, reg); 2647 amdgpu_ring_write(ring, 0); 2648 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2649 reg_val_offs * 4)); 2650 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2651 reg_val_offs * 4)); 2652 } 2653 2654 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2655 uint32_t val) 2656 { 2657 uint32_t cmd = 0; 2658 2659 switch (ring->funcs->type) { 2660 case AMDGPU_RING_TYPE_GFX: 2661 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2662 break; 2663 case AMDGPU_RING_TYPE_KIQ: 2664 cmd = (1 << 16); /* no inc addr */ 2665 break; 2666 default: 2667 cmd = WR_CONFIRM; 2668 break; 2669 } 2670 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2671 amdgpu_ring_write(ring, cmd); 2672 amdgpu_ring_write(ring, reg); 2673 amdgpu_ring_write(ring, 0); 2674 amdgpu_ring_write(ring, val); 2675 } 2676 2677 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2678 uint32_t val, uint32_t mask) 2679 { 2680 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2681 } 2682 2683 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2684 uint32_t reg0, uint32_t reg1, 2685 uint32_t ref, uint32_t mask) 2686 { 2687 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2688 ref, mask); 2689 } 2690 2691 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2692 struct amdgpu_device *adev, int me, int pipe, 2693 enum amdgpu_interrupt_state state, int xcc_id) 2694 { 2695 u32 mec_int_cntl, mec_int_cntl_reg; 2696 2697 /* 2698 * amdgpu controls only the first MEC. That's why this function only 2699 * handles the setting of interrupts for this specific MEC. All other 2700 * pipes' interrupts are set by amdkfd. 2701 */ 2702 2703 if (me == 1) { 2704 switch (pipe) { 2705 case 0: 2706 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2707 break; 2708 case 1: 2709 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2710 break; 2711 case 2: 2712 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2713 break; 2714 case 3: 2715 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2716 break; 2717 default: 2718 DRM_DEBUG("invalid pipe %d\n", pipe); 2719 return; 2720 } 2721 } else { 2722 DRM_DEBUG("invalid me %d\n", me); 2723 return; 2724 } 2725 2726 switch (state) { 2727 case AMDGPU_IRQ_STATE_DISABLE: 2728 mec_int_cntl = RREG32(mec_int_cntl_reg); 2729 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2730 TIME_STAMP_INT_ENABLE, 0); 2731 WREG32(mec_int_cntl_reg, mec_int_cntl); 2732 break; 2733 case AMDGPU_IRQ_STATE_ENABLE: 2734 mec_int_cntl = RREG32(mec_int_cntl_reg); 2735 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2736 TIME_STAMP_INT_ENABLE, 1); 2737 WREG32(mec_int_cntl_reg, mec_int_cntl); 2738 break; 2739 default: 2740 break; 2741 } 2742 } 2743 2744 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2745 struct amdgpu_irq_src *source, 2746 unsigned type, 2747 enum amdgpu_interrupt_state state) 2748 { 2749 int i, num_xcc; 2750 2751 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2752 switch (state) { 2753 case AMDGPU_IRQ_STATE_DISABLE: 2754 case AMDGPU_IRQ_STATE_ENABLE: 2755 for (i = 0; i < num_xcc; i++) 2756 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2757 PRIV_REG_INT_ENABLE, 2758 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2759 break; 2760 default: 2761 break; 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2768 struct amdgpu_irq_src *source, 2769 unsigned type, 2770 enum amdgpu_interrupt_state state) 2771 { 2772 int i, num_xcc; 2773 2774 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2775 switch (state) { 2776 case AMDGPU_IRQ_STATE_DISABLE: 2777 case AMDGPU_IRQ_STATE_ENABLE: 2778 for (i = 0; i < num_xcc; i++) 2779 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2780 PRIV_INSTR_INT_ENABLE, 2781 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2782 break; 2783 default: 2784 break; 2785 } 2786 2787 return 0; 2788 } 2789 2790 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2791 struct amdgpu_irq_src *src, 2792 unsigned type, 2793 enum amdgpu_interrupt_state state) 2794 { 2795 int i, num_xcc; 2796 2797 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2798 for (i = 0; i < num_xcc; i++) { 2799 switch (type) { 2800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2801 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2802 adev, 1, 0, state, i); 2803 break; 2804 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2805 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2806 adev, 1, 1, state, i); 2807 break; 2808 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2809 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2810 adev, 1, 2, state, i); 2811 break; 2812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2813 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2814 adev, 1, 3, state, i); 2815 break; 2816 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2817 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2818 adev, 2, 0, state, i); 2819 break; 2820 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2821 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2822 adev, 2, 1, state, i); 2823 break; 2824 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2825 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2826 adev, 2, 2, state, i); 2827 break; 2828 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2829 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2830 adev, 2, 3, state, i); 2831 break; 2832 default: 2833 break; 2834 } 2835 } 2836 2837 return 0; 2838 } 2839 2840 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2841 struct amdgpu_irq_src *source, 2842 struct amdgpu_iv_entry *entry) 2843 { 2844 int i, xcc_id; 2845 u8 me_id, pipe_id, queue_id; 2846 struct amdgpu_ring *ring; 2847 2848 DRM_DEBUG("IH: CP EOP\n"); 2849 me_id = (entry->ring_id & 0x0c) >> 2; 2850 pipe_id = (entry->ring_id & 0x03) >> 0; 2851 queue_id = (entry->ring_id & 0x70) >> 4; 2852 2853 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2854 2855 if (xcc_id == -EINVAL) 2856 return -EINVAL; 2857 2858 switch (me_id) { 2859 case 0: 2860 case 1: 2861 case 2: 2862 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2863 ring = &adev->gfx.compute_ring 2864 [i + 2865 xcc_id * adev->gfx.num_compute_rings]; 2866 /* Per-queue interrupt is supported for MEC starting from VI. 2867 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2868 */ 2869 2870 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2871 amdgpu_fence_process(ring); 2872 } 2873 break; 2874 } 2875 return 0; 2876 } 2877 2878 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2879 struct amdgpu_iv_entry *entry) 2880 { 2881 u8 me_id, pipe_id, queue_id; 2882 struct amdgpu_ring *ring; 2883 int i, xcc_id; 2884 2885 me_id = (entry->ring_id & 0x0c) >> 2; 2886 pipe_id = (entry->ring_id & 0x03) >> 0; 2887 queue_id = (entry->ring_id & 0x70) >> 4; 2888 2889 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2890 2891 if (xcc_id == -EINVAL) 2892 return; 2893 2894 switch (me_id) { 2895 case 0: 2896 case 1: 2897 case 2: 2898 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2899 ring = &adev->gfx.compute_ring 2900 [i + 2901 xcc_id * adev->gfx.num_compute_rings]; 2902 if (ring->me == me_id && ring->pipe == pipe_id && 2903 ring->queue == queue_id) 2904 drm_sched_fault(&ring->sched); 2905 } 2906 break; 2907 } 2908 } 2909 2910 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2911 struct amdgpu_irq_src *source, 2912 struct amdgpu_iv_entry *entry) 2913 { 2914 DRM_ERROR("Illegal register access in command stream\n"); 2915 gfx_v9_4_3_fault(adev, entry); 2916 return 0; 2917 } 2918 2919 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2920 struct amdgpu_irq_src *source, 2921 struct amdgpu_iv_entry *entry) 2922 { 2923 DRM_ERROR("Illegal instruction in command stream\n"); 2924 gfx_v9_4_3_fault(adev, entry); 2925 return 0; 2926 } 2927 2928 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2929 { 2930 const unsigned int cp_coher_cntl = 2931 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2932 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2933 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2934 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2935 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2936 2937 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2938 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2939 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2940 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2941 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2942 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2943 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2944 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2945 } 2946 2947 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2948 uint32_t pipe, bool enable) 2949 { 2950 struct amdgpu_device *adev = ring->adev; 2951 uint32_t val; 2952 uint32_t wcl_cs_reg; 2953 2954 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2955 val = enable ? 0x1 : 0x7f; 2956 2957 switch (pipe) { 2958 case 0: 2959 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2960 break; 2961 case 1: 2962 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2963 break; 2964 case 2: 2965 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2966 break; 2967 case 3: 2968 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2969 break; 2970 default: 2971 DRM_DEBUG("invalid pipe %d\n", pipe); 2972 return; 2973 } 2974 2975 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2976 2977 } 2978 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2979 { 2980 struct amdgpu_device *adev = ring->adev; 2981 uint32_t val; 2982 int i; 2983 2984 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2985 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2986 * around 25% of gpu resources. 2987 */ 2988 val = enable ? 0x1f : 0x07ffffff; 2989 amdgpu_ring_emit_wreg(ring, 2990 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 2991 val); 2992 2993 /* Restrict waves for normal/low priority compute queues as well 2994 * to get best QoS for high priority compute jobs. 2995 * 2996 * amdgpu controls only 1st ME(0-3 CS pipes). 2997 */ 2998 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2999 if (i != ring->pipe) 3000 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3001 3002 } 3003 } 3004 3005 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 3006 .name = "gfx_v9_4_3", 3007 .early_init = gfx_v9_4_3_early_init, 3008 .late_init = gfx_v9_4_3_late_init, 3009 .sw_init = gfx_v9_4_3_sw_init, 3010 .sw_fini = gfx_v9_4_3_sw_fini, 3011 .hw_init = gfx_v9_4_3_hw_init, 3012 .hw_fini = gfx_v9_4_3_hw_fini, 3013 .suspend = gfx_v9_4_3_suspend, 3014 .resume = gfx_v9_4_3_resume, 3015 .is_idle = gfx_v9_4_3_is_idle, 3016 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 3017 .soft_reset = gfx_v9_4_3_soft_reset, 3018 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 3019 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 3020 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 3021 }; 3022 3023 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 3024 .type = AMDGPU_RING_TYPE_COMPUTE, 3025 .align_mask = 0xff, 3026 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3027 .support_64bit_ptrs = true, 3028 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 3029 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 3030 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 3031 .emit_frame_size = 3032 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 3033 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 3034 5 + /* hdp invalidate */ 3035 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 3036 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3037 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3038 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 3039 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 3040 7 + /* gfx_v9_4_3_emit_mem_sync */ 3041 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 3042 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 3043 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 3044 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 3045 .emit_fence = gfx_v9_4_3_ring_emit_fence, 3046 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 3047 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 3048 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 3049 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 3050 .test_ring = gfx_v9_4_3_ring_test_ring, 3051 .test_ib = gfx_v9_4_3_ring_test_ib, 3052 .insert_nop = amdgpu_ring_insert_nop, 3053 .pad_ib = amdgpu_ring_generic_pad_ib, 3054 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 3055 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 3056 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 3057 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 3058 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 3059 }; 3060 3061 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 3062 .type = AMDGPU_RING_TYPE_KIQ, 3063 .align_mask = 0xff, 3064 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3065 .support_64bit_ptrs = true, 3066 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 3067 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 3068 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 3069 .emit_frame_size = 3070 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 3071 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 3072 5 + /* hdp invalidate */ 3073 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 3074 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3075 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3076 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 3077 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 3078 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 3079 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 3080 .test_ring = gfx_v9_4_3_ring_test_ring, 3081 .insert_nop = amdgpu_ring_insert_nop, 3082 .pad_ib = amdgpu_ring_generic_pad_ib, 3083 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 3084 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 3085 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 3086 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 3087 }; 3088 3089 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 3090 { 3091 int i, j, num_xcc; 3092 3093 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3094 for (i = 0; i < num_xcc; i++) { 3095 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 3096 3097 for (j = 0; j < adev->gfx.num_compute_rings; j++) 3098 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 3099 = &gfx_v9_4_3_ring_funcs_compute; 3100 } 3101 } 3102 3103 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 3104 .set = gfx_v9_4_3_set_eop_interrupt_state, 3105 .process = gfx_v9_4_3_eop_irq, 3106 }; 3107 3108 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 3109 .set = gfx_v9_4_3_set_priv_reg_fault_state, 3110 .process = gfx_v9_4_3_priv_reg_irq, 3111 }; 3112 3113 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 3114 .set = gfx_v9_4_3_set_priv_inst_fault_state, 3115 .process = gfx_v9_4_3_priv_inst_irq, 3116 }; 3117 3118 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 3119 { 3120 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3121 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 3122 3123 adev->gfx.priv_reg_irq.num_types = 1; 3124 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 3125 3126 adev->gfx.priv_inst_irq.num_types = 1; 3127 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 3128 } 3129 3130 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 3131 { 3132 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 3133 } 3134 3135 3136 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 3137 { 3138 /* init asci gds info */ 3139 switch (adev->ip_versions[GC_HWIP][0]) { 3140 case IP_VERSION(9, 4, 3): 3141 /* 9.4.3 removed all the GDS internal memory, 3142 * only support GWS opcode in kernel, like barrier 3143 * semaphore.etc */ 3144 adev->gds.gds_size = 0; 3145 break; 3146 default: 3147 adev->gds.gds_size = 0x10000; 3148 break; 3149 } 3150 3151 switch (adev->ip_versions[GC_HWIP][0]) { 3152 case IP_VERSION(9, 4, 3): 3153 /* deprecated for 9.4.3, no usage at all */ 3154 adev->gds.gds_compute_max_wave_id = 0; 3155 break; 3156 default: 3157 /* this really depends on the chip */ 3158 adev->gds.gds_compute_max_wave_id = 0x7ff; 3159 break; 3160 } 3161 3162 adev->gds.gws_size = 64; 3163 adev->gds.oa_size = 16; 3164 } 3165 3166 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3167 u32 bitmap) 3168 { 3169 u32 data; 3170 3171 if (!bitmap) 3172 return; 3173 3174 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3175 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3176 3177 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 3178 } 3179 3180 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 3181 { 3182 u32 data, mask; 3183 3184 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 3185 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 3186 3187 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3188 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3189 3190 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3191 3192 return (~data) & mask; 3193 } 3194 3195 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 3196 struct amdgpu_cu_info *cu_info) 3197 { 3198 int i, j, k, counter, active_cu_number = 0; 3199 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3200 unsigned disable_masks[4 * 4]; 3201 3202 if (!adev || !cu_info) 3203 return -EINVAL; 3204 3205 /* 3206 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 3207 */ 3208 if (adev->gfx.config.max_shader_engines * 3209 adev->gfx.config.max_sh_per_se > 16) 3210 return -EINVAL; 3211 3212 amdgpu_gfx_parse_disable_cu(disable_masks, 3213 adev->gfx.config.max_shader_engines, 3214 adev->gfx.config.max_sh_per_se); 3215 3216 mutex_lock(&adev->grbm_idx_mutex); 3217 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3218 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3219 mask = 1; 3220 ao_bitmap = 0; 3221 counter = 0; 3222 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 3223 gfx_v9_4_3_set_user_cu_inactive_bitmap( 3224 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 3225 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 3226 3227 /* 3228 * The bitmap(and ao_cu_bitmap) in cu_info structure is 3229 * 4x4 size array, and it's usually suitable for Vega 3230 * ASICs which has 4*2 SE/SH layout. 3231 * But for Arcturus, SE/SH layout is changed to 8*1. 3232 * To mostly reduce the impact, we make it compatible 3233 * with current bitmap array as below: 3234 * SE4,SH0 --> bitmap[0][1] 3235 * SE5,SH0 --> bitmap[1][1] 3236 * SE6,SH0 --> bitmap[2][1] 3237 * SE7,SH0 --> bitmap[3][1] 3238 */ 3239 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 3240 3241 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3242 if (bitmap & mask) { 3243 if (counter < adev->gfx.config.max_cu_per_sh) 3244 ao_bitmap |= mask; 3245 counter++; 3246 } 3247 mask <<= 1; 3248 } 3249 active_cu_number += counter; 3250 if (i < 2 && j < 2) 3251 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3252 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 3253 } 3254 } 3255 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3256 0); 3257 mutex_unlock(&adev->grbm_idx_mutex); 3258 3259 cu_info->number = active_cu_number; 3260 cu_info->ao_cu_mask = ao_cu_mask; 3261 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 3262 3263 return 0; 3264 } 3265 3266 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 3267 .type = AMD_IP_BLOCK_TYPE_GFX, 3268 .major = 9, 3269 .minor = 4, 3270 .rev = 0, 3271 .funcs = &gfx_v9_4_3_ip_funcs, 3272 }; 3273 3274 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 3275 { 3276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3277 uint32_t tmp_mask; 3278 int i, r; 3279 3280 /* TODO : Initialize golden regs */ 3281 /* gfx_v9_4_3_init_golden_registers(adev); */ 3282 3283 tmp_mask = inst_mask; 3284 for_each_inst(i, tmp_mask) 3285 gfx_v9_4_3_xcc_constants_init(adev, i); 3286 3287 tmp_mask = inst_mask; 3288 for_each_inst(i, tmp_mask) { 3289 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 3290 if (r) 3291 return r; 3292 } 3293 3294 tmp_mask = inst_mask; 3295 for_each_inst(i, tmp_mask) { 3296 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 3297 if (r) 3298 return r; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 3305 { 3306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3307 int i; 3308 3309 for_each_inst(i, inst_mask) 3310 gfx_v9_4_3_xcc_fini(adev, i); 3311 3312 return 0; 3313 } 3314 3315 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 3316 .suspend = &gfx_v9_4_3_xcp_suspend, 3317 .resume = &gfx_v9_4_3_xcp_resume 3318 }; 3319