1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 50 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 51 52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 57 struct amdgpu_cu_info *cu_info); 58 59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 60 uint64_t queue_mask) 61 { 62 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 63 amdgpu_ring_write(kiq_ring, 64 PACKET3_SET_RESOURCES_VMID_MASK(0) | 65 /* vmid_mask:0* queue_type:0 (KIQ) */ 66 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 67 amdgpu_ring_write(kiq_ring, 68 lower_32_bits(queue_mask)); /* queue mask lo */ 69 amdgpu_ring_write(kiq_ring, 70 upper_32_bits(queue_mask)); /* queue mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 73 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 74 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 75 } 76 77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring) 79 { 80 struct amdgpu_device *adev = kiq_ring->adev; 81 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 82 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 83 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 84 85 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 86 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 87 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 88 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 89 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 90 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 91 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 92 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 93 /*queue_type: normal compute queue */ 94 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 95 /* alloc format: all_on_one_pipe */ 96 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 97 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 98 /* num_queues: must be 1 */ 99 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 100 amdgpu_ring_write(kiq_ring, 101 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 105 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 106 } 107 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 109 struct amdgpu_ring *ring, 110 enum amdgpu_unmap_queues_action action, 111 u64 gpu_addr, u64 seq) 112 { 113 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 114 115 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 116 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 117 PACKET3_UNMAP_QUEUES_ACTION(action) | 118 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 119 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 120 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 121 amdgpu_ring_write(kiq_ring, 122 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 123 124 if (action == PREEMPT_QUEUES_NO_UNMAP) { 125 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 126 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, seq); 128 } else { 129 amdgpu_ring_write(kiq_ring, 0); 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 } 133 } 134 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 u64 addr, 138 u64 seq) 139 { 140 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 141 142 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 143 amdgpu_ring_write(kiq_ring, 144 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 145 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 146 PACKET3_QUERY_STATUS_COMMAND(2)); 147 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 148 amdgpu_ring_write(kiq_ring, 149 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 150 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 155 } 156 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 158 uint16_t pasid, uint32_t flush_type, 159 bool all_hub) 160 { 161 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 162 amdgpu_ring_write(kiq_ring, 163 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 164 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 165 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 166 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 167 } 168 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 170 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 171 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 172 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 173 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 174 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 175 .set_resources_size = 8, 176 .map_queues_size = 7, 177 .unmap_queues_size = 6, 178 .query_status_size = 7, 179 .invalidate_tlbs_size = 2, 180 }; 181 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 183 { 184 int i, num_xcc; 185 186 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 187 for (i = 0; i < num_xcc; i++) 188 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 189 } 190 191 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 192 { 193 int i, num_xcc, dev_inst; 194 195 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 196 for (i = 0; i < num_xcc; i++) { 197 dev_inst = GET_INST(GC, i); 198 if (dev_inst >= 2) 199 WREG32_SOC15(GC, dev_inst, regGRBM_MCM_ADDR, 0x4); 200 201 /* Golden settings applied by driver for ASIC with rev_id 0 */ 202 if (adev->rev_id == 0) { 203 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 204 GOLDEN_GB_ADDR_CONFIG); 205 206 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 207 REDUCE_FIFO_DEPTH_BY_2, 2); 208 } 209 } 210 } 211 212 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 213 bool wc, uint32_t reg, uint32_t val) 214 { 215 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 216 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 217 WRITE_DATA_DST_SEL(0) | 218 (wc ? WR_CONFIRM : 0)); 219 amdgpu_ring_write(ring, reg); 220 amdgpu_ring_write(ring, 0); 221 amdgpu_ring_write(ring, val); 222 } 223 224 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 225 int mem_space, int opt, uint32_t addr0, 226 uint32_t addr1, uint32_t ref, uint32_t mask, 227 uint32_t inv) 228 { 229 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 230 amdgpu_ring_write(ring, 231 /* memory (1) or register (0) */ 232 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 233 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 234 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 235 WAIT_REG_MEM_ENGINE(eng_sel))); 236 237 if (mem_space) 238 BUG_ON(addr0 & 0x3); /* Dword align */ 239 amdgpu_ring_write(ring, addr0); 240 amdgpu_ring_write(ring, addr1); 241 amdgpu_ring_write(ring, ref); 242 amdgpu_ring_write(ring, mask); 243 amdgpu_ring_write(ring, inv); /* poll interval */ 244 } 245 246 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 247 { 248 uint32_t scratch_reg0_offset, xcc_offset; 249 struct amdgpu_device *adev = ring->adev; 250 uint32_t tmp = 0; 251 unsigned i; 252 int r; 253 254 /* Use register offset which is local to XCC in the packet */ 255 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 256 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 257 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 258 259 r = amdgpu_ring_alloc(ring, 3); 260 if (r) 261 return r; 262 263 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 264 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 265 amdgpu_ring_write(ring, 0xDEADBEEF); 266 amdgpu_ring_commit(ring); 267 268 for (i = 0; i < adev->usec_timeout; i++) { 269 tmp = RREG32(scratch_reg0_offset); 270 if (tmp == 0xDEADBEEF) 271 break; 272 udelay(1); 273 } 274 275 if (i >= adev->usec_timeout) 276 r = -ETIMEDOUT; 277 return r; 278 } 279 280 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 281 { 282 struct amdgpu_device *adev = ring->adev; 283 struct amdgpu_ib ib; 284 struct dma_fence *f = NULL; 285 286 unsigned index; 287 uint64_t gpu_addr; 288 uint32_t tmp; 289 long r; 290 291 r = amdgpu_device_wb_get(adev, &index); 292 if (r) 293 return r; 294 295 gpu_addr = adev->wb.gpu_addr + (index * 4); 296 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 297 memset(&ib, 0, sizeof(ib)); 298 r = amdgpu_ib_get(adev, NULL, 16, 299 AMDGPU_IB_POOL_DIRECT, &ib); 300 if (r) 301 goto err1; 302 303 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 304 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 305 ib.ptr[2] = lower_32_bits(gpu_addr); 306 ib.ptr[3] = upper_32_bits(gpu_addr); 307 ib.ptr[4] = 0xDEADBEEF; 308 ib.length_dw = 5; 309 310 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 311 if (r) 312 goto err2; 313 314 r = dma_fence_wait_timeout(f, false, timeout); 315 if (r == 0) { 316 r = -ETIMEDOUT; 317 goto err2; 318 } else if (r < 0) { 319 goto err2; 320 } 321 322 tmp = adev->wb.wb[index]; 323 if (tmp == 0xDEADBEEF) 324 r = 0; 325 else 326 r = -EINVAL; 327 328 err2: 329 amdgpu_ib_free(adev, &ib, NULL); 330 dma_fence_put(f); 331 err1: 332 amdgpu_device_wb_free(adev, index); 333 return r; 334 } 335 336 337 /* This value might differs per partition */ 338 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 339 { 340 uint64_t clock; 341 342 amdgpu_gfx_off_ctrl(adev, false); 343 mutex_lock(&adev->gfx.gpu_clock_mutex); 344 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 345 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 346 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 347 mutex_unlock(&adev->gfx.gpu_clock_mutex); 348 amdgpu_gfx_off_ctrl(adev, true); 349 350 return clock; 351 } 352 353 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 354 { 355 amdgpu_ucode_release(&adev->gfx.pfp_fw); 356 amdgpu_ucode_release(&adev->gfx.me_fw); 357 amdgpu_ucode_release(&adev->gfx.ce_fw); 358 amdgpu_ucode_release(&adev->gfx.rlc_fw); 359 amdgpu_ucode_release(&adev->gfx.mec_fw); 360 amdgpu_ucode_release(&adev->gfx.mec2_fw); 361 362 kfree(adev->gfx.rlc.register_list_format); 363 } 364 365 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 366 const char *chip_name) 367 { 368 char fw_name[30]; 369 int err; 370 const struct rlc_firmware_header_v2_0 *rlc_hdr; 371 uint16_t version_major; 372 uint16_t version_minor; 373 374 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 375 376 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 377 if (err) 378 goto out; 379 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 380 381 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 382 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 383 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 384 out: 385 if (err) 386 amdgpu_ucode_release(&adev->gfx.rlc_fw); 387 388 return err; 389 } 390 391 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 392 { 393 return true; 394 } 395 396 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 397 { 398 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 399 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 400 } 401 402 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 403 const char *chip_name) 404 { 405 char fw_name[30]; 406 int err; 407 408 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 409 410 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 411 if (err) 412 goto out; 413 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 414 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 415 416 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 417 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 418 419 gfx_v9_4_3_check_if_need_gfxoff(adev); 420 421 out: 422 if (err) 423 amdgpu_ucode_release(&adev->gfx.mec_fw); 424 return err; 425 } 426 427 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 428 { 429 const char *chip_name; 430 int r; 431 432 chip_name = "gc_9_4_3"; 433 434 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 435 if (r) 436 return r; 437 438 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 439 if (r) 440 return r; 441 442 return r; 443 } 444 445 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 446 { 447 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 448 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 449 } 450 451 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 452 { 453 int r, i, num_xcc; 454 u32 *hpd; 455 const __le32 *fw_data; 456 unsigned fw_size; 457 u32 *fw; 458 size_t mec_hpd_size; 459 460 const struct gfx_firmware_header_v1_0 *mec_hdr; 461 462 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 463 for (i = 0; i < num_xcc; i++) 464 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 465 AMDGPU_MAX_COMPUTE_QUEUES); 466 467 /* take ownership of the relevant compute queues */ 468 amdgpu_gfx_compute_queue_acquire(adev); 469 mec_hpd_size = 470 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 471 if (mec_hpd_size) { 472 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 473 AMDGPU_GEM_DOMAIN_VRAM | 474 AMDGPU_GEM_DOMAIN_GTT, 475 &adev->gfx.mec.hpd_eop_obj, 476 &adev->gfx.mec.hpd_eop_gpu_addr, 477 (void **)&hpd); 478 if (r) { 479 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 480 gfx_v9_4_3_mec_fini(adev); 481 return r; 482 } 483 484 if (amdgpu_emu_mode == 1) { 485 for (i = 0; i < mec_hpd_size / 4; i++) { 486 memset((void *)(hpd + i), 0, 4); 487 if (i % 50 == 0) 488 msleep(1); 489 } 490 } else { 491 memset(hpd, 0, mec_hpd_size); 492 } 493 494 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 495 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 496 } 497 498 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 499 500 fw_data = (const __le32 *) 501 (adev->gfx.mec_fw->data + 502 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 503 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 504 505 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 507 &adev->gfx.mec.mec_fw_obj, 508 &adev->gfx.mec.mec_fw_gpu_addr, 509 (void **)&fw); 510 if (r) { 511 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 512 gfx_v9_4_3_mec_fini(adev); 513 return r; 514 } 515 516 memcpy(fw, fw_data, fw_size); 517 518 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 519 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 520 521 return 0; 522 } 523 524 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 525 u32 sh_num, u32 instance, int xcc_id) 526 { 527 u32 data; 528 529 if (instance == 0xffffffff) 530 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 531 INSTANCE_BROADCAST_WRITES, 1); 532 else 533 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 534 INSTANCE_INDEX, instance); 535 536 if (se_num == 0xffffffff) 537 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 538 SE_BROADCAST_WRITES, 1); 539 else 540 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 541 542 if (sh_num == 0xffffffff) 543 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 544 SH_BROADCAST_WRITES, 1); 545 else 546 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 547 548 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 549 } 550 551 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 552 { 553 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 554 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 555 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 556 (address << SQ_IND_INDEX__INDEX__SHIFT) | 557 (SQ_IND_INDEX__FORCE_READ_MASK)); 558 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 559 } 560 561 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 562 uint32_t wave, uint32_t thread, 563 uint32_t regno, uint32_t num, uint32_t *out) 564 { 565 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 566 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 567 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 568 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 569 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 570 (SQ_IND_INDEX__FORCE_READ_MASK) | 571 (SQ_IND_INDEX__AUTO_INCR_MASK)); 572 while (num--) 573 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 574 } 575 576 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 577 uint32_t xcc_id, uint32_t simd, uint32_t wave, 578 uint32_t *dst, int *no_fields) 579 { 580 /* type 1 wave data */ 581 dst[(*no_fields)++] = 1; 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 596 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 597 } 598 599 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 600 uint32_t wave, uint32_t start, 601 uint32_t size, uint32_t *dst) 602 { 603 wave_read_regs(adev, xcc_id, simd, wave, 0, 604 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 605 } 606 607 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 608 uint32_t wave, uint32_t thread, 609 uint32_t start, uint32_t size, 610 uint32_t *dst) 611 { 612 wave_read_regs(adev, xcc_id, simd, wave, thread, 613 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 614 } 615 616 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 617 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 618 { 619 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 620 } 621 622 623 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 624 int num_xccs_per_xcp) 625 { 626 int i, num_xcc; 627 u32 tmp = 0; 628 629 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 630 631 for (i = 0; i < num_xcc; i++) { 632 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 633 num_xccs_per_xcp); 634 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 635 i % num_xccs_per_xcp); 636 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, tmp); 637 } 638 639 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 640 641 return 0; 642 } 643 644 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 645 { 646 int xcc; 647 648 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 649 if (!xcc) { 650 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 651 return -EINVAL; 652 } 653 654 return xcc - 1; 655 } 656 657 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 658 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 659 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 660 .read_wave_data = &gfx_v9_4_3_read_wave_data, 661 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 662 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 663 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 664 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 665 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 666 }; 667 668 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 669 { 670 u32 gb_addr_config; 671 672 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 673 adev->gfx.ras = &gfx_v9_4_3_ras; 674 675 switch (adev->ip_versions[GC_HWIP][0]) { 676 case IP_VERSION(9, 4, 3): 677 adev->gfx.config.max_hw_contexts = 8; 678 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 679 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 680 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 681 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 682 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 683 break; 684 default: 685 BUG(); 686 break; 687 } 688 689 adev->gfx.config.gb_addr_config = gb_addr_config; 690 691 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 692 REG_GET_FIELD( 693 adev->gfx.config.gb_addr_config, 694 GB_ADDR_CONFIG, 695 NUM_PIPES); 696 697 adev->gfx.config.max_tile_pipes = 698 adev->gfx.config.gb_addr_config_fields.num_pipes; 699 700 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 701 REG_GET_FIELD( 702 adev->gfx.config.gb_addr_config, 703 GB_ADDR_CONFIG, 704 NUM_BANKS); 705 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 706 REG_GET_FIELD( 707 adev->gfx.config.gb_addr_config, 708 GB_ADDR_CONFIG, 709 MAX_COMPRESSED_FRAGS); 710 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 711 REG_GET_FIELD( 712 adev->gfx.config.gb_addr_config, 713 GB_ADDR_CONFIG, 714 NUM_RB_PER_SE); 715 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 716 REG_GET_FIELD( 717 adev->gfx.config.gb_addr_config, 718 GB_ADDR_CONFIG, 719 NUM_SHADER_ENGINES); 720 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 721 REG_GET_FIELD( 722 adev->gfx.config.gb_addr_config, 723 GB_ADDR_CONFIG, 724 PIPE_INTERLEAVE_SIZE)); 725 726 return 0; 727 } 728 729 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 730 int xcc_id, int mec, int pipe, int queue) 731 { 732 unsigned irq_type; 733 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 734 unsigned int hw_prio; 735 uint32_t xcc_doorbell_start; 736 737 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 738 ring_id]; 739 740 /* mec0 is me1 */ 741 ring->xcc_id = xcc_id; 742 ring->me = mec + 1; 743 ring->pipe = pipe; 744 ring->queue = queue; 745 746 ring->ring_obj = NULL; 747 ring->use_doorbell = true; 748 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 749 xcc_id * adev->doorbell_index.xcc_doorbell_range; 750 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 751 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 752 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 753 GFX9_MEC_HPD_SIZE; 754 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 755 sprintf(ring->name, "comp_%d.%d.%d.%d", 756 ring->xcc_id, ring->me, ring->pipe, ring->queue); 757 758 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 759 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 760 + ring->pipe; 761 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 762 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 763 /* type-2 packets are deprecated on MEC, use type-3 instead */ 764 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 765 hw_prio, NULL); 766 } 767 768 static int gfx_v9_4_3_sw_init(void *handle) 769 { 770 int i, j, k, r, ring_id, xcc_id, num_xcc; 771 struct amdgpu_kiq *kiq; 772 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 773 774 adev->gfx.mec.num_mec = 2; 775 adev->gfx.mec.num_pipe_per_mec = 4; 776 adev->gfx.mec.num_queue_per_pipe = 8; 777 778 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 779 780 /* EOP Event */ 781 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 782 if (r) 783 return r; 784 785 /* Privileged reg */ 786 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 787 &adev->gfx.priv_reg_irq); 788 if (r) 789 return r; 790 791 /* Privileged inst */ 792 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 793 &adev->gfx.priv_inst_irq); 794 if (r) 795 return r; 796 797 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 798 799 r = adev->gfx.rlc.funcs->init(adev); 800 if (r) { 801 DRM_ERROR("Failed to init rlc BOs!\n"); 802 return r; 803 } 804 805 r = gfx_v9_4_3_mec_init(adev); 806 if (r) { 807 DRM_ERROR("Failed to init MEC BOs!\n"); 808 return r; 809 } 810 811 /* set up the compute queues - allocate horizontally across pipes */ 812 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 813 ring_id = 0; 814 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 815 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 816 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 817 k++) { 818 if (!amdgpu_gfx_is_mec_queue_enabled( 819 adev, xcc_id, i, k, j)) 820 continue; 821 822 r = gfx_v9_4_3_compute_ring_init(adev, 823 ring_id, 824 xcc_id, 825 i, k, j); 826 if (r) 827 return r; 828 829 ring_id++; 830 } 831 } 832 } 833 834 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 835 if (r) { 836 DRM_ERROR("Failed to init KIQ BOs!\n"); 837 return r; 838 } 839 840 kiq = &adev->gfx.kiq[xcc_id]; 841 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 842 if (r) 843 return r; 844 845 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 846 r = amdgpu_gfx_mqd_sw_init(adev, 847 sizeof(struct v9_mqd_allocation), xcc_id); 848 if (r) 849 return r; 850 } 851 852 r = gfx_v9_4_3_gpu_early_init(adev); 853 if (r) 854 return r; 855 856 r = amdgpu_gfx_sysfs_init(adev); 857 if (r) 858 return r; 859 860 return amdgpu_gfx_ras_sw_init(adev); 861 } 862 863 static int gfx_v9_4_3_sw_fini(void *handle) 864 { 865 int i, num_xcc; 866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 867 868 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 869 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 870 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 871 872 for (i = 0; i < num_xcc; i++) { 873 amdgpu_gfx_mqd_sw_fini(adev, i); 874 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 875 amdgpu_gfx_kiq_fini(adev, i); 876 } 877 878 gfx_v9_4_3_mec_fini(adev); 879 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 880 gfx_v9_4_3_free_microcode(adev); 881 amdgpu_gfx_sysfs_fini(adev); 882 883 return 0; 884 } 885 886 #define DEFAULT_SH_MEM_BASES (0x6000) 887 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 888 int xcc_id) 889 { 890 int i; 891 uint32_t sh_mem_config; 892 uint32_t sh_mem_bases; 893 894 /* 895 * Configure apertures: 896 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 897 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 898 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 899 */ 900 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 901 902 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 903 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 904 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 905 906 mutex_lock(&adev->srbm_mutex); 907 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 908 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 909 /* CP and shaders */ 910 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 911 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 912 } 913 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 914 mutex_unlock(&adev->srbm_mutex); 915 916 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 917 acccess. These should be enabled by FW for target VMIDs. */ 918 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 919 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 920 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 921 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 922 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 923 } 924 } 925 926 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 927 { 928 int vmid; 929 930 /* 931 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 932 * access. Compute VMIDs should be enabled by FW for target VMIDs, 933 * the driver can enable them for graphics. VMID0 should maintain 934 * access so that HWS firmware can save/restore entries. 935 */ 936 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 937 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 938 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 939 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 940 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 941 } 942 } 943 944 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 945 int xcc_id) 946 { 947 u32 tmp; 948 int i; 949 950 /* XXX SH_MEM regs */ 951 /* where to put LDS, scratch, GPUVM in FSA64 space */ 952 mutex_lock(&adev->srbm_mutex); 953 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 954 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 955 /* CP and shaders */ 956 if (i == 0) { 957 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 958 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 959 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 960 !!adev->gmc.noretry); 961 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 962 regSH_MEM_CONFIG, tmp); 963 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 964 regSH_MEM_BASES, 0); 965 } else { 966 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 967 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 968 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 969 !!adev->gmc.noretry); 970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 971 regSH_MEM_CONFIG, tmp); 972 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 973 (adev->gmc.private_aperture_start >> 974 48)); 975 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 976 (adev->gmc.shared_aperture_start >> 977 48)); 978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 979 regSH_MEM_BASES, tmp); 980 } 981 } 982 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 983 984 mutex_unlock(&adev->srbm_mutex); 985 986 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 987 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 988 } 989 990 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 991 { 992 int i, num_xcc; 993 994 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 995 996 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 997 adev->gfx.config.db_debug2 = 998 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 999 1000 for (i = 0; i < num_xcc; i++) 1001 gfx_v9_4_3_xcc_constants_init(adev, i); 1002 } 1003 1004 static void 1005 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1006 int xcc_id) 1007 { 1008 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1009 } 1010 1011 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1012 { 1013 /* 1014 * Rlc save restore list is workable since v2_1. 1015 * And it's needed by gfxoff feature. 1016 */ 1017 if (adev->gfx.rlc.is_rlc_v2_1) 1018 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1019 } 1020 1021 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1022 { 1023 uint32_t data; 1024 1025 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1026 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1027 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1028 } 1029 1030 static void gfx_v9_4_3_xcc_program_xcc_id(struct amdgpu_device *adev, 1031 int xcc_id) 1032 { 1033 uint32_t tmp = 0; 1034 int num_xcc; 1035 1036 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1037 switch (num_xcc) { 1038 /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ 1039 case 1: 1040 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, 0x8); 1041 break; 1042 case 2: 1043 case 4: 1044 case 6: 1045 case 8: 1046 tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); 1047 tmp = tmp | (adev->gfx.num_xcc_per_xcp << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); 1048 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HYP_XCP_CTL, tmp); 1049 1050 break; 1051 default: 1052 break; 1053 } 1054 } 1055 1056 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1057 { 1058 uint32_t rlc_setting; 1059 1060 /* if RLC is not enabled, do nothing */ 1061 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1062 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1063 return false; 1064 1065 return true; 1066 } 1067 1068 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1069 { 1070 uint32_t data; 1071 unsigned i; 1072 1073 data = RLC_SAFE_MODE__CMD_MASK; 1074 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1075 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1076 1077 /* wait for RLC_SAFE_MODE */ 1078 for (i = 0; i < adev->usec_timeout; i++) { 1079 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1080 break; 1081 udelay(1); 1082 } 1083 } 1084 1085 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1086 int xcc_id) 1087 { 1088 uint32_t data; 1089 1090 data = RLC_SAFE_MODE__CMD_MASK; 1091 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1092 } 1093 1094 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1095 { 1096 /* init spm vmid with 0xf */ 1097 if (adev->gfx.rlc.funcs->update_spm_vmid) 1098 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1099 1100 return 0; 1101 } 1102 1103 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1104 int xcc_id) 1105 { 1106 u32 i, j, k; 1107 u32 mask; 1108 1109 mutex_lock(&adev->grbm_idx_mutex); 1110 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1111 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1112 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1113 xcc_id); 1114 for (k = 0; k < adev->usec_timeout; k++) { 1115 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1116 break; 1117 udelay(1); 1118 } 1119 if (k == adev->usec_timeout) { 1120 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1121 0xffffffff, 1122 0xffffffff, xcc_id); 1123 mutex_unlock(&adev->grbm_idx_mutex); 1124 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1125 i, j); 1126 return; 1127 } 1128 } 1129 } 1130 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1131 xcc_id); 1132 mutex_unlock(&adev->grbm_idx_mutex); 1133 1134 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1135 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1136 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1137 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1138 for (k = 0; k < adev->usec_timeout; k++) { 1139 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1140 break; 1141 udelay(1); 1142 } 1143 } 1144 1145 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1146 bool enable, int xcc_id) 1147 { 1148 u32 tmp; 1149 1150 /* These interrupts should be enabled to drive DS clock */ 1151 1152 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1153 1154 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1155 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1156 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1157 1158 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1159 } 1160 1161 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1162 { 1163 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1164 RLC_ENABLE_F32, 0); 1165 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1166 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1167 } 1168 1169 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1170 { 1171 int i, num_xcc; 1172 1173 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1174 for (i = 0; i < num_xcc; i++) 1175 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1176 } 1177 1178 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1179 { 1180 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1181 SOFT_RESET_RLC, 1); 1182 udelay(50); 1183 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1184 SOFT_RESET_RLC, 0); 1185 udelay(50); 1186 } 1187 1188 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1189 { 1190 int i, num_xcc; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (i = 0; i < num_xcc; i++) 1194 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1195 } 1196 1197 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1198 { 1199 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1200 RLC_ENABLE_F32, 1); 1201 udelay(50); 1202 1203 /* carrizo do enable cp interrupt after cp inited */ 1204 if (!(adev->flags & AMD_IS_APU)) { 1205 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1206 udelay(50); 1207 } 1208 } 1209 1210 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1211 { 1212 #ifdef AMDGPU_RLC_DEBUG_RETRY 1213 u32 rlc_ucode_ver; 1214 #endif 1215 int i, num_xcc; 1216 1217 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1218 for (i = 0; i < num_xcc; i++) { 1219 gfx_v9_4_3_xcc_rlc_start(adev, i); 1220 #ifdef AMDGPU_RLC_DEBUG_RETRY 1221 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1222 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1223 if (rlc_ucode_ver == 0x108) { 1224 dev_info(adev->dev, 1225 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1226 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1227 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1228 * default is 0x9C4 to create a 100us interval */ 1229 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1230 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1231 * to disable the page fault retry interrupts, default is 1232 * 0x100 (256) */ 1233 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1234 } 1235 #endif 1236 } 1237 } 1238 1239 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1240 int xcc_id) 1241 { 1242 const struct rlc_firmware_header_v2_0 *hdr; 1243 const __le32 *fw_data; 1244 unsigned i, fw_size; 1245 1246 if (!adev->gfx.rlc_fw) 1247 return -EINVAL; 1248 1249 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1250 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1251 1252 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1253 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1254 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1255 1256 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1257 RLCG_UCODE_LOADING_START_ADDRESS); 1258 for (i = 0; i < fw_size; i++) { 1259 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1260 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1261 msleep(1); 1262 } 1263 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1264 } 1265 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1266 1267 return 0; 1268 } 1269 1270 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1271 { 1272 int r; 1273 1274 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1275 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1276 /* legacy rlc firmware loading */ 1277 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1278 if (r) 1279 return r; 1280 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1281 } 1282 1283 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1284 /* disable CG */ 1285 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1286 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1287 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1288 1289 return 0; 1290 } 1291 1292 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1293 { 1294 int r, i, num_xcc; 1295 1296 if (amdgpu_sriov_vf(adev)) 1297 return 0; 1298 1299 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1300 for (i = 0; i < num_xcc; i++) { 1301 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1302 if (r) 1303 return r; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1310 unsigned vmid) 1311 { 1312 u32 reg, data; 1313 1314 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1315 if (amdgpu_sriov_is_pp_one_vf(adev)) 1316 data = RREG32_NO_KIQ(reg); 1317 else 1318 data = RREG32(reg); 1319 1320 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1321 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1322 1323 if (amdgpu_sriov_is_pp_one_vf(adev)) 1324 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1325 else 1326 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1327 } 1328 1329 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1330 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1331 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1332 }; 1333 1334 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1335 uint32_t offset, 1336 struct soc15_reg_rlcg *entries, int arr_size) 1337 { 1338 int i, inst; 1339 uint32_t reg; 1340 1341 if (!entries) 1342 return false; 1343 1344 for (i = 0; i < arr_size; i++) { 1345 const struct soc15_reg_rlcg *entry; 1346 1347 entry = &entries[i]; 1348 inst = adev->ip_map.logical_to_dev_inst ? 1349 adev->ip_map.logical_to_dev_inst( 1350 adev, entry->hwip, entry->instance) : 1351 entry->instance; 1352 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1353 entry->reg; 1354 if (offset == reg) 1355 return true; 1356 } 1357 1358 return false; 1359 } 1360 1361 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1362 { 1363 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1364 (void *)rlcg_access_gc_9_4_3, 1365 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1366 } 1367 1368 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1369 bool enable, int xcc_id) 1370 { 1371 if (enable) { 1372 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1373 } else { 1374 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1375 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1376 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1377 } 1378 udelay(50); 1379 } 1380 1381 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1382 int xcc_id) 1383 { 1384 const struct gfx_firmware_header_v1_0 *mec_hdr; 1385 const __le32 *fw_data; 1386 unsigned i; 1387 u32 tmp; 1388 u32 mec_ucode_addr_offset; 1389 u32 mec_ucode_data_offset; 1390 1391 if (!adev->gfx.mec_fw) 1392 return -EINVAL; 1393 1394 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1395 1396 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1397 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1398 1399 fw_data = (const __le32 *) 1400 (adev->gfx.mec_fw->data + 1401 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1402 tmp = 0; 1403 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1404 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1405 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1406 1407 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1408 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1409 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1410 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1411 1412 mec_ucode_addr_offset = 1413 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1414 mec_ucode_data_offset = 1415 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1416 1417 /* MEC1 */ 1418 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1419 for (i = 0; i < mec_hdr->jt_size; i++) 1420 WREG32(mec_ucode_data_offset, 1421 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1422 1423 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1424 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1425 1426 return 0; 1427 } 1428 1429 /* KIQ functions */ 1430 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1431 { 1432 uint32_t tmp; 1433 struct amdgpu_device *adev = ring->adev; 1434 1435 /* tell RLC which is KIQ queue */ 1436 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1437 tmp &= 0xffffff00; 1438 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1439 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1440 tmp |= 0x80; 1441 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1442 } 1443 1444 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1445 { 1446 struct amdgpu_device *adev = ring->adev; 1447 1448 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1449 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1450 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1451 mqd->cp_hqd_queue_priority = 1452 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1453 } 1454 } 1455 } 1456 1457 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1458 { 1459 struct amdgpu_device *adev = ring->adev; 1460 struct v9_mqd *mqd = ring->mqd_ptr; 1461 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1462 uint32_t tmp; 1463 1464 mqd->header = 0xC0310800; 1465 mqd->compute_pipelinestat_enable = 0x00000001; 1466 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1467 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1468 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1469 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1470 mqd->compute_misc_reserved = 0x00000003; 1471 1472 mqd->dynamic_cu_mask_addr_lo = 1473 lower_32_bits(ring->mqd_gpu_addr 1474 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1475 mqd->dynamic_cu_mask_addr_hi = 1476 upper_32_bits(ring->mqd_gpu_addr 1477 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1478 1479 eop_base_addr = ring->eop_gpu_addr >> 8; 1480 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1481 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1482 1483 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1484 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1485 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1486 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1487 1488 mqd->cp_hqd_eop_control = tmp; 1489 1490 /* enable doorbell? */ 1491 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1492 1493 if (ring->use_doorbell) { 1494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1495 DOORBELL_OFFSET, ring->doorbell_index); 1496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1497 DOORBELL_EN, 1); 1498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1499 DOORBELL_SOURCE, 0); 1500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1501 DOORBELL_HIT, 0); 1502 } else { 1503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1504 DOORBELL_EN, 0); 1505 } 1506 1507 mqd->cp_hqd_pq_doorbell_control = tmp; 1508 1509 /* disable the queue if it's active */ 1510 ring->wptr = 0; 1511 mqd->cp_hqd_dequeue_request = 0; 1512 mqd->cp_hqd_pq_rptr = 0; 1513 mqd->cp_hqd_pq_wptr_lo = 0; 1514 mqd->cp_hqd_pq_wptr_hi = 0; 1515 1516 /* set the pointer to the MQD */ 1517 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1518 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1519 1520 /* set MQD vmid to 0 */ 1521 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1522 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1523 mqd->cp_mqd_control = tmp; 1524 1525 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1526 hqd_gpu_addr = ring->gpu_addr >> 8; 1527 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1528 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1529 1530 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1531 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1533 (order_base_2(ring->ring_size / 4) - 1)); 1534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1535 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1536 #ifdef __BIG_ENDIAN 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1538 #endif 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1543 mqd->cp_hqd_pq_control = tmp; 1544 1545 /* set the wb address whether it's enabled or not */ 1546 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1547 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1548 mqd->cp_hqd_pq_rptr_report_addr_hi = 1549 upper_32_bits(wb_gpu_addr) & 0xffff; 1550 1551 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1552 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1553 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1554 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1555 1556 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1557 ring->wptr = 0; 1558 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1559 1560 /* set the vmid for the queue */ 1561 mqd->cp_hqd_vmid = 0; 1562 1563 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1564 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1565 mqd->cp_hqd_persistent_state = tmp; 1566 1567 /* set MIN_IB_AVAIL_SIZE */ 1568 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1569 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1570 mqd->cp_hqd_ib_control = tmp; 1571 1572 /* set static priority for a queue/ring */ 1573 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1574 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1575 1576 /* map_queues packet doesn't need activate the queue, 1577 * so only kiq need set this field. 1578 */ 1579 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1580 mqd->cp_hqd_active = 1; 1581 1582 return 0; 1583 } 1584 1585 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1586 int xcc_id) 1587 { 1588 struct amdgpu_device *adev = ring->adev; 1589 struct v9_mqd *mqd = ring->mqd_ptr; 1590 int j; 1591 1592 /* disable wptr polling */ 1593 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1594 1595 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1596 mqd->cp_hqd_eop_base_addr_lo); 1597 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1598 mqd->cp_hqd_eop_base_addr_hi); 1599 1600 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1601 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1602 mqd->cp_hqd_eop_control); 1603 1604 /* enable doorbell? */ 1605 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1606 mqd->cp_hqd_pq_doorbell_control); 1607 1608 /* disable the queue if it's active */ 1609 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1611 for (j = 0; j < adev->usec_timeout; j++) { 1612 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1613 break; 1614 udelay(1); 1615 } 1616 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1617 mqd->cp_hqd_dequeue_request); 1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1619 mqd->cp_hqd_pq_rptr); 1620 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1621 mqd->cp_hqd_pq_wptr_lo); 1622 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1623 mqd->cp_hqd_pq_wptr_hi); 1624 } 1625 1626 /* set the pointer to the MQD */ 1627 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1628 mqd->cp_mqd_base_addr_lo); 1629 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1630 mqd->cp_mqd_base_addr_hi); 1631 1632 /* set MQD vmid to 0 */ 1633 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1634 mqd->cp_mqd_control); 1635 1636 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1637 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1638 mqd->cp_hqd_pq_base_lo); 1639 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1640 mqd->cp_hqd_pq_base_hi); 1641 1642 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1643 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1644 mqd->cp_hqd_pq_control); 1645 1646 /* set the wb address whether it's enabled or not */ 1647 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1648 mqd->cp_hqd_pq_rptr_report_addr_lo); 1649 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1650 mqd->cp_hqd_pq_rptr_report_addr_hi); 1651 1652 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1653 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1654 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1655 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1656 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1657 1658 /* enable the doorbell if requested */ 1659 if (ring->use_doorbell) { 1660 WREG32_SOC15( 1661 GC, GET_INST(GC, xcc_id), 1662 regCP_MEC_DOORBELL_RANGE_LOWER, 1663 ((adev->doorbell_index.kiq + 1664 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1665 2) << 2); 1666 WREG32_SOC15( 1667 GC, GET_INST(GC, xcc_id), 1668 regCP_MEC_DOORBELL_RANGE_UPPER, 1669 ((adev->doorbell_index.userqueue_end + 1670 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1671 2) << 2); 1672 } 1673 1674 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1675 mqd->cp_hqd_pq_doorbell_control); 1676 1677 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1678 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1679 mqd->cp_hqd_pq_wptr_lo); 1680 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1681 mqd->cp_hqd_pq_wptr_hi); 1682 1683 /* set the vmid for the queue */ 1684 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1685 1686 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1687 mqd->cp_hqd_persistent_state); 1688 1689 /* activate the queue */ 1690 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1691 mqd->cp_hqd_active); 1692 1693 if (ring->use_doorbell) 1694 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1695 1696 return 0; 1697 } 1698 1699 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1700 int xcc_id) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 int j; 1704 1705 /* disable the queue if it's active */ 1706 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1707 1708 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1709 1710 for (j = 0; j < adev->usec_timeout; j++) { 1711 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1712 break; 1713 udelay(1); 1714 } 1715 1716 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1717 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1718 1719 /* Manual disable if dequeue request times out */ 1720 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1721 } 1722 1723 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1724 0); 1725 } 1726 1727 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0); 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1731 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1735 1736 return 0; 1737 } 1738 1739 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1740 { 1741 struct amdgpu_device *adev = ring->adev; 1742 struct v9_mqd *mqd = ring->mqd_ptr; 1743 struct v9_mqd *tmp_mqd; 1744 1745 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1746 1747 /* GPU could be in bad state during probe, driver trigger the reset 1748 * after load the SMU, in this case , the mqd is not be initialized. 1749 * driver need to re-init the mqd. 1750 * check mqd->cp_hqd_pq_control since this value should not be 0 1751 */ 1752 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1753 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1754 /* for GPU_RESET case , reset MQD to a clean status */ 1755 if (adev->gfx.kiq[xcc_id].mqd_backup) 1756 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1757 1758 /* reset ring buffer */ 1759 ring->wptr = 0; 1760 amdgpu_ring_clear_ring(ring); 1761 mutex_lock(&adev->srbm_mutex); 1762 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1763 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1764 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1765 mutex_unlock(&adev->srbm_mutex); 1766 } else { 1767 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1768 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1769 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1770 mutex_lock(&adev->srbm_mutex); 1771 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1772 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1773 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1774 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1775 mutex_unlock(&adev->srbm_mutex); 1776 1777 if (adev->gfx.kiq[xcc_id].mqd_backup) 1778 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1779 } 1780 1781 return 0; 1782 } 1783 1784 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1785 { 1786 struct amdgpu_device *adev = ring->adev; 1787 struct v9_mqd *mqd = ring->mqd_ptr; 1788 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1789 struct v9_mqd *tmp_mqd; 1790 1791 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1792 * is not be initialized before 1793 */ 1794 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1795 1796 if (!tmp_mqd->cp_hqd_pq_control || 1797 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1798 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1799 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1800 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1801 mutex_lock(&adev->srbm_mutex); 1802 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1803 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1804 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1805 mutex_unlock(&adev->srbm_mutex); 1806 1807 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1808 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1809 } else { 1810 /* restore MQD to a clean status */ 1811 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1812 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1813 /* reset ring buffer */ 1814 ring->wptr = 0; 1815 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1816 amdgpu_ring_clear_ring(ring); 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1823 { 1824 struct amdgpu_ring *ring; 1825 int j; 1826 1827 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1828 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1829 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1830 mutex_lock(&adev->srbm_mutex); 1831 soc15_grbm_select(adev, ring->me, 1832 ring->pipe, 1833 ring->queue, 0, GET_INST(GC, xcc_id)); 1834 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1835 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1836 mutex_unlock(&adev->srbm_mutex); 1837 } 1838 } 1839 1840 return 0; 1841 } 1842 1843 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1844 { 1845 struct amdgpu_ring *ring; 1846 int r; 1847 1848 ring = &adev->gfx.kiq[xcc_id].ring; 1849 1850 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1851 if (unlikely(r != 0)) 1852 return r; 1853 1854 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1855 if (unlikely(r != 0)) { 1856 amdgpu_bo_unreserve(ring->mqd_obj); 1857 return r; 1858 } 1859 1860 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1861 amdgpu_bo_kunmap(ring->mqd_obj); 1862 ring->mqd_ptr = NULL; 1863 amdgpu_bo_unreserve(ring->mqd_obj); 1864 return 0; 1865 } 1866 1867 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1868 { 1869 struct amdgpu_ring *ring = NULL; 1870 int r = 0, i; 1871 1872 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1873 1874 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1875 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1876 1877 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1878 if (unlikely(r != 0)) 1879 goto done; 1880 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1881 if (!r) { 1882 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1883 amdgpu_bo_kunmap(ring->mqd_obj); 1884 ring->mqd_ptr = NULL; 1885 } 1886 amdgpu_bo_unreserve(ring->mqd_obj); 1887 if (r) 1888 goto done; 1889 } 1890 1891 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1892 done: 1893 return r; 1894 } 1895 1896 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1897 { 1898 struct amdgpu_ring *ring; 1899 int r, j; 1900 1901 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1902 1903 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1904 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1905 1906 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1907 if (r) 1908 return r; 1909 } 1910 1911 /* set the virtual and physical id based on partition_mode */ 1912 gfx_v9_4_3_xcc_program_xcc_id(adev, xcc_id); 1913 1914 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1915 if (r) 1916 return r; 1917 1918 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1919 if (r) 1920 return r; 1921 1922 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1923 ring = &adev->gfx.compute_ring 1924 [j + xcc_id * adev->gfx.num_compute_rings]; 1925 r = amdgpu_ring_test_helper(ring); 1926 if (r) 1927 return r; 1928 } 1929 1930 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1931 1932 return 0; 1933 } 1934 1935 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1936 { 1937 int r = 0, i, num_xcc; 1938 1939 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1940 AMDGPU_XCP_FL_NONE) == 1941 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1942 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1943 amdgpu_user_partt_mode); 1944 1945 if (r) 1946 return r; 1947 1948 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1949 for (i = 0; i < num_xcc; i++) { 1950 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1951 if (r) 1952 return r; 1953 } 1954 1955 return 0; 1956 } 1957 1958 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1959 int xcc_id) 1960 { 1961 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1962 } 1963 1964 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1965 { 1966 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1967 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1968 1969 /* Use deinitialize sequence from CAIL when unbinding device 1970 * from driver, otherwise KIQ is hanging when binding back 1971 */ 1972 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1973 mutex_lock(&adev->srbm_mutex); 1974 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1975 adev->gfx.kiq[xcc_id].ring.pipe, 1976 adev->gfx.kiq[xcc_id].ring.queue, 0, 1977 GET_INST(GC, xcc_id)); 1978 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1979 xcc_id); 1980 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1981 mutex_unlock(&adev->srbm_mutex); 1982 } 1983 1984 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 1985 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 1986 } 1987 1988 static int gfx_v9_4_3_hw_init(void *handle) 1989 { 1990 int r; 1991 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1992 1993 gfx_v9_4_3_init_golden_registers(adev); 1994 1995 gfx_v9_4_3_constants_init(adev); 1996 1997 r = adev->gfx.rlc.funcs->resume(adev); 1998 if (r) 1999 return r; 2000 2001 r = gfx_v9_4_3_cp_resume(adev); 2002 if (r) 2003 return r; 2004 2005 return r; 2006 } 2007 2008 static int gfx_v9_4_3_hw_fini(void *handle) 2009 { 2010 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2011 int i, num_xcc; 2012 2013 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2014 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2015 2016 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2017 for (i = 0; i < num_xcc; i++) { 2018 gfx_v9_4_3_xcc_fini(adev, i); 2019 } 2020 2021 return 0; 2022 } 2023 2024 static int gfx_v9_4_3_suspend(void *handle) 2025 { 2026 return gfx_v9_4_3_hw_fini(handle); 2027 } 2028 2029 static int gfx_v9_4_3_resume(void *handle) 2030 { 2031 return gfx_v9_4_3_hw_init(handle); 2032 } 2033 2034 static bool gfx_v9_4_3_is_idle(void *handle) 2035 { 2036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2037 int i, num_xcc; 2038 2039 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2040 for (i = 0; i < num_xcc; i++) { 2041 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2042 GRBM_STATUS, GUI_ACTIVE)) 2043 return false; 2044 } 2045 return true; 2046 } 2047 2048 static int gfx_v9_4_3_wait_for_idle(void *handle) 2049 { 2050 unsigned i; 2051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2052 2053 for (i = 0; i < adev->usec_timeout; i++) { 2054 if (gfx_v9_4_3_is_idle(handle)) 2055 return 0; 2056 udelay(1); 2057 } 2058 return -ETIMEDOUT; 2059 } 2060 2061 static int gfx_v9_4_3_soft_reset(void *handle) 2062 { 2063 u32 grbm_soft_reset = 0; 2064 u32 tmp; 2065 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2066 2067 /* GRBM_STATUS */ 2068 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2069 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2070 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2071 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2072 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2073 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2074 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2075 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2076 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2077 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2078 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2079 } 2080 2081 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2082 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2083 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2084 } 2085 2086 /* GRBM_STATUS2 */ 2087 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2088 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2089 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2090 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2091 2092 2093 if (grbm_soft_reset) { 2094 /* stop the rlc */ 2095 adev->gfx.rlc.funcs->stop(adev); 2096 2097 /* Disable MEC parsing/prefetching */ 2098 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2099 2100 if (grbm_soft_reset) { 2101 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2102 tmp |= grbm_soft_reset; 2103 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2104 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2105 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2106 2107 udelay(50); 2108 2109 tmp &= ~grbm_soft_reset; 2110 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2111 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2112 } 2113 2114 /* Wait a little for things to settle down */ 2115 udelay(50); 2116 } 2117 return 0; 2118 } 2119 2120 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2121 uint32_t vmid, 2122 uint32_t gds_base, uint32_t gds_size, 2123 uint32_t gws_base, uint32_t gws_size, 2124 uint32_t oa_base, uint32_t oa_size) 2125 { 2126 struct amdgpu_device *adev = ring->adev; 2127 2128 /* GDS Base */ 2129 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2130 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2131 gds_base); 2132 2133 /* GDS Size */ 2134 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2135 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2136 gds_size); 2137 2138 /* GWS */ 2139 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2140 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2141 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2142 2143 /* OA */ 2144 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2145 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2146 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2147 } 2148 2149 static int gfx_v9_4_3_early_init(void *handle) 2150 { 2151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2152 2153 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2154 AMDGPU_MAX_COMPUTE_RINGS); 2155 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2156 gfx_v9_4_3_set_ring_funcs(adev); 2157 gfx_v9_4_3_set_irq_funcs(adev); 2158 gfx_v9_4_3_set_gds_init(adev); 2159 gfx_v9_4_3_set_rlc_funcs(adev); 2160 2161 return gfx_v9_4_3_init_microcode(adev); 2162 } 2163 2164 static int gfx_v9_4_3_late_init(void *handle) 2165 { 2166 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2167 int r; 2168 2169 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2170 if (r) 2171 return r; 2172 2173 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2174 if (r) 2175 return r; 2176 2177 return 0; 2178 } 2179 2180 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2181 bool enable, int xcc_id) 2182 { 2183 uint32_t def, data; 2184 2185 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2186 return; 2187 2188 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2189 regRLC_CGTT_MGCG_OVERRIDE); 2190 2191 if (enable) 2192 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2193 else 2194 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2195 2196 if (def != data) 2197 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2198 regRLC_CGTT_MGCG_OVERRIDE, data); 2199 2200 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2201 2202 if (enable) 2203 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2204 else 2205 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2206 2207 if (def != data) 2208 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2209 } 2210 2211 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2212 bool enable, int xcc_id) 2213 { 2214 uint32_t def, data; 2215 2216 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2217 return; 2218 2219 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2220 regRLC_CGTT_MGCG_OVERRIDE); 2221 2222 if (enable) 2223 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2224 else 2225 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2226 2227 if (def != data) 2228 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2229 regRLC_CGTT_MGCG_OVERRIDE, data); 2230 } 2231 2232 static void 2233 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2234 bool enable, int xcc_id) 2235 { 2236 uint32_t data, def; 2237 2238 /* It is disabled by HW by default */ 2239 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2240 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2241 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2242 2243 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2244 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2245 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2246 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2247 2248 if (def != data) 2249 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2250 2251 /* MGLS is a global flag to control all MGLS in GFX */ 2252 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2253 /* 2 - RLC memory Light sleep */ 2254 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2255 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2256 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2257 if (def != data) 2258 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2259 } 2260 /* 3 - CP memory Light sleep */ 2261 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2262 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2263 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2264 if (def != data) 2265 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2266 } 2267 } 2268 } else { 2269 /* 1 - MGCG_OVERRIDE */ 2270 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2271 2272 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2273 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2274 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2275 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2276 2277 if (def != data) 2278 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2279 2280 /* 2 - disable MGLS in RLC */ 2281 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2282 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2283 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2284 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2285 } 2286 2287 /* 3 - disable MGLS in CP */ 2288 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2289 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2290 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2291 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2292 } 2293 } 2294 2295 } 2296 2297 static void 2298 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2299 bool enable, int xcc_id) 2300 { 2301 uint32_t def, data; 2302 2303 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2304 2305 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2306 /* unset CGCG override */ 2307 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2308 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2309 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2310 else 2311 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2312 /* update CGCG and CGLS override bits */ 2313 if (def != data) 2314 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2315 2316 /* enable cgcg FSM(0x0000363F) */ 2317 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2318 2319 data = (0x36 2320 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2321 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2322 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2323 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2324 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2325 if (def != data) 2326 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2327 2328 /* set IDLE_POLL_COUNT(0x00900100) */ 2329 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2330 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2331 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2332 if (def != data) 2333 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2334 } else { 2335 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2336 /* reset CGCG/CGLS bits */ 2337 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2338 /* disable cgcg and cgls in FSM */ 2339 if (def != data) 2340 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2341 } 2342 2343 } 2344 2345 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2346 bool enable, int xcc_id) 2347 { 2348 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2349 2350 if (enable) { 2351 /* FGCG */ 2352 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2353 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2354 2355 /* CGCG/CGLS should be enabled after MGCG/MGLS 2356 * === MGCG + MGLS === 2357 */ 2358 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2359 xcc_id); 2360 /* === CGCG + CGLS === */ 2361 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2362 xcc_id); 2363 } else { 2364 /* CGCG/CGLS should be disabled before MGCG/MGLS 2365 * === CGCG + CGLS === 2366 */ 2367 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2368 xcc_id); 2369 /* === MGCG + MGLS === */ 2370 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2371 xcc_id); 2372 2373 /* FGCG */ 2374 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2375 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2376 } 2377 2378 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2379 2380 return 0; 2381 } 2382 2383 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2384 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2385 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2386 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2387 .init = gfx_v9_4_3_rlc_init, 2388 .resume = gfx_v9_4_3_rlc_resume, 2389 .stop = gfx_v9_4_3_rlc_stop, 2390 .reset = gfx_v9_4_3_rlc_reset, 2391 .start = gfx_v9_4_3_rlc_start, 2392 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2393 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2394 }; 2395 2396 static int gfx_v9_4_3_set_powergating_state(void *handle, 2397 enum amd_powergating_state state) 2398 { 2399 return 0; 2400 } 2401 2402 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2403 enum amd_clockgating_state state) 2404 { 2405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2406 int i, num_xcc; 2407 2408 if (amdgpu_sriov_vf(adev)) 2409 return 0; 2410 2411 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2412 switch (adev->ip_versions[GC_HWIP][0]) { 2413 case IP_VERSION(9, 4, 3): 2414 for (i = 0; i < num_xcc; i++) 2415 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2416 adev, state == AMD_CG_STATE_GATE, i); 2417 break; 2418 default: 2419 break; 2420 } 2421 return 0; 2422 } 2423 2424 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2425 { 2426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2427 int data; 2428 2429 if (amdgpu_sriov_vf(adev)) 2430 *flags = 0; 2431 2432 /* AMD_CG_SUPPORT_GFX_MGCG */ 2433 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2434 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2435 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2436 2437 /* AMD_CG_SUPPORT_GFX_CGCG */ 2438 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2439 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2440 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2441 2442 /* AMD_CG_SUPPORT_GFX_CGLS */ 2443 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2444 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2445 2446 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2447 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2448 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2449 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2450 2451 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2452 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2453 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2454 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2455 } 2456 2457 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2458 { 2459 struct amdgpu_device *adev = ring->adev; 2460 u32 ref_and_mask, reg_mem_engine; 2461 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2462 2463 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2464 switch (ring->me) { 2465 case 1: 2466 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2467 break; 2468 case 2: 2469 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2470 break; 2471 default: 2472 return; 2473 } 2474 reg_mem_engine = 0; 2475 } else { 2476 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2477 reg_mem_engine = 1; /* pfp */ 2478 } 2479 2480 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2481 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2482 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2483 ref_and_mask, ref_and_mask, 0x20); 2484 } 2485 2486 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2487 struct amdgpu_job *job, 2488 struct amdgpu_ib *ib, 2489 uint32_t flags) 2490 { 2491 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2492 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2493 2494 /* Currently, there is a high possibility to get wave ID mismatch 2495 * between ME and GDS, leading to a hw deadlock, because ME generates 2496 * different wave IDs than the GDS expects. This situation happens 2497 * randomly when at least 5 compute pipes use GDS ordered append. 2498 * The wave IDs generated by ME are also wrong after suspend/resume. 2499 * Those are probably bugs somewhere else in the kernel driver. 2500 * 2501 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2502 * GDS to 0 for this ring (me/pipe). 2503 */ 2504 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2505 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2506 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2507 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2508 } 2509 2510 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2511 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2512 amdgpu_ring_write(ring, 2513 #ifdef __BIG_ENDIAN 2514 (2 << 0) | 2515 #endif 2516 lower_32_bits(ib->gpu_addr)); 2517 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2518 amdgpu_ring_write(ring, control); 2519 } 2520 2521 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2522 u64 seq, unsigned flags) 2523 { 2524 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2525 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2526 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2527 2528 /* RELEASE_MEM - flush caches, send int */ 2529 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2530 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2531 EOP_TC_NC_ACTION_EN) : 2532 (EOP_TCL1_ACTION_EN | 2533 EOP_TC_ACTION_EN | 2534 EOP_TC_WB_ACTION_EN | 2535 EOP_TC_MD_ACTION_EN)) | 2536 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2537 EVENT_INDEX(5))); 2538 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2539 2540 /* 2541 * the address should be Qword aligned if 64bit write, Dword 2542 * aligned if only send 32bit data low (discard data high) 2543 */ 2544 if (write64bit) 2545 BUG_ON(addr & 0x7); 2546 else 2547 BUG_ON(addr & 0x3); 2548 amdgpu_ring_write(ring, lower_32_bits(addr)); 2549 amdgpu_ring_write(ring, upper_32_bits(addr)); 2550 amdgpu_ring_write(ring, lower_32_bits(seq)); 2551 amdgpu_ring_write(ring, upper_32_bits(seq)); 2552 amdgpu_ring_write(ring, 0); 2553 } 2554 2555 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2556 { 2557 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2558 uint32_t seq = ring->fence_drv.sync_seq; 2559 uint64_t addr = ring->fence_drv.gpu_addr; 2560 2561 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2562 lower_32_bits(addr), upper_32_bits(addr), 2563 seq, 0xffffffff, 4); 2564 } 2565 2566 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2567 unsigned vmid, uint64_t pd_addr) 2568 { 2569 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2570 } 2571 2572 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2573 { 2574 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2575 } 2576 2577 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2578 { 2579 u64 wptr; 2580 2581 /* XXX check if swapping is necessary on BE */ 2582 if (ring->use_doorbell) 2583 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2584 else 2585 BUG(); 2586 return wptr; 2587 } 2588 2589 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2590 { 2591 struct amdgpu_device *adev = ring->adev; 2592 2593 /* XXX check if swapping is necessary on BE */ 2594 if (ring->use_doorbell) { 2595 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2596 WDOORBELL64(ring->doorbell_index, ring->wptr); 2597 } else { 2598 BUG(); /* only DOORBELL method supported on gfx9 now */ 2599 } 2600 } 2601 2602 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2603 u64 seq, unsigned int flags) 2604 { 2605 struct amdgpu_device *adev = ring->adev; 2606 2607 /* we only allocate 32bit for each seq wb address */ 2608 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2609 2610 /* write fence seq to the "addr" */ 2611 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2612 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2613 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2614 amdgpu_ring_write(ring, lower_32_bits(addr)); 2615 amdgpu_ring_write(ring, upper_32_bits(addr)); 2616 amdgpu_ring_write(ring, lower_32_bits(seq)); 2617 2618 if (flags & AMDGPU_FENCE_FLAG_INT) { 2619 /* set register to trigger INT */ 2620 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2621 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2622 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2623 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2624 amdgpu_ring_write(ring, 0); 2625 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2626 } 2627 } 2628 2629 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2630 uint32_t reg_val_offs) 2631 { 2632 struct amdgpu_device *adev = ring->adev; 2633 2634 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2635 amdgpu_ring_write(ring, 0 | /* src: register*/ 2636 (5 << 8) | /* dst: memory */ 2637 (1 << 20)); /* write confirm */ 2638 amdgpu_ring_write(ring, reg); 2639 amdgpu_ring_write(ring, 0); 2640 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2641 reg_val_offs * 4)); 2642 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2643 reg_val_offs * 4)); 2644 } 2645 2646 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2647 uint32_t val) 2648 { 2649 uint32_t cmd = 0; 2650 2651 switch (ring->funcs->type) { 2652 case AMDGPU_RING_TYPE_GFX: 2653 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2654 break; 2655 case AMDGPU_RING_TYPE_KIQ: 2656 cmd = (1 << 16); /* no inc addr */ 2657 break; 2658 default: 2659 cmd = WR_CONFIRM; 2660 break; 2661 } 2662 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2663 amdgpu_ring_write(ring, cmd); 2664 amdgpu_ring_write(ring, reg); 2665 amdgpu_ring_write(ring, 0); 2666 amdgpu_ring_write(ring, val); 2667 } 2668 2669 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2670 uint32_t val, uint32_t mask) 2671 { 2672 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2673 } 2674 2675 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2676 uint32_t reg0, uint32_t reg1, 2677 uint32_t ref, uint32_t mask) 2678 { 2679 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2680 ref, mask); 2681 } 2682 2683 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2684 struct amdgpu_device *adev, int me, int pipe, 2685 enum amdgpu_interrupt_state state, int xcc_id) 2686 { 2687 u32 mec_int_cntl, mec_int_cntl_reg; 2688 2689 /* 2690 * amdgpu controls only the first MEC. That's why this function only 2691 * handles the setting of interrupts for this specific MEC. All other 2692 * pipes' interrupts are set by amdkfd. 2693 */ 2694 2695 if (me == 1) { 2696 switch (pipe) { 2697 case 0: 2698 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2699 break; 2700 case 1: 2701 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2702 break; 2703 case 2: 2704 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2705 break; 2706 case 3: 2707 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2708 break; 2709 default: 2710 DRM_DEBUG("invalid pipe %d\n", pipe); 2711 return; 2712 } 2713 } else { 2714 DRM_DEBUG("invalid me %d\n", me); 2715 return; 2716 } 2717 2718 switch (state) { 2719 case AMDGPU_IRQ_STATE_DISABLE: 2720 mec_int_cntl = RREG32(mec_int_cntl_reg); 2721 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2722 TIME_STAMP_INT_ENABLE, 0); 2723 WREG32(mec_int_cntl_reg, mec_int_cntl); 2724 break; 2725 case AMDGPU_IRQ_STATE_ENABLE: 2726 mec_int_cntl = RREG32(mec_int_cntl_reg); 2727 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2728 TIME_STAMP_INT_ENABLE, 1); 2729 WREG32(mec_int_cntl_reg, mec_int_cntl); 2730 break; 2731 default: 2732 break; 2733 } 2734 } 2735 2736 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2737 struct amdgpu_irq_src *source, 2738 unsigned type, 2739 enum amdgpu_interrupt_state state) 2740 { 2741 int i, num_xcc; 2742 2743 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2744 switch (state) { 2745 case AMDGPU_IRQ_STATE_DISABLE: 2746 case AMDGPU_IRQ_STATE_ENABLE: 2747 for (i = 0; i < num_xcc; i++) 2748 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2749 PRIV_REG_INT_ENABLE, 2750 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2751 break; 2752 default: 2753 break; 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2760 struct amdgpu_irq_src *source, 2761 unsigned type, 2762 enum amdgpu_interrupt_state state) 2763 { 2764 int i, num_xcc; 2765 2766 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2767 switch (state) { 2768 case AMDGPU_IRQ_STATE_DISABLE: 2769 case AMDGPU_IRQ_STATE_ENABLE: 2770 for (i = 0; i < num_xcc; i++) 2771 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2772 PRIV_INSTR_INT_ENABLE, 2773 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2774 break; 2775 default: 2776 break; 2777 } 2778 2779 return 0; 2780 } 2781 2782 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2783 struct amdgpu_irq_src *src, 2784 unsigned type, 2785 enum amdgpu_interrupt_state state) 2786 { 2787 int i, num_xcc; 2788 2789 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2790 for (i = 0; i < num_xcc; i++) { 2791 switch (type) { 2792 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2793 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2794 adev, 1, 0, state, i); 2795 break; 2796 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2797 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2798 adev, 1, 1, state, i); 2799 break; 2800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2801 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2802 adev, 1, 2, state, i); 2803 break; 2804 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2805 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2806 adev, 1, 3, state, i); 2807 break; 2808 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2809 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2810 adev, 2, 0, state, i); 2811 break; 2812 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2813 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2814 adev, 2, 1, state, i); 2815 break; 2816 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2817 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2818 adev, 2, 2, state, i); 2819 break; 2820 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2821 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2822 adev, 2, 3, state, i); 2823 break; 2824 default: 2825 break; 2826 } 2827 } 2828 2829 return 0; 2830 } 2831 2832 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2833 struct amdgpu_irq_src *source, 2834 struct amdgpu_iv_entry *entry) 2835 { 2836 int i, xcc_id; 2837 u8 me_id, pipe_id, queue_id; 2838 struct amdgpu_ring *ring; 2839 2840 DRM_DEBUG("IH: CP EOP\n"); 2841 me_id = (entry->ring_id & 0x0c) >> 2; 2842 pipe_id = (entry->ring_id & 0x03) >> 0; 2843 queue_id = (entry->ring_id & 0x70) >> 4; 2844 2845 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2846 2847 if (xcc_id == -EINVAL) 2848 return -EINVAL; 2849 2850 switch (me_id) { 2851 case 0: 2852 case 1: 2853 case 2: 2854 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2855 ring = &adev->gfx.compute_ring 2856 [i + 2857 xcc_id * adev->gfx.num_compute_rings]; 2858 /* Per-queue interrupt is supported for MEC starting from VI. 2859 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2860 */ 2861 2862 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2863 amdgpu_fence_process(ring); 2864 } 2865 break; 2866 } 2867 return 0; 2868 } 2869 2870 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2871 struct amdgpu_iv_entry *entry) 2872 { 2873 u8 me_id, pipe_id, queue_id; 2874 struct amdgpu_ring *ring; 2875 int i, xcc_id; 2876 2877 me_id = (entry->ring_id & 0x0c) >> 2; 2878 pipe_id = (entry->ring_id & 0x03) >> 0; 2879 queue_id = (entry->ring_id & 0x70) >> 4; 2880 2881 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2882 2883 if (xcc_id == -EINVAL) 2884 return; 2885 2886 switch (me_id) { 2887 case 0: 2888 case 1: 2889 case 2: 2890 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2891 ring = &adev->gfx.compute_ring 2892 [i + 2893 xcc_id * adev->gfx.num_compute_rings]; 2894 if (ring->me == me_id && ring->pipe == pipe_id && 2895 ring->queue == queue_id) 2896 drm_sched_fault(&ring->sched); 2897 } 2898 break; 2899 } 2900 } 2901 2902 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2903 struct amdgpu_irq_src *source, 2904 struct amdgpu_iv_entry *entry) 2905 { 2906 DRM_ERROR("Illegal register access in command stream\n"); 2907 gfx_v9_4_3_fault(adev, entry); 2908 return 0; 2909 } 2910 2911 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2912 struct amdgpu_irq_src *source, 2913 struct amdgpu_iv_entry *entry) 2914 { 2915 DRM_ERROR("Illegal instruction in command stream\n"); 2916 gfx_v9_4_3_fault(adev, entry); 2917 return 0; 2918 } 2919 2920 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2921 { 2922 const unsigned int cp_coher_cntl = 2923 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2924 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2925 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2926 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2927 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2928 2929 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2930 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2931 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2932 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2933 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2934 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2935 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2936 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2937 } 2938 2939 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2940 uint32_t pipe, bool enable) 2941 { 2942 struct amdgpu_device *adev = ring->adev; 2943 uint32_t val; 2944 uint32_t wcl_cs_reg; 2945 2946 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2947 val = enable ? 0x1 : 0x7f; 2948 2949 switch (pipe) { 2950 case 0: 2951 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2952 break; 2953 case 1: 2954 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2955 break; 2956 case 2: 2957 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2958 break; 2959 case 3: 2960 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2961 break; 2962 default: 2963 DRM_DEBUG("invalid pipe %d\n", pipe); 2964 return; 2965 } 2966 2967 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2968 2969 } 2970 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2971 { 2972 struct amdgpu_device *adev = ring->adev; 2973 uint32_t val; 2974 int i; 2975 2976 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2977 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2978 * around 25% of gpu resources. 2979 */ 2980 val = enable ? 0x1f : 0x07ffffff; 2981 amdgpu_ring_emit_wreg(ring, 2982 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 2983 val); 2984 2985 /* Restrict waves for normal/low priority compute queues as well 2986 * to get best QoS for high priority compute jobs. 2987 * 2988 * amdgpu controls only 1st ME(0-3 CS pipes). 2989 */ 2990 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2991 if (i != ring->pipe) 2992 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 2993 2994 } 2995 } 2996 2997 enum amdgpu_gfx_cp_ras_mem_id { 2998 AMDGPU_GFX_CP_MEM1 = 1, 2999 AMDGPU_GFX_CP_MEM2, 3000 AMDGPU_GFX_CP_MEM3, 3001 AMDGPU_GFX_CP_MEM4, 3002 AMDGPU_GFX_CP_MEM5, 3003 }; 3004 3005 enum amdgpu_gfx_gcea_ras_mem_id { 3006 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3007 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3008 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3009 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3010 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3011 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3012 AMDGPU_GFX_GCEA_MAM_DMEM0, 3013 AMDGPU_GFX_GCEA_MAM_DMEM1, 3014 AMDGPU_GFX_GCEA_MAM_DMEM2, 3015 AMDGPU_GFX_GCEA_MAM_DMEM3, 3016 AMDGPU_GFX_GCEA_MAM_AMEM0, 3017 AMDGPU_GFX_GCEA_MAM_AMEM1, 3018 AMDGPU_GFX_GCEA_MAM_AMEM2, 3019 AMDGPU_GFX_GCEA_MAM_AMEM3, 3020 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3021 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3022 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3023 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3024 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3025 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3026 }; 3027 3028 enum amdgpu_gfx_gc_cane_ras_mem_id { 3029 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3030 }; 3031 3032 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3033 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3034 }; 3035 3036 enum amdgpu_gfx_gds_ras_mem_id { 3037 AMDGPU_GFX_GDS_MEM0 = 0, 3038 }; 3039 3040 enum amdgpu_gfx_lds_ras_mem_id { 3041 AMDGPU_GFX_LDS_BANK0 = 0, 3042 AMDGPU_GFX_LDS_BANK1, 3043 AMDGPU_GFX_LDS_BANK2, 3044 AMDGPU_GFX_LDS_BANK3, 3045 AMDGPU_GFX_LDS_BANK4, 3046 AMDGPU_GFX_LDS_BANK5, 3047 AMDGPU_GFX_LDS_BANK6, 3048 AMDGPU_GFX_LDS_BANK7, 3049 AMDGPU_GFX_LDS_BANK8, 3050 AMDGPU_GFX_LDS_BANK9, 3051 AMDGPU_GFX_LDS_BANK10, 3052 AMDGPU_GFX_LDS_BANK11, 3053 AMDGPU_GFX_LDS_BANK12, 3054 AMDGPU_GFX_LDS_BANK13, 3055 AMDGPU_GFX_LDS_BANK14, 3056 AMDGPU_GFX_LDS_BANK15, 3057 AMDGPU_GFX_LDS_BANK16, 3058 AMDGPU_GFX_LDS_BANK17, 3059 AMDGPU_GFX_LDS_BANK18, 3060 AMDGPU_GFX_LDS_BANK19, 3061 AMDGPU_GFX_LDS_BANK20, 3062 AMDGPU_GFX_LDS_BANK21, 3063 AMDGPU_GFX_LDS_BANK22, 3064 AMDGPU_GFX_LDS_BANK23, 3065 AMDGPU_GFX_LDS_BANK24, 3066 AMDGPU_GFX_LDS_BANK25, 3067 AMDGPU_GFX_LDS_BANK26, 3068 AMDGPU_GFX_LDS_BANK27, 3069 AMDGPU_GFX_LDS_BANK28, 3070 AMDGPU_GFX_LDS_BANK29, 3071 AMDGPU_GFX_LDS_BANK30, 3072 AMDGPU_GFX_LDS_BANK31, 3073 AMDGPU_GFX_LDS_SP_BUFFER_A, 3074 AMDGPU_GFX_LDS_SP_BUFFER_B, 3075 }; 3076 3077 enum amdgpu_gfx_rlc_ras_mem_id { 3078 AMDGPU_GFX_RLC_GPMF32 = 1, 3079 AMDGPU_GFX_RLC_RLCVF32, 3080 AMDGPU_GFX_RLC_SCRATCH, 3081 AMDGPU_GFX_RLC_SRM_ARAM, 3082 AMDGPU_GFX_RLC_SRM_DRAM, 3083 AMDGPU_GFX_RLC_TCTAG, 3084 AMDGPU_GFX_RLC_SPM_SE, 3085 AMDGPU_GFX_RLC_SPM_GRBMT, 3086 }; 3087 3088 enum amdgpu_gfx_sp_ras_mem_id { 3089 AMDGPU_GFX_SP_SIMDID0 = 0, 3090 }; 3091 3092 enum amdgpu_gfx_spi_ras_mem_id { 3093 AMDGPU_GFX_SPI_MEM0 = 0, 3094 AMDGPU_GFX_SPI_MEM1, 3095 AMDGPU_GFX_SPI_MEM2, 3096 AMDGPU_GFX_SPI_MEM3, 3097 }; 3098 3099 enum amdgpu_gfx_sqc_ras_mem_id { 3100 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3101 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3102 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3103 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3104 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3105 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3106 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3107 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3108 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3109 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3110 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3111 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3112 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3113 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3114 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3115 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3116 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3117 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3118 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3119 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3120 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3121 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3122 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3123 }; 3124 3125 enum amdgpu_gfx_sq_ras_mem_id { 3126 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3127 AMDGPU_GFX_SQ_SGPR_MEM1, 3128 AMDGPU_GFX_SQ_SGPR_MEM2, 3129 AMDGPU_GFX_SQ_SGPR_MEM3, 3130 }; 3131 3132 enum amdgpu_gfx_ta_ras_mem_id { 3133 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3134 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3135 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3136 AMDGPU_GFX_TA_FSX_LFIFO, 3137 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3138 }; 3139 3140 enum amdgpu_gfx_tcc_ras_mem_id { 3141 AMDGPU_GFX_TCC_MEM1 = 1, 3142 }; 3143 3144 enum amdgpu_gfx_tca_ras_mem_id { 3145 AMDGPU_GFX_TCA_MEM1 = 1, 3146 }; 3147 3148 enum amdgpu_gfx_tci_ras_mem_id { 3149 AMDGPU_GFX_TCIW_MEM = 1, 3150 }; 3151 3152 enum amdgpu_gfx_tcp_ras_mem_id { 3153 AMDGPU_GFX_TCP_LFIFO0 = 1, 3154 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3155 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3156 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3157 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3158 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3159 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3160 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3161 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3162 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3163 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3164 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3165 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3166 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3167 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3168 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3169 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3170 AMDGPU_GFX_TCP_VM_FIFO, 3171 AMDGPU_GFX_TCP_DB_TAGRAM0, 3172 AMDGPU_GFX_TCP_DB_TAGRAM1, 3173 AMDGPU_GFX_TCP_DB_TAGRAM2, 3174 AMDGPU_GFX_TCP_DB_TAGRAM3, 3175 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3176 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3177 AMDGPU_GFX_TCP_CMD_FIFO, 3178 }; 3179 3180 enum amdgpu_gfx_td_ras_mem_id { 3181 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3182 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3183 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3184 }; 3185 3186 enum amdgpu_gfx_tcx_ras_mem_id { 3187 AMDGPU_GFX_TCX_FIFOD0 = 0, 3188 AMDGPU_GFX_TCX_FIFOD1, 3189 AMDGPU_GFX_TCX_FIFOD2, 3190 AMDGPU_GFX_TCX_FIFOD3, 3191 AMDGPU_GFX_TCX_FIFOD4, 3192 AMDGPU_GFX_TCX_FIFOD5, 3193 AMDGPU_GFX_TCX_FIFOD6, 3194 AMDGPU_GFX_TCX_FIFOD7, 3195 AMDGPU_GFX_TCX_FIFOB0, 3196 AMDGPU_GFX_TCX_FIFOB1, 3197 AMDGPU_GFX_TCX_FIFOB2, 3198 AMDGPU_GFX_TCX_FIFOB3, 3199 AMDGPU_GFX_TCX_FIFOB4, 3200 AMDGPU_GFX_TCX_FIFOB5, 3201 AMDGPU_GFX_TCX_FIFOB6, 3202 AMDGPU_GFX_TCX_FIFOB7, 3203 AMDGPU_GFX_TCX_FIFOA0, 3204 AMDGPU_GFX_TCX_FIFOA1, 3205 AMDGPU_GFX_TCX_FIFOA2, 3206 AMDGPU_GFX_TCX_FIFOA3, 3207 AMDGPU_GFX_TCX_FIFOA4, 3208 AMDGPU_GFX_TCX_FIFOA5, 3209 AMDGPU_GFX_TCX_FIFOA6, 3210 AMDGPU_GFX_TCX_FIFOA7, 3211 AMDGPU_GFX_TCX_CFIFO0, 3212 AMDGPU_GFX_TCX_CFIFO1, 3213 AMDGPU_GFX_TCX_CFIFO2, 3214 AMDGPU_GFX_TCX_CFIFO3, 3215 AMDGPU_GFX_TCX_CFIFO4, 3216 AMDGPU_GFX_TCX_CFIFO5, 3217 AMDGPU_GFX_TCX_CFIFO6, 3218 AMDGPU_GFX_TCX_CFIFO7, 3219 AMDGPU_GFX_TCX_FIFO_ACKB0, 3220 AMDGPU_GFX_TCX_FIFO_ACKB1, 3221 AMDGPU_GFX_TCX_FIFO_ACKB2, 3222 AMDGPU_GFX_TCX_FIFO_ACKB3, 3223 AMDGPU_GFX_TCX_FIFO_ACKB4, 3224 AMDGPU_GFX_TCX_FIFO_ACKB5, 3225 AMDGPU_GFX_TCX_FIFO_ACKB6, 3226 AMDGPU_GFX_TCX_FIFO_ACKB7, 3227 AMDGPU_GFX_TCX_FIFO_ACKD0, 3228 AMDGPU_GFX_TCX_FIFO_ACKD1, 3229 AMDGPU_GFX_TCX_FIFO_ACKD2, 3230 AMDGPU_GFX_TCX_FIFO_ACKD3, 3231 AMDGPU_GFX_TCX_FIFO_ACKD4, 3232 AMDGPU_GFX_TCX_FIFO_ACKD5, 3233 AMDGPU_GFX_TCX_FIFO_ACKD6, 3234 AMDGPU_GFX_TCX_FIFO_ACKD7, 3235 AMDGPU_GFX_TCX_DST_FIFOA0, 3236 AMDGPU_GFX_TCX_DST_FIFOA1, 3237 AMDGPU_GFX_TCX_DST_FIFOA2, 3238 AMDGPU_GFX_TCX_DST_FIFOA3, 3239 AMDGPU_GFX_TCX_DST_FIFOA4, 3240 AMDGPU_GFX_TCX_DST_FIFOA5, 3241 AMDGPU_GFX_TCX_DST_FIFOA6, 3242 AMDGPU_GFX_TCX_DST_FIFOA7, 3243 AMDGPU_GFX_TCX_DST_FIFOB0, 3244 AMDGPU_GFX_TCX_DST_FIFOB1, 3245 AMDGPU_GFX_TCX_DST_FIFOB2, 3246 AMDGPU_GFX_TCX_DST_FIFOB3, 3247 AMDGPU_GFX_TCX_DST_FIFOB4, 3248 AMDGPU_GFX_TCX_DST_FIFOB5, 3249 AMDGPU_GFX_TCX_DST_FIFOB6, 3250 AMDGPU_GFX_TCX_DST_FIFOB7, 3251 AMDGPU_GFX_TCX_DST_FIFOD0, 3252 AMDGPU_GFX_TCX_DST_FIFOD1, 3253 AMDGPU_GFX_TCX_DST_FIFOD2, 3254 AMDGPU_GFX_TCX_DST_FIFOD3, 3255 AMDGPU_GFX_TCX_DST_FIFOD4, 3256 AMDGPU_GFX_TCX_DST_FIFOD5, 3257 AMDGPU_GFX_TCX_DST_FIFOD6, 3258 AMDGPU_GFX_TCX_DST_FIFOD7, 3259 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3260 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3261 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3262 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3263 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3264 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3265 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3266 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3267 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3268 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3269 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3270 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3271 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3272 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3273 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3274 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3275 }; 3276 3277 enum amdgpu_gfx_atc_l2_ras_mem_id { 3278 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3279 }; 3280 3281 enum amdgpu_gfx_utcl2_ras_mem_id { 3282 AMDGPU_GFX_UTCL2_MEM0 = 0, 3283 }; 3284 3285 enum amdgpu_gfx_vml2_ras_mem_id { 3286 AMDGPU_GFX_VML2_MEM0 = 0, 3287 }; 3288 3289 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3290 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3291 }; 3292 3293 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3294 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3295 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3296 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3297 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3298 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3299 }; 3300 3301 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3302 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3303 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3304 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3305 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3306 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3307 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3308 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3309 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3310 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3311 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3312 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3313 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3314 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3315 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3316 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3317 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3318 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3319 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3320 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3321 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3322 }; 3323 3324 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3325 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3326 }; 3327 3328 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3329 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3330 }; 3331 3332 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3333 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3334 }; 3335 3336 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3337 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3338 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3339 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3340 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3341 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3342 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3343 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3344 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3345 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3346 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3347 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3348 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3349 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3350 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3351 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3352 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3353 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3354 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3355 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3356 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3357 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3358 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3359 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3360 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3361 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3362 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3363 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3364 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3365 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3366 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3367 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3368 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3369 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3370 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3371 }; 3372 3373 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3374 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3375 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3376 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3377 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3378 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3379 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3380 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3381 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3382 }; 3383 3384 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3385 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3386 }; 3387 3388 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3389 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3390 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3391 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3392 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3393 }; 3394 3395 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3396 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3397 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3398 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3399 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3400 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3401 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3402 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3403 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3404 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3405 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3406 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3407 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3408 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3409 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3410 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3411 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3412 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3413 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3414 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3415 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3416 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3417 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3418 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3419 }; 3420 3421 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3422 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3423 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3424 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3425 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3426 }; 3427 3428 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3429 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3430 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3431 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3432 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3433 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3434 }; 3435 3436 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3437 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3438 }; 3439 3440 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3441 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3442 }; 3443 3444 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3445 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3446 }; 3447 3448 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3449 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3450 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3451 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3452 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3453 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3454 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3455 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3456 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3457 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3458 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3459 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3460 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3461 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3462 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3463 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3464 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3465 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3466 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3467 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3468 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3469 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3470 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3471 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3472 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3473 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3474 }; 3475 3476 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3477 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3478 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3479 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3480 }; 3481 3482 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3483 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3484 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3485 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3486 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3487 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3488 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3489 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3490 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3491 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3492 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3493 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3494 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3495 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3496 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3497 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3498 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3499 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3500 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3501 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3502 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3503 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3504 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3505 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3506 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3507 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3508 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3509 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3510 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3511 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3512 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3513 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3514 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3515 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3516 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3517 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3518 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3519 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3520 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3521 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3522 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3523 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3524 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3525 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3526 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3527 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3528 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3529 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3530 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3531 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3532 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3533 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3534 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3535 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3536 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3537 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3538 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3539 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3540 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3541 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3542 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3543 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3544 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3545 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3546 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3547 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3548 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3549 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3550 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3551 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3552 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3553 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3554 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3555 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3556 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3557 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3558 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3559 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3560 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3561 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3562 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3563 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3564 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3565 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3566 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3567 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3568 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3569 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3570 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3571 }; 3572 3573 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3574 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3575 }; 3576 3577 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3578 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3579 }; 3580 3581 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3582 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3583 }; 3584 3585 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3586 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3587 }; 3588 3589 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3590 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3591 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3592 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3593 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3594 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3595 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3596 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3597 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3598 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3599 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3600 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3601 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3602 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3603 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3604 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3605 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3606 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3607 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3608 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3609 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3610 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3612 }; 3613 3614 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3615 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3616 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3617 AMDGPU_GFX_RLC_MEM, 1}, 3618 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3619 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3620 AMDGPU_GFX_CP_MEM, 1}, 3621 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3622 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3623 AMDGPU_GFX_CP_MEM, 1}, 3624 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3625 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3626 AMDGPU_GFX_CP_MEM, 1}, 3627 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3628 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3629 AMDGPU_GFX_GDS_MEM, 1}, 3630 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3631 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3632 AMDGPU_GFX_GC_CANE_MEM, 1}, 3633 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3634 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3635 AMDGPU_GFX_SPI_MEM, 8}, 3636 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3637 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3638 AMDGPU_GFX_SP_MEM, 1}, 3639 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3640 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3641 AMDGPU_GFX_SP_MEM, 1}, 3642 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3643 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3644 AMDGPU_GFX_SQ_MEM, 8}, 3645 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3646 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3647 AMDGPU_GFX_SQC_MEM, 8}, 3648 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3649 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3650 AMDGPU_GFX_TCX_MEM, 1}, 3651 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3652 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3653 AMDGPU_GFX_TCC_MEM, 1}, 3654 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3655 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3656 AMDGPU_GFX_TA_MEM, 8}, 3657 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3658 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3659 AMDGPU_GFX_TCI_MEM, 1}, 3660 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3661 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3662 AMDGPU_GFX_TCP_MEM, 8}, 3663 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3664 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3665 AMDGPU_GFX_TD_MEM, 8}, 3666 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3667 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3668 AMDGPU_GFX_GCEA_MEM, 1}, 3669 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3670 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3671 AMDGPU_GFX_LDS_MEM, 1}, 3672 }; 3673 3674 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3675 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3676 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3677 AMDGPU_GFX_RLC_MEM, 1}, 3678 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3679 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3680 AMDGPU_GFX_CP_MEM, 1}, 3681 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3682 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3683 AMDGPU_GFX_CP_MEM, 1}, 3684 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3685 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3686 AMDGPU_GFX_CP_MEM, 1}, 3687 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3688 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3689 AMDGPU_GFX_GDS_MEM, 1}, 3690 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3691 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3692 AMDGPU_GFX_GC_CANE_MEM, 1}, 3693 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3694 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3695 AMDGPU_GFX_SPI_MEM, 8}, 3696 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3697 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3698 AMDGPU_GFX_SP_MEM, 1}, 3699 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3700 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3701 AMDGPU_GFX_SP_MEM, 1}, 3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3703 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3704 AMDGPU_GFX_SQ_MEM, 8}, 3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3706 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3707 AMDGPU_GFX_SQC_MEM, 8}, 3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3709 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3710 AMDGPU_GFX_TCX_MEM, 1}, 3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3712 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3713 AMDGPU_GFX_TCC_MEM, 1}, 3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3715 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3716 AMDGPU_GFX_TA_MEM, 8}, 3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3718 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3719 AMDGPU_GFX_TCI_MEM, 1}, 3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3721 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3722 AMDGPU_GFX_TCP_MEM, 8}, 3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3724 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3725 AMDGPU_GFX_TD_MEM, 8}, 3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3727 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3728 AMDGPU_GFX_TCA_MEM, 1}, 3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3730 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3731 AMDGPU_GFX_GCEA_MEM, 1}, 3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3733 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3734 AMDGPU_GFX_LDS_MEM, 1}, 3735 }; 3736 3737 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3738 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3739 }; 3740 3741 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3742 void *ras_error_status, int xcc_id) 3743 { 3744 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3745 unsigned long ce_count = 0, ue_count = 0; 3746 uint32_t i, j, k; 3747 3748 mutex_lock(&adev->grbm_idx_mutex); 3749 3750 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3751 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3752 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3753 /* no need to select if instance number is 1 */ 3754 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3755 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3756 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3757 3758 amdgpu_ras_inst_query_ras_error_count(adev, 3759 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3760 1, 3761 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3762 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3763 GET_INST(GC, xcc_id), 3764 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3765 &ce_count); 3766 3767 amdgpu_ras_inst_query_ras_error_count(adev, 3768 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3769 1, 3770 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3771 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3772 GET_INST(GC, xcc_id), 3773 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3774 &ue_count); 3775 } 3776 } 3777 } 3778 3779 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3780 xcc_id); 3781 mutex_unlock(&adev->grbm_idx_mutex); 3782 3783 /* the caller should make sure initialize value of 3784 * err_data->ue_count and err_data->ce_count 3785 */ 3786 err_data->ce_count += ce_count; 3787 err_data->ue_count += ue_count; 3788 } 3789 3790 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3791 void *ras_error_status, int xcc_id) 3792 { 3793 uint32_t i, j, k; 3794 3795 mutex_lock(&adev->grbm_idx_mutex); 3796 3797 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3798 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3799 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3800 /* no need to select if instance number is 1 */ 3801 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3802 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3803 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3804 3805 amdgpu_ras_inst_reset_ras_error_count(adev, 3806 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3807 1, 3808 GET_INST(GC, xcc_id)); 3809 3810 amdgpu_ras_inst_reset_ras_error_count(adev, 3811 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3812 1, 3813 GET_INST(GC, xcc_id)); 3814 } 3815 } 3816 } 3817 3818 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3819 xcc_id); 3820 mutex_unlock(&adev->grbm_idx_mutex); 3821 } 3822 3823 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3824 int xcc_id) 3825 { 3826 uint32_t i, j; 3827 uint32_t reg_value; 3828 3829 mutex_lock(&adev->grbm_idx_mutex); 3830 3831 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3832 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3833 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3834 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3835 regGCEA_ERR_STATUS); 3836 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3837 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3838 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3839 dev_warn(adev->dev, 3840 "GCEA err detected at instance: %d, status: 0x%x!\n", 3841 j, reg_value); 3842 } 3843 /* clear after read */ 3844 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3845 CLEAR_ERROR_STATUS, 0x1); 3846 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3847 reg_value); 3848 } 3849 } 3850 3851 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3852 xcc_id); 3853 mutex_unlock(&adev->grbm_idx_mutex); 3854 } 3855 3856 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3857 int xcc_id) 3858 { 3859 uint32_t data; 3860 3861 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3862 if (data) { 3863 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3864 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3865 } 3866 3867 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3868 if (data) { 3869 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3870 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3871 } 3872 3873 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3874 regVML2_WALKER_MEM_ECC_STATUS); 3875 if (data) { 3876 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3877 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3878 0x3); 3879 } 3880 } 3881 3882 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3883 uint32_t status, int xcc_id) 3884 { 3885 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3886 uint32_t i, simd, wave; 3887 uint32_t wave_status; 3888 uint32_t wave_pc_lo, wave_pc_hi; 3889 uint32_t wave_exec_lo, wave_exec_hi; 3890 uint32_t wave_inst_dw0, wave_inst_dw1; 3891 uint32_t wave_ib_sts; 3892 3893 for (i = 0; i < 32; i++) { 3894 if (!((i << 1) & status)) 3895 continue; 3896 3897 simd = i / cu_info->max_waves_per_simd; 3898 wave = i % cu_info->max_waves_per_simd; 3899 3900 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3901 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3902 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3903 wave_exec_lo = 3904 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3905 wave_exec_hi = 3906 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3907 wave_inst_dw0 = 3908 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3909 wave_inst_dw1 = 3910 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3911 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3912 3913 dev_info( 3914 adev->dev, 3915 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3916 simd, wave, wave_status, 3917 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3918 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3919 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3920 wave_ib_sts); 3921 } 3922 } 3923 3924 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3925 int xcc_id) 3926 { 3927 uint32_t se_idx, sh_idx, cu_idx; 3928 uint32_t status; 3929 3930 mutex_lock(&adev->grbm_idx_mutex); 3931 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3932 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3933 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3934 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3935 cu_idx, xcc_id); 3936 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3937 regSQ_TIMEOUT_STATUS); 3938 if (status != 0) { 3939 dev_info( 3940 adev->dev, 3941 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3942 se_idx, sh_idx, cu_idx); 3943 gfx_v9_4_3_log_cu_timeout_status( 3944 adev, status, xcc_id); 3945 } 3946 /* clear old status */ 3947 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3948 regSQ_TIMEOUT_STATUS, 0); 3949 } 3950 } 3951 } 3952 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3953 xcc_id); 3954 mutex_unlock(&adev->grbm_idx_mutex); 3955 } 3956 3957 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3958 void *ras_error_status, int xcc_id) 3959 { 3960 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3961 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3962 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3963 } 3964 3965 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3966 int xcc_id) 3967 { 3968 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3969 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3970 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3971 } 3972 3973 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3974 int xcc_id) 3975 { 3976 uint32_t i, j; 3977 uint32_t value; 3978 3979 mutex_lock(&adev->grbm_idx_mutex); 3980 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3981 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3982 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3983 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 3984 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 3985 CLEAR_ERROR_STATUS, 0x1); 3986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 3987 } 3988 } 3989 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3990 xcc_id); 3991 mutex_unlock(&adev->grbm_idx_mutex); 3992 } 3993 3994 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 3995 int xcc_id) 3996 { 3997 uint32_t se_idx, sh_idx, cu_idx; 3998 3999 mutex_lock(&adev->grbm_idx_mutex); 4000 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 4001 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 4002 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 4003 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 4004 cu_idx, xcc_id); 4005 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4006 regSQ_TIMEOUT_STATUS, 0); 4007 } 4008 } 4009 } 4010 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4011 xcc_id); 4012 mutex_unlock(&adev->grbm_idx_mutex); 4013 } 4014 4015 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4016 void *ras_error_status, int xcc_id) 4017 { 4018 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4019 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4020 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4021 } 4022 4023 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4024 void *ras_error_status) 4025 { 4026 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4027 gfx_v9_4_3_inst_query_ras_err_count); 4028 } 4029 4030 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4031 { 4032 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4033 } 4034 4035 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4036 { 4037 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4038 } 4039 4040 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4041 { 4042 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4043 } 4044 4045 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4046 .name = "gfx_v9_4_3", 4047 .early_init = gfx_v9_4_3_early_init, 4048 .late_init = gfx_v9_4_3_late_init, 4049 .sw_init = gfx_v9_4_3_sw_init, 4050 .sw_fini = gfx_v9_4_3_sw_fini, 4051 .hw_init = gfx_v9_4_3_hw_init, 4052 .hw_fini = gfx_v9_4_3_hw_fini, 4053 .suspend = gfx_v9_4_3_suspend, 4054 .resume = gfx_v9_4_3_resume, 4055 .is_idle = gfx_v9_4_3_is_idle, 4056 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4057 .soft_reset = gfx_v9_4_3_soft_reset, 4058 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4059 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4060 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4061 }; 4062 4063 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4064 .type = AMDGPU_RING_TYPE_COMPUTE, 4065 .align_mask = 0xff, 4066 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4067 .support_64bit_ptrs = true, 4068 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4069 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4070 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4071 .emit_frame_size = 4072 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4073 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4074 5 + /* hdp invalidate */ 4075 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4076 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4077 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4078 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4079 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4080 7 + /* gfx_v9_4_3_emit_mem_sync */ 4081 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4082 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4083 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4084 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4085 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4086 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4087 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4088 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4089 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4090 .test_ring = gfx_v9_4_3_ring_test_ring, 4091 .test_ib = gfx_v9_4_3_ring_test_ib, 4092 .insert_nop = amdgpu_ring_insert_nop, 4093 .pad_ib = amdgpu_ring_generic_pad_ib, 4094 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4095 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4096 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4097 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4098 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4099 }; 4100 4101 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4102 .type = AMDGPU_RING_TYPE_KIQ, 4103 .align_mask = 0xff, 4104 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4105 .support_64bit_ptrs = true, 4106 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4107 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4108 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4109 .emit_frame_size = 4110 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4111 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4112 5 + /* hdp invalidate */ 4113 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4114 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4115 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4116 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4117 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4118 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4119 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4120 .test_ring = gfx_v9_4_3_ring_test_ring, 4121 .insert_nop = amdgpu_ring_insert_nop, 4122 .pad_ib = amdgpu_ring_generic_pad_ib, 4123 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4124 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4125 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4126 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4127 }; 4128 4129 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4130 { 4131 int i, j, num_xcc; 4132 4133 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4134 for (i = 0; i < num_xcc; i++) { 4135 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4136 4137 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4138 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4139 = &gfx_v9_4_3_ring_funcs_compute; 4140 } 4141 } 4142 4143 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4144 .set = gfx_v9_4_3_set_eop_interrupt_state, 4145 .process = gfx_v9_4_3_eop_irq, 4146 }; 4147 4148 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4149 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4150 .process = gfx_v9_4_3_priv_reg_irq, 4151 }; 4152 4153 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4154 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4155 .process = gfx_v9_4_3_priv_inst_irq, 4156 }; 4157 4158 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4159 { 4160 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4161 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4162 4163 adev->gfx.priv_reg_irq.num_types = 1; 4164 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4165 4166 adev->gfx.priv_inst_irq.num_types = 1; 4167 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4168 } 4169 4170 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4171 { 4172 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4173 } 4174 4175 4176 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4177 { 4178 /* init asci gds info */ 4179 switch (adev->ip_versions[GC_HWIP][0]) { 4180 case IP_VERSION(9, 4, 3): 4181 /* 9.4.3 removed all the GDS internal memory, 4182 * only support GWS opcode in kernel, like barrier 4183 * semaphore.etc */ 4184 adev->gds.gds_size = 0; 4185 break; 4186 default: 4187 adev->gds.gds_size = 0x10000; 4188 break; 4189 } 4190 4191 switch (adev->ip_versions[GC_HWIP][0]) { 4192 case IP_VERSION(9, 4, 3): 4193 /* deprecated for 9.4.3, no usage at all */ 4194 adev->gds.gds_compute_max_wave_id = 0; 4195 break; 4196 default: 4197 /* this really depends on the chip */ 4198 adev->gds.gds_compute_max_wave_id = 0x7ff; 4199 break; 4200 } 4201 4202 adev->gds.gws_size = 64; 4203 adev->gds.oa_size = 16; 4204 } 4205 4206 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4207 u32 bitmap) 4208 { 4209 u32 data; 4210 4211 if (!bitmap) 4212 return; 4213 4214 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4215 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4216 4217 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4218 } 4219 4220 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4221 { 4222 u32 data, mask; 4223 4224 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4225 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4226 4227 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4228 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4229 4230 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4231 4232 return (~data) & mask; 4233 } 4234 4235 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4236 struct amdgpu_cu_info *cu_info) 4237 { 4238 int i, j, k, counter, active_cu_number = 0; 4239 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4240 unsigned disable_masks[4 * 4]; 4241 4242 if (!adev || !cu_info) 4243 return -EINVAL; 4244 4245 /* 4246 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4247 */ 4248 if (adev->gfx.config.max_shader_engines * 4249 adev->gfx.config.max_sh_per_se > 16) 4250 return -EINVAL; 4251 4252 amdgpu_gfx_parse_disable_cu(disable_masks, 4253 adev->gfx.config.max_shader_engines, 4254 adev->gfx.config.max_sh_per_se); 4255 4256 mutex_lock(&adev->grbm_idx_mutex); 4257 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4258 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4259 mask = 1; 4260 ao_bitmap = 0; 4261 counter = 0; 4262 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4263 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4264 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4265 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4266 4267 /* 4268 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4269 * 4x4 size array, and it's usually suitable for Vega 4270 * ASICs which has 4*2 SE/SH layout. 4271 * But for Arcturus, SE/SH layout is changed to 8*1. 4272 * To mostly reduce the impact, we make it compatible 4273 * with current bitmap array as below: 4274 * SE4,SH0 --> bitmap[0][1] 4275 * SE5,SH0 --> bitmap[1][1] 4276 * SE6,SH0 --> bitmap[2][1] 4277 * SE7,SH0 --> bitmap[3][1] 4278 */ 4279 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4280 4281 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4282 if (bitmap & mask) { 4283 if (counter < adev->gfx.config.max_cu_per_sh) 4284 ao_bitmap |= mask; 4285 counter++; 4286 } 4287 mask <<= 1; 4288 } 4289 active_cu_number += counter; 4290 if (i < 2 && j < 2) 4291 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4292 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4293 } 4294 } 4295 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4296 0); 4297 mutex_unlock(&adev->grbm_idx_mutex); 4298 4299 cu_info->number = active_cu_number; 4300 cu_info->ao_cu_mask = ao_cu_mask; 4301 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4302 4303 return 0; 4304 } 4305 4306 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4307 .type = AMD_IP_BLOCK_TYPE_GFX, 4308 .major = 9, 4309 .minor = 4, 4310 .rev = 0, 4311 .funcs = &gfx_v9_4_3_ip_funcs, 4312 }; 4313 4314 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4315 { 4316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4317 uint32_t tmp_mask; 4318 int i, r; 4319 4320 /* TODO : Initialize golden regs */ 4321 /* gfx_v9_4_3_init_golden_registers(adev); */ 4322 4323 tmp_mask = inst_mask; 4324 for_each_inst(i, tmp_mask) 4325 gfx_v9_4_3_xcc_constants_init(adev, i); 4326 4327 if (!amdgpu_sriov_vf(adev)) { 4328 tmp_mask = inst_mask; 4329 for_each_inst(i, tmp_mask) { 4330 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4331 if (r) 4332 return r; 4333 } 4334 } 4335 4336 tmp_mask = inst_mask; 4337 for_each_inst(i, tmp_mask) { 4338 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4339 if (r) 4340 return r; 4341 } 4342 4343 return 0; 4344 } 4345 4346 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4347 { 4348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4349 int i; 4350 4351 for_each_inst(i, inst_mask) 4352 gfx_v9_4_3_xcc_fini(adev, i); 4353 4354 return 0; 4355 } 4356 4357 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4358 .suspend = &gfx_v9_4_3_xcp_suspend, 4359 .resume = &gfx_v9_4_3_xcp_resume 4360 }; 4361 4362 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4363 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4364 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4365 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4366 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4367 }; 4368 4369 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4370 .ras_block = { 4371 .hw_ops = &gfx_v9_4_3_ras_ops, 4372 }, 4373 }; 4374