1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "clearstate_gfx9.h" 33 #include "v9_structs.h" 34 35 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 36 37 #include "gc/gc_9_4_3_offset.h" 38 #include "gc/gc_9_4_3_sh_mask.h" 39 40 #include "gfx_v9_4_3.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 static const struct soc15_reg_golden golden_settings_gc_9_4_3[] = { 49 50 }; 51 52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 57 struct amdgpu_cu_info *cu_info); 58 59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 60 uint64_t queue_mask) 61 { 62 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 63 amdgpu_ring_write(kiq_ring, 64 PACKET3_SET_RESOURCES_VMID_MASK(0) | 65 /* vmid_mask:0* queue_type:0 (KIQ) */ 66 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 67 amdgpu_ring_write(kiq_ring, 68 lower_32_bits(queue_mask)); /* queue mask lo */ 69 amdgpu_ring_write(kiq_ring, 70 upper_32_bits(queue_mask)); /* queue mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 73 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 74 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 75 } 76 77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring) 79 { 80 struct amdgpu_device *adev = kiq_ring->adev; 81 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 82 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 83 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 84 85 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 86 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 87 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 88 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 89 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 90 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 91 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 92 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 93 /*queue_type: normal compute queue */ 94 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 95 /* alloc format: all_on_one_pipe */ 96 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 97 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 98 /* num_queues: must be 1 */ 99 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 100 amdgpu_ring_write(kiq_ring, 101 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 105 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 106 } 107 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 109 struct amdgpu_ring *ring, 110 enum amdgpu_unmap_queues_action action, 111 u64 gpu_addr, u64 seq) 112 { 113 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 114 115 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 116 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 117 PACKET3_UNMAP_QUEUES_ACTION(action) | 118 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 119 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 120 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 121 amdgpu_ring_write(kiq_ring, 122 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 123 124 if (action == PREEMPT_QUEUES_NO_UNMAP) { 125 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 126 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, seq); 128 } else { 129 amdgpu_ring_write(kiq_ring, 0); 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 } 133 } 134 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 u64 addr, 138 u64 seq) 139 { 140 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 141 142 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 143 amdgpu_ring_write(kiq_ring, 144 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 145 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 146 PACKET3_QUERY_STATUS_COMMAND(2)); 147 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 148 amdgpu_ring_write(kiq_ring, 149 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 150 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 155 } 156 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 158 uint16_t pasid, uint32_t flush_type, 159 bool all_hub) 160 { 161 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 162 amdgpu_ring_write(kiq_ring, 163 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 164 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 165 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 166 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 167 } 168 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 170 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 171 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 172 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 173 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 174 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 175 .set_resources_size = 8, 176 .map_queues_size = 7, 177 .unmap_queues_size = 6, 178 .query_status_size = 7, 179 .invalidate_tlbs_size = 2, 180 }; 181 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 183 { 184 int i; 185 for (i = 0; i < adev->gfx.num_xcd; i++) 186 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 187 } 188 189 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 190 { 191 192 } 193 194 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 195 bool wc, uint32_t reg, uint32_t val) 196 { 197 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 198 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 199 WRITE_DATA_DST_SEL(0) | 200 (wc ? WR_CONFIRM : 0)); 201 amdgpu_ring_write(ring, reg); 202 amdgpu_ring_write(ring, 0); 203 amdgpu_ring_write(ring, val); 204 } 205 206 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 207 int mem_space, int opt, uint32_t addr0, 208 uint32_t addr1, uint32_t ref, uint32_t mask, 209 uint32_t inv) 210 { 211 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 212 amdgpu_ring_write(ring, 213 /* memory (1) or register (0) */ 214 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 215 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 216 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 217 WAIT_REG_MEM_ENGINE(eng_sel))); 218 219 if (mem_space) 220 BUG_ON(addr0 & 0x3); /* Dword align */ 221 amdgpu_ring_write(ring, addr0); 222 amdgpu_ring_write(ring, addr1); 223 amdgpu_ring_write(ring, ref); 224 amdgpu_ring_write(ring, mask); 225 amdgpu_ring_write(ring, inv); /* poll interval */ 226 } 227 228 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 229 { 230 struct amdgpu_device *adev = ring->adev; 231 uint32_t tmp = 0; 232 unsigned i; 233 int r; 234 235 WREG32_SOC15(GC, 0, regSCRATCH_REG0, 0xCAFEDEAD); 236 r = amdgpu_ring_alloc(ring, 3); 237 if (r) 238 return r; 239 240 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 241 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0) - 242 PACKET3_SET_UCONFIG_REG_START); 243 amdgpu_ring_write(ring, 0xDEADBEEF); 244 amdgpu_ring_commit(ring); 245 246 for (i = 0; i < adev->usec_timeout; i++) { 247 tmp = RREG32_SOC15(GC, 0, regSCRATCH_REG0); 248 if (tmp == 0xDEADBEEF) 249 break; 250 udelay(1); 251 } 252 253 if (i >= adev->usec_timeout) 254 r = -ETIMEDOUT; 255 return r; 256 } 257 258 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 259 { 260 struct amdgpu_device *adev = ring->adev; 261 struct amdgpu_ib ib; 262 struct dma_fence *f = NULL; 263 264 unsigned index; 265 uint64_t gpu_addr; 266 uint32_t tmp; 267 long r; 268 269 r = amdgpu_device_wb_get(adev, &index); 270 if (r) 271 return r; 272 273 gpu_addr = adev->wb.gpu_addr + (index * 4); 274 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 275 memset(&ib, 0, sizeof(ib)); 276 r = amdgpu_ib_get(adev, NULL, 16, 277 AMDGPU_IB_POOL_DIRECT, &ib); 278 if (r) 279 goto err1; 280 281 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 282 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 283 ib.ptr[2] = lower_32_bits(gpu_addr); 284 ib.ptr[3] = upper_32_bits(gpu_addr); 285 ib.ptr[4] = 0xDEADBEEF; 286 ib.length_dw = 5; 287 288 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 289 if (r) 290 goto err2; 291 292 r = dma_fence_wait_timeout(f, false, timeout); 293 if (r == 0) { 294 r = -ETIMEDOUT; 295 goto err2; 296 } else if (r < 0) { 297 goto err2; 298 } 299 300 tmp = adev->wb.wb[index]; 301 if (tmp == 0xDEADBEEF) 302 r = 0; 303 else 304 r = -EINVAL; 305 306 err2: 307 amdgpu_ib_free(adev, &ib, NULL); 308 dma_fence_put(f); 309 err1: 310 amdgpu_device_wb_free(adev, index); 311 return r; 312 } 313 314 315 /* This value might differs per partition */ 316 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 317 { 318 uint64_t clock; 319 320 amdgpu_gfx_off_ctrl(adev, false); 321 mutex_lock(&adev->gfx.gpu_clock_mutex); 322 WREG32_SOC15(GC, 0, regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 323 clock = (uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_LSB) | 324 ((uint64_t)RREG32_SOC15(GC, 0, regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 325 mutex_unlock(&adev->gfx.gpu_clock_mutex); 326 amdgpu_gfx_off_ctrl(adev, true); 327 328 return clock; 329 } 330 331 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 332 { 333 amdgpu_ucode_release(&adev->gfx.pfp_fw); 334 amdgpu_ucode_release(&adev->gfx.me_fw); 335 amdgpu_ucode_release(&adev->gfx.ce_fw); 336 amdgpu_ucode_release(&adev->gfx.rlc_fw); 337 amdgpu_ucode_release(&adev->gfx.mec_fw); 338 amdgpu_ucode_release(&adev->gfx.mec2_fw); 339 340 kfree(adev->gfx.rlc.register_list_format); 341 } 342 343 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 344 const char *chip_name) 345 { 346 char fw_name[30]; 347 int err; 348 const struct rlc_firmware_header_v2_0 *rlc_hdr; 349 uint16_t version_major; 350 uint16_t version_minor; 351 352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 353 354 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 355 if (err) 356 goto out; 357 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 358 359 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 360 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 361 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 362 out: 363 if (err) 364 amdgpu_ucode_release(&adev->gfx.rlc_fw); 365 366 return err; 367 } 368 369 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 370 { 371 return true; 372 } 373 374 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 375 { 376 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 377 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 378 } 379 380 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 381 const char *chip_name) 382 { 383 char fw_name[30]; 384 int err; 385 386 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 387 388 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 389 if (err) 390 goto out; 391 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 392 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 393 394 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 395 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 396 397 gfx_v9_4_3_check_if_need_gfxoff(adev); 398 399 out: 400 if (err) 401 amdgpu_ucode_release(&adev->gfx.mec_fw); 402 return err; 403 } 404 405 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 406 { 407 const char *chip_name; 408 int r; 409 410 chip_name = "gc_9_4_3"; 411 412 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 413 if (r) 414 return r; 415 416 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 417 if (r) 418 return r; 419 420 return r; 421 } 422 423 static u32 gfx_v9_4_3_get_csb_size(struct amdgpu_device *adev) 424 { 425 u32 count = 0; 426 const struct cs_section_def *sect = NULL; 427 const struct cs_extent_def *ext = NULL; 428 429 /* begin clear state */ 430 count += 2; 431 /* context control state */ 432 count += 3; 433 434 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 435 for (ext = sect->section; ext->extent != NULL; ++ext) { 436 if (sect->id == SECT_CONTEXT) 437 count += 2 + ext->reg_count; 438 else 439 return 0; 440 } 441 } 442 443 /* end clear state */ 444 count += 2; 445 /* clear state */ 446 count += 2; 447 448 return count; 449 } 450 451 static void gfx_v9_4_3_get_csb_buffer(struct amdgpu_device *adev, 452 volatile u32 *buffer) 453 { 454 u32 count = 0, i; 455 const struct cs_section_def *sect = NULL; 456 const struct cs_extent_def *ext = NULL; 457 458 if (adev->gfx.rlc.cs_data == NULL) 459 return; 460 if (buffer == NULL) 461 return; 462 463 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 464 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 465 466 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 467 buffer[count++] = cpu_to_le32(0x80000000); 468 buffer[count++] = cpu_to_le32(0x80000000); 469 470 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 471 for (ext = sect->section; ext->extent != NULL; ++ext) { 472 if (sect->id == SECT_CONTEXT) { 473 buffer[count++] = 474 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 475 buffer[count++] = cpu_to_le32(ext->reg_index - 476 PACKET3_SET_CONTEXT_REG_START); 477 for (i = 0; i < ext->reg_count; i++) 478 buffer[count++] = cpu_to_le32(ext->extent[i]); 479 } else { 480 return; 481 } 482 } 483 } 484 485 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 486 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 487 488 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 489 buffer[count++] = cpu_to_le32(0); 490 } 491 492 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 493 { 494 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 495 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 496 } 497 498 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 499 { 500 int r, i; 501 u32 *hpd; 502 const __le32 *fw_data; 503 unsigned fw_size; 504 u32 *fw; 505 size_t mec_hpd_size; 506 507 const struct gfx_firmware_header_v1_0 *mec_hdr; 508 509 for (i = 0; i < adev->gfx.num_xcd; i++) 510 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 511 AMDGPU_MAX_COMPUTE_QUEUES); 512 513 /* take ownership of the relevant compute queues */ 514 amdgpu_gfx_compute_queue_acquire(adev); 515 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 516 if (mec_hpd_size) { 517 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 518 AMDGPU_GEM_DOMAIN_VRAM, 519 &adev->gfx.mec.hpd_eop_obj, 520 &adev->gfx.mec.hpd_eop_gpu_addr, 521 (void **)&hpd); 522 if (r) { 523 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 524 gfx_v9_4_3_mec_fini(adev); 525 return r; 526 } 527 528 if (amdgpu_emu_mode == 1) { 529 for (i = 0; i < mec_hpd_size / 4; i++) { 530 memset((void *)(hpd + i), 0, 4); 531 if (i % 50 == 0) 532 msleep(1); 533 } 534 } else { 535 memset(hpd, 0, mec_hpd_size); 536 } 537 538 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 539 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 540 } 541 542 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 543 544 fw_data = (const __le32 *) 545 (adev->gfx.mec_fw->data + 546 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 547 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 548 549 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 551 &adev->gfx.mec.mec_fw_obj, 552 &adev->gfx.mec.mec_fw_gpu_addr, 553 (void **)&fw); 554 if (r) { 555 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 556 gfx_v9_4_3_mec_fini(adev); 557 return r; 558 } 559 560 memcpy(fw, fw_data, fw_size); 561 562 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 563 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 564 565 return 0; 566 } 567 568 static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev, 569 u32 se_num, 570 u32 sh_num, 571 u32 instance, 572 int xcc_id) 573 { 574 u32 data; 575 576 if (instance == 0xffffffff) 577 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 578 INSTANCE_BROADCAST_WRITES, 1); 579 else 580 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 581 INSTANCE_INDEX, instance); 582 583 if (se_num == 0xffffffff) 584 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 585 SE_BROADCAST_WRITES, 1); 586 else 587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 588 589 if (sh_num == 0xffffffff) 590 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 591 SH_BROADCAST_WRITES, 1); 592 else 593 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 594 595 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, xcc_id, regGRBM_GFX_INDEX, data); 596 } 597 598 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 599 { 600 WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX, 601 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 602 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 603 (address << SQ_IND_INDEX__INDEX__SHIFT) | 604 (SQ_IND_INDEX__FORCE_READ_MASK)); 605 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); 606 } 607 608 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 609 uint32_t wave, uint32_t thread, 610 uint32_t regno, uint32_t num, uint32_t *out) 611 { 612 WREG32_SOC15_RLC(GC, 0, regSQ_IND_INDEX, 613 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 614 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 615 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 616 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 617 (SQ_IND_INDEX__FORCE_READ_MASK) | 618 (SQ_IND_INDEX__AUTO_INCR_MASK)); 619 while (num--) 620 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); 621 } 622 623 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 624 uint32_t simd, uint32_t wave, 625 uint32_t *dst, int *no_fields) 626 { 627 /* type 1 wave data */ 628 dst[(*no_fields)++] = 1; 629 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 630 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 631 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 632 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 633 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 634 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 635 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 636 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 637 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 638 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 639 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 640 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 641 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 642 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 643 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 644 } 645 646 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 647 uint32_t wave, uint32_t start, 648 uint32_t size, uint32_t *dst) 649 { 650 wave_read_regs(adev, simd, wave, 0, 651 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 652 } 653 654 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 655 uint32_t wave, uint32_t thread, 656 uint32_t start, uint32_t size, 657 uint32_t *dst) 658 { 659 wave_read_regs(adev, simd, wave, thread, 660 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 661 } 662 663 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 664 u32 me, u32 pipe, u32 q, u32 vm) 665 { 666 soc15_grbm_select(adev, me, pipe, q, vm, 0); 667 } 668 669 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 670 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 671 .select_se_sh = &gfx_v9_4_3_select_se_sh, 672 .read_wave_data = &gfx_v9_4_3_read_wave_data, 673 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 674 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 675 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 676 }; 677 678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 679 { 680 u32 gb_addr_config; 681 682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 683 684 switch (adev->ip_versions[GC_HWIP][0]) { 685 case IP_VERSION(9, 4, 3): 686 adev->gfx.config.max_hw_contexts = 8; 687 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 688 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 689 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 690 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 691 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); 692 break; 693 default: 694 BUG(); 695 break; 696 } 697 698 adev->gfx.config.gb_addr_config = gb_addr_config; 699 700 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 701 REG_GET_FIELD( 702 adev->gfx.config.gb_addr_config, 703 GB_ADDR_CONFIG, 704 NUM_PIPES); 705 706 adev->gfx.config.max_tile_pipes = 707 adev->gfx.config.gb_addr_config_fields.num_pipes; 708 709 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 710 REG_GET_FIELD( 711 adev->gfx.config.gb_addr_config, 712 GB_ADDR_CONFIG, 713 NUM_BANKS); 714 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 715 REG_GET_FIELD( 716 adev->gfx.config.gb_addr_config, 717 GB_ADDR_CONFIG, 718 MAX_COMPRESSED_FRAGS); 719 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 720 REG_GET_FIELD( 721 adev->gfx.config.gb_addr_config, 722 GB_ADDR_CONFIG, 723 NUM_RB_PER_SE); 724 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 725 REG_GET_FIELD( 726 adev->gfx.config.gb_addr_config, 727 GB_ADDR_CONFIG, 728 NUM_SHADER_ENGINES); 729 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 730 REG_GET_FIELD( 731 adev->gfx.config.gb_addr_config, 732 GB_ADDR_CONFIG, 733 PIPE_INTERLEAVE_SIZE)); 734 735 return 0; 736 } 737 738 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 739 int xcc_id, int mec, int pipe, int queue) 740 { 741 unsigned irq_type; 742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 743 unsigned int hw_prio; 744 745 ring = &adev->gfx.compute_ring[ring_id]; 746 747 /* mec0 is me1 */ 748 ring->xcc_id = xcc_id; 749 ring->me = mec + 1; 750 ring->pipe = pipe; 751 ring->queue = queue; 752 753 ring->ring_obj = NULL; 754 ring->use_doorbell = true; 755 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 756 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 757 + (ring_id * GFX9_MEC_HPD_SIZE); 758 ring->vm_hub = AMDGPU_GFXHUB_0; 759 sprintf(ring->name, "comp_%d.%d.%d.%d", 760 ring->xcc_id, ring->me, ring->pipe, ring->queue); 761 762 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 763 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 764 + ring->pipe; 765 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 766 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 767 /* type-2 packets are deprecated on MEC, use type-3 instead */ 768 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 769 hw_prio, NULL); 770 } 771 772 static int gfx_v9_4_3_sw_init(void *handle) 773 { 774 int i, j, k, r, ring_id, xcc_id; 775 struct amdgpu_kiq *kiq; 776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 777 778 adev->gfx.mec.num_mec = 2; 779 adev->gfx.mec.num_pipe_per_mec = 4; 780 adev->gfx.mec.num_queue_per_pipe = 8; 781 782 /* EOP Event */ 783 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 784 if (r) 785 return r; 786 787 /* Privileged reg */ 788 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 789 &adev->gfx.priv_reg_irq); 790 if (r) 791 return r; 792 793 /* Privileged inst */ 794 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 795 &adev->gfx.priv_inst_irq); 796 if (r) 797 return r; 798 799 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 800 801 r = adev->gfx.rlc.funcs->init(adev); 802 if (r) { 803 DRM_ERROR("Failed to init rlc BOs!\n"); 804 return r; 805 } 806 807 r = gfx_v9_4_3_mec_init(adev); 808 if (r) { 809 DRM_ERROR("Failed to init MEC BOs!\n"); 810 return r; 811 } 812 813 /* set up the compute queues - allocate horizontally across pipes */ 814 ring_id = 0; 815 for (xcc_id = 0; xcc_id < adev->gfx.num_xcd; xcc_id++) { 816 817 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 818 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 819 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 820 k++) { 821 if (!amdgpu_gfx_is_mec_queue_enabled( 822 adev, xcc_id, i, k, j)) 823 continue; 824 825 r = gfx_v9_4_3_compute_ring_init(adev, 826 ring_id, 827 xcc_id, 828 i, k, j); 829 if (r) 830 return r; 831 832 ring_id++; 833 } 834 } 835 } 836 837 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 838 if (r) { 839 DRM_ERROR("Failed to init KIQ BOs!\n"); 840 return r; 841 } 842 843 kiq = &adev->gfx.kiq[xcc_id]; 844 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 845 if (r) 846 return r; 847 848 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 849 r = amdgpu_gfx_mqd_sw_init(adev, 850 sizeof(struct v9_mqd_allocation), xcc_id); 851 if (r) 852 return r; 853 } 854 855 r = gfx_v9_4_3_gpu_early_init(adev); 856 if (r) 857 return r; 858 859 return 0; 860 } 861 862 static int gfx_v9_4_3_sw_fini(void *handle) 863 { 864 int i; 865 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 866 867 for (i = 0; i < adev->gfx.num_compute_rings * 868 adev->gfx.num_xcd; i++) 869 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 870 871 for (i = 0; i < adev->gfx.num_xcd; i++) { 872 amdgpu_gfx_mqd_sw_fini(adev, i); 873 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 874 amdgpu_gfx_kiq_fini(adev, i); 875 } 876 877 gfx_v9_4_3_mec_fini(adev); 878 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 879 gfx_v9_4_3_free_microcode(adev); 880 881 return 0; 882 } 883 884 static u32 gfx_v9_4_3_get_rb_active_bitmap(struct amdgpu_device *adev) 885 { 886 u32 data, mask; 887 888 data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); 889 data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); 890 891 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 892 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 893 894 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 895 adev->gfx.config.max_sh_per_se); 896 897 return (~data) & mask; 898 } 899 900 static void gfx_v9_4_3_setup_rb(struct amdgpu_device *adev, int xcc_id) 901 { 902 int i, j; 903 u32 data; 904 u32 active_rbs = 0; 905 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 906 adev->gfx.config.max_sh_per_se; 907 908 mutex_lock(&adev->grbm_idx_mutex); 909 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 910 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 911 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 912 data = gfx_v9_4_3_get_rb_active_bitmap(adev); 913 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 914 rb_bitmap_width_per_sh); 915 } 916 } 917 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 918 mutex_unlock(&adev->grbm_idx_mutex); 919 920 adev->gfx.config.backend_enable_mask = active_rbs; 921 adev->gfx.config.num_rbs = hweight32(active_rbs); 922 } 923 924 #define DEFAULT_SH_MEM_BASES (0x6000) 925 static void gfx_v9_4_3_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) 926 { 927 int i; 928 uint32_t sh_mem_config; 929 uint32_t sh_mem_bases; 930 931 /* 932 * Configure apertures: 933 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 934 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 935 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 936 */ 937 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 938 939 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 940 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 941 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 942 943 mutex_lock(&adev->srbm_mutex); 944 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 945 soc15_grbm_select(adev, 0, 0, 0, i, xcc_id); 946 /* CP and shaders */ 947 WREG32_SOC15_RLC(GC, xcc_id, regSH_MEM_CONFIG, sh_mem_config); 948 WREG32_SOC15_RLC(GC, xcc_id, regSH_MEM_BASES, sh_mem_bases); 949 } 950 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 951 mutex_unlock(&adev->srbm_mutex); 952 953 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 954 acccess. These should be enabled by FW for target VMIDs. */ 955 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 956 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_BASE, 2 * i, 0); 957 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_SIZE, 2 * i, 0); 958 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_GWS_VMID0, i, 0); 959 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_OA_VMID0, i, 0); 960 } 961 } 962 963 static void gfx_v9_4_3_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 964 { 965 int vmid; 966 967 /* 968 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 969 * access. Compute VMIDs should be enabled by FW for target VMIDs, 970 * the driver can enable them for graphics. VMID0 should maintain 971 * access so that HWS firmware can save/restore entries. 972 */ 973 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 974 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_BASE, 2 * vmid, 0); 975 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_VMID0_SIZE, 2 * vmid, 0); 976 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_GWS_VMID0, vmid, 0); 977 WREG32_SOC15_OFFSET(GC, xcc_id, regGDS_OA_VMID0, vmid, 0); 978 } 979 } 980 981 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 982 { 983 u32 tmp; 984 int i, j; 985 986 for (i = 0; i < adev->gfx.num_xcd; i++) { 987 WREG32_FIELD15_PREREG(GC, i, GRBM_CNTL, READ_TIMEOUT, 0xff); 988 gfx_v9_4_3_setup_rb(adev, i); 989 } 990 991 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 992 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, regDB_DEBUG2); 993 994 /* XXX SH_MEM regs */ 995 /* where to put LDS, scratch, GPUVM in FSA64 space */ 996 mutex_lock(&adev->srbm_mutex); 997 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 998 for (j = 0; j < adev->gfx.num_xcd; j++) { 999 soc15_grbm_select(adev, 0, 0, 0, i, j); 1000 /* CP and shaders */ 1001 if (i == 0) { 1002 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1003 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1004 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1005 !!adev->gmc.noretry); 1006 WREG32_SOC15_RLC(GC, j, regSH_MEM_CONFIG, tmp); 1007 WREG32_SOC15_RLC(GC, j, regSH_MEM_BASES, 0); 1008 } else { 1009 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1010 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1011 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1012 !!adev->gmc.noretry); 1013 WREG32_SOC15_RLC(GC, j, regSH_MEM_CONFIG, tmp); 1014 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1015 (adev->gmc.private_aperture_start >> 48)); 1016 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1017 (adev->gmc.shared_aperture_start >> 48)); 1018 WREG32_SOC15_RLC(GC, j, regSH_MEM_BASES, tmp); 1019 } 1020 } 1021 } 1022 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 1023 1024 mutex_unlock(&adev->srbm_mutex); 1025 1026 for (i = 0; i < adev->gfx.num_xcd; i++) { 1027 gfx_v9_4_3_init_compute_vmid(adev, i); 1028 gfx_v9_4_3_init_gds_vmid(adev, i); 1029 } 1030 } 1031 1032 static void gfx_v9_4_3_enable_save_restore_machine(struct amdgpu_device *adev, 1033 int xcc_id) 1034 { 1035 WREG32_FIELD15_PREREG(GC, xcc_id, RLC_SRM_CNTL, SRM_ENABLE, 1); 1036 } 1037 1038 static void gfx_v9_4_3_init_csb(struct amdgpu_device *adev, int xcc_id) 1039 { 1040 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1041 /* csib */ 1042 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_ADDR_HI), 1043 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1044 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_ADDR_LO), 1045 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1046 WREG32_RLC(SOC15_REG_OFFSET(GC, xcc_id, regRLC_CSIB_LENGTH), 1047 adev->gfx.rlc.clear_state_size); 1048 } 1049 1050 static void gfx_v9_4_3_init_pg(struct amdgpu_device *adev, int xcc_id) 1051 { 1052 gfx_v9_4_3_init_csb(adev, xcc_id); 1053 1054 /* 1055 * Rlc save restore list is workable since v2_1. 1056 * And it's needed by gfxoff feature. 1057 */ 1058 if (adev->gfx.rlc.is_rlc_v2_1) 1059 gfx_v9_4_3_enable_save_restore_machine(adev, xcc_id); 1060 1061 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1062 AMD_PG_SUPPORT_GFX_SMG | 1063 AMD_PG_SUPPORT_GFX_DMG | 1064 AMD_PG_SUPPORT_CP | 1065 AMD_PG_SUPPORT_GDS | 1066 AMD_PG_SUPPORT_RLC_SMU_HS)) { 1067 WREG32_SOC15(GC, 0, regRLC_JUMP_TABLE_RESTORE, 1068 adev->gfx.rlc.cp_table_gpu_addr >> 8); 1069 } 1070 } 1071 1072 void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1073 { 1074 uint32_t data; 1075 1076 data = RREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG); 1077 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1078 WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data); 1079 } 1080 1081 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1082 { 1083 uint32_t rlc_setting; 1084 1085 /* if RLC is not enabled, do nothing */ 1086 rlc_setting = RREG32_SOC15(GC, 0, regRLC_CNTL); 1087 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1088 return false; 1089 1090 return true; 1091 } 1092 1093 static void gfx_v9_4_3_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1094 { 1095 uint32_t data; 1096 unsigned i; 1097 1098 data = RLC_SAFE_MODE__CMD_MASK; 1099 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1100 WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data); 1101 1102 /* wait for RLC_SAFE_MODE */ 1103 for (i = 0; i < adev->usec_timeout; i++) { 1104 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1105 break; 1106 udelay(1); 1107 } 1108 } 1109 1110 static void gfx_v9_4_3_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 1111 { 1112 uint32_t data; 1113 1114 data = RLC_SAFE_MODE__CMD_MASK; 1115 WREG32_SOC15(GC, xcc_id, regRLC_SAFE_MODE, data); 1116 } 1117 1118 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1119 { 1120 const struct cs_section_def *cs_data; 1121 int r; 1122 1123 adev->gfx.rlc.cs_data = gfx9_cs_data; 1124 1125 cs_data = adev->gfx.rlc.cs_data; 1126 1127 if (cs_data) { 1128 /* init clear state block */ 1129 r = amdgpu_gfx_rlc_init_csb(adev); 1130 if (r) 1131 return r; 1132 } 1133 1134 /* init spm vmid with 0xf */ 1135 if (adev->gfx.rlc.funcs->update_spm_vmid) 1136 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1137 1138 return 0; 1139 } 1140 1141 static void gfx_v9_4_3_wait_for_rlc_serdes(struct amdgpu_device *adev, 1142 int xcc_id) 1143 { 1144 u32 i, j, k; 1145 u32 mask; 1146 1147 mutex_lock(&adev->grbm_idx_mutex); 1148 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1149 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1150 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 1151 for (k = 0; k < adev->usec_timeout; k++) { 1152 if (RREG32_SOC15(GC, 0, regRLC_SERDES_CU_MASTER_BUSY) == 0) 1153 break; 1154 udelay(1); 1155 } 1156 if (k == adev->usec_timeout) { 1157 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 1158 0xffffffff, 0xffffffff, 1159 xcc_id); 1160 mutex_unlock(&adev->grbm_idx_mutex); 1161 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1162 i, j); 1163 return; 1164 } 1165 } 1166 } 1167 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 1168 mutex_unlock(&adev->grbm_idx_mutex); 1169 1170 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1171 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1172 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1173 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1174 for (k = 0; k < adev->usec_timeout; k++) { 1175 if ((RREG32_SOC15(GC, 0, regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1176 break; 1177 udelay(1); 1178 } 1179 } 1180 1181 static void gfx_v9_4_3_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1182 bool enable, int xcc_id) 1183 { 1184 u32 tmp; 1185 1186 /* These interrupts should be enabled to drive DS clock */ 1187 1188 tmp = RREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0); 1189 1190 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1191 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1192 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1193 1194 WREG32_SOC15(GC, xcc_id, regCP_INT_CNTL_RING0, tmp); 1195 } 1196 1197 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1198 { 1199 int i; 1200 1201 for (i = 0; i < adev->gfx.num_xcd; i++) { 1202 WREG32_FIELD15_PREREG(GC, i, RLC_CNTL, RLC_ENABLE_F32, 0); 1203 gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1204 gfx_v9_4_3_wait_for_rlc_serdes(adev, i); 1205 } 1206 } 1207 1208 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1209 { 1210 int i; 1211 1212 for (i = 0; i < adev->gfx.num_xcd; i++) { 1213 WREG32_FIELD15_PREREG(GC, i, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1214 udelay(50); 1215 WREG32_FIELD15_PREREG(GC, i, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1216 udelay(50); 1217 } 1218 } 1219 1220 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1221 { 1222 #ifdef AMDGPU_RLC_DEBUG_RETRY 1223 u32 rlc_ucode_ver; 1224 #endif 1225 int i; 1226 1227 for (i = 0; i < adev->gfx.num_xcd; i++) { 1228 WREG32_FIELD15_PREREG(GC, i, RLC_CNTL, RLC_ENABLE_F32, 1); 1229 udelay(50); 1230 1231 /* carrizo do enable cp interrupt after cp inited */ 1232 if (!(adev->flags & AMD_IS_APU)) { 1233 gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1234 udelay(50); 1235 } 1236 1237 #ifdef AMDGPU_RLC_DEBUG_RETRY 1238 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1239 rlc_ucode_ver = RREG32_SOC15(GC, i, regRLC_GPM_GENERAL_6); 1240 if (rlc_ucode_ver == 0x108) { 1241 dev_info(adev->dev, 1242 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1243 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1244 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1245 * default is 0x9C4 to create a 100us interval */ 1246 WREG32_SOC15(GC, i, regRLC_GPM_TIMER_INT_3, 0x9C4); 1247 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1248 * to disable the page fault retry interrupts, default is 1249 * 0x100 (256) */ 1250 WREG32_SOC15(GC, i, regRLC_GPM_GENERAL_12, 0x100); 1251 } 1252 #endif 1253 } 1254 } 1255 1256 static int gfx_v9_4_3_rlc_load_microcode(struct amdgpu_device *adev, int xcc_id) 1257 { 1258 const struct rlc_firmware_header_v2_0 *hdr; 1259 const __le32 *fw_data; 1260 unsigned i, fw_size; 1261 1262 if (!adev->gfx.rlc_fw) 1263 return -EINVAL; 1264 1265 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1266 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1267 1268 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1269 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1270 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1271 1272 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_ADDR, 1273 RLCG_UCODE_LOADING_START_ADDRESS); 1274 for (i = 0; i < fw_size; i++) { 1275 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1276 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1277 msleep(1); 1278 } 1279 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1280 } 1281 WREG32_SOC15(GC, xcc_id, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1282 1283 return 0; 1284 } 1285 1286 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1287 { 1288 int r, i; 1289 1290 adev->gfx.rlc.funcs->stop(adev); 1291 1292 for (i = 0; i < adev->gfx.num_xcd; i++) { 1293 /* disable CG */ 1294 WREG32_SOC15(GC, i, regRLC_CGCG_CGLS_CTRL, 0); 1295 1296 gfx_v9_4_3_init_pg(adev, i); 1297 1298 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1299 /* legacy rlc firmware loading */ 1300 r = gfx_v9_4_3_rlc_load_microcode(adev, i); 1301 if (r) 1302 return r; 1303 } 1304 } 1305 1306 adev->gfx.rlc.funcs->start(adev); 1307 1308 return 0; 1309 } 1310 1311 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1312 unsigned vmid) 1313 { 1314 u32 reg, data; 1315 1316 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); 1317 if (amdgpu_sriov_is_pp_one_vf(adev)) 1318 data = RREG32_NO_KIQ(reg); 1319 else 1320 data = RREG32(reg); 1321 1322 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1323 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1324 1325 if (amdgpu_sriov_is_pp_one_vf(adev)) 1326 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); 1327 else 1328 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); 1329 } 1330 1331 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1332 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1333 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1334 }; 1335 1336 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1337 uint32_t offset, 1338 struct soc15_reg_rlcg *entries, int arr_size) 1339 { 1340 int i; 1341 uint32_t reg; 1342 1343 if (!entries) 1344 return false; 1345 1346 for (i = 0; i < arr_size; i++) { 1347 const struct soc15_reg_rlcg *entry; 1348 1349 entry = &entries[i]; 1350 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 1351 if (offset == reg) 1352 return true; 1353 } 1354 1355 return false; 1356 } 1357 1358 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1359 { 1360 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1361 (void *)rlcg_access_gc_9_4_3, 1362 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1363 } 1364 1365 static void gfx_v9_4_3_cp_compute_enable(struct amdgpu_device *adev, 1366 bool enable, int xcc_id) 1367 { 1368 if (enable) { 1369 WREG32_SOC15_RLC(GC, xcc_id, regCP_MEC_CNTL, 0); 1370 } else { 1371 WREG32_SOC15_RLC(GC, xcc_id, regCP_MEC_CNTL, 1372 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1373 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1374 } 1375 udelay(50); 1376 } 1377 1378 static int gfx_v9_4_3_cp_compute_load_microcode(struct amdgpu_device *adev, 1379 int xcc_id) 1380 { 1381 const struct gfx_firmware_header_v1_0 *mec_hdr; 1382 const __le32 *fw_data; 1383 unsigned i; 1384 u32 tmp; 1385 u32 mec_ucode_addr_offset; 1386 u32 mec_ucode_data_offset; 1387 1388 if (!adev->gfx.mec_fw) 1389 return -EINVAL; 1390 1391 gfx_v9_4_3_cp_compute_enable(adev, false, xcc_id); 1392 1393 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1394 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1395 1396 fw_data = (const __le32 *) 1397 (adev->gfx.mec_fw->data + 1398 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1399 tmp = 0; 1400 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1401 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1402 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_CNTL, tmp); 1403 1404 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_LO, 1405 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1406 WREG32_SOC15(GC, xcc_id, regCP_CPC_IC_BASE_HI, 1407 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1408 1409 mec_ucode_addr_offset = 1410 SOC15_REG_OFFSET(GC, xcc_id, regCP_MEC_ME1_UCODE_ADDR); 1411 mec_ucode_data_offset = 1412 SOC15_REG_OFFSET(GC, xcc_id, regCP_MEC_ME1_UCODE_DATA); 1413 1414 /* MEC1 */ 1415 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1416 for (i = 0; i < mec_hdr->jt_size; i++) 1417 WREG32(mec_ucode_data_offset, 1418 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1419 1420 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1421 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1422 1423 return 0; 1424 } 1425 1426 /* KIQ functions */ 1427 static void gfx_v9_4_3_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1428 { 1429 uint32_t tmp; 1430 struct amdgpu_device *adev = ring->adev; 1431 1432 /* tell RLC which is KIQ queue */ 1433 tmp = RREG32_SOC15(GC, xcc_id, regRLC_CP_SCHEDULERS); 1434 tmp &= 0xffffff00; 1435 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1436 WREG32_SOC15_RLC(GC, xcc_id, regRLC_CP_SCHEDULERS, tmp); 1437 tmp |= 0x80; 1438 WREG32_SOC15_RLC(GC, xcc_id, regRLC_CP_SCHEDULERS, tmp); 1439 } 1440 1441 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1442 { 1443 struct amdgpu_device *adev = ring->adev; 1444 1445 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1446 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1447 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1448 mqd->cp_hqd_queue_priority = 1449 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1450 } 1451 } 1452 } 1453 1454 static int gfx_v9_4_3_mqd_init(struct amdgpu_ring *ring) 1455 { 1456 struct amdgpu_device *adev = ring->adev; 1457 struct v9_mqd *mqd = ring->mqd_ptr; 1458 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1459 uint32_t tmp; 1460 1461 mqd->header = 0xC0310800; 1462 mqd->compute_pipelinestat_enable = 0x00000001; 1463 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1464 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1465 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1466 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1467 mqd->compute_misc_reserved = 0x00000003; 1468 1469 mqd->dynamic_cu_mask_addr_lo = 1470 lower_32_bits(ring->mqd_gpu_addr 1471 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1472 mqd->dynamic_cu_mask_addr_hi = 1473 upper_32_bits(ring->mqd_gpu_addr 1474 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1475 1476 eop_base_addr = ring->eop_gpu_addr >> 8; 1477 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1478 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1479 1480 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1481 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); 1482 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1483 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1484 1485 mqd->cp_hqd_eop_control = tmp; 1486 1487 /* enable doorbell? */ 1488 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1489 1490 if (ring->use_doorbell) { 1491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1492 DOORBELL_OFFSET, ring->doorbell_index); 1493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1494 DOORBELL_EN, 1); 1495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1496 DOORBELL_SOURCE, 0); 1497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1498 DOORBELL_HIT, 0); 1499 } else { 1500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1501 DOORBELL_EN, 0); 1502 } 1503 1504 mqd->cp_hqd_pq_doorbell_control = tmp; 1505 1506 /* disable the queue if it's active */ 1507 ring->wptr = 0; 1508 mqd->cp_hqd_dequeue_request = 0; 1509 mqd->cp_hqd_pq_rptr = 0; 1510 mqd->cp_hqd_pq_wptr_lo = 0; 1511 mqd->cp_hqd_pq_wptr_hi = 0; 1512 1513 /* set the pointer to the MQD */ 1514 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1515 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1516 1517 /* set MQD vmid to 0 */ 1518 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 1519 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1520 mqd->cp_mqd_control = tmp; 1521 1522 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1523 hqd_gpu_addr = ring->gpu_addr >> 8; 1524 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1525 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1526 1527 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1528 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); 1529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1530 (order_base_2(ring->ring_size / 4) - 1)); 1531 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1532 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1533 #ifdef __BIG_ENDIAN 1534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1535 #endif 1536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1540 mqd->cp_hqd_pq_control = tmp; 1541 1542 /* set the wb address whether it's enabled or not */ 1543 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1544 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1545 mqd->cp_hqd_pq_rptr_report_addr_hi = 1546 upper_32_bits(wb_gpu_addr) & 0xffff; 1547 1548 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1549 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1550 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1551 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1552 1553 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1554 ring->wptr = 0; 1555 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); 1556 1557 /* set the vmid for the queue */ 1558 mqd->cp_hqd_vmid = 0; 1559 1560 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); 1561 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1562 mqd->cp_hqd_persistent_state = tmp; 1563 1564 /* set MIN_IB_AVAIL_SIZE */ 1565 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); 1566 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1567 mqd->cp_hqd_ib_control = tmp; 1568 1569 /* set static priority for a queue/ring */ 1570 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1571 mqd->cp_hqd_quantum = RREG32(regCP_HQD_QUANTUM); 1572 1573 /* map_queues packet doesn't need activate the queue, 1574 * so only kiq need set this field. 1575 */ 1576 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1577 mqd->cp_hqd_active = 1; 1578 1579 return 0; 1580 } 1581 1582 static int gfx_v9_4_3_kiq_init_register(struct amdgpu_ring *ring, int xcc_id) 1583 { 1584 struct amdgpu_device *adev = ring->adev; 1585 struct v9_mqd *mqd = ring->mqd_ptr; 1586 int j; 1587 1588 /* disable wptr polling */ 1589 WREG32_FIELD15_PREREG(GC, xcc_id, CP_PQ_WPTR_POLL_CNTL, EN, 0); 1590 1591 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_BASE_ADDR, 1592 mqd->cp_hqd_eop_base_addr_lo); 1593 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_BASE_ADDR_HI, 1594 mqd->cp_hqd_eop_base_addr_hi); 1595 1596 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1597 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_EOP_CONTROL, 1598 mqd->cp_hqd_eop_control); 1599 1600 /* enable doorbell? */ 1601 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 1602 mqd->cp_hqd_pq_doorbell_control); 1603 1604 /* disable the queue if it's active */ 1605 if (RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1) { 1606 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1); 1607 for (j = 0; j < adev->usec_timeout; j++) { 1608 if (!(RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1)) 1609 break; 1610 udelay(1); 1611 } 1612 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1613 mqd->cp_hqd_dequeue_request); 1614 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR, 1615 mqd->cp_hqd_pq_rptr); 1616 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 1617 mqd->cp_hqd_pq_wptr_lo); 1618 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 1619 mqd->cp_hqd_pq_wptr_hi); 1620 } 1621 1622 /* set the pointer to the MQD */ 1623 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_BASE_ADDR, 1624 mqd->cp_mqd_base_addr_lo); 1625 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_BASE_ADDR_HI, 1626 mqd->cp_mqd_base_addr_hi); 1627 1628 /* set MQD vmid to 0 */ 1629 WREG32_SOC15_RLC(GC, xcc_id, regCP_MQD_CONTROL, 1630 mqd->cp_mqd_control); 1631 1632 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1633 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_BASE, 1634 mqd->cp_hqd_pq_base_lo); 1635 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_BASE_HI, 1636 mqd->cp_hqd_pq_base_hi); 1637 1638 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1639 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_CONTROL, 1640 mqd->cp_hqd_pq_control); 1641 1642 /* set the wb address whether it's enabled or not */ 1643 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR_REPORT_ADDR, 1644 mqd->cp_hqd_pq_rptr_report_addr_lo); 1645 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1646 mqd->cp_hqd_pq_rptr_report_addr_hi); 1647 1648 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1649 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_POLL_ADDR, 1650 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1651 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1652 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1653 1654 /* enable the doorbell if requested */ 1655 if (ring->use_doorbell) { 1656 WREG32_SOC15(GC, xcc_id, regCP_MEC_DOORBELL_RANGE_LOWER, 1657 (adev->doorbell_index.kiq * 2) << 2); 1658 WREG32_SOC15(GC, xcc_id, regCP_MEC_DOORBELL_RANGE_UPPER, 1659 (adev->doorbell_index.userqueue_end * 2) << 2); 1660 } 1661 1662 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 1663 mqd->cp_hqd_pq_doorbell_control); 1664 1665 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1666 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 1667 mqd->cp_hqd_pq_wptr_lo); 1668 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 1669 mqd->cp_hqd_pq_wptr_hi); 1670 1671 /* set the vmid for the queue */ 1672 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_VMID, mqd->cp_hqd_vmid); 1673 1674 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PERSISTENT_STATE, 1675 mqd->cp_hqd_persistent_state); 1676 1677 /* activate the queue */ 1678 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_ACTIVE, 1679 mqd->cp_hqd_active); 1680 1681 if (ring->use_doorbell) 1682 WREG32_FIELD15_PREREG(GC, xcc_id, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1683 1684 return 0; 1685 } 1686 1687 static int gfx_v9_4_3_kiq_fini_register(struct amdgpu_ring *ring, int xcc_id) 1688 { 1689 struct amdgpu_device *adev = ring->adev; 1690 int j; 1691 1692 /* disable the queue if it's active */ 1693 if (RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1) { 1694 1695 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1); 1696 1697 for (j = 0; j < adev->usec_timeout; j++) { 1698 if (!(RREG32_SOC15(GC, xcc_id, regCP_HQD_ACTIVE) & 1)) 1699 break; 1700 udelay(1); 1701 } 1702 1703 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1704 DRM_DEBUG("KIQ dequeue request failed.\n"); 1705 1706 /* Manual disable if dequeue request times out */ 1707 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_ACTIVE, 0); 1708 } 1709 1710 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_DEQUEUE_REQUEST, 1711 0); 1712 } 1713 1714 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_IQ_TIMER, 0); 1715 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_IB_CONTROL, 0); 1716 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PERSISTENT_STATE, 0); 1717 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1718 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1719 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_RPTR, 0); 1720 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_HI, 0); 1721 WREG32_SOC15_RLC(GC, xcc_id, regCP_HQD_PQ_WPTR_LO, 0); 1722 1723 return 0; 1724 } 1725 1726 static int gfx_v9_4_3_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1727 { 1728 struct amdgpu_device *adev = ring->adev; 1729 struct v9_mqd *mqd = ring->mqd_ptr; 1730 struct v9_mqd *tmp_mqd; 1731 1732 gfx_v9_4_3_kiq_setting(ring, xcc_id); 1733 1734 /* GPU could be in bad state during probe, driver trigger the reset 1735 * after load the SMU, in this case , the mqd is not be initialized. 1736 * driver need to re-init the mqd. 1737 * check mqd->cp_hqd_pq_control since this value should not be 0 1738 */ 1739 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1740 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1741 /* for GPU_RESET case , reset MQD to a clean status */ 1742 if (adev->gfx.kiq[xcc_id].mqd_backup) 1743 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1744 1745 /* reset ring buffer */ 1746 ring->wptr = 0; 1747 amdgpu_ring_clear_ring(ring); 1748 mutex_lock(&adev->srbm_mutex); 1749 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1750 gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1751 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1752 mutex_unlock(&adev->srbm_mutex); 1753 } else { 1754 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1755 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1756 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1757 mutex_lock(&adev->srbm_mutex); 1758 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1759 gfx_v9_4_3_mqd_init(ring); 1760 gfx_v9_4_3_kiq_init_register(ring, xcc_id); 1761 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1762 mutex_unlock(&adev->srbm_mutex); 1763 1764 if (adev->gfx.kiq[xcc_id].mqd_backup) 1765 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int gfx_v9_4_3_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1772 { 1773 struct amdgpu_device *adev = ring->adev; 1774 struct v9_mqd *mqd = ring->mqd_ptr; 1775 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1776 struct v9_mqd *tmp_mqd; 1777 1778 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1779 * is not be initialized before 1780 */ 1781 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1782 1783 if (!tmp_mqd->cp_hqd_pq_control || 1784 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1785 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1786 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1787 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1788 mutex_lock(&adev->srbm_mutex); 1789 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, xcc_id); 1790 gfx_v9_4_3_mqd_init(ring); 1791 soc15_grbm_select(adev, 0, 0, 0, 0, xcc_id); 1792 mutex_unlock(&adev->srbm_mutex); 1793 1794 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1795 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1796 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 1797 /* reset MQD to a clean status */ 1798 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1799 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1800 1801 /* reset ring buffer */ 1802 ring->wptr = 0; 1803 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1804 amdgpu_ring_clear_ring(ring); 1805 } else { 1806 amdgpu_ring_clear_ring(ring); 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int gfx_v9_4_3_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1813 { 1814 struct amdgpu_ring *ring; 1815 int r; 1816 1817 ring = &adev->gfx.kiq[xcc_id].ring; 1818 1819 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1820 if (unlikely(r != 0)) 1821 return r; 1822 1823 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1824 if (unlikely(r != 0)) 1825 return r; 1826 1827 gfx_v9_4_3_kiq_init_queue(ring, xcc_id); 1828 amdgpu_bo_kunmap(ring->mqd_obj); 1829 ring->mqd_ptr = NULL; 1830 amdgpu_bo_unreserve(ring->mqd_obj); 1831 ring->sched.ready = true; 1832 return 0; 1833 } 1834 1835 static int gfx_v9_4_3_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1836 { 1837 struct amdgpu_ring *ring = NULL; 1838 int r = 0, i; 1839 1840 gfx_v9_4_3_cp_compute_enable(adev, true, xcc_id); 1841 1842 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1843 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1844 1845 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1846 if (unlikely(r != 0)) 1847 goto done; 1848 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1849 if (!r) { 1850 r = gfx_v9_4_3_kcq_init_queue(ring, xcc_id); 1851 amdgpu_bo_kunmap(ring->mqd_obj); 1852 ring->mqd_ptr = NULL; 1853 } 1854 amdgpu_bo_unreserve(ring->mqd_obj); 1855 if (r) 1856 goto done; 1857 } 1858 1859 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1860 done: 1861 return r; 1862 } 1863 1864 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1865 { 1866 int r, i, j; 1867 struct amdgpu_ring *ring; 1868 1869 for (i = 0; i < adev->gfx.num_xcd; i++) { 1870 gfx_v9_4_3_enable_gui_idle_interrupt(adev, false, i); 1871 1872 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1873 gfx_v9_4_3_disable_gpa_mode(adev, i); 1874 1875 r = gfx_v9_4_3_cp_compute_load_microcode(adev, i); 1876 if (r) 1877 return r; 1878 } 1879 1880 r = gfx_v9_4_3_kiq_resume(adev, i); 1881 if (r) 1882 return r; 1883 1884 r = gfx_v9_4_3_kcq_resume(adev, i); 1885 if (r) 1886 return r; 1887 1888 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1889 ring = &adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings]; 1890 amdgpu_ring_test_helper(ring); 1891 } 1892 1893 gfx_v9_4_3_enable_gui_idle_interrupt(adev, true, i); 1894 } 1895 1896 return 0; 1897 } 1898 1899 static void gfx_v9_4_3_cp_enable(struct amdgpu_device *adev, bool enable, 1900 int xcc_id) 1901 { 1902 gfx_v9_4_3_cp_compute_enable(adev, enable, xcc_id); 1903 } 1904 1905 static int gfx_v9_4_3_hw_init(void *handle) 1906 { 1907 int r; 1908 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1909 1910 gfx_v9_4_3_init_golden_registers(adev); 1911 1912 gfx_v9_4_3_constants_init(adev); 1913 1914 r = adev->gfx.rlc.funcs->resume(adev); 1915 if (r) 1916 return r; 1917 1918 r = gfx_v9_4_3_cp_resume(adev); 1919 if (r) 1920 return r; 1921 1922 return r; 1923 } 1924 1925 static int gfx_v9_4_3_hw_fini(void *handle) 1926 { 1927 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1928 int i; 1929 1930 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 1931 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 1932 1933 for (i = 0; i < adev->gfx.num_xcd; i++) { 1934 if (amdgpu_gfx_disable_kcq(adev, i)) 1935 DRM_ERROR("XCD %d KCQ disable failed\n", i); 1936 1937 /* Use deinitialize sequence from CAIL when unbinding device 1938 * from driver, otherwise KIQ is hanging when binding back 1939 */ 1940 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1941 mutex_lock(&adev->srbm_mutex); 1942 soc15_grbm_select(adev, adev->gfx.kiq[i].ring.me, 1943 adev->gfx.kiq[i].ring.pipe, 1944 adev->gfx.kiq[i].ring.queue, 0, i); 1945 gfx_v9_4_3_kiq_fini_register(&adev->gfx.kiq[i].ring, i); 1946 soc15_grbm_select(adev, 0, 0, 0, 0, i); 1947 mutex_unlock(&adev->srbm_mutex); 1948 } 1949 1950 gfx_v9_4_3_cp_enable(adev, false, i); 1951 } 1952 1953 /* Skip suspend with A+A reset */ 1954 if (adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) { 1955 dev_dbg(adev->dev, "Device in reset. Skipping RLC halt\n"); 1956 return 0; 1957 } 1958 1959 adev->gfx.rlc.funcs->stop(adev); 1960 return 0; 1961 } 1962 1963 static int gfx_v9_4_3_suspend(void *handle) 1964 { 1965 return gfx_v9_4_3_hw_fini(handle); 1966 } 1967 1968 static int gfx_v9_4_3_resume(void *handle) 1969 { 1970 return gfx_v9_4_3_hw_init(handle); 1971 } 1972 1973 static bool gfx_v9_4_3_is_idle(void *handle) 1974 { 1975 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1976 int i; 1977 1978 for (i = 0; i < adev->gfx.num_xcd; i++) { 1979 if (REG_GET_FIELD(RREG32_SOC15(GC, i, regGRBM_STATUS), 1980 GRBM_STATUS, GUI_ACTIVE)) 1981 return false; 1982 } 1983 return true; 1984 } 1985 1986 static int gfx_v9_4_3_wait_for_idle(void *handle) 1987 { 1988 unsigned i; 1989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1990 1991 for (i = 0; i < adev->usec_timeout; i++) { 1992 if (gfx_v9_4_3_is_idle(handle)) 1993 return 0; 1994 udelay(1); 1995 } 1996 return -ETIMEDOUT; 1997 } 1998 1999 static int gfx_v9_4_3_soft_reset(void *handle) 2000 { 2001 u32 grbm_soft_reset = 0; 2002 u32 tmp; 2003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2004 2005 /* GRBM_STATUS */ 2006 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS); 2007 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2008 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2009 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2010 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2011 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2012 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2013 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2014 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2015 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2016 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2017 } 2018 2019 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2020 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2021 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2022 } 2023 2024 /* GRBM_STATUS2 */ 2025 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS2); 2026 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2027 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2028 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2029 2030 2031 if (grbm_soft_reset) { 2032 /* stop the rlc */ 2033 adev->gfx.rlc.funcs->stop(adev); 2034 2035 /* Disable MEC parsing/prefetching */ 2036 gfx_v9_4_3_cp_compute_enable(adev, false, 0); 2037 2038 if (grbm_soft_reset) { 2039 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2040 tmp |= grbm_soft_reset; 2041 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2042 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 2043 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2044 2045 udelay(50); 2046 2047 tmp &= ~grbm_soft_reset; 2048 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 2049 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 2050 } 2051 2052 /* Wait a little for things to settle down */ 2053 udelay(50); 2054 } 2055 return 0; 2056 } 2057 2058 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2059 uint32_t vmid, 2060 uint32_t gds_base, uint32_t gds_size, 2061 uint32_t gws_base, uint32_t gws_size, 2062 uint32_t oa_base, uint32_t oa_size) 2063 { 2064 struct amdgpu_device *adev = ring->adev; 2065 2066 /* GDS Base */ 2067 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2068 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, 2069 gds_base); 2070 2071 /* GDS Size */ 2072 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2073 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, 2074 gds_size); 2075 2076 /* GWS */ 2077 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2078 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, 2079 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2080 2081 /* OA */ 2082 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2083 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, 2084 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2085 } 2086 2087 static int gfx_v9_4_3_early_init(void *handle) 2088 { 2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2090 2091 /* hardcode in emulation phase */ 2092 adev->gfx.num_xcd = 1; 2093 adev->gfx.num_xcc_per_xcp = 1; 2094 adev->gfx.partition_mode = AMDGPU_SPX_PARTITION_MODE; 2095 2096 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2097 AMDGPU_MAX_COMPUTE_RINGS); 2098 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2099 gfx_v9_4_3_set_ring_funcs(adev); 2100 gfx_v9_4_3_set_irq_funcs(adev); 2101 gfx_v9_4_3_set_gds_init(adev); 2102 gfx_v9_4_3_set_rlc_funcs(adev); 2103 2104 return gfx_v9_4_3_init_microcode(adev); 2105 } 2106 2107 static int gfx_v9_4_3_late_init(void *handle) 2108 { 2109 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2110 int r; 2111 2112 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2113 if (r) 2114 return r; 2115 2116 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2117 if (r) 2118 return r; 2119 2120 return 0; 2121 } 2122 2123 static void gfx_v9_4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2124 bool enable, int xcc_id) 2125 { 2126 uint32_t data, def; 2127 2128 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2129 2130 /* It is disabled by HW by default */ 2131 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2132 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2133 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2134 2135 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2136 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2137 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2138 2139 /* only for Vega10 & Raven1 */ 2140 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 2141 2142 if (def != data) 2143 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2144 2145 /* MGLS is a global flag to control all MGLS in GFX */ 2146 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2147 /* 2 - RLC memory Light sleep */ 2148 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2149 def = data = RREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL); 2150 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2151 if (def != data) 2152 WREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL, data); 2153 } 2154 /* 3 - CP memory Light sleep */ 2155 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2156 def = data = RREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL); 2157 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2158 if (def != data) 2159 WREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL, data); 2160 } 2161 } 2162 } else { 2163 /* 1 - MGCG_OVERRIDE */ 2164 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2165 2166 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2167 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2168 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2169 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2170 2171 if (def != data) 2172 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2173 2174 /* 2 - disable MGLS in RLC */ 2175 data = RREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL); 2176 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2177 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2178 WREG32_SOC15(GC, xcc_id, regRLC_MEM_SLP_CNTL, data); 2179 } 2180 2181 /* 3 - disable MGLS in CP */ 2182 data = RREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL); 2183 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2184 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2185 WREG32_SOC15(GC, xcc_id, regCP_MEM_SLP_CNTL, data); 2186 } 2187 } 2188 2189 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2190 } 2191 2192 static void gfx_v9_4_3_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2193 bool enable, int xcc_id) 2194 { 2195 uint32_t def, data; 2196 2197 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2198 2199 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2200 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE); 2201 /* unset CGCG override */ 2202 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2203 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2204 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2205 else 2206 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2207 /* update CGCG and CGLS override bits */ 2208 if (def != data) 2209 WREG32_SOC15(GC, xcc_id, regRLC_CGTT_MGCG_OVERRIDE, data); 2210 2211 /* enable cgcg FSM(0x0000363F) */ 2212 def = RREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL); 2213 2214 if (adev->asic_type == CHIP_ARCTURUS) 2215 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2216 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2217 else 2218 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2219 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2220 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2221 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2222 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2223 if (def != data) 2224 WREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL, data); 2225 2226 /* set IDLE_POLL_COUNT(0x00900100) */ 2227 def = RREG32_SOC15(GC, xcc_id, regCP_RB_WPTR_POLL_CNTL); 2228 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2229 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2230 if (def != data) 2231 WREG32_SOC15(GC, xcc_id, regCP_RB_WPTR_POLL_CNTL, data); 2232 } else { 2233 def = data = RREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL); 2234 /* reset CGCG/CGLS bits */ 2235 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2236 /* disable cgcg and cgls in FSM */ 2237 if (def != data) 2238 WREG32_SOC15(GC, xcc_id, regRLC_CGCG_CGLS_CTRL, data); 2239 } 2240 2241 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2242 } 2243 2244 static int gfx_v9_4_3_update_gfx_clock_gating(struct amdgpu_device *adev, 2245 bool enable, int xcc_id) 2246 { 2247 if (enable) { 2248 /* CGCG/CGLS should be enabled after MGCG/MGLS 2249 * === MGCG + MGLS === 2250 */ 2251 gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2252 /* === CGCG + CGLS === */ 2253 gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2254 } else { 2255 /* CGCG/CGLS should be disabled before MGCG/MGLS 2256 * === CGCG + CGLS === 2257 */ 2258 gfx_v9_4_3_update_coarse_grain_clock_gating(adev, enable, xcc_id); 2259 /* === MGCG + MGLS === */ 2260 gfx_v9_4_3_update_medium_grain_clock_gating(adev, enable, xcc_id); 2261 } 2262 return 0; 2263 } 2264 2265 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2266 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2267 .set_safe_mode = gfx_v9_4_3_set_safe_mode, 2268 .unset_safe_mode = gfx_v9_4_3_unset_safe_mode, 2269 .init = gfx_v9_4_3_rlc_init, 2270 .get_csb_size = gfx_v9_4_3_get_csb_size, 2271 .get_csb_buffer = gfx_v9_4_3_get_csb_buffer, 2272 .resume = gfx_v9_4_3_rlc_resume, 2273 .stop = gfx_v9_4_3_rlc_stop, 2274 .reset = gfx_v9_4_3_rlc_reset, 2275 .start = gfx_v9_4_3_rlc_start, 2276 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2277 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2278 }; 2279 2280 static int gfx_v9_4_3_set_powergating_state(void *handle, 2281 enum amd_powergating_state state) 2282 { 2283 return 0; 2284 } 2285 2286 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2287 enum amd_clockgating_state state) 2288 { 2289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2290 int i; 2291 2292 if (amdgpu_sriov_vf(adev)) 2293 return 0; 2294 2295 switch (adev->ip_versions[GC_HWIP][0]) { 2296 case IP_VERSION(9, 4, 3): 2297 for (i = 0; i < adev->gfx.num_xcd; i++) 2298 gfx_v9_4_3_update_gfx_clock_gating(adev, 2299 state == AMD_CG_STATE_GATE, i); 2300 break; 2301 default: 2302 break; 2303 } 2304 return 0; 2305 } 2306 2307 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2308 { 2309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2310 int data; 2311 2312 if (amdgpu_sriov_vf(adev)) 2313 *flags = 0; 2314 2315 /* AMD_CG_SUPPORT_GFX_MGCG */ 2316 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGTT_MGCG_OVERRIDE)); 2317 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2318 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2319 2320 /* AMD_CG_SUPPORT_GFX_CGCG */ 2321 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_CGCG_CGLS_CTRL)); 2322 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2323 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2324 2325 /* AMD_CG_SUPPORT_GFX_CGLS */ 2326 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2327 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2328 2329 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2330 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regRLC_MEM_SLP_CNTL)); 2331 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2332 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2333 2334 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2335 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, regCP_MEM_SLP_CNTL)); 2336 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2337 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2338 } 2339 2340 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2341 { 2342 struct amdgpu_device *adev = ring->adev; 2343 u32 ref_and_mask, reg_mem_engine; 2344 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2345 2346 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2347 switch (ring->me) { 2348 case 1: 2349 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2350 break; 2351 case 2: 2352 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2353 break; 2354 default: 2355 return; 2356 } 2357 reg_mem_engine = 0; 2358 } else { 2359 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2360 reg_mem_engine = 1; /* pfp */ 2361 } 2362 2363 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2364 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2365 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2366 ref_and_mask, ref_and_mask, 0x20); 2367 } 2368 2369 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2370 struct amdgpu_job *job, 2371 struct amdgpu_ib *ib, 2372 uint32_t flags) 2373 { 2374 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2375 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2376 2377 /* Currently, there is a high possibility to get wave ID mismatch 2378 * between ME and GDS, leading to a hw deadlock, because ME generates 2379 * different wave IDs than the GDS expects. This situation happens 2380 * randomly when at least 5 compute pipes use GDS ordered append. 2381 * The wave IDs generated by ME are also wrong after suspend/resume. 2382 * Those are probably bugs somewhere else in the kernel driver. 2383 * 2384 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2385 * GDS to 0 for this ring (me/pipe). 2386 */ 2387 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2389 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2390 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2391 } 2392 2393 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2394 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2395 amdgpu_ring_write(ring, 2396 #ifdef __BIG_ENDIAN 2397 (2 << 0) | 2398 #endif 2399 lower_32_bits(ib->gpu_addr)); 2400 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2401 amdgpu_ring_write(ring, control); 2402 } 2403 2404 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2405 u64 seq, unsigned flags) 2406 { 2407 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2408 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2409 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2410 2411 /* RELEASE_MEM - flush caches, send int */ 2412 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2413 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2414 EOP_TC_NC_ACTION_EN) : 2415 (EOP_TCL1_ACTION_EN | 2416 EOP_TC_ACTION_EN | 2417 EOP_TC_WB_ACTION_EN | 2418 EOP_TC_MD_ACTION_EN)) | 2419 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2420 EVENT_INDEX(5))); 2421 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2422 2423 /* 2424 * the address should be Qword aligned if 64bit write, Dword 2425 * aligned if only send 32bit data low (discard data high) 2426 */ 2427 if (write64bit) 2428 BUG_ON(addr & 0x7); 2429 else 2430 BUG_ON(addr & 0x3); 2431 amdgpu_ring_write(ring, lower_32_bits(addr)); 2432 amdgpu_ring_write(ring, upper_32_bits(addr)); 2433 amdgpu_ring_write(ring, lower_32_bits(seq)); 2434 amdgpu_ring_write(ring, upper_32_bits(seq)); 2435 amdgpu_ring_write(ring, 0); 2436 } 2437 2438 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2439 { 2440 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2441 uint32_t seq = ring->fence_drv.sync_seq; 2442 uint64_t addr = ring->fence_drv.gpu_addr; 2443 2444 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2445 lower_32_bits(addr), upper_32_bits(addr), 2446 seq, 0xffffffff, 4); 2447 } 2448 2449 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2450 unsigned vmid, uint64_t pd_addr) 2451 { 2452 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2453 } 2454 2455 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2456 { 2457 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2458 } 2459 2460 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2461 { 2462 u64 wptr; 2463 2464 /* XXX check if swapping is necessary on BE */ 2465 if (ring->use_doorbell) 2466 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2467 else 2468 BUG(); 2469 return wptr; 2470 } 2471 2472 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2473 { 2474 struct amdgpu_device *adev = ring->adev; 2475 2476 /* XXX check if swapping is necessary on BE */ 2477 if (ring->use_doorbell) { 2478 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2479 WDOORBELL64(ring->doorbell_index, ring->wptr); 2480 } else { 2481 BUG(); /* only DOORBELL method supported on gfx9 now */ 2482 } 2483 } 2484 2485 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2486 u64 seq, unsigned int flags) 2487 { 2488 struct amdgpu_device *adev = ring->adev; 2489 2490 /* we only allocate 32bit for each seq wb address */ 2491 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2492 2493 /* write fence seq to the "addr" */ 2494 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2495 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2496 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2497 amdgpu_ring_write(ring, lower_32_bits(addr)); 2498 amdgpu_ring_write(ring, upper_32_bits(addr)); 2499 amdgpu_ring_write(ring, lower_32_bits(seq)); 2500 2501 if (flags & AMDGPU_FENCE_FLAG_INT) { 2502 /* set register to trigger INT */ 2503 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2504 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2505 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2506 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); 2507 amdgpu_ring_write(ring, 0); 2508 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2509 } 2510 } 2511 2512 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2513 uint32_t reg_val_offs) 2514 { 2515 struct amdgpu_device *adev = ring->adev; 2516 2517 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2518 amdgpu_ring_write(ring, 0 | /* src: register*/ 2519 (5 << 8) | /* dst: memory */ 2520 (1 << 20)); /* write confirm */ 2521 amdgpu_ring_write(ring, reg); 2522 amdgpu_ring_write(ring, 0); 2523 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2524 reg_val_offs * 4)); 2525 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2526 reg_val_offs * 4)); 2527 } 2528 2529 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2530 uint32_t val) 2531 { 2532 uint32_t cmd = 0; 2533 2534 switch (ring->funcs->type) { 2535 case AMDGPU_RING_TYPE_GFX: 2536 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2537 break; 2538 case AMDGPU_RING_TYPE_KIQ: 2539 cmd = (1 << 16); /* no inc addr */ 2540 break; 2541 default: 2542 cmd = WR_CONFIRM; 2543 break; 2544 } 2545 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2546 amdgpu_ring_write(ring, cmd); 2547 amdgpu_ring_write(ring, reg); 2548 amdgpu_ring_write(ring, 0); 2549 amdgpu_ring_write(ring, val); 2550 } 2551 2552 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2553 uint32_t val, uint32_t mask) 2554 { 2555 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2556 } 2557 2558 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2559 uint32_t reg0, uint32_t reg1, 2560 uint32_t ref, uint32_t mask) 2561 { 2562 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2563 ref, mask); 2564 } 2565 2566 static void gfx_v9_4_3_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 2567 int me, int pipe, 2568 enum amdgpu_interrupt_state state, 2569 int xcc_id) 2570 { 2571 u32 mec_int_cntl, mec_int_cntl_reg; 2572 2573 /* 2574 * amdgpu controls only the first MEC. That's why this function only 2575 * handles the setting of interrupts for this specific MEC. All other 2576 * pipes' interrupts are set by amdkfd. 2577 */ 2578 2579 if (me == 1) { 2580 switch (pipe) { 2581 case 0: 2582 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE0_INT_CNTL); 2583 break; 2584 case 1: 2585 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE1_INT_CNTL); 2586 break; 2587 case 2: 2588 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE2_INT_CNTL); 2589 break; 2590 case 3: 2591 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, xcc_id, regCP_ME1_PIPE3_INT_CNTL); 2592 break; 2593 default: 2594 DRM_DEBUG("invalid pipe %d\n", pipe); 2595 return; 2596 } 2597 } else { 2598 DRM_DEBUG("invalid me %d\n", me); 2599 return; 2600 } 2601 2602 switch (state) { 2603 case AMDGPU_IRQ_STATE_DISABLE: 2604 mec_int_cntl = RREG32(mec_int_cntl_reg); 2605 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2606 TIME_STAMP_INT_ENABLE, 0); 2607 WREG32(mec_int_cntl_reg, mec_int_cntl); 2608 break; 2609 case AMDGPU_IRQ_STATE_ENABLE: 2610 mec_int_cntl = RREG32(mec_int_cntl_reg); 2611 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2612 TIME_STAMP_INT_ENABLE, 1); 2613 WREG32(mec_int_cntl_reg, mec_int_cntl); 2614 break; 2615 default: 2616 break; 2617 } 2618 } 2619 2620 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2621 struct amdgpu_irq_src *source, 2622 unsigned type, 2623 enum amdgpu_interrupt_state state) 2624 { 2625 int i; 2626 2627 switch (state) { 2628 case AMDGPU_IRQ_STATE_DISABLE: 2629 case AMDGPU_IRQ_STATE_ENABLE: 2630 for (i = 0; i < adev->gfx.num_xcd; i++) 2631 WREG32_FIELD15_PREREG(GC, i, CP_INT_CNTL_RING0, 2632 PRIV_REG_INT_ENABLE, 2633 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2634 break; 2635 default: 2636 break; 2637 } 2638 2639 return 0; 2640 } 2641 2642 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2643 struct amdgpu_irq_src *source, 2644 unsigned type, 2645 enum amdgpu_interrupt_state state) 2646 { 2647 int i; 2648 2649 switch (state) { 2650 case AMDGPU_IRQ_STATE_DISABLE: 2651 case AMDGPU_IRQ_STATE_ENABLE: 2652 for (i = 0; i < adev->gfx.num_xcd; i++) 2653 WREG32_FIELD15_PREREG(GC, i, CP_INT_CNTL_RING0, 2654 PRIV_INSTR_INT_ENABLE, 2655 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2656 break; 2657 default: 2658 break; 2659 } 2660 2661 return 0; 2662 } 2663 2664 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2665 struct amdgpu_irq_src *src, 2666 unsigned type, 2667 enum amdgpu_interrupt_state state) 2668 { 2669 int i; 2670 for (i = 0; i < adev->gfx.num_xcd; i++) { 2671 switch (type) { 2672 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2673 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 0, state, i); 2674 break; 2675 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2676 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 1, state, i); 2677 break; 2678 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2679 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 2, state, i); 2680 break; 2681 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2682 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 1, 3, state, i); 2683 break; 2684 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2685 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 0, state, i); 2686 break; 2687 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2688 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 1, state, i); 2689 break; 2690 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2691 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 2, state, i); 2692 break; 2693 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2694 gfx_v9_4_3_set_compute_eop_interrupt_state(adev, 2, 3, state, i); 2695 break; 2696 default: 2697 break; 2698 } 2699 } 2700 2701 return 0; 2702 } 2703 2704 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2705 struct amdgpu_irq_src *source, 2706 struct amdgpu_iv_entry *entry) 2707 { 2708 int i; 2709 u8 me_id, pipe_id, queue_id; 2710 struct amdgpu_ring *ring; 2711 2712 DRM_DEBUG("IH: CP EOP\n"); 2713 me_id = (entry->ring_id & 0x0c) >> 2; 2714 pipe_id = (entry->ring_id & 0x03) >> 0; 2715 queue_id = (entry->ring_id & 0x70) >> 4; 2716 2717 switch (me_id) { 2718 case 0: 2719 case 1: 2720 case 2: 2721 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2722 ring = &adev->gfx.compute_ring[i]; 2723 /* Per-queue interrupt is supported for MEC starting from VI. 2724 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2725 */ 2726 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2727 amdgpu_fence_process(ring); 2728 } 2729 break; 2730 } 2731 return 0; 2732 } 2733 2734 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2735 struct amdgpu_iv_entry *entry) 2736 { 2737 u8 me_id, pipe_id, queue_id; 2738 struct amdgpu_ring *ring; 2739 int i; 2740 2741 me_id = (entry->ring_id & 0x0c) >> 2; 2742 pipe_id = (entry->ring_id & 0x03) >> 0; 2743 queue_id = (entry->ring_id & 0x70) >> 4; 2744 2745 switch (me_id) { 2746 case 0: 2747 case 1: 2748 case 2: 2749 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2750 ring = &adev->gfx.compute_ring[i]; 2751 if (ring->me == me_id && ring->pipe == pipe_id && 2752 ring->queue == queue_id) 2753 drm_sched_fault(&ring->sched); 2754 } 2755 break; 2756 } 2757 } 2758 2759 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2760 struct amdgpu_irq_src *source, 2761 struct amdgpu_iv_entry *entry) 2762 { 2763 DRM_ERROR("Illegal register access in command stream\n"); 2764 gfx_v9_4_3_fault(adev, entry); 2765 return 0; 2766 } 2767 2768 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2769 struct amdgpu_irq_src *source, 2770 struct amdgpu_iv_entry *entry) 2771 { 2772 DRM_ERROR("Illegal instruction in command stream\n"); 2773 gfx_v9_4_3_fault(adev, entry); 2774 return 0; 2775 } 2776 2777 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2778 { 2779 const unsigned int cp_coher_cntl = 2780 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2781 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2782 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2783 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2784 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2785 2786 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2787 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2788 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2789 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2790 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2791 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2792 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2793 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2794 } 2795 2796 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2797 uint32_t pipe, bool enable) 2798 { 2799 struct amdgpu_device *adev = ring->adev; 2800 uint32_t val; 2801 uint32_t wcl_cs_reg; 2802 2803 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2804 val = enable ? 0x1 : 0x7f; 2805 2806 switch (pipe) { 2807 case 0: 2808 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS0); 2809 break; 2810 case 1: 2811 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS1); 2812 break; 2813 case 2: 2814 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS2); 2815 break; 2816 case 3: 2817 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_CS3); 2818 break; 2819 default: 2820 DRM_DEBUG("invalid pipe %d\n", pipe); 2821 return; 2822 } 2823 2824 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2825 2826 } 2827 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2828 { 2829 struct amdgpu_device *adev = ring->adev; 2830 uint32_t val; 2831 int i; 2832 2833 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2834 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2835 * around 25% of gpu resources. 2836 */ 2837 val = enable ? 0x1f : 0x07ffffff; 2838 amdgpu_ring_emit_wreg(ring, 2839 SOC15_REG_OFFSET(GC, 0, regSPI_WCL_PIPE_PERCENT_GFX), 2840 val); 2841 2842 /* Restrict waves for normal/low priority compute queues as well 2843 * to get best QoS for high priority compute jobs. 2844 * 2845 * amdgpu controls only 1st ME(0-3 CS pipes). 2846 */ 2847 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2848 if (i != ring->pipe) 2849 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 2850 2851 } 2852 } 2853 2854 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 2855 .name = "gfx_v9_4_3", 2856 .early_init = gfx_v9_4_3_early_init, 2857 .late_init = gfx_v9_4_3_late_init, 2858 .sw_init = gfx_v9_4_3_sw_init, 2859 .sw_fini = gfx_v9_4_3_sw_fini, 2860 .hw_init = gfx_v9_4_3_hw_init, 2861 .hw_fini = gfx_v9_4_3_hw_fini, 2862 .suspend = gfx_v9_4_3_suspend, 2863 .resume = gfx_v9_4_3_resume, 2864 .is_idle = gfx_v9_4_3_is_idle, 2865 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 2866 .soft_reset = gfx_v9_4_3_soft_reset, 2867 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 2868 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 2869 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 2870 }; 2871 2872 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 2873 .type = AMDGPU_RING_TYPE_COMPUTE, 2874 .align_mask = 0xff, 2875 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 2876 .support_64bit_ptrs = true, 2877 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 2878 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 2879 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 2880 .emit_frame_size = 2881 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 2882 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 2883 5 + /* hdp invalidate */ 2884 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 2885 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 2886 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2887 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 2888 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 2889 7 + /* gfx_v9_4_3_emit_mem_sync */ 2890 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 2891 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 2892 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 2893 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 2894 .emit_fence = gfx_v9_4_3_ring_emit_fence, 2895 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 2896 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 2897 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 2898 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 2899 .test_ring = gfx_v9_4_3_ring_test_ring, 2900 .test_ib = gfx_v9_4_3_ring_test_ib, 2901 .insert_nop = amdgpu_ring_insert_nop, 2902 .pad_ib = amdgpu_ring_generic_pad_ib, 2903 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 2904 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 2905 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 2906 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 2907 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 2908 }; 2909 2910 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 2911 .type = AMDGPU_RING_TYPE_KIQ, 2912 .align_mask = 0xff, 2913 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 2914 .support_64bit_ptrs = true, 2915 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 2916 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 2917 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 2918 .emit_frame_size = 2919 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 2920 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 2921 5 + /* hdp invalidate */ 2922 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 2923 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 2924 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2925 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 2926 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 2927 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 2928 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 2929 .test_ring = gfx_v9_4_3_ring_test_ring, 2930 .insert_nop = amdgpu_ring_insert_nop, 2931 .pad_ib = amdgpu_ring_generic_pad_ib, 2932 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 2933 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 2934 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 2935 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 2936 }; 2937 2938 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 2939 { 2940 int i, j; 2941 2942 for (i = 0; i < adev->gfx.num_xcd; i++) { 2943 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 2944 2945 for (j = 0; j < adev->gfx.num_compute_rings; j++) 2946 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 2947 = &gfx_v9_4_3_ring_funcs_compute; 2948 } 2949 } 2950 2951 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 2952 .set = gfx_v9_4_3_set_eop_interrupt_state, 2953 .process = gfx_v9_4_3_eop_irq, 2954 }; 2955 2956 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 2957 .set = gfx_v9_4_3_set_priv_reg_fault_state, 2958 .process = gfx_v9_4_3_priv_reg_irq, 2959 }; 2960 2961 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 2962 .set = gfx_v9_4_3_set_priv_inst_fault_state, 2963 .process = gfx_v9_4_3_priv_inst_irq, 2964 }; 2965 2966 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 2967 { 2968 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 2969 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 2970 2971 adev->gfx.priv_reg_irq.num_types = 1; 2972 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 2973 2974 adev->gfx.priv_inst_irq.num_types = 1; 2975 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 2976 } 2977 2978 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 2979 { 2980 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 2981 } 2982 2983 2984 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 2985 { 2986 /* init asci gds info */ 2987 switch (adev->ip_versions[GC_HWIP][0]) { 2988 case IP_VERSION(9, 4, 3): 2989 /* 9.4.3 removed all the GDS internal memory, 2990 * only support GWS opcode in kernel, like barrier 2991 * semaphore.etc */ 2992 adev->gds.gds_size = 0; 2993 break; 2994 default: 2995 adev->gds.gds_size = 0x10000; 2996 break; 2997 } 2998 2999 switch (adev->ip_versions[GC_HWIP][0]) { 3000 case IP_VERSION(9, 4, 3): 3001 /* deprecated for 9.4.3, no usage at all */ 3002 adev->gds.gds_compute_max_wave_id = 0; 3003 break; 3004 default: 3005 /* this really depends on the chip */ 3006 adev->gds.gds_compute_max_wave_id = 0x7ff; 3007 break; 3008 } 3009 3010 adev->gds.gws_size = 64; 3011 adev->gds.oa_size = 16; 3012 } 3013 3014 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3015 u32 bitmap) 3016 { 3017 u32 data; 3018 3019 if (!bitmap) 3020 return; 3021 3022 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3023 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3024 3025 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); 3026 } 3027 3028 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 3029 { 3030 u32 data, mask; 3031 3032 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); 3033 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); 3034 3035 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3036 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3037 3038 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3039 3040 return (~data) & mask; 3041 } 3042 3043 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 3044 struct amdgpu_cu_info *cu_info) 3045 { 3046 int i, j, k, counter, active_cu_number = 0; 3047 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3048 unsigned disable_masks[4 * 4]; 3049 3050 if (!adev || !cu_info) 3051 return -EINVAL; 3052 3053 /* 3054 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 3055 */ 3056 if (adev->gfx.config.max_shader_engines * 3057 adev->gfx.config.max_sh_per_se > 16) 3058 return -EINVAL; 3059 3060 amdgpu_gfx_parse_disable_cu(disable_masks, 3061 adev->gfx.config.max_shader_engines, 3062 adev->gfx.config.max_sh_per_se); 3063 3064 mutex_lock(&adev->grbm_idx_mutex); 3065 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3066 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3067 mask = 1; 3068 ao_bitmap = 0; 3069 counter = 0; 3070 gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, 0); 3071 gfx_v9_4_3_set_user_cu_inactive_bitmap( 3072 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 3073 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 3074 3075 /* 3076 * The bitmap(and ao_cu_bitmap) in cu_info structure is 3077 * 4x4 size array, and it's usually suitable for Vega 3078 * ASICs which has 4*2 SE/SH layout. 3079 * But for Arcturus, SE/SH layout is changed to 8*1. 3080 * To mostly reduce the impact, we make it compatible 3081 * with current bitmap array as below: 3082 * SE4,SH0 --> bitmap[0][1] 3083 * SE5,SH0 --> bitmap[1][1] 3084 * SE6,SH0 --> bitmap[2][1] 3085 * SE7,SH0 --> bitmap[3][1] 3086 */ 3087 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 3088 3089 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3090 if (bitmap & mask) { 3091 if (counter < adev->gfx.config.max_cu_per_sh) 3092 ao_bitmap |= mask; 3093 counter++; 3094 } 3095 mask <<= 1; 3096 } 3097 active_cu_number += counter; 3098 if (i < 2 && j < 2) 3099 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3100 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 3101 } 3102 } 3103 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3104 mutex_unlock(&adev->grbm_idx_mutex); 3105 3106 cu_info->number = active_cu_number; 3107 cu_info->ao_cu_mask = ao_cu_mask; 3108 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 3109 3110 return 0; 3111 } 3112 3113 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 3114 .type = AMD_IP_BLOCK_TYPE_GFX, 3115 .major = 9, 3116 .minor = 4, 3117 .rev = 0, 3118 .funcs = &gfx_v9_4_3_ip_funcs, 3119 }; 3120