1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 50 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 51 52 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 53 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 56 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 57 struct amdgpu_cu_info *cu_info); 58 59 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 60 uint64_t queue_mask) 61 { 62 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 63 amdgpu_ring_write(kiq_ring, 64 PACKET3_SET_RESOURCES_VMID_MASK(0) | 65 /* vmid_mask:0* queue_type:0 (KIQ) */ 66 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 67 amdgpu_ring_write(kiq_ring, 68 lower_32_bits(queue_mask)); /* queue mask lo */ 69 amdgpu_ring_write(kiq_ring, 70 upper_32_bits(queue_mask)); /* queue mask hi */ 71 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 73 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 74 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 75 } 76 77 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 78 struct amdgpu_ring *ring) 79 { 80 struct amdgpu_device *adev = kiq_ring->adev; 81 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 82 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 83 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 84 85 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 86 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 87 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 88 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 89 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 90 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 91 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 92 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 93 /*queue_type: normal compute queue */ 94 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 95 /* alloc format: all_on_one_pipe */ 96 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 97 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 98 /* num_queues: must be 1 */ 99 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 100 amdgpu_ring_write(kiq_ring, 101 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 102 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 103 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 105 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 106 } 107 108 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 109 struct amdgpu_ring *ring, 110 enum amdgpu_unmap_queues_action action, 111 u64 gpu_addr, u64 seq) 112 { 113 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 114 115 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 116 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 117 PACKET3_UNMAP_QUEUES_ACTION(action) | 118 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 119 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 120 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 121 amdgpu_ring_write(kiq_ring, 122 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 123 124 if (action == PREEMPT_QUEUES_NO_UNMAP) { 125 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 126 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, seq); 128 } else { 129 amdgpu_ring_write(kiq_ring, 0); 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 } 133 } 134 135 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 136 struct amdgpu_ring *ring, 137 u64 addr, 138 u64 seq) 139 { 140 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 141 142 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 143 amdgpu_ring_write(kiq_ring, 144 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 145 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 146 PACKET3_QUERY_STATUS_COMMAND(2)); 147 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 148 amdgpu_ring_write(kiq_ring, 149 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 150 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 151 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 152 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 154 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 155 } 156 157 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 158 uint16_t pasid, uint32_t flush_type, 159 bool all_hub) 160 { 161 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 162 amdgpu_ring_write(kiq_ring, 163 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 164 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 165 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 166 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 167 } 168 169 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 170 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 171 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 172 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 173 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 174 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 175 .set_resources_size = 8, 176 .map_queues_size = 7, 177 .unmap_queues_size = 6, 178 .query_status_size = 7, 179 .invalidate_tlbs_size = 2, 180 }; 181 182 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 183 { 184 int i, num_xcc; 185 186 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 187 for (i = 0; i < num_xcc; i++) 188 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 189 } 190 191 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 192 { 193 int i, num_xcc, dev_inst; 194 195 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 196 for (i = 0; i < num_xcc; i++) { 197 dev_inst = GET_INST(GC, i); 198 199 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 200 GOLDEN_GB_ADDR_CONFIG); 201 /* Golden settings applied by driver for ASIC with rev_id 0 */ 202 if (adev->rev_id == 0) { 203 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 204 REDUCE_FIFO_DEPTH_BY_2, 2); 205 } 206 } 207 } 208 209 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 210 bool wc, uint32_t reg, uint32_t val) 211 { 212 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 213 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 214 WRITE_DATA_DST_SEL(0) | 215 (wc ? WR_CONFIRM : 0)); 216 amdgpu_ring_write(ring, reg); 217 amdgpu_ring_write(ring, 0); 218 amdgpu_ring_write(ring, val); 219 } 220 221 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 222 int mem_space, int opt, uint32_t addr0, 223 uint32_t addr1, uint32_t ref, uint32_t mask, 224 uint32_t inv) 225 { 226 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 227 amdgpu_ring_write(ring, 228 /* memory (1) or register (0) */ 229 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 230 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 231 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 232 WAIT_REG_MEM_ENGINE(eng_sel))); 233 234 if (mem_space) 235 BUG_ON(addr0 & 0x3); /* Dword align */ 236 amdgpu_ring_write(ring, addr0); 237 amdgpu_ring_write(ring, addr1); 238 amdgpu_ring_write(ring, ref); 239 amdgpu_ring_write(ring, mask); 240 amdgpu_ring_write(ring, inv); /* poll interval */ 241 } 242 243 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 244 { 245 uint32_t scratch_reg0_offset, xcc_offset; 246 struct amdgpu_device *adev = ring->adev; 247 uint32_t tmp = 0; 248 unsigned i; 249 int r; 250 251 /* Use register offset which is local to XCC in the packet */ 252 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 253 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 254 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 255 256 r = amdgpu_ring_alloc(ring, 3); 257 if (r) 258 return r; 259 260 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 261 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 262 amdgpu_ring_write(ring, 0xDEADBEEF); 263 amdgpu_ring_commit(ring); 264 265 for (i = 0; i < adev->usec_timeout; i++) { 266 tmp = RREG32(scratch_reg0_offset); 267 if (tmp == 0xDEADBEEF) 268 break; 269 udelay(1); 270 } 271 272 if (i >= adev->usec_timeout) 273 r = -ETIMEDOUT; 274 return r; 275 } 276 277 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 278 { 279 struct amdgpu_device *adev = ring->adev; 280 struct amdgpu_ib ib; 281 struct dma_fence *f = NULL; 282 283 unsigned index; 284 uint64_t gpu_addr; 285 uint32_t tmp; 286 long r; 287 288 r = amdgpu_device_wb_get(adev, &index); 289 if (r) 290 return r; 291 292 gpu_addr = adev->wb.gpu_addr + (index * 4); 293 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 294 memset(&ib, 0, sizeof(ib)); 295 r = amdgpu_ib_get(adev, NULL, 16, 296 AMDGPU_IB_POOL_DIRECT, &ib); 297 if (r) 298 goto err1; 299 300 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 301 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 302 ib.ptr[2] = lower_32_bits(gpu_addr); 303 ib.ptr[3] = upper_32_bits(gpu_addr); 304 ib.ptr[4] = 0xDEADBEEF; 305 ib.length_dw = 5; 306 307 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 308 if (r) 309 goto err2; 310 311 r = dma_fence_wait_timeout(f, false, timeout); 312 if (r == 0) { 313 r = -ETIMEDOUT; 314 goto err2; 315 } else if (r < 0) { 316 goto err2; 317 } 318 319 tmp = adev->wb.wb[index]; 320 if (tmp == 0xDEADBEEF) 321 r = 0; 322 else 323 r = -EINVAL; 324 325 err2: 326 amdgpu_ib_free(adev, &ib, NULL); 327 dma_fence_put(f); 328 err1: 329 amdgpu_device_wb_free(adev, index); 330 return r; 331 } 332 333 334 /* This value might differs per partition */ 335 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 336 { 337 uint64_t clock; 338 339 amdgpu_gfx_off_ctrl(adev, false); 340 mutex_lock(&adev->gfx.gpu_clock_mutex); 341 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 342 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 343 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 344 mutex_unlock(&adev->gfx.gpu_clock_mutex); 345 amdgpu_gfx_off_ctrl(adev, true); 346 347 return clock; 348 } 349 350 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 351 { 352 amdgpu_ucode_release(&adev->gfx.pfp_fw); 353 amdgpu_ucode_release(&adev->gfx.me_fw); 354 amdgpu_ucode_release(&adev->gfx.ce_fw); 355 amdgpu_ucode_release(&adev->gfx.rlc_fw); 356 amdgpu_ucode_release(&adev->gfx.mec_fw); 357 amdgpu_ucode_release(&adev->gfx.mec2_fw); 358 359 kfree(adev->gfx.rlc.register_list_format); 360 } 361 362 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 363 const char *chip_name) 364 { 365 char fw_name[30]; 366 int err; 367 const struct rlc_firmware_header_v2_0 *rlc_hdr; 368 uint16_t version_major; 369 uint16_t version_minor; 370 371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 372 373 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 374 if (err) 375 goto out; 376 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 377 378 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 379 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 380 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 381 out: 382 if (err) 383 amdgpu_ucode_release(&adev->gfx.rlc_fw); 384 385 return err; 386 } 387 388 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 389 { 390 return true; 391 } 392 393 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 394 { 395 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 396 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 397 } 398 399 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 400 const char *chip_name) 401 { 402 char fw_name[30]; 403 int err; 404 405 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 406 407 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 408 if (err) 409 goto out; 410 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 411 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 412 413 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 414 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 415 416 gfx_v9_4_3_check_if_need_gfxoff(adev); 417 418 out: 419 if (err) 420 amdgpu_ucode_release(&adev->gfx.mec_fw); 421 return err; 422 } 423 424 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 425 { 426 const char *chip_name; 427 int r; 428 429 chip_name = "gc_9_4_3"; 430 431 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 432 if (r) 433 return r; 434 435 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 436 if (r) 437 return r; 438 439 return r; 440 } 441 442 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 443 { 444 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 445 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 446 } 447 448 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 449 { 450 int r, i, num_xcc; 451 u32 *hpd; 452 const __le32 *fw_data; 453 unsigned fw_size; 454 u32 *fw; 455 size_t mec_hpd_size; 456 457 const struct gfx_firmware_header_v1_0 *mec_hdr; 458 459 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 460 for (i = 0; i < num_xcc; i++) 461 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 462 AMDGPU_MAX_COMPUTE_QUEUES); 463 464 /* take ownership of the relevant compute queues */ 465 amdgpu_gfx_compute_queue_acquire(adev); 466 mec_hpd_size = 467 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 468 if (mec_hpd_size) { 469 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 470 AMDGPU_GEM_DOMAIN_VRAM | 471 AMDGPU_GEM_DOMAIN_GTT, 472 &adev->gfx.mec.hpd_eop_obj, 473 &adev->gfx.mec.hpd_eop_gpu_addr, 474 (void **)&hpd); 475 if (r) { 476 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 477 gfx_v9_4_3_mec_fini(adev); 478 return r; 479 } 480 481 if (amdgpu_emu_mode == 1) { 482 for (i = 0; i < mec_hpd_size / 4; i++) { 483 memset((void *)(hpd + i), 0, 4); 484 if (i % 50 == 0) 485 msleep(1); 486 } 487 } else { 488 memset(hpd, 0, mec_hpd_size); 489 } 490 491 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 492 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 493 } 494 495 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 496 497 fw_data = (const __le32 *) 498 (adev->gfx.mec_fw->data + 499 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 500 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 501 502 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 504 &adev->gfx.mec.mec_fw_obj, 505 &adev->gfx.mec.mec_fw_gpu_addr, 506 (void **)&fw); 507 if (r) { 508 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 509 gfx_v9_4_3_mec_fini(adev); 510 return r; 511 } 512 513 memcpy(fw, fw_data, fw_size); 514 515 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 516 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 517 518 return 0; 519 } 520 521 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 522 u32 sh_num, u32 instance, int xcc_id) 523 { 524 u32 data; 525 526 if (instance == 0xffffffff) 527 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 528 INSTANCE_BROADCAST_WRITES, 1); 529 else 530 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 531 INSTANCE_INDEX, instance); 532 533 if (se_num == 0xffffffff) 534 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 535 SE_BROADCAST_WRITES, 1); 536 else 537 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 538 539 if (sh_num == 0xffffffff) 540 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 541 SH_BROADCAST_WRITES, 1); 542 else 543 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 544 545 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 546 } 547 548 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 549 { 550 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 551 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 552 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 553 (address << SQ_IND_INDEX__INDEX__SHIFT) | 554 (SQ_IND_INDEX__FORCE_READ_MASK)); 555 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 556 } 557 558 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 559 uint32_t wave, uint32_t thread, 560 uint32_t regno, uint32_t num, uint32_t *out) 561 { 562 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 563 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 564 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 565 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 566 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 567 (SQ_IND_INDEX__FORCE_READ_MASK) | 568 (SQ_IND_INDEX__AUTO_INCR_MASK)); 569 while (num--) 570 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 571 } 572 573 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 574 uint32_t xcc_id, uint32_t simd, uint32_t wave, 575 uint32_t *dst, int *no_fields) 576 { 577 /* type 1 wave data */ 578 dst[(*no_fields)++] = 1; 579 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 594 } 595 596 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 597 uint32_t wave, uint32_t start, 598 uint32_t size, uint32_t *dst) 599 { 600 wave_read_regs(adev, xcc_id, simd, wave, 0, 601 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 602 } 603 604 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 605 uint32_t wave, uint32_t thread, 606 uint32_t start, uint32_t size, 607 uint32_t *dst) 608 { 609 wave_read_regs(adev, xcc_id, simd, wave, thread, 610 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 611 } 612 613 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 614 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 615 { 616 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 617 } 618 619 620 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 621 int num_xccs_per_xcp) 622 { 623 int ret, i, num_xcc; 624 u32 tmp = 0; 625 626 if (adev->psp.funcs) { 627 ret = psp_spatial_partition(&adev->psp, 628 NUM_XCC(adev->gfx.xcc_mask) / 629 num_xccs_per_xcp); 630 if (ret) 631 return ret; 632 } else { 633 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 634 635 for (i = 0; i < num_xcc; i++) { 636 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 637 num_xccs_per_xcp); 638 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 639 i % num_xccs_per_xcp); 640 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 641 tmp); 642 } 643 ret = 0; 644 } 645 646 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 647 648 return ret; 649 } 650 651 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 652 { 653 int xcc; 654 655 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 656 if (!xcc) { 657 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 658 return -EINVAL; 659 } 660 661 return xcc - 1; 662 } 663 664 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 665 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 666 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 667 .read_wave_data = &gfx_v9_4_3_read_wave_data, 668 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 669 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 670 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 671 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 672 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 673 }; 674 675 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 676 { 677 u32 gb_addr_config; 678 679 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 680 adev->gfx.ras = &gfx_v9_4_3_ras; 681 682 switch (adev->ip_versions[GC_HWIP][0]) { 683 case IP_VERSION(9, 4, 3): 684 adev->gfx.config.max_hw_contexts = 8; 685 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 686 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 687 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 688 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 689 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 690 break; 691 default: 692 BUG(); 693 break; 694 } 695 696 adev->gfx.config.gb_addr_config = gb_addr_config; 697 698 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 699 REG_GET_FIELD( 700 adev->gfx.config.gb_addr_config, 701 GB_ADDR_CONFIG, 702 NUM_PIPES); 703 704 adev->gfx.config.max_tile_pipes = 705 adev->gfx.config.gb_addr_config_fields.num_pipes; 706 707 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 708 REG_GET_FIELD( 709 adev->gfx.config.gb_addr_config, 710 GB_ADDR_CONFIG, 711 NUM_BANKS); 712 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 713 REG_GET_FIELD( 714 adev->gfx.config.gb_addr_config, 715 GB_ADDR_CONFIG, 716 MAX_COMPRESSED_FRAGS); 717 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 718 REG_GET_FIELD( 719 adev->gfx.config.gb_addr_config, 720 GB_ADDR_CONFIG, 721 NUM_RB_PER_SE); 722 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 723 REG_GET_FIELD( 724 adev->gfx.config.gb_addr_config, 725 GB_ADDR_CONFIG, 726 NUM_SHADER_ENGINES); 727 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 728 REG_GET_FIELD( 729 adev->gfx.config.gb_addr_config, 730 GB_ADDR_CONFIG, 731 PIPE_INTERLEAVE_SIZE)); 732 733 return 0; 734 } 735 736 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 737 int xcc_id, int mec, int pipe, int queue) 738 { 739 unsigned irq_type; 740 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 741 unsigned int hw_prio; 742 uint32_t xcc_doorbell_start; 743 744 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 745 ring_id]; 746 747 /* mec0 is me1 */ 748 ring->xcc_id = xcc_id; 749 ring->me = mec + 1; 750 ring->pipe = pipe; 751 ring->queue = queue; 752 753 ring->ring_obj = NULL; 754 ring->use_doorbell = true; 755 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 756 xcc_id * adev->doorbell_index.xcc_doorbell_range; 757 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 758 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 759 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 760 GFX9_MEC_HPD_SIZE; 761 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 762 sprintf(ring->name, "comp_%d.%d.%d.%d", 763 ring->xcc_id, ring->me, ring->pipe, ring->queue); 764 765 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 766 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 767 + ring->pipe; 768 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 769 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 770 /* type-2 packets are deprecated on MEC, use type-3 instead */ 771 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 772 hw_prio, NULL); 773 } 774 775 static int gfx_v9_4_3_sw_init(void *handle) 776 { 777 int i, j, k, r, ring_id, xcc_id, num_xcc; 778 struct amdgpu_kiq *kiq; 779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 780 781 adev->gfx.mec.num_mec = 2; 782 adev->gfx.mec.num_pipe_per_mec = 4; 783 adev->gfx.mec.num_queue_per_pipe = 8; 784 785 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 786 787 /* EOP Event */ 788 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 789 if (r) 790 return r; 791 792 /* Privileged reg */ 793 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 794 &adev->gfx.priv_reg_irq); 795 if (r) 796 return r; 797 798 /* Privileged inst */ 799 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 800 &adev->gfx.priv_inst_irq); 801 if (r) 802 return r; 803 804 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 805 806 r = adev->gfx.rlc.funcs->init(adev); 807 if (r) { 808 DRM_ERROR("Failed to init rlc BOs!\n"); 809 return r; 810 } 811 812 r = gfx_v9_4_3_mec_init(adev); 813 if (r) { 814 DRM_ERROR("Failed to init MEC BOs!\n"); 815 return r; 816 } 817 818 /* set up the compute queues - allocate horizontally across pipes */ 819 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 820 ring_id = 0; 821 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 822 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 823 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 824 k++) { 825 if (!amdgpu_gfx_is_mec_queue_enabled( 826 adev, xcc_id, i, k, j)) 827 continue; 828 829 r = gfx_v9_4_3_compute_ring_init(adev, 830 ring_id, 831 xcc_id, 832 i, k, j); 833 if (r) 834 return r; 835 836 ring_id++; 837 } 838 } 839 } 840 841 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 842 if (r) { 843 DRM_ERROR("Failed to init KIQ BOs!\n"); 844 return r; 845 } 846 847 kiq = &adev->gfx.kiq[xcc_id]; 848 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 849 if (r) 850 return r; 851 852 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 853 r = amdgpu_gfx_mqd_sw_init(adev, 854 sizeof(struct v9_mqd_allocation), xcc_id); 855 if (r) 856 return r; 857 } 858 859 r = gfx_v9_4_3_gpu_early_init(adev); 860 if (r) 861 return r; 862 863 r = amdgpu_gfx_sysfs_init(adev); 864 if (r) 865 return r; 866 867 return amdgpu_gfx_ras_sw_init(adev); 868 } 869 870 static int gfx_v9_4_3_sw_fini(void *handle) 871 { 872 int i, num_xcc; 873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 874 875 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 876 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 877 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 878 879 for (i = 0; i < num_xcc; i++) { 880 amdgpu_gfx_mqd_sw_fini(adev, i); 881 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 882 amdgpu_gfx_kiq_fini(adev, i); 883 } 884 885 gfx_v9_4_3_mec_fini(adev); 886 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 887 gfx_v9_4_3_free_microcode(adev); 888 amdgpu_gfx_sysfs_fini(adev); 889 890 return 0; 891 } 892 893 #define DEFAULT_SH_MEM_BASES (0x6000) 894 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 895 int xcc_id) 896 { 897 int i; 898 uint32_t sh_mem_config; 899 uint32_t sh_mem_bases; 900 901 /* 902 * Configure apertures: 903 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 904 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 905 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 906 */ 907 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 908 909 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 910 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 911 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 912 913 mutex_lock(&adev->srbm_mutex); 914 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 915 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 916 /* CP and shaders */ 917 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 918 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 919 } 920 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 921 mutex_unlock(&adev->srbm_mutex); 922 923 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 924 acccess. These should be enabled by FW for target VMIDs. */ 925 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 926 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 927 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 928 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 929 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 930 } 931 } 932 933 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 934 { 935 int vmid; 936 937 /* 938 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 939 * access. Compute VMIDs should be enabled by FW for target VMIDs, 940 * the driver can enable them for graphics. VMID0 should maintain 941 * access so that HWS firmware can save/restore entries. 942 */ 943 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 944 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 945 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 946 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 947 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 948 } 949 } 950 951 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 952 int xcc_id) 953 { 954 u32 tmp; 955 int i; 956 957 /* XXX SH_MEM regs */ 958 /* where to put LDS, scratch, GPUVM in FSA64 space */ 959 mutex_lock(&adev->srbm_mutex); 960 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 961 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 962 /* CP and shaders */ 963 if (i == 0) { 964 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 965 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 966 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 967 !!adev->gmc.noretry); 968 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 969 regSH_MEM_CONFIG, tmp); 970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 971 regSH_MEM_BASES, 0); 972 } else { 973 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 974 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 975 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 976 !!adev->gmc.noretry); 977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 978 regSH_MEM_CONFIG, tmp); 979 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 980 (adev->gmc.private_aperture_start >> 981 48)); 982 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 983 (adev->gmc.shared_aperture_start >> 984 48)); 985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 986 regSH_MEM_BASES, tmp); 987 } 988 } 989 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 990 991 mutex_unlock(&adev->srbm_mutex); 992 993 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 994 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 995 } 996 997 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 998 { 999 int i, num_xcc; 1000 1001 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1002 1003 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1004 adev->gfx.config.db_debug2 = 1005 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1006 1007 for (i = 0; i < num_xcc; i++) 1008 gfx_v9_4_3_xcc_constants_init(adev, i); 1009 } 1010 1011 static void 1012 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1013 int xcc_id) 1014 { 1015 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1016 } 1017 1018 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1019 { 1020 /* 1021 * Rlc save restore list is workable since v2_1. 1022 * And it's needed by gfxoff feature. 1023 */ 1024 if (adev->gfx.rlc.is_rlc_v2_1) 1025 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1026 } 1027 1028 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1029 { 1030 uint32_t data; 1031 1032 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1033 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1034 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1035 } 1036 1037 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1038 { 1039 uint32_t rlc_setting; 1040 1041 /* if RLC is not enabled, do nothing */ 1042 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1043 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1044 return false; 1045 1046 return true; 1047 } 1048 1049 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1050 { 1051 uint32_t data; 1052 unsigned i; 1053 1054 data = RLC_SAFE_MODE__CMD_MASK; 1055 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1056 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1057 1058 /* wait for RLC_SAFE_MODE */ 1059 for (i = 0; i < adev->usec_timeout; i++) { 1060 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1061 break; 1062 udelay(1); 1063 } 1064 } 1065 1066 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1067 int xcc_id) 1068 { 1069 uint32_t data; 1070 1071 data = RLC_SAFE_MODE__CMD_MASK; 1072 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1073 } 1074 1075 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1076 { 1077 /* init spm vmid with 0xf */ 1078 if (adev->gfx.rlc.funcs->update_spm_vmid) 1079 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1080 1081 return 0; 1082 } 1083 1084 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1085 int xcc_id) 1086 { 1087 u32 i, j, k; 1088 u32 mask; 1089 1090 mutex_lock(&adev->grbm_idx_mutex); 1091 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1092 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1093 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1094 xcc_id); 1095 for (k = 0; k < adev->usec_timeout; k++) { 1096 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1097 break; 1098 udelay(1); 1099 } 1100 if (k == adev->usec_timeout) { 1101 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1102 0xffffffff, 1103 0xffffffff, xcc_id); 1104 mutex_unlock(&adev->grbm_idx_mutex); 1105 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1106 i, j); 1107 return; 1108 } 1109 } 1110 } 1111 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1112 xcc_id); 1113 mutex_unlock(&adev->grbm_idx_mutex); 1114 1115 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1116 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1117 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1118 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1119 for (k = 0; k < adev->usec_timeout; k++) { 1120 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1121 break; 1122 udelay(1); 1123 } 1124 } 1125 1126 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1127 bool enable, int xcc_id) 1128 { 1129 u32 tmp; 1130 1131 /* These interrupts should be enabled to drive DS clock */ 1132 1133 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1134 1135 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1136 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1137 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1138 1139 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1140 } 1141 1142 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1143 { 1144 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1145 RLC_ENABLE_F32, 0); 1146 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1147 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1148 } 1149 1150 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1151 { 1152 int i, num_xcc; 1153 1154 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1155 for (i = 0; i < num_xcc; i++) 1156 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1157 } 1158 1159 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1160 { 1161 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1162 SOFT_RESET_RLC, 1); 1163 udelay(50); 1164 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1165 SOFT_RESET_RLC, 0); 1166 udelay(50); 1167 } 1168 1169 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1170 { 1171 int i, num_xcc; 1172 1173 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1174 for (i = 0; i < num_xcc; i++) 1175 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1176 } 1177 1178 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1179 { 1180 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1181 RLC_ENABLE_F32, 1); 1182 udelay(50); 1183 1184 /* carrizo do enable cp interrupt after cp inited */ 1185 if (!(adev->flags & AMD_IS_APU)) { 1186 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1187 udelay(50); 1188 } 1189 } 1190 1191 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1192 { 1193 #ifdef AMDGPU_RLC_DEBUG_RETRY 1194 u32 rlc_ucode_ver; 1195 #endif 1196 int i, num_xcc; 1197 1198 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1199 for (i = 0; i < num_xcc; i++) { 1200 gfx_v9_4_3_xcc_rlc_start(adev, i); 1201 #ifdef AMDGPU_RLC_DEBUG_RETRY 1202 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1203 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1204 if (rlc_ucode_ver == 0x108) { 1205 dev_info(adev->dev, 1206 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1207 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1208 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1209 * default is 0x9C4 to create a 100us interval */ 1210 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1211 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1212 * to disable the page fault retry interrupts, default is 1213 * 0x100 (256) */ 1214 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1215 } 1216 #endif 1217 } 1218 } 1219 1220 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1221 int xcc_id) 1222 { 1223 const struct rlc_firmware_header_v2_0 *hdr; 1224 const __le32 *fw_data; 1225 unsigned i, fw_size; 1226 1227 if (!adev->gfx.rlc_fw) 1228 return -EINVAL; 1229 1230 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1231 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1232 1233 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1234 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1235 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1236 1237 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1238 RLCG_UCODE_LOADING_START_ADDRESS); 1239 for (i = 0; i < fw_size; i++) { 1240 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1241 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1242 msleep(1); 1243 } 1244 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1245 } 1246 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1247 1248 return 0; 1249 } 1250 1251 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1252 { 1253 int r; 1254 1255 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1256 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1257 /* legacy rlc firmware loading */ 1258 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1259 if (r) 1260 return r; 1261 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1262 } 1263 1264 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1265 /* disable CG */ 1266 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1267 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1268 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1269 1270 return 0; 1271 } 1272 1273 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1274 { 1275 int r, i, num_xcc; 1276 1277 if (amdgpu_sriov_vf(adev)) 1278 return 0; 1279 1280 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1281 for (i = 0; i < num_xcc; i++) { 1282 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1283 if (r) 1284 return r; 1285 } 1286 1287 return 0; 1288 } 1289 1290 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1291 unsigned vmid) 1292 { 1293 u32 reg, data; 1294 1295 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1296 if (amdgpu_sriov_is_pp_one_vf(adev)) 1297 data = RREG32_NO_KIQ(reg); 1298 else 1299 data = RREG32(reg); 1300 1301 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1302 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1303 1304 if (amdgpu_sriov_is_pp_one_vf(adev)) 1305 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1306 else 1307 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1308 } 1309 1310 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1311 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1312 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1313 }; 1314 1315 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1316 uint32_t offset, 1317 struct soc15_reg_rlcg *entries, int arr_size) 1318 { 1319 int i, inst; 1320 uint32_t reg; 1321 1322 if (!entries) 1323 return false; 1324 1325 for (i = 0; i < arr_size; i++) { 1326 const struct soc15_reg_rlcg *entry; 1327 1328 entry = &entries[i]; 1329 inst = adev->ip_map.logical_to_dev_inst ? 1330 adev->ip_map.logical_to_dev_inst( 1331 adev, entry->hwip, entry->instance) : 1332 entry->instance; 1333 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1334 entry->reg; 1335 if (offset == reg) 1336 return true; 1337 } 1338 1339 return false; 1340 } 1341 1342 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1343 { 1344 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1345 (void *)rlcg_access_gc_9_4_3, 1346 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1347 } 1348 1349 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1350 bool enable, int xcc_id) 1351 { 1352 if (enable) { 1353 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1354 } else { 1355 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1356 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1357 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1358 } 1359 udelay(50); 1360 } 1361 1362 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1363 int xcc_id) 1364 { 1365 const struct gfx_firmware_header_v1_0 *mec_hdr; 1366 const __le32 *fw_data; 1367 unsigned i; 1368 u32 tmp; 1369 u32 mec_ucode_addr_offset; 1370 u32 mec_ucode_data_offset; 1371 1372 if (!adev->gfx.mec_fw) 1373 return -EINVAL; 1374 1375 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1376 1377 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1378 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1379 1380 fw_data = (const __le32 *) 1381 (adev->gfx.mec_fw->data + 1382 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1383 tmp = 0; 1384 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1385 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1386 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1387 1388 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1389 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1390 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1391 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1392 1393 mec_ucode_addr_offset = 1394 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1395 mec_ucode_data_offset = 1396 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1397 1398 /* MEC1 */ 1399 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1400 for (i = 0; i < mec_hdr->jt_size; i++) 1401 WREG32(mec_ucode_data_offset, 1402 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1403 1404 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1405 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1406 1407 return 0; 1408 } 1409 1410 /* KIQ functions */ 1411 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1412 { 1413 uint32_t tmp; 1414 struct amdgpu_device *adev = ring->adev; 1415 1416 /* tell RLC which is KIQ queue */ 1417 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1418 tmp &= 0xffffff00; 1419 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1420 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1421 tmp |= 0x80; 1422 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1423 } 1424 1425 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1426 { 1427 struct amdgpu_device *adev = ring->adev; 1428 1429 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1430 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1431 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1432 mqd->cp_hqd_queue_priority = 1433 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1434 } 1435 } 1436 } 1437 1438 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1439 { 1440 struct amdgpu_device *adev = ring->adev; 1441 struct v9_mqd *mqd = ring->mqd_ptr; 1442 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1443 uint32_t tmp; 1444 1445 mqd->header = 0xC0310800; 1446 mqd->compute_pipelinestat_enable = 0x00000001; 1447 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1448 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1449 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1450 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1451 mqd->compute_misc_reserved = 0x00000003; 1452 1453 mqd->dynamic_cu_mask_addr_lo = 1454 lower_32_bits(ring->mqd_gpu_addr 1455 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1456 mqd->dynamic_cu_mask_addr_hi = 1457 upper_32_bits(ring->mqd_gpu_addr 1458 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1459 1460 eop_base_addr = ring->eop_gpu_addr >> 8; 1461 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1462 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1463 1464 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1465 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1466 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1467 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1468 1469 mqd->cp_hqd_eop_control = tmp; 1470 1471 /* enable doorbell? */ 1472 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1473 1474 if (ring->use_doorbell) { 1475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1476 DOORBELL_OFFSET, ring->doorbell_index); 1477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1478 DOORBELL_EN, 1); 1479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1480 DOORBELL_SOURCE, 0); 1481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1482 DOORBELL_HIT, 0); 1483 } else { 1484 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1485 DOORBELL_EN, 0); 1486 } 1487 1488 mqd->cp_hqd_pq_doorbell_control = tmp; 1489 1490 /* disable the queue if it's active */ 1491 ring->wptr = 0; 1492 mqd->cp_hqd_dequeue_request = 0; 1493 mqd->cp_hqd_pq_rptr = 0; 1494 mqd->cp_hqd_pq_wptr_lo = 0; 1495 mqd->cp_hqd_pq_wptr_hi = 0; 1496 1497 /* set the pointer to the MQD */ 1498 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1499 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1500 1501 /* set MQD vmid to 0 */ 1502 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1503 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1504 mqd->cp_mqd_control = tmp; 1505 1506 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1507 hqd_gpu_addr = ring->gpu_addr >> 8; 1508 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1509 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1510 1511 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1512 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1514 (order_base_2(ring->ring_size / 4) - 1)); 1515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1516 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1517 #ifdef __BIG_ENDIAN 1518 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1519 #endif 1520 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1521 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1523 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1524 mqd->cp_hqd_pq_control = tmp; 1525 1526 /* set the wb address whether it's enabled or not */ 1527 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1528 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1529 mqd->cp_hqd_pq_rptr_report_addr_hi = 1530 upper_32_bits(wb_gpu_addr) & 0xffff; 1531 1532 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1533 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1534 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1535 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1536 1537 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1538 ring->wptr = 0; 1539 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1540 1541 /* set the vmid for the queue */ 1542 mqd->cp_hqd_vmid = 0; 1543 1544 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1546 mqd->cp_hqd_persistent_state = tmp; 1547 1548 /* set MIN_IB_AVAIL_SIZE */ 1549 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1550 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1551 mqd->cp_hqd_ib_control = tmp; 1552 1553 /* set static priority for a queue/ring */ 1554 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1555 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1556 1557 /* map_queues packet doesn't need activate the queue, 1558 * so only kiq need set this field. 1559 */ 1560 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1561 mqd->cp_hqd_active = 1; 1562 1563 return 0; 1564 } 1565 1566 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1567 int xcc_id) 1568 { 1569 struct amdgpu_device *adev = ring->adev; 1570 struct v9_mqd *mqd = ring->mqd_ptr; 1571 int j; 1572 1573 /* disable wptr polling */ 1574 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1575 1576 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1577 mqd->cp_hqd_eop_base_addr_lo); 1578 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1579 mqd->cp_hqd_eop_base_addr_hi); 1580 1581 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1582 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1583 mqd->cp_hqd_eop_control); 1584 1585 /* enable doorbell? */ 1586 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1587 mqd->cp_hqd_pq_doorbell_control); 1588 1589 /* disable the queue if it's active */ 1590 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1591 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1592 for (j = 0; j < adev->usec_timeout; j++) { 1593 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1594 break; 1595 udelay(1); 1596 } 1597 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1598 mqd->cp_hqd_dequeue_request); 1599 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1600 mqd->cp_hqd_pq_rptr); 1601 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1602 mqd->cp_hqd_pq_wptr_lo); 1603 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1604 mqd->cp_hqd_pq_wptr_hi); 1605 } 1606 1607 /* set the pointer to the MQD */ 1608 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1609 mqd->cp_mqd_base_addr_lo); 1610 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1611 mqd->cp_mqd_base_addr_hi); 1612 1613 /* set MQD vmid to 0 */ 1614 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1615 mqd->cp_mqd_control); 1616 1617 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1619 mqd->cp_hqd_pq_base_lo); 1620 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1621 mqd->cp_hqd_pq_base_hi); 1622 1623 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1624 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1625 mqd->cp_hqd_pq_control); 1626 1627 /* set the wb address whether it's enabled or not */ 1628 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1629 mqd->cp_hqd_pq_rptr_report_addr_lo); 1630 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1631 mqd->cp_hqd_pq_rptr_report_addr_hi); 1632 1633 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1634 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1635 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1636 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1637 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1638 1639 /* enable the doorbell if requested */ 1640 if (ring->use_doorbell) { 1641 WREG32_SOC15( 1642 GC, GET_INST(GC, xcc_id), 1643 regCP_MEC_DOORBELL_RANGE_LOWER, 1644 ((adev->doorbell_index.kiq + 1645 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1646 2) << 2); 1647 WREG32_SOC15( 1648 GC, GET_INST(GC, xcc_id), 1649 regCP_MEC_DOORBELL_RANGE_UPPER, 1650 ((adev->doorbell_index.userqueue_end + 1651 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1652 2) << 2); 1653 } 1654 1655 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1656 mqd->cp_hqd_pq_doorbell_control); 1657 1658 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1659 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1660 mqd->cp_hqd_pq_wptr_lo); 1661 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1662 mqd->cp_hqd_pq_wptr_hi); 1663 1664 /* set the vmid for the queue */ 1665 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1666 1667 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1668 mqd->cp_hqd_persistent_state); 1669 1670 /* activate the queue */ 1671 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1672 mqd->cp_hqd_active); 1673 1674 if (ring->use_doorbell) 1675 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1676 1677 return 0; 1678 } 1679 1680 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1681 int xcc_id) 1682 { 1683 struct amdgpu_device *adev = ring->adev; 1684 int j; 1685 1686 /* disable the queue if it's active */ 1687 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1688 1689 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1690 1691 for (j = 0; j < adev->usec_timeout; j++) { 1692 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1693 break; 1694 udelay(1); 1695 } 1696 1697 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1698 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1699 1700 /* Manual disable if dequeue request times out */ 1701 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1702 } 1703 1704 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1705 0); 1706 } 1707 1708 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1709 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1710 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 0); 1711 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1712 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1714 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1716 1717 return 0; 1718 } 1719 1720 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1721 { 1722 struct amdgpu_device *adev = ring->adev; 1723 struct v9_mqd *mqd = ring->mqd_ptr; 1724 struct v9_mqd *tmp_mqd; 1725 1726 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1727 1728 /* GPU could be in bad state during probe, driver trigger the reset 1729 * after load the SMU, in this case , the mqd is not be initialized. 1730 * driver need to re-init the mqd. 1731 * check mqd->cp_hqd_pq_control since this value should not be 0 1732 */ 1733 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1734 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1735 /* for GPU_RESET case , reset MQD to a clean status */ 1736 if (adev->gfx.kiq[xcc_id].mqd_backup) 1737 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1738 1739 /* reset ring buffer */ 1740 ring->wptr = 0; 1741 amdgpu_ring_clear_ring(ring); 1742 mutex_lock(&adev->srbm_mutex); 1743 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1744 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1745 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1746 mutex_unlock(&adev->srbm_mutex); 1747 } else { 1748 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1749 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1750 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1751 mutex_lock(&adev->srbm_mutex); 1752 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1753 amdgpu_ring_clear_ring(ring); 1754 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1755 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1756 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1757 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1758 mutex_unlock(&adev->srbm_mutex); 1759 1760 if (adev->gfx.kiq[xcc_id].mqd_backup) 1761 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1768 { 1769 struct amdgpu_device *adev = ring->adev; 1770 struct v9_mqd *mqd = ring->mqd_ptr; 1771 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1772 struct v9_mqd *tmp_mqd; 1773 1774 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1775 * is not be initialized before 1776 */ 1777 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1778 1779 if (!tmp_mqd->cp_hqd_pq_control || 1780 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1781 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1782 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1783 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1784 mutex_lock(&adev->srbm_mutex); 1785 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1786 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1787 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1788 mutex_unlock(&adev->srbm_mutex); 1789 1790 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1791 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1792 } else { 1793 /* restore MQD to a clean status */ 1794 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1795 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1796 /* reset ring buffer */ 1797 ring->wptr = 0; 1798 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1799 amdgpu_ring_clear_ring(ring); 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1806 { 1807 struct amdgpu_ring *ring; 1808 int j; 1809 1810 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1811 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1812 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1813 mutex_lock(&adev->srbm_mutex); 1814 soc15_grbm_select(adev, ring->me, 1815 ring->pipe, 1816 ring->queue, 0, GET_INST(GC, xcc_id)); 1817 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1818 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1819 mutex_unlock(&adev->srbm_mutex); 1820 } 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1827 { 1828 struct amdgpu_ring *ring; 1829 int r; 1830 1831 ring = &adev->gfx.kiq[xcc_id].ring; 1832 1833 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1834 if (unlikely(r != 0)) 1835 return r; 1836 1837 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1838 if (unlikely(r != 0)) { 1839 amdgpu_bo_unreserve(ring->mqd_obj); 1840 return r; 1841 } 1842 1843 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1844 amdgpu_bo_kunmap(ring->mqd_obj); 1845 ring->mqd_ptr = NULL; 1846 amdgpu_bo_unreserve(ring->mqd_obj); 1847 return 0; 1848 } 1849 1850 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1851 { 1852 struct amdgpu_ring *ring = NULL; 1853 int r = 0, i; 1854 1855 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1856 1857 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1858 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1859 1860 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1861 if (unlikely(r != 0)) 1862 goto done; 1863 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1864 if (!r) { 1865 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1866 amdgpu_bo_kunmap(ring->mqd_obj); 1867 ring->mqd_ptr = NULL; 1868 } 1869 amdgpu_bo_unreserve(ring->mqd_obj); 1870 if (r) 1871 goto done; 1872 } 1873 1874 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1875 done: 1876 return r; 1877 } 1878 1879 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1880 { 1881 struct amdgpu_ring *ring; 1882 int r, j; 1883 1884 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1885 1886 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1887 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1888 1889 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1890 if (r) 1891 return r; 1892 } 1893 1894 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1895 if (r) 1896 return r; 1897 1898 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1899 if (r) 1900 return r; 1901 1902 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1903 ring = &adev->gfx.compute_ring 1904 [j + xcc_id * adev->gfx.num_compute_rings]; 1905 r = amdgpu_ring_test_helper(ring); 1906 if (r) 1907 return r; 1908 } 1909 1910 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1911 1912 return 0; 1913 } 1914 1915 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1916 { 1917 int r = 0, i, num_xcc; 1918 1919 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1920 AMDGPU_XCP_FL_NONE) == 1921 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1922 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1923 amdgpu_user_partt_mode); 1924 1925 if (r) 1926 return r; 1927 1928 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1929 for (i = 0; i < num_xcc; i++) { 1930 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1931 if (r) 1932 return r; 1933 } 1934 1935 return 0; 1936 } 1937 1938 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1939 int xcc_id) 1940 { 1941 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1942 } 1943 1944 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1945 { 1946 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1947 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1948 1949 if (amdgpu_sriov_vf(adev)) { 1950 /* must disable polling for SRIOV when hw finished, otherwise 1951 * CPC engine may still keep fetching WB address which is already 1952 * invalid after sw finished and trigger DMAR reading error in 1953 * hypervisor side. 1954 */ 1955 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1956 return; 1957 } 1958 1959 /* Use deinitialize sequence from CAIL when unbinding device 1960 * from driver, otherwise KIQ is hanging when binding back 1961 */ 1962 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1963 mutex_lock(&adev->srbm_mutex); 1964 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1965 adev->gfx.kiq[xcc_id].ring.pipe, 1966 adev->gfx.kiq[xcc_id].ring.queue, 0, 1967 GET_INST(GC, xcc_id)); 1968 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1969 xcc_id); 1970 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1971 mutex_unlock(&adev->srbm_mutex); 1972 } 1973 1974 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 1975 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 1976 } 1977 1978 static int gfx_v9_4_3_hw_init(void *handle) 1979 { 1980 int r; 1981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1982 1983 if (!amdgpu_sriov_vf(adev)) 1984 gfx_v9_4_3_init_golden_registers(adev); 1985 1986 gfx_v9_4_3_constants_init(adev); 1987 1988 r = adev->gfx.rlc.funcs->resume(adev); 1989 if (r) 1990 return r; 1991 1992 r = gfx_v9_4_3_cp_resume(adev); 1993 if (r) 1994 return r; 1995 1996 return r; 1997 } 1998 1999 static int gfx_v9_4_3_hw_fini(void *handle) 2000 { 2001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2002 int i, num_xcc; 2003 2004 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2005 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2006 2007 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2008 for (i = 0; i < num_xcc; i++) { 2009 gfx_v9_4_3_xcc_fini(adev, i); 2010 } 2011 2012 return 0; 2013 } 2014 2015 static int gfx_v9_4_3_suspend(void *handle) 2016 { 2017 return gfx_v9_4_3_hw_fini(handle); 2018 } 2019 2020 static int gfx_v9_4_3_resume(void *handle) 2021 { 2022 return gfx_v9_4_3_hw_init(handle); 2023 } 2024 2025 static bool gfx_v9_4_3_is_idle(void *handle) 2026 { 2027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2028 int i, num_xcc; 2029 2030 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2031 for (i = 0; i < num_xcc; i++) { 2032 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2033 GRBM_STATUS, GUI_ACTIVE)) 2034 return false; 2035 } 2036 return true; 2037 } 2038 2039 static int gfx_v9_4_3_wait_for_idle(void *handle) 2040 { 2041 unsigned i; 2042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2043 2044 for (i = 0; i < adev->usec_timeout; i++) { 2045 if (gfx_v9_4_3_is_idle(handle)) 2046 return 0; 2047 udelay(1); 2048 } 2049 return -ETIMEDOUT; 2050 } 2051 2052 static int gfx_v9_4_3_soft_reset(void *handle) 2053 { 2054 u32 grbm_soft_reset = 0; 2055 u32 tmp; 2056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2057 2058 /* GRBM_STATUS */ 2059 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2060 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2061 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2062 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2063 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2064 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2065 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2066 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2067 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2068 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2069 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2070 } 2071 2072 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2073 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2074 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2075 } 2076 2077 /* GRBM_STATUS2 */ 2078 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2079 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2080 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2081 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2082 2083 2084 if (grbm_soft_reset) { 2085 /* stop the rlc */ 2086 adev->gfx.rlc.funcs->stop(adev); 2087 2088 /* Disable MEC parsing/prefetching */ 2089 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2090 2091 if (grbm_soft_reset) { 2092 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2093 tmp |= grbm_soft_reset; 2094 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2095 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2096 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2097 2098 udelay(50); 2099 2100 tmp &= ~grbm_soft_reset; 2101 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2102 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2103 } 2104 2105 /* Wait a little for things to settle down */ 2106 udelay(50); 2107 } 2108 return 0; 2109 } 2110 2111 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2112 uint32_t vmid, 2113 uint32_t gds_base, uint32_t gds_size, 2114 uint32_t gws_base, uint32_t gws_size, 2115 uint32_t oa_base, uint32_t oa_size) 2116 { 2117 struct amdgpu_device *adev = ring->adev; 2118 2119 /* GDS Base */ 2120 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2121 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2122 gds_base); 2123 2124 /* GDS Size */ 2125 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2126 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2127 gds_size); 2128 2129 /* GWS */ 2130 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2131 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2132 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2133 2134 /* OA */ 2135 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2136 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2137 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2138 } 2139 2140 static int gfx_v9_4_3_early_init(void *handle) 2141 { 2142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2143 2144 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2145 AMDGPU_MAX_COMPUTE_RINGS); 2146 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2147 gfx_v9_4_3_set_ring_funcs(adev); 2148 gfx_v9_4_3_set_irq_funcs(adev); 2149 gfx_v9_4_3_set_gds_init(adev); 2150 gfx_v9_4_3_set_rlc_funcs(adev); 2151 2152 return gfx_v9_4_3_init_microcode(adev); 2153 } 2154 2155 static int gfx_v9_4_3_late_init(void *handle) 2156 { 2157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2158 int r; 2159 2160 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2161 if (r) 2162 return r; 2163 2164 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2165 if (r) 2166 return r; 2167 2168 if (adev->gfx.ras && 2169 adev->gfx.ras->enable_watchdog_timer) 2170 adev->gfx.ras->enable_watchdog_timer(adev); 2171 2172 return 0; 2173 } 2174 2175 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2176 bool enable, int xcc_id) 2177 { 2178 uint32_t def, data; 2179 2180 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2181 return; 2182 2183 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2184 regRLC_CGTT_MGCG_OVERRIDE); 2185 2186 if (enable) 2187 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2188 else 2189 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2190 2191 if (def != data) 2192 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2193 regRLC_CGTT_MGCG_OVERRIDE, data); 2194 2195 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2196 2197 if (enable) 2198 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2199 else 2200 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2201 2202 if (def != data) 2203 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2204 } 2205 2206 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2207 bool enable, int xcc_id) 2208 { 2209 uint32_t def, data; 2210 2211 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2212 return; 2213 2214 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2215 regRLC_CGTT_MGCG_OVERRIDE); 2216 2217 if (enable) 2218 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2219 else 2220 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2221 2222 if (def != data) 2223 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2224 regRLC_CGTT_MGCG_OVERRIDE, data); 2225 } 2226 2227 static void 2228 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2229 bool enable, int xcc_id) 2230 { 2231 uint32_t data, def; 2232 2233 /* It is disabled by HW by default */ 2234 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2235 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2236 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2237 2238 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2239 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2240 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2241 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2242 2243 if (def != data) 2244 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2245 2246 /* MGLS is a global flag to control all MGLS in GFX */ 2247 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2248 /* 2 - RLC memory Light sleep */ 2249 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2250 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2251 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2252 if (def != data) 2253 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2254 } 2255 /* 3 - CP memory Light sleep */ 2256 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2257 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2258 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2259 if (def != data) 2260 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2261 } 2262 } 2263 } else { 2264 /* 1 - MGCG_OVERRIDE */ 2265 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2266 2267 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2268 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2269 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2270 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2271 2272 if (def != data) 2273 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2274 2275 /* 2 - disable MGLS in RLC */ 2276 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2277 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2278 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2279 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2280 } 2281 2282 /* 3 - disable MGLS in CP */ 2283 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2284 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2285 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2286 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2287 } 2288 } 2289 2290 } 2291 2292 static void 2293 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2294 bool enable, int xcc_id) 2295 { 2296 uint32_t def, data; 2297 2298 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2299 2300 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2301 /* unset CGCG override */ 2302 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2303 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2304 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2305 else 2306 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2307 /* update CGCG and CGLS override bits */ 2308 if (def != data) 2309 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2310 2311 /* enable cgcg FSM(0x0000363F) */ 2312 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2313 2314 data = (0x36 2315 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2316 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2317 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2318 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2319 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2320 if (def != data) 2321 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2322 2323 /* set IDLE_POLL_COUNT(0x00900100) */ 2324 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2325 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2326 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2327 if (def != data) 2328 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2329 } else { 2330 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2331 /* reset CGCG/CGLS bits */ 2332 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2333 /* disable cgcg and cgls in FSM */ 2334 if (def != data) 2335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2336 } 2337 2338 } 2339 2340 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2341 bool enable, int xcc_id) 2342 { 2343 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2344 2345 if (enable) { 2346 /* FGCG */ 2347 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2348 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2349 2350 /* CGCG/CGLS should be enabled after MGCG/MGLS 2351 * === MGCG + MGLS === 2352 */ 2353 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2354 xcc_id); 2355 /* === CGCG + CGLS === */ 2356 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2357 xcc_id); 2358 } else { 2359 /* CGCG/CGLS should be disabled before MGCG/MGLS 2360 * === CGCG + CGLS === 2361 */ 2362 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2363 xcc_id); 2364 /* === MGCG + MGLS === */ 2365 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2366 xcc_id); 2367 2368 /* FGCG */ 2369 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2370 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2371 } 2372 2373 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2374 2375 return 0; 2376 } 2377 2378 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2379 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2380 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2381 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2382 .init = gfx_v9_4_3_rlc_init, 2383 .resume = gfx_v9_4_3_rlc_resume, 2384 .stop = gfx_v9_4_3_rlc_stop, 2385 .reset = gfx_v9_4_3_rlc_reset, 2386 .start = gfx_v9_4_3_rlc_start, 2387 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2388 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2389 }; 2390 2391 static int gfx_v9_4_3_set_powergating_state(void *handle, 2392 enum amd_powergating_state state) 2393 { 2394 return 0; 2395 } 2396 2397 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2398 enum amd_clockgating_state state) 2399 { 2400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2401 int i, num_xcc; 2402 2403 if (amdgpu_sriov_vf(adev)) 2404 return 0; 2405 2406 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2407 switch (adev->ip_versions[GC_HWIP][0]) { 2408 case IP_VERSION(9, 4, 3): 2409 for (i = 0; i < num_xcc; i++) 2410 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2411 adev, state == AMD_CG_STATE_GATE, i); 2412 break; 2413 default: 2414 break; 2415 } 2416 return 0; 2417 } 2418 2419 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2420 { 2421 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2422 int data; 2423 2424 if (amdgpu_sriov_vf(adev)) 2425 *flags = 0; 2426 2427 /* AMD_CG_SUPPORT_GFX_MGCG */ 2428 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2429 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2430 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2431 2432 /* AMD_CG_SUPPORT_GFX_CGCG */ 2433 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2434 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2435 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2436 2437 /* AMD_CG_SUPPORT_GFX_CGLS */ 2438 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2439 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2440 2441 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2442 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2443 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2444 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2445 2446 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2447 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2448 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2449 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2450 } 2451 2452 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2453 { 2454 struct amdgpu_device *adev = ring->adev; 2455 u32 ref_and_mask, reg_mem_engine; 2456 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2457 2458 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2459 switch (ring->me) { 2460 case 1: 2461 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2462 break; 2463 case 2: 2464 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2465 break; 2466 default: 2467 return; 2468 } 2469 reg_mem_engine = 0; 2470 } else { 2471 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2472 reg_mem_engine = 1; /* pfp */ 2473 } 2474 2475 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2476 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2477 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2478 ref_and_mask, ref_and_mask, 0x20); 2479 } 2480 2481 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2482 struct amdgpu_job *job, 2483 struct amdgpu_ib *ib, 2484 uint32_t flags) 2485 { 2486 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2487 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2488 2489 /* Currently, there is a high possibility to get wave ID mismatch 2490 * between ME and GDS, leading to a hw deadlock, because ME generates 2491 * different wave IDs than the GDS expects. This situation happens 2492 * randomly when at least 5 compute pipes use GDS ordered append. 2493 * The wave IDs generated by ME are also wrong after suspend/resume. 2494 * Those are probably bugs somewhere else in the kernel driver. 2495 * 2496 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2497 * GDS to 0 for this ring (me/pipe). 2498 */ 2499 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2500 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2501 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2502 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2503 } 2504 2505 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2506 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2507 amdgpu_ring_write(ring, 2508 #ifdef __BIG_ENDIAN 2509 (2 << 0) | 2510 #endif 2511 lower_32_bits(ib->gpu_addr)); 2512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2513 amdgpu_ring_write(ring, control); 2514 } 2515 2516 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2517 u64 seq, unsigned flags) 2518 { 2519 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2520 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2521 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2522 2523 /* RELEASE_MEM - flush caches, send int */ 2524 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2525 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2526 EOP_TC_NC_ACTION_EN) : 2527 (EOP_TCL1_ACTION_EN | 2528 EOP_TC_ACTION_EN | 2529 EOP_TC_WB_ACTION_EN | 2530 EOP_TC_MD_ACTION_EN)) | 2531 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2532 EVENT_INDEX(5))); 2533 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2534 2535 /* 2536 * the address should be Qword aligned if 64bit write, Dword 2537 * aligned if only send 32bit data low (discard data high) 2538 */ 2539 if (write64bit) 2540 BUG_ON(addr & 0x7); 2541 else 2542 BUG_ON(addr & 0x3); 2543 amdgpu_ring_write(ring, lower_32_bits(addr)); 2544 amdgpu_ring_write(ring, upper_32_bits(addr)); 2545 amdgpu_ring_write(ring, lower_32_bits(seq)); 2546 amdgpu_ring_write(ring, upper_32_bits(seq)); 2547 amdgpu_ring_write(ring, 0); 2548 } 2549 2550 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2551 { 2552 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2553 uint32_t seq = ring->fence_drv.sync_seq; 2554 uint64_t addr = ring->fence_drv.gpu_addr; 2555 2556 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2557 lower_32_bits(addr), upper_32_bits(addr), 2558 seq, 0xffffffff, 4); 2559 } 2560 2561 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2562 unsigned vmid, uint64_t pd_addr) 2563 { 2564 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2565 } 2566 2567 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2568 { 2569 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2570 } 2571 2572 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2573 { 2574 u64 wptr; 2575 2576 /* XXX check if swapping is necessary on BE */ 2577 if (ring->use_doorbell) 2578 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2579 else 2580 BUG(); 2581 return wptr; 2582 } 2583 2584 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2585 { 2586 struct amdgpu_device *adev = ring->adev; 2587 2588 /* XXX check if swapping is necessary on BE */ 2589 if (ring->use_doorbell) { 2590 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2591 WDOORBELL64(ring->doorbell_index, ring->wptr); 2592 } else { 2593 BUG(); /* only DOORBELL method supported on gfx9 now */ 2594 } 2595 } 2596 2597 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2598 u64 seq, unsigned int flags) 2599 { 2600 struct amdgpu_device *adev = ring->adev; 2601 2602 /* we only allocate 32bit for each seq wb address */ 2603 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2604 2605 /* write fence seq to the "addr" */ 2606 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2607 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2608 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2609 amdgpu_ring_write(ring, lower_32_bits(addr)); 2610 amdgpu_ring_write(ring, upper_32_bits(addr)); 2611 amdgpu_ring_write(ring, lower_32_bits(seq)); 2612 2613 if (flags & AMDGPU_FENCE_FLAG_INT) { 2614 /* set register to trigger INT */ 2615 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2616 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2617 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2618 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2619 amdgpu_ring_write(ring, 0); 2620 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2621 } 2622 } 2623 2624 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2625 uint32_t reg_val_offs) 2626 { 2627 struct amdgpu_device *adev = ring->adev; 2628 2629 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2630 amdgpu_ring_write(ring, 0 | /* src: register*/ 2631 (5 << 8) | /* dst: memory */ 2632 (1 << 20)); /* write confirm */ 2633 amdgpu_ring_write(ring, reg); 2634 amdgpu_ring_write(ring, 0); 2635 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2636 reg_val_offs * 4)); 2637 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2638 reg_val_offs * 4)); 2639 } 2640 2641 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2642 uint32_t val) 2643 { 2644 uint32_t cmd = 0; 2645 2646 switch (ring->funcs->type) { 2647 case AMDGPU_RING_TYPE_GFX: 2648 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2649 break; 2650 case AMDGPU_RING_TYPE_KIQ: 2651 cmd = (1 << 16); /* no inc addr */ 2652 break; 2653 default: 2654 cmd = WR_CONFIRM; 2655 break; 2656 } 2657 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2658 amdgpu_ring_write(ring, cmd); 2659 amdgpu_ring_write(ring, reg); 2660 amdgpu_ring_write(ring, 0); 2661 amdgpu_ring_write(ring, val); 2662 } 2663 2664 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2665 uint32_t val, uint32_t mask) 2666 { 2667 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2668 } 2669 2670 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2671 uint32_t reg0, uint32_t reg1, 2672 uint32_t ref, uint32_t mask) 2673 { 2674 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2675 ref, mask); 2676 } 2677 2678 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2679 struct amdgpu_device *adev, int me, int pipe, 2680 enum amdgpu_interrupt_state state, int xcc_id) 2681 { 2682 u32 mec_int_cntl, mec_int_cntl_reg; 2683 2684 /* 2685 * amdgpu controls only the first MEC. That's why this function only 2686 * handles the setting of interrupts for this specific MEC. All other 2687 * pipes' interrupts are set by amdkfd. 2688 */ 2689 2690 if (me == 1) { 2691 switch (pipe) { 2692 case 0: 2693 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2694 break; 2695 case 1: 2696 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2697 break; 2698 case 2: 2699 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2700 break; 2701 case 3: 2702 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2703 break; 2704 default: 2705 DRM_DEBUG("invalid pipe %d\n", pipe); 2706 return; 2707 } 2708 } else { 2709 DRM_DEBUG("invalid me %d\n", me); 2710 return; 2711 } 2712 2713 switch (state) { 2714 case AMDGPU_IRQ_STATE_DISABLE: 2715 mec_int_cntl = RREG32(mec_int_cntl_reg); 2716 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2717 TIME_STAMP_INT_ENABLE, 0); 2718 WREG32(mec_int_cntl_reg, mec_int_cntl); 2719 break; 2720 case AMDGPU_IRQ_STATE_ENABLE: 2721 mec_int_cntl = RREG32(mec_int_cntl_reg); 2722 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2723 TIME_STAMP_INT_ENABLE, 1); 2724 WREG32(mec_int_cntl_reg, mec_int_cntl); 2725 break; 2726 default: 2727 break; 2728 } 2729 } 2730 2731 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2732 struct amdgpu_irq_src *source, 2733 unsigned type, 2734 enum amdgpu_interrupt_state state) 2735 { 2736 int i, num_xcc; 2737 2738 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2739 switch (state) { 2740 case AMDGPU_IRQ_STATE_DISABLE: 2741 case AMDGPU_IRQ_STATE_ENABLE: 2742 for (i = 0; i < num_xcc; i++) 2743 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2744 PRIV_REG_INT_ENABLE, 2745 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2746 break; 2747 default: 2748 break; 2749 } 2750 2751 return 0; 2752 } 2753 2754 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2755 struct amdgpu_irq_src *source, 2756 unsigned type, 2757 enum amdgpu_interrupt_state state) 2758 { 2759 int i, num_xcc; 2760 2761 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2762 switch (state) { 2763 case AMDGPU_IRQ_STATE_DISABLE: 2764 case AMDGPU_IRQ_STATE_ENABLE: 2765 for (i = 0; i < num_xcc; i++) 2766 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2767 PRIV_INSTR_INT_ENABLE, 2768 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2769 break; 2770 default: 2771 break; 2772 } 2773 2774 return 0; 2775 } 2776 2777 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2778 struct amdgpu_irq_src *src, 2779 unsigned type, 2780 enum amdgpu_interrupt_state state) 2781 { 2782 int i, num_xcc; 2783 2784 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2785 for (i = 0; i < num_xcc; i++) { 2786 switch (type) { 2787 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2788 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2789 adev, 1, 0, state, i); 2790 break; 2791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2792 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2793 adev, 1, 1, state, i); 2794 break; 2795 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2796 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2797 adev, 1, 2, state, i); 2798 break; 2799 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2800 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2801 adev, 1, 3, state, i); 2802 break; 2803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2804 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2805 adev, 2, 0, state, i); 2806 break; 2807 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2808 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2809 adev, 2, 1, state, i); 2810 break; 2811 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2812 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2813 adev, 2, 2, state, i); 2814 break; 2815 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2816 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2817 adev, 2, 3, state, i); 2818 break; 2819 default: 2820 break; 2821 } 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2828 struct amdgpu_irq_src *source, 2829 struct amdgpu_iv_entry *entry) 2830 { 2831 int i, xcc_id; 2832 u8 me_id, pipe_id, queue_id; 2833 struct amdgpu_ring *ring; 2834 2835 DRM_DEBUG("IH: CP EOP\n"); 2836 me_id = (entry->ring_id & 0x0c) >> 2; 2837 pipe_id = (entry->ring_id & 0x03) >> 0; 2838 queue_id = (entry->ring_id & 0x70) >> 4; 2839 2840 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2841 2842 if (xcc_id == -EINVAL) 2843 return -EINVAL; 2844 2845 switch (me_id) { 2846 case 0: 2847 case 1: 2848 case 2: 2849 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2850 ring = &adev->gfx.compute_ring 2851 [i + 2852 xcc_id * adev->gfx.num_compute_rings]; 2853 /* Per-queue interrupt is supported for MEC starting from VI. 2854 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2855 */ 2856 2857 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2858 amdgpu_fence_process(ring); 2859 } 2860 break; 2861 } 2862 return 0; 2863 } 2864 2865 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2866 struct amdgpu_iv_entry *entry) 2867 { 2868 u8 me_id, pipe_id, queue_id; 2869 struct amdgpu_ring *ring; 2870 int i, xcc_id; 2871 2872 me_id = (entry->ring_id & 0x0c) >> 2; 2873 pipe_id = (entry->ring_id & 0x03) >> 0; 2874 queue_id = (entry->ring_id & 0x70) >> 4; 2875 2876 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2877 2878 if (xcc_id == -EINVAL) 2879 return; 2880 2881 switch (me_id) { 2882 case 0: 2883 case 1: 2884 case 2: 2885 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2886 ring = &adev->gfx.compute_ring 2887 [i + 2888 xcc_id * adev->gfx.num_compute_rings]; 2889 if (ring->me == me_id && ring->pipe == pipe_id && 2890 ring->queue == queue_id) 2891 drm_sched_fault(&ring->sched); 2892 } 2893 break; 2894 } 2895 } 2896 2897 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2898 struct amdgpu_irq_src *source, 2899 struct amdgpu_iv_entry *entry) 2900 { 2901 DRM_ERROR("Illegal register access in command stream\n"); 2902 gfx_v9_4_3_fault(adev, entry); 2903 return 0; 2904 } 2905 2906 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2907 struct amdgpu_irq_src *source, 2908 struct amdgpu_iv_entry *entry) 2909 { 2910 DRM_ERROR("Illegal instruction in command stream\n"); 2911 gfx_v9_4_3_fault(adev, entry); 2912 return 0; 2913 } 2914 2915 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2916 { 2917 const unsigned int cp_coher_cntl = 2918 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2919 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2920 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2921 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2922 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2923 2924 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2925 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2926 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2927 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2928 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2929 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2930 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2931 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2932 } 2933 2934 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2935 uint32_t pipe, bool enable) 2936 { 2937 struct amdgpu_device *adev = ring->adev; 2938 uint32_t val; 2939 uint32_t wcl_cs_reg; 2940 2941 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2942 val = enable ? 0x1 : 0x7f; 2943 2944 switch (pipe) { 2945 case 0: 2946 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2947 break; 2948 case 1: 2949 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2950 break; 2951 case 2: 2952 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2953 break; 2954 case 3: 2955 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2956 break; 2957 default: 2958 DRM_DEBUG("invalid pipe %d\n", pipe); 2959 return; 2960 } 2961 2962 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2963 2964 } 2965 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2966 { 2967 struct amdgpu_device *adev = ring->adev; 2968 uint32_t val; 2969 int i; 2970 2971 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2972 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2973 * around 25% of gpu resources. 2974 */ 2975 val = enable ? 0x1f : 0x07ffffff; 2976 amdgpu_ring_emit_wreg(ring, 2977 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 2978 val); 2979 2980 /* Restrict waves for normal/low priority compute queues as well 2981 * to get best QoS for high priority compute jobs. 2982 * 2983 * amdgpu controls only 1st ME(0-3 CS pipes). 2984 */ 2985 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2986 if (i != ring->pipe) 2987 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 2988 2989 } 2990 } 2991 2992 enum amdgpu_gfx_cp_ras_mem_id { 2993 AMDGPU_GFX_CP_MEM1 = 1, 2994 AMDGPU_GFX_CP_MEM2, 2995 AMDGPU_GFX_CP_MEM3, 2996 AMDGPU_GFX_CP_MEM4, 2997 AMDGPU_GFX_CP_MEM5, 2998 }; 2999 3000 enum amdgpu_gfx_gcea_ras_mem_id { 3001 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3002 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3003 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3004 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3005 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3006 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3007 AMDGPU_GFX_GCEA_MAM_DMEM0, 3008 AMDGPU_GFX_GCEA_MAM_DMEM1, 3009 AMDGPU_GFX_GCEA_MAM_DMEM2, 3010 AMDGPU_GFX_GCEA_MAM_DMEM3, 3011 AMDGPU_GFX_GCEA_MAM_AMEM0, 3012 AMDGPU_GFX_GCEA_MAM_AMEM1, 3013 AMDGPU_GFX_GCEA_MAM_AMEM2, 3014 AMDGPU_GFX_GCEA_MAM_AMEM3, 3015 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3016 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3017 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3018 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3019 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3020 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3021 }; 3022 3023 enum amdgpu_gfx_gc_cane_ras_mem_id { 3024 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3025 }; 3026 3027 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3028 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3029 }; 3030 3031 enum amdgpu_gfx_gds_ras_mem_id { 3032 AMDGPU_GFX_GDS_MEM0 = 0, 3033 }; 3034 3035 enum amdgpu_gfx_lds_ras_mem_id { 3036 AMDGPU_GFX_LDS_BANK0 = 0, 3037 AMDGPU_GFX_LDS_BANK1, 3038 AMDGPU_GFX_LDS_BANK2, 3039 AMDGPU_GFX_LDS_BANK3, 3040 AMDGPU_GFX_LDS_BANK4, 3041 AMDGPU_GFX_LDS_BANK5, 3042 AMDGPU_GFX_LDS_BANK6, 3043 AMDGPU_GFX_LDS_BANK7, 3044 AMDGPU_GFX_LDS_BANK8, 3045 AMDGPU_GFX_LDS_BANK9, 3046 AMDGPU_GFX_LDS_BANK10, 3047 AMDGPU_GFX_LDS_BANK11, 3048 AMDGPU_GFX_LDS_BANK12, 3049 AMDGPU_GFX_LDS_BANK13, 3050 AMDGPU_GFX_LDS_BANK14, 3051 AMDGPU_GFX_LDS_BANK15, 3052 AMDGPU_GFX_LDS_BANK16, 3053 AMDGPU_GFX_LDS_BANK17, 3054 AMDGPU_GFX_LDS_BANK18, 3055 AMDGPU_GFX_LDS_BANK19, 3056 AMDGPU_GFX_LDS_BANK20, 3057 AMDGPU_GFX_LDS_BANK21, 3058 AMDGPU_GFX_LDS_BANK22, 3059 AMDGPU_GFX_LDS_BANK23, 3060 AMDGPU_GFX_LDS_BANK24, 3061 AMDGPU_GFX_LDS_BANK25, 3062 AMDGPU_GFX_LDS_BANK26, 3063 AMDGPU_GFX_LDS_BANK27, 3064 AMDGPU_GFX_LDS_BANK28, 3065 AMDGPU_GFX_LDS_BANK29, 3066 AMDGPU_GFX_LDS_BANK30, 3067 AMDGPU_GFX_LDS_BANK31, 3068 AMDGPU_GFX_LDS_SP_BUFFER_A, 3069 AMDGPU_GFX_LDS_SP_BUFFER_B, 3070 }; 3071 3072 enum amdgpu_gfx_rlc_ras_mem_id { 3073 AMDGPU_GFX_RLC_GPMF32 = 1, 3074 AMDGPU_GFX_RLC_RLCVF32, 3075 AMDGPU_GFX_RLC_SCRATCH, 3076 AMDGPU_GFX_RLC_SRM_ARAM, 3077 AMDGPU_GFX_RLC_SRM_DRAM, 3078 AMDGPU_GFX_RLC_TCTAG, 3079 AMDGPU_GFX_RLC_SPM_SE, 3080 AMDGPU_GFX_RLC_SPM_GRBMT, 3081 }; 3082 3083 enum amdgpu_gfx_sp_ras_mem_id { 3084 AMDGPU_GFX_SP_SIMDID0 = 0, 3085 }; 3086 3087 enum amdgpu_gfx_spi_ras_mem_id { 3088 AMDGPU_GFX_SPI_MEM0 = 0, 3089 AMDGPU_GFX_SPI_MEM1, 3090 AMDGPU_GFX_SPI_MEM2, 3091 AMDGPU_GFX_SPI_MEM3, 3092 }; 3093 3094 enum amdgpu_gfx_sqc_ras_mem_id { 3095 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3096 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3097 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3098 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3099 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3100 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3101 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3102 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3103 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3104 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3105 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3106 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3107 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3108 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3109 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3110 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3111 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3112 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3113 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3114 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3115 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3116 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3117 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3118 }; 3119 3120 enum amdgpu_gfx_sq_ras_mem_id { 3121 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3122 AMDGPU_GFX_SQ_SGPR_MEM1, 3123 AMDGPU_GFX_SQ_SGPR_MEM2, 3124 AMDGPU_GFX_SQ_SGPR_MEM3, 3125 }; 3126 3127 enum amdgpu_gfx_ta_ras_mem_id { 3128 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3129 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3130 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3131 AMDGPU_GFX_TA_FSX_LFIFO, 3132 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3133 }; 3134 3135 enum amdgpu_gfx_tcc_ras_mem_id { 3136 AMDGPU_GFX_TCC_MEM1 = 1, 3137 }; 3138 3139 enum amdgpu_gfx_tca_ras_mem_id { 3140 AMDGPU_GFX_TCA_MEM1 = 1, 3141 }; 3142 3143 enum amdgpu_gfx_tci_ras_mem_id { 3144 AMDGPU_GFX_TCIW_MEM = 1, 3145 }; 3146 3147 enum amdgpu_gfx_tcp_ras_mem_id { 3148 AMDGPU_GFX_TCP_LFIFO0 = 1, 3149 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3150 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3151 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3152 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3153 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3154 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3155 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3156 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3157 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3158 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3159 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3160 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3161 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3162 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3163 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3164 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3165 AMDGPU_GFX_TCP_VM_FIFO, 3166 AMDGPU_GFX_TCP_DB_TAGRAM0, 3167 AMDGPU_GFX_TCP_DB_TAGRAM1, 3168 AMDGPU_GFX_TCP_DB_TAGRAM2, 3169 AMDGPU_GFX_TCP_DB_TAGRAM3, 3170 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3171 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3172 AMDGPU_GFX_TCP_CMD_FIFO, 3173 }; 3174 3175 enum amdgpu_gfx_td_ras_mem_id { 3176 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3177 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3178 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3179 }; 3180 3181 enum amdgpu_gfx_tcx_ras_mem_id { 3182 AMDGPU_GFX_TCX_FIFOD0 = 0, 3183 AMDGPU_GFX_TCX_FIFOD1, 3184 AMDGPU_GFX_TCX_FIFOD2, 3185 AMDGPU_GFX_TCX_FIFOD3, 3186 AMDGPU_GFX_TCX_FIFOD4, 3187 AMDGPU_GFX_TCX_FIFOD5, 3188 AMDGPU_GFX_TCX_FIFOD6, 3189 AMDGPU_GFX_TCX_FIFOD7, 3190 AMDGPU_GFX_TCX_FIFOB0, 3191 AMDGPU_GFX_TCX_FIFOB1, 3192 AMDGPU_GFX_TCX_FIFOB2, 3193 AMDGPU_GFX_TCX_FIFOB3, 3194 AMDGPU_GFX_TCX_FIFOB4, 3195 AMDGPU_GFX_TCX_FIFOB5, 3196 AMDGPU_GFX_TCX_FIFOB6, 3197 AMDGPU_GFX_TCX_FIFOB7, 3198 AMDGPU_GFX_TCX_FIFOA0, 3199 AMDGPU_GFX_TCX_FIFOA1, 3200 AMDGPU_GFX_TCX_FIFOA2, 3201 AMDGPU_GFX_TCX_FIFOA3, 3202 AMDGPU_GFX_TCX_FIFOA4, 3203 AMDGPU_GFX_TCX_FIFOA5, 3204 AMDGPU_GFX_TCX_FIFOA6, 3205 AMDGPU_GFX_TCX_FIFOA7, 3206 AMDGPU_GFX_TCX_CFIFO0, 3207 AMDGPU_GFX_TCX_CFIFO1, 3208 AMDGPU_GFX_TCX_CFIFO2, 3209 AMDGPU_GFX_TCX_CFIFO3, 3210 AMDGPU_GFX_TCX_CFIFO4, 3211 AMDGPU_GFX_TCX_CFIFO5, 3212 AMDGPU_GFX_TCX_CFIFO6, 3213 AMDGPU_GFX_TCX_CFIFO7, 3214 AMDGPU_GFX_TCX_FIFO_ACKB0, 3215 AMDGPU_GFX_TCX_FIFO_ACKB1, 3216 AMDGPU_GFX_TCX_FIFO_ACKB2, 3217 AMDGPU_GFX_TCX_FIFO_ACKB3, 3218 AMDGPU_GFX_TCX_FIFO_ACKB4, 3219 AMDGPU_GFX_TCX_FIFO_ACKB5, 3220 AMDGPU_GFX_TCX_FIFO_ACKB6, 3221 AMDGPU_GFX_TCX_FIFO_ACKB7, 3222 AMDGPU_GFX_TCX_FIFO_ACKD0, 3223 AMDGPU_GFX_TCX_FIFO_ACKD1, 3224 AMDGPU_GFX_TCX_FIFO_ACKD2, 3225 AMDGPU_GFX_TCX_FIFO_ACKD3, 3226 AMDGPU_GFX_TCX_FIFO_ACKD4, 3227 AMDGPU_GFX_TCX_FIFO_ACKD5, 3228 AMDGPU_GFX_TCX_FIFO_ACKD6, 3229 AMDGPU_GFX_TCX_FIFO_ACKD7, 3230 AMDGPU_GFX_TCX_DST_FIFOA0, 3231 AMDGPU_GFX_TCX_DST_FIFOA1, 3232 AMDGPU_GFX_TCX_DST_FIFOA2, 3233 AMDGPU_GFX_TCX_DST_FIFOA3, 3234 AMDGPU_GFX_TCX_DST_FIFOA4, 3235 AMDGPU_GFX_TCX_DST_FIFOA5, 3236 AMDGPU_GFX_TCX_DST_FIFOA6, 3237 AMDGPU_GFX_TCX_DST_FIFOA7, 3238 AMDGPU_GFX_TCX_DST_FIFOB0, 3239 AMDGPU_GFX_TCX_DST_FIFOB1, 3240 AMDGPU_GFX_TCX_DST_FIFOB2, 3241 AMDGPU_GFX_TCX_DST_FIFOB3, 3242 AMDGPU_GFX_TCX_DST_FIFOB4, 3243 AMDGPU_GFX_TCX_DST_FIFOB5, 3244 AMDGPU_GFX_TCX_DST_FIFOB6, 3245 AMDGPU_GFX_TCX_DST_FIFOB7, 3246 AMDGPU_GFX_TCX_DST_FIFOD0, 3247 AMDGPU_GFX_TCX_DST_FIFOD1, 3248 AMDGPU_GFX_TCX_DST_FIFOD2, 3249 AMDGPU_GFX_TCX_DST_FIFOD3, 3250 AMDGPU_GFX_TCX_DST_FIFOD4, 3251 AMDGPU_GFX_TCX_DST_FIFOD5, 3252 AMDGPU_GFX_TCX_DST_FIFOD6, 3253 AMDGPU_GFX_TCX_DST_FIFOD7, 3254 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3255 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3256 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3257 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3258 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3259 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3260 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3261 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3262 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3263 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3264 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3265 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3266 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3267 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3268 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3269 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3270 }; 3271 3272 enum amdgpu_gfx_atc_l2_ras_mem_id { 3273 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3274 }; 3275 3276 enum amdgpu_gfx_utcl2_ras_mem_id { 3277 AMDGPU_GFX_UTCL2_MEM0 = 0, 3278 }; 3279 3280 enum amdgpu_gfx_vml2_ras_mem_id { 3281 AMDGPU_GFX_VML2_MEM0 = 0, 3282 }; 3283 3284 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3285 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3286 }; 3287 3288 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3289 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3290 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3291 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3292 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3293 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3294 }; 3295 3296 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3297 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3298 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3299 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3300 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3301 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3302 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3303 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3304 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3305 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3306 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3307 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3308 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3309 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3310 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3311 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3312 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3313 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3314 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3315 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3316 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3317 }; 3318 3319 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3320 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3321 }; 3322 3323 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3324 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3325 }; 3326 3327 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3328 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3329 }; 3330 3331 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3332 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3333 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3334 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3335 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3336 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3337 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3338 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3339 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3340 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3341 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3342 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3343 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3344 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3345 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3346 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3347 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3348 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3349 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3350 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3351 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3352 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3353 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3354 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3355 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3356 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3357 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3358 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3359 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3360 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3361 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3362 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3363 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3364 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3365 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3366 }; 3367 3368 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3369 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3370 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3371 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3372 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3373 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3374 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3375 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3376 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3377 }; 3378 3379 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3380 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3381 }; 3382 3383 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3384 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3385 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3386 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3387 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3388 }; 3389 3390 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3391 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3392 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3393 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3394 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3395 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3396 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3397 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3398 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3399 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3400 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3401 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3402 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3403 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3404 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3405 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3406 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3407 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3408 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3409 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3410 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3411 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3412 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3413 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3414 }; 3415 3416 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3417 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3418 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3419 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3420 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3421 }; 3422 3423 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3424 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3425 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3426 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3427 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3428 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3429 }; 3430 3431 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3432 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3433 }; 3434 3435 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3436 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3437 }; 3438 3439 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3440 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3441 }; 3442 3443 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3444 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3445 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3446 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3447 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3448 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3449 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3450 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3451 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3452 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3453 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3454 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3455 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3456 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3457 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3458 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3459 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3460 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3461 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3462 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3463 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3464 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3465 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3466 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3467 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3468 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3469 }; 3470 3471 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3472 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3473 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3474 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3475 }; 3476 3477 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3478 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3479 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3480 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3481 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3482 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3483 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3484 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3485 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3486 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3487 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3488 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3489 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3490 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3491 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3492 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3493 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3494 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3495 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3496 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3497 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3498 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3499 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3500 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3501 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3502 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3503 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3504 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3505 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3506 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3507 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3508 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3509 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3510 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3511 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3512 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3513 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3514 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3515 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3516 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3517 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3518 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3519 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3520 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3521 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3522 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3523 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3524 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3525 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3526 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3527 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3528 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3529 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3530 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3531 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3532 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3533 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3534 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3535 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3536 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3537 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3538 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3539 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3540 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3541 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3542 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3543 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3544 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3545 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3546 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3547 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3548 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3549 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3550 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3551 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3552 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3553 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3554 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3555 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3556 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3557 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3558 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3559 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3560 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3561 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3562 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3563 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3564 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3565 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3566 }; 3567 3568 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3569 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3570 }; 3571 3572 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3573 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3574 }; 3575 3576 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3577 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3578 }; 3579 3580 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3581 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3582 }; 3583 3584 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3585 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3586 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3587 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3588 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3589 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3590 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3591 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3592 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3593 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3594 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3595 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3596 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3597 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3598 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3599 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3600 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3601 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3602 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3603 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3604 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3605 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3606 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3607 }; 3608 3609 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3610 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3611 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3612 AMDGPU_GFX_RLC_MEM, 1}, 3613 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3614 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3615 AMDGPU_GFX_CP_MEM, 1}, 3616 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3617 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3618 AMDGPU_GFX_CP_MEM, 1}, 3619 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3620 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3621 AMDGPU_GFX_CP_MEM, 1}, 3622 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3623 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3624 AMDGPU_GFX_GDS_MEM, 1}, 3625 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3626 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3627 AMDGPU_GFX_GC_CANE_MEM, 1}, 3628 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3629 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3630 AMDGPU_GFX_SPI_MEM, 8}, 3631 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3632 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3633 AMDGPU_GFX_SP_MEM, 1}, 3634 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3635 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3636 AMDGPU_GFX_SP_MEM, 1}, 3637 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3638 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3639 AMDGPU_GFX_SQ_MEM, 8}, 3640 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3641 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3642 AMDGPU_GFX_SQC_MEM, 8}, 3643 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3644 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3645 AMDGPU_GFX_TCX_MEM, 1}, 3646 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3647 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3648 AMDGPU_GFX_TCC_MEM, 1}, 3649 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3650 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3651 AMDGPU_GFX_TA_MEM, 8}, 3652 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3653 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3654 AMDGPU_GFX_TCI_MEM, 1}, 3655 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3656 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3657 AMDGPU_GFX_TCP_MEM, 8}, 3658 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3659 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3660 AMDGPU_GFX_TD_MEM, 8}, 3661 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3662 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3663 AMDGPU_GFX_GCEA_MEM, 1}, 3664 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3665 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3666 AMDGPU_GFX_LDS_MEM, 1}, 3667 }; 3668 3669 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3670 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3671 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3672 AMDGPU_GFX_RLC_MEM, 1}, 3673 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3674 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3675 AMDGPU_GFX_CP_MEM, 1}, 3676 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3677 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3678 AMDGPU_GFX_CP_MEM, 1}, 3679 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3680 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3681 AMDGPU_GFX_CP_MEM, 1}, 3682 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3683 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3684 AMDGPU_GFX_GDS_MEM, 1}, 3685 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3686 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3687 AMDGPU_GFX_GC_CANE_MEM, 1}, 3688 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3689 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3690 AMDGPU_GFX_SPI_MEM, 8}, 3691 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3692 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3693 AMDGPU_GFX_SP_MEM, 1}, 3694 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3695 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3696 AMDGPU_GFX_SP_MEM, 1}, 3697 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3698 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3699 AMDGPU_GFX_SQ_MEM, 8}, 3700 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3701 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3702 AMDGPU_GFX_SQC_MEM, 8}, 3703 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3704 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3705 AMDGPU_GFX_TCX_MEM, 1}, 3706 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3707 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3708 AMDGPU_GFX_TCC_MEM, 1}, 3709 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3710 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3711 AMDGPU_GFX_TA_MEM, 8}, 3712 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3713 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3714 AMDGPU_GFX_TCI_MEM, 1}, 3715 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3716 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3717 AMDGPU_GFX_TCP_MEM, 8}, 3718 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3719 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3720 AMDGPU_GFX_TD_MEM, 8}, 3721 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3722 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3723 AMDGPU_GFX_TCA_MEM, 1}, 3724 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3725 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3726 AMDGPU_GFX_GCEA_MEM, 1}, 3727 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3728 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3729 AMDGPU_GFX_LDS_MEM, 1}, 3730 }; 3731 3732 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3733 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3734 }; 3735 3736 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3737 void *ras_error_status, int xcc_id) 3738 { 3739 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3740 unsigned long ce_count = 0, ue_count = 0; 3741 uint32_t i, j, k; 3742 3743 mutex_lock(&adev->grbm_idx_mutex); 3744 3745 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3746 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3747 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3748 /* no need to select if instance number is 1 */ 3749 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3750 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3751 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3752 3753 amdgpu_ras_inst_query_ras_error_count(adev, 3754 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3755 1, 3756 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3757 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3758 GET_INST(GC, xcc_id), 3759 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3760 &ce_count); 3761 3762 amdgpu_ras_inst_query_ras_error_count(adev, 3763 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3764 1, 3765 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3766 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3767 GET_INST(GC, xcc_id), 3768 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3769 &ue_count); 3770 } 3771 } 3772 } 3773 3774 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3775 xcc_id); 3776 mutex_unlock(&adev->grbm_idx_mutex); 3777 3778 /* the caller should make sure initialize value of 3779 * err_data->ue_count and err_data->ce_count 3780 */ 3781 err_data->ce_count += ce_count; 3782 err_data->ue_count += ue_count; 3783 } 3784 3785 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3786 void *ras_error_status, int xcc_id) 3787 { 3788 uint32_t i, j, k; 3789 3790 mutex_lock(&adev->grbm_idx_mutex); 3791 3792 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3793 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3794 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3795 /* no need to select if instance number is 1 */ 3796 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3797 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3798 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3799 3800 amdgpu_ras_inst_reset_ras_error_count(adev, 3801 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3802 1, 3803 GET_INST(GC, xcc_id)); 3804 3805 amdgpu_ras_inst_reset_ras_error_count(adev, 3806 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3807 1, 3808 GET_INST(GC, xcc_id)); 3809 } 3810 } 3811 } 3812 3813 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3814 xcc_id); 3815 mutex_unlock(&adev->grbm_idx_mutex); 3816 } 3817 3818 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3819 int xcc_id) 3820 { 3821 uint32_t i, j; 3822 uint32_t reg_value; 3823 3824 mutex_lock(&adev->grbm_idx_mutex); 3825 3826 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3827 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3828 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3829 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3830 regGCEA_ERR_STATUS); 3831 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3832 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3833 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3834 dev_warn(adev->dev, 3835 "GCEA err detected at instance: %d, status: 0x%x!\n", 3836 j, reg_value); 3837 } 3838 /* clear after read */ 3839 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3840 CLEAR_ERROR_STATUS, 0x1); 3841 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3842 reg_value); 3843 } 3844 } 3845 3846 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3847 xcc_id); 3848 mutex_unlock(&adev->grbm_idx_mutex); 3849 } 3850 3851 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3852 int xcc_id) 3853 { 3854 uint32_t data; 3855 3856 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3857 if (data) { 3858 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3859 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3860 } 3861 3862 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3863 if (data) { 3864 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3865 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3866 } 3867 3868 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3869 regVML2_WALKER_MEM_ECC_STATUS); 3870 if (data) { 3871 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3872 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3873 0x3); 3874 } 3875 } 3876 3877 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3878 uint32_t status, int xcc_id) 3879 { 3880 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3881 uint32_t i, simd, wave; 3882 uint32_t wave_status; 3883 uint32_t wave_pc_lo, wave_pc_hi; 3884 uint32_t wave_exec_lo, wave_exec_hi; 3885 uint32_t wave_inst_dw0, wave_inst_dw1; 3886 uint32_t wave_ib_sts; 3887 3888 for (i = 0; i < 32; i++) { 3889 if (!((i << 1) & status)) 3890 continue; 3891 3892 simd = i / cu_info->max_waves_per_simd; 3893 wave = i % cu_info->max_waves_per_simd; 3894 3895 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3896 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3897 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3898 wave_exec_lo = 3899 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3900 wave_exec_hi = 3901 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3902 wave_inst_dw0 = 3903 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3904 wave_inst_dw1 = 3905 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3906 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3907 3908 dev_info( 3909 adev->dev, 3910 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3911 simd, wave, wave_status, 3912 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3913 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3914 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3915 wave_ib_sts); 3916 } 3917 } 3918 3919 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3920 int xcc_id) 3921 { 3922 uint32_t se_idx, sh_idx, cu_idx; 3923 uint32_t status; 3924 3925 mutex_lock(&adev->grbm_idx_mutex); 3926 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3927 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3928 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3929 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3930 cu_idx, xcc_id); 3931 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3932 regSQ_TIMEOUT_STATUS); 3933 if (status != 0) { 3934 dev_info( 3935 adev->dev, 3936 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3937 se_idx, sh_idx, cu_idx); 3938 gfx_v9_4_3_log_cu_timeout_status( 3939 adev, status, xcc_id); 3940 } 3941 /* clear old status */ 3942 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3943 regSQ_TIMEOUT_STATUS, 0); 3944 } 3945 } 3946 } 3947 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3948 xcc_id); 3949 mutex_unlock(&adev->grbm_idx_mutex); 3950 } 3951 3952 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3953 void *ras_error_status, int xcc_id) 3954 { 3955 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3956 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3957 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3958 } 3959 3960 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3961 int xcc_id) 3962 { 3963 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3964 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3965 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3966 } 3967 3968 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3969 int xcc_id) 3970 { 3971 uint32_t i, j; 3972 uint32_t value; 3973 3974 mutex_lock(&adev->grbm_idx_mutex); 3975 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3976 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3977 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3978 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 3979 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 3980 CLEAR_ERROR_STATUS, 0x1); 3981 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 3982 } 3983 } 3984 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3985 xcc_id); 3986 mutex_unlock(&adev->grbm_idx_mutex); 3987 } 3988 3989 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 3990 int xcc_id) 3991 { 3992 uint32_t se_idx, sh_idx, cu_idx; 3993 3994 mutex_lock(&adev->grbm_idx_mutex); 3995 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3996 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3997 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3998 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3999 cu_idx, xcc_id); 4000 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4001 regSQ_TIMEOUT_STATUS, 0); 4002 } 4003 } 4004 } 4005 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4006 xcc_id); 4007 mutex_unlock(&adev->grbm_idx_mutex); 4008 } 4009 4010 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4011 void *ras_error_status, int xcc_id) 4012 { 4013 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4014 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4015 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4016 } 4017 4018 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4019 void *ras_error_status, int xcc_id) 4020 { 4021 uint32_t i; 4022 uint32_t data; 4023 4024 data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4025 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4026 4027 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4028 (amdgpu_watchdog_timer.period < 1 || 4029 amdgpu_watchdog_timer.period > 0x23)) { 4030 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4031 amdgpu_watchdog_timer.period = 0x23; 4032 } 4033 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4034 amdgpu_watchdog_timer.period); 4035 4036 mutex_lock(&adev->grbm_idx_mutex); 4037 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4038 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4039 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4040 } 4041 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4042 xcc_id); 4043 mutex_unlock(&adev->grbm_idx_mutex); 4044 } 4045 4046 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4047 void *ras_error_status) 4048 { 4049 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4050 gfx_v9_4_3_inst_query_ras_err_count); 4051 } 4052 4053 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4054 { 4055 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4056 } 4057 4058 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4059 { 4060 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4061 } 4062 4063 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4064 { 4065 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4066 } 4067 4068 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4069 { 4070 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4071 } 4072 4073 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4074 .name = "gfx_v9_4_3", 4075 .early_init = gfx_v9_4_3_early_init, 4076 .late_init = gfx_v9_4_3_late_init, 4077 .sw_init = gfx_v9_4_3_sw_init, 4078 .sw_fini = gfx_v9_4_3_sw_fini, 4079 .hw_init = gfx_v9_4_3_hw_init, 4080 .hw_fini = gfx_v9_4_3_hw_fini, 4081 .suspend = gfx_v9_4_3_suspend, 4082 .resume = gfx_v9_4_3_resume, 4083 .is_idle = gfx_v9_4_3_is_idle, 4084 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4085 .soft_reset = gfx_v9_4_3_soft_reset, 4086 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4087 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4088 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4089 }; 4090 4091 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4092 .type = AMDGPU_RING_TYPE_COMPUTE, 4093 .align_mask = 0xff, 4094 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4095 .support_64bit_ptrs = true, 4096 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4097 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4098 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4099 .emit_frame_size = 4100 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4101 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4102 5 + /* hdp invalidate */ 4103 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4104 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4105 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4106 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4107 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4108 7 + /* gfx_v9_4_3_emit_mem_sync */ 4109 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4110 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4111 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4112 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4113 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4114 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4115 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4116 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4117 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4118 .test_ring = gfx_v9_4_3_ring_test_ring, 4119 .test_ib = gfx_v9_4_3_ring_test_ib, 4120 .insert_nop = amdgpu_ring_insert_nop, 4121 .pad_ib = amdgpu_ring_generic_pad_ib, 4122 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4123 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4124 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4125 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4126 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4127 }; 4128 4129 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4130 .type = AMDGPU_RING_TYPE_KIQ, 4131 .align_mask = 0xff, 4132 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4133 .support_64bit_ptrs = true, 4134 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4135 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4136 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4137 .emit_frame_size = 4138 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4139 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4140 5 + /* hdp invalidate */ 4141 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4142 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4143 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4144 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4145 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4146 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4147 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4148 .test_ring = gfx_v9_4_3_ring_test_ring, 4149 .insert_nop = amdgpu_ring_insert_nop, 4150 .pad_ib = amdgpu_ring_generic_pad_ib, 4151 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4152 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4153 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4154 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4155 }; 4156 4157 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4158 { 4159 int i, j, num_xcc; 4160 4161 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4162 for (i = 0; i < num_xcc; i++) { 4163 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4164 4165 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4166 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4167 = &gfx_v9_4_3_ring_funcs_compute; 4168 } 4169 } 4170 4171 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4172 .set = gfx_v9_4_3_set_eop_interrupt_state, 4173 .process = gfx_v9_4_3_eop_irq, 4174 }; 4175 4176 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4177 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4178 .process = gfx_v9_4_3_priv_reg_irq, 4179 }; 4180 4181 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4182 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4183 .process = gfx_v9_4_3_priv_inst_irq, 4184 }; 4185 4186 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4187 { 4188 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4189 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4190 4191 adev->gfx.priv_reg_irq.num_types = 1; 4192 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4193 4194 adev->gfx.priv_inst_irq.num_types = 1; 4195 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4196 } 4197 4198 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4199 { 4200 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4201 } 4202 4203 4204 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4205 { 4206 /* init asci gds info */ 4207 switch (adev->ip_versions[GC_HWIP][0]) { 4208 case IP_VERSION(9, 4, 3): 4209 /* 9.4.3 removed all the GDS internal memory, 4210 * only support GWS opcode in kernel, like barrier 4211 * semaphore.etc */ 4212 adev->gds.gds_size = 0; 4213 break; 4214 default: 4215 adev->gds.gds_size = 0x10000; 4216 break; 4217 } 4218 4219 switch (adev->ip_versions[GC_HWIP][0]) { 4220 case IP_VERSION(9, 4, 3): 4221 /* deprecated for 9.4.3, no usage at all */ 4222 adev->gds.gds_compute_max_wave_id = 0; 4223 break; 4224 default: 4225 /* this really depends on the chip */ 4226 adev->gds.gds_compute_max_wave_id = 0x7ff; 4227 break; 4228 } 4229 4230 adev->gds.gws_size = 64; 4231 adev->gds.oa_size = 16; 4232 } 4233 4234 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4235 u32 bitmap) 4236 { 4237 u32 data; 4238 4239 if (!bitmap) 4240 return; 4241 4242 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4243 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4244 4245 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4246 } 4247 4248 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4249 { 4250 u32 data, mask; 4251 4252 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4253 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4254 4255 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4256 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4257 4258 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4259 4260 return (~data) & mask; 4261 } 4262 4263 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4264 struct amdgpu_cu_info *cu_info) 4265 { 4266 int i, j, k, counter, active_cu_number = 0; 4267 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4268 unsigned disable_masks[4 * 4]; 4269 4270 if (!adev || !cu_info) 4271 return -EINVAL; 4272 4273 /* 4274 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4275 */ 4276 if (adev->gfx.config.max_shader_engines * 4277 adev->gfx.config.max_sh_per_se > 16) 4278 return -EINVAL; 4279 4280 amdgpu_gfx_parse_disable_cu(disable_masks, 4281 adev->gfx.config.max_shader_engines, 4282 adev->gfx.config.max_sh_per_se); 4283 4284 mutex_lock(&adev->grbm_idx_mutex); 4285 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4286 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4287 mask = 1; 4288 ao_bitmap = 0; 4289 counter = 0; 4290 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4291 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4292 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4293 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4294 4295 /* 4296 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4297 * 4x4 size array, and it's usually suitable for Vega 4298 * ASICs which has 4*2 SE/SH layout. 4299 * But for Arcturus, SE/SH layout is changed to 8*1. 4300 * To mostly reduce the impact, we make it compatible 4301 * with current bitmap array as below: 4302 * SE4,SH0 --> bitmap[0][1] 4303 * SE5,SH0 --> bitmap[1][1] 4304 * SE6,SH0 --> bitmap[2][1] 4305 * SE7,SH0 --> bitmap[3][1] 4306 */ 4307 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4308 4309 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4310 if (bitmap & mask) { 4311 if (counter < adev->gfx.config.max_cu_per_sh) 4312 ao_bitmap |= mask; 4313 counter++; 4314 } 4315 mask <<= 1; 4316 } 4317 active_cu_number += counter; 4318 if (i < 2 && j < 2) 4319 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4320 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4321 } 4322 } 4323 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4324 0); 4325 mutex_unlock(&adev->grbm_idx_mutex); 4326 4327 cu_info->number = active_cu_number; 4328 cu_info->ao_cu_mask = ao_cu_mask; 4329 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4330 4331 return 0; 4332 } 4333 4334 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4335 .type = AMD_IP_BLOCK_TYPE_GFX, 4336 .major = 9, 4337 .minor = 4, 4338 .rev = 0, 4339 .funcs = &gfx_v9_4_3_ip_funcs, 4340 }; 4341 4342 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4343 { 4344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4345 uint32_t tmp_mask; 4346 int i, r; 4347 4348 /* TODO : Initialize golden regs */ 4349 /* gfx_v9_4_3_init_golden_registers(adev); */ 4350 4351 tmp_mask = inst_mask; 4352 for_each_inst(i, tmp_mask) 4353 gfx_v9_4_3_xcc_constants_init(adev, i); 4354 4355 if (!amdgpu_sriov_vf(adev)) { 4356 tmp_mask = inst_mask; 4357 for_each_inst(i, tmp_mask) { 4358 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4359 if (r) 4360 return r; 4361 } 4362 } 4363 4364 tmp_mask = inst_mask; 4365 for_each_inst(i, tmp_mask) { 4366 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4367 if (r) 4368 return r; 4369 } 4370 4371 return 0; 4372 } 4373 4374 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4375 { 4376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4377 int i; 4378 4379 for_each_inst(i, inst_mask) 4380 gfx_v9_4_3_xcc_fini(adev, i); 4381 4382 return 0; 4383 } 4384 4385 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4386 .suspend = &gfx_v9_4_3_xcp_suspend, 4387 .resume = &gfx_v9_4_3_xcp_resume 4388 }; 4389 4390 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4391 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4392 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4393 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4394 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4395 }; 4396 4397 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4398 .ras_block = { 4399 .hw_ops = &gfx_v9_4_3_ras_ops, 4400 }, 4401 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4402 }; 4403