1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 50 51 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 52 53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 58 struct amdgpu_cu_info *cu_info); 59 60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 61 uint64_t queue_mask) 62 { 63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 64 amdgpu_ring_write(kiq_ring, 65 PACKET3_SET_RESOURCES_VMID_MASK(0) | 66 /* vmid_mask:0* queue_type:0 (KIQ) */ 67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 68 amdgpu_ring_write(kiq_ring, 69 lower_32_bits(queue_mask)); /* queue mask lo */ 70 amdgpu_ring_write(kiq_ring, 71 upper_32_bits(queue_mask)); /* queue mask hi */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 76 } 77 78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 79 struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = kiq_ring->adev; 82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 85 86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 94 /*queue_type: normal compute queue */ 95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 96 /* alloc format: all_on_one_pipe */ 97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 99 /* num_queues: must be 1 */ 100 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 101 amdgpu_ring_write(kiq_ring, 102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 107 } 108 109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 110 struct amdgpu_ring *ring, 111 enum amdgpu_unmap_queues_action action, 112 u64 gpu_addr, u64 seq) 113 { 114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 115 116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 118 PACKET3_UNMAP_QUEUES_ACTION(action) | 119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 122 amdgpu_ring_write(kiq_ring, 123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 124 125 if (action == PREEMPT_QUEUES_NO_UNMAP) { 126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 128 amdgpu_ring_write(kiq_ring, seq); 129 } else { 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 amdgpu_ring_write(kiq_ring, 0); 133 } 134 } 135 136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 137 struct amdgpu_ring *ring, 138 u64 addr, 139 u64 seq) 140 { 141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 142 143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 144 amdgpu_ring_write(kiq_ring, 145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 147 PACKET3_QUERY_STATUS_COMMAND(2)); 148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 149 amdgpu_ring_write(kiq_ring, 150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 156 } 157 158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 159 uint16_t pasid, uint32_t flush_type, 160 bool all_hub) 161 { 162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 163 amdgpu_ring_write(kiq_ring, 164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 166 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 168 } 169 170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 174 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 176 .set_resources_size = 8, 177 .map_queues_size = 7, 178 .unmap_queues_size = 6, 179 .query_status_size = 7, 180 .invalidate_tlbs_size = 2, 181 }; 182 183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 184 { 185 int i, num_xcc; 186 187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 188 for (i = 0; i < num_xcc; i++) 189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 190 } 191 192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 193 { 194 int i, num_xcc, dev_inst; 195 196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 197 for (i = 0; i < num_xcc; i++) { 198 dev_inst = GET_INST(GC, i); 199 200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 201 GOLDEN_GB_ADDR_CONFIG); 202 /* Golden settings applied by driver for ASIC with rev_id 0 */ 203 if (adev->rev_id == 0) { 204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 205 REDUCE_FIFO_DEPTH_BY_2, 2); 206 } 207 } 208 } 209 210 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 211 bool wc, uint32_t reg, uint32_t val) 212 { 213 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 214 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 215 WRITE_DATA_DST_SEL(0) | 216 (wc ? WR_CONFIRM : 0)); 217 amdgpu_ring_write(ring, reg); 218 amdgpu_ring_write(ring, 0); 219 amdgpu_ring_write(ring, val); 220 } 221 222 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 223 int mem_space, int opt, uint32_t addr0, 224 uint32_t addr1, uint32_t ref, uint32_t mask, 225 uint32_t inv) 226 { 227 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 228 amdgpu_ring_write(ring, 229 /* memory (1) or register (0) */ 230 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 231 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 232 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 233 WAIT_REG_MEM_ENGINE(eng_sel))); 234 235 if (mem_space) 236 BUG_ON(addr0 & 0x3); /* Dword align */ 237 amdgpu_ring_write(ring, addr0); 238 amdgpu_ring_write(ring, addr1); 239 amdgpu_ring_write(ring, ref); 240 amdgpu_ring_write(ring, mask); 241 amdgpu_ring_write(ring, inv); /* poll interval */ 242 } 243 244 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 245 { 246 uint32_t scratch_reg0_offset, xcc_offset; 247 struct amdgpu_device *adev = ring->adev; 248 uint32_t tmp = 0; 249 unsigned i; 250 int r; 251 252 /* Use register offset which is local to XCC in the packet */ 253 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 254 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 255 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 256 257 r = amdgpu_ring_alloc(ring, 3); 258 if (r) 259 return r; 260 261 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 262 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 263 amdgpu_ring_write(ring, 0xDEADBEEF); 264 amdgpu_ring_commit(ring); 265 266 for (i = 0; i < adev->usec_timeout; i++) { 267 tmp = RREG32(scratch_reg0_offset); 268 if (tmp == 0xDEADBEEF) 269 break; 270 udelay(1); 271 } 272 273 if (i >= adev->usec_timeout) 274 r = -ETIMEDOUT; 275 return r; 276 } 277 278 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 279 { 280 struct amdgpu_device *adev = ring->adev; 281 struct amdgpu_ib ib; 282 struct dma_fence *f = NULL; 283 284 unsigned index; 285 uint64_t gpu_addr; 286 uint32_t tmp; 287 long r; 288 289 r = amdgpu_device_wb_get(adev, &index); 290 if (r) 291 return r; 292 293 gpu_addr = adev->wb.gpu_addr + (index * 4); 294 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 295 memset(&ib, 0, sizeof(ib)); 296 r = amdgpu_ib_get(adev, NULL, 16, 297 AMDGPU_IB_POOL_DIRECT, &ib); 298 if (r) 299 goto err1; 300 301 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 302 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 303 ib.ptr[2] = lower_32_bits(gpu_addr); 304 ib.ptr[3] = upper_32_bits(gpu_addr); 305 ib.ptr[4] = 0xDEADBEEF; 306 ib.length_dw = 5; 307 308 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 309 if (r) 310 goto err2; 311 312 r = dma_fence_wait_timeout(f, false, timeout); 313 if (r == 0) { 314 r = -ETIMEDOUT; 315 goto err2; 316 } else if (r < 0) { 317 goto err2; 318 } 319 320 tmp = adev->wb.wb[index]; 321 if (tmp == 0xDEADBEEF) 322 r = 0; 323 else 324 r = -EINVAL; 325 326 err2: 327 amdgpu_ib_free(adev, &ib, NULL); 328 dma_fence_put(f); 329 err1: 330 amdgpu_device_wb_free(adev, index); 331 return r; 332 } 333 334 335 /* This value might differs per partition */ 336 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 337 { 338 uint64_t clock; 339 340 amdgpu_gfx_off_ctrl(adev, false); 341 mutex_lock(&adev->gfx.gpu_clock_mutex); 342 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 343 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 344 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 345 mutex_unlock(&adev->gfx.gpu_clock_mutex); 346 amdgpu_gfx_off_ctrl(adev, true); 347 348 return clock; 349 } 350 351 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 352 { 353 amdgpu_ucode_release(&adev->gfx.pfp_fw); 354 amdgpu_ucode_release(&adev->gfx.me_fw); 355 amdgpu_ucode_release(&adev->gfx.ce_fw); 356 amdgpu_ucode_release(&adev->gfx.rlc_fw); 357 amdgpu_ucode_release(&adev->gfx.mec_fw); 358 amdgpu_ucode_release(&adev->gfx.mec2_fw); 359 360 kfree(adev->gfx.rlc.register_list_format); 361 } 362 363 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 364 const char *chip_name) 365 { 366 char fw_name[30]; 367 int err; 368 const struct rlc_firmware_header_v2_0 *rlc_hdr; 369 uint16_t version_major; 370 uint16_t version_minor; 371 372 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 373 374 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 375 if (err) 376 goto out; 377 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 378 379 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 380 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 381 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 382 out: 383 if (err) 384 amdgpu_ucode_release(&adev->gfx.rlc_fw); 385 386 return err; 387 } 388 389 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 390 { 391 return true; 392 } 393 394 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 395 { 396 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 397 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 398 } 399 400 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 401 const char *chip_name) 402 { 403 char fw_name[30]; 404 int err; 405 406 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 407 408 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 409 if (err) 410 goto out; 411 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 412 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 413 414 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 415 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 416 417 gfx_v9_4_3_check_if_need_gfxoff(adev); 418 419 out: 420 if (err) 421 amdgpu_ucode_release(&adev->gfx.mec_fw); 422 return err; 423 } 424 425 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 426 { 427 const char *chip_name; 428 int r; 429 430 chip_name = "gc_9_4_3"; 431 432 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 433 if (r) 434 return r; 435 436 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 437 if (r) 438 return r; 439 440 return r; 441 } 442 443 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 444 { 445 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 446 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 447 } 448 449 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 450 { 451 int r, i, num_xcc; 452 u32 *hpd; 453 const __le32 *fw_data; 454 unsigned fw_size; 455 u32 *fw; 456 size_t mec_hpd_size; 457 458 const struct gfx_firmware_header_v1_0 *mec_hdr; 459 460 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 461 for (i = 0; i < num_xcc; i++) 462 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 463 AMDGPU_MAX_COMPUTE_QUEUES); 464 465 /* take ownership of the relevant compute queues */ 466 amdgpu_gfx_compute_queue_acquire(adev); 467 mec_hpd_size = 468 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 469 if (mec_hpd_size) { 470 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 471 AMDGPU_GEM_DOMAIN_VRAM | 472 AMDGPU_GEM_DOMAIN_GTT, 473 &adev->gfx.mec.hpd_eop_obj, 474 &adev->gfx.mec.hpd_eop_gpu_addr, 475 (void **)&hpd); 476 if (r) { 477 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 478 gfx_v9_4_3_mec_fini(adev); 479 return r; 480 } 481 482 if (amdgpu_emu_mode == 1) { 483 for (i = 0; i < mec_hpd_size / 4; i++) { 484 memset((void *)(hpd + i), 0, 4); 485 if (i % 50 == 0) 486 msleep(1); 487 } 488 } else { 489 memset(hpd, 0, mec_hpd_size); 490 } 491 492 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 493 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 494 } 495 496 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 497 498 fw_data = (const __le32 *) 499 (adev->gfx.mec_fw->data + 500 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 501 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 502 503 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 505 &adev->gfx.mec.mec_fw_obj, 506 &adev->gfx.mec.mec_fw_gpu_addr, 507 (void **)&fw); 508 if (r) { 509 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 510 gfx_v9_4_3_mec_fini(adev); 511 return r; 512 } 513 514 memcpy(fw, fw_data, fw_size); 515 516 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 517 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 518 519 return 0; 520 } 521 522 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 523 u32 sh_num, u32 instance, int xcc_id) 524 { 525 u32 data; 526 527 if (instance == 0xffffffff) 528 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 529 INSTANCE_BROADCAST_WRITES, 1); 530 else 531 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 532 INSTANCE_INDEX, instance); 533 534 if (se_num == 0xffffffff) 535 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 536 SE_BROADCAST_WRITES, 1); 537 else 538 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 539 540 if (sh_num == 0xffffffff) 541 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 542 SH_BROADCAST_WRITES, 1); 543 else 544 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 545 546 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 547 } 548 549 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 550 { 551 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 552 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 553 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 554 (address << SQ_IND_INDEX__INDEX__SHIFT) | 555 (SQ_IND_INDEX__FORCE_READ_MASK)); 556 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 557 } 558 559 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 560 uint32_t wave, uint32_t thread, 561 uint32_t regno, uint32_t num, uint32_t *out) 562 { 563 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 564 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 565 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 566 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 567 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 568 (SQ_IND_INDEX__FORCE_READ_MASK) | 569 (SQ_IND_INDEX__AUTO_INCR_MASK)); 570 while (num--) 571 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 572 } 573 574 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 575 uint32_t xcc_id, uint32_t simd, uint32_t wave, 576 uint32_t *dst, int *no_fields) 577 { 578 /* type 1 wave data */ 579 dst[(*no_fields)++] = 1; 580 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 595 } 596 597 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 598 uint32_t wave, uint32_t start, 599 uint32_t size, uint32_t *dst) 600 { 601 wave_read_regs(adev, xcc_id, simd, wave, 0, 602 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 603 } 604 605 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 606 uint32_t wave, uint32_t thread, 607 uint32_t start, uint32_t size, 608 uint32_t *dst) 609 { 610 wave_read_regs(adev, xcc_id, simd, wave, thread, 611 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 612 } 613 614 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 615 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 616 { 617 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 618 } 619 620 621 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 622 int num_xccs_per_xcp) 623 { 624 int ret, i, num_xcc; 625 u32 tmp = 0, regval; 626 627 if (adev->psp.funcs) { 628 ret = psp_spatial_partition(&adev->psp, 629 NUM_XCC(adev->gfx.xcc_mask) / 630 num_xccs_per_xcp); 631 if (ret) 632 return ret; 633 } 634 635 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 636 637 for (i = 0; i < num_xcc; i++) { 638 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 639 num_xccs_per_xcp); 640 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 641 i % num_xccs_per_xcp); 642 regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL); 643 if (regval != tmp) 644 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 645 tmp); 646 } 647 648 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 649 650 return 0; 651 } 652 653 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 654 { 655 int xcc; 656 657 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 658 if (!xcc) { 659 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 660 return -EINVAL; 661 } 662 663 return xcc - 1; 664 } 665 666 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 667 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 668 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 669 .read_wave_data = &gfx_v9_4_3_read_wave_data, 670 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 671 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 672 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 673 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 674 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 675 }; 676 677 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 678 { 679 u32 gb_addr_config; 680 681 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 682 adev->gfx.ras = &gfx_v9_4_3_ras; 683 684 switch (adev->ip_versions[GC_HWIP][0]) { 685 case IP_VERSION(9, 4, 3): 686 adev->gfx.config.max_hw_contexts = 8; 687 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 688 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 689 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 690 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 691 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 692 break; 693 default: 694 BUG(); 695 break; 696 } 697 698 adev->gfx.config.gb_addr_config = gb_addr_config; 699 700 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 701 REG_GET_FIELD( 702 adev->gfx.config.gb_addr_config, 703 GB_ADDR_CONFIG, 704 NUM_PIPES); 705 706 adev->gfx.config.max_tile_pipes = 707 adev->gfx.config.gb_addr_config_fields.num_pipes; 708 709 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 710 REG_GET_FIELD( 711 adev->gfx.config.gb_addr_config, 712 GB_ADDR_CONFIG, 713 NUM_BANKS); 714 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 715 REG_GET_FIELD( 716 adev->gfx.config.gb_addr_config, 717 GB_ADDR_CONFIG, 718 MAX_COMPRESSED_FRAGS); 719 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 720 REG_GET_FIELD( 721 adev->gfx.config.gb_addr_config, 722 GB_ADDR_CONFIG, 723 NUM_RB_PER_SE); 724 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 725 REG_GET_FIELD( 726 adev->gfx.config.gb_addr_config, 727 GB_ADDR_CONFIG, 728 NUM_SHADER_ENGINES); 729 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 730 REG_GET_FIELD( 731 adev->gfx.config.gb_addr_config, 732 GB_ADDR_CONFIG, 733 PIPE_INTERLEAVE_SIZE)); 734 735 return 0; 736 } 737 738 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 739 int xcc_id, int mec, int pipe, int queue) 740 { 741 unsigned irq_type; 742 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 743 unsigned int hw_prio; 744 uint32_t xcc_doorbell_start; 745 746 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 747 ring_id]; 748 749 /* mec0 is me1 */ 750 ring->xcc_id = xcc_id; 751 ring->me = mec + 1; 752 ring->pipe = pipe; 753 ring->queue = queue; 754 755 ring->ring_obj = NULL; 756 ring->use_doorbell = true; 757 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 758 xcc_id * adev->doorbell_index.xcc_doorbell_range; 759 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 760 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 761 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 762 GFX9_MEC_HPD_SIZE; 763 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 764 sprintf(ring->name, "comp_%d.%d.%d.%d", 765 ring->xcc_id, ring->me, ring->pipe, ring->queue); 766 767 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 768 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 769 + ring->pipe; 770 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 771 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 772 /* type-2 packets are deprecated on MEC, use type-3 instead */ 773 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 774 hw_prio, NULL); 775 } 776 777 static int gfx_v9_4_3_sw_init(void *handle) 778 { 779 int i, j, k, r, ring_id, xcc_id, num_xcc; 780 struct amdgpu_kiq *kiq; 781 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 782 783 adev->gfx.mec.num_mec = 2; 784 adev->gfx.mec.num_pipe_per_mec = 4; 785 adev->gfx.mec.num_queue_per_pipe = 8; 786 787 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 788 789 /* EOP Event */ 790 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 791 if (r) 792 return r; 793 794 /* Privileged reg */ 795 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 796 &adev->gfx.priv_reg_irq); 797 if (r) 798 return r; 799 800 /* Privileged inst */ 801 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 802 &adev->gfx.priv_inst_irq); 803 if (r) 804 return r; 805 806 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 807 808 r = adev->gfx.rlc.funcs->init(adev); 809 if (r) { 810 DRM_ERROR("Failed to init rlc BOs!\n"); 811 return r; 812 } 813 814 r = gfx_v9_4_3_mec_init(adev); 815 if (r) { 816 DRM_ERROR("Failed to init MEC BOs!\n"); 817 return r; 818 } 819 820 /* set up the compute queues - allocate horizontally across pipes */ 821 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 822 ring_id = 0; 823 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 824 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 825 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 826 k++) { 827 if (!amdgpu_gfx_is_mec_queue_enabled( 828 adev, xcc_id, i, k, j)) 829 continue; 830 831 r = gfx_v9_4_3_compute_ring_init(adev, 832 ring_id, 833 xcc_id, 834 i, k, j); 835 if (r) 836 return r; 837 838 ring_id++; 839 } 840 } 841 } 842 843 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 844 if (r) { 845 DRM_ERROR("Failed to init KIQ BOs!\n"); 846 return r; 847 } 848 849 kiq = &adev->gfx.kiq[xcc_id]; 850 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 851 if (r) 852 return r; 853 854 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 855 r = amdgpu_gfx_mqd_sw_init(adev, 856 sizeof(struct v9_mqd_allocation), xcc_id); 857 if (r) 858 return r; 859 } 860 861 r = gfx_v9_4_3_gpu_early_init(adev); 862 if (r) 863 return r; 864 865 r = amdgpu_gfx_sysfs_init(adev); 866 if (r) 867 return r; 868 869 return amdgpu_gfx_ras_sw_init(adev); 870 } 871 872 static int gfx_v9_4_3_sw_fini(void *handle) 873 { 874 int i, num_xcc; 875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 876 877 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 878 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 879 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 880 881 for (i = 0; i < num_xcc; i++) { 882 amdgpu_gfx_mqd_sw_fini(adev, i); 883 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 884 amdgpu_gfx_kiq_fini(adev, i); 885 } 886 887 gfx_v9_4_3_mec_fini(adev); 888 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 889 gfx_v9_4_3_free_microcode(adev); 890 amdgpu_gfx_sysfs_fini(adev); 891 892 return 0; 893 } 894 895 #define DEFAULT_SH_MEM_BASES (0x6000) 896 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 897 int xcc_id) 898 { 899 int i; 900 uint32_t sh_mem_config; 901 uint32_t sh_mem_bases; 902 uint32_t data; 903 904 /* 905 * Configure apertures: 906 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 907 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 908 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 909 */ 910 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 911 912 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 913 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 914 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 915 916 mutex_lock(&adev->srbm_mutex); 917 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 918 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 919 /* CP and shaders */ 920 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 921 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 922 923 /* Enable trap for each kfd vmid. */ 924 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 925 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 927 } 928 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 929 mutex_unlock(&adev->srbm_mutex); 930 931 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 932 acccess. These should be enabled by FW for target VMIDs. */ 933 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 934 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 935 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 936 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 937 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 938 } 939 } 940 941 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 942 { 943 int vmid; 944 945 /* 946 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 947 * access. Compute VMIDs should be enabled by FW for target VMIDs, 948 * the driver can enable them for graphics. VMID0 should maintain 949 * access so that HWS firmware can save/restore entries. 950 */ 951 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 952 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 953 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 954 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 955 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 956 } 957 } 958 959 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 960 int xcc_id) 961 { 962 u32 tmp; 963 int i; 964 965 /* XXX SH_MEM regs */ 966 /* where to put LDS, scratch, GPUVM in FSA64 space */ 967 mutex_lock(&adev->srbm_mutex); 968 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 969 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 970 /* CP and shaders */ 971 if (i == 0) { 972 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 973 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 974 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 975 !!adev->gmc.noretry); 976 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 977 regSH_MEM_CONFIG, tmp); 978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 979 regSH_MEM_BASES, 0); 980 } else { 981 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 982 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 983 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 984 !!adev->gmc.noretry); 985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 986 regSH_MEM_CONFIG, tmp); 987 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 988 (adev->gmc.private_aperture_start >> 989 48)); 990 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 991 (adev->gmc.shared_aperture_start >> 992 48)); 993 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 994 regSH_MEM_BASES, tmp); 995 } 996 } 997 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 998 999 mutex_unlock(&adev->srbm_mutex); 1000 1001 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1002 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1003 } 1004 1005 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1006 { 1007 int i, num_xcc; 1008 1009 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1010 1011 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1012 adev->gfx.config.db_debug2 = 1013 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1014 1015 for (i = 0; i < num_xcc; i++) 1016 gfx_v9_4_3_xcc_constants_init(adev, i); 1017 } 1018 1019 static void 1020 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1021 int xcc_id) 1022 { 1023 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1024 } 1025 1026 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1027 { 1028 /* 1029 * Rlc save restore list is workable since v2_1. 1030 * And it's needed by gfxoff feature. 1031 */ 1032 if (adev->gfx.rlc.is_rlc_v2_1) 1033 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1034 } 1035 1036 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1037 { 1038 uint32_t data; 1039 1040 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1041 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1042 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1043 } 1044 1045 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1046 { 1047 uint32_t rlc_setting; 1048 1049 /* if RLC is not enabled, do nothing */ 1050 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1051 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1052 return false; 1053 1054 return true; 1055 } 1056 1057 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1058 { 1059 uint32_t data; 1060 unsigned i; 1061 1062 data = RLC_SAFE_MODE__CMD_MASK; 1063 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1064 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1065 1066 /* wait for RLC_SAFE_MODE */ 1067 for (i = 0; i < adev->usec_timeout; i++) { 1068 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1069 break; 1070 udelay(1); 1071 } 1072 } 1073 1074 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1075 int xcc_id) 1076 { 1077 uint32_t data; 1078 1079 data = RLC_SAFE_MODE__CMD_MASK; 1080 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1081 } 1082 1083 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1084 { 1085 int xcc_id, num_xcc; 1086 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1087 1088 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1089 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1090 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1091 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1092 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1093 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1094 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1095 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1096 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1097 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1098 } 1099 } 1100 1101 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1102 { 1103 /* init spm vmid with 0xf */ 1104 if (adev->gfx.rlc.funcs->update_spm_vmid) 1105 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1106 1107 return 0; 1108 } 1109 1110 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1111 int xcc_id) 1112 { 1113 u32 i, j, k; 1114 u32 mask; 1115 1116 mutex_lock(&adev->grbm_idx_mutex); 1117 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1118 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1119 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1120 xcc_id); 1121 for (k = 0; k < adev->usec_timeout; k++) { 1122 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1123 break; 1124 udelay(1); 1125 } 1126 if (k == adev->usec_timeout) { 1127 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1128 0xffffffff, 1129 0xffffffff, xcc_id); 1130 mutex_unlock(&adev->grbm_idx_mutex); 1131 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1132 i, j); 1133 return; 1134 } 1135 } 1136 } 1137 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1138 xcc_id); 1139 mutex_unlock(&adev->grbm_idx_mutex); 1140 1141 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1142 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1143 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1144 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1145 for (k = 0; k < adev->usec_timeout; k++) { 1146 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1147 break; 1148 udelay(1); 1149 } 1150 } 1151 1152 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1153 bool enable, int xcc_id) 1154 { 1155 u32 tmp; 1156 1157 /* These interrupts should be enabled to drive DS clock */ 1158 1159 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1160 1161 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1162 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1163 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1164 1165 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1166 } 1167 1168 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1169 { 1170 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1171 RLC_ENABLE_F32, 0); 1172 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1173 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1174 } 1175 1176 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1177 { 1178 int i, num_xcc; 1179 1180 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1181 for (i = 0; i < num_xcc; i++) 1182 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1183 } 1184 1185 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1186 { 1187 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1188 SOFT_RESET_RLC, 1); 1189 udelay(50); 1190 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1191 SOFT_RESET_RLC, 0); 1192 udelay(50); 1193 } 1194 1195 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1196 { 1197 int i, num_xcc; 1198 1199 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1200 for (i = 0; i < num_xcc; i++) 1201 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1202 } 1203 1204 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1205 { 1206 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1207 RLC_ENABLE_F32, 1); 1208 udelay(50); 1209 1210 /* carrizo do enable cp interrupt after cp inited */ 1211 if (!(adev->flags & AMD_IS_APU)) { 1212 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1213 udelay(50); 1214 } 1215 } 1216 1217 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1218 { 1219 #ifdef AMDGPU_RLC_DEBUG_RETRY 1220 u32 rlc_ucode_ver; 1221 #endif 1222 int i, num_xcc; 1223 1224 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1225 for (i = 0; i < num_xcc; i++) { 1226 gfx_v9_4_3_xcc_rlc_start(adev, i); 1227 #ifdef AMDGPU_RLC_DEBUG_RETRY 1228 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1229 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1230 if (rlc_ucode_ver == 0x108) { 1231 dev_info(adev->dev, 1232 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1233 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1234 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1235 * default is 0x9C4 to create a 100us interval */ 1236 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1237 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1238 * to disable the page fault retry interrupts, default is 1239 * 0x100 (256) */ 1240 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1241 } 1242 #endif 1243 } 1244 } 1245 1246 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1247 int xcc_id) 1248 { 1249 const struct rlc_firmware_header_v2_0 *hdr; 1250 const __le32 *fw_data; 1251 unsigned i, fw_size; 1252 1253 if (!adev->gfx.rlc_fw) 1254 return -EINVAL; 1255 1256 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1257 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1258 1259 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1260 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1261 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1262 1263 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1264 RLCG_UCODE_LOADING_START_ADDRESS); 1265 for (i = 0; i < fw_size; i++) { 1266 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1267 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1268 msleep(1); 1269 } 1270 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1271 } 1272 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1273 1274 return 0; 1275 } 1276 1277 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1278 { 1279 int r; 1280 1281 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1282 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1283 /* legacy rlc firmware loading */ 1284 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1285 if (r) 1286 return r; 1287 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1288 } 1289 1290 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1291 /* disable CG */ 1292 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1293 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1294 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1295 1296 return 0; 1297 } 1298 1299 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1300 { 1301 int r, i, num_xcc; 1302 1303 if (amdgpu_sriov_vf(adev)) 1304 return 0; 1305 1306 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1307 for (i = 0; i < num_xcc; i++) { 1308 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1309 if (r) 1310 return r; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1317 unsigned vmid) 1318 { 1319 u32 reg, data; 1320 1321 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1322 if (amdgpu_sriov_is_pp_one_vf(adev)) 1323 data = RREG32_NO_KIQ(reg); 1324 else 1325 data = RREG32(reg); 1326 1327 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1328 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1329 1330 if (amdgpu_sriov_is_pp_one_vf(adev)) 1331 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1332 else 1333 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1334 } 1335 1336 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1337 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1338 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1339 }; 1340 1341 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1342 uint32_t offset, 1343 struct soc15_reg_rlcg *entries, int arr_size) 1344 { 1345 int i, inst; 1346 uint32_t reg; 1347 1348 if (!entries) 1349 return false; 1350 1351 for (i = 0; i < arr_size; i++) { 1352 const struct soc15_reg_rlcg *entry; 1353 1354 entry = &entries[i]; 1355 inst = adev->ip_map.logical_to_dev_inst ? 1356 adev->ip_map.logical_to_dev_inst( 1357 adev, entry->hwip, entry->instance) : 1358 entry->instance; 1359 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1360 entry->reg; 1361 if (offset == reg) 1362 return true; 1363 } 1364 1365 return false; 1366 } 1367 1368 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1369 { 1370 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1371 (void *)rlcg_access_gc_9_4_3, 1372 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1373 } 1374 1375 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1376 bool enable, int xcc_id) 1377 { 1378 if (enable) { 1379 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1380 } else { 1381 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1382 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1383 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1384 } 1385 udelay(50); 1386 } 1387 1388 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1389 int xcc_id) 1390 { 1391 const struct gfx_firmware_header_v1_0 *mec_hdr; 1392 const __le32 *fw_data; 1393 unsigned i; 1394 u32 tmp; 1395 u32 mec_ucode_addr_offset; 1396 u32 mec_ucode_data_offset; 1397 1398 if (!adev->gfx.mec_fw) 1399 return -EINVAL; 1400 1401 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1402 1403 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1404 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1405 1406 fw_data = (const __le32 *) 1407 (adev->gfx.mec_fw->data + 1408 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1409 tmp = 0; 1410 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1411 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1412 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1413 1414 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1415 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1416 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1417 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1418 1419 mec_ucode_addr_offset = 1420 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1421 mec_ucode_data_offset = 1422 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1423 1424 /* MEC1 */ 1425 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1426 for (i = 0; i < mec_hdr->jt_size; i++) 1427 WREG32(mec_ucode_data_offset, 1428 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1429 1430 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1431 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1432 1433 return 0; 1434 } 1435 1436 /* KIQ functions */ 1437 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1438 { 1439 uint32_t tmp; 1440 struct amdgpu_device *adev = ring->adev; 1441 1442 /* tell RLC which is KIQ queue */ 1443 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1444 tmp &= 0xffffff00; 1445 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1446 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1447 tmp |= 0x80; 1448 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1449 } 1450 1451 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1452 { 1453 struct amdgpu_device *adev = ring->adev; 1454 1455 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1456 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1457 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1458 mqd->cp_hqd_queue_priority = 1459 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1460 } 1461 } 1462 } 1463 1464 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1465 { 1466 struct amdgpu_device *adev = ring->adev; 1467 struct v9_mqd *mqd = ring->mqd_ptr; 1468 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1469 uint32_t tmp; 1470 1471 mqd->header = 0xC0310800; 1472 mqd->compute_pipelinestat_enable = 0x00000001; 1473 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1474 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1475 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1476 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1477 mqd->compute_misc_reserved = 0x00000003; 1478 1479 mqd->dynamic_cu_mask_addr_lo = 1480 lower_32_bits(ring->mqd_gpu_addr 1481 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1482 mqd->dynamic_cu_mask_addr_hi = 1483 upper_32_bits(ring->mqd_gpu_addr 1484 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1485 1486 eop_base_addr = ring->eop_gpu_addr >> 8; 1487 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1488 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1489 1490 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1491 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1492 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1493 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1494 1495 mqd->cp_hqd_eop_control = tmp; 1496 1497 /* enable doorbell? */ 1498 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1499 1500 if (ring->use_doorbell) { 1501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1502 DOORBELL_OFFSET, ring->doorbell_index); 1503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1504 DOORBELL_EN, 1); 1505 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1506 DOORBELL_SOURCE, 0); 1507 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1508 DOORBELL_HIT, 0); 1509 } else { 1510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1511 DOORBELL_EN, 0); 1512 } 1513 1514 mqd->cp_hqd_pq_doorbell_control = tmp; 1515 1516 /* disable the queue if it's active */ 1517 ring->wptr = 0; 1518 mqd->cp_hqd_dequeue_request = 0; 1519 mqd->cp_hqd_pq_rptr = 0; 1520 mqd->cp_hqd_pq_wptr_lo = 0; 1521 mqd->cp_hqd_pq_wptr_hi = 0; 1522 1523 /* set the pointer to the MQD */ 1524 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1525 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1526 1527 /* set MQD vmid to 0 */ 1528 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1529 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1530 mqd->cp_mqd_control = tmp; 1531 1532 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1533 hqd_gpu_addr = ring->gpu_addr >> 8; 1534 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1535 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1536 1537 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1538 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1540 (order_base_2(ring->ring_size / 4) - 1)); 1541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1542 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1543 #ifdef __BIG_ENDIAN 1544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1545 #endif 1546 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1550 mqd->cp_hqd_pq_control = tmp; 1551 1552 /* set the wb address whether it's enabled or not */ 1553 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1554 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1555 mqd->cp_hqd_pq_rptr_report_addr_hi = 1556 upper_32_bits(wb_gpu_addr) & 0xffff; 1557 1558 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1559 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1560 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1561 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1562 1563 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1564 ring->wptr = 0; 1565 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1566 1567 /* set the vmid for the queue */ 1568 mqd->cp_hqd_vmid = 0; 1569 1570 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1571 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1572 mqd->cp_hqd_persistent_state = tmp; 1573 1574 /* set MIN_IB_AVAIL_SIZE */ 1575 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1576 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1577 mqd->cp_hqd_ib_control = tmp; 1578 1579 /* set static priority for a queue/ring */ 1580 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1581 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1582 1583 /* map_queues packet doesn't need activate the queue, 1584 * so only kiq need set this field. 1585 */ 1586 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1587 mqd->cp_hqd_active = 1; 1588 1589 return 0; 1590 } 1591 1592 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1593 int xcc_id) 1594 { 1595 struct amdgpu_device *adev = ring->adev; 1596 struct v9_mqd *mqd = ring->mqd_ptr; 1597 int j; 1598 1599 /* disable wptr polling */ 1600 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1601 1602 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1603 mqd->cp_hqd_eop_base_addr_lo); 1604 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1605 mqd->cp_hqd_eop_base_addr_hi); 1606 1607 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1608 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1609 mqd->cp_hqd_eop_control); 1610 1611 /* enable doorbell? */ 1612 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1613 mqd->cp_hqd_pq_doorbell_control); 1614 1615 /* disable the queue if it's active */ 1616 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1617 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1618 for (j = 0; j < adev->usec_timeout; j++) { 1619 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1620 break; 1621 udelay(1); 1622 } 1623 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1624 mqd->cp_hqd_dequeue_request); 1625 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1626 mqd->cp_hqd_pq_rptr); 1627 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1628 mqd->cp_hqd_pq_wptr_lo); 1629 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1630 mqd->cp_hqd_pq_wptr_hi); 1631 } 1632 1633 /* set the pointer to the MQD */ 1634 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1635 mqd->cp_mqd_base_addr_lo); 1636 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1637 mqd->cp_mqd_base_addr_hi); 1638 1639 /* set MQD vmid to 0 */ 1640 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1641 mqd->cp_mqd_control); 1642 1643 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1644 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1645 mqd->cp_hqd_pq_base_lo); 1646 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1647 mqd->cp_hqd_pq_base_hi); 1648 1649 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1650 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1651 mqd->cp_hqd_pq_control); 1652 1653 /* set the wb address whether it's enabled or not */ 1654 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1655 mqd->cp_hqd_pq_rptr_report_addr_lo); 1656 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1657 mqd->cp_hqd_pq_rptr_report_addr_hi); 1658 1659 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1660 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1661 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1662 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1663 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1664 1665 /* enable the doorbell if requested */ 1666 if (ring->use_doorbell) { 1667 WREG32_SOC15( 1668 GC, GET_INST(GC, xcc_id), 1669 regCP_MEC_DOORBELL_RANGE_LOWER, 1670 ((adev->doorbell_index.kiq + 1671 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1672 2) << 2); 1673 WREG32_SOC15( 1674 GC, GET_INST(GC, xcc_id), 1675 regCP_MEC_DOORBELL_RANGE_UPPER, 1676 ((adev->doorbell_index.userqueue_end + 1677 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1678 2) << 2); 1679 } 1680 1681 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1682 mqd->cp_hqd_pq_doorbell_control); 1683 1684 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1685 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1686 mqd->cp_hqd_pq_wptr_lo); 1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1688 mqd->cp_hqd_pq_wptr_hi); 1689 1690 /* set the vmid for the queue */ 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1692 1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1694 mqd->cp_hqd_persistent_state); 1695 1696 /* activate the queue */ 1697 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1698 mqd->cp_hqd_active); 1699 1700 if (ring->use_doorbell) 1701 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1702 1703 return 0; 1704 } 1705 1706 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1707 int xcc_id) 1708 { 1709 struct amdgpu_device *adev = ring->adev; 1710 int j; 1711 1712 /* disable the queue if it's active */ 1713 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1714 1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1716 1717 for (j = 0; j < adev->usec_timeout; j++) { 1718 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1719 break; 1720 udelay(1); 1721 } 1722 1723 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1724 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1725 1726 /* Manual disable if dequeue request times out */ 1727 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1728 } 1729 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1731 0); 1732 } 1733 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1738 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1742 1743 return 0; 1744 } 1745 1746 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1747 { 1748 struct amdgpu_device *adev = ring->adev; 1749 struct v9_mqd *mqd = ring->mqd_ptr; 1750 struct v9_mqd *tmp_mqd; 1751 1752 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1753 1754 /* GPU could be in bad state during probe, driver trigger the reset 1755 * after load the SMU, in this case , the mqd is not be initialized. 1756 * driver need to re-init the mqd. 1757 * check mqd->cp_hqd_pq_control since this value should not be 0 1758 */ 1759 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1760 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1761 /* for GPU_RESET case , reset MQD to a clean status */ 1762 if (adev->gfx.kiq[xcc_id].mqd_backup) 1763 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1764 1765 /* reset ring buffer */ 1766 ring->wptr = 0; 1767 amdgpu_ring_clear_ring(ring); 1768 mutex_lock(&adev->srbm_mutex); 1769 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1770 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1771 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1772 mutex_unlock(&adev->srbm_mutex); 1773 } else { 1774 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1775 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1776 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1777 mutex_lock(&adev->srbm_mutex); 1778 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1779 amdgpu_ring_clear_ring(ring); 1780 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1781 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1782 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1783 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1784 mutex_unlock(&adev->srbm_mutex); 1785 1786 if (adev->gfx.kiq[xcc_id].mqd_backup) 1787 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1788 } 1789 1790 return 0; 1791 } 1792 1793 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1794 { 1795 struct amdgpu_device *adev = ring->adev; 1796 struct v9_mqd *mqd = ring->mqd_ptr; 1797 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1798 struct v9_mqd *tmp_mqd; 1799 1800 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1801 * is not be initialized before 1802 */ 1803 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1804 1805 if (!tmp_mqd->cp_hqd_pq_control || 1806 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1807 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1808 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1809 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1810 mutex_lock(&adev->srbm_mutex); 1811 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1812 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1813 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1814 mutex_unlock(&adev->srbm_mutex); 1815 1816 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1817 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1818 } else { 1819 /* restore MQD to a clean status */ 1820 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1821 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1822 /* reset ring buffer */ 1823 ring->wptr = 0; 1824 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1825 amdgpu_ring_clear_ring(ring); 1826 } 1827 1828 return 0; 1829 } 1830 1831 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1832 { 1833 struct amdgpu_ring *ring; 1834 int j; 1835 1836 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1837 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1838 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1839 mutex_lock(&adev->srbm_mutex); 1840 soc15_grbm_select(adev, ring->me, 1841 ring->pipe, 1842 ring->queue, 0, GET_INST(GC, xcc_id)); 1843 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1844 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1845 mutex_unlock(&adev->srbm_mutex); 1846 } 1847 } 1848 1849 return 0; 1850 } 1851 1852 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1853 { 1854 struct amdgpu_ring *ring; 1855 int r; 1856 1857 ring = &adev->gfx.kiq[xcc_id].ring; 1858 1859 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1860 if (unlikely(r != 0)) 1861 return r; 1862 1863 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1864 if (unlikely(r != 0)) { 1865 amdgpu_bo_unreserve(ring->mqd_obj); 1866 return r; 1867 } 1868 1869 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1870 amdgpu_bo_kunmap(ring->mqd_obj); 1871 ring->mqd_ptr = NULL; 1872 amdgpu_bo_unreserve(ring->mqd_obj); 1873 return 0; 1874 } 1875 1876 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1877 { 1878 struct amdgpu_ring *ring = NULL; 1879 int r = 0, i; 1880 1881 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1882 1883 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1884 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1885 1886 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1887 if (unlikely(r != 0)) 1888 goto done; 1889 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1890 if (!r) { 1891 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1892 amdgpu_bo_kunmap(ring->mqd_obj); 1893 ring->mqd_ptr = NULL; 1894 } 1895 amdgpu_bo_unreserve(ring->mqd_obj); 1896 if (r) 1897 goto done; 1898 } 1899 1900 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1901 done: 1902 return r; 1903 } 1904 1905 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1906 { 1907 struct amdgpu_ring *ring; 1908 int r, j; 1909 1910 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1911 1912 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1913 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1914 1915 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1916 if (r) 1917 return r; 1918 } 1919 1920 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1921 if (r) 1922 return r; 1923 1924 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1925 if (r) 1926 return r; 1927 1928 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1929 ring = &adev->gfx.compute_ring 1930 [j + xcc_id * adev->gfx.num_compute_rings]; 1931 r = amdgpu_ring_test_helper(ring); 1932 if (r) 1933 return r; 1934 } 1935 1936 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1937 1938 return 0; 1939 } 1940 1941 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1942 { 1943 int r = 0, i, num_xcc; 1944 1945 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1946 AMDGPU_XCP_FL_NONE) == 1947 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1948 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1949 amdgpu_user_partt_mode); 1950 1951 if (r) 1952 return r; 1953 1954 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1955 for (i = 0; i < num_xcc; i++) { 1956 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1957 if (r) 1958 return r; 1959 } 1960 1961 return 0; 1962 } 1963 1964 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1965 int xcc_id) 1966 { 1967 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1968 } 1969 1970 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1971 { 1972 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1973 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1974 1975 if (amdgpu_sriov_vf(adev)) { 1976 /* must disable polling for SRIOV when hw finished, otherwise 1977 * CPC engine may still keep fetching WB address which is already 1978 * invalid after sw finished and trigger DMAR reading error in 1979 * hypervisor side. 1980 */ 1981 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1982 return; 1983 } 1984 1985 /* Use deinitialize sequence from CAIL when unbinding device 1986 * from driver, otherwise KIQ is hanging when binding back 1987 */ 1988 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1989 mutex_lock(&adev->srbm_mutex); 1990 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1991 adev->gfx.kiq[xcc_id].ring.pipe, 1992 adev->gfx.kiq[xcc_id].ring.queue, 0, 1993 GET_INST(GC, xcc_id)); 1994 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1995 xcc_id); 1996 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1997 mutex_unlock(&adev->srbm_mutex); 1998 } 1999 2000 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2001 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2002 } 2003 2004 static int gfx_v9_4_3_hw_init(void *handle) 2005 { 2006 int r; 2007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2008 2009 if (!amdgpu_sriov_vf(adev)) 2010 gfx_v9_4_3_init_golden_registers(adev); 2011 2012 gfx_v9_4_3_constants_init(adev); 2013 2014 r = adev->gfx.rlc.funcs->resume(adev); 2015 if (r) 2016 return r; 2017 2018 r = gfx_v9_4_3_cp_resume(adev); 2019 if (r) 2020 return r; 2021 2022 return r; 2023 } 2024 2025 static int gfx_v9_4_3_hw_fini(void *handle) 2026 { 2027 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2028 int i, num_xcc; 2029 2030 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2031 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2032 2033 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2034 for (i = 0; i < num_xcc; i++) { 2035 gfx_v9_4_3_xcc_fini(adev, i); 2036 } 2037 2038 return 0; 2039 } 2040 2041 static int gfx_v9_4_3_suspend(void *handle) 2042 { 2043 return gfx_v9_4_3_hw_fini(handle); 2044 } 2045 2046 static int gfx_v9_4_3_resume(void *handle) 2047 { 2048 return gfx_v9_4_3_hw_init(handle); 2049 } 2050 2051 static bool gfx_v9_4_3_is_idle(void *handle) 2052 { 2053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2054 int i, num_xcc; 2055 2056 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2057 for (i = 0; i < num_xcc; i++) { 2058 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2059 GRBM_STATUS, GUI_ACTIVE)) 2060 return false; 2061 } 2062 return true; 2063 } 2064 2065 static int gfx_v9_4_3_wait_for_idle(void *handle) 2066 { 2067 unsigned i; 2068 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2069 2070 for (i = 0; i < adev->usec_timeout; i++) { 2071 if (gfx_v9_4_3_is_idle(handle)) 2072 return 0; 2073 udelay(1); 2074 } 2075 return -ETIMEDOUT; 2076 } 2077 2078 static int gfx_v9_4_3_soft_reset(void *handle) 2079 { 2080 u32 grbm_soft_reset = 0; 2081 u32 tmp; 2082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2083 2084 /* GRBM_STATUS */ 2085 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2086 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2087 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2088 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2089 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2090 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2091 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2093 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2094 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2095 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2096 } 2097 2098 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2099 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2100 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2101 } 2102 2103 /* GRBM_STATUS2 */ 2104 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2105 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2106 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2107 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2108 2109 2110 if (grbm_soft_reset) { 2111 /* stop the rlc */ 2112 adev->gfx.rlc.funcs->stop(adev); 2113 2114 /* Disable MEC parsing/prefetching */ 2115 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2116 2117 if (grbm_soft_reset) { 2118 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2119 tmp |= grbm_soft_reset; 2120 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2121 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2122 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2123 2124 udelay(50); 2125 2126 tmp &= ~grbm_soft_reset; 2127 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2128 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2129 } 2130 2131 /* Wait a little for things to settle down */ 2132 udelay(50); 2133 } 2134 return 0; 2135 } 2136 2137 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2138 uint32_t vmid, 2139 uint32_t gds_base, uint32_t gds_size, 2140 uint32_t gws_base, uint32_t gws_size, 2141 uint32_t oa_base, uint32_t oa_size) 2142 { 2143 struct amdgpu_device *adev = ring->adev; 2144 2145 /* GDS Base */ 2146 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2147 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2148 gds_base); 2149 2150 /* GDS Size */ 2151 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2152 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2153 gds_size); 2154 2155 /* GWS */ 2156 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2157 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2158 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2159 2160 /* OA */ 2161 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2162 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2163 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2164 } 2165 2166 static int gfx_v9_4_3_early_init(void *handle) 2167 { 2168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2169 2170 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2171 AMDGPU_MAX_COMPUTE_RINGS); 2172 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2173 gfx_v9_4_3_set_ring_funcs(adev); 2174 gfx_v9_4_3_set_irq_funcs(adev); 2175 gfx_v9_4_3_set_gds_init(adev); 2176 gfx_v9_4_3_set_rlc_funcs(adev); 2177 2178 /* init rlcg reg access ctrl */ 2179 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2180 2181 return gfx_v9_4_3_init_microcode(adev); 2182 } 2183 2184 static int gfx_v9_4_3_late_init(void *handle) 2185 { 2186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2187 int r; 2188 2189 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2190 if (r) 2191 return r; 2192 2193 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2194 if (r) 2195 return r; 2196 2197 if (adev->gfx.ras && 2198 adev->gfx.ras->enable_watchdog_timer) 2199 adev->gfx.ras->enable_watchdog_timer(adev); 2200 2201 return 0; 2202 } 2203 2204 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2205 bool enable, int xcc_id) 2206 { 2207 uint32_t def, data; 2208 2209 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2210 return; 2211 2212 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2213 regRLC_CGTT_MGCG_OVERRIDE); 2214 2215 if (enable) 2216 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2217 else 2218 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2219 2220 if (def != data) 2221 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2222 regRLC_CGTT_MGCG_OVERRIDE, data); 2223 2224 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); 2225 2226 if (enable) 2227 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2228 else 2229 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 2230 2231 if (def != data) 2232 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); 2233 } 2234 2235 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2236 bool enable, int xcc_id) 2237 { 2238 uint32_t def, data; 2239 2240 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2241 return; 2242 2243 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2244 regRLC_CGTT_MGCG_OVERRIDE); 2245 2246 if (enable) 2247 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2248 else 2249 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2250 2251 if (def != data) 2252 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2253 regRLC_CGTT_MGCG_OVERRIDE, data); 2254 } 2255 2256 static void 2257 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2258 bool enable, int xcc_id) 2259 { 2260 uint32_t data, def; 2261 2262 /* It is disabled by HW by default */ 2263 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2264 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2265 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2266 2267 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2268 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2269 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2270 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2271 2272 if (def != data) 2273 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2274 2275 /* MGLS is a global flag to control all MGLS in GFX */ 2276 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2277 /* 2 - RLC memory Light sleep */ 2278 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2279 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2280 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2281 if (def != data) 2282 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2283 } 2284 /* 3 - CP memory Light sleep */ 2285 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2286 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2287 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2288 if (def != data) 2289 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2290 } 2291 } 2292 } else { 2293 /* 1 - MGCG_OVERRIDE */ 2294 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2295 2296 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2297 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2298 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2299 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2300 2301 if (def != data) 2302 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2303 2304 /* 2 - disable MGLS in RLC */ 2305 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2306 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2307 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2308 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2309 } 2310 2311 /* 3 - disable MGLS in CP */ 2312 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2313 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2314 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2315 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2316 } 2317 } 2318 2319 } 2320 2321 static void 2322 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2323 bool enable, int xcc_id) 2324 { 2325 uint32_t def, data; 2326 2327 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2328 2329 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2330 /* unset CGCG override */ 2331 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2332 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2333 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2334 else 2335 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2336 /* update CGCG and CGLS override bits */ 2337 if (def != data) 2338 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2339 2340 /* enable cgcg FSM(0x0000363F) */ 2341 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2342 2343 data = (0x36 2344 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2345 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2346 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2347 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2348 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2349 if (def != data) 2350 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2351 2352 /* set IDLE_POLL_COUNT(0x00900100) */ 2353 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2354 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2355 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2356 if (def != data) 2357 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2358 } else { 2359 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2360 /* reset CGCG/CGLS bits */ 2361 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2362 /* disable cgcg and cgls in FSM */ 2363 if (def != data) 2364 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2365 } 2366 2367 } 2368 2369 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2370 bool enable, int xcc_id) 2371 { 2372 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2373 2374 if (enable) { 2375 /* FGCG */ 2376 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2377 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2378 2379 /* CGCG/CGLS should be enabled after MGCG/MGLS 2380 * === MGCG + MGLS === 2381 */ 2382 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2383 xcc_id); 2384 /* === CGCG + CGLS === */ 2385 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2386 xcc_id); 2387 } else { 2388 /* CGCG/CGLS should be disabled before MGCG/MGLS 2389 * === CGCG + CGLS === 2390 */ 2391 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2392 xcc_id); 2393 /* === MGCG + MGLS === */ 2394 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2395 xcc_id); 2396 2397 /* FGCG */ 2398 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2399 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2400 } 2401 2402 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2403 2404 return 0; 2405 } 2406 2407 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2408 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2409 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2410 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2411 .init = gfx_v9_4_3_rlc_init, 2412 .resume = gfx_v9_4_3_rlc_resume, 2413 .stop = gfx_v9_4_3_rlc_stop, 2414 .reset = gfx_v9_4_3_rlc_reset, 2415 .start = gfx_v9_4_3_rlc_start, 2416 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2417 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2418 }; 2419 2420 static int gfx_v9_4_3_set_powergating_state(void *handle, 2421 enum amd_powergating_state state) 2422 { 2423 return 0; 2424 } 2425 2426 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2427 enum amd_clockgating_state state) 2428 { 2429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2430 int i, num_xcc; 2431 2432 if (amdgpu_sriov_vf(adev)) 2433 return 0; 2434 2435 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2436 switch (adev->ip_versions[GC_HWIP][0]) { 2437 case IP_VERSION(9, 4, 3): 2438 for (i = 0; i < num_xcc; i++) 2439 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2440 adev, state == AMD_CG_STATE_GATE, i); 2441 break; 2442 default: 2443 break; 2444 } 2445 return 0; 2446 } 2447 2448 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2449 { 2450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2451 int data; 2452 2453 if (amdgpu_sriov_vf(adev)) 2454 *flags = 0; 2455 2456 /* AMD_CG_SUPPORT_GFX_MGCG */ 2457 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2458 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2459 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2460 2461 /* AMD_CG_SUPPORT_GFX_CGCG */ 2462 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2463 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2464 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2465 2466 /* AMD_CG_SUPPORT_GFX_CGLS */ 2467 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2468 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2469 2470 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2471 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2472 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2473 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2474 2475 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2476 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2477 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2478 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2479 } 2480 2481 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2482 { 2483 struct amdgpu_device *adev = ring->adev; 2484 u32 ref_and_mask, reg_mem_engine; 2485 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2486 2487 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2488 switch (ring->me) { 2489 case 1: 2490 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2491 break; 2492 case 2: 2493 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2494 break; 2495 default: 2496 return; 2497 } 2498 reg_mem_engine = 0; 2499 } else { 2500 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2501 reg_mem_engine = 1; /* pfp */ 2502 } 2503 2504 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2505 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2506 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2507 ref_and_mask, ref_and_mask, 0x20); 2508 } 2509 2510 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2511 struct amdgpu_job *job, 2512 struct amdgpu_ib *ib, 2513 uint32_t flags) 2514 { 2515 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2516 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2517 2518 /* Currently, there is a high possibility to get wave ID mismatch 2519 * between ME and GDS, leading to a hw deadlock, because ME generates 2520 * different wave IDs than the GDS expects. This situation happens 2521 * randomly when at least 5 compute pipes use GDS ordered append. 2522 * The wave IDs generated by ME are also wrong after suspend/resume. 2523 * Those are probably bugs somewhere else in the kernel driver. 2524 * 2525 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2526 * GDS to 0 for this ring (me/pipe). 2527 */ 2528 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2529 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2530 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2531 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2532 } 2533 2534 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2535 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2536 amdgpu_ring_write(ring, 2537 #ifdef __BIG_ENDIAN 2538 (2 << 0) | 2539 #endif 2540 lower_32_bits(ib->gpu_addr)); 2541 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2542 amdgpu_ring_write(ring, control); 2543 } 2544 2545 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2546 u64 seq, unsigned flags) 2547 { 2548 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2549 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2550 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2551 2552 /* RELEASE_MEM - flush caches, send int */ 2553 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2554 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2555 EOP_TC_NC_ACTION_EN) : 2556 (EOP_TCL1_ACTION_EN | 2557 EOP_TC_ACTION_EN | 2558 EOP_TC_WB_ACTION_EN | 2559 EOP_TC_MD_ACTION_EN)) | 2560 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2561 EVENT_INDEX(5))); 2562 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2563 2564 /* 2565 * the address should be Qword aligned if 64bit write, Dword 2566 * aligned if only send 32bit data low (discard data high) 2567 */ 2568 if (write64bit) 2569 BUG_ON(addr & 0x7); 2570 else 2571 BUG_ON(addr & 0x3); 2572 amdgpu_ring_write(ring, lower_32_bits(addr)); 2573 amdgpu_ring_write(ring, upper_32_bits(addr)); 2574 amdgpu_ring_write(ring, lower_32_bits(seq)); 2575 amdgpu_ring_write(ring, upper_32_bits(seq)); 2576 amdgpu_ring_write(ring, 0); 2577 } 2578 2579 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2580 { 2581 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2582 uint32_t seq = ring->fence_drv.sync_seq; 2583 uint64_t addr = ring->fence_drv.gpu_addr; 2584 2585 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2586 lower_32_bits(addr), upper_32_bits(addr), 2587 seq, 0xffffffff, 4); 2588 } 2589 2590 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2591 unsigned vmid, uint64_t pd_addr) 2592 { 2593 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2594 } 2595 2596 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2597 { 2598 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2599 } 2600 2601 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2602 { 2603 u64 wptr; 2604 2605 /* XXX check if swapping is necessary on BE */ 2606 if (ring->use_doorbell) 2607 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2608 else 2609 BUG(); 2610 return wptr; 2611 } 2612 2613 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2614 { 2615 struct amdgpu_device *adev = ring->adev; 2616 2617 /* XXX check if swapping is necessary on BE */ 2618 if (ring->use_doorbell) { 2619 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2620 WDOORBELL64(ring->doorbell_index, ring->wptr); 2621 } else { 2622 BUG(); /* only DOORBELL method supported on gfx9 now */ 2623 } 2624 } 2625 2626 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2627 u64 seq, unsigned int flags) 2628 { 2629 struct amdgpu_device *adev = ring->adev; 2630 2631 /* we only allocate 32bit for each seq wb address */ 2632 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2633 2634 /* write fence seq to the "addr" */ 2635 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2636 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2637 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2638 amdgpu_ring_write(ring, lower_32_bits(addr)); 2639 amdgpu_ring_write(ring, upper_32_bits(addr)); 2640 amdgpu_ring_write(ring, lower_32_bits(seq)); 2641 2642 if (flags & AMDGPU_FENCE_FLAG_INT) { 2643 /* set register to trigger INT */ 2644 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2645 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2646 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2647 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2648 amdgpu_ring_write(ring, 0); 2649 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2650 } 2651 } 2652 2653 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2654 uint32_t reg_val_offs) 2655 { 2656 struct amdgpu_device *adev = ring->adev; 2657 2658 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2659 amdgpu_ring_write(ring, 0 | /* src: register*/ 2660 (5 << 8) | /* dst: memory */ 2661 (1 << 20)); /* write confirm */ 2662 amdgpu_ring_write(ring, reg); 2663 amdgpu_ring_write(ring, 0); 2664 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2665 reg_val_offs * 4)); 2666 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2667 reg_val_offs * 4)); 2668 } 2669 2670 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2671 uint32_t val) 2672 { 2673 uint32_t cmd = 0; 2674 2675 switch (ring->funcs->type) { 2676 case AMDGPU_RING_TYPE_GFX: 2677 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2678 break; 2679 case AMDGPU_RING_TYPE_KIQ: 2680 cmd = (1 << 16); /* no inc addr */ 2681 break; 2682 default: 2683 cmd = WR_CONFIRM; 2684 break; 2685 } 2686 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2687 amdgpu_ring_write(ring, cmd); 2688 amdgpu_ring_write(ring, reg); 2689 amdgpu_ring_write(ring, 0); 2690 amdgpu_ring_write(ring, val); 2691 } 2692 2693 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2694 uint32_t val, uint32_t mask) 2695 { 2696 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2697 } 2698 2699 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2700 uint32_t reg0, uint32_t reg1, 2701 uint32_t ref, uint32_t mask) 2702 { 2703 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2704 ref, mask); 2705 } 2706 2707 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2708 struct amdgpu_device *adev, int me, int pipe, 2709 enum amdgpu_interrupt_state state, int xcc_id) 2710 { 2711 u32 mec_int_cntl, mec_int_cntl_reg; 2712 2713 /* 2714 * amdgpu controls only the first MEC. That's why this function only 2715 * handles the setting of interrupts for this specific MEC. All other 2716 * pipes' interrupts are set by amdkfd. 2717 */ 2718 2719 if (me == 1) { 2720 switch (pipe) { 2721 case 0: 2722 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2723 break; 2724 case 1: 2725 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2726 break; 2727 case 2: 2728 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2729 break; 2730 case 3: 2731 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2732 break; 2733 default: 2734 DRM_DEBUG("invalid pipe %d\n", pipe); 2735 return; 2736 } 2737 } else { 2738 DRM_DEBUG("invalid me %d\n", me); 2739 return; 2740 } 2741 2742 switch (state) { 2743 case AMDGPU_IRQ_STATE_DISABLE: 2744 mec_int_cntl = RREG32(mec_int_cntl_reg); 2745 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2746 TIME_STAMP_INT_ENABLE, 0); 2747 WREG32(mec_int_cntl_reg, mec_int_cntl); 2748 break; 2749 case AMDGPU_IRQ_STATE_ENABLE: 2750 mec_int_cntl = RREG32(mec_int_cntl_reg); 2751 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2752 TIME_STAMP_INT_ENABLE, 1); 2753 WREG32(mec_int_cntl_reg, mec_int_cntl); 2754 break; 2755 default: 2756 break; 2757 } 2758 } 2759 2760 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2761 struct amdgpu_irq_src *source, 2762 unsigned type, 2763 enum amdgpu_interrupt_state state) 2764 { 2765 int i, num_xcc; 2766 2767 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2768 switch (state) { 2769 case AMDGPU_IRQ_STATE_DISABLE: 2770 case AMDGPU_IRQ_STATE_ENABLE: 2771 for (i = 0; i < num_xcc; i++) 2772 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2773 PRIV_REG_INT_ENABLE, 2774 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2775 break; 2776 default: 2777 break; 2778 } 2779 2780 return 0; 2781 } 2782 2783 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2784 struct amdgpu_irq_src *source, 2785 unsigned type, 2786 enum amdgpu_interrupt_state state) 2787 { 2788 int i, num_xcc; 2789 2790 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2791 switch (state) { 2792 case AMDGPU_IRQ_STATE_DISABLE: 2793 case AMDGPU_IRQ_STATE_ENABLE: 2794 for (i = 0; i < num_xcc; i++) 2795 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2796 PRIV_INSTR_INT_ENABLE, 2797 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2798 break; 2799 default: 2800 break; 2801 } 2802 2803 return 0; 2804 } 2805 2806 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2807 struct amdgpu_irq_src *src, 2808 unsigned type, 2809 enum amdgpu_interrupt_state state) 2810 { 2811 int i, num_xcc; 2812 2813 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2814 for (i = 0; i < num_xcc; i++) { 2815 switch (type) { 2816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2817 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2818 adev, 1, 0, state, i); 2819 break; 2820 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2821 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2822 adev, 1, 1, state, i); 2823 break; 2824 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2825 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2826 adev, 1, 2, state, i); 2827 break; 2828 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2829 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2830 adev, 1, 3, state, i); 2831 break; 2832 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2833 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2834 adev, 2, 0, state, i); 2835 break; 2836 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2837 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2838 adev, 2, 1, state, i); 2839 break; 2840 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2841 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2842 adev, 2, 2, state, i); 2843 break; 2844 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2845 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2846 adev, 2, 3, state, i); 2847 break; 2848 default: 2849 break; 2850 } 2851 } 2852 2853 return 0; 2854 } 2855 2856 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2857 struct amdgpu_irq_src *source, 2858 struct amdgpu_iv_entry *entry) 2859 { 2860 int i, xcc_id; 2861 u8 me_id, pipe_id, queue_id; 2862 struct amdgpu_ring *ring; 2863 2864 DRM_DEBUG("IH: CP EOP\n"); 2865 me_id = (entry->ring_id & 0x0c) >> 2; 2866 pipe_id = (entry->ring_id & 0x03) >> 0; 2867 queue_id = (entry->ring_id & 0x70) >> 4; 2868 2869 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2870 2871 if (xcc_id == -EINVAL) 2872 return -EINVAL; 2873 2874 switch (me_id) { 2875 case 0: 2876 case 1: 2877 case 2: 2878 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2879 ring = &adev->gfx.compute_ring 2880 [i + 2881 xcc_id * adev->gfx.num_compute_rings]; 2882 /* Per-queue interrupt is supported for MEC starting from VI. 2883 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2884 */ 2885 2886 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2887 amdgpu_fence_process(ring); 2888 } 2889 break; 2890 } 2891 return 0; 2892 } 2893 2894 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2895 struct amdgpu_iv_entry *entry) 2896 { 2897 u8 me_id, pipe_id, queue_id; 2898 struct amdgpu_ring *ring; 2899 int i, xcc_id; 2900 2901 me_id = (entry->ring_id & 0x0c) >> 2; 2902 pipe_id = (entry->ring_id & 0x03) >> 0; 2903 queue_id = (entry->ring_id & 0x70) >> 4; 2904 2905 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2906 2907 if (xcc_id == -EINVAL) 2908 return; 2909 2910 switch (me_id) { 2911 case 0: 2912 case 1: 2913 case 2: 2914 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2915 ring = &adev->gfx.compute_ring 2916 [i + 2917 xcc_id * adev->gfx.num_compute_rings]; 2918 if (ring->me == me_id && ring->pipe == pipe_id && 2919 ring->queue == queue_id) 2920 drm_sched_fault(&ring->sched); 2921 } 2922 break; 2923 } 2924 } 2925 2926 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2927 struct amdgpu_irq_src *source, 2928 struct amdgpu_iv_entry *entry) 2929 { 2930 DRM_ERROR("Illegal register access in command stream\n"); 2931 gfx_v9_4_3_fault(adev, entry); 2932 return 0; 2933 } 2934 2935 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2936 struct amdgpu_irq_src *source, 2937 struct amdgpu_iv_entry *entry) 2938 { 2939 DRM_ERROR("Illegal instruction in command stream\n"); 2940 gfx_v9_4_3_fault(adev, entry); 2941 return 0; 2942 } 2943 2944 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2945 { 2946 const unsigned int cp_coher_cntl = 2947 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2948 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2949 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2950 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2951 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2952 2953 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2954 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2955 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2956 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2957 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2958 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2959 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2960 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2961 } 2962 2963 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2964 uint32_t pipe, bool enable) 2965 { 2966 struct amdgpu_device *adev = ring->adev; 2967 uint32_t val; 2968 uint32_t wcl_cs_reg; 2969 2970 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2971 val = enable ? 0x1 : 0x7f; 2972 2973 switch (pipe) { 2974 case 0: 2975 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2976 break; 2977 case 1: 2978 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2979 break; 2980 case 2: 2981 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2982 break; 2983 case 3: 2984 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2985 break; 2986 default: 2987 DRM_DEBUG("invalid pipe %d\n", pipe); 2988 return; 2989 } 2990 2991 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2992 2993 } 2994 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2995 { 2996 struct amdgpu_device *adev = ring->adev; 2997 uint32_t val; 2998 int i; 2999 3000 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3001 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3002 * around 25% of gpu resources. 3003 */ 3004 val = enable ? 0x1f : 0x07ffffff; 3005 amdgpu_ring_emit_wreg(ring, 3006 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3007 val); 3008 3009 /* Restrict waves for normal/low priority compute queues as well 3010 * to get best QoS for high priority compute jobs. 3011 * 3012 * amdgpu controls only 1st ME(0-3 CS pipes). 3013 */ 3014 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3015 if (i != ring->pipe) 3016 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3017 3018 } 3019 } 3020 3021 enum amdgpu_gfx_cp_ras_mem_id { 3022 AMDGPU_GFX_CP_MEM1 = 1, 3023 AMDGPU_GFX_CP_MEM2, 3024 AMDGPU_GFX_CP_MEM3, 3025 AMDGPU_GFX_CP_MEM4, 3026 AMDGPU_GFX_CP_MEM5, 3027 }; 3028 3029 enum amdgpu_gfx_gcea_ras_mem_id { 3030 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3031 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3032 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3033 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3034 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3035 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3036 AMDGPU_GFX_GCEA_MAM_DMEM0, 3037 AMDGPU_GFX_GCEA_MAM_DMEM1, 3038 AMDGPU_GFX_GCEA_MAM_DMEM2, 3039 AMDGPU_GFX_GCEA_MAM_DMEM3, 3040 AMDGPU_GFX_GCEA_MAM_AMEM0, 3041 AMDGPU_GFX_GCEA_MAM_AMEM1, 3042 AMDGPU_GFX_GCEA_MAM_AMEM2, 3043 AMDGPU_GFX_GCEA_MAM_AMEM3, 3044 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3045 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3046 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3047 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3048 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3049 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3050 }; 3051 3052 enum amdgpu_gfx_gc_cane_ras_mem_id { 3053 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3054 }; 3055 3056 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3057 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3058 }; 3059 3060 enum amdgpu_gfx_gds_ras_mem_id { 3061 AMDGPU_GFX_GDS_MEM0 = 0, 3062 }; 3063 3064 enum amdgpu_gfx_lds_ras_mem_id { 3065 AMDGPU_GFX_LDS_BANK0 = 0, 3066 AMDGPU_GFX_LDS_BANK1, 3067 AMDGPU_GFX_LDS_BANK2, 3068 AMDGPU_GFX_LDS_BANK3, 3069 AMDGPU_GFX_LDS_BANK4, 3070 AMDGPU_GFX_LDS_BANK5, 3071 AMDGPU_GFX_LDS_BANK6, 3072 AMDGPU_GFX_LDS_BANK7, 3073 AMDGPU_GFX_LDS_BANK8, 3074 AMDGPU_GFX_LDS_BANK9, 3075 AMDGPU_GFX_LDS_BANK10, 3076 AMDGPU_GFX_LDS_BANK11, 3077 AMDGPU_GFX_LDS_BANK12, 3078 AMDGPU_GFX_LDS_BANK13, 3079 AMDGPU_GFX_LDS_BANK14, 3080 AMDGPU_GFX_LDS_BANK15, 3081 AMDGPU_GFX_LDS_BANK16, 3082 AMDGPU_GFX_LDS_BANK17, 3083 AMDGPU_GFX_LDS_BANK18, 3084 AMDGPU_GFX_LDS_BANK19, 3085 AMDGPU_GFX_LDS_BANK20, 3086 AMDGPU_GFX_LDS_BANK21, 3087 AMDGPU_GFX_LDS_BANK22, 3088 AMDGPU_GFX_LDS_BANK23, 3089 AMDGPU_GFX_LDS_BANK24, 3090 AMDGPU_GFX_LDS_BANK25, 3091 AMDGPU_GFX_LDS_BANK26, 3092 AMDGPU_GFX_LDS_BANK27, 3093 AMDGPU_GFX_LDS_BANK28, 3094 AMDGPU_GFX_LDS_BANK29, 3095 AMDGPU_GFX_LDS_BANK30, 3096 AMDGPU_GFX_LDS_BANK31, 3097 AMDGPU_GFX_LDS_SP_BUFFER_A, 3098 AMDGPU_GFX_LDS_SP_BUFFER_B, 3099 }; 3100 3101 enum amdgpu_gfx_rlc_ras_mem_id { 3102 AMDGPU_GFX_RLC_GPMF32 = 1, 3103 AMDGPU_GFX_RLC_RLCVF32, 3104 AMDGPU_GFX_RLC_SCRATCH, 3105 AMDGPU_GFX_RLC_SRM_ARAM, 3106 AMDGPU_GFX_RLC_SRM_DRAM, 3107 AMDGPU_GFX_RLC_TCTAG, 3108 AMDGPU_GFX_RLC_SPM_SE, 3109 AMDGPU_GFX_RLC_SPM_GRBMT, 3110 }; 3111 3112 enum amdgpu_gfx_sp_ras_mem_id { 3113 AMDGPU_GFX_SP_SIMDID0 = 0, 3114 }; 3115 3116 enum amdgpu_gfx_spi_ras_mem_id { 3117 AMDGPU_GFX_SPI_MEM0 = 0, 3118 AMDGPU_GFX_SPI_MEM1, 3119 AMDGPU_GFX_SPI_MEM2, 3120 AMDGPU_GFX_SPI_MEM3, 3121 }; 3122 3123 enum amdgpu_gfx_sqc_ras_mem_id { 3124 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3125 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3126 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3127 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3128 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3129 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3130 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3131 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3132 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3133 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3134 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3135 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3136 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3137 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3138 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3139 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3140 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3141 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3142 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3143 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3144 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3145 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3146 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3147 }; 3148 3149 enum amdgpu_gfx_sq_ras_mem_id { 3150 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3151 AMDGPU_GFX_SQ_SGPR_MEM1, 3152 AMDGPU_GFX_SQ_SGPR_MEM2, 3153 AMDGPU_GFX_SQ_SGPR_MEM3, 3154 }; 3155 3156 enum amdgpu_gfx_ta_ras_mem_id { 3157 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3158 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3159 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3160 AMDGPU_GFX_TA_FSX_LFIFO, 3161 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3162 }; 3163 3164 enum amdgpu_gfx_tcc_ras_mem_id { 3165 AMDGPU_GFX_TCC_MEM1 = 1, 3166 }; 3167 3168 enum amdgpu_gfx_tca_ras_mem_id { 3169 AMDGPU_GFX_TCA_MEM1 = 1, 3170 }; 3171 3172 enum amdgpu_gfx_tci_ras_mem_id { 3173 AMDGPU_GFX_TCIW_MEM = 1, 3174 }; 3175 3176 enum amdgpu_gfx_tcp_ras_mem_id { 3177 AMDGPU_GFX_TCP_LFIFO0 = 1, 3178 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3179 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3180 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3181 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3182 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3183 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3184 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3185 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3186 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3187 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3188 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3189 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3190 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3191 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3192 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3193 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3194 AMDGPU_GFX_TCP_VM_FIFO, 3195 AMDGPU_GFX_TCP_DB_TAGRAM0, 3196 AMDGPU_GFX_TCP_DB_TAGRAM1, 3197 AMDGPU_GFX_TCP_DB_TAGRAM2, 3198 AMDGPU_GFX_TCP_DB_TAGRAM3, 3199 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3200 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3201 AMDGPU_GFX_TCP_CMD_FIFO, 3202 }; 3203 3204 enum amdgpu_gfx_td_ras_mem_id { 3205 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3206 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3207 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3208 }; 3209 3210 enum amdgpu_gfx_tcx_ras_mem_id { 3211 AMDGPU_GFX_TCX_FIFOD0 = 0, 3212 AMDGPU_GFX_TCX_FIFOD1, 3213 AMDGPU_GFX_TCX_FIFOD2, 3214 AMDGPU_GFX_TCX_FIFOD3, 3215 AMDGPU_GFX_TCX_FIFOD4, 3216 AMDGPU_GFX_TCX_FIFOD5, 3217 AMDGPU_GFX_TCX_FIFOD6, 3218 AMDGPU_GFX_TCX_FIFOD7, 3219 AMDGPU_GFX_TCX_FIFOB0, 3220 AMDGPU_GFX_TCX_FIFOB1, 3221 AMDGPU_GFX_TCX_FIFOB2, 3222 AMDGPU_GFX_TCX_FIFOB3, 3223 AMDGPU_GFX_TCX_FIFOB4, 3224 AMDGPU_GFX_TCX_FIFOB5, 3225 AMDGPU_GFX_TCX_FIFOB6, 3226 AMDGPU_GFX_TCX_FIFOB7, 3227 AMDGPU_GFX_TCX_FIFOA0, 3228 AMDGPU_GFX_TCX_FIFOA1, 3229 AMDGPU_GFX_TCX_FIFOA2, 3230 AMDGPU_GFX_TCX_FIFOA3, 3231 AMDGPU_GFX_TCX_FIFOA4, 3232 AMDGPU_GFX_TCX_FIFOA5, 3233 AMDGPU_GFX_TCX_FIFOA6, 3234 AMDGPU_GFX_TCX_FIFOA7, 3235 AMDGPU_GFX_TCX_CFIFO0, 3236 AMDGPU_GFX_TCX_CFIFO1, 3237 AMDGPU_GFX_TCX_CFIFO2, 3238 AMDGPU_GFX_TCX_CFIFO3, 3239 AMDGPU_GFX_TCX_CFIFO4, 3240 AMDGPU_GFX_TCX_CFIFO5, 3241 AMDGPU_GFX_TCX_CFIFO6, 3242 AMDGPU_GFX_TCX_CFIFO7, 3243 AMDGPU_GFX_TCX_FIFO_ACKB0, 3244 AMDGPU_GFX_TCX_FIFO_ACKB1, 3245 AMDGPU_GFX_TCX_FIFO_ACKB2, 3246 AMDGPU_GFX_TCX_FIFO_ACKB3, 3247 AMDGPU_GFX_TCX_FIFO_ACKB4, 3248 AMDGPU_GFX_TCX_FIFO_ACKB5, 3249 AMDGPU_GFX_TCX_FIFO_ACKB6, 3250 AMDGPU_GFX_TCX_FIFO_ACKB7, 3251 AMDGPU_GFX_TCX_FIFO_ACKD0, 3252 AMDGPU_GFX_TCX_FIFO_ACKD1, 3253 AMDGPU_GFX_TCX_FIFO_ACKD2, 3254 AMDGPU_GFX_TCX_FIFO_ACKD3, 3255 AMDGPU_GFX_TCX_FIFO_ACKD4, 3256 AMDGPU_GFX_TCX_FIFO_ACKD5, 3257 AMDGPU_GFX_TCX_FIFO_ACKD6, 3258 AMDGPU_GFX_TCX_FIFO_ACKD7, 3259 AMDGPU_GFX_TCX_DST_FIFOA0, 3260 AMDGPU_GFX_TCX_DST_FIFOA1, 3261 AMDGPU_GFX_TCX_DST_FIFOA2, 3262 AMDGPU_GFX_TCX_DST_FIFOA3, 3263 AMDGPU_GFX_TCX_DST_FIFOA4, 3264 AMDGPU_GFX_TCX_DST_FIFOA5, 3265 AMDGPU_GFX_TCX_DST_FIFOA6, 3266 AMDGPU_GFX_TCX_DST_FIFOA7, 3267 AMDGPU_GFX_TCX_DST_FIFOB0, 3268 AMDGPU_GFX_TCX_DST_FIFOB1, 3269 AMDGPU_GFX_TCX_DST_FIFOB2, 3270 AMDGPU_GFX_TCX_DST_FIFOB3, 3271 AMDGPU_GFX_TCX_DST_FIFOB4, 3272 AMDGPU_GFX_TCX_DST_FIFOB5, 3273 AMDGPU_GFX_TCX_DST_FIFOB6, 3274 AMDGPU_GFX_TCX_DST_FIFOB7, 3275 AMDGPU_GFX_TCX_DST_FIFOD0, 3276 AMDGPU_GFX_TCX_DST_FIFOD1, 3277 AMDGPU_GFX_TCX_DST_FIFOD2, 3278 AMDGPU_GFX_TCX_DST_FIFOD3, 3279 AMDGPU_GFX_TCX_DST_FIFOD4, 3280 AMDGPU_GFX_TCX_DST_FIFOD5, 3281 AMDGPU_GFX_TCX_DST_FIFOD6, 3282 AMDGPU_GFX_TCX_DST_FIFOD7, 3283 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3284 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3285 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3286 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3287 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3288 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3289 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3290 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3291 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3292 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3293 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3294 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3295 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3296 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3297 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3298 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3299 }; 3300 3301 enum amdgpu_gfx_atc_l2_ras_mem_id { 3302 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3303 }; 3304 3305 enum amdgpu_gfx_utcl2_ras_mem_id { 3306 AMDGPU_GFX_UTCL2_MEM0 = 0, 3307 }; 3308 3309 enum amdgpu_gfx_vml2_ras_mem_id { 3310 AMDGPU_GFX_VML2_MEM0 = 0, 3311 }; 3312 3313 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3314 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3315 }; 3316 3317 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3318 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3319 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3320 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3321 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3322 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3323 }; 3324 3325 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3326 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3327 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3328 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3329 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3330 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3331 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3332 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3333 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3334 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3335 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3336 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3337 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3338 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3339 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3340 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3341 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3342 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3343 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3344 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3345 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3346 }; 3347 3348 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3349 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3350 }; 3351 3352 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3353 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3354 }; 3355 3356 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3357 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3358 }; 3359 3360 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3361 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3362 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3363 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3364 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3365 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3366 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3367 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3368 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3369 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3370 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3371 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3372 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3373 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3374 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3375 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3376 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3377 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3378 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3379 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3380 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3381 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3382 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3383 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3384 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3385 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3386 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3387 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3388 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3389 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3390 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3391 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3392 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3393 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3394 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3395 }; 3396 3397 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3398 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3399 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3400 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3401 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3402 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3403 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3404 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3405 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3406 }; 3407 3408 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3409 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3410 }; 3411 3412 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3413 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3414 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3415 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3416 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3417 }; 3418 3419 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3420 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3421 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3422 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3423 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3424 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3425 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3426 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3427 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3428 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3429 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3430 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3431 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3432 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3433 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3434 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3435 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3436 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3437 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3438 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3439 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3440 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3441 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3442 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3443 }; 3444 3445 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3446 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3447 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3448 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3449 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3450 }; 3451 3452 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3453 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3454 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3455 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3456 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3457 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3458 }; 3459 3460 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3461 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3462 }; 3463 3464 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3465 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3466 }; 3467 3468 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3469 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3470 }; 3471 3472 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3473 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3474 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3475 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3476 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3477 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3478 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3479 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3480 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3481 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3482 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3483 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3484 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3485 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3486 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3487 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3488 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3489 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3490 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3491 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3492 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3493 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3494 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3495 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3496 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3497 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3498 }; 3499 3500 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3501 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3502 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3503 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3504 }; 3505 3506 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3507 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3508 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3509 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3510 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3511 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3512 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3513 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3514 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3515 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3516 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3517 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3518 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3519 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3520 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3521 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3522 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3523 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3524 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3525 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3526 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3527 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3528 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3529 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3530 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3531 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3532 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3533 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3534 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3535 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3536 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3537 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3538 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3539 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3540 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3541 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3542 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3543 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3544 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3545 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3546 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3547 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3548 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3549 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3550 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3551 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3552 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3553 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3554 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3555 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3556 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3557 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3558 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3559 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3560 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3561 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3562 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3563 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3564 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3565 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3566 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3567 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3568 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3569 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3570 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3571 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3572 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3573 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3574 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3575 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3576 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3577 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3578 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3587 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3588 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3589 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3590 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3591 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3592 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3593 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3594 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3595 }; 3596 3597 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3598 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3599 }; 3600 3601 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3602 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3603 }; 3604 3605 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3606 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3607 }; 3608 3609 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3610 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3611 }; 3612 3613 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3628 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3629 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3630 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3631 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3632 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3633 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3634 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3635 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3636 }; 3637 3638 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3639 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3640 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3641 AMDGPU_GFX_RLC_MEM, 1}, 3642 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3643 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3644 AMDGPU_GFX_CP_MEM, 1}, 3645 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3646 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3647 AMDGPU_GFX_CP_MEM, 1}, 3648 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3649 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3650 AMDGPU_GFX_CP_MEM, 1}, 3651 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3652 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3653 AMDGPU_GFX_GDS_MEM, 1}, 3654 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3655 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3656 AMDGPU_GFX_GC_CANE_MEM, 1}, 3657 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3658 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3659 AMDGPU_GFX_SPI_MEM, 8}, 3660 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3661 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3662 AMDGPU_GFX_SP_MEM, 1}, 3663 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3664 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3665 AMDGPU_GFX_SP_MEM, 1}, 3666 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3667 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3668 AMDGPU_GFX_SQ_MEM, 8}, 3669 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3670 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3671 AMDGPU_GFX_SQC_MEM, 8}, 3672 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3673 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3674 AMDGPU_GFX_TCX_MEM, 1}, 3675 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3676 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3677 AMDGPU_GFX_TCC_MEM, 1}, 3678 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3679 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3680 AMDGPU_GFX_TA_MEM, 8}, 3681 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3682 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3683 AMDGPU_GFX_TCI_MEM, 1}, 3684 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3685 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3686 AMDGPU_GFX_TCP_MEM, 8}, 3687 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3688 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3689 AMDGPU_GFX_TD_MEM, 8}, 3690 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3691 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3692 AMDGPU_GFX_GCEA_MEM, 1}, 3693 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3694 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3695 AMDGPU_GFX_LDS_MEM, 1}, 3696 }; 3697 3698 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3699 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3700 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3701 AMDGPU_GFX_RLC_MEM, 1}, 3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3703 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3704 AMDGPU_GFX_CP_MEM, 1}, 3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3706 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3707 AMDGPU_GFX_CP_MEM, 1}, 3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3709 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3710 AMDGPU_GFX_CP_MEM, 1}, 3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3712 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3713 AMDGPU_GFX_GDS_MEM, 1}, 3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3715 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3716 AMDGPU_GFX_GC_CANE_MEM, 1}, 3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3718 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3719 AMDGPU_GFX_SPI_MEM, 8}, 3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3721 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3722 AMDGPU_GFX_SP_MEM, 1}, 3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3724 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3725 AMDGPU_GFX_SP_MEM, 1}, 3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3727 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3728 AMDGPU_GFX_SQ_MEM, 8}, 3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3730 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3731 AMDGPU_GFX_SQC_MEM, 8}, 3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3733 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3734 AMDGPU_GFX_TCX_MEM, 1}, 3735 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3736 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3737 AMDGPU_GFX_TCC_MEM, 1}, 3738 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3739 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3740 AMDGPU_GFX_TA_MEM, 8}, 3741 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3742 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3743 AMDGPU_GFX_TCI_MEM, 1}, 3744 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3745 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3746 AMDGPU_GFX_TCP_MEM, 8}, 3747 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3748 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3749 AMDGPU_GFX_TD_MEM, 8}, 3750 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3751 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3752 AMDGPU_GFX_TCA_MEM, 1}, 3753 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3754 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3755 AMDGPU_GFX_GCEA_MEM, 1}, 3756 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3757 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3758 AMDGPU_GFX_LDS_MEM, 1}, 3759 }; 3760 3761 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3762 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3763 }; 3764 3765 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3766 void *ras_error_status, int xcc_id) 3767 { 3768 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3769 unsigned long ce_count = 0, ue_count = 0; 3770 uint32_t i, j, k; 3771 3772 mutex_lock(&adev->grbm_idx_mutex); 3773 3774 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3775 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3776 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3777 /* no need to select if instance number is 1 */ 3778 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3779 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3780 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3781 3782 amdgpu_ras_inst_query_ras_error_count(adev, 3783 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3784 1, 3785 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3786 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3787 GET_INST(GC, xcc_id), 3788 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3789 &ce_count); 3790 3791 amdgpu_ras_inst_query_ras_error_count(adev, 3792 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3793 1, 3794 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3795 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3796 GET_INST(GC, xcc_id), 3797 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3798 &ue_count); 3799 } 3800 } 3801 } 3802 3803 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3804 xcc_id); 3805 mutex_unlock(&adev->grbm_idx_mutex); 3806 3807 /* the caller should make sure initialize value of 3808 * err_data->ue_count and err_data->ce_count 3809 */ 3810 err_data->ce_count += ce_count; 3811 err_data->ue_count += ue_count; 3812 } 3813 3814 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3815 void *ras_error_status, int xcc_id) 3816 { 3817 uint32_t i, j, k; 3818 3819 mutex_lock(&adev->grbm_idx_mutex); 3820 3821 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3822 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3823 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3824 /* no need to select if instance number is 1 */ 3825 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3826 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3827 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3828 3829 amdgpu_ras_inst_reset_ras_error_count(adev, 3830 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3831 1, 3832 GET_INST(GC, xcc_id)); 3833 3834 amdgpu_ras_inst_reset_ras_error_count(adev, 3835 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3836 1, 3837 GET_INST(GC, xcc_id)); 3838 } 3839 } 3840 } 3841 3842 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3843 xcc_id); 3844 mutex_unlock(&adev->grbm_idx_mutex); 3845 } 3846 3847 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3848 int xcc_id) 3849 { 3850 uint32_t i, j; 3851 uint32_t reg_value; 3852 3853 mutex_lock(&adev->grbm_idx_mutex); 3854 3855 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3856 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3857 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3858 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3859 regGCEA_ERR_STATUS); 3860 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3861 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3862 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3863 dev_warn(adev->dev, 3864 "GCEA err detected at instance: %d, status: 0x%x!\n", 3865 j, reg_value); 3866 } 3867 /* clear after read */ 3868 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3869 CLEAR_ERROR_STATUS, 0x1); 3870 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3871 reg_value); 3872 } 3873 } 3874 3875 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3876 xcc_id); 3877 mutex_unlock(&adev->grbm_idx_mutex); 3878 } 3879 3880 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3881 int xcc_id) 3882 { 3883 uint32_t data; 3884 3885 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3886 if (data) { 3887 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3888 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3889 } 3890 3891 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3892 if (data) { 3893 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3894 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3895 } 3896 3897 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3898 regVML2_WALKER_MEM_ECC_STATUS); 3899 if (data) { 3900 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3901 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3902 0x3); 3903 } 3904 } 3905 3906 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3907 uint32_t status, int xcc_id) 3908 { 3909 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3910 uint32_t i, simd, wave; 3911 uint32_t wave_status; 3912 uint32_t wave_pc_lo, wave_pc_hi; 3913 uint32_t wave_exec_lo, wave_exec_hi; 3914 uint32_t wave_inst_dw0, wave_inst_dw1; 3915 uint32_t wave_ib_sts; 3916 3917 for (i = 0; i < 32; i++) { 3918 if (!((i << 1) & status)) 3919 continue; 3920 3921 simd = i / cu_info->max_waves_per_simd; 3922 wave = i % cu_info->max_waves_per_simd; 3923 3924 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3925 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3926 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3927 wave_exec_lo = 3928 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3929 wave_exec_hi = 3930 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3931 wave_inst_dw0 = 3932 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3933 wave_inst_dw1 = 3934 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3935 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3936 3937 dev_info( 3938 adev->dev, 3939 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3940 simd, wave, wave_status, 3941 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3942 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3943 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3944 wave_ib_sts); 3945 } 3946 } 3947 3948 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3949 int xcc_id) 3950 { 3951 uint32_t se_idx, sh_idx, cu_idx; 3952 uint32_t status; 3953 3954 mutex_lock(&adev->grbm_idx_mutex); 3955 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3956 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3957 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3958 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3959 cu_idx, xcc_id); 3960 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3961 regSQ_TIMEOUT_STATUS); 3962 if (status != 0) { 3963 dev_info( 3964 adev->dev, 3965 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3966 se_idx, sh_idx, cu_idx); 3967 gfx_v9_4_3_log_cu_timeout_status( 3968 adev, status, xcc_id); 3969 } 3970 /* clear old status */ 3971 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3972 regSQ_TIMEOUT_STATUS, 0); 3973 } 3974 } 3975 } 3976 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3977 xcc_id); 3978 mutex_unlock(&adev->grbm_idx_mutex); 3979 } 3980 3981 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3982 void *ras_error_status, int xcc_id) 3983 { 3984 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3985 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3986 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3987 } 3988 3989 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3990 int xcc_id) 3991 { 3992 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3993 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3994 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3995 } 3996 3997 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3998 int xcc_id) 3999 { 4000 uint32_t i, j; 4001 uint32_t value; 4002 4003 mutex_lock(&adev->grbm_idx_mutex); 4004 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 4005 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 4006 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 4007 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 4008 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 4009 CLEAR_ERROR_STATUS, 0x1); 4010 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 4011 } 4012 } 4013 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4014 xcc_id); 4015 mutex_unlock(&adev->grbm_idx_mutex); 4016 } 4017 4018 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 4019 int xcc_id) 4020 { 4021 uint32_t se_idx, sh_idx, cu_idx; 4022 4023 mutex_lock(&adev->grbm_idx_mutex); 4024 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 4025 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 4026 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 4027 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 4028 cu_idx, xcc_id); 4029 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4030 regSQ_TIMEOUT_STATUS, 0); 4031 } 4032 } 4033 } 4034 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4035 xcc_id); 4036 mutex_unlock(&adev->grbm_idx_mutex); 4037 } 4038 4039 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4040 void *ras_error_status, int xcc_id) 4041 { 4042 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4043 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4044 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4045 } 4046 4047 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4048 void *ras_error_status, int xcc_id) 4049 { 4050 uint32_t i; 4051 uint32_t data; 4052 4053 data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4054 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4055 4056 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4057 (amdgpu_watchdog_timer.period < 1 || 4058 amdgpu_watchdog_timer.period > 0x23)) { 4059 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4060 amdgpu_watchdog_timer.period = 0x23; 4061 } 4062 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4063 amdgpu_watchdog_timer.period); 4064 4065 mutex_lock(&adev->grbm_idx_mutex); 4066 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4067 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4068 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4069 } 4070 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4071 xcc_id); 4072 mutex_unlock(&adev->grbm_idx_mutex); 4073 } 4074 4075 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4076 void *ras_error_status) 4077 { 4078 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4079 gfx_v9_4_3_inst_query_ras_err_count); 4080 } 4081 4082 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4083 { 4084 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4085 } 4086 4087 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4088 { 4089 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4090 } 4091 4092 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4093 { 4094 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4095 } 4096 4097 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4098 { 4099 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4100 } 4101 4102 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4103 .name = "gfx_v9_4_3", 4104 .early_init = gfx_v9_4_3_early_init, 4105 .late_init = gfx_v9_4_3_late_init, 4106 .sw_init = gfx_v9_4_3_sw_init, 4107 .sw_fini = gfx_v9_4_3_sw_fini, 4108 .hw_init = gfx_v9_4_3_hw_init, 4109 .hw_fini = gfx_v9_4_3_hw_fini, 4110 .suspend = gfx_v9_4_3_suspend, 4111 .resume = gfx_v9_4_3_resume, 4112 .is_idle = gfx_v9_4_3_is_idle, 4113 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4114 .soft_reset = gfx_v9_4_3_soft_reset, 4115 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4116 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4117 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4118 }; 4119 4120 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4121 .type = AMDGPU_RING_TYPE_COMPUTE, 4122 .align_mask = 0xff, 4123 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4124 .support_64bit_ptrs = true, 4125 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4126 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4127 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4128 .emit_frame_size = 4129 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4130 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4131 5 + /* hdp invalidate */ 4132 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4133 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4134 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4135 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4136 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4137 7 + /* gfx_v9_4_3_emit_mem_sync */ 4138 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4139 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4140 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4141 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4142 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4143 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4144 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4145 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4146 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4147 .test_ring = gfx_v9_4_3_ring_test_ring, 4148 .test_ib = gfx_v9_4_3_ring_test_ib, 4149 .insert_nop = amdgpu_ring_insert_nop, 4150 .pad_ib = amdgpu_ring_generic_pad_ib, 4151 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4152 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4153 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4154 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4155 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4156 }; 4157 4158 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4159 .type = AMDGPU_RING_TYPE_KIQ, 4160 .align_mask = 0xff, 4161 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4162 .support_64bit_ptrs = true, 4163 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4164 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4165 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4166 .emit_frame_size = 4167 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4168 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4169 5 + /* hdp invalidate */ 4170 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4171 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4172 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4173 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4174 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4175 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4176 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4177 .test_ring = gfx_v9_4_3_ring_test_ring, 4178 .insert_nop = amdgpu_ring_insert_nop, 4179 .pad_ib = amdgpu_ring_generic_pad_ib, 4180 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4181 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4182 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4183 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4184 }; 4185 4186 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4187 { 4188 int i, j, num_xcc; 4189 4190 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4191 for (i = 0; i < num_xcc; i++) { 4192 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4193 4194 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4195 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4196 = &gfx_v9_4_3_ring_funcs_compute; 4197 } 4198 } 4199 4200 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4201 .set = gfx_v9_4_3_set_eop_interrupt_state, 4202 .process = gfx_v9_4_3_eop_irq, 4203 }; 4204 4205 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4206 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4207 .process = gfx_v9_4_3_priv_reg_irq, 4208 }; 4209 4210 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4211 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4212 .process = gfx_v9_4_3_priv_inst_irq, 4213 }; 4214 4215 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4216 { 4217 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4218 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4219 4220 adev->gfx.priv_reg_irq.num_types = 1; 4221 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4222 4223 adev->gfx.priv_inst_irq.num_types = 1; 4224 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4225 } 4226 4227 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4228 { 4229 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4230 } 4231 4232 4233 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4234 { 4235 /* init asci gds info */ 4236 switch (adev->ip_versions[GC_HWIP][0]) { 4237 case IP_VERSION(9, 4, 3): 4238 /* 9.4.3 removed all the GDS internal memory, 4239 * only support GWS opcode in kernel, like barrier 4240 * semaphore.etc */ 4241 adev->gds.gds_size = 0; 4242 break; 4243 default: 4244 adev->gds.gds_size = 0x10000; 4245 break; 4246 } 4247 4248 switch (adev->ip_versions[GC_HWIP][0]) { 4249 case IP_VERSION(9, 4, 3): 4250 /* deprecated for 9.4.3, no usage at all */ 4251 adev->gds.gds_compute_max_wave_id = 0; 4252 break; 4253 default: 4254 /* this really depends on the chip */ 4255 adev->gds.gds_compute_max_wave_id = 0x7ff; 4256 break; 4257 } 4258 4259 adev->gds.gws_size = 64; 4260 adev->gds.oa_size = 16; 4261 } 4262 4263 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4264 u32 bitmap) 4265 { 4266 u32 data; 4267 4268 if (!bitmap) 4269 return; 4270 4271 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4272 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4273 4274 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4275 } 4276 4277 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4278 { 4279 u32 data, mask; 4280 4281 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4282 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4283 4284 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4285 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4286 4287 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4288 4289 return (~data) & mask; 4290 } 4291 4292 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4293 struct amdgpu_cu_info *cu_info) 4294 { 4295 int i, j, k, counter, active_cu_number = 0; 4296 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4297 unsigned disable_masks[4 * 4]; 4298 4299 if (!adev || !cu_info) 4300 return -EINVAL; 4301 4302 /* 4303 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4304 */ 4305 if (adev->gfx.config.max_shader_engines * 4306 adev->gfx.config.max_sh_per_se > 16) 4307 return -EINVAL; 4308 4309 amdgpu_gfx_parse_disable_cu(disable_masks, 4310 adev->gfx.config.max_shader_engines, 4311 adev->gfx.config.max_sh_per_se); 4312 4313 mutex_lock(&adev->grbm_idx_mutex); 4314 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4315 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4316 mask = 1; 4317 ao_bitmap = 0; 4318 counter = 0; 4319 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4320 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4321 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4322 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4323 4324 /* 4325 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4326 * 4x4 size array, and it's usually suitable for Vega 4327 * ASICs which has 4*2 SE/SH layout. 4328 * But for Arcturus, SE/SH layout is changed to 8*1. 4329 * To mostly reduce the impact, we make it compatible 4330 * with current bitmap array as below: 4331 * SE4,SH0 --> bitmap[0][1] 4332 * SE5,SH0 --> bitmap[1][1] 4333 * SE6,SH0 --> bitmap[2][1] 4334 * SE7,SH0 --> bitmap[3][1] 4335 */ 4336 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4337 4338 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4339 if (bitmap & mask) { 4340 if (counter < adev->gfx.config.max_cu_per_sh) 4341 ao_bitmap |= mask; 4342 counter++; 4343 } 4344 mask <<= 1; 4345 } 4346 active_cu_number += counter; 4347 if (i < 2 && j < 2) 4348 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4349 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4350 } 4351 } 4352 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4353 0); 4354 mutex_unlock(&adev->grbm_idx_mutex); 4355 4356 cu_info->number = active_cu_number; 4357 cu_info->ao_cu_mask = ao_cu_mask; 4358 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4359 4360 return 0; 4361 } 4362 4363 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4364 .type = AMD_IP_BLOCK_TYPE_GFX, 4365 .major = 9, 4366 .minor = 4, 4367 .rev = 0, 4368 .funcs = &gfx_v9_4_3_ip_funcs, 4369 }; 4370 4371 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4372 { 4373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4374 uint32_t tmp_mask; 4375 int i, r; 4376 4377 /* TODO : Initialize golden regs */ 4378 /* gfx_v9_4_3_init_golden_registers(adev); */ 4379 4380 tmp_mask = inst_mask; 4381 for_each_inst(i, tmp_mask) 4382 gfx_v9_4_3_xcc_constants_init(adev, i); 4383 4384 if (!amdgpu_sriov_vf(adev)) { 4385 tmp_mask = inst_mask; 4386 for_each_inst(i, tmp_mask) { 4387 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4388 if (r) 4389 return r; 4390 } 4391 } 4392 4393 tmp_mask = inst_mask; 4394 for_each_inst(i, tmp_mask) { 4395 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4396 if (r) 4397 return r; 4398 } 4399 4400 return 0; 4401 } 4402 4403 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4404 { 4405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4406 int i; 4407 4408 for_each_inst(i, inst_mask) 4409 gfx_v9_4_3_xcc_fini(adev, i); 4410 4411 return 0; 4412 } 4413 4414 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4415 .suspend = &gfx_v9_4_3_xcp_suspend, 4416 .resume = &gfx_v9_4_3_xcp_resume 4417 }; 4418 4419 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4420 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4421 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4422 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4423 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4424 }; 4425 4426 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4427 .ras_block = { 4428 .hw_ops = &gfx_v9_4_3_ras_ops, 4429 }, 4430 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4431 }; 4432