1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 #include "hdp/hdp_4_0_offset.h" 42 43 #include "soc15_common.h" 44 #include "clearstate_gfx9.h" 45 #include "v9_structs.h" 46 47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 48 49 #include "amdgpu_ras.h" 50 51 #include "gfx_v9_4.h" 52 53 #define GFX9_NUM_GFX_RINGS 1 54 #define GFX9_MEC_HPD_SIZE 4096 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 57 58 #define mmPWR_MISC_CNTL_STATUS 0x0183 59 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 60 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 61 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 62 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 63 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin"); 114 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 115 116 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 120 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin"); 121 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 122 123 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 124 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 125 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 126 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 127 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 128 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 129 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 130 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 131 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 132 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 133 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 134 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 135 136 enum ta_ras_gfx_subblock { 137 /*CPC*/ 138 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 139 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 140 TA_RAS_BLOCK__GFX_CPC_UCODE, 141 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 142 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 143 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 144 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 145 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 146 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 147 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 148 /* CPF*/ 149 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 150 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 151 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 152 TA_RAS_BLOCK__GFX_CPF_TAG, 153 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 154 /* CPG*/ 155 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 156 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 157 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 158 TA_RAS_BLOCK__GFX_CPG_TAG, 159 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 160 /* GDS*/ 161 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 162 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 163 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 164 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 165 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 166 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 167 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 168 /* SPI*/ 169 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 170 /* SQ*/ 171 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 172 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 173 TA_RAS_BLOCK__GFX_SQ_LDS_D, 174 TA_RAS_BLOCK__GFX_SQ_LDS_I, 175 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 176 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 177 /* SQC (3 ranges)*/ 178 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 179 /* SQC range 0*/ 180 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 181 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 182 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 183 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 184 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 185 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 186 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 187 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 188 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 189 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 190 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 191 /* SQC range 1*/ 192 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 193 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 194 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 195 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 196 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 197 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 198 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 199 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 200 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 201 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 202 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 203 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 204 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 205 /* SQC range 2*/ 206 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 207 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 208 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 210 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 212 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 217 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 219 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 220 /* TA*/ 221 TA_RAS_BLOCK__GFX_TA_INDEX_START, 222 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 223 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 224 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 225 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 226 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 227 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 228 /* TCA*/ 229 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 230 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 231 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 232 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 233 /* TCC (5 sub-ranges)*/ 234 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 235 /* TCC range 0*/ 236 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 237 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 238 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 239 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 240 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 241 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 242 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 243 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 244 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 245 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 246 /* TCC range 1*/ 247 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 248 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 249 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 250 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 251 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 252 /* TCC range 2*/ 253 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 254 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 255 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 256 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 257 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 258 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 259 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 260 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 261 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 262 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 263 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 264 /* TCC range 3*/ 265 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 266 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 267 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 268 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 269 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 270 /* TCC range 4*/ 271 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 272 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 273 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 274 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 275 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 276 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 277 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 278 /* TCI*/ 279 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 280 /* TCP*/ 281 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 282 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 283 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 284 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 285 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 286 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 287 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 288 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 289 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 290 /* TD*/ 291 TA_RAS_BLOCK__GFX_TD_INDEX_START, 292 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 293 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 294 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 295 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 296 /* EA (3 sub-ranges)*/ 297 TA_RAS_BLOCK__GFX_EA_INDEX_START, 298 /* EA range 0*/ 299 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 300 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 301 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 302 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 303 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 304 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 305 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 306 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 307 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 308 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 309 /* EA range 1*/ 310 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 311 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 312 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 313 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 314 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 315 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 316 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 317 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 318 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 319 /* EA range 2*/ 320 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 321 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 322 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 323 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 324 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 325 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 326 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 327 /* UTC VM L2 bank*/ 328 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 329 /* UTC VM walker*/ 330 TA_RAS_BLOCK__UTC_VML2_WALKER, 331 /* UTC ATC L2 2MB cache*/ 332 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 333 /* UTC ATC L2 4KB cache*/ 334 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 335 TA_RAS_BLOCK__GFX_MAX 336 }; 337 338 struct ras_gfx_subblock { 339 unsigned char *name; 340 int ta_subblock; 341 int hw_supported_error_type; 342 int sw_supported_error_type; 343 }; 344 345 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 346 [AMDGPU_RAS_BLOCK__##subblock] = { \ 347 #subblock, \ 348 TA_RAS_BLOCK__##subblock, \ 349 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 350 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 351 } 352 353 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 354 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 355 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 356 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 357 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 358 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 359 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 360 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 361 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 362 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 363 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 364 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 365 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 366 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 367 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 368 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 369 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 370 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 371 0), 372 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 373 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 375 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 378 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 379 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 380 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 382 0, 0), 383 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 384 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 386 0, 0), 387 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 388 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 390 0, 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 392 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 394 1), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 396 0, 0, 0), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 398 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 400 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 402 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 404 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 406 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 408 0, 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 410 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 412 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 414 0, 0, 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 416 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 422 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 426 0, 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 430 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 432 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 434 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 436 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 437 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 438 1), 439 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 440 1), 441 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 442 1), 443 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 446 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 448 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 459 0), 460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 462 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 464 0, 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 466 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 468 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 478 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 479 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 480 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 485 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 501 }; 502 503 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 504 { 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 525 }; 526 527 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 528 { 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 547 }; 548 549 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 550 { 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 562 }; 563 564 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 565 { 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 590 }; 591 592 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 593 { 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 601 }; 602 603 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 604 { 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 624 }; 625 626 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 627 { 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 640 }; 641 642 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 643 { 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 647 }; 648 649 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 650 { 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 667 }; 668 669 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 670 { 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 684 }; 685 686 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 687 { 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 698 }; 699 700 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 701 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 702 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 703 }; 704 705 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 706 { 707 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 708 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 709 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 710 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 711 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 712 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 713 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 714 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 715 }; 716 717 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 718 { 719 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 720 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 721 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 722 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 723 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 724 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 725 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 726 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 727 }; 728 729 void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 730 { 731 static void *scratch_reg0; 732 static void *scratch_reg1; 733 static void *scratch_reg2; 734 static void *scratch_reg3; 735 static void *spare_int; 736 static uint32_t grbm_cntl; 737 static uint32_t grbm_idx; 738 739 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 740 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 741 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 742 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 743 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 744 745 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 746 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 747 748 if (amdgpu_sriov_runtime(adev)) { 749 pr_err("shouldn't call rlcg write register during runtime\n"); 750 return; 751 } 752 753 if (offset == grbm_cntl || offset == grbm_idx) { 754 if (offset == grbm_cntl) 755 writel(v, scratch_reg2); 756 else if (offset == grbm_idx) 757 writel(v, scratch_reg3); 758 759 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 760 } else { 761 uint32_t i = 0; 762 uint32_t retries = 50000; 763 764 writel(v, scratch_reg0); 765 writel(offset | 0x80000000, scratch_reg1); 766 writel(1, spare_int); 767 for (i = 0; i < retries; i++) { 768 u32 tmp; 769 770 tmp = readl(scratch_reg1); 771 if (!(tmp & 0x80000000)) 772 break; 773 774 udelay(10); 775 } 776 if (i >= retries) 777 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 778 } 779 780 } 781 782 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 783 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 784 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 785 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 786 787 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 788 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 789 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 790 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 791 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 792 struct amdgpu_cu_info *cu_info); 793 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 794 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 795 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 796 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 797 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 798 void *ras_error_status); 799 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 800 void *inject_if); 801 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 802 803 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 804 uint64_t queue_mask) 805 { 806 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 807 amdgpu_ring_write(kiq_ring, 808 PACKET3_SET_RESOURCES_VMID_MASK(0) | 809 /* vmid_mask:0* queue_type:0 (KIQ) */ 810 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 811 amdgpu_ring_write(kiq_ring, 812 lower_32_bits(queue_mask)); /* queue mask lo */ 813 amdgpu_ring_write(kiq_ring, 814 upper_32_bits(queue_mask)); /* queue mask hi */ 815 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 816 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 817 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 818 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 819 } 820 821 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 822 struct amdgpu_ring *ring) 823 { 824 struct amdgpu_device *adev = kiq_ring->adev; 825 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 826 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 827 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 828 829 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 830 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 831 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 832 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 833 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 834 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 835 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 836 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 837 /*queue_type: normal compute queue */ 838 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 839 /* alloc format: all_on_one_pipe */ 840 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 841 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 842 /* num_queues: must be 1 */ 843 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 844 amdgpu_ring_write(kiq_ring, 845 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 846 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 847 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 848 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 849 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 850 } 851 852 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 853 struct amdgpu_ring *ring, 854 enum amdgpu_unmap_queues_action action, 855 u64 gpu_addr, u64 seq) 856 { 857 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 858 859 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 860 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 861 PACKET3_UNMAP_QUEUES_ACTION(action) | 862 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 863 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 864 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 865 amdgpu_ring_write(kiq_ring, 866 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 867 868 if (action == PREEMPT_QUEUES_NO_UNMAP) { 869 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 870 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 871 amdgpu_ring_write(kiq_ring, seq); 872 } else { 873 amdgpu_ring_write(kiq_ring, 0); 874 amdgpu_ring_write(kiq_ring, 0); 875 amdgpu_ring_write(kiq_ring, 0); 876 } 877 } 878 879 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 880 struct amdgpu_ring *ring, 881 u64 addr, 882 u64 seq) 883 { 884 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 885 886 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 887 amdgpu_ring_write(kiq_ring, 888 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 889 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 890 PACKET3_QUERY_STATUS_COMMAND(2)); 891 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 892 amdgpu_ring_write(kiq_ring, 893 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 894 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 895 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 896 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 897 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 898 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 899 } 900 901 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 902 uint16_t pasid, uint32_t flush_type, 903 bool all_hub) 904 { 905 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 906 amdgpu_ring_write(kiq_ring, 907 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 908 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 909 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 910 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 911 } 912 913 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 914 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 915 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 916 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 917 .kiq_query_status = gfx_v9_0_kiq_query_status, 918 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 919 .set_resources_size = 8, 920 .map_queues_size = 7, 921 .unmap_queues_size = 6, 922 .query_status_size = 7, 923 .invalidate_tlbs_size = 2, 924 }; 925 926 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 927 { 928 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 929 } 930 931 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 932 { 933 switch (adev->asic_type) { 934 case CHIP_VEGA10: 935 soc15_program_register_sequence(adev, 936 golden_settings_gc_9_0, 937 ARRAY_SIZE(golden_settings_gc_9_0)); 938 soc15_program_register_sequence(adev, 939 golden_settings_gc_9_0_vg10, 940 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 941 break; 942 case CHIP_VEGA12: 943 soc15_program_register_sequence(adev, 944 golden_settings_gc_9_2_1, 945 ARRAY_SIZE(golden_settings_gc_9_2_1)); 946 soc15_program_register_sequence(adev, 947 golden_settings_gc_9_2_1_vg12, 948 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 949 break; 950 case CHIP_VEGA20: 951 soc15_program_register_sequence(adev, 952 golden_settings_gc_9_0, 953 ARRAY_SIZE(golden_settings_gc_9_0)); 954 soc15_program_register_sequence(adev, 955 golden_settings_gc_9_0_vg20, 956 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 957 break; 958 case CHIP_ARCTURUS: 959 soc15_program_register_sequence(adev, 960 golden_settings_gc_9_4_1_arct, 961 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 962 break; 963 case CHIP_RAVEN: 964 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 965 ARRAY_SIZE(golden_settings_gc_9_1)); 966 if (adev->rev_id >= 8) 967 soc15_program_register_sequence(adev, 968 golden_settings_gc_9_1_rv2, 969 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 970 else 971 soc15_program_register_sequence(adev, 972 golden_settings_gc_9_1_rv1, 973 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 974 break; 975 case CHIP_RENOIR: 976 soc15_program_register_sequence(adev, 977 golden_settings_gc_9_1_rn, 978 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 979 return; /* for renoir, don't need common goldensetting */ 980 default: 981 break; 982 } 983 984 if (adev->asic_type != CHIP_ARCTURUS) 985 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 986 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 987 } 988 989 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 990 { 991 adev->gfx.scratch.num_reg = 8; 992 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 993 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 994 } 995 996 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 997 bool wc, uint32_t reg, uint32_t val) 998 { 999 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1000 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 1001 WRITE_DATA_DST_SEL(0) | 1002 (wc ? WR_CONFIRM : 0)); 1003 amdgpu_ring_write(ring, reg); 1004 amdgpu_ring_write(ring, 0); 1005 amdgpu_ring_write(ring, val); 1006 } 1007 1008 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 1009 int mem_space, int opt, uint32_t addr0, 1010 uint32_t addr1, uint32_t ref, uint32_t mask, 1011 uint32_t inv) 1012 { 1013 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1014 amdgpu_ring_write(ring, 1015 /* memory (1) or register (0) */ 1016 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 1017 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 1018 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 1019 WAIT_REG_MEM_ENGINE(eng_sel))); 1020 1021 if (mem_space) 1022 BUG_ON(addr0 & 0x3); /* Dword align */ 1023 amdgpu_ring_write(ring, addr0); 1024 amdgpu_ring_write(ring, addr1); 1025 amdgpu_ring_write(ring, ref); 1026 amdgpu_ring_write(ring, mask); 1027 amdgpu_ring_write(ring, inv); /* poll interval */ 1028 } 1029 1030 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1031 { 1032 struct amdgpu_device *adev = ring->adev; 1033 uint32_t scratch; 1034 uint32_t tmp = 0; 1035 unsigned i; 1036 int r; 1037 1038 r = amdgpu_gfx_scratch_get(adev, &scratch); 1039 if (r) 1040 return r; 1041 1042 WREG32(scratch, 0xCAFEDEAD); 1043 r = amdgpu_ring_alloc(ring, 3); 1044 if (r) 1045 goto error_free_scratch; 1046 1047 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1048 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 1049 amdgpu_ring_write(ring, 0xDEADBEEF); 1050 amdgpu_ring_commit(ring); 1051 1052 for (i = 0; i < adev->usec_timeout; i++) { 1053 tmp = RREG32(scratch); 1054 if (tmp == 0xDEADBEEF) 1055 break; 1056 udelay(1); 1057 } 1058 1059 if (i >= adev->usec_timeout) 1060 r = -ETIMEDOUT; 1061 1062 error_free_scratch: 1063 amdgpu_gfx_scratch_free(adev, scratch); 1064 return r; 1065 } 1066 1067 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1068 { 1069 struct amdgpu_device *adev = ring->adev; 1070 struct amdgpu_ib ib; 1071 struct dma_fence *f = NULL; 1072 1073 unsigned index; 1074 uint64_t gpu_addr; 1075 uint32_t tmp; 1076 long r; 1077 1078 r = amdgpu_device_wb_get(adev, &index); 1079 if (r) 1080 return r; 1081 1082 gpu_addr = adev->wb.gpu_addr + (index * 4); 1083 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1084 memset(&ib, 0, sizeof(ib)); 1085 r = amdgpu_ib_get(adev, NULL, 16, &ib); 1086 if (r) 1087 goto err1; 1088 1089 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1090 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1091 ib.ptr[2] = lower_32_bits(gpu_addr); 1092 ib.ptr[3] = upper_32_bits(gpu_addr); 1093 ib.ptr[4] = 0xDEADBEEF; 1094 ib.length_dw = 5; 1095 1096 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1097 if (r) 1098 goto err2; 1099 1100 r = dma_fence_wait_timeout(f, false, timeout); 1101 if (r == 0) { 1102 r = -ETIMEDOUT; 1103 goto err2; 1104 } else if (r < 0) { 1105 goto err2; 1106 } 1107 1108 tmp = adev->wb.wb[index]; 1109 if (tmp == 0xDEADBEEF) 1110 r = 0; 1111 else 1112 r = -EINVAL; 1113 1114 err2: 1115 amdgpu_ib_free(adev, &ib, NULL); 1116 dma_fence_put(f); 1117 err1: 1118 amdgpu_device_wb_free(adev, index); 1119 return r; 1120 } 1121 1122 1123 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1124 { 1125 release_firmware(adev->gfx.pfp_fw); 1126 adev->gfx.pfp_fw = NULL; 1127 release_firmware(adev->gfx.me_fw); 1128 adev->gfx.me_fw = NULL; 1129 release_firmware(adev->gfx.ce_fw); 1130 adev->gfx.ce_fw = NULL; 1131 release_firmware(adev->gfx.rlc_fw); 1132 adev->gfx.rlc_fw = NULL; 1133 release_firmware(adev->gfx.mec_fw); 1134 adev->gfx.mec_fw = NULL; 1135 release_firmware(adev->gfx.mec2_fw); 1136 adev->gfx.mec2_fw = NULL; 1137 1138 kfree(adev->gfx.rlc.register_list_format); 1139 } 1140 1141 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 1142 { 1143 const struct rlc_firmware_header_v2_1 *rlc_hdr; 1144 1145 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1146 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 1147 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 1148 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 1149 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 1150 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 1151 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 1152 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 1153 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 1154 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 1155 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 1156 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 1157 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 1158 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 1159 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 1160 } 1161 1162 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1163 { 1164 adev->gfx.me_fw_write_wait = false; 1165 adev->gfx.mec_fw_write_wait = false; 1166 1167 if ((adev->asic_type != CHIP_ARCTURUS) && 1168 ((adev->gfx.mec_fw_version < 0x000001a5) || 1169 (adev->gfx.mec_feature_version < 46) || 1170 (adev->gfx.pfp_fw_version < 0x000000b7) || 1171 (adev->gfx.pfp_feature_version < 46))) 1172 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1173 1174 switch (adev->asic_type) { 1175 case CHIP_VEGA10: 1176 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1177 (adev->gfx.me_feature_version >= 42) && 1178 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1179 (adev->gfx.pfp_feature_version >= 42)) 1180 adev->gfx.me_fw_write_wait = true; 1181 1182 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1183 (adev->gfx.mec_feature_version >= 42)) 1184 adev->gfx.mec_fw_write_wait = true; 1185 break; 1186 case CHIP_VEGA12: 1187 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1188 (adev->gfx.me_feature_version >= 44) && 1189 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1190 (adev->gfx.pfp_feature_version >= 44)) 1191 adev->gfx.me_fw_write_wait = true; 1192 1193 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1194 (adev->gfx.mec_feature_version >= 44)) 1195 adev->gfx.mec_fw_write_wait = true; 1196 break; 1197 case CHIP_VEGA20: 1198 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1199 (adev->gfx.me_feature_version >= 44) && 1200 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1201 (adev->gfx.pfp_feature_version >= 44)) 1202 adev->gfx.me_fw_write_wait = true; 1203 1204 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1205 (adev->gfx.mec_feature_version >= 44)) 1206 adev->gfx.mec_fw_write_wait = true; 1207 break; 1208 case CHIP_RAVEN: 1209 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1210 (adev->gfx.me_feature_version >= 42) && 1211 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1212 (adev->gfx.pfp_feature_version >= 42)) 1213 adev->gfx.me_fw_write_wait = true; 1214 1215 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1216 (adev->gfx.mec_feature_version >= 42)) 1217 adev->gfx.mec_fw_write_wait = true; 1218 break; 1219 default: 1220 adev->gfx.me_fw_write_wait = true; 1221 adev->gfx.mec_fw_write_wait = true; 1222 break; 1223 } 1224 } 1225 1226 struct amdgpu_gfxoff_quirk { 1227 u16 chip_vendor; 1228 u16 chip_device; 1229 u16 subsys_vendor; 1230 u16 subsys_device; 1231 u8 revision; 1232 }; 1233 1234 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1235 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1236 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1237 { 0, 0, 0, 0, 0 }, 1238 }; 1239 1240 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1241 { 1242 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1243 1244 while (p && p->chip_device != 0) { 1245 if (pdev->vendor == p->chip_vendor && 1246 pdev->device == p->chip_device && 1247 pdev->subsystem_vendor == p->subsys_vendor && 1248 pdev->subsystem_device == p->subsys_device && 1249 pdev->revision == p->revision) { 1250 return true; 1251 } 1252 ++p; 1253 } 1254 return false; 1255 } 1256 1257 static bool is_raven_kicker(struct amdgpu_device *adev) 1258 { 1259 if (adev->pm.fw_version >= 0x41e2b) 1260 return true; 1261 else 1262 return false; 1263 } 1264 1265 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1266 { 1267 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1268 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1269 1270 switch (adev->asic_type) { 1271 case CHIP_VEGA10: 1272 case CHIP_VEGA12: 1273 case CHIP_VEGA20: 1274 break; 1275 case CHIP_RAVEN: 1276 if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) && 1277 ((!is_raven_kicker(adev) && 1278 adev->gfx.rlc_fw_version < 531) || 1279 (adev->gfx.rlc_feature_version < 1) || 1280 !adev->gfx.rlc.is_rlc_v2_1)) 1281 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1282 1283 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1284 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1285 AMD_PG_SUPPORT_CP | 1286 AMD_PG_SUPPORT_RLC_SMU_HS; 1287 break; 1288 case CHIP_RENOIR: 1289 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1290 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1291 AMD_PG_SUPPORT_CP | 1292 AMD_PG_SUPPORT_RLC_SMU_HS; 1293 break; 1294 default: 1295 break; 1296 } 1297 } 1298 1299 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1300 const char *chip_name) 1301 { 1302 char fw_name[30]; 1303 int err; 1304 struct amdgpu_firmware_info *info = NULL; 1305 const struct common_firmware_header *header = NULL; 1306 const struct gfx_firmware_header_v1_0 *cp_hdr; 1307 1308 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1309 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 1310 if (err) 1311 goto out; 1312 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 1313 if (err) 1314 goto out; 1315 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1316 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1317 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1318 1319 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1320 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 1321 if (err) 1322 goto out; 1323 err = amdgpu_ucode_validate(adev->gfx.me_fw); 1324 if (err) 1325 goto out; 1326 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1327 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1328 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1329 1330 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1331 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 1332 if (err) 1333 goto out; 1334 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 1335 if (err) 1336 goto out; 1337 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1338 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1339 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1340 1341 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1342 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 1343 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 1344 info->fw = adev->gfx.pfp_fw; 1345 header = (const struct common_firmware_header *)info->fw->data; 1346 adev->firmware.fw_size += 1347 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1348 1349 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 1350 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 1351 info->fw = adev->gfx.me_fw; 1352 header = (const struct common_firmware_header *)info->fw->data; 1353 adev->firmware.fw_size += 1354 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1355 1356 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 1357 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 1358 info->fw = adev->gfx.ce_fw; 1359 header = (const struct common_firmware_header *)info->fw->data; 1360 adev->firmware.fw_size += 1361 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1362 } 1363 1364 out: 1365 if (err) { 1366 dev_err(adev->dev, 1367 "gfx9: Failed to load firmware \"%s\"\n", 1368 fw_name); 1369 release_firmware(adev->gfx.pfp_fw); 1370 adev->gfx.pfp_fw = NULL; 1371 release_firmware(adev->gfx.me_fw); 1372 adev->gfx.me_fw = NULL; 1373 release_firmware(adev->gfx.ce_fw); 1374 adev->gfx.ce_fw = NULL; 1375 } 1376 return err; 1377 } 1378 1379 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1380 const char *chip_name) 1381 { 1382 char fw_name[30]; 1383 int err; 1384 struct amdgpu_firmware_info *info = NULL; 1385 const struct common_firmware_header *header = NULL; 1386 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1387 unsigned int *tmp = NULL; 1388 unsigned int i = 0; 1389 uint16_t version_major; 1390 uint16_t version_minor; 1391 uint32_t smu_version; 1392 1393 /* 1394 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1395 * instead of picasso_rlc.bin. 1396 * Judgment method: 1397 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1398 * or revision >= 0xD8 && revision <= 0xDF 1399 * otherwise is PCO FP5 1400 */ 1401 if (!strcmp(chip_name, "picasso") && 1402 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1403 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1404 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1405 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1406 (smu_version >= 0x41e2b)) 1407 /** 1408 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1409 */ 1410 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1411 else 1412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1413 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1414 if (err) 1415 goto out; 1416 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1417 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1418 1419 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1420 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1421 if (version_major == 2 && version_minor == 1) 1422 adev->gfx.rlc.is_rlc_v2_1 = true; 1423 1424 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 1425 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 1426 adev->gfx.rlc.save_and_restore_offset = 1427 le32_to_cpu(rlc_hdr->save_and_restore_offset); 1428 adev->gfx.rlc.clear_state_descriptor_offset = 1429 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 1430 adev->gfx.rlc.avail_scratch_ram_locations = 1431 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 1432 adev->gfx.rlc.reg_restore_list_size = 1433 le32_to_cpu(rlc_hdr->reg_restore_list_size); 1434 adev->gfx.rlc.reg_list_format_start = 1435 le32_to_cpu(rlc_hdr->reg_list_format_start); 1436 adev->gfx.rlc.reg_list_format_separate_start = 1437 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 1438 adev->gfx.rlc.starting_offsets_start = 1439 le32_to_cpu(rlc_hdr->starting_offsets_start); 1440 adev->gfx.rlc.reg_list_format_size_bytes = 1441 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 1442 adev->gfx.rlc.reg_list_size_bytes = 1443 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 1444 adev->gfx.rlc.register_list_format = 1445 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 1446 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 1447 if (!adev->gfx.rlc.register_list_format) { 1448 err = -ENOMEM; 1449 goto out; 1450 } 1451 1452 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1453 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 1454 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 1455 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 1456 1457 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 1458 1459 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1460 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 1461 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 1462 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 1463 1464 if (adev->gfx.rlc.is_rlc_v2_1) 1465 gfx_v9_0_init_rlc_ext_microcode(adev); 1466 1467 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1468 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 1469 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 1470 info->fw = adev->gfx.rlc_fw; 1471 header = (const struct common_firmware_header *)info->fw->data; 1472 adev->firmware.fw_size += 1473 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1474 1475 if (adev->gfx.rlc.is_rlc_v2_1 && 1476 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 1477 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 1478 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 1479 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 1480 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 1481 info->fw = adev->gfx.rlc_fw; 1482 adev->firmware.fw_size += 1483 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 1484 1485 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 1486 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 1487 info->fw = adev->gfx.rlc_fw; 1488 adev->firmware.fw_size += 1489 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 1490 1491 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 1492 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 1493 info->fw = adev->gfx.rlc_fw; 1494 adev->firmware.fw_size += 1495 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 1496 } 1497 } 1498 1499 out: 1500 if (err) { 1501 dev_err(adev->dev, 1502 "gfx9: Failed to load firmware \"%s\"\n", 1503 fw_name); 1504 release_firmware(adev->gfx.rlc_fw); 1505 adev->gfx.rlc_fw = NULL; 1506 } 1507 return err; 1508 } 1509 1510 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1511 const char *chip_name) 1512 { 1513 char fw_name[30]; 1514 int err; 1515 struct amdgpu_firmware_info *info = NULL; 1516 const struct common_firmware_header *header = NULL; 1517 const struct gfx_firmware_header_v1_0 *cp_hdr; 1518 1519 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1520 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1521 if (err) 1522 goto out; 1523 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1524 if (err) 1525 goto out; 1526 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1527 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1528 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1529 1530 1531 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1532 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1533 if (!err) { 1534 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1535 if (err) 1536 goto out; 1537 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1538 adev->gfx.mec2_fw->data; 1539 adev->gfx.mec2_fw_version = 1540 le32_to_cpu(cp_hdr->header.ucode_version); 1541 adev->gfx.mec2_feature_version = 1542 le32_to_cpu(cp_hdr->ucode_feature_version); 1543 } else { 1544 err = 0; 1545 adev->gfx.mec2_fw = NULL; 1546 } 1547 1548 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1549 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 1550 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 1551 info->fw = adev->gfx.mec_fw; 1552 header = (const struct common_firmware_header *)info->fw->data; 1553 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1554 adev->firmware.fw_size += 1555 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1556 1557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 1558 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 1559 info->fw = adev->gfx.mec_fw; 1560 adev->firmware.fw_size += 1561 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1562 1563 if (adev->gfx.mec2_fw) { 1564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 1565 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 1566 info->fw = adev->gfx.mec2_fw; 1567 header = (const struct common_firmware_header *)info->fw->data; 1568 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1569 adev->firmware.fw_size += 1570 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1571 1572 /* TODO: Determine if MEC2 JT FW loading can be removed 1573 for all GFX V9 asic and above */ 1574 if (adev->asic_type != CHIP_ARCTURUS && 1575 adev->asic_type != CHIP_RENOIR) { 1576 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 1577 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 1578 info->fw = adev->gfx.mec2_fw; 1579 adev->firmware.fw_size += 1580 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 1581 PAGE_SIZE); 1582 } 1583 } 1584 } 1585 1586 out: 1587 gfx_v9_0_check_if_need_gfxoff(adev); 1588 gfx_v9_0_check_fw_write_wait(adev); 1589 if (err) { 1590 dev_err(adev->dev, 1591 "gfx9: Failed to load firmware \"%s\"\n", 1592 fw_name); 1593 release_firmware(adev->gfx.mec_fw); 1594 adev->gfx.mec_fw = NULL; 1595 release_firmware(adev->gfx.mec2_fw); 1596 adev->gfx.mec2_fw = NULL; 1597 } 1598 return err; 1599 } 1600 1601 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1602 { 1603 const char *chip_name; 1604 int r; 1605 1606 DRM_DEBUG("\n"); 1607 1608 switch (adev->asic_type) { 1609 case CHIP_VEGA10: 1610 chip_name = "vega10"; 1611 break; 1612 case CHIP_VEGA12: 1613 chip_name = "vega12"; 1614 break; 1615 case CHIP_VEGA20: 1616 chip_name = "vega20"; 1617 break; 1618 case CHIP_RAVEN: 1619 if (adev->rev_id >= 8) 1620 chip_name = "raven2"; 1621 else if (adev->pdev->device == 0x15d8) 1622 chip_name = "picasso"; 1623 else 1624 chip_name = "raven"; 1625 break; 1626 case CHIP_ARCTURUS: 1627 chip_name = "arcturus"; 1628 break; 1629 case CHIP_RENOIR: 1630 chip_name = "renoir"; 1631 break; 1632 default: 1633 BUG(); 1634 } 1635 1636 /* No CPG in Arcturus */ 1637 if (adev->asic_type != CHIP_ARCTURUS) { 1638 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); 1639 if (r) 1640 return r; 1641 } 1642 1643 r = gfx_v9_0_init_rlc_microcode(adev, chip_name); 1644 if (r) 1645 return r; 1646 1647 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); 1648 if (r) 1649 return r; 1650 1651 return r; 1652 } 1653 1654 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1655 { 1656 u32 count = 0; 1657 const struct cs_section_def *sect = NULL; 1658 const struct cs_extent_def *ext = NULL; 1659 1660 /* begin clear state */ 1661 count += 2; 1662 /* context control state */ 1663 count += 3; 1664 1665 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1666 for (ext = sect->section; ext->extent != NULL; ++ext) { 1667 if (sect->id == SECT_CONTEXT) 1668 count += 2 + ext->reg_count; 1669 else 1670 return 0; 1671 } 1672 } 1673 1674 /* end clear state */ 1675 count += 2; 1676 /* clear state */ 1677 count += 2; 1678 1679 return count; 1680 } 1681 1682 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1683 volatile u32 *buffer) 1684 { 1685 u32 count = 0, i; 1686 const struct cs_section_def *sect = NULL; 1687 const struct cs_extent_def *ext = NULL; 1688 1689 if (adev->gfx.rlc.cs_data == NULL) 1690 return; 1691 if (buffer == NULL) 1692 return; 1693 1694 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1695 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1696 1697 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1698 buffer[count++] = cpu_to_le32(0x80000000); 1699 buffer[count++] = cpu_to_le32(0x80000000); 1700 1701 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1702 for (ext = sect->section; ext->extent != NULL; ++ext) { 1703 if (sect->id == SECT_CONTEXT) { 1704 buffer[count++] = 1705 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1706 buffer[count++] = cpu_to_le32(ext->reg_index - 1707 PACKET3_SET_CONTEXT_REG_START); 1708 for (i = 0; i < ext->reg_count; i++) 1709 buffer[count++] = cpu_to_le32(ext->extent[i]); 1710 } else { 1711 return; 1712 } 1713 } 1714 } 1715 1716 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1717 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1718 1719 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1720 buffer[count++] = cpu_to_le32(0); 1721 } 1722 1723 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1724 { 1725 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1726 uint32_t pg_always_on_cu_num = 2; 1727 uint32_t always_on_cu_num; 1728 uint32_t i, j, k; 1729 uint32_t mask, cu_bitmap, counter; 1730 1731 if (adev->flags & AMD_IS_APU) 1732 always_on_cu_num = 4; 1733 else if (adev->asic_type == CHIP_VEGA12) 1734 always_on_cu_num = 8; 1735 else 1736 always_on_cu_num = 12; 1737 1738 mutex_lock(&adev->grbm_idx_mutex); 1739 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1740 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1741 mask = 1; 1742 cu_bitmap = 0; 1743 counter = 0; 1744 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1745 1746 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1747 if (cu_info->bitmap[i][j] & mask) { 1748 if (counter == pg_always_on_cu_num) 1749 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1750 if (counter < always_on_cu_num) 1751 cu_bitmap |= mask; 1752 else 1753 break; 1754 counter++; 1755 } 1756 mask <<= 1; 1757 } 1758 1759 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1760 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1761 } 1762 } 1763 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1764 mutex_unlock(&adev->grbm_idx_mutex); 1765 } 1766 1767 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1768 { 1769 uint32_t data; 1770 1771 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1772 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1773 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1774 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1775 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1776 1777 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1778 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1779 1780 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1781 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1782 1783 mutex_lock(&adev->grbm_idx_mutex); 1784 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1785 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1786 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1787 1788 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1789 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1790 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1791 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1792 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1793 1794 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1795 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1796 data &= 0x0000FFFF; 1797 data |= 0x00C00000; 1798 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1799 1800 /* 1801 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1802 * programmed in gfx_v9_0_init_always_on_cu_mask() 1803 */ 1804 1805 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1806 * but used for RLC_LB_CNTL configuration */ 1807 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1808 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1809 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1810 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1811 mutex_unlock(&adev->grbm_idx_mutex); 1812 1813 gfx_v9_0_init_always_on_cu_mask(adev); 1814 } 1815 1816 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1817 { 1818 uint32_t data; 1819 1820 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1821 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1822 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1823 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1824 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1825 1826 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1827 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1828 1829 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1830 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1831 1832 mutex_lock(&adev->grbm_idx_mutex); 1833 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1834 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1835 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1836 1837 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1838 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1839 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1840 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1841 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1842 1843 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1844 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1845 data &= 0x0000FFFF; 1846 data |= 0x00C00000; 1847 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1848 1849 /* 1850 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1851 * programmed in gfx_v9_0_init_always_on_cu_mask() 1852 */ 1853 1854 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1855 * but used for RLC_LB_CNTL configuration */ 1856 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1857 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1858 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1859 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1860 mutex_unlock(&adev->grbm_idx_mutex); 1861 1862 gfx_v9_0_init_always_on_cu_mask(adev); 1863 } 1864 1865 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1866 { 1867 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1868 } 1869 1870 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1871 { 1872 return 5; 1873 } 1874 1875 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1876 { 1877 const struct cs_section_def *cs_data; 1878 int r; 1879 1880 adev->gfx.rlc.cs_data = gfx9_cs_data; 1881 1882 cs_data = adev->gfx.rlc.cs_data; 1883 1884 if (cs_data) { 1885 /* init clear state block */ 1886 r = amdgpu_gfx_rlc_init_csb(adev); 1887 if (r) 1888 return r; 1889 } 1890 1891 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { 1892 /* TODO: double check the cp_table_size for RV */ 1893 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1894 r = amdgpu_gfx_rlc_init_cpt(adev); 1895 if (r) 1896 return r; 1897 } 1898 1899 switch (adev->asic_type) { 1900 case CHIP_RAVEN: 1901 gfx_v9_0_init_lbpw(adev); 1902 break; 1903 case CHIP_VEGA20: 1904 gfx_v9_4_init_lbpw(adev); 1905 break; 1906 default: 1907 break; 1908 } 1909 1910 /* init spm vmid with 0xf */ 1911 if (adev->gfx.rlc.funcs->update_spm_vmid) 1912 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1913 1914 return 0; 1915 } 1916 1917 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1918 { 1919 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1920 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1921 } 1922 1923 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1924 { 1925 int r; 1926 u32 *hpd; 1927 const __le32 *fw_data; 1928 unsigned fw_size; 1929 u32 *fw; 1930 size_t mec_hpd_size; 1931 1932 const struct gfx_firmware_header_v1_0 *mec_hdr; 1933 1934 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1935 1936 /* take ownership of the relevant compute queues */ 1937 amdgpu_gfx_compute_queue_acquire(adev); 1938 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1939 1940 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1941 AMDGPU_GEM_DOMAIN_VRAM, 1942 &adev->gfx.mec.hpd_eop_obj, 1943 &adev->gfx.mec.hpd_eop_gpu_addr, 1944 (void **)&hpd); 1945 if (r) { 1946 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1947 gfx_v9_0_mec_fini(adev); 1948 return r; 1949 } 1950 1951 memset(hpd, 0, mec_hpd_size); 1952 1953 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1954 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1955 1956 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1957 1958 fw_data = (const __le32 *) 1959 (adev->gfx.mec_fw->data + 1960 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1961 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 1962 1963 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1964 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1965 &adev->gfx.mec.mec_fw_obj, 1966 &adev->gfx.mec.mec_fw_gpu_addr, 1967 (void **)&fw); 1968 if (r) { 1969 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1970 gfx_v9_0_mec_fini(adev); 1971 return r; 1972 } 1973 1974 memcpy(fw, fw_data, fw_size); 1975 1976 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1977 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1978 1979 return 0; 1980 } 1981 1982 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1983 { 1984 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1985 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1986 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1987 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1988 (SQ_IND_INDEX__FORCE_READ_MASK)); 1989 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1990 } 1991 1992 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1993 uint32_t wave, uint32_t thread, 1994 uint32_t regno, uint32_t num, uint32_t *out) 1995 { 1996 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1997 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1998 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1999 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2000 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2001 (SQ_IND_INDEX__FORCE_READ_MASK) | 2002 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2003 while (num--) 2004 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 2005 } 2006 2007 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2008 { 2009 /* type 1 wave data */ 2010 dst[(*no_fields)++] = 1; 2011 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2012 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2013 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2014 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2015 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2016 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2017 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2018 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2019 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2025 } 2026 2027 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 2028 uint32_t wave, uint32_t start, 2029 uint32_t size, uint32_t *dst) 2030 { 2031 wave_read_regs( 2032 adev, simd, wave, 0, 2033 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 2034 } 2035 2036 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 2037 uint32_t wave, uint32_t thread, 2038 uint32_t start, uint32_t size, 2039 uint32_t *dst) 2040 { 2041 wave_read_regs( 2042 adev, simd, wave, thread, 2043 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 2044 } 2045 2046 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 2047 u32 me, u32 pipe, u32 q, u32 vm) 2048 { 2049 soc15_grbm_select(adev, me, pipe, q, vm); 2050 } 2051 2052 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 2053 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2054 .select_se_sh = &gfx_v9_0_select_se_sh, 2055 .read_wave_data = &gfx_v9_0_read_wave_data, 2056 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2057 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2058 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2059 .ras_error_inject = &gfx_v9_0_ras_error_inject, 2060 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 2061 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 2062 }; 2063 2064 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { 2065 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2066 .select_se_sh = &gfx_v9_0_select_se_sh, 2067 .read_wave_data = &gfx_v9_0_read_wave_data, 2068 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2069 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2070 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2071 .ras_error_inject = &gfx_v9_4_ras_error_inject, 2072 .query_ras_error_count = &gfx_v9_4_query_ras_error_count, 2073 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count, 2074 }; 2075 2076 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 2077 { 2078 u32 gb_addr_config; 2079 int err; 2080 2081 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 2082 2083 switch (adev->asic_type) { 2084 case CHIP_VEGA10: 2085 adev->gfx.config.max_hw_contexts = 8; 2086 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2087 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2088 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2089 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2090 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 2091 break; 2092 case CHIP_VEGA12: 2093 adev->gfx.config.max_hw_contexts = 8; 2094 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2095 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2096 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2097 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2098 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 2099 DRM_INFO("fix gfx.config for vega12\n"); 2100 break; 2101 case CHIP_VEGA20: 2102 adev->gfx.config.max_hw_contexts = 8; 2103 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2104 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2105 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2106 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2107 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2108 gb_addr_config &= ~0xf3e777ff; 2109 gb_addr_config |= 0x22014042; 2110 /* check vbios table if gpu info is not available */ 2111 err = amdgpu_atomfirmware_get_gfx_info(adev); 2112 if (err) 2113 return err; 2114 break; 2115 case CHIP_RAVEN: 2116 adev->gfx.config.max_hw_contexts = 8; 2117 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2118 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2119 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2120 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2121 if (adev->rev_id >= 8) 2122 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 2123 else 2124 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 2125 break; 2126 case CHIP_ARCTURUS: 2127 adev->gfx.funcs = &gfx_v9_4_gfx_funcs; 2128 adev->gfx.config.max_hw_contexts = 8; 2129 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2130 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2131 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2132 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2133 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2134 gb_addr_config &= ~0xf3e777ff; 2135 gb_addr_config |= 0x22014042; 2136 break; 2137 case CHIP_RENOIR: 2138 adev->gfx.config.max_hw_contexts = 8; 2139 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2140 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2141 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 2142 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2143 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2144 gb_addr_config &= ~0xf3e777ff; 2145 gb_addr_config |= 0x22010042; 2146 break; 2147 default: 2148 BUG(); 2149 break; 2150 } 2151 2152 adev->gfx.config.gb_addr_config = gb_addr_config; 2153 2154 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2155 REG_GET_FIELD( 2156 adev->gfx.config.gb_addr_config, 2157 GB_ADDR_CONFIG, 2158 NUM_PIPES); 2159 2160 adev->gfx.config.max_tile_pipes = 2161 adev->gfx.config.gb_addr_config_fields.num_pipes; 2162 2163 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2164 REG_GET_FIELD( 2165 adev->gfx.config.gb_addr_config, 2166 GB_ADDR_CONFIG, 2167 NUM_BANKS); 2168 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2169 REG_GET_FIELD( 2170 adev->gfx.config.gb_addr_config, 2171 GB_ADDR_CONFIG, 2172 MAX_COMPRESSED_FRAGS); 2173 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2174 REG_GET_FIELD( 2175 adev->gfx.config.gb_addr_config, 2176 GB_ADDR_CONFIG, 2177 NUM_RB_PER_SE); 2178 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2179 REG_GET_FIELD( 2180 adev->gfx.config.gb_addr_config, 2181 GB_ADDR_CONFIG, 2182 NUM_SHADER_ENGINES); 2183 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2184 REG_GET_FIELD( 2185 adev->gfx.config.gb_addr_config, 2186 GB_ADDR_CONFIG, 2187 PIPE_INTERLEAVE_SIZE)); 2188 2189 return 0; 2190 } 2191 2192 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2193 int mec, int pipe, int queue) 2194 { 2195 int r; 2196 unsigned irq_type; 2197 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2198 2199 ring = &adev->gfx.compute_ring[ring_id]; 2200 2201 /* mec0 is me1 */ 2202 ring->me = mec + 1; 2203 ring->pipe = pipe; 2204 ring->queue = queue; 2205 2206 ring->ring_obj = NULL; 2207 ring->use_doorbell = true; 2208 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2209 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2210 + (ring_id * GFX9_MEC_HPD_SIZE); 2211 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2212 2213 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2214 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2215 + ring->pipe; 2216 2217 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2218 r = amdgpu_ring_init(adev, ring, 1024, 2219 &adev->gfx.eop_irq, irq_type); 2220 if (r) 2221 return r; 2222 2223 2224 return 0; 2225 } 2226 2227 static int gfx_v9_0_sw_init(void *handle) 2228 { 2229 int i, j, k, r, ring_id; 2230 struct amdgpu_ring *ring; 2231 struct amdgpu_kiq *kiq; 2232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2233 2234 switch (adev->asic_type) { 2235 case CHIP_VEGA10: 2236 case CHIP_VEGA12: 2237 case CHIP_VEGA20: 2238 case CHIP_RAVEN: 2239 case CHIP_ARCTURUS: 2240 case CHIP_RENOIR: 2241 adev->gfx.mec.num_mec = 2; 2242 break; 2243 default: 2244 adev->gfx.mec.num_mec = 1; 2245 break; 2246 } 2247 2248 adev->gfx.mec.num_pipe_per_mec = 4; 2249 adev->gfx.mec.num_queue_per_pipe = 8; 2250 2251 /* EOP Event */ 2252 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2253 if (r) 2254 return r; 2255 2256 /* Privileged reg */ 2257 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2258 &adev->gfx.priv_reg_irq); 2259 if (r) 2260 return r; 2261 2262 /* Privileged inst */ 2263 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2264 &adev->gfx.priv_inst_irq); 2265 if (r) 2266 return r; 2267 2268 /* ECC error */ 2269 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2270 &adev->gfx.cp_ecc_error_irq); 2271 if (r) 2272 return r; 2273 2274 /* FUE error */ 2275 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2276 &adev->gfx.cp_ecc_error_irq); 2277 if (r) 2278 return r; 2279 2280 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2281 2282 gfx_v9_0_scratch_init(adev); 2283 2284 r = gfx_v9_0_init_microcode(adev); 2285 if (r) { 2286 DRM_ERROR("Failed to load gfx firmware!\n"); 2287 return r; 2288 } 2289 2290 r = adev->gfx.rlc.funcs->init(adev); 2291 if (r) { 2292 DRM_ERROR("Failed to init rlc BOs!\n"); 2293 return r; 2294 } 2295 2296 r = gfx_v9_0_mec_init(adev); 2297 if (r) { 2298 DRM_ERROR("Failed to init MEC BOs!\n"); 2299 return r; 2300 } 2301 2302 /* set up the gfx ring */ 2303 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2304 ring = &adev->gfx.gfx_ring[i]; 2305 ring->ring_obj = NULL; 2306 if (!i) 2307 sprintf(ring->name, "gfx"); 2308 else 2309 sprintf(ring->name, "gfx_%d", i); 2310 ring->use_doorbell = true; 2311 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2312 r = amdgpu_ring_init(adev, ring, 1024, 2313 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); 2314 if (r) 2315 return r; 2316 } 2317 2318 /* set up the compute queues - allocate horizontally across pipes */ 2319 ring_id = 0; 2320 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2321 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2322 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2323 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2324 continue; 2325 2326 r = gfx_v9_0_compute_ring_init(adev, 2327 ring_id, 2328 i, k, j); 2329 if (r) 2330 return r; 2331 2332 ring_id++; 2333 } 2334 } 2335 } 2336 2337 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2338 if (r) { 2339 DRM_ERROR("Failed to init KIQ BOs!\n"); 2340 return r; 2341 } 2342 2343 kiq = &adev->gfx.kiq; 2344 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2345 if (r) 2346 return r; 2347 2348 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2349 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2350 if (r) 2351 return r; 2352 2353 adev->gfx.ce_ram_size = 0x8000; 2354 2355 r = gfx_v9_0_gpu_early_init(adev); 2356 if (r) 2357 return r; 2358 2359 return 0; 2360 } 2361 2362 2363 static int gfx_v9_0_sw_fini(void *handle) 2364 { 2365 int i; 2366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2367 2368 amdgpu_gfx_ras_fini(adev); 2369 2370 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2371 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2372 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2373 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2374 2375 amdgpu_gfx_mqd_sw_fini(adev); 2376 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2377 amdgpu_gfx_kiq_fini(adev); 2378 2379 gfx_v9_0_mec_fini(adev); 2380 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 2381 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { 2382 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2383 &adev->gfx.rlc.cp_table_gpu_addr, 2384 (void **)&adev->gfx.rlc.cp_table_ptr); 2385 } 2386 gfx_v9_0_free_microcode(adev); 2387 2388 return 0; 2389 } 2390 2391 2392 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2393 { 2394 /* TODO */ 2395 } 2396 2397 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 2398 { 2399 u32 data; 2400 2401 if (instance == 0xffffffff) 2402 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2403 else 2404 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2405 2406 if (se_num == 0xffffffff) 2407 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2408 else 2409 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2410 2411 if (sh_num == 0xffffffff) 2412 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2413 else 2414 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2415 2416 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2417 } 2418 2419 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2420 { 2421 u32 data, mask; 2422 2423 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2424 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2425 2426 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2427 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2428 2429 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2430 adev->gfx.config.max_sh_per_se); 2431 2432 return (~data) & mask; 2433 } 2434 2435 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2436 { 2437 int i, j; 2438 u32 data; 2439 u32 active_rbs = 0; 2440 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2441 adev->gfx.config.max_sh_per_se; 2442 2443 mutex_lock(&adev->grbm_idx_mutex); 2444 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2445 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2446 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2447 data = gfx_v9_0_get_rb_active_bitmap(adev); 2448 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2449 rb_bitmap_width_per_sh); 2450 } 2451 } 2452 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2453 mutex_unlock(&adev->grbm_idx_mutex); 2454 2455 adev->gfx.config.backend_enable_mask = active_rbs; 2456 adev->gfx.config.num_rbs = hweight32(active_rbs); 2457 } 2458 2459 #define DEFAULT_SH_MEM_BASES (0x6000) 2460 #define FIRST_COMPUTE_VMID (8) 2461 #define LAST_COMPUTE_VMID (16) 2462 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2463 { 2464 int i; 2465 uint32_t sh_mem_config; 2466 uint32_t sh_mem_bases; 2467 2468 /* 2469 * Configure apertures: 2470 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2471 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2472 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2473 */ 2474 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2475 2476 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2477 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2478 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2479 2480 mutex_lock(&adev->srbm_mutex); 2481 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 2482 soc15_grbm_select(adev, 0, 0, 0, i); 2483 /* CP and shaders */ 2484 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2485 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2486 } 2487 soc15_grbm_select(adev, 0, 0, 0, 0); 2488 mutex_unlock(&adev->srbm_mutex); 2489 2490 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2491 acccess. These should be enabled by FW for target VMIDs. */ 2492 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 2493 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2494 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2495 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2496 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2497 } 2498 } 2499 2500 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2501 { 2502 int vmid; 2503 2504 /* 2505 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2506 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2507 * the driver can enable them for graphics. VMID0 should maintain 2508 * access so that HWS firmware can save/restore entries. 2509 */ 2510 for (vmid = 1; vmid < 16; vmid++) { 2511 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2512 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2513 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2514 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2515 } 2516 } 2517 2518 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2519 { 2520 uint32_t tmp; 2521 2522 switch (adev->asic_type) { 2523 case CHIP_ARCTURUS: 2524 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2525 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2526 DISABLE_BARRIER_WAITCNT, 1); 2527 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2528 break; 2529 default: 2530 break; 2531 }; 2532 } 2533 2534 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2535 { 2536 u32 tmp; 2537 int i; 2538 2539 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2540 2541 gfx_v9_0_tiling_mode_table_init(adev); 2542 2543 gfx_v9_0_setup_rb(adev); 2544 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2545 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2546 2547 /* XXX SH_MEM regs */ 2548 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2549 mutex_lock(&adev->srbm_mutex); 2550 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2551 soc15_grbm_select(adev, 0, 0, 0, i); 2552 /* CP and shaders */ 2553 if (i == 0) { 2554 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2555 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2556 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2557 !!amdgpu_noretry); 2558 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2559 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2560 } else { 2561 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2562 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2563 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2564 !!amdgpu_noretry); 2565 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2566 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2567 (adev->gmc.private_aperture_start >> 48)); 2568 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2569 (adev->gmc.shared_aperture_start >> 48)); 2570 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2571 } 2572 } 2573 soc15_grbm_select(adev, 0, 0, 0, 0); 2574 2575 mutex_unlock(&adev->srbm_mutex); 2576 2577 gfx_v9_0_init_compute_vmid(adev); 2578 gfx_v9_0_init_gds_vmid(adev); 2579 gfx_v9_0_init_sq_config(adev); 2580 } 2581 2582 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2583 { 2584 u32 i, j, k; 2585 u32 mask; 2586 2587 mutex_lock(&adev->grbm_idx_mutex); 2588 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2589 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2590 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2591 for (k = 0; k < adev->usec_timeout; k++) { 2592 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2593 break; 2594 udelay(1); 2595 } 2596 if (k == adev->usec_timeout) { 2597 gfx_v9_0_select_se_sh(adev, 0xffffffff, 2598 0xffffffff, 0xffffffff); 2599 mutex_unlock(&adev->grbm_idx_mutex); 2600 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2601 i, j); 2602 return; 2603 } 2604 } 2605 } 2606 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2607 mutex_unlock(&adev->grbm_idx_mutex); 2608 2609 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2610 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2611 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2612 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2613 for (k = 0; k < adev->usec_timeout; k++) { 2614 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2615 break; 2616 udelay(1); 2617 } 2618 } 2619 2620 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2621 bool enable) 2622 { 2623 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2624 2625 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2626 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2627 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2628 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2629 2630 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2631 } 2632 2633 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2634 { 2635 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2636 /* csib */ 2637 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2638 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2639 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2640 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2641 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2642 adev->gfx.rlc.clear_state_size); 2643 } 2644 2645 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2646 int indirect_offset, 2647 int list_size, 2648 int *unique_indirect_regs, 2649 int unique_indirect_reg_count, 2650 int *indirect_start_offsets, 2651 int *indirect_start_offsets_count, 2652 int max_start_offsets_count) 2653 { 2654 int idx; 2655 2656 for (; indirect_offset < list_size; indirect_offset++) { 2657 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2658 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2659 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2660 2661 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2662 indirect_offset += 2; 2663 2664 /* look for the matching indice */ 2665 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2666 if (unique_indirect_regs[idx] == 2667 register_list_format[indirect_offset] || 2668 !unique_indirect_regs[idx]) 2669 break; 2670 } 2671 2672 BUG_ON(idx >= unique_indirect_reg_count); 2673 2674 if (!unique_indirect_regs[idx]) 2675 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2676 2677 indirect_offset++; 2678 } 2679 } 2680 } 2681 2682 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2683 { 2684 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2685 int unique_indirect_reg_count = 0; 2686 2687 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2688 int indirect_start_offsets_count = 0; 2689 2690 int list_size = 0; 2691 int i = 0, j = 0; 2692 u32 tmp = 0; 2693 2694 u32 *register_list_format = 2695 kmemdup(adev->gfx.rlc.register_list_format, 2696 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2697 if (!register_list_format) 2698 return -ENOMEM; 2699 2700 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2701 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2702 gfx_v9_1_parse_ind_reg_list(register_list_format, 2703 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2704 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2705 unique_indirect_regs, 2706 unique_indirect_reg_count, 2707 indirect_start_offsets, 2708 &indirect_start_offsets_count, 2709 ARRAY_SIZE(indirect_start_offsets)); 2710 2711 /* enable auto inc in case it is disabled */ 2712 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2713 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2714 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2715 2716 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2717 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2718 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2719 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2720 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2721 adev->gfx.rlc.register_restore[i]); 2722 2723 /* load indirect register */ 2724 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2725 adev->gfx.rlc.reg_list_format_start); 2726 2727 /* direct register portion */ 2728 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2729 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2730 register_list_format[i]); 2731 2732 /* indirect register portion */ 2733 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2734 if (register_list_format[i] == 0xFFFFFFFF) { 2735 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2736 continue; 2737 } 2738 2739 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2740 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2741 2742 for (j = 0; j < unique_indirect_reg_count; j++) { 2743 if (register_list_format[i] == unique_indirect_regs[j]) { 2744 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2745 break; 2746 } 2747 } 2748 2749 BUG_ON(j >= unique_indirect_reg_count); 2750 2751 i++; 2752 } 2753 2754 /* set save/restore list size */ 2755 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2756 list_size = list_size >> 1; 2757 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2758 adev->gfx.rlc.reg_restore_list_size); 2759 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2760 2761 /* write the starting offsets to RLC scratch ram */ 2762 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2763 adev->gfx.rlc.starting_offsets_start); 2764 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2765 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2766 indirect_start_offsets[i]); 2767 2768 /* load unique indirect regs*/ 2769 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2770 if (unique_indirect_regs[i] != 0) { 2771 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2772 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2773 unique_indirect_regs[i] & 0x3FFFF); 2774 2775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2776 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2777 unique_indirect_regs[i] >> 20); 2778 } 2779 } 2780 2781 kfree(register_list_format); 2782 return 0; 2783 } 2784 2785 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2786 { 2787 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2788 } 2789 2790 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2791 bool enable) 2792 { 2793 uint32_t data = 0; 2794 uint32_t default_data = 0; 2795 2796 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2797 if (enable == true) { 2798 /* enable GFXIP control over CGPG */ 2799 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2800 if(default_data != data) 2801 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2802 2803 /* update status */ 2804 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2805 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2806 if(default_data != data) 2807 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2808 } else { 2809 /* restore GFXIP control over GCPG */ 2810 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2811 if(default_data != data) 2812 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2813 } 2814 } 2815 2816 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2817 { 2818 uint32_t data = 0; 2819 2820 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2821 AMD_PG_SUPPORT_GFX_SMG | 2822 AMD_PG_SUPPORT_GFX_DMG)) { 2823 /* init IDLE_POLL_COUNT = 60 */ 2824 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2825 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2826 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2827 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2828 2829 /* init RLC PG Delay */ 2830 data = 0; 2831 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2832 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2833 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2834 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2835 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2836 2837 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2838 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2839 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2840 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2841 2842 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2843 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2844 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2845 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2846 2847 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2848 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2849 2850 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2851 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2853 2854 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2855 } 2856 } 2857 2858 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2859 bool enable) 2860 { 2861 uint32_t data = 0; 2862 uint32_t default_data = 0; 2863 2864 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2865 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2866 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2867 enable ? 1 : 0); 2868 if (default_data != data) 2869 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2870 } 2871 2872 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2873 bool enable) 2874 { 2875 uint32_t data = 0; 2876 uint32_t default_data = 0; 2877 2878 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2879 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2880 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2881 enable ? 1 : 0); 2882 if(default_data != data) 2883 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2884 } 2885 2886 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2887 bool enable) 2888 { 2889 uint32_t data = 0; 2890 uint32_t default_data = 0; 2891 2892 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2893 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2894 CP_PG_DISABLE, 2895 enable ? 0 : 1); 2896 if(default_data != data) 2897 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2898 } 2899 2900 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2901 bool enable) 2902 { 2903 uint32_t data, default_data; 2904 2905 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2906 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2907 GFX_POWER_GATING_ENABLE, 2908 enable ? 1 : 0); 2909 if(default_data != data) 2910 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2911 } 2912 2913 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2914 bool enable) 2915 { 2916 uint32_t data, default_data; 2917 2918 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2919 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2920 GFX_PIPELINE_PG_ENABLE, 2921 enable ? 1 : 0); 2922 if(default_data != data) 2923 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2924 2925 if (!enable) 2926 /* read any GFX register to wake up GFX */ 2927 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2928 } 2929 2930 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2931 bool enable) 2932 { 2933 uint32_t data, default_data; 2934 2935 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2936 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2937 STATIC_PER_CU_PG_ENABLE, 2938 enable ? 1 : 0); 2939 if(default_data != data) 2940 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2941 } 2942 2943 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2944 bool enable) 2945 { 2946 uint32_t data, default_data; 2947 2948 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2949 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2950 DYN_PER_CU_PG_ENABLE, 2951 enable ? 1 : 0); 2952 if(default_data != data) 2953 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2954 } 2955 2956 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2957 { 2958 gfx_v9_0_init_csb(adev); 2959 2960 /* 2961 * Rlc save restore list is workable since v2_1. 2962 * And it's needed by gfxoff feature. 2963 */ 2964 if (adev->gfx.rlc.is_rlc_v2_1) { 2965 if (adev->asic_type == CHIP_VEGA12 || 2966 (adev->asic_type == CHIP_RAVEN && 2967 adev->rev_id >= 8)) 2968 gfx_v9_1_init_rlc_save_restore_list(adev); 2969 gfx_v9_0_enable_save_restore_machine(adev); 2970 } 2971 2972 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2973 AMD_PG_SUPPORT_GFX_SMG | 2974 AMD_PG_SUPPORT_GFX_DMG | 2975 AMD_PG_SUPPORT_CP | 2976 AMD_PG_SUPPORT_GDS | 2977 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2978 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2979 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2980 gfx_v9_0_init_gfx_power_gating(adev); 2981 } 2982 } 2983 2984 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2985 { 2986 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2987 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2988 gfx_v9_0_wait_for_rlc_serdes(adev); 2989 } 2990 2991 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2992 { 2993 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2994 udelay(50); 2995 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2996 udelay(50); 2997 } 2998 2999 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 3000 { 3001 #ifdef AMDGPU_RLC_DEBUG_RETRY 3002 u32 rlc_ucode_ver; 3003 #endif 3004 3005 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 3006 udelay(50); 3007 3008 /* carrizo do enable cp interrupt after cp inited */ 3009 if (!(adev->flags & AMD_IS_APU)) { 3010 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3011 udelay(50); 3012 } 3013 3014 #ifdef AMDGPU_RLC_DEBUG_RETRY 3015 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 3016 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 3017 if(rlc_ucode_ver == 0x108) { 3018 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 3019 rlc_ucode_ver, adev->gfx.rlc_fw_version); 3020 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 3021 * default is 0x9C4 to create a 100us interval */ 3022 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 3023 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 3024 * to disable the page fault retry interrupts, default is 3025 * 0x100 (256) */ 3026 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 3027 } 3028 #endif 3029 } 3030 3031 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 3032 { 3033 const struct rlc_firmware_header_v2_0 *hdr; 3034 const __le32 *fw_data; 3035 unsigned i, fw_size; 3036 3037 if (!adev->gfx.rlc_fw) 3038 return -EINVAL; 3039 3040 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3041 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3042 3043 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 3044 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3045 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3046 3047 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 3048 RLCG_UCODE_LOADING_START_ADDRESS); 3049 for (i = 0; i < fw_size; i++) 3050 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3051 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3052 3053 return 0; 3054 } 3055 3056 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 3057 { 3058 int r; 3059 3060 if (amdgpu_sriov_vf(adev)) { 3061 gfx_v9_0_init_csb(adev); 3062 return 0; 3063 } 3064 3065 adev->gfx.rlc.funcs->stop(adev); 3066 3067 /* disable CG */ 3068 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 3069 3070 gfx_v9_0_init_pg(adev); 3071 3072 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3073 /* legacy rlc firmware loading */ 3074 r = gfx_v9_0_rlc_load_microcode(adev); 3075 if (r) 3076 return r; 3077 } 3078 3079 switch (adev->asic_type) { 3080 case CHIP_RAVEN: 3081 if (amdgpu_lbpw == 0) 3082 gfx_v9_0_enable_lbpw(adev, false); 3083 else 3084 gfx_v9_0_enable_lbpw(adev, true); 3085 break; 3086 case CHIP_VEGA20: 3087 if (amdgpu_lbpw > 0) 3088 gfx_v9_0_enable_lbpw(adev, true); 3089 else 3090 gfx_v9_0_enable_lbpw(adev, false); 3091 break; 3092 default: 3093 break; 3094 } 3095 3096 adev->gfx.rlc.funcs->start(adev); 3097 3098 return 0; 3099 } 3100 3101 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3102 { 3103 int i; 3104 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 3105 3106 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3107 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3108 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 3109 if (!enable) { 3110 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3111 adev->gfx.gfx_ring[i].sched.ready = false; 3112 } 3113 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 3114 udelay(50); 3115 } 3116 3117 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3118 { 3119 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3120 const struct gfx_firmware_header_v1_0 *ce_hdr; 3121 const struct gfx_firmware_header_v1_0 *me_hdr; 3122 const __le32 *fw_data; 3123 unsigned i, fw_size; 3124 3125 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3126 return -EINVAL; 3127 3128 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3129 adev->gfx.pfp_fw->data; 3130 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3131 adev->gfx.ce_fw->data; 3132 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3133 adev->gfx.me_fw->data; 3134 3135 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3136 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3137 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3138 3139 gfx_v9_0_cp_gfx_enable(adev, false); 3140 3141 /* PFP */ 3142 fw_data = (const __le32 *) 3143 (adev->gfx.pfp_fw->data + 3144 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3145 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3146 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3147 for (i = 0; i < fw_size; i++) 3148 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3149 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3150 3151 /* CE */ 3152 fw_data = (const __le32 *) 3153 (adev->gfx.ce_fw->data + 3154 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3155 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3156 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3157 for (i = 0; i < fw_size; i++) 3158 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3159 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3160 3161 /* ME */ 3162 fw_data = (const __le32 *) 3163 (adev->gfx.me_fw->data + 3164 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3165 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3166 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3167 for (i = 0; i < fw_size; i++) 3168 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3169 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3170 3171 return 0; 3172 } 3173 3174 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3175 { 3176 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3177 const struct cs_section_def *sect = NULL; 3178 const struct cs_extent_def *ext = NULL; 3179 int r, i, tmp; 3180 3181 /* init the CP */ 3182 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3183 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3184 3185 gfx_v9_0_cp_gfx_enable(adev, true); 3186 3187 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3188 if (r) { 3189 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3190 return r; 3191 } 3192 3193 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3194 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3195 3196 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3197 amdgpu_ring_write(ring, 0x80000000); 3198 amdgpu_ring_write(ring, 0x80000000); 3199 3200 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3201 for (ext = sect->section; ext->extent != NULL; ++ext) { 3202 if (sect->id == SECT_CONTEXT) { 3203 amdgpu_ring_write(ring, 3204 PACKET3(PACKET3_SET_CONTEXT_REG, 3205 ext->reg_count)); 3206 amdgpu_ring_write(ring, 3207 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3208 for (i = 0; i < ext->reg_count; i++) 3209 amdgpu_ring_write(ring, ext->extent[i]); 3210 } 3211 } 3212 } 3213 3214 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3215 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3216 3217 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3218 amdgpu_ring_write(ring, 0); 3219 3220 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3221 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3222 amdgpu_ring_write(ring, 0x8000); 3223 amdgpu_ring_write(ring, 0x8000); 3224 3225 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3226 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3227 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3228 amdgpu_ring_write(ring, tmp); 3229 amdgpu_ring_write(ring, 0); 3230 3231 amdgpu_ring_commit(ring); 3232 3233 return 0; 3234 } 3235 3236 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3237 { 3238 struct amdgpu_ring *ring; 3239 u32 tmp; 3240 u32 rb_bufsz; 3241 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3242 3243 /* Set the write pointer delay */ 3244 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3245 3246 /* set the RB to use vmid 0 */ 3247 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3248 3249 /* Set ring buffer size */ 3250 ring = &adev->gfx.gfx_ring[0]; 3251 rb_bufsz = order_base_2(ring->ring_size / 8); 3252 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3253 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3254 #ifdef __BIG_ENDIAN 3255 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3256 #endif 3257 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3258 3259 /* Initialize the ring buffer's write pointers */ 3260 ring->wptr = 0; 3261 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3262 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3263 3264 /* set the wb address wether it's enabled or not */ 3265 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3266 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3267 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3268 3269 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3270 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3271 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3272 3273 mdelay(1); 3274 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3275 3276 rb_addr = ring->gpu_addr >> 8; 3277 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3278 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3279 3280 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3281 if (ring->use_doorbell) { 3282 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3283 DOORBELL_OFFSET, ring->doorbell_index); 3284 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3285 DOORBELL_EN, 1); 3286 } else { 3287 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3288 } 3289 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3290 3291 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3292 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3293 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3294 3295 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3296 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3297 3298 3299 /* start the ring */ 3300 gfx_v9_0_cp_gfx_start(adev); 3301 ring->sched.ready = true; 3302 3303 return 0; 3304 } 3305 3306 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3307 { 3308 int i; 3309 3310 if (enable) { 3311 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3312 } else { 3313 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3314 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3315 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3316 adev->gfx.compute_ring[i].sched.ready = false; 3317 adev->gfx.kiq.ring.sched.ready = false; 3318 } 3319 udelay(50); 3320 } 3321 3322 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3323 { 3324 const struct gfx_firmware_header_v1_0 *mec_hdr; 3325 const __le32 *fw_data; 3326 unsigned i; 3327 u32 tmp; 3328 3329 if (!adev->gfx.mec_fw) 3330 return -EINVAL; 3331 3332 gfx_v9_0_cp_compute_enable(adev, false); 3333 3334 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3335 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3336 3337 fw_data = (const __le32 *) 3338 (adev->gfx.mec_fw->data + 3339 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3340 tmp = 0; 3341 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3342 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3343 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3344 3345 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3346 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3348 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3349 3350 /* MEC1 */ 3351 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3352 mec_hdr->jt_offset); 3353 for (i = 0; i < mec_hdr->jt_size; i++) 3354 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3355 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3356 3357 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3358 adev->gfx.mec_fw_version); 3359 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3360 3361 return 0; 3362 } 3363 3364 /* KIQ functions */ 3365 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3366 { 3367 uint32_t tmp; 3368 struct amdgpu_device *adev = ring->adev; 3369 3370 /* tell RLC which is KIQ queue */ 3371 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3372 tmp &= 0xffffff00; 3373 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3374 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3375 tmp |= 0x80; 3376 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3377 } 3378 3379 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3380 { 3381 struct amdgpu_device *adev = ring->adev; 3382 3383 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3384 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) { 3385 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3386 ring->has_high_prio = true; 3387 mqd->cp_hqd_queue_priority = 3388 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3389 } else { 3390 ring->has_high_prio = false; 3391 } 3392 } 3393 } 3394 3395 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3396 { 3397 struct amdgpu_device *adev = ring->adev; 3398 struct v9_mqd *mqd = ring->mqd_ptr; 3399 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3400 uint32_t tmp; 3401 3402 mqd->header = 0xC0310800; 3403 mqd->compute_pipelinestat_enable = 0x00000001; 3404 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3405 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3406 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3407 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3408 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3409 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3410 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3411 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3412 mqd->compute_misc_reserved = 0x00000003; 3413 3414 mqd->dynamic_cu_mask_addr_lo = 3415 lower_32_bits(ring->mqd_gpu_addr 3416 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3417 mqd->dynamic_cu_mask_addr_hi = 3418 upper_32_bits(ring->mqd_gpu_addr 3419 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3420 3421 eop_base_addr = ring->eop_gpu_addr >> 8; 3422 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3423 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3424 3425 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3426 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3427 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3428 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3429 3430 mqd->cp_hqd_eop_control = tmp; 3431 3432 /* enable doorbell? */ 3433 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3434 3435 if (ring->use_doorbell) { 3436 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3437 DOORBELL_OFFSET, ring->doorbell_index); 3438 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3439 DOORBELL_EN, 1); 3440 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3441 DOORBELL_SOURCE, 0); 3442 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3443 DOORBELL_HIT, 0); 3444 } else { 3445 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3446 DOORBELL_EN, 0); 3447 } 3448 3449 mqd->cp_hqd_pq_doorbell_control = tmp; 3450 3451 /* disable the queue if it's active */ 3452 ring->wptr = 0; 3453 mqd->cp_hqd_dequeue_request = 0; 3454 mqd->cp_hqd_pq_rptr = 0; 3455 mqd->cp_hqd_pq_wptr_lo = 0; 3456 mqd->cp_hqd_pq_wptr_hi = 0; 3457 3458 /* set the pointer to the MQD */ 3459 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3460 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3461 3462 /* set MQD vmid to 0 */ 3463 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3464 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3465 mqd->cp_mqd_control = tmp; 3466 3467 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3468 hqd_gpu_addr = ring->gpu_addr >> 8; 3469 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3470 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3471 3472 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3473 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3474 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3475 (order_base_2(ring->ring_size / 4) - 1)); 3476 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3477 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3478 #ifdef __BIG_ENDIAN 3479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3480 #endif 3481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3482 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3483 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3484 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3485 mqd->cp_hqd_pq_control = tmp; 3486 3487 /* set the wb address whether it's enabled or not */ 3488 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3489 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3490 mqd->cp_hqd_pq_rptr_report_addr_hi = 3491 upper_32_bits(wb_gpu_addr) & 0xffff; 3492 3493 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3494 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3495 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3496 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3497 3498 tmp = 0; 3499 /* enable the doorbell if requested */ 3500 if (ring->use_doorbell) { 3501 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3502 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3503 DOORBELL_OFFSET, ring->doorbell_index); 3504 3505 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3506 DOORBELL_EN, 1); 3507 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3508 DOORBELL_SOURCE, 0); 3509 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3510 DOORBELL_HIT, 0); 3511 } 3512 3513 mqd->cp_hqd_pq_doorbell_control = tmp; 3514 3515 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3516 ring->wptr = 0; 3517 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3518 3519 /* set the vmid for the queue */ 3520 mqd->cp_hqd_vmid = 0; 3521 3522 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3523 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3524 mqd->cp_hqd_persistent_state = tmp; 3525 3526 /* set MIN_IB_AVAIL_SIZE */ 3527 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3528 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3529 mqd->cp_hqd_ib_control = tmp; 3530 3531 /* set static priority for a queue/ring */ 3532 gfx_v9_0_mqd_set_priority(ring, mqd); 3533 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3534 3535 /* map_queues packet doesn't need activate the queue, 3536 * so only kiq need set this field. 3537 */ 3538 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3539 mqd->cp_hqd_active = 1; 3540 3541 return 0; 3542 } 3543 3544 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3545 { 3546 struct amdgpu_device *adev = ring->adev; 3547 struct v9_mqd *mqd = ring->mqd_ptr; 3548 int j; 3549 3550 /* disable wptr polling */ 3551 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3552 3553 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3554 mqd->cp_hqd_eop_base_addr_lo); 3555 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3556 mqd->cp_hqd_eop_base_addr_hi); 3557 3558 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3559 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3560 mqd->cp_hqd_eop_control); 3561 3562 /* enable doorbell? */ 3563 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3564 mqd->cp_hqd_pq_doorbell_control); 3565 3566 /* disable the queue if it's active */ 3567 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3568 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3569 for (j = 0; j < adev->usec_timeout; j++) { 3570 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3571 break; 3572 udelay(1); 3573 } 3574 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3575 mqd->cp_hqd_dequeue_request); 3576 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3577 mqd->cp_hqd_pq_rptr); 3578 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3579 mqd->cp_hqd_pq_wptr_lo); 3580 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3581 mqd->cp_hqd_pq_wptr_hi); 3582 } 3583 3584 /* set the pointer to the MQD */ 3585 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3586 mqd->cp_mqd_base_addr_lo); 3587 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3588 mqd->cp_mqd_base_addr_hi); 3589 3590 /* set MQD vmid to 0 */ 3591 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3592 mqd->cp_mqd_control); 3593 3594 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3595 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3596 mqd->cp_hqd_pq_base_lo); 3597 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3598 mqd->cp_hqd_pq_base_hi); 3599 3600 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3601 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3602 mqd->cp_hqd_pq_control); 3603 3604 /* set the wb address whether it's enabled or not */ 3605 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3606 mqd->cp_hqd_pq_rptr_report_addr_lo); 3607 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3608 mqd->cp_hqd_pq_rptr_report_addr_hi); 3609 3610 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3611 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3612 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3613 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3614 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3615 3616 /* enable the doorbell if requested */ 3617 if (ring->use_doorbell) { 3618 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3619 (adev->doorbell_index.kiq * 2) << 2); 3620 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3621 (adev->doorbell_index.userqueue_end * 2) << 2); 3622 } 3623 3624 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3625 mqd->cp_hqd_pq_doorbell_control); 3626 3627 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3628 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3629 mqd->cp_hqd_pq_wptr_lo); 3630 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3631 mqd->cp_hqd_pq_wptr_hi); 3632 3633 /* set the vmid for the queue */ 3634 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3635 3636 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3637 mqd->cp_hqd_persistent_state); 3638 3639 /* activate the queue */ 3640 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3641 mqd->cp_hqd_active); 3642 3643 if (ring->use_doorbell) 3644 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3645 3646 return 0; 3647 } 3648 3649 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3650 { 3651 struct amdgpu_device *adev = ring->adev; 3652 int j; 3653 3654 /* disable the queue if it's active */ 3655 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3656 3657 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3658 3659 for (j = 0; j < adev->usec_timeout; j++) { 3660 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3661 break; 3662 udelay(1); 3663 } 3664 3665 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3666 DRM_DEBUG("KIQ dequeue request failed.\n"); 3667 3668 /* Manual disable if dequeue request times out */ 3669 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3670 } 3671 3672 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3673 0); 3674 } 3675 3676 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3677 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3678 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3679 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3680 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3681 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3682 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3683 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3684 3685 return 0; 3686 } 3687 3688 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3689 { 3690 struct amdgpu_device *adev = ring->adev; 3691 struct v9_mqd *mqd = ring->mqd_ptr; 3692 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3693 3694 gfx_v9_0_kiq_setting(ring); 3695 3696 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3697 /* reset MQD to a clean status */ 3698 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3699 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3700 3701 /* reset ring buffer */ 3702 ring->wptr = 0; 3703 amdgpu_ring_clear_ring(ring); 3704 3705 mutex_lock(&adev->srbm_mutex); 3706 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3707 gfx_v9_0_kiq_init_register(ring); 3708 soc15_grbm_select(adev, 0, 0, 0, 0); 3709 mutex_unlock(&adev->srbm_mutex); 3710 } else { 3711 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3712 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3713 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3714 mutex_lock(&adev->srbm_mutex); 3715 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3716 gfx_v9_0_mqd_init(ring); 3717 gfx_v9_0_kiq_init_register(ring); 3718 soc15_grbm_select(adev, 0, 0, 0, 0); 3719 mutex_unlock(&adev->srbm_mutex); 3720 3721 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3722 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3723 } 3724 3725 return 0; 3726 } 3727 3728 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3729 { 3730 struct amdgpu_device *adev = ring->adev; 3731 struct v9_mqd *mqd = ring->mqd_ptr; 3732 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3733 3734 if (!adev->in_gpu_reset && !adev->in_suspend) { 3735 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3736 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3737 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3738 mutex_lock(&adev->srbm_mutex); 3739 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3740 gfx_v9_0_mqd_init(ring); 3741 soc15_grbm_select(adev, 0, 0, 0, 0); 3742 mutex_unlock(&adev->srbm_mutex); 3743 3744 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3745 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3746 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3747 /* reset MQD to a clean status */ 3748 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3749 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3750 3751 /* reset ring buffer */ 3752 ring->wptr = 0; 3753 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 3754 amdgpu_ring_clear_ring(ring); 3755 } else { 3756 amdgpu_ring_clear_ring(ring); 3757 } 3758 3759 return 0; 3760 } 3761 3762 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3763 { 3764 struct amdgpu_ring *ring; 3765 int r; 3766 3767 ring = &adev->gfx.kiq.ring; 3768 3769 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3770 if (unlikely(r != 0)) 3771 return r; 3772 3773 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3774 if (unlikely(r != 0)) 3775 return r; 3776 3777 gfx_v9_0_kiq_init_queue(ring); 3778 amdgpu_bo_kunmap(ring->mqd_obj); 3779 ring->mqd_ptr = NULL; 3780 amdgpu_bo_unreserve(ring->mqd_obj); 3781 ring->sched.ready = true; 3782 return 0; 3783 } 3784 3785 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3786 { 3787 struct amdgpu_ring *ring = NULL; 3788 int r = 0, i; 3789 3790 gfx_v9_0_cp_compute_enable(adev, true); 3791 3792 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3793 ring = &adev->gfx.compute_ring[i]; 3794 3795 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3796 if (unlikely(r != 0)) 3797 goto done; 3798 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3799 if (!r) { 3800 r = gfx_v9_0_kcq_init_queue(ring); 3801 amdgpu_bo_kunmap(ring->mqd_obj); 3802 ring->mqd_ptr = NULL; 3803 } 3804 amdgpu_bo_unreserve(ring->mqd_obj); 3805 if (r) 3806 goto done; 3807 } 3808 3809 r = amdgpu_gfx_enable_kcq(adev); 3810 done: 3811 return r; 3812 } 3813 3814 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3815 { 3816 int r, i; 3817 struct amdgpu_ring *ring; 3818 3819 if (!(adev->flags & AMD_IS_APU)) 3820 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3821 3822 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3823 if (adev->asic_type != CHIP_ARCTURUS) { 3824 /* legacy firmware loading */ 3825 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3826 if (r) 3827 return r; 3828 } 3829 3830 r = gfx_v9_0_cp_compute_load_microcode(adev); 3831 if (r) 3832 return r; 3833 } 3834 3835 r = gfx_v9_0_kiq_resume(adev); 3836 if (r) 3837 return r; 3838 3839 if (adev->asic_type != CHIP_ARCTURUS) { 3840 r = gfx_v9_0_cp_gfx_resume(adev); 3841 if (r) 3842 return r; 3843 } 3844 3845 r = gfx_v9_0_kcq_resume(adev); 3846 if (r) 3847 return r; 3848 3849 if (adev->asic_type != CHIP_ARCTURUS) { 3850 ring = &adev->gfx.gfx_ring[0]; 3851 r = amdgpu_ring_test_helper(ring); 3852 if (r) 3853 return r; 3854 } 3855 3856 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3857 ring = &adev->gfx.compute_ring[i]; 3858 amdgpu_ring_test_helper(ring); 3859 } 3860 3861 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3862 3863 return 0; 3864 } 3865 3866 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3867 { 3868 u32 tmp; 3869 3870 if (adev->asic_type != CHIP_ARCTURUS) 3871 return; 3872 3873 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3874 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3875 adev->df.hash_status.hash_64k); 3876 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3877 adev->df.hash_status.hash_2m); 3878 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3879 adev->df.hash_status.hash_1g); 3880 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3881 } 3882 3883 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3884 { 3885 if (adev->asic_type != CHIP_ARCTURUS) 3886 gfx_v9_0_cp_gfx_enable(adev, enable); 3887 gfx_v9_0_cp_compute_enable(adev, enable); 3888 } 3889 3890 static int gfx_v9_0_hw_init(void *handle) 3891 { 3892 int r; 3893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3894 3895 if (!amdgpu_sriov_vf(adev)) 3896 gfx_v9_0_init_golden_registers(adev); 3897 3898 gfx_v9_0_constants_init(adev); 3899 3900 gfx_v9_0_init_tcp_config(adev); 3901 3902 r = adev->gfx.rlc.funcs->resume(adev); 3903 if (r) 3904 return r; 3905 3906 r = gfx_v9_0_cp_resume(adev); 3907 if (r) 3908 return r; 3909 3910 return r; 3911 } 3912 3913 static int gfx_v9_0_hw_fini(void *handle) 3914 { 3915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3916 3917 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3918 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3919 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3920 3921 /* DF freeze and kcq disable will fail */ 3922 if (!amdgpu_ras_intr_triggered()) 3923 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3924 amdgpu_gfx_disable_kcq(adev); 3925 3926 if (amdgpu_sriov_vf(adev)) { 3927 gfx_v9_0_cp_gfx_enable(adev, false); 3928 /* must disable polling for SRIOV when hw finished, otherwise 3929 * CPC engine may still keep fetching WB address which is already 3930 * invalid after sw finished and trigger DMAR reading error in 3931 * hypervisor side. 3932 */ 3933 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3934 return 0; 3935 } 3936 3937 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3938 * otherwise KIQ is hanging when binding back 3939 */ 3940 if (!adev->in_gpu_reset && !adev->in_suspend) { 3941 mutex_lock(&adev->srbm_mutex); 3942 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3943 adev->gfx.kiq.ring.pipe, 3944 adev->gfx.kiq.ring.queue, 0); 3945 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3946 soc15_grbm_select(adev, 0, 0, 0, 0); 3947 mutex_unlock(&adev->srbm_mutex); 3948 } 3949 3950 gfx_v9_0_cp_enable(adev, false); 3951 adev->gfx.rlc.funcs->stop(adev); 3952 3953 return 0; 3954 } 3955 3956 static int gfx_v9_0_suspend(void *handle) 3957 { 3958 return gfx_v9_0_hw_fini(handle); 3959 } 3960 3961 static int gfx_v9_0_resume(void *handle) 3962 { 3963 return gfx_v9_0_hw_init(handle); 3964 } 3965 3966 static bool gfx_v9_0_is_idle(void *handle) 3967 { 3968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3969 3970 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3971 GRBM_STATUS, GUI_ACTIVE)) 3972 return false; 3973 else 3974 return true; 3975 } 3976 3977 static int gfx_v9_0_wait_for_idle(void *handle) 3978 { 3979 unsigned i; 3980 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3981 3982 for (i = 0; i < adev->usec_timeout; i++) { 3983 if (gfx_v9_0_is_idle(handle)) 3984 return 0; 3985 udelay(1); 3986 } 3987 return -ETIMEDOUT; 3988 } 3989 3990 static int gfx_v9_0_soft_reset(void *handle) 3991 { 3992 u32 grbm_soft_reset = 0; 3993 u32 tmp; 3994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3995 3996 /* GRBM_STATUS */ 3997 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3998 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3999 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4000 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4001 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4002 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4003 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 4004 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4005 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4006 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4007 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4008 } 4009 4010 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4011 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4012 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4013 } 4014 4015 /* GRBM_STATUS2 */ 4016 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 4017 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4018 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4019 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4020 4021 4022 if (grbm_soft_reset) { 4023 /* stop the rlc */ 4024 adev->gfx.rlc.funcs->stop(adev); 4025 4026 if (adev->asic_type != CHIP_ARCTURUS) 4027 /* Disable GFX parsing/prefetching */ 4028 gfx_v9_0_cp_gfx_enable(adev, false); 4029 4030 /* Disable MEC parsing/prefetching */ 4031 gfx_v9_0_cp_compute_enable(adev, false); 4032 4033 if (grbm_soft_reset) { 4034 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4035 tmp |= grbm_soft_reset; 4036 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4037 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4038 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4039 4040 udelay(50); 4041 4042 tmp &= ~grbm_soft_reset; 4043 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4044 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4045 } 4046 4047 /* Wait a little for things to settle down */ 4048 udelay(50); 4049 } 4050 return 0; 4051 } 4052 4053 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 4054 { 4055 signed long r, cnt = 0; 4056 unsigned long flags; 4057 uint32_t seq; 4058 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4059 struct amdgpu_ring *ring = &kiq->ring; 4060 4061 BUG_ON(!ring->funcs->emit_rreg); 4062 4063 spin_lock_irqsave(&kiq->ring_lock, flags); 4064 amdgpu_ring_alloc(ring, 32); 4065 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4066 amdgpu_ring_write(ring, 9 | /* src: register*/ 4067 (5 << 8) | /* dst: memory */ 4068 (1 << 16) | /* count sel */ 4069 (1 << 20)); /* write confirm */ 4070 amdgpu_ring_write(ring, 0); 4071 amdgpu_ring_write(ring, 0); 4072 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4073 kiq->reg_val_offs * 4)); 4074 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4075 kiq->reg_val_offs * 4)); 4076 amdgpu_fence_emit_polling(ring, &seq); 4077 amdgpu_ring_commit(ring); 4078 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4079 4080 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4081 4082 /* don't wait anymore for gpu reset case because this way may 4083 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 4084 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 4085 * never return if we keep waiting in virt_kiq_rreg, which cause 4086 * gpu_recover() hang there. 4087 * 4088 * also don't wait anymore for IRQ context 4089 * */ 4090 if (r < 1 && (adev->in_gpu_reset || in_interrupt())) 4091 goto failed_kiq_read; 4092 4093 might_sleep(); 4094 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 4095 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 4096 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4097 } 4098 4099 if (cnt > MAX_KIQ_REG_TRY) 4100 goto failed_kiq_read; 4101 4102 return (uint64_t)adev->wb.wb[kiq->reg_val_offs] | 4103 (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL; 4104 4105 failed_kiq_read: 4106 pr_err("failed to read gpu clock\n"); 4107 return ~0; 4108 } 4109 4110 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4111 { 4112 uint64_t clock; 4113 4114 amdgpu_gfx_off_ctrl(adev, false); 4115 mutex_lock(&adev->gfx.gpu_clock_mutex); 4116 if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) { 4117 clock = gfx_v9_0_kiq_read_clock(adev); 4118 } else { 4119 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4120 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4121 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4122 } 4123 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4124 amdgpu_gfx_off_ctrl(adev, true); 4125 return clock; 4126 } 4127 4128 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4129 uint32_t vmid, 4130 uint32_t gds_base, uint32_t gds_size, 4131 uint32_t gws_base, uint32_t gws_size, 4132 uint32_t oa_base, uint32_t oa_size) 4133 { 4134 struct amdgpu_device *adev = ring->adev; 4135 4136 /* GDS Base */ 4137 gfx_v9_0_write_data_to_reg(ring, 0, false, 4138 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4139 gds_base); 4140 4141 /* GDS Size */ 4142 gfx_v9_0_write_data_to_reg(ring, 0, false, 4143 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4144 gds_size); 4145 4146 /* GWS */ 4147 gfx_v9_0_write_data_to_reg(ring, 0, false, 4148 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4149 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4150 4151 /* OA */ 4152 gfx_v9_0_write_data_to_reg(ring, 0, false, 4153 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4154 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4155 } 4156 4157 static const u32 vgpr_init_compute_shader[] = 4158 { 4159 0xb07c0000, 0xbe8000ff, 4160 0x000000f8, 0xbf110800, 4161 0x7e000280, 0x7e020280, 4162 0x7e040280, 0x7e060280, 4163 0x7e080280, 0x7e0a0280, 4164 0x7e0c0280, 0x7e0e0280, 4165 0x80808800, 0xbe803200, 4166 0xbf84fff5, 0xbf9c0000, 4167 0xd28c0001, 0x0001007f, 4168 0xd28d0001, 0x0002027e, 4169 0x10020288, 0xb8810904, 4170 0xb7814000, 0xd1196a01, 4171 0x00000301, 0xbe800087, 4172 0xbefc00c1, 0xd89c4000, 4173 0x00020201, 0xd89cc080, 4174 0x00040401, 0x320202ff, 4175 0x00000800, 0x80808100, 4176 0xbf84fff8, 0x7e020280, 4177 0xbf810000, 0x00000000, 4178 }; 4179 4180 static const u32 sgpr_init_compute_shader[] = 4181 { 4182 0xb07c0000, 0xbe8000ff, 4183 0x0000005f, 0xbee50080, 4184 0xbe812c65, 0xbe822c65, 4185 0xbe832c65, 0xbe842c65, 4186 0xbe852c65, 0xb77c0005, 4187 0x80808500, 0xbf84fff8, 4188 0xbe800080, 0xbf810000, 4189 }; 4190 4191 static const u32 vgpr_init_compute_shader_arcturus[] = { 4192 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4193 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4194 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4195 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4196 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4197 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4198 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4199 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4200 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4201 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4202 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4203 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4204 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4205 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4206 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4207 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4208 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4209 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4210 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4211 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4212 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4213 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4214 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4215 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4216 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4217 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4218 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4219 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4220 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4221 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4222 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4223 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4224 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4225 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4226 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4227 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4228 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4229 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4230 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4231 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4232 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4233 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4234 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4235 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4236 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4237 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4238 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4239 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4240 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4241 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4242 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4243 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4244 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4245 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4246 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4247 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4248 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4249 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4250 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4251 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4252 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4253 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4254 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4255 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4256 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4257 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4258 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4259 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4260 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4261 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4262 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4263 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4264 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4265 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4266 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4267 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4268 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4269 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4270 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4271 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4272 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4273 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4274 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4275 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4276 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4277 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4278 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4279 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4280 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4281 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4282 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4283 0xbf84fff8, 0xbf810000, 4284 }; 4285 4286 /* When below register arrays changed, please update gpr_reg_size, 4287 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4288 to cover all gfx9 ASICs */ 4289 static const struct soc15_reg_entry vgpr_init_regs[] = { 4290 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4291 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4292 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4293 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4294 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4295 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4296 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4297 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4298 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4299 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4300 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4301 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4302 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4303 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4304 }; 4305 4306 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4307 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4308 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4309 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4310 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4311 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4312 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4313 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4314 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4315 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4316 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4317 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4318 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4319 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4320 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4321 }; 4322 4323 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4324 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4325 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4326 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4327 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4328 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4329 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4330 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4331 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4332 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4333 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4334 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4335 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4336 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4337 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4338 }; 4339 4340 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4341 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4342 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4343 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4344 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4345 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4346 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4347 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4348 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4349 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4350 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4351 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4352 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4353 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4354 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4355 }; 4356 4357 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4358 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4359 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4360 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4361 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4362 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4363 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4364 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4365 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4366 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4367 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4368 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4369 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4370 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4371 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4372 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4373 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4374 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4375 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4376 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4377 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4378 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4379 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4380 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4381 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4382 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4383 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4384 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4385 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4386 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4387 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4388 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4389 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4390 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4391 }; 4392 4393 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4394 { 4395 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4396 int i, r; 4397 4398 /* only support when RAS is enabled */ 4399 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4400 return 0; 4401 4402 r = amdgpu_ring_alloc(ring, 7); 4403 if (r) { 4404 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4405 ring->name, r); 4406 return r; 4407 } 4408 4409 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4410 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4411 4412 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4413 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4414 PACKET3_DMA_DATA_DST_SEL(1) | 4415 PACKET3_DMA_DATA_SRC_SEL(2) | 4416 PACKET3_DMA_DATA_ENGINE(0))); 4417 amdgpu_ring_write(ring, 0); 4418 amdgpu_ring_write(ring, 0); 4419 amdgpu_ring_write(ring, 0); 4420 amdgpu_ring_write(ring, 0); 4421 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4422 adev->gds.gds_size); 4423 4424 amdgpu_ring_commit(ring); 4425 4426 for (i = 0; i < adev->usec_timeout; i++) { 4427 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4428 break; 4429 udelay(1); 4430 } 4431 4432 if (i >= adev->usec_timeout) 4433 r = -ETIMEDOUT; 4434 4435 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4436 4437 return r; 4438 } 4439 4440 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4441 { 4442 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4443 struct amdgpu_ib ib; 4444 struct dma_fence *f = NULL; 4445 int r, i; 4446 unsigned total_size, vgpr_offset, sgpr_offset; 4447 u64 gpu_addr; 4448 4449 int compute_dim_x = adev->gfx.config.max_shader_engines * 4450 adev->gfx.config.max_cu_per_sh * 4451 adev->gfx.config.max_sh_per_se; 4452 int sgpr_work_group_size = 5; 4453 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4454 int vgpr_init_shader_size; 4455 const u32 *vgpr_init_shader_ptr; 4456 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4457 4458 /* only support when RAS is enabled */ 4459 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4460 return 0; 4461 4462 /* bail if the compute ring is not ready */ 4463 if (!ring->sched.ready) 4464 return 0; 4465 4466 if (adev->asic_type == CHIP_ARCTURUS) { 4467 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4468 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4469 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4470 } else { 4471 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4472 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4473 vgpr_init_regs_ptr = vgpr_init_regs; 4474 } 4475 4476 total_size = 4477 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4478 total_size += 4479 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4480 total_size += 4481 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4482 total_size = ALIGN(total_size, 256); 4483 vgpr_offset = total_size; 4484 total_size += ALIGN(vgpr_init_shader_size, 256); 4485 sgpr_offset = total_size; 4486 total_size += sizeof(sgpr_init_compute_shader); 4487 4488 /* allocate an indirect buffer to put the commands in */ 4489 memset(&ib, 0, sizeof(ib)); 4490 r = amdgpu_ib_get(adev, NULL, total_size, &ib); 4491 if (r) { 4492 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4493 return r; 4494 } 4495 4496 /* load the compute shaders */ 4497 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4498 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4499 4500 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4501 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4502 4503 /* init the ib length to 0 */ 4504 ib.length_dw = 0; 4505 4506 /* VGPR */ 4507 /* write the register state for the compute dispatch */ 4508 for (i = 0; i < gpr_reg_size; i++) { 4509 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4510 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4511 - PACKET3_SET_SH_REG_START; 4512 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4513 } 4514 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4515 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4516 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4517 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4518 - PACKET3_SET_SH_REG_START; 4519 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4520 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4521 4522 /* write dispatch packet */ 4523 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4524 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4525 ib.ptr[ib.length_dw++] = 1; /* y */ 4526 ib.ptr[ib.length_dw++] = 1; /* z */ 4527 ib.ptr[ib.length_dw++] = 4528 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4529 4530 /* write CS partial flush packet */ 4531 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4532 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4533 4534 /* SGPR1 */ 4535 /* write the register state for the compute dispatch */ 4536 for (i = 0; i < gpr_reg_size; i++) { 4537 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4538 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4539 - PACKET3_SET_SH_REG_START; 4540 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4541 } 4542 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4543 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4544 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4545 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4546 - PACKET3_SET_SH_REG_START; 4547 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4548 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4549 4550 /* write dispatch packet */ 4551 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4552 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4553 ib.ptr[ib.length_dw++] = 1; /* y */ 4554 ib.ptr[ib.length_dw++] = 1; /* z */ 4555 ib.ptr[ib.length_dw++] = 4556 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4557 4558 /* write CS partial flush packet */ 4559 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4560 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4561 4562 /* SGPR2 */ 4563 /* write the register state for the compute dispatch */ 4564 for (i = 0; i < gpr_reg_size; i++) { 4565 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4566 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4567 - PACKET3_SET_SH_REG_START; 4568 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4569 } 4570 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4571 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4572 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4573 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4574 - PACKET3_SET_SH_REG_START; 4575 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4576 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4577 4578 /* write dispatch packet */ 4579 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4580 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4581 ib.ptr[ib.length_dw++] = 1; /* y */ 4582 ib.ptr[ib.length_dw++] = 1; /* z */ 4583 ib.ptr[ib.length_dw++] = 4584 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4585 4586 /* write CS partial flush packet */ 4587 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4588 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4589 4590 /* shedule the ib on the ring */ 4591 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4592 if (r) { 4593 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4594 goto fail; 4595 } 4596 4597 /* wait for the GPU to finish processing the IB */ 4598 r = dma_fence_wait(f, false); 4599 if (r) { 4600 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4601 goto fail; 4602 } 4603 4604 fail: 4605 amdgpu_ib_free(adev, &ib, NULL); 4606 dma_fence_put(f); 4607 4608 return r; 4609 } 4610 4611 static int gfx_v9_0_early_init(void *handle) 4612 { 4613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4614 4615 if (adev->asic_type == CHIP_ARCTURUS) 4616 adev->gfx.num_gfx_rings = 0; 4617 else 4618 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4619 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4620 gfx_v9_0_set_kiq_pm4_funcs(adev); 4621 gfx_v9_0_set_ring_funcs(adev); 4622 gfx_v9_0_set_irq_funcs(adev); 4623 gfx_v9_0_set_gds_init(adev); 4624 gfx_v9_0_set_rlc_funcs(adev); 4625 4626 return 0; 4627 } 4628 4629 static int gfx_v9_0_ecc_late_init(void *handle) 4630 { 4631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4632 int r; 4633 4634 /* 4635 * Temp workaround to fix the issue that CP firmware fails to 4636 * update read pointer when CPDMA is writing clearing operation 4637 * to GDS in suspend/resume sequence on several cards. So just 4638 * limit this operation in cold boot sequence. 4639 */ 4640 if (!adev->in_suspend) { 4641 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4642 if (r) 4643 return r; 4644 } 4645 4646 /* requires IBs so do in late init after IB pool is initialized */ 4647 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4648 if (r) 4649 return r; 4650 4651 if (adev->gfx.funcs && 4652 adev->gfx.funcs->reset_ras_error_count) 4653 adev->gfx.funcs->reset_ras_error_count(adev); 4654 4655 r = amdgpu_gfx_ras_late_init(adev); 4656 if (r) 4657 return r; 4658 4659 return 0; 4660 } 4661 4662 static int gfx_v9_0_late_init(void *handle) 4663 { 4664 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4665 int r; 4666 4667 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4668 if (r) 4669 return r; 4670 4671 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4672 if (r) 4673 return r; 4674 4675 r = gfx_v9_0_ecc_late_init(handle); 4676 if (r) 4677 return r; 4678 4679 return 0; 4680 } 4681 4682 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4683 { 4684 uint32_t rlc_setting; 4685 4686 /* if RLC is not enabled, do nothing */ 4687 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4688 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4689 return false; 4690 4691 return true; 4692 } 4693 4694 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4695 { 4696 uint32_t data; 4697 unsigned i; 4698 4699 data = RLC_SAFE_MODE__CMD_MASK; 4700 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4701 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4702 4703 /* wait for RLC_SAFE_MODE */ 4704 for (i = 0; i < adev->usec_timeout; i++) { 4705 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4706 break; 4707 udelay(1); 4708 } 4709 } 4710 4711 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4712 { 4713 uint32_t data; 4714 4715 data = RLC_SAFE_MODE__CMD_MASK; 4716 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4717 } 4718 4719 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4720 bool enable) 4721 { 4722 amdgpu_gfx_rlc_enter_safe_mode(adev); 4723 4724 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4725 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4726 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4727 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4728 } else { 4729 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4730 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4731 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4732 } 4733 4734 amdgpu_gfx_rlc_exit_safe_mode(adev); 4735 } 4736 4737 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4738 bool enable) 4739 { 4740 /* TODO: double check if we need to perform under safe mode */ 4741 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4742 4743 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4744 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4745 else 4746 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4747 4748 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4749 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4750 else 4751 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4752 4753 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4754 } 4755 4756 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4757 bool enable) 4758 { 4759 uint32_t data, def; 4760 4761 amdgpu_gfx_rlc_enter_safe_mode(adev); 4762 4763 /* It is disabled by HW by default */ 4764 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4765 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4766 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4767 4768 if (adev->asic_type != CHIP_VEGA12) 4769 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4770 4771 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4772 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4773 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4774 4775 /* only for Vega10 & Raven1 */ 4776 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4777 4778 if (def != data) 4779 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4780 4781 /* MGLS is a global flag to control all MGLS in GFX */ 4782 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4783 /* 2 - RLC memory Light sleep */ 4784 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4785 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4786 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4787 if (def != data) 4788 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4789 } 4790 /* 3 - CP memory Light sleep */ 4791 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4792 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4793 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4794 if (def != data) 4795 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4796 } 4797 } 4798 } else { 4799 /* 1 - MGCG_OVERRIDE */ 4800 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4801 4802 if (adev->asic_type != CHIP_VEGA12) 4803 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4804 4805 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4806 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4807 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4808 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4809 4810 if (def != data) 4811 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4812 4813 /* 2 - disable MGLS in RLC */ 4814 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4815 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4816 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4817 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4818 } 4819 4820 /* 3 - disable MGLS in CP */ 4821 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4822 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4823 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4824 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4825 } 4826 } 4827 4828 amdgpu_gfx_rlc_exit_safe_mode(adev); 4829 } 4830 4831 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4832 bool enable) 4833 { 4834 uint32_t data, def; 4835 4836 if (adev->asic_type == CHIP_ARCTURUS) 4837 return; 4838 4839 amdgpu_gfx_rlc_enter_safe_mode(adev); 4840 4841 /* Enable 3D CGCG/CGLS */ 4842 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4843 /* write cmd to clear cgcg/cgls ov */ 4844 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4845 /* unset CGCG override */ 4846 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4847 /* update CGCG and CGLS override bits */ 4848 if (def != data) 4849 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4850 4851 /* enable 3Dcgcg FSM(0x0000363f) */ 4852 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4853 4854 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4855 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4856 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4857 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4858 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4859 if (def != data) 4860 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4861 4862 /* set IDLE_POLL_COUNT(0x00900100) */ 4863 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4864 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4865 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4866 if (def != data) 4867 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4868 } else { 4869 /* Disable CGCG/CGLS */ 4870 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4871 /* disable cgcg, cgls should be disabled */ 4872 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4873 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4874 /* disable cgcg and cgls in FSM */ 4875 if (def != data) 4876 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4877 } 4878 4879 amdgpu_gfx_rlc_exit_safe_mode(adev); 4880 } 4881 4882 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4883 bool enable) 4884 { 4885 uint32_t def, data; 4886 4887 amdgpu_gfx_rlc_enter_safe_mode(adev); 4888 4889 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4890 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4891 /* unset CGCG override */ 4892 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4893 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4894 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4895 else 4896 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4897 /* update CGCG and CGLS override bits */ 4898 if (def != data) 4899 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4900 4901 /* enable cgcg FSM(0x0000363F) */ 4902 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4903 4904 if (adev->asic_type == CHIP_ARCTURUS) 4905 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4906 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4907 else 4908 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4909 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4910 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4911 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4912 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4913 if (def != data) 4914 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4915 4916 /* set IDLE_POLL_COUNT(0x00900100) */ 4917 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4918 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4919 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4920 if (def != data) 4921 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4922 } else { 4923 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4924 /* reset CGCG/CGLS bits */ 4925 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4926 /* disable cgcg and cgls in FSM */ 4927 if (def != data) 4928 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4929 } 4930 4931 amdgpu_gfx_rlc_exit_safe_mode(adev); 4932 } 4933 4934 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4935 bool enable) 4936 { 4937 if (enable) { 4938 /* CGCG/CGLS should be enabled after MGCG/MGLS 4939 * === MGCG + MGLS === 4940 */ 4941 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4942 /* === CGCG /CGLS for GFX 3D Only === */ 4943 gfx_v9_0_update_3d_clock_gating(adev, enable); 4944 /* === CGCG + CGLS === */ 4945 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4946 } else { 4947 /* CGCG/CGLS should be disabled before MGCG/MGLS 4948 * === CGCG + CGLS === 4949 */ 4950 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4951 /* === CGCG /CGLS for GFX 3D Only === */ 4952 gfx_v9_0_update_3d_clock_gating(adev, enable); 4953 /* === MGCG + MGLS === */ 4954 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4955 } 4956 return 0; 4957 } 4958 4959 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4960 { 4961 u32 data; 4962 4963 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4964 4965 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4966 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4967 4968 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4969 } 4970 4971 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4972 uint32_t offset, 4973 struct soc15_reg_rlcg *entries, int arr_size) 4974 { 4975 int i; 4976 uint32_t reg; 4977 4978 if (!entries) 4979 return false; 4980 4981 for (i = 0; i < arr_size; i++) { 4982 const struct soc15_reg_rlcg *entry; 4983 4984 entry = &entries[i]; 4985 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4986 if (offset == reg) 4987 return true; 4988 } 4989 4990 return false; 4991 } 4992 4993 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4994 { 4995 return gfx_v9_0_check_rlcg_range(adev, offset, 4996 (void *)rlcg_access_gc_9_0, 4997 ARRAY_SIZE(rlcg_access_gc_9_0)); 4998 } 4999 5000 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 5001 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 5002 .set_safe_mode = gfx_v9_0_set_safe_mode, 5003 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 5004 .init = gfx_v9_0_rlc_init, 5005 .get_csb_size = gfx_v9_0_get_csb_size, 5006 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 5007 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 5008 .resume = gfx_v9_0_rlc_resume, 5009 .stop = gfx_v9_0_rlc_stop, 5010 .reset = gfx_v9_0_rlc_reset, 5011 .start = gfx_v9_0_rlc_start, 5012 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 5013 .rlcg_wreg = gfx_v9_0_rlcg_wreg, 5014 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 5015 }; 5016 5017 static int gfx_v9_0_set_powergating_state(void *handle, 5018 enum amd_powergating_state state) 5019 { 5020 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5021 bool enable = (state == AMD_PG_STATE_GATE); 5022 5023 switch (adev->asic_type) { 5024 case CHIP_RAVEN: 5025 case CHIP_RENOIR: 5026 if (!enable) { 5027 amdgpu_gfx_off_ctrl(adev, false); 5028 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 5029 } 5030 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5031 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 5032 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 5033 } else { 5034 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 5035 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 5036 } 5037 5038 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5039 gfx_v9_0_enable_cp_power_gating(adev, true); 5040 else 5041 gfx_v9_0_enable_cp_power_gating(adev, false); 5042 5043 /* update gfx cgpg state */ 5044 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 5045 5046 /* update mgcg state */ 5047 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 5048 5049 if (enable) 5050 amdgpu_gfx_off_ctrl(adev, true); 5051 break; 5052 case CHIP_VEGA12: 5053 if (!enable) { 5054 amdgpu_gfx_off_ctrl(adev, false); 5055 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 5056 } else { 5057 amdgpu_gfx_off_ctrl(adev, true); 5058 } 5059 break; 5060 default: 5061 break; 5062 } 5063 5064 return 0; 5065 } 5066 5067 static int gfx_v9_0_set_clockgating_state(void *handle, 5068 enum amd_clockgating_state state) 5069 { 5070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5071 5072 if (amdgpu_sriov_vf(adev)) 5073 return 0; 5074 5075 switch (adev->asic_type) { 5076 case CHIP_VEGA10: 5077 case CHIP_VEGA12: 5078 case CHIP_VEGA20: 5079 case CHIP_RAVEN: 5080 case CHIP_ARCTURUS: 5081 case CHIP_RENOIR: 5082 gfx_v9_0_update_gfx_clock_gating(adev, 5083 state == AMD_CG_STATE_GATE); 5084 break; 5085 default: 5086 break; 5087 } 5088 return 0; 5089 } 5090 5091 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 5092 { 5093 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5094 int data; 5095 5096 if (amdgpu_sriov_vf(adev)) 5097 *flags = 0; 5098 5099 /* AMD_CG_SUPPORT_GFX_MGCG */ 5100 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5101 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5102 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5103 5104 /* AMD_CG_SUPPORT_GFX_CGCG */ 5105 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5106 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5107 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5108 5109 /* AMD_CG_SUPPORT_GFX_CGLS */ 5110 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5111 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5112 5113 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5114 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5115 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5116 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5117 5118 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5119 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5120 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5121 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5122 5123 if (adev->asic_type != CHIP_ARCTURUS) { 5124 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5125 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5126 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5127 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5128 5129 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5130 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5131 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5132 } 5133 } 5134 5135 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5136 { 5137 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 5138 } 5139 5140 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5141 { 5142 struct amdgpu_device *adev = ring->adev; 5143 u64 wptr; 5144 5145 /* XXX check if swapping is necessary on BE */ 5146 if (ring->use_doorbell) { 5147 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 5148 } else { 5149 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5150 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5151 } 5152 5153 return wptr; 5154 } 5155 5156 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5157 { 5158 struct amdgpu_device *adev = ring->adev; 5159 5160 if (ring->use_doorbell) { 5161 /* XXX check if swapping is necessary on BE */ 5162 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5163 WDOORBELL64(ring->doorbell_index, ring->wptr); 5164 } else { 5165 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5166 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5167 } 5168 } 5169 5170 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5171 { 5172 struct amdgpu_device *adev = ring->adev; 5173 u32 ref_and_mask, reg_mem_engine; 5174 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5175 5176 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5177 switch (ring->me) { 5178 case 1: 5179 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5180 break; 5181 case 2: 5182 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5183 break; 5184 default: 5185 return; 5186 } 5187 reg_mem_engine = 0; 5188 } else { 5189 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5190 reg_mem_engine = 1; /* pfp */ 5191 } 5192 5193 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5194 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5195 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5196 ref_and_mask, ref_and_mask, 0x20); 5197 } 5198 5199 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5200 struct amdgpu_job *job, 5201 struct amdgpu_ib *ib, 5202 uint32_t flags) 5203 { 5204 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5205 u32 header, control = 0; 5206 5207 if (ib->flags & AMDGPU_IB_FLAG_CE) 5208 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5209 else 5210 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5211 5212 control |= ib->length_dw | (vmid << 24); 5213 5214 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5215 control |= INDIRECT_BUFFER_PRE_ENB(1); 5216 5217 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5218 gfx_v9_0_ring_emit_de_meta(ring); 5219 } 5220 5221 amdgpu_ring_write(ring, header); 5222 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5223 amdgpu_ring_write(ring, 5224 #ifdef __BIG_ENDIAN 5225 (2 << 0) | 5226 #endif 5227 lower_32_bits(ib->gpu_addr)); 5228 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5229 amdgpu_ring_write(ring, control); 5230 } 5231 5232 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5233 struct amdgpu_job *job, 5234 struct amdgpu_ib *ib, 5235 uint32_t flags) 5236 { 5237 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5238 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5239 5240 /* Currently, there is a high possibility to get wave ID mismatch 5241 * between ME and GDS, leading to a hw deadlock, because ME generates 5242 * different wave IDs than the GDS expects. This situation happens 5243 * randomly when at least 5 compute pipes use GDS ordered append. 5244 * The wave IDs generated by ME are also wrong after suspend/resume. 5245 * Those are probably bugs somewhere else in the kernel driver. 5246 * 5247 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5248 * GDS to 0 for this ring (me/pipe). 5249 */ 5250 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5251 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5252 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5253 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5254 } 5255 5256 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5257 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5258 amdgpu_ring_write(ring, 5259 #ifdef __BIG_ENDIAN 5260 (2 << 0) | 5261 #endif 5262 lower_32_bits(ib->gpu_addr)); 5263 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5264 amdgpu_ring_write(ring, control); 5265 } 5266 5267 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5268 u64 seq, unsigned flags) 5269 { 5270 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5271 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5272 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5273 5274 /* RELEASE_MEM - flush caches, send int */ 5275 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5276 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 5277 EOP_TC_NC_ACTION_EN) : 5278 (EOP_TCL1_ACTION_EN | 5279 EOP_TC_ACTION_EN | 5280 EOP_TC_WB_ACTION_EN | 5281 EOP_TC_MD_ACTION_EN)) | 5282 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5283 EVENT_INDEX(5))); 5284 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5285 5286 /* 5287 * the address should be Qword aligned if 64bit write, Dword 5288 * aligned if only send 32bit data low (discard data high) 5289 */ 5290 if (write64bit) 5291 BUG_ON(addr & 0x7); 5292 else 5293 BUG_ON(addr & 0x3); 5294 amdgpu_ring_write(ring, lower_32_bits(addr)); 5295 amdgpu_ring_write(ring, upper_32_bits(addr)); 5296 amdgpu_ring_write(ring, lower_32_bits(seq)); 5297 amdgpu_ring_write(ring, upper_32_bits(seq)); 5298 amdgpu_ring_write(ring, 0); 5299 } 5300 5301 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5302 { 5303 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5304 uint32_t seq = ring->fence_drv.sync_seq; 5305 uint64_t addr = ring->fence_drv.gpu_addr; 5306 5307 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5308 lower_32_bits(addr), upper_32_bits(addr), 5309 seq, 0xffffffff, 4); 5310 } 5311 5312 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5313 unsigned vmid, uint64_t pd_addr) 5314 { 5315 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5316 5317 /* compute doesn't have PFP */ 5318 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5319 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5320 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5321 amdgpu_ring_write(ring, 0x0); 5322 } 5323 } 5324 5325 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5326 { 5327 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 5328 } 5329 5330 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5331 { 5332 u64 wptr; 5333 5334 /* XXX check if swapping is necessary on BE */ 5335 if (ring->use_doorbell) 5336 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 5337 else 5338 BUG(); 5339 return wptr; 5340 } 5341 5342 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5343 { 5344 struct amdgpu_device *adev = ring->adev; 5345 5346 /* XXX check if swapping is necessary on BE */ 5347 if (ring->use_doorbell) { 5348 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5349 WDOORBELL64(ring->doorbell_index, ring->wptr); 5350 } else{ 5351 BUG(); /* only DOORBELL method supported on gfx9 now */ 5352 } 5353 } 5354 5355 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5356 u64 seq, unsigned int flags) 5357 { 5358 struct amdgpu_device *adev = ring->adev; 5359 5360 /* we only allocate 32bit for each seq wb address */ 5361 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5362 5363 /* write fence seq to the "addr" */ 5364 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5365 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5366 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5367 amdgpu_ring_write(ring, lower_32_bits(addr)); 5368 amdgpu_ring_write(ring, upper_32_bits(addr)); 5369 amdgpu_ring_write(ring, lower_32_bits(seq)); 5370 5371 if (flags & AMDGPU_FENCE_FLAG_INT) { 5372 /* set register to trigger INT */ 5373 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5374 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5375 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5376 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5377 amdgpu_ring_write(ring, 0); 5378 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5379 } 5380 } 5381 5382 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5383 { 5384 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5385 amdgpu_ring_write(ring, 0); 5386 } 5387 5388 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 5389 { 5390 struct v9_ce_ib_state ce_payload = {0}; 5391 uint64_t csa_addr; 5392 int cnt; 5393 5394 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5395 csa_addr = amdgpu_csa_vaddr(ring->adev); 5396 5397 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5398 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5399 WRITE_DATA_DST_SEL(8) | 5400 WR_CONFIRM) | 5401 WRITE_DATA_CACHE_POLICY(0)); 5402 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5403 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5404 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 5405 } 5406 5407 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 5408 { 5409 struct v9_de_ib_state de_payload = {0}; 5410 uint64_t csa_addr, gds_addr; 5411 int cnt; 5412 5413 csa_addr = amdgpu_csa_vaddr(ring->adev); 5414 gds_addr = csa_addr + 4096; 5415 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5416 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5417 5418 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5419 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5420 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5421 WRITE_DATA_DST_SEL(8) | 5422 WR_CONFIRM) | 5423 WRITE_DATA_CACHE_POLICY(0)); 5424 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5425 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5426 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 5427 } 5428 5429 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 5430 { 5431 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5432 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 5433 } 5434 5435 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5436 { 5437 uint32_t dw2 = 0; 5438 5439 if (amdgpu_sriov_vf(ring->adev)) 5440 gfx_v9_0_ring_emit_ce_meta(ring); 5441 5442 gfx_v9_0_ring_emit_tmz(ring, true); 5443 5444 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5445 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5446 /* set load_global_config & load_global_uconfig */ 5447 dw2 |= 0x8001; 5448 /* set load_cs_sh_regs */ 5449 dw2 |= 0x01000000; 5450 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5451 dw2 |= 0x10002; 5452 5453 /* set load_ce_ram if preamble presented */ 5454 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5455 dw2 |= 0x10000000; 5456 } else { 5457 /* still load_ce_ram if this is the first time preamble presented 5458 * although there is no context switch happens. 5459 */ 5460 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5461 dw2 |= 0x10000000; 5462 } 5463 5464 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5465 amdgpu_ring_write(ring, dw2); 5466 amdgpu_ring_write(ring, 0); 5467 } 5468 5469 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5470 { 5471 unsigned ret; 5472 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5473 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5474 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5475 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5476 ret = ring->wptr & ring->buf_mask; 5477 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5478 return ret; 5479 } 5480 5481 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5482 { 5483 unsigned cur; 5484 BUG_ON(offset > ring->buf_mask); 5485 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5486 5487 cur = (ring->wptr & ring->buf_mask) - 1; 5488 if (likely(cur > offset)) 5489 ring->ring[offset] = cur - offset; 5490 else 5491 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5492 } 5493 5494 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 5495 { 5496 struct amdgpu_device *adev = ring->adev; 5497 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5498 5499 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5500 amdgpu_ring_write(ring, 0 | /* src: register*/ 5501 (5 << 8) | /* dst: memory */ 5502 (1 << 20)); /* write confirm */ 5503 amdgpu_ring_write(ring, reg); 5504 amdgpu_ring_write(ring, 0); 5505 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5506 kiq->reg_val_offs * 4)); 5507 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5508 kiq->reg_val_offs * 4)); 5509 } 5510 5511 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5512 uint32_t val) 5513 { 5514 uint32_t cmd = 0; 5515 5516 switch (ring->funcs->type) { 5517 case AMDGPU_RING_TYPE_GFX: 5518 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5519 break; 5520 case AMDGPU_RING_TYPE_KIQ: 5521 cmd = (1 << 16); /* no inc addr */ 5522 break; 5523 default: 5524 cmd = WR_CONFIRM; 5525 break; 5526 } 5527 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5528 amdgpu_ring_write(ring, cmd); 5529 amdgpu_ring_write(ring, reg); 5530 amdgpu_ring_write(ring, 0); 5531 amdgpu_ring_write(ring, val); 5532 } 5533 5534 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5535 uint32_t val, uint32_t mask) 5536 { 5537 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5538 } 5539 5540 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5541 uint32_t reg0, uint32_t reg1, 5542 uint32_t ref, uint32_t mask) 5543 { 5544 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5545 struct amdgpu_device *adev = ring->adev; 5546 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5547 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5548 5549 if (fw_version_ok) 5550 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5551 ref, mask, 0x20); 5552 else 5553 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5554 ref, mask); 5555 } 5556 5557 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5558 { 5559 struct amdgpu_device *adev = ring->adev; 5560 uint32_t value = 0; 5561 5562 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5563 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5564 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5565 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5566 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5567 } 5568 5569 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5570 enum amdgpu_interrupt_state state) 5571 { 5572 switch (state) { 5573 case AMDGPU_IRQ_STATE_DISABLE: 5574 case AMDGPU_IRQ_STATE_ENABLE: 5575 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5576 TIME_STAMP_INT_ENABLE, 5577 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5578 break; 5579 default: 5580 break; 5581 } 5582 } 5583 5584 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5585 int me, int pipe, 5586 enum amdgpu_interrupt_state state) 5587 { 5588 u32 mec_int_cntl, mec_int_cntl_reg; 5589 5590 /* 5591 * amdgpu controls only the first MEC. That's why this function only 5592 * handles the setting of interrupts for this specific MEC. All other 5593 * pipes' interrupts are set by amdkfd. 5594 */ 5595 5596 if (me == 1) { 5597 switch (pipe) { 5598 case 0: 5599 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5600 break; 5601 case 1: 5602 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5603 break; 5604 case 2: 5605 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5606 break; 5607 case 3: 5608 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5609 break; 5610 default: 5611 DRM_DEBUG("invalid pipe %d\n", pipe); 5612 return; 5613 } 5614 } else { 5615 DRM_DEBUG("invalid me %d\n", me); 5616 return; 5617 } 5618 5619 switch (state) { 5620 case AMDGPU_IRQ_STATE_DISABLE: 5621 mec_int_cntl = RREG32(mec_int_cntl_reg); 5622 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5623 TIME_STAMP_INT_ENABLE, 0); 5624 WREG32(mec_int_cntl_reg, mec_int_cntl); 5625 break; 5626 case AMDGPU_IRQ_STATE_ENABLE: 5627 mec_int_cntl = RREG32(mec_int_cntl_reg); 5628 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5629 TIME_STAMP_INT_ENABLE, 1); 5630 WREG32(mec_int_cntl_reg, mec_int_cntl); 5631 break; 5632 default: 5633 break; 5634 } 5635 } 5636 5637 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5638 struct amdgpu_irq_src *source, 5639 unsigned type, 5640 enum amdgpu_interrupt_state state) 5641 { 5642 switch (state) { 5643 case AMDGPU_IRQ_STATE_DISABLE: 5644 case AMDGPU_IRQ_STATE_ENABLE: 5645 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5646 PRIV_REG_INT_ENABLE, 5647 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5648 break; 5649 default: 5650 break; 5651 } 5652 5653 return 0; 5654 } 5655 5656 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5657 struct amdgpu_irq_src *source, 5658 unsigned type, 5659 enum amdgpu_interrupt_state state) 5660 { 5661 switch (state) { 5662 case AMDGPU_IRQ_STATE_DISABLE: 5663 case AMDGPU_IRQ_STATE_ENABLE: 5664 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5665 PRIV_INSTR_INT_ENABLE, 5666 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5667 default: 5668 break; 5669 } 5670 5671 return 0; 5672 } 5673 5674 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5675 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5676 CP_ECC_ERROR_INT_ENABLE, 1) 5677 5678 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5679 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5680 CP_ECC_ERROR_INT_ENABLE, 0) 5681 5682 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5683 struct amdgpu_irq_src *source, 5684 unsigned type, 5685 enum amdgpu_interrupt_state state) 5686 { 5687 switch (state) { 5688 case AMDGPU_IRQ_STATE_DISABLE: 5689 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5690 CP_ECC_ERROR_INT_ENABLE, 0); 5691 DISABLE_ECC_ON_ME_PIPE(1, 0); 5692 DISABLE_ECC_ON_ME_PIPE(1, 1); 5693 DISABLE_ECC_ON_ME_PIPE(1, 2); 5694 DISABLE_ECC_ON_ME_PIPE(1, 3); 5695 break; 5696 5697 case AMDGPU_IRQ_STATE_ENABLE: 5698 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5699 CP_ECC_ERROR_INT_ENABLE, 1); 5700 ENABLE_ECC_ON_ME_PIPE(1, 0); 5701 ENABLE_ECC_ON_ME_PIPE(1, 1); 5702 ENABLE_ECC_ON_ME_PIPE(1, 2); 5703 ENABLE_ECC_ON_ME_PIPE(1, 3); 5704 break; 5705 default: 5706 break; 5707 } 5708 5709 return 0; 5710 } 5711 5712 5713 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5714 struct amdgpu_irq_src *src, 5715 unsigned type, 5716 enum amdgpu_interrupt_state state) 5717 { 5718 switch (type) { 5719 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5720 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5721 break; 5722 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5723 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5724 break; 5725 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5726 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5727 break; 5728 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5729 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5730 break; 5731 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5732 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5733 break; 5734 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5735 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5736 break; 5737 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5738 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5739 break; 5740 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5741 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5742 break; 5743 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5744 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5745 break; 5746 default: 5747 break; 5748 } 5749 return 0; 5750 } 5751 5752 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5753 struct amdgpu_irq_src *source, 5754 struct amdgpu_iv_entry *entry) 5755 { 5756 int i; 5757 u8 me_id, pipe_id, queue_id; 5758 struct amdgpu_ring *ring; 5759 5760 DRM_DEBUG("IH: CP EOP\n"); 5761 me_id = (entry->ring_id & 0x0c) >> 2; 5762 pipe_id = (entry->ring_id & 0x03) >> 0; 5763 queue_id = (entry->ring_id & 0x70) >> 4; 5764 5765 switch (me_id) { 5766 case 0: 5767 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5768 break; 5769 case 1: 5770 case 2: 5771 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5772 ring = &adev->gfx.compute_ring[i]; 5773 /* Per-queue interrupt is supported for MEC starting from VI. 5774 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5775 */ 5776 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5777 amdgpu_fence_process(ring); 5778 } 5779 break; 5780 } 5781 return 0; 5782 } 5783 5784 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5785 struct amdgpu_iv_entry *entry) 5786 { 5787 u8 me_id, pipe_id, queue_id; 5788 struct amdgpu_ring *ring; 5789 int i; 5790 5791 me_id = (entry->ring_id & 0x0c) >> 2; 5792 pipe_id = (entry->ring_id & 0x03) >> 0; 5793 queue_id = (entry->ring_id & 0x70) >> 4; 5794 5795 switch (me_id) { 5796 case 0: 5797 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5798 break; 5799 case 1: 5800 case 2: 5801 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5802 ring = &adev->gfx.compute_ring[i]; 5803 if (ring->me == me_id && ring->pipe == pipe_id && 5804 ring->queue == queue_id) 5805 drm_sched_fault(&ring->sched); 5806 } 5807 break; 5808 } 5809 } 5810 5811 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5812 struct amdgpu_irq_src *source, 5813 struct amdgpu_iv_entry *entry) 5814 { 5815 DRM_ERROR("Illegal register access in command stream\n"); 5816 gfx_v9_0_fault(adev, entry); 5817 return 0; 5818 } 5819 5820 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5821 struct amdgpu_irq_src *source, 5822 struct amdgpu_iv_entry *entry) 5823 { 5824 DRM_ERROR("Illegal instruction in command stream\n"); 5825 gfx_v9_0_fault(adev, entry); 5826 return 0; 5827 } 5828 5829 5830 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5831 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5832 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5833 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5834 }, 5835 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5836 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5837 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5838 }, 5839 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5840 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5841 0, 0 5842 }, 5843 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5844 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5845 0, 0 5846 }, 5847 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5848 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5849 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5850 }, 5851 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5852 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5853 0, 0 5854 }, 5855 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5856 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5857 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5858 }, 5859 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5860 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5861 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5862 }, 5863 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5864 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5865 0, 0 5866 }, 5867 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5868 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5869 0, 0 5870 }, 5871 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5872 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5873 0, 0 5874 }, 5875 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5876 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5877 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5878 }, 5879 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5880 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5881 0, 0 5882 }, 5883 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5884 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5885 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5886 }, 5887 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5888 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5889 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5890 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5891 }, 5892 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5893 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5894 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5895 0, 0 5896 }, 5897 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5898 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5899 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5900 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5901 }, 5902 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5903 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5904 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5905 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5906 }, 5907 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5908 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5909 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5910 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5911 }, 5912 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5913 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5914 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5915 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5916 }, 5917 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5918 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5919 0, 0 5920 }, 5921 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5922 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5923 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5924 }, 5925 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5926 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5927 0, 0 5928 }, 5929 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5930 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5931 0, 0 5932 }, 5933 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5934 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 5935 0, 0 5936 }, 5937 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5938 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 5939 0, 0 5940 }, 5941 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5942 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 5943 0, 0 5944 }, 5945 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5946 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 5947 0, 0 5948 }, 5949 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5950 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 5951 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 5952 }, 5953 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5954 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 5955 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 5956 }, 5957 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5958 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 5959 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 5960 }, 5961 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5962 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 5963 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 5964 }, 5965 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5966 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 5967 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 5968 }, 5969 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5970 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 5971 0, 0 5972 }, 5973 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5974 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 5975 0, 0 5976 }, 5977 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5978 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 5979 0, 0 5980 }, 5981 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5982 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 5983 0, 0 5984 }, 5985 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5986 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 5987 0, 0 5988 }, 5989 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5990 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 5991 0, 0 5992 }, 5993 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5994 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 5995 0, 0 5996 }, 5997 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 5998 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 5999 0, 0 6000 }, 6001 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6002 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6003 0, 0 6004 }, 6005 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6006 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6007 0, 0 6008 }, 6009 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6010 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6011 0, 0 6012 }, 6013 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6014 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6015 0, 0 6016 }, 6017 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6018 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6019 0, 0 6020 }, 6021 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6022 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6023 0, 0 6024 }, 6025 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6026 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6027 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6028 }, 6029 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6030 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6031 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6032 }, 6033 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6034 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6035 0, 0 6036 }, 6037 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6038 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6039 0, 0 6040 }, 6041 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6042 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6043 0, 0 6044 }, 6045 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6046 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6047 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6048 }, 6049 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6050 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6051 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6052 }, 6053 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6054 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6055 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6056 }, 6057 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6058 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6059 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6060 }, 6061 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6062 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6063 0, 0 6064 }, 6065 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6066 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6067 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6068 }, 6069 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6070 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6071 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6072 }, 6073 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6074 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6075 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6076 }, 6077 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6078 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6079 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6080 }, 6081 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6082 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6083 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6084 }, 6085 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6086 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6087 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6088 }, 6089 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6090 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6091 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6092 }, 6093 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6094 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6095 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6096 }, 6097 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6098 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6099 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6100 }, 6101 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6102 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6103 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6104 }, 6105 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6106 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6107 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6108 }, 6109 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6110 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6111 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6112 }, 6113 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6114 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6115 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6116 }, 6117 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6118 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6119 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6120 }, 6121 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6122 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6123 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6124 }, 6125 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6126 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6127 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6128 }, 6129 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6130 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6131 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6132 }, 6133 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6134 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6135 0, 0 6136 }, 6137 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6138 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6139 0, 0 6140 }, 6141 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6142 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6143 0, 0 6144 }, 6145 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6146 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6147 0, 0 6148 }, 6149 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6150 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6151 0, 0 6152 }, 6153 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6154 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6155 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6156 }, 6157 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6158 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6159 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6160 }, 6161 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6162 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6163 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6164 }, 6165 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6166 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6167 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6168 }, 6169 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6170 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6171 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6172 }, 6173 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6174 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6175 0, 0 6176 }, 6177 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6178 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6179 0, 0 6180 }, 6181 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6182 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6183 0, 0 6184 }, 6185 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6186 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6187 0, 0 6188 }, 6189 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6190 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6191 0, 0 6192 }, 6193 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6194 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6195 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6196 }, 6197 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6198 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6199 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6200 }, 6201 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6202 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6203 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6204 }, 6205 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6206 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6207 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6208 }, 6209 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6210 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6211 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6212 }, 6213 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6214 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6215 0, 0 6216 }, 6217 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6218 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6219 0, 0 6220 }, 6221 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6222 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6223 0, 0 6224 }, 6225 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6226 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6227 0, 0 6228 }, 6229 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6230 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6231 0, 0 6232 }, 6233 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6234 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6235 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6236 }, 6237 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6238 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6239 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6240 }, 6241 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6242 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6243 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6244 }, 6245 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6246 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6247 0, 0 6248 }, 6249 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6250 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6251 0, 0 6252 }, 6253 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6254 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6255 0, 0 6256 }, 6257 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6258 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6259 0, 0 6260 }, 6261 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6262 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6263 0, 0 6264 }, 6265 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6266 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6267 0, 0 6268 } 6269 }; 6270 6271 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6272 void *inject_if) 6273 { 6274 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6275 int ret; 6276 struct ta_ras_trigger_error_input block_info = { 0 }; 6277 6278 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6279 return -EINVAL; 6280 6281 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6282 return -EINVAL; 6283 6284 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6285 return -EPERM; 6286 6287 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6288 info->head.type)) { 6289 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6290 ras_gfx_subblocks[info->head.sub_block_index].name, 6291 info->head.type); 6292 return -EPERM; 6293 } 6294 6295 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6296 info->head.type)) { 6297 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6298 ras_gfx_subblocks[info->head.sub_block_index].name, 6299 info->head.type); 6300 return -EPERM; 6301 } 6302 6303 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6304 block_info.sub_block_index = 6305 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6306 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6307 block_info.address = info->address; 6308 block_info.value = info->value; 6309 6310 mutex_lock(&adev->grbm_idx_mutex); 6311 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6312 mutex_unlock(&adev->grbm_idx_mutex); 6313 6314 return ret; 6315 } 6316 6317 static const char *vml2_mems[] = { 6318 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6319 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6320 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6321 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6322 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6323 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6324 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6325 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6326 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6327 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6328 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6329 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6330 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6331 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6332 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6333 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6334 }; 6335 6336 static const char *vml2_walker_mems[] = { 6337 "UTC_VML2_CACHE_PDE0_MEM0", 6338 "UTC_VML2_CACHE_PDE0_MEM1", 6339 "UTC_VML2_CACHE_PDE1_MEM0", 6340 "UTC_VML2_CACHE_PDE1_MEM1", 6341 "UTC_VML2_CACHE_PDE2_MEM0", 6342 "UTC_VML2_CACHE_PDE2_MEM1", 6343 "UTC_VML2_RDIF_LOG_FIFO", 6344 }; 6345 6346 static const char *atc_l2_cache_2m_mems[] = { 6347 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6348 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6349 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6350 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6351 }; 6352 6353 static const char *atc_l2_cache_4k_mems[] = { 6354 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6355 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6356 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6357 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6358 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6359 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6360 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6361 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6362 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6363 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6364 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6365 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6366 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6367 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6368 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6369 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6370 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6371 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6372 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6373 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6374 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6375 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6376 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6377 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6378 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6379 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6380 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6381 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6382 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6383 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6384 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6385 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6386 }; 6387 6388 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6389 struct ras_err_data *err_data) 6390 { 6391 uint32_t i, data; 6392 uint32_t sec_count, ded_count; 6393 6394 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6395 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6396 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6397 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6398 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6399 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6400 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6401 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6402 6403 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6404 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6405 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6406 6407 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6408 if (sec_count) { 6409 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6410 vml2_mems[i], sec_count); 6411 err_data->ce_count += sec_count; 6412 } 6413 6414 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6415 if (ded_count) { 6416 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6417 vml2_mems[i], ded_count); 6418 err_data->ue_count += ded_count; 6419 } 6420 } 6421 6422 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6423 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6424 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6425 6426 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6427 SEC_COUNT); 6428 if (sec_count) { 6429 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6430 vml2_walker_mems[i], sec_count); 6431 err_data->ce_count += sec_count; 6432 } 6433 6434 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6435 DED_COUNT); 6436 if (ded_count) { 6437 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6438 vml2_walker_mems[i], ded_count); 6439 err_data->ue_count += ded_count; 6440 } 6441 } 6442 6443 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6444 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6445 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6446 6447 sec_count = (data & 0x00006000L) >> 0xd; 6448 if (sec_count) { 6449 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6450 atc_l2_cache_2m_mems[i], sec_count); 6451 err_data->ce_count += sec_count; 6452 } 6453 } 6454 6455 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6456 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6457 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6458 6459 sec_count = (data & 0x00006000L) >> 0xd; 6460 if (sec_count) { 6461 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6462 atc_l2_cache_4k_mems[i], sec_count); 6463 err_data->ce_count += sec_count; 6464 } 6465 6466 ded_count = (data & 0x00018000L) >> 0xf; 6467 if (ded_count) { 6468 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6469 atc_l2_cache_4k_mems[i], ded_count); 6470 err_data->ue_count += ded_count; 6471 } 6472 } 6473 6474 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6475 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6476 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6477 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6478 6479 return 0; 6480 } 6481 6482 static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg, 6483 uint32_t se_id, uint32_t inst_id, uint32_t value, 6484 uint32_t *sec_count, uint32_t *ded_count) 6485 { 6486 uint32_t i; 6487 uint32_t sec_cnt, ded_cnt; 6488 6489 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6490 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6491 gfx_v9_0_ras_fields[i].seg != reg->seg || 6492 gfx_v9_0_ras_fields[i].inst != reg->inst) 6493 continue; 6494 6495 sec_cnt = (value & 6496 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6497 gfx_v9_0_ras_fields[i].sec_count_shift; 6498 if (sec_cnt) { 6499 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n", 6500 gfx_v9_0_ras_fields[i].name, 6501 se_id, inst_id, 6502 sec_cnt); 6503 *sec_count += sec_cnt; 6504 } 6505 6506 ded_cnt = (value & 6507 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6508 gfx_v9_0_ras_fields[i].ded_count_shift; 6509 if (ded_cnt) { 6510 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n", 6511 gfx_v9_0_ras_fields[i].name, 6512 se_id, inst_id, 6513 ded_cnt); 6514 *ded_count += ded_cnt; 6515 } 6516 } 6517 6518 return 0; 6519 } 6520 6521 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6522 { 6523 int i, j, k; 6524 6525 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6526 return; 6527 6528 /* read back registers to clear the counters */ 6529 mutex_lock(&adev->grbm_idx_mutex); 6530 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6531 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6532 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6533 gfx_v9_0_select_se_sh(adev, j, 0x0, k); 6534 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6535 } 6536 } 6537 } 6538 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6539 mutex_unlock(&adev->grbm_idx_mutex); 6540 6541 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6542 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6543 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6544 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6545 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6546 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6547 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6548 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6549 6550 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6551 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6552 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6553 } 6554 6555 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6556 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6557 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6558 } 6559 6560 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6561 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6562 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6563 } 6564 6565 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6566 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6567 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6568 } 6569 6570 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6571 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6572 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6573 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6574 } 6575 6576 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6577 void *ras_error_status) 6578 { 6579 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6580 uint32_t sec_count = 0, ded_count = 0; 6581 uint32_t i, j, k; 6582 uint32_t reg_value; 6583 6584 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6585 return -EINVAL; 6586 6587 err_data->ue_count = 0; 6588 err_data->ce_count = 0; 6589 6590 mutex_lock(&adev->grbm_idx_mutex); 6591 6592 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6593 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6594 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6595 gfx_v9_0_select_se_sh(adev, j, 0, k); 6596 reg_value = 6597 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6598 if (reg_value) 6599 gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs[i], 6600 j, k, reg_value, 6601 &sec_count, &ded_count); 6602 } 6603 } 6604 } 6605 6606 err_data->ce_count += sec_count; 6607 err_data->ue_count += ded_count; 6608 6609 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6610 mutex_unlock(&adev->grbm_idx_mutex); 6611 6612 gfx_v9_0_query_utc_edc_status(adev, err_data); 6613 6614 return 0; 6615 } 6616 6617 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6618 .name = "gfx_v9_0", 6619 .early_init = gfx_v9_0_early_init, 6620 .late_init = gfx_v9_0_late_init, 6621 .sw_init = gfx_v9_0_sw_init, 6622 .sw_fini = gfx_v9_0_sw_fini, 6623 .hw_init = gfx_v9_0_hw_init, 6624 .hw_fini = gfx_v9_0_hw_fini, 6625 .suspend = gfx_v9_0_suspend, 6626 .resume = gfx_v9_0_resume, 6627 .is_idle = gfx_v9_0_is_idle, 6628 .wait_for_idle = gfx_v9_0_wait_for_idle, 6629 .soft_reset = gfx_v9_0_soft_reset, 6630 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6631 .set_powergating_state = gfx_v9_0_set_powergating_state, 6632 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6633 }; 6634 6635 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6636 .type = AMDGPU_RING_TYPE_GFX, 6637 .align_mask = 0xff, 6638 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6639 .support_64bit_ptrs = true, 6640 .vmhub = AMDGPU_GFXHUB_0, 6641 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6642 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6643 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6644 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6645 5 + /* COND_EXEC */ 6646 7 + /* PIPELINE_SYNC */ 6647 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6648 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6649 2 + /* VM_FLUSH */ 6650 8 + /* FENCE for VM_FLUSH */ 6651 20 + /* GDS switch */ 6652 4 + /* double SWITCH_BUFFER, 6653 the first COND_EXEC jump to the place just 6654 prior to this double SWITCH_BUFFER */ 6655 5 + /* COND_EXEC */ 6656 7 + /* HDP_flush */ 6657 4 + /* VGT_flush */ 6658 14 + /* CE_META */ 6659 31 + /* DE_META */ 6660 3 + /* CNTX_CTRL */ 6661 5 + /* HDP_INVL */ 6662 8 + 8 + /* FENCE x2 */ 6663 2, /* SWITCH_BUFFER */ 6664 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6665 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6666 .emit_fence = gfx_v9_0_ring_emit_fence, 6667 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6668 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6669 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6670 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6671 .test_ring = gfx_v9_0_ring_test_ring, 6672 .test_ib = gfx_v9_0_ring_test_ib, 6673 .insert_nop = amdgpu_ring_insert_nop, 6674 .pad_ib = amdgpu_ring_generic_pad_ib, 6675 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6676 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6677 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6678 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6679 .emit_tmz = gfx_v9_0_ring_emit_tmz, 6680 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6681 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6682 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6683 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6684 }; 6685 6686 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6687 .type = AMDGPU_RING_TYPE_COMPUTE, 6688 .align_mask = 0xff, 6689 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6690 .support_64bit_ptrs = true, 6691 .vmhub = AMDGPU_GFXHUB_0, 6692 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6693 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6694 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6695 .emit_frame_size = 6696 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6697 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6698 5 + /* hdp invalidate */ 6699 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6700 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6701 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6702 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6703 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6704 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6705 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6706 .emit_fence = gfx_v9_0_ring_emit_fence, 6707 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6708 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6709 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6710 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6711 .test_ring = gfx_v9_0_ring_test_ring, 6712 .test_ib = gfx_v9_0_ring_test_ib, 6713 .insert_nop = amdgpu_ring_insert_nop, 6714 .pad_ib = amdgpu_ring_generic_pad_ib, 6715 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6716 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6717 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6718 }; 6719 6720 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6721 .type = AMDGPU_RING_TYPE_KIQ, 6722 .align_mask = 0xff, 6723 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6724 .support_64bit_ptrs = true, 6725 .vmhub = AMDGPU_GFXHUB_0, 6726 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6727 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6728 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6729 .emit_frame_size = 6730 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6731 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6732 5 + /* hdp invalidate */ 6733 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6734 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6735 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6736 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6737 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6738 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6739 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6740 .test_ring = gfx_v9_0_ring_test_ring, 6741 .insert_nop = amdgpu_ring_insert_nop, 6742 .pad_ib = amdgpu_ring_generic_pad_ib, 6743 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6744 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6745 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6746 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6747 }; 6748 6749 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6750 { 6751 int i; 6752 6753 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6754 6755 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6756 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6757 6758 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6759 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6760 } 6761 6762 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6763 .set = gfx_v9_0_set_eop_interrupt_state, 6764 .process = gfx_v9_0_eop_irq, 6765 }; 6766 6767 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6768 .set = gfx_v9_0_set_priv_reg_fault_state, 6769 .process = gfx_v9_0_priv_reg_irq, 6770 }; 6771 6772 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6773 .set = gfx_v9_0_set_priv_inst_fault_state, 6774 .process = gfx_v9_0_priv_inst_irq, 6775 }; 6776 6777 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6778 .set = gfx_v9_0_set_cp_ecc_error_state, 6779 .process = amdgpu_gfx_cp_ecc_error_irq, 6780 }; 6781 6782 6783 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6784 { 6785 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6786 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 6787 6788 adev->gfx.priv_reg_irq.num_types = 1; 6789 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 6790 6791 adev->gfx.priv_inst_irq.num_types = 1; 6792 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 6793 6794 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 6795 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 6796 } 6797 6798 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 6799 { 6800 switch (adev->asic_type) { 6801 case CHIP_VEGA10: 6802 case CHIP_VEGA12: 6803 case CHIP_VEGA20: 6804 case CHIP_RAVEN: 6805 case CHIP_ARCTURUS: 6806 case CHIP_RENOIR: 6807 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 6808 break; 6809 default: 6810 break; 6811 } 6812 } 6813 6814 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 6815 { 6816 /* init asci gds info */ 6817 switch (adev->asic_type) { 6818 case CHIP_VEGA10: 6819 case CHIP_VEGA12: 6820 case CHIP_VEGA20: 6821 adev->gds.gds_size = 0x10000; 6822 break; 6823 case CHIP_RAVEN: 6824 case CHIP_ARCTURUS: 6825 adev->gds.gds_size = 0x1000; 6826 break; 6827 default: 6828 adev->gds.gds_size = 0x10000; 6829 break; 6830 } 6831 6832 switch (adev->asic_type) { 6833 case CHIP_VEGA10: 6834 case CHIP_VEGA20: 6835 adev->gds.gds_compute_max_wave_id = 0x7ff; 6836 break; 6837 case CHIP_VEGA12: 6838 adev->gds.gds_compute_max_wave_id = 0x27f; 6839 break; 6840 case CHIP_RAVEN: 6841 if (adev->rev_id >= 0x8) 6842 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 6843 else 6844 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 6845 break; 6846 case CHIP_ARCTURUS: 6847 adev->gds.gds_compute_max_wave_id = 0xfff; 6848 break; 6849 default: 6850 /* this really depends on the chip */ 6851 adev->gds.gds_compute_max_wave_id = 0x7ff; 6852 break; 6853 } 6854 6855 adev->gds.gws_size = 64; 6856 adev->gds.oa_size = 16; 6857 } 6858 6859 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 6860 u32 bitmap) 6861 { 6862 u32 data; 6863 6864 if (!bitmap) 6865 return; 6866 6867 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6868 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6869 6870 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 6871 } 6872 6873 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 6874 { 6875 u32 data, mask; 6876 6877 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 6878 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 6879 6880 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6881 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6882 6883 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 6884 6885 return (~data) & mask; 6886 } 6887 6888 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 6889 struct amdgpu_cu_info *cu_info) 6890 { 6891 int i, j, k, counter, active_cu_number = 0; 6892 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 6893 unsigned disable_masks[4 * 4]; 6894 6895 if (!adev || !cu_info) 6896 return -EINVAL; 6897 6898 /* 6899 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 6900 */ 6901 if (adev->gfx.config.max_shader_engines * 6902 adev->gfx.config.max_sh_per_se > 16) 6903 return -EINVAL; 6904 6905 amdgpu_gfx_parse_disable_cu(disable_masks, 6906 adev->gfx.config.max_shader_engines, 6907 adev->gfx.config.max_sh_per_se); 6908 6909 mutex_lock(&adev->grbm_idx_mutex); 6910 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6911 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6912 mask = 1; 6913 ao_bitmap = 0; 6914 counter = 0; 6915 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 6916 gfx_v9_0_set_user_cu_inactive_bitmap( 6917 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 6918 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 6919 6920 /* 6921 * The bitmap(and ao_cu_bitmap) in cu_info structure is 6922 * 4x4 size array, and it's usually suitable for Vega 6923 * ASICs which has 4*2 SE/SH layout. 6924 * But for Arcturus, SE/SH layout is changed to 8*1. 6925 * To mostly reduce the impact, we make it compatible 6926 * with current bitmap array as below: 6927 * SE4,SH0 --> bitmap[0][1] 6928 * SE5,SH0 --> bitmap[1][1] 6929 * SE6,SH0 --> bitmap[2][1] 6930 * SE7,SH0 --> bitmap[3][1] 6931 */ 6932 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 6933 6934 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 6935 if (bitmap & mask) { 6936 if (counter < adev->gfx.config.max_cu_per_sh) 6937 ao_bitmap |= mask; 6938 counter ++; 6939 } 6940 mask <<= 1; 6941 } 6942 active_cu_number += counter; 6943 if (i < 2 && j < 2) 6944 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 6945 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 6946 } 6947 } 6948 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6949 mutex_unlock(&adev->grbm_idx_mutex); 6950 6951 cu_info->number = active_cu_number; 6952 cu_info->ao_cu_mask = ao_cu_mask; 6953 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6954 6955 return 0; 6956 } 6957 6958 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 6959 { 6960 .type = AMD_IP_BLOCK_TYPE_GFX, 6961 .major = 9, 6962 .minor = 0, 6963 .rev = 0, 6964 .funcs = &gfx_v9_0_ip_funcs, 6965 }; 6966