1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 30 #include "vega10/soc15ip.h" 31 #include "vega10/GC/gc_9_0_offset.h" 32 #include "vega10/GC/gc_9_0_sh_mask.h" 33 #include "vega10/vega10_enum.h" 34 #include "vega10/HDP/hdp_4_0_offset.h" 35 36 #include "soc15_common.h" 37 #include "clearstate_gfx9.h" 38 #include "v9_structs.h" 39 40 #define GFX9_NUM_GFX_RINGS 1 41 #define GFX9_NUM_COMPUTE_RINGS 8 42 #define GFX9_NUM_SE 4 43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000 44 45 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 46 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 47 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 48 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 49 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 50 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 51 52 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 53 { 54 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 55 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)}, 56 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), 57 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)}, 58 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), 59 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)}, 60 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), 61 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)}, 62 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), 63 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)}, 64 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), 65 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)}, 66 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), 67 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)}, 68 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), 69 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)}, 70 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), 71 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)}, 72 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), 73 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)}, 74 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), 75 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)}, 76 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), 77 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)}, 78 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), 79 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, 80 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), 81 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)}, 82 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), 83 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)}, 84 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), 85 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)} 86 }; 87 88 static const u32 golden_settings_gc_9_0[] = 89 { 90 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400, 91 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 92 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 93 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 94 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 95 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 96 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, 97 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, 98 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff 99 }; 100 101 static const u32 golden_settings_gc_9_0_vg10[] = 102 { 103 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, 104 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 105 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, 106 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, 107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, 108 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 109 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800, 110 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007 111 }; 112 113 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 114 115 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 116 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 117 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 118 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 119 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 120 struct amdgpu_cu_info *cu_info); 121 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 122 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 123 124 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 125 { 126 switch (adev->asic_type) { 127 case CHIP_VEGA10: 128 amdgpu_program_register_sequence(adev, 129 golden_settings_gc_9_0, 130 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 131 amdgpu_program_register_sequence(adev, 132 golden_settings_gc_9_0_vg10, 133 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 134 break; 135 default: 136 break; 137 } 138 } 139 140 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 141 { 142 adev->gfx.scratch.num_reg = 7; 143 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 144 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 145 } 146 147 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 148 bool wc, uint32_t reg, uint32_t val) 149 { 150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 151 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 152 WRITE_DATA_DST_SEL(0) | 153 (wc ? WR_CONFIRM : 0)); 154 amdgpu_ring_write(ring, reg); 155 amdgpu_ring_write(ring, 0); 156 amdgpu_ring_write(ring, val); 157 } 158 159 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 160 int mem_space, int opt, uint32_t addr0, 161 uint32_t addr1, uint32_t ref, uint32_t mask, 162 uint32_t inv) 163 { 164 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 165 amdgpu_ring_write(ring, 166 /* memory (1) or register (0) */ 167 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 168 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 169 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 170 WAIT_REG_MEM_ENGINE(eng_sel))); 171 172 if (mem_space) 173 BUG_ON(addr0 & 0x3); /* Dword align */ 174 amdgpu_ring_write(ring, addr0); 175 amdgpu_ring_write(ring, addr1); 176 amdgpu_ring_write(ring, ref); 177 amdgpu_ring_write(ring, mask); 178 amdgpu_ring_write(ring, inv); /* poll interval */ 179 } 180 181 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 182 { 183 struct amdgpu_device *adev = ring->adev; 184 uint32_t scratch; 185 uint32_t tmp = 0; 186 unsigned i; 187 int r; 188 189 r = amdgpu_gfx_scratch_get(adev, &scratch); 190 if (r) { 191 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 192 return r; 193 } 194 WREG32(scratch, 0xCAFEDEAD); 195 r = amdgpu_ring_alloc(ring, 3); 196 if (r) { 197 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 198 ring->idx, r); 199 amdgpu_gfx_scratch_free(adev, scratch); 200 return r; 201 } 202 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 203 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 204 amdgpu_ring_write(ring, 0xDEADBEEF); 205 amdgpu_ring_commit(ring); 206 207 for (i = 0; i < adev->usec_timeout; i++) { 208 tmp = RREG32(scratch); 209 if (tmp == 0xDEADBEEF) 210 break; 211 DRM_UDELAY(1); 212 } 213 if (i < adev->usec_timeout) { 214 DRM_INFO("ring test on %d succeeded in %d usecs\n", 215 ring->idx, i); 216 } else { 217 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 218 ring->idx, scratch, tmp); 219 r = -EINVAL; 220 } 221 amdgpu_gfx_scratch_free(adev, scratch); 222 return r; 223 } 224 225 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 226 { 227 struct amdgpu_device *adev = ring->adev; 228 struct amdgpu_ib ib; 229 struct dma_fence *f = NULL; 230 uint32_t scratch; 231 uint32_t tmp = 0; 232 long r; 233 234 r = amdgpu_gfx_scratch_get(adev, &scratch); 235 if (r) { 236 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 237 return r; 238 } 239 WREG32(scratch, 0xCAFEDEAD); 240 memset(&ib, 0, sizeof(ib)); 241 r = amdgpu_ib_get(adev, NULL, 256, &ib); 242 if (r) { 243 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 244 goto err1; 245 } 246 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 247 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 248 ib.ptr[2] = 0xDEADBEEF; 249 ib.length_dw = 3; 250 251 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 252 if (r) 253 goto err2; 254 255 r = dma_fence_wait_timeout(f, false, timeout); 256 if (r == 0) { 257 DRM_ERROR("amdgpu: IB test timed out.\n"); 258 r = -ETIMEDOUT; 259 goto err2; 260 } else if (r < 0) { 261 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 262 goto err2; 263 } 264 tmp = RREG32(scratch); 265 if (tmp == 0xDEADBEEF) { 266 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 267 r = 0; 268 } else { 269 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 270 scratch, tmp); 271 r = -EINVAL; 272 } 273 err2: 274 amdgpu_ib_free(adev, &ib, NULL); 275 dma_fence_put(f); 276 err1: 277 amdgpu_gfx_scratch_free(adev, scratch); 278 return r; 279 } 280 281 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 282 { 283 const char *chip_name; 284 char fw_name[30]; 285 int err; 286 struct amdgpu_firmware_info *info = NULL; 287 const struct common_firmware_header *header = NULL; 288 const struct gfx_firmware_header_v1_0 *cp_hdr; 289 290 DRM_DEBUG("\n"); 291 292 switch (adev->asic_type) { 293 case CHIP_VEGA10: 294 chip_name = "vega10"; 295 break; 296 default: 297 BUG(); 298 } 299 300 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 301 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 302 if (err) 303 goto out; 304 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 305 if (err) 306 goto out; 307 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 308 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 309 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 310 311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 312 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 313 if (err) 314 goto out; 315 err = amdgpu_ucode_validate(adev->gfx.me_fw); 316 if (err) 317 goto out; 318 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 319 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 320 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 321 322 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 323 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 324 if (err) 325 goto out; 326 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 327 if (err) 328 goto out; 329 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 330 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 331 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 332 333 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 334 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 335 if (err) 336 goto out; 337 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 338 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 339 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 340 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 341 342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 343 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 344 if (err) 345 goto out; 346 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 347 if (err) 348 goto out; 349 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 350 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 351 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 352 353 354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 355 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 356 if (!err) { 357 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 358 if (err) 359 goto out; 360 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 361 adev->gfx.mec2_fw->data; 362 adev->gfx.mec2_fw_version = 363 le32_to_cpu(cp_hdr->header.ucode_version); 364 adev->gfx.mec2_feature_version = 365 le32_to_cpu(cp_hdr->ucode_feature_version); 366 } else { 367 err = 0; 368 adev->gfx.mec2_fw = NULL; 369 } 370 371 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 372 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 373 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 374 info->fw = adev->gfx.pfp_fw; 375 header = (const struct common_firmware_header *)info->fw->data; 376 adev->firmware.fw_size += 377 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 378 379 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 380 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 381 info->fw = adev->gfx.me_fw; 382 header = (const struct common_firmware_header *)info->fw->data; 383 adev->firmware.fw_size += 384 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 385 386 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 387 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 388 info->fw = adev->gfx.ce_fw; 389 header = (const struct common_firmware_header *)info->fw->data; 390 adev->firmware.fw_size += 391 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 392 393 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 394 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 395 info->fw = adev->gfx.rlc_fw; 396 header = (const struct common_firmware_header *)info->fw->data; 397 adev->firmware.fw_size += 398 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 399 400 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 401 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 402 info->fw = adev->gfx.mec_fw; 403 header = (const struct common_firmware_header *)info->fw->data; 404 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 405 adev->firmware.fw_size += 406 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 407 408 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 409 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 410 info->fw = adev->gfx.mec_fw; 411 adev->firmware.fw_size += 412 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 413 414 if (adev->gfx.mec2_fw) { 415 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 416 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 417 info->fw = adev->gfx.mec2_fw; 418 header = (const struct common_firmware_header *)info->fw->data; 419 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 420 adev->firmware.fw_size += 421 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 422 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 423 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 424 info->fw = adev->gfx.mec2_fw; 425 adev->firmware.fw_size += 426 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 427 } 428 429 } 430 431 out: 432 if (err) { 433 dev_err(adev->dev, 434 "gfx9: Failed to load firmware \"%s\"\n", 435 fw_name); 436 release_firmware(adev->gfx.pfp_fw); 437 adev->gfx.pfp_fw = NULL; 438 release_firmware(adev->gfx.me_fw); 439 adev->gfx.me_fw = NULL; 440 release_firmware(adev->gfx.ce_fw); 441 adev->gfx.ce_fw = NULL; 442 release_firmware(adev->gfx.rlc_fw); 443 adev->gfx.rlc_fw = NULL; 444 release_firmware(adev->gfx.mec_fw); 445 adev->gfx.mec_fw = NULL; 446 release_firmware(adev->gfx.mec2_fw); 447 adev->gfx.mec2_fw = NULL; 448 } 449 return err; 450 } 451 452 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 453 { 454 int r; 455 456 if (adev->gfx.mec.hpd_eop_obj) { 457 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 458 if (unlikely(r != 0)) 459 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 460 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 461 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 462 463 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 464 adev->gfx.mec.hpd_eop_obj = NULL; 465 } 466 if (adev->gfx.mec.mec_fw_obj) { 467 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); 468 if (unlikely(r != 0)) 469 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r); 470 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj); 471 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 472 473 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj); 474 adev->gfx.mec.mec_fw_obj = NULL; 475 } 476 } 477 478 #define MEC_HPD_SIZE 2048 479 480 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 481 { 482 int r; 483 u32 *hpd; 484 const __le32 *fw_data; 485 unsigned fw_size; 486 u32 *fw; 487 488 const struct gfx_firmware_header_v1_0 *mec_hdr; 489 490 /* 491 * we assign only 1 pipe because all other pipes will 492 * be handled by KFD 493 */ 494 adev->gfx.mec.num_mec = 1; 495 adev->gfx.mec.num_pipe = 1; 496 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 497 498 if (adev->gfx.mec.hpd_eop_obj == NULL) { 499 r = amdgpu_bo_create(adev, 500 adev->gfx.mec.num_queue * MEC_HPD_SIZE, 501 PAGE_SIZE, true, 502 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 503 &adev->gfx.mec.hpd_eop_obj); 504 if (r) { 505 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 506 return r; 507 } 508 } 509 510 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 511 if (unlikely(r != 0)) { 512 gfx_v9_0_mec_fini(adev); 513 return r; 514 } 515 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 516 &adev->gfx.mec.hpd_eop_gpu_addr); 517 if (r) { 518 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 519 gfx_v9_0_mec_fini(adev); 520 return r; 521 } 522 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 523 if (r) { 524 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 525 gfx_v9_0_mec_fini(adev); 526 return r; 527 } 528 529 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 530 531 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 532 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 533 534 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 535 536 fw_data = (const __le32 *) 537 (adev->gfx.mec_fw->data + 538 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 539 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 540 541 if (adev->gfx.mec.mec_fw_obj == NULL) { 542 r = amdgpu_bo_create(adev, 543 mec_hdr->header.ucode_size_bytes, 544 PAGE_SIZE, true, 545 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 546 &adev->gfx.mec.mec_fw_obj); 547 if (r) { 548 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 549 return r; 550 } 551 } 552 553 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); 554 if (unlikely(r != 0)) { 555 gfx_v9_0_mec_fini(adev); 556 return r; 557 } 558 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT, 559 &adev->gfx.mec.mec_fw_gpu_addr); 560 if (r) { 561 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r); 562 gfx_v9_0_mec_fini(adev); 563 return r; 564 } 565 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw); 566 if (r) { 567 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r); 568 gfx_v9_0_mec_fini(adev); 569 return r; 570 } 571 memcpy(fw, fw_data, fw_size); 572 573 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 574 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 575 576 577 return 0; 578 } 579 580 static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev) 581 { 582 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 583 584 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 585 } 586 587 static int gfx_v9_0_kiq_init(struct amdgpu_device *adev) 588 { 589 int r; 590 u32 *hpd; 591 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 592 593 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, 594 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 595 &kiq->eop_gpu_addr, (void **)&hpd); 596 if (r) { 597 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 598 return r; 599 } 600 601 memset(hpd, 0, MEC_HPD_SIZE); 602 603 r = amdgpu_bo_reserve(kiq->eop_obj, false); 604 if (unlikely(r != 0)) 605 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 606 amdgpu_bo_kunmap(kiq->eop_obj); 607 amdgpu_bo_unreserve(kiq->eop_obj); 608 609 return 0; 610 } 611 612 static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, 613 struct amdgpu_ring *ring, 614 struct amdgpu_irq_src *irq) 615 { 616 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 617 int r = 0; 618 619 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); 620 if (r) 621 return r; 622 623 ring->adev = NULL; 624 ring->ring_obj = NULL; 625 ring->use_doorbell = true; 626 ring->doorbell_index = AMDGPU_DOORBELL_KIQ; 627 if (adev->gfx.mec2_fw) { 628 ring->me = 2; 629 ring->pipe = 0; 630 } else { 631 ring->me = 1; 632 ring->pipe = 1; 633 } 634 635 irq->data = ring; 636 ring->queue = 0; 637 ring->eop_gpu_addr = kiq->eop_gpu_addr; 638 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); 639 r = amdgpu_ring_init(adev, ring, 1024, 640 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); 641 if (r) 642 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 643 644 return r; 645 } 646 static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, 647 struct amdgpu_irq_src *irq) 648 { 649 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); 650 amdgpu_ring_fini(ring); 651 irq->data = NULL; 652 } 653 654 /* create MQD for each compute queue */ 655 static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) 656 { 657 struct amdgpu_ring *ring = NULL; 658 int r, i; 659 660 /* create MQD for KIQ */ 661 ring = &adev->gfx.kiq.ring; 662 if (!ring->mqd_obj) { 663 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, 664 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 665 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 666 if (r) { 667 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 668 return r; 669 } 670 671 /*TODO: prepare MQD backup */ 672 } 673 674 /* create MQD for each KCQ */ 675 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 676 ring = &adev->gfx.compute_ring[i]; 677 if (!ring->mqd_obj) { 678 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, 679 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 680 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 681 if (r) { 682 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 683 return r; 684 } 685 686 /* TODO: prepare MQD backup */ 687 } 688 } 689 690 return 0; 691 } 692 693 static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev) 694 { 695 struct amdgpu_ring *ring = NULL; 696 int i; 697 698 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 699 ring = &adev->gfx.compute_ring[i]; 700 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 701 } 702 703 ring = &adev->gfx.kiq.ring; 704 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 705 } 706 707 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 708 { 709 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX), 710 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 711 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 712 (address << SQ_IND_INDEX__INDEX__SHIFT) | 713 (SQ_IND_INDEX__FORCE_READ_MASK)); 714 return RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA)); 715 } 716 717 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 718 uint32_t wave, uint32_t thread, 719 uint32_t regno, uint32_t num, uint32_t *out) 720 { 721 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_INDEX), 722 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 723 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 724 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 725 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 726 (SQ_IND_INDEX__FORCE_READ_MASK) | 727 (SQ_IND_INDEX__AUTO_INCR_MASK)); 728 while (num--) 729 *(out++) = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_IND_DATA)); 730 } 731 732 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 733 { 734 /* type 1 wave data */ 735 dst[(*no_fields)++] = 1; 736 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 737 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 738 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 739 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 740 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 741 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 742 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 743 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 744 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 745 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 746 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 747 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 748 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 749 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 750 } 751 752 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 753 uint32_t wave, uint32_t start, 754 uint32_t size, uint32_t *dst) 755 { 756 wave_read_regs( 757 adev, simd, wave, 0, 758 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 759 } 760 761 762 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 763 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 764 .select_se_sh = &gfx_v9_0_select_se_sh, 765 .read_wave_data = &gfx_v9_0_read_wave_data, 766 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 767 }; 768 769 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 770 { 771 u32 gb_addr_config; 772 773 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 774 775 switch (adev->asic_type) { 776 case CHIP_VEGA10: 777 adev->gfx.config.max_shader_engines = 4; 778 adev->gfx.config.max_tile_pipes = 8; //?? 779 adev->gfx.config.max_cu_per_sh = 16; 780 adev->gfx.config.max_sh_per_se = 1; 781 adev->gfx.config.max_backends_per_se = 4; 782 adev->gfx.config.max_texture_channel_caches = 16; 783 adev->gfx.config.max_gprs = 256; 784 adev->gfx.config.max_gs_threads = 32; 785 adev->gfx.config.max_hw_contexts = 8; 786 787 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 788 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 789 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 790 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 791 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 792 break; 793 default: 794 BUG(); 795 break; 796 } 797 798 adev->gfx.config.gb_addr_config = gb_addr_config; 799 800 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 801 REG_GET_FIELD( 802 adev->gfx.config.gb_addr_config, 803 GB_ADDR_CONFIG, 804 NUM_PIPES); 805 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 806 REG_GET_FIELD( 807 adev->gfx.config.gb_addr_config, 808 GB_ADDR_CONFIG, 809 NUM_BANKS); 810 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 811 REG_GET_FIELD( 812 adev->gfx.config.gb_addr_config, 813 GB_ADDR_CONFIG, 814 MAX_COMPRESSED_FRAGS); 815 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 816 REG_GET_FIELD( 817 adev->gfx.config.gb_addr_config, 818 GB_ADDR_CONFIG, 819 NUM_RB_PER_SE); 820 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 821 REG_GET_FIELD( 822 adev->gfx.config.gb_addr_config, 823 GB_ADDR_CONFIG, 824 NUM_SHADER_ENGINES); 825 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 826 REG_GET_FIELD( 827 adev->gfx.config.gb_addr_config, 828 GB_ADDR_CONFIG, 829 PIPE_INTERLEAVE_SIZE)); 830 } 831 832 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 833 struct amdgpu_ngg_buf *ngg_buf, 834 int size_se, 835 int default_size_se) 836 { 837 int r; 838 839 if (size_se < 0) { 840 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 841 return -EINVAL; 842 } 843 size_se = size_se ? size_se : default_size_se; 844 845 ngg_buf->size = size_se * GFX9_NUM_SE; 846 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 847 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 848 &ngg_buf->bo, 849 &ngg_buf->gpu_addr, 850 NULL); 851 if (r) { 852 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 853 return r; 854 } 855 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 856 857 return r; 858 } 859 860 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 861 { 862 int i; 863 864 for (i = 0; i < NGG_BUF_MAX; i++) 865 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 866 &adev->gfx.ngg.buf[i].gpu_addr, 867 NULL); 868 869 memset(&adev->gfx.ngg.buf[0], 0, 870 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 871 872 adev->gfx.ngg.init = false; 873 874 return 0; 875 } 876 877 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 878 { 879 int r; 880 881 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 882 return 0; 883 884 /* GDS reserve memory: 64 bytes alignment */ 885 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 886 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 887 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 888 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; 889 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; 890 891 /* Primitive Buffer */ 892 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PRIM], 893 amdgpu_prim_buf_per_se, 894 64 * 1024); 895 if (r) { 896 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 897 goto err; 898 } 899 900 /* Position Buffer */ 901 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[POS], 902 amdgpu_pos_buf_per_se, 903 256 * 1024); 904 if (r) { 905 dev_err(adev->dev, "Failed to create Position Buffer\n"); 906 goto err; 907 } 908 909 /* Control Sideband */ 910 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[CNTL], 911 amdgpu_cntl_sb_buf_per_se, 912 256); 913 if (r) { 914 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 915 goto err; 916 } 917 918 /* Parameter Cache, not created by default */ 919 if (amdgpu_param_buf_per_se <= 0) 920 goto out; 921 922 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[PARAM], 923 amdgpu_param_buf_per_se, 924 512 * 1024); 925 if (r) { 926 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 927 goto err; 928 } 929 930 out: 931 adev->gfx.ngg.init = true; 932 return 0; 933 err: 934 gfx_v9_0_ngg_fini(adev); 935 return r; 936 } 937 938 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 939 { 940 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 941 int r; 942 u32 data; 943 u32 size; 944 u32 base; 945 946 if (!amdgpu_ngg) 947 return 0; 948 949 /* Program buffer size */ 950 data = 0; 951 size = adev->gfx.ngg.buf[PRIM].size / 256; 952 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size); 953 954 size = adev->gfx.ngg.buf[POS].size / 256; 955 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size); 956 957 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_1), data); 958 959 data = 0; 960 size = adev->gfx.ngg.buf[CNTL].size / 256; 961 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size); 962 963 size = adev->gfx.ngg.buf[PARAM].size / 1024; 964 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size); 965 966 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_BUF_RESOURCE_2), data); 967 968 /* Program buffer base address */ 969 base = lower_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr); 970 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 971 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE), data); 972 973 base = upper_32_bits(adev->gfx.ngg.buf[PRIM].gpu_addr); 974 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 975 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_INDEX_BUF_BASE_HI), data); 976 977 base = lower_32_bits(adev->gfx.ngg.buf[POS].gpu_addr); 978 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 979 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE), data); 980 981 base = upper_32_bits(adev->gfx.ngg.buf[POS].gpu_addr); 982 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 983 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_POS_BUF_BASE_HI), data); 984 985 base = lower_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr); 986 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 987 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE), data); 988 989 base = upper_32_bits(adev->gfx.ngg.buf[CNTL].gpu_addr); 990 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 991 WREG32(SOC15_REG_OFFSET(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI), data); 992 993 /* Clear GDS reserved memory */ 994 r = amdgpu_ring_alloc(ring, 17); 995 if (r) { 996 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", 997 ring->idx, r); 998 return r; 999 } 1000 1001 gfx_v9_0_write_data_to_reg(ring, 0, false, 1002 amdgpu_gds_reg_offset[0].mem_size, 1003 (adev->gds.mem.total_size + 1004 adev->gfx.ngg.gds_reserve_size) >> 1005 AMDGPU_GDS_SHIFT); 1006 1007 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1008 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1009 PACKET3_DMA_DATA_SRC_SEL(2))); 1010 amdgpu_ring_write(ring, 0); 1011 amdgpu_ring_write(ring, 0); 1012 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1013 amdgpu_ring_write(ring, 0); 1014 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); 1015 1016 1017 gfx_v9_0_write_data_to_reg(ring, 0, false, 1018 amdgpu_gds_reg_offset[0].mem_size, 0); 1019 1020 amdgpu_ring_commit(ring); 1021 1022 return 0; 1023 } 1024 1025 static int gfx_v9_0_sw_init(void *handle) 1026 { 1027 int i, r; 1028 struct amdgpu_ring *ring; 1029 struct amdgpu_kiq *kiq; 1030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1031 1032 /* KIQ event */ 1033 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); 1034 if (r) 1035 return r; 1036 1037 /* EOP Event */ 1038 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); 1039 if (r) 1040 return r; 1041 1042 /* Privileged reg */ 1043 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, 1044 &adev->gfx.priv_reg_irq); 1045 if (r) 1046 return r; 1047 1048 /* Privileged inst */ 1049 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, 1050 &adev->gfx.priv_inst_irq); 1051 if (r) 1052 return r; 1053 1054 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1055 1056 gfx_v9_0_scratch_init(adev); 1057 1058 r = gfx_v9_0_init_microcode(adev); 1059 if (r) { 1060 DRM_ERROR("Failed to load gfx firmware!\n"); 1061 return r; 1062 } 1063 1064 r = gfx_v9_0_mec_init(adev); 1065 if (r) { 1066 DRM_ERROR("Failed to init MEC BOs!\n"); 1067 return r; 1068 } 1069 1070 /* set up the gfx ring */ 1071 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1072 ring = &adev->gfx.gfx_ring[i]; 1073 ring->ring_obj = NULL; 1074 sprintf(ring->name, "gfx"); 1075 ring->use_doorbell = true; 1076 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; 1077 r = amdgpu_ring_init(adev, ring, 1024, 1078 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1079 if (r) 1080 return r; 1081 } 1082 1083 /* set up the compute queues */ 1084 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1085 unsigned irq_type; 1086 1087 /* max 32 queues per MEC */ 1088 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 1089 DRM_ERROR("Too many (%d) compute rings!\n", i); 1090 break; 1091 } 1092 ring = &adev->gfx.compute_ring[i]; 1093 ring->ring_obj = NULL; 1094 ring->use_doorbell = true; 1095 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1; 1096 ring->me = 1; /* first MEC */ 1097 ring->pipe = i / 8; 1098 ring->queue = i % 8; 1099 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 1100 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 1101 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 1102 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1103 r = amdgpu_ring_init(adev, ring, 1024, 1104 &adev->gfx.eop_irq, irq_type); 1105 if (r) 1106 return r; 1107 } 1108 1109 if (amdgpu_sriov_vf(adev)) { 1110 r = gfx_v9_0_kiq_init(adev); 1111 if (r) { 1112 DRM_ERROR("Failed to init KIQ BOs!\n"); 1113 return r; 1114 } 1115 1116 kiq = &adev->gfx.kiq; 1117 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1118 if (r) 1119 return r; 1120 1121 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1122 r = gfx_v9_0_compute_mqd_sw_init(adev); 1123 if (r) 1124 return r; 1125 } 1126 1127 /* reserve GDS, GWS and OA resource for gfx */ 1128 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 1129 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 1130 &adev->gds.gds_gfx_bo, NULL, NULL); 1131 if (r) 1132 return r; 1133 1134 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 1135 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 1136 &adev->gds.gws_gfx_bo, NULL, NULL); 1137 if (r) 1138 return r; 1139 1140 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 1141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 1142 &adev->gds.oa_gfx_bo, NULL, NULL); 1143 if (r) 1144 return r; 1145 1146 adev->gfx.ce_ram_size = 0x8000; 1147 1148 gfx_v9_0_gpu_early_init(adev); 1149 1150 r = gfx_v9_0_ngg_init(adev); 1151 if (r) 1152 return r; 1153 1154 return 0; 1155 } 1156 1157 1158 static int gfx_v9_0_sw_fini(void *handle) 1159 { 1160 int i; 1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1162 1163 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1164 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1165 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1166 1167 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1168 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1169 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1170 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1171 1172 if (amdgpu_sriov_vf(adev)) { 1173 gfx_v9_0_compute_mqd_sw_fini(adev); 1174 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1175 gfx_v9_0_kiq_fini(adev); 1176 } 1177 1178 gfx_v9_0_mec_fini(adev); 1179 gfx_v9_0_ngg_fini(adev); 1180 1181 return 0; 1182 } 1183 1184 1185 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1186 { 1187 /* TODO */ 1188 } 1189 1190 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1191 { 1192 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1193 1194 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { 1195 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1196 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1197 } else if (se_num == 0xffffffff) { 1198 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1199 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1200 } else if (sh_num == 0xffffffff) { 1201 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1202 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1203 } else { 1204 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1205 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1206 } 1207 WREG32( SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 1208 } 1209 1210 static u32 gfx_v9_0_create_bitmask(u32 bit_width) 1211 { 1212 return (u32)((1ULL << bit_width) - 1); 1213 } 1214 1215 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1216 { 1217 u32 data, mask; 1218 1219 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_RB_BACKEND_DISABLE)); 1220 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)); 1221 1222 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1223 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1224 1225 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se / 1226 adev->gfx.config.max_sh_per_se); 1227 1228 return (~data) & mask; 1229 } 1230 1231 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1232 { 1233 int i, j; 1234 u32 data, tmp, num_rbs = 0; 1235 u32 active_rbs = 0; 1236 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1237 adev->gfx.config.max_sh_per_se; 1238 1239 mutex_lock(&adev->grbm_idx_mutex); 1240 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1241 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1242 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1243 data = gfx_v9_0_get_rb_active_bitmap(adev); 1244 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1245 rb_bitmap_width_per_sh); 1246 } 1247 } 1248 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1249 mutex_unlock(&adev->grbm_idx_mutex); 1250 1251 adev->gfx.config.backend_enable_mask = active_rbs; 1252 tmp = active_rbs; 1253 while (tmp >>= 1) 1254 num_rbs++; 1255 adev->gfx.config.num_rbs = num_rbs; 1256 } 1257 1258 #define DEFAULT_SH_MEM_BASES (0x6000) 1259 #define FIRST_COMPUTE_VMID (8) 1260 #define LAST_COMPUTE_VMID (16) 1261 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1262 { 1263 int i; 1264 uint32_t sh_mem_config; 1265 uint32_t sh_mem_bases; 1266 1267 /* 1268 * Configure apertures: 1269 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1270 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1271 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1272 */ 1273 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1274 1275 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1276 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1277 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1278 1279 mutex_lock(&adev->srbm_mutex); 1280 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1281 soc15_grbm_select(adev, 0, 0, 0, i); 1282 /* CP and shaders */ 1283 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 1284 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 1285 } 1286 soc15_grbm_select(adev, 0, 0, 0, 0); 1287 mutex_unlock(&adev->srbm_mutex); 1288 } 1289 1290 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 1291 { 1292 u32 tmp; 1293 int i; 1294 1295 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL)); 1296 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); 1297 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_CNTL), tmp); 1298 1299 gfx_v9_0_tiling_mode_table_init(adev); 1300 1301 gfx_v9_0_setup_rb(adev); 1302 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1303 1304 /* XXX SH_MEM regs */ 1305 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1306 mutex_lock(&adev->srbm_mutex); 1307 for (i = 0; i < 16; i++) { 1308 soc15_grbm_select(adev, 0, 0, 0, i); 1309 /* CP and shaders */ 1310 tmp = 0; 1311 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 1312 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1313 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), tmp); 1314 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), 0); 1315 } 1316 soc15_grbm_select(adev, 0, 0, 0, 0); 1317 1318 mutex_unlock(&adev->srbm_mutex); 1319 1320 gfx_v9_0_init_compute_vmid(adev); 1321 1322 mutex_lock(&adev->grbm_idx_mutex); 1323 /* 1324 * making sure that the following register writes will be broadcasted 1325 * to all the shaders 1326 */ 1327 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1328 1329 WREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE), 1330 (adev->gfx.config.sc_prim_fifo_size_frontend << 1331 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1332 (adev->gfx.config.sc_prim_fifo_size_backend << 1333 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1334 (adev->gfx.config.sc_hiz_tile_fifo_size << 1335 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1336 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1337 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1338 mutex_unlock(&adev->grbm_idx_mutex); 1339 1340 } 1341 1342 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1343 { 1344 u32 i, j, k; 1345 u32 mask; 1346 1347 mutex_lock(&adev->grbm_idx_mutex); 1348 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1349 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1350 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1351 for (k = 0; k < adev->usec_timeout; k++) { 1352 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY)) == 0) 1353 break; 1354 udelay(1); 1355 } 1356 } 1357 } 1358 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1359 mutex_unlock(&adev->grbm_idx_mutex); 1360 1361 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1362 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1363 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1364 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1365 for (k = 0; k < adev->usec_timeout; k++) { 1366 if ((RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY)) & mask) == 0) 1367 break; 1368 udelay(1); 1369 } 1370 } 1371 1372 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1373 bool enable) 1374 { 1375 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 1376 1377 if (enable) 1378 return; 1379 1380 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1381 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1382 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1383 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1384 1385 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), tmp); 1386 } 1387 1388 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 1389 { 1390 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); 1391 1392 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1393 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp); 1394 1395 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 1396 1397 gfx_v9_0_wait_for_rlc_serdes(adev); 1398 } 1399 1400 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 1401 { 1402 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); 1403 1404 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1405 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); 1406 udelay(50); 1407 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1408 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); 1409 udelay(50); 1410 } 1411 1412 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 1413 { 1414 #ifdef AMDGPU_RLC_DEBUG_RETRY 1415 u32 rlc_ucode_ver; 1416 #endif 1417 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); 1418 1419 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); 1420 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL), tmp); 1421 1422 /* carrizo do enable cp interrupt after cp inited */ 1423 if (!(adev->flags & AMD_IS_APU)) 1424 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 1425 1426 udelay(50); 1427 1428 #ifdef AMDGPU_RLC_DEBUG_RETRY 1429 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1430 rlc_ucode_ver = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6)); 1431 if(rlc_ucode_ver == 0x108) { 1432 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1433 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1434 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1435 * default is 0x9C4 to create a 100us interval */ 1436 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3), 0x9C4); 1437 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1438 * to disable the page fault retry interrupts, default is 1439 * 0x100 (256) */ 1440 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12), 0x100); 1441 } 1442 #endif 1443 } 1444 1445 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 1446 { 1447 const struct rlc_firmware_header_v2_0 *hdr; 1448 const __le32 *fw_data; 1449 unsigned i, fw_size; 1450 1451 if (!adev->gfx.rlc_fw) 1452 return -EINVAL; 1453 1454 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1455 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1456 1457 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1458 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1459 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1460 1461 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), 1462 RLCG_UCODE_LOADING_START_ADDRESS); 1463 for (i = 0; i < fw_size; i++) 1464 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA), le32_to_cpup(fw_data++)); 1465 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR), adev->gfx.rlc_fw_version); 1466 1467 return 0; 1468 } 1469 1470 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 1471 { 1472 int r; 1473 1474 if (amdgpu_sriov_vf(adev)) 1475 return 0; 1476 1477 gfx_v9_0_rlc_stop(adev); 1478 1479 /* disable CG */ 1480 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), 0); 1481 1482 /* disable PG */ 1483 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), 0); 1484 1485 gfx_v9_0_rlc_reset(adev); 1486 1487 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1488 /* legacy rlc firmware loading */ 1489 r = gfx_v9_0_rlc_load_microcode(adev); 1490 if (r) 1491 return r; 1492 } 1493 1494 gfx_v9_0_rlc_start(adev); 1495 1496 return 0; 1497 } 1498 1499 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1500 { 1501 int i; 1502 u32 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)); 1503 1504 if (enable) { 1505 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); 1506 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); 1507 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); 1508 } else { 1509 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); 1510 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); 1511 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); 1512 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1513 adev->gfx.gfx_ring[i].ready = false; 1514 } 1515 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL), tmp); 1516 udelay(50); 1517 } 1518 1519 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1520 { 1521 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1522 const struct gfx_firmware_header_v1_0 *ce_hdr; 1523 const struct gfx_firmware_header_v1_0 *me_hdr; 1524 const __le32 *fw_data; 1525 unsigned i, fw_size; 1526 1527 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1528 return -EINVAL; 1529 1530 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 1531 adev->gfx.pfp_fw->data; 1532 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 1533 adev->gfx.ce_fw->data; 1534 me_hdr = (const struct gfx_firmware_header_v1_0 *) 1535 adev->gfx.me_fw->data; 1536 1537 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1538 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1539 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1540 1541 gfx_v9_0_cp_gfx_enable(adev, false); 1542 1543 /* PFP */ 1544 fw_data = (const __le32 *) 1545 (adev->gfx.pfp_fw->data + 1546 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1547 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1548 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), 0); 1549 for (i = 0; i < fw_size; i++) 1550 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA), le32_to_cpup(fw_data++)); 1551 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR), adev->gfx.pfp_fw_version); 1552 1553 /* CE */ 1554 fw_data = (const __le32 *) 1555 (adev->gfx.ce_fw->data + 1556 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 1557 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 1558 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), 0); 1559 for (i = 0; i < fw_size; i++) 1560 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA), le32_to_cpup(fw_data++)); 1561 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR), adev->gfx.ce_fw_version); 1562 1563 /* ME */ 1564 fw_data = (const __le32 *) 1565 (adev->gfx.me_fw->data + 1566 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 1567 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 1568 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), 0); 1569 for (i = 0; i < fw_size; i++) 1570 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_DATA), le32_to_cpup(fw_data++)); 1571 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_RAM_WADDR), adev->gfx.me_fw_version); 1572 1573 return 0; 1574 } 1575 1576 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1577 { 1578 u32 count = 0; 1579 const struct cs_section_def *sect = NULL; 1580 const struct cs_extent_def *ext = NULL; 1581 1582 /* begin clear state */ 1583 count += 2; 1584 /* context control state */ 1585 count += 3; 1586 1587 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1588 for (ext = sect->section; ext->extent != NULL; ++ext) { 1589 if (sect->id == SECT_CONTEXT) 1590 count += 2 + ext->reg_count; 1591 else 1592 return 0; 1593 } 1594 } 1595 /* pa_sc_raster_config/pa_sc_raster_config1 */ 1596 count += 4; 1597 /* end clear state */ 1598 count += 2; 1599 /* clear state */ 1600 count += 2; 1601 1602 return count; 1603 } 1604 1605 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 1606 { 1607 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1608 const struct cs_section_def *sect = NULL; 1609 const struct cs_extent_def *ext = NULL; 1610 int r, i; 1611 1612 /* init the CP */ 1613 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT), adev->gfx.config.max_hw_contexts - 1); 1614 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID), 1); 1615 1616 gfx_v9_0_cp_gfx_enable(adev, true); 1617 1618 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4); 1619 if (r) { 1620 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 1621 return r; 1622 } 1623 1624 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1625 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1626 1627 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1628 amdgpu_ring_write(ring, 0x80000000); 1629 amdgpu_ring_write(ring, 0x80000000); 1630 1631 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1632 for (ext = sect->section; ext->extent != NULL; ++ext) { 1633 if (sect->id == SECT_CONTEXT) { 1634 amdgpu_ring_write(ring, 1635 PACKET3(PACKET3_SET_CONTEXT_REG, 1636 ext->reg_count)); 1637 amdgpu_ring_write(ring, 1638 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 1639 for (i = 0; i < ext->reg_count; i++) 1640 amdgpu_ring_write(ring, ext->extent[i]); 1641 } 1642 } 1643 } 1644 1645 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1646 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1647 1648 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1649 amdgpu_ring_write(ring, 0); 1650 1651 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1652 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1653 amdgpu_ring_write(ring, 0x8000); 1654 amdgpu_ring_write(ring, 0x8000); 1655 1656 amdgpu_ring_commit(ring); 1657 1658 return 0; 1659 } 1660 1661 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 1662 { 1663 struct amdgpu_ring *ring; 1664 u32 tmp; 1665 u32 rb_bufsz; 1666 u64 rb_addr, rptr_addr, wptr_gpu_addr; 1667 1668 /* Set the write pointer delay */ 1669 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY), 0); 1670 1671 /* set the RB to use vmid 0 */ 1672 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID), 0); 1673 1674 /* Set ring buffer size */ 1675 ring = &adev->gfx.gfx_ring[0]; 1676 rb_bufsz = order_base_2(ring->ring_size / 8); 1677 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 1678 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 1679 #ifdef __BIG_ENDIAN 1680 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 1681 #endif 1682 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp); 1683 1684 /* Initialize the ring buffer's write pointers */ 1685 ring->wptr = 0; 1686 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr)); 1687 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr)); 1688 1689 /* set the wb address wether it's enabled or not */ 1690 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1691 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR), lower_32_bits(rptr_addr)); 1692 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI), upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 1693 1694 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1695 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO), lower_32_bits(wptr_gpu_addr)); 1696 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI), upper_32_bits(wptr_gpu_addr)); 1697 1698 mdelay(1); 1699 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL), tmp); 1700 1701 rb_addr = ring->gpu_addr >> 8; 1702 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE), rb_addr); 1703 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI), upper_32_bits(rb_addr)); 1704 1705 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL)); 1706 if (ring->use_doorbell) { 1707 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 1708 DOORBELL_OFFSET, ring->doorbell_index); 1709 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 1710 DOORBELL_EN, 1); 1711 } else { 1712 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 1713 } 1714 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_CONTROL), tmp); 1715 1716 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 1717 DOORBELL_RANGE_LOWER, ring->doorbell_index); 1718 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER), tmp); 1719 1720 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER), 1721 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 1722 1723 1724 /* start the ring */ 1725 gfx_v9_0_cp_gfx_start(adev); 1726 ring->ready = true; 1727 1728 return 0; 1729 } 1730 1731 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 1732 { 1733 int i; 1734 1735 if (enable) { 1736 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 0); 1737 } else { 1738 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL), 1739 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1740 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1741 adev->gfx.compute_ring[i].ready = false; 1742 adev->gfx.kiq.ring.ready = false; 1743 } 1744 udelay(50); 1745 } 1746 1747 static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev) 1748 { 1749 gfx_v9_0_cp_compute_enable(adev, true); 1750 1751 return 0; 1752 } 1753 1754 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 1755 { 1756 const struct gfx_firmware_header_v1_0 *mec_hdr; 1757 const __le32 *fw_data; 1758 unsigned i; 1759 u32 tmp; 1760 1761 if (!adev->gfx.mec_fw) 1762 return -EINVAL; 1763 1764 gfx_v9_0_cp_compute_enable(adev, false); 1765 1766 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1767 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1768 1769 fw_data = (const __le32 *) 1770 (adev->gfx.mec_fw->data + 1771 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1772 tmp = 0; 1773 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1774 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1775 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_CNTL), tmp); 1776 1777 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_LO), 1778 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1779 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_IC_BASE_HI), 1780 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1781 1782 /* MEC1 */ 1783 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR), 1784 mec_hdr->jt_offset); 1785 for (i = 0; i < mec_hdr->jt_size; i++) 1786 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA), 1787 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1788 1789 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR), 1790 adev->gfx.mec_fw_version); 1791 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1792 1793 return 0; 1794 } 1795 1796 static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev) 1797 { 1798 int i, r; 1799 1800 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1801 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 1802 1803 if (ring->mqd_obj) { 1804 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1805 if (unlikely(r != 0)) 1806 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 1807 1808 amdgpu_bo_unpin(ring->mqd_obj); 1809 amdgpu_bo_unreserve(ring->mqd_obj); 1810 1811 amdgpu_bo_unref(&ring->mqd_obj); 1812 ring->mqd_obj = NULL; 1813 } 1814 } 1815 } 1816 1817 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring); 1818 1819 static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev) 1820 { 1821 int i, r; 1822 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1823 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 1824 if (gfx_v9_0_init_queue(ring)) 1825 dev_warn(adev->dev, "compute queue %d init failed!\n", i); 1826 } 1827 1828 r = gfx_v9_0_cp_compute_start(adev); 1829 if (r) 1830 return r; 1831 1832 return 0; 1833 } 1834 1835 /* KIQ functions */ 1836 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 1837 { 1838 uint32_t tmp; 1839 struct amdgpu_device *adev = ring->adev; 1840 1841 /* tell RLC which is KIQ queue */ 1842 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 1843 tmp &= 0xffffff00; 1844 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1845 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp); 1846 tmp |= 0x80; 1847 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), tmp); 1848 } 1849 1850 static void gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) 1851 { 1852 amdgpu_ring_alloc(ring, 8); 1853 /* set resources */ 1854 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 1855 amdgpu_ring_write(ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ 1856 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ 1857 amdgpu_ring_write(ring, 0); /* queue mask hi */ 1858 amdgpu_ring_write(ring, 0); /* gws mask lo */ 1859 amdgpu_ring_write(ring, 0); /* gws mask hi */ 1860 amdgpu_ring_write(ring, 0); /* oac mask */ 1861 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ 1862 amdgpu_ring_commit(ring); 1863 udelay(50); 1864 } 1865 1866 static void gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, 1867 struct amdgpu_ring *ring) 1868 { 1869 struct amdgpu_device *adev = kiq_ring->adev; 1870 uint64_t mqd_addr, wptr_addr; 1871 1872 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 1873 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1874 amdgpu_ring_alloc(kiq_ring, 8); 1875 1876 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 1877 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 1878 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 1879 (0 << 4) | /* Queue_Sel */ 1880 (0 << 8) | /* VMID */ 1881 (ring->queue << 13 ) | 1882 (ring->pipe << 16) | 1883 ((ring->me == 1 ? 0 : 1) << 18) | 1884 (0 << 21) | /*queue_type: normal compute queue */ 1885 (1 << 24) | /* alloc format: all_on_one_pipe */ 1886 (0 << 26) | /* engine_sel: compute */ 1887 (1 << 29)); /* num_queues: must be 1 */ 1888 amdgpu_ring_write(kiq_ring, (ring->doorbell_index << 2)); 1889 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 1890 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 1891 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 1892 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 1893 amdgpu_ring_commit(kiq_ring); 1894 udelay(50); 1895 } 1896 1897 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 1898 { 1899 struct amdgpu_device *adev = ring->adev; 1900 struct v9_mqd *mqd = ring->mqd_ptr; 1901 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1902 uint32_t tmp; 1903 1904 mqd->header = 0xC0310800; 1905 mqd->compute_pipelinestat_enable = 0x00000001; 1906 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1907 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1908 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1909 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1910 mqd->compute_misc_reserved = 0x00000003; 1911 1912 eop_base_addr = ring->eop_gpu_addr >> 8; 1913 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1914 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1915 1916 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1917 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL)); 1918 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1919 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 1920 1921 mqd->cp_hqd_eop_control = tmp; 1922 1923 /* enable doorbell? */ 1924 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); 1925 1926 if (ring->use_doorbell) { 1927 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1928 DOORBELL_OFFSET, ring->doorbell_index); 1929 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1930 DOORBELL_EN, 1); 1931 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1932 DOORBELL_SOURCE, 0); 1933 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1934 DOORBELL_HIT, 0); 1935 } 1936 else 1937 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1938 DOORBELL_EN, 0); 1939 1940 mqd->cp_hqd_pq_doorbell_control = tmp; 1941 1942 /* disable the queue if it's active */ 1943 ring->wptr = 0; 1944 mqd->cp_hqd_dequeue_request = 0; 1945 mqd->cp_hqd_pq_rptr = 0; 1946 mqd->cp_hqd_pq_wptr_lo = 0; 1947 mqd->cp_hqd_pq_wptr_hi = 0; 1948 1949 /* set the pointer to the MQD */ 1950 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1951 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1952 1953 /* set MQD vmid to 0 */ 1954 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL)); 1955 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1956 mqd->cp_mqd_control = tmp; 1957 1958 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1959 hqd_gpu_addr = ring->gpu_addr >> 8; 1960 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1961 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1962 1963 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1964 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL)); 1965 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1966 (order_base_2(ring->ring_size / 4) - 1)); 1967 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1968 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1969 #ifdef __BIG_ENDIAN 1970 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1971 #endif 1972 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1973 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1974 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1975 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1976 mqd->cp_hqd_pq_control = tmp; 1977 1978 /* set the wb address whether it's enabled or not */ 1979 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1980 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1981 mqd->cp_hqd_pq_rptr_report_addr_hi = 1982 upper_32_bits(wb_gpu_addr) & 0xffff; 1983 1984 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1985 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1986 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1987 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1988 1989 tmp = 0; 1990 /* enable the doorbell if requested */ 1991 if (ring->use_doorbell) { 1992 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); 1993 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1994 DOORBELL_OFFSET, ring->doorbell_index); 1995 1996 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1997 DOORBELL_EN, 1); 1998 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1999 DOORBELL_SOURCE, 0); 2000 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2001 DOORBELL_HIT, 0); 2002 } 2003 2004 mqd->cp_hqd_pq_doorbell_control = tmp; 2005 2006 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2007 ring->wptr = 0; 2008 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2009 2010 /* set the vmid for the queue */ 2011 mqd->cp_hqd_vmid = 0; 2012 2013 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); 2014 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2015 mqd->cp_hqd_persistent_state = tmp; 2016 2017 /* activate the queue */ 2018 mqd->cp_hqd_active = 1; 2019 2020 return 0; 2021 } 2022 2023 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2024 { 2025 struct amdgpu_device *adev = ring->adev; 2026 struct v9_mqd *mqd = ring->mqd_ptr; 2027 uint32_t tmp; 2028 int j; 2029 2030 /* disable wptr polling */ 2031 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL)); 2032 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2033 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp); 2034 2035 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), 2036 mqd->cp_hqd_eop_base_addr_lo); 2037 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), 2038 mqd->cp_hqd_eop_base_addr_hi); 2039 2040 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2041 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), 2042 mqd->cp_hqd_eop_control); 2043 2044 /* enable doorbell? */ 2045 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 2046 mqd->cp_hqd_pq_doorbell_control); 2047 2048 /* disable the queue if it's active */ 2049 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) { 2050 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1); 2051 for (j = 0; j < adev->usec_timeout; j++) { 2052 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1)) 2053 break; 2054 udelay(1); 2055 } 2056 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 2057 mqd->cp_hqd_dequeue_request); 2058 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), 2059 mqd->cp_hqd_pq_rptr); 2060 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 2061 mqd->cp_hqd_pq_wptr_lo); 2062 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 2063 mqd->cp_hqd_pq_wptr_hi); 2064 } 2065 2066 /* set the pointer to the MQD */ 2067 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), 2068 mqd->cp_mqd_base_addr_lo); 2069 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), 2070 mqd->cp_mqd_base_addr_hi); 2071 2072 /* set MQD vmid to 0 */ 2073 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), 2074 mqd->cp_mqd_control); 2075 2076 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2077 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), 2078 mqd->cp_hqd_pq_base_lo); 2079 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), 2080 mqd->cp_hqd_pq_base_hi); 2081 2082 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2083 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), 2084 mqd->cp_hqd_pq_control); 2085 2086 /* set the wb address whether it's enabled or not */ 2087 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR), 2088 mqd->cp_hqd_pq_rptr_report_addr_lo); 2089 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI), 2090 mqd->cp_hqd_pq_rptr_report_addr_hi); 2091 2092 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2093 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 2094 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2095 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 2096 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2097 2098 /* enable the doorbell if requested */ 2099 if (ring->use_doorbell) { 2100 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER), 2101 (AMDGPU_DOORBELL64_KIQ *2) << 2); 2102 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER), 2103 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); 2104 } 2105 2106 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 2107 mqd->cp_hqd_pq_doorbell_control); 2108 2109 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2110 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 2111 mqd->cp_hqd_pq_wptr_lo); 2112 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 2113 mqd->cp_hqd_pq_wptr_hi); 2114 2115 /* set the vmid for the queue */ 2116 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid); 2117 2118 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), 2119 mqd->cp_hqd_persistent_state); 2120 2121 /* activate the queue */ 2122 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), 2123 mqd->cp_hqd_active); 2124 2125 if (ring->use_doorbell) { 2126 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS)); 2127 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2128 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp); 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 2135 { 2136 struct amdgpu_device *adev = ring->adev; 2137 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 2138 struct v9_mqd *mqd = ring->mqd_ptr; 2139 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); 2140 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2141 2142 if (is_kiq) { 2143 gfx_v9_0_kiq_setting(&kiq->ring); 2144 } else { 2145 mqd_idx = ring - &adev->gfx.compute_ring[0]; 2146 } 2147 2148 if (!adev->gfx.in_reset) { 2149 memset((void *)mqd, 0, sizeof(*mqd)); 2150 mutex_lock(&adev->srbm_mutex); 2151 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2152 gfx_v9_0_mqd_init(ring); 2153 if (is_kiq) 2154 gfx_v9_0_kiq_init_register(ring); 2155 soc15_grbm_select(adev, 0, 0, 0, 0); 2156 mutex_unlock(&adev->srbm_mutex); 2157 2158 } else { /* for GPU_RESET case */ 2159 /* reset MQD to a clean status */ 2160 2161 /* reset ring buffer */ 2162 ring->wptr = 0; 2163 2164 if (is_kiq) { 2165 mutex_lock(&adev->srbm_mutex); 2166 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2167 gfx_v9_0_kiq_init_register(ring); 2168 soc15_grbm_select(adev, 0, 0, 0, 0); 2169 mutex_unlock(&adev->srbm_mutex); 2170 } 2171 } 2172 2173 if (is_kiq) 2174 gfx_v9_0_kiq_enable(ring); 2175 else 2176 gfx_v9_0_map_queue_enable(&kiq->ring, ring); 2177 2178 return 0; 2179 } 2180 2181 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 2182 { 2183 struct amdgpu_ring *ring = NULL; 2184 int r = 0, i; 2185 2186 gfx_v9_0_cp_compute_enable(adev, true); 2187 2188 ring = &adev->gfx.kiq.ring; 2189 2190 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2191 if (unlikely(r != 0)) 2192 goto done; 2193 2194 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2195 if (!r) { 2196 r = gfx_v9_0_kiq_init_queue(ring); 2197 amdgpu_bo_kunmap(ring->mqd_obj); 2198 ring->mqd_ptr = NULL; 2199 } 2200 amdgpu_bo_unreserve(ring->mqd_obj); 2201 if (r) 2202 goto done; 2203 2204 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2205 ring = &adev->gfx.compute_ring[i]; 2206 2207 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2208 if (unlikely(r != 0)) 2209 goto done; 2210 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2211 if (!r) { 2212 r = gfx_v9_0_kiq_init_queue(ring); 2213 amdgpu_bo_kunmap(ring->mqd_obj); 2214 ring->mqd_ptr = NULL; 2215 } 2216 amdgpu_bo_unreserve(ring->mqd_obj); 2217 if (r) 2218 goto done; 2219 } 2220 2221 done: 2222 return r; 2223 } 2224 2225 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 2226 { 2227 int r,i; 2228 struct amdgpu_ring *ring; 2229 2230 if (!(adev->flags & AMD_IS_APU)) 2231 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2232 2233 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2234 /* legacy firmware loading */ 2235 r = gfx_v9_0_cp_gfx_load_microcode(adev); 2236 if (r) 2237 return r; 2238 2239 r = gfx_v9_0_cp_compute_load_microcode(adev); 2240 if (r) 2241 return r; 2242 } 2243 2244 r = gfx_v9_0_cp_gfx_resume(adev); 2245 if (r) 2246 return r; 2247 2248 if (amdgpu_sriov_vf(adev)) 2249 r = gfx_v9_0_kiq_resume(adev); 2250 else 2251 r = gfx_v9_0_cp_compute_resume(adev); 2252 if (r) 2253 return r; 2254 2255 ring = &adev->gfx.gfx_ring[0]; 2256 r = amdgpu_ring_test_ring(ring); 2257 if (r) { 2258 ring->ready = false; 2259 return r; 2260 } 2261 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2262 ring = &adev->gfx.compute_ring[i]; 2263 2264 ring->ready = true; 2265 r = amdgpu_ring_test_ring(ring); 2266 if (r) 2267 ring->ready = false; 2268 } 2269 2270 if (amdgpu_sriov_vf(adev)) { 2271 ring = &adev->gfx.kiq.ring; 2272 ring->ready = true; 2273 r = amdgpu_ring_test_ring(ring); 2274 if (r) 2275 ring->ready = false; 2276 } 2277 2278 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2279 2280 return 0; 2281 } 2282 2283 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 2284 { 2285 gfx_v9_0_cp_gfx_enable(adev, enable); 2286 gfx_v9_0_cp_compute_enable(adev, enable); 2287 } 2288 2289 static int gfx_v9_0_hw_init(void *handle) 2290 { 2291 int r; 2292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2293 2294 gfx_v9_0_init_golden_registers(adev); 2295 2296 gfx_v9_0_gpu_init(adev); 2297 2298 r = gfx_v9_0_rlc_resume(adev); 2299 if (r) 2300 return r; 2301 2302 r = gfx_v9_0_cp_resume(adev); 2303 if (r) 2304 return r; 2305 2306 r = gfx_v9_0_ngg_en(adev); 2307 if (r) 2308 return r; 2309 2310 return r; 2311 } 2312 2313 static int gfx_v9_0_hw_fini(void *handle) 2314 { 2315 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2316 2317 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2318 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2319 if (amdgpu_sriov_vf(adev)) { 2320 pr_debug("For SRIOV client, shouldn't do anything.\n"); 2321 return 0; 2322 } 2323 gfx_v9_0_cp_enable(adev, false); 2324 gfx_v9_0_rlc_stop(adev); 2325 gfx_v9_0_cp_compute_fini(adev); 2326 2327 return 0; 2328 } 2329 2330 static int gfx_v9_0_suspend(void *handle) 2331 { 2332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2333 2334 return gfx_v9_0_hw_fini(adev); 2335 } 2336 2337 static int gfx_v9_0_resume(void *handle) 2338 { 2339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2340 2341 return gfx_v9_0_hw_init(adev); 2342 } 2343 2344 static bool gfx_v9_0_is_idle(void *handle) 2345 { 2346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2347 2348 if (REG_GET_FIELD(RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)), 2349 GRBM_STATUS, GUI_ACTIVE)) 2350 return false; 2351 else 2352 return true; 2353 } 2354 2355 static int gfx_v9_0_wait_for_idle(void *handle) 2356 { 2357 unsigned i; 2358 u32 tmp; 2359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2360 2361 for (i = 0; i < adev->usec_timeout; i++) { 2362 /* read MC_STATUS */ 2363 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)) & 2364 GRBM_STATUS__GUI_ACTIVE_MASK; 2365 2366 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 2367 return 0; 2368 udelay(1); 2369 } 2370 return -ETIMEDOUT; 2371 } 2372 2373 static void gfx_v9_0_print_status(void *handle) 2374 { 2375 int i; 2376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2377 2378 dev_info(adev->dev, "GFX 9.x registers\n"); 2379 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 2380 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS))); 2381 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 2382 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2))); 2383 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2384 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0))); 2385 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2386 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1))); 2387 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 2388 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2))); 2389 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 2390 RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3))); 2391 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STAT))); 2392 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 2393 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1))); 2394 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 2395 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2))); 2396 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 2397 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3))); 2398 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 2399 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT))); 2400 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 2401 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1))); 2402 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS))); 2403 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_BUSY_STAT))); 2404 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 2405 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1))); 2406 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS))); 2407 2408 for (i = 0; i < 32; i++) { 2409 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", 2410 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_TILE_MODE0 ) + i*4)); 2411 } 2412 for (i = 0; i < 16; i++) { 2413 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", 2414 i, RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_MACROTILE_MODE0) + i*4)); 2415 } 2416 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2417 dev_info(adev->dev, " se: %d\n", i); 2418 gfx_v9_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff); 2419 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", 2420 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG))); 2421 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", 2422 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_RASTER_CONFIG_1))); 2423 } 2424 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2425 2426 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", 2427 RREG32(SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))); 2428 2429 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", 2430 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEQ_THRESHOLDS))); 2431 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", 2432 RREG32(SOC15_REG_OFFSET(GC, 0, mmSX_DEBUG_1))); 2433 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", 2434 RREG32(SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX))); 2435 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", 2436 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL))); 2437 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", 2438 RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG))); 2439 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", 2440 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG))); 2441 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", 2442 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))); 2443 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", 2444 RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG3))); 2445 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", 2446 RREG32(SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL))); 2447 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", 2448 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1))); 2449 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", 2450 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FIFO_SIZE))); 2451 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", 2452 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_NUM_INSTANCES))); 2453 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", 2454 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL))); 2455 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", 2456 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_FORCE_EOV_MAX_CNTS))); 2457 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", 2458 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION))); 2459 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", 2460 RREG32(SOC15_REG_OFFSET(GC, 0, mmVGT_GS_VERTEX_REUSE))); 2461 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", 2462 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE))); 2463 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", 2464 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_CL_ENHANCE))); 2465 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", 2466 RREG32(SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE))); 2467 2468 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", 2469 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL))); 2470 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", 2471 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MAX_CONTEXT))); 2472 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", 2473 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_DEVICE_ID))); 2474 2475 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", 2476 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_SEM_WAIT_TIMER))); 2477 2478 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", 2479 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_DELAY))); 2480 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", 2481 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_VMID))); 2482 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 2483 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL))); 2484 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", 2485 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR))); 2486 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", 2487 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR))); 2488 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", 2489 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_RPTR_ADDR_HI))); 2490 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 2491 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_CNTL))); 2492 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", 2493 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE))); 2494 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", 2495 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_BASE_HI))); 2496 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", 2497 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_CNTL))); 2498 2499 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", 2500 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_ADDR))); 2501 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", 2502 RREG32(SOC15_REG_OFFSET(GC, 0, mmSCRATCH_UMSK))); 2503 2504 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", 2505 RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0))); 2506 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 2507 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL))); 2508 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", 2509 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL))); 2510 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", 2511 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL))); 2512 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", 2513 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_INIT))); 2514 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", 2515 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTR_MAX))); 2516 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", 2517 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_INIT_CU_MASK))); 2518 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", 2519 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_PARAMS))); 2520 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 2521 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_LB_CNTL))); 2522 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", 2523 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_UCODE_CNTL))); 2524 2525 dev_info(adev->dev, " RLC_GPM_GENERAL_6=0x%08X\n", 2526 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_6))); 2527 dev_info(adev->dev, " RLC_GPM_GENERAL_12=0x%08X\n", 2528 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_GENERAL_12))); 2529 dev_info(adev->dev, " RLC_GPM_TIMER_INT_3=0x%08X\n", 2530 RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_TIMER_INT_3))); 2531 mutex_lock(&adev->srbm_mutex); 2532 for (i = 0; i < 16; i++) { 2533 soc15_grbm_select(adev, 0, 0, 0, i); 2534 dev_info(adev->dev, " VM %d:\n", i); 2535 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", 2536 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))); 2537 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", 2538 RREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES))); 2539 } 2540 soc15_grbm_select(adev, 0, 0, 0, 0); 2541 mutex_unlock(&adev->srbm_mutex); 2542 } 2543 2544 static int gfx_v9_0_soft_reset(void *handle) 2545 { 2546 u32 grbm_soft_reset = 0; 2547 u32 tmp; 2548 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2549 2550 /* GRBM_STATUS */ 2551 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)); 2552 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2553 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2554 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2555 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2556 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2557 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2558 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2559 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2560 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2561 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2562 } 2563 2564 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2565 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2566 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2567 } 2568 2569 /* GRBM_STATUS2 */ 2570 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)); 2571 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2572 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2573 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2574 2575 2576 if (grbm_soft_reset ) { 2577 gfx_v9_0_print_status((void *)adev); 2578 /* stop the rlc */ 2579 gfx_v9_0_rlc_stop(adev); 2580 2581 /* Disable GFX parsing/prefetching */ 2582 gfx_v9_0_cp_gfx_enable(adev, false); 2583 2584 /* Disable MEC parsing/prefetching */ 2585 gfx_v9_0_cp_compute_enable(adev, false); 2586 2587 if (grbm_soft_reset) { 2588 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); 2589 tmp |= grbm_soft_reset; 2590 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2591 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); 2592 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); 2593 2594 udelay(50); 2595 2596 tmp &= ~grbm_soft_reset; 2597 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET), tmp); 2598 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_SOFT_RESET)); 2599 } 2600 2601 /* Wait a little for things to settle down */ 2602 udelay(50); 2603 gfx_v9_0_print_status((void *)adev); 2604 } 2605 return 0; 2606 } 2607 2608 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2609 { 2610 uint64_t clock; 2611 2612 mutex_lock(&adev->gfx.gpu_clock_mutex); 2613 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT), 1); 2614 clock = (uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB)) | 2615 ((uint64_t)RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB)) << 32ULL); 2616 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2617 return clock; 2618 } 2619 2620 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 2621 uint32_t vmid, 2622 uint32_t gds_base, uint32_t gds_size, 2623 uint32_t gws_base, uint32_t gws_size, 2624 uint32_t oa_base, uint32_t oa_size) 2625 { 2626 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 2627 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 2628 2629 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 2630 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 2631 2632 oa_base = oa_base >> AMDGPU_OA_SHIFT; 2633 oa_size = oa_size >> AMDGPU_OA_SHIFT; 2634 2635 /* GDS Base */ 2636 gfx_v9_0_write_data_to_reg(ring, 0, false, 2637 amdgpu_gds_reg_offset[vmid].mem_base, 2638 gds_base); 2639 2640 /* GDS Size */ 2641 gfx_v9_0_write_data_to_reg(ring, 0, false, 2642 amdgpu_gds_reg_offset[vmid].mem_size, 2643 gds_size); 2644 2645 /* GWS */ 2646 gfx_v9_0_write_data_to_reg(ring, 0, false, 2647 amdgpu_gds_reg_offset[vmid].gws, 2648 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2649 2650 /* OA */ 2651 gfx_v9_0_write_data_to_reg(ring, 0, false, 2652 amdgpu_gds_reg_offset[vmid].oa, 2653 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2654 } 2655 2656 static int gfx_v9_0_early_init(void *handle) 2657 { 2658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2659 2660 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 2661 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS; 2662 gfx_v9_0_set_ring_funcs(adev); 2663 gfx_v9_0_set_irq_funcs(adev); 2664 gfx_v9_0_set_gds_init(adev); 2665 gfx_v9_0_set_rlc_funcs(adev); 2666 2667 return 0; 2668 } 2669 2670 static int gfx_v9_0_late_init(void *handle) 2671 { 2672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2673 int r; 2674 2675 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2676 if (r) 2677 return r; 2678 2679 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2680 if (r) 2681 return r; 2682 2683 return 0; 2684 } 2685 2686 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 2687 { 2688 uint32_t rlc_setting, data; 2689 unsigned i; 2690 2691 if (adev->gfx.rlc.in_safe_mode) 2692 return; 2693 2694 /* if RLC is not enabled, do nothing */ 2695 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); 2696 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 2697 return; 2698 2699 if (adev->cg_flags & 2700 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | 2701 AMD_CG_SUPPORT_GFX_3D_CGCG)) { 2702 data = RLC_SAFE_MODE__CMD_MASK; 2703 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 2704 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data); 2705 2706 /* wait for RLC_SAFE_MODE */ 2707 for (i = 0; i < adev->usec_timeout; i++) { 2708 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 2709 break; 2710 udelay(1); 2711 } 2712 adev->gfx.rlc.in_safe_mode = true; 2713 } 2714 } 2715 2716 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 2717 { 2718 uint32_t rlc_setting, data; 2719 2720 if (!adev->gfx.rlc.in_safe_mode) 2721 return; 2722 2723 /* if RLC is not enabled, do nothing */ 2724 rlc_setting = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CNTL)); 2725 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 2726 return; 2727 2728 if (adev->cg_flags & 2729 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 2730 /* 2731 * Try to exit safe mode only if it is already in safe 2732 * mode. 2733 */ 2734 data = RLC_SAFE_MODE__CMD_MASK; 2735 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), data); 2736 adev->gfx.rlc.in_safe_mode = false; 2737 } 2738 } 2739 2740 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2741 bool enable) 2742 { 2743 uint32_t data, def; 2744 2745 /* It is disabled by HW by default */ 2746 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2747 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2748 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 2749 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 2750 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2751 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2752 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2753 2754 /* only for Vega10 & Raven1 */ 2755 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 2756 2757 if (def != data) 2758 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); 2759 2760 /* MGLS is a global flag to control all MGLS in GFX */ 2761 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2762 /* 2 - RLC memory Light sleep */ 2763 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2764 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 2765 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2766 if (def != data) 2767 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data); 2768 } 2769 /* 3 - CP memory Light sleep */ 2770 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2771 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 2772 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2773 if (def != data) 2774 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data); 2775 } 2776 } 2777 } else { 2778 /* 1 - MGCG_OVERRIDE */ 2779 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 2780 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 2781 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2782 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2783 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2784 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2785 if (def != data) 2786 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); 2787 2788 /* 2 - disable MGLS in RLC */ 2789 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 2790 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2791 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL), data); 2793 } 2794 2795 /* 3 - disable MGLS in CP */ 2796 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 2797 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2798 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2799 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL), data); 2800 } 2801 } 2802 } 2803 2804 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 2805 bool enable) 2806 { 2807 uint32_t data, def; 2808 2809 adev->gfx.rlc.funcs->enter_safe_mode(adev); 2810 2811 /* Enable 3D CGCG/CGLS */ 2812 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 2813 /* write cmd to clear cgcg/cgls ov */ 2814 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 2815 /* unset CGCG override */ 2816 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 2817 /* update CGCG and CGLS override bits */ 2818 if (def != data) 2819 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); 2820 /* enable 3Dcgcg FSM(0x0020003f) */ 2821 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 2822 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2823 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 2824 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 2825 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2826 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 2827 if (def != data) 2828 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data); 2829 2830 /* set IDLE_POLL_COUNT(0x00900100) */ 2831 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2832 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2833 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2834 if (def != data) 2835 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2836 } else { 2837 /* Disable CGCG/CGLS */ 2838 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 2839 /* disable cgcg, cgls should be disabled */ 2840 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 2841 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 2842 /* disable cgcg and cgls in FSM */ 2843 if (def != data) 2844 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D), data); 2845 } 2846 2847 adev->gfx.rlc.funcs->exit_safe_mode(adev); 2848 } 2849 2850 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2851 bool enable) 2852 { 2853 uint32_t def, data; 2854 2855 adev->gfx.rlc.funcs->enter_safe_mode(adev); 2856 2857 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2858 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 2859 /* unset CGCG override */ 2860 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2861 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2862 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2863 else 2864 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2865 /* update CGCG and CGLS override bits */ 2866 if (def != data) 2867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE), data); 2868 2869 /* enable cgcg FSM(0x0020003F) */ 2870 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 2871 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2872 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2873 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2874 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2875 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2876 if (def != data) 2877 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data); 2878 2879 /* set IDLE_POLL_COUNT(0x00900100) */ 2880 def = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2881 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2882 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2883 if (def != data) 2884 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2885 } else { 2886 def = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 2887 /* reset CGCG/CGLS bits */ 2888 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2889 /* disable cgcg and cgls in FSM */ 2890 if (def != data) 2891 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL), data); 2892 } 2893 2894 adev->gfx.rlc.funcs->exit_safe_mode(adev); 2895 } 2896 2897 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 2898 bool enable) 2899 { 2900 if (enable) { 2901 /* CGCG/CGLS should be enabled after MGCG/MGLS 2902 * === MGCG + MGLS === 2903 */ 2904 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 2905 /* === CGCG /CGLS for GFX 3D Only === */ 2906 gfx_v9_0_update_3d_clock_gating(adev, enable); 2907 /* === CGCG + CGLS === */ 2908 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 2909 } else { 2910 /* CGCG/CGLS should be disabled before MGCG/MGLS 2911 * === CGCG + CGLS === 2912 */ 2913 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 2914 /* === CGCG /CGLS for GFX 3D Only === */ 2915 gfx_v9_0_update_3d_clock_gating(adev, enable); 2916 /* === MGCG + MGLS === */ 2917 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 2918 } 2919 return 0; 2920 } 2921 2922 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 2923 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 2924 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 2925 }; 2926 2927 static int gfx_v9_0_set_powergating_state(void *handle, 2928 enum amd_powergating_state state) 2929 { 2930 return 0; 2931 } 2932 2933 static int gfx_v9_0_set_clockgating_state(void *handle, 2934 enum amd_clockgating_state state) 2935 { 2936 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2937 2938 switch (adev->asic_type) { 2939 case CHIP_VEGA10: 2940 gfx_v9_0_update_gfx_clock_gating(adev, 2941 state == AMD_CG_STATE_GATE ? true : false); 2942 break; 2943 default: 2944 break; 2945 } 2946 return 0; 2947 } 2948 2949 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 2950 { 2951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2952 int data; 2953 2954 if (amdgpu_sriov_vf(adev)) 2955 *flags = 0; 2956 2957 /* AMD_CG_SUPPORT_GFX_MGCG */ 2958 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 2959 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2960 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2961 2962 /* AMD_CG_SUPPORT_GFX_CGCG */ 2963 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 2964 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2965 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2966 2967 /* AMD_CG_SUPPORT_GFX_CGLS */ 2968 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2969 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2970 2971 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2972 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 2973 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2974 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2975 2976 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2977 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 2978 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2979 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2980 2981 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 2982 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 2983 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 2984 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 2985 2986 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 2987 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 2988 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 2989 } 2990 2991 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 2992 { 2993 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 2994 } 2995 2996 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2997 { 2998 struct amdgpu_device *adev = ring->adev; 2999 u64 wptr; 3000 3001 /* XXX check if swapping is necessary on BE */ 3002 if (ring->use_doorbell) { 3003 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3004 } else { 3005 wptr = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR)); 3006 wptr += (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI)) << 32; 3007 } 3008 3009 return wptr; 3010 } 3011 3012 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3013 { 3014 struct amdgpu_device *adev = ring->adev; 3015 3016 if (ring->use_doorbell) { 3017 /* XXX check if swapping is necessary on BE */ 3018 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3019 WDOORBELL64(ring->doorbell_index, ring->wptr); 3020 } else { 3021 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR), lower_32_bits(ring->wptr)); 3022 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB0_WPTR_HI), upper_32_bits(ring->wptr)); 3023 } 3024 } 3025 3026 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3027 { 3028 u32 ref_and_mask, reg_mem_engine; 3029 struct nbio_hdp_flush_reg *nbio_hf_reg; 3030 3031 if (ring->adev->asic_type == CHIP_VEGA10) 3032 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 3033 3034 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3035 switch (ring->me) { 3036 case 1: 3037 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3038 break; 3039 case 2: 3040 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3041 break; 3042 default: 3043 return; 3044 } 3045 reg_mem_engine = 0; 3046 } else { 3047 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3048 reg_mem_engine = 1; /* pfp */ 3049 } 3050 3051 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3052 nbio_hf_reg->hdp_flush_req_offset, 3053 nbio_hf_reg->hdp_flush_done_offset, 3054 ref_and_mask, ref_and_mask, 0x20); 3055 } 3056 3057 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 3058 { 3059 gfx_v9_0_write_data_to_reg(ring, 0, true, 3060 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1); 3061 } 3062 3063 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3064 struct amdgpu_ib *ib, 3065 unsigned vm_id, bool ctx_switch) 3066 { 3067 u32 header, control = 0; 3068 3069 if (ib->flags & AMDGPU_IB_FLAG_CE) 3070 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3071 else 3072 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3073 3074 control |= ib->length_dw | (vm_id << 24); 3075 3076 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) 3077 control |= INDIRECT_BUFFER_PRE_ENB(1); 3078 3079 amdgpu_ring_write(ring, header); 3080 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3081 amdgpu_ring_write(ring, 3082 #ifdef __BIG_ENDIAN 3083 (2 << 0) | 3084 #endif 3085 lower_32_bits(ib->gpu_addr)); 3086 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3087 amdgpu_ring_write(ring, control); 3088 } 3089 3090 #define INDIRECT_BUFFER_VALID (1 << 23) 3091 3092 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3093 struct amdgpu_ib *ib, 3094 unsigned vm_id, bool ctx_switch) 3095 { 3096 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 3097 3098 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3099 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3100 amdgpu_ring_write(ring, 3101 #ifdef __BIG_ENDIAN 3102 (2 << 0) | 3103 #endif 3104 lower_32_bits(ib->gpu_addr)); 3105 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3106 amdgpu_ring_write(ring, control); 3107 } 3108 3109 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3110 u64 seq, unsigned flags) 3111 { 3112 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3113 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3114 3115 /* RELEASE_MEM - flush caches, send int */ 3116 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3117 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3118 EOP_TC_ACTION_EN | 3119 EOP_TC_WB_ACTION_EN | 3120 EOP_TC_MD_ACTION_EN | 3121 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3122 EVENT_INDEX(5))); 3123 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3124 3125 /* 3126 * the address should be Qword aligned if 64bit write, Dword 3127 * aligned if only send 32bit data low (discard data high) 3128 */ 3129 if (write64bit) 3130 BUG_ON(addr & 0x7); 3131 else 3132 BUG_ON(addr & 0x3); 3133 amdgpu_ring_write(ring, lower_32_bits(addr)); 3134 amdgpu_ring_write(ring, upper_32_bits(addr)); 3135 amdgpu_ring_write(ring, lower_32_bits(seq)); 3136 amdgpu_ring_write(ring, upper_32_bits(seq)); 3137 amdgpu_ring_write(ring, 0); 3138 } 3139 3140 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3141 { 3142 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3143 uint32_t seq = ring->fence_drv.sync_seq; 3144 uint64_t addr = ring->fence_drv.gpu_addr; 3145 3146 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 3147 lower_32_bits(addr), upper_32_bits(addr), 3148 seq, 0xffffffff, 4); 3149 } 3150 3151 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3152 unsigned vm_id, uint64_t pd_addr) 3153 { 3154 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3155 unsigned eng = ring->idx; 3156 unsigned i; 3157 3158 pd_addr = pd_addr | 0x1; /* valid bit */ 3159 /* now only use physical base address of PDE and valid */ 3160 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 3161 3162 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 3163 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; 3164 uint32_t req = hub->get_invalidate_req(vm_id); 3165 3166 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3167 hub->ctx0_ptb_addr_lo32 3168 + (2 * vm_id), 3169 lower_32_bits(pd_addr)); 3170 3171 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3172 hub->ctx0_ptb_addr_hi32 3173 + (2 * vm_id), 3174 upper_32_bits(pd_addr)); 3175 3176 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3177 hub->vm_inv_eng0_req + eng, req); 3178 3179 /* wait for the invalidate to complete */ 3180 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + 3181 eng, 0, 1 << vm_id, 1 << vm_id, 0x20); 3182 } 3183 3184 /* compute doesn't have PFP */ 3185 if (usepfp) { 3186 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3187 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3188 amdgpu_ring_write(ring, 0x0); 3189 } 3190 } 3191 3192 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3193 { 3194 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3195 } 3196 3197 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3198 { 3199 u64 wptr; 3200 3201 /* XXX check if swapping is necessary on BE */ 3202 if (ring->use_doorbell) 3203 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3204 else 3205 BUG(); 3206 return wptr; 3207 } 3208 3209 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 3210 { 3211 struct amdgpu_device *adev = ring->adev; 3212 3213 /* XXX check if swapping is necessary on BE */ 3214 if (ring->use_doorbell) { 3215 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3216 WDOORBELL64(ring->doorbell_index, ring->wptr); 3217 } else{ 3218 BUG(); /* only DOORBELL method supported on gfx9 now */ 3219 } 3220 } 3221 3222 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3223 u64 seq, unsigned int flags) 3224 { 3225 /* we only allocate 32bit for each seq wb address */ 3226 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 3227 3228 /* write fence seq to the "addr" */ 3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3230 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3231 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3232 amdgpu_ring_write(ring, lower_32_bits(addr)); 3233 amdgpu_ring_write(ring, upper_32_bits(addr)); 3234 amdgpu_ring_write(ring, lower_32_bits(seq)); 3235 3236 if (flags & AMDGPU_FENCE_FLAG_INT) { 3237 /* set register to trigger INT */ 3238 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3239 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3240 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3241 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 3242 amdgpu_ring_write(ring, 0); 3243 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3244 } 3245 } 3246 3247 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 3248 { 3249 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3250 amdgpu_ring_write(ring, 0); 3251 } 3252 3253 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 3254 { 3255 static struct v9_ce_ib_state ce_payload = {0}; 3256 uint64_t csa_addr; 3257 int cnt; 3258 3259 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 3260 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3261 3262 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3263 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 3264 WRITE_DATA_DST_SEL(8) | 3265 WR_CONFIRM) | 3266 WRITE_DATA_CACHE_POLICY(0)); 3267 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3268 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3269 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 3270 } 3271 3272 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 3273 { 3274 static struct v9_de_ib_state de_payload = {0}; 3275 uint64_t csa_addr, gds_addr; 3276 int cnt; 3277 3278 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3279 gds_addr = csa_addr + 4096; 3280 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 3281 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 3282 3283 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 3284 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3285 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 3286 WRITE_DATA_DST_SEL(8) | 3287 WR_CONFIRM) | 3288 WRITE_DATA_CACHE_POLICY(0)); 3289 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3290 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3291 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 3292 } 3293 3294 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3295 { 3296 uint32_t dw2 = 0; 3297 3298 if (amdgpu_sriov_vf(ring->adev)) 3299 gfx_v9_0_ring_emit_ce_meta(ring); 3300 3301 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3302 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3303 /* set load_global_config & load_global_uconfig */ 3304 dw2 |= 0x8001; 3305 /* set load_cs_sh_regs */ 3306 dw2 |= 0x01000000; 3307 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 3308 dw2 |= 0x10002; 3309 3310 /* set load_ce_ram if preamble presented */ 3311 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 3312 dw2 |= 0x10000000; 3313 } else { 3314 /* still load_ce_ram if this is the first time preamble presented 3315 * although there is no context switch happens. 3316 */ 3317 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 3318 dw2 |= 0x10000000; 3319 } 3320 3321 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3322 amdgpu_ring_write(ring, dw2); 3323 amdgpu_ring_write(ring, 0); 3324 3325 if (amdgpu_sriov_vf(ring->adev)) 3326 gfx_v9_0_ring_emit_de_meta(ring); 3327 } 3328 3329 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 3330 { 3331 unsigned ret; 3332 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 3333 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 3334 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 3335 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 3336 ret = ring->wptr & ring->buf_mask; 3337 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 3338 return ret; 3339 } 3340 3341 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 3342 { 3343 unsigned cur; 3344 BUG_ON(offset > ring->buf_mask); 3345 BUG_ON(ring->ring[offset] != 0x55aa55aa); 3346 3347 cur = (ring->wptr & ring->buf_mask) - 1; 3348 if (likely(cur > offset)) 3349 ring->ring[offset] = cur - offset; 3350 else 3351 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 3352 } 3353 3354 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 3355 { 3356 struct amdgpu_device *adev = ring->adev; 3357 3358 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3359 amdgpu_ring_write(ring, 0 | /* src: register*/ 3360 (5 << 8) | /* dst: memory */ 3361 (1 << 20)); /* write confirm */ 3362 amdgpu_ring_write(ring, reg); 3363 amdgpu_ring_write(ring, 0); 3364 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3365 adev->virt.reg_val_offs * 4)); 3366 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3367 adev->virt.reg_val_offs * 4)); 3368 } 3369 3370 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3371 uint32_t val) 3372 { 3373 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3374 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ 3375 amdgpu_ring_write(ring, reg); 3376 amdgpu_ring_write(ring, 0); 3377 amdgpu_ring_write(ring, val); 3378 } 3379 3380 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3381 enum amdgpu_interrupt_state state) 3382 { 3383 u32 cp_int_cntl; 3384 3385 switch (state) { 3386 case AMDGPU_IRQ_STATE_DISABLE: 3387 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3388 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3389 TIME_STAMP_INT_ENABLE, 0); 3390 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3391 break; 3392 case AMDGPU_IRQ_STATE_ENABLE: 3393 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3394 cp_int_cntl = 3395 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3396 TIME_STAMP_INT_ENABLE, 1); 3397 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3398 break; 3399 default: 3400 break; 3401 } 3402 } 3403 3404 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3405 int me, int pipe, 3406 enum amdgpu_interrupt_state state) 3407 { 3408 u32 mec_int_cntl, mec_int_cntl_reg; 3409 3410 /* 3411 * amdgpu controls only pipe 0 of MEC1. That's why this function only 3412 * handles the setting of interrupts for this specific pipe. All other 3413 * pipes' interrupts are set by amdkfd. 3414 */ 3415 3416 if (me == 1) { 3417 switch (pipe) { 3418 case 0: 3419 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 3420 break; 3421 default: 3422 DRM_DEBUG("invalid pipe %d\n", pipe); 3423 return; 3424 } 3425 } else { 3426 DRM_DEBUG("invalid me %d\n", me); 3427 return; 3428 } 3429 3430 switch (state) { 3431 case AMDGPU_IRQ_STATE_DISABLE: 3432 mec_int_cntl = RREG32(mec_int_cntl_reg); 3433 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3434 TIME_STAMP_INT_ENABLE, 0); 3435 WREG32(mec_int_cntl_reg, mec_int_cntl); 3436 break; 3437 case AMDGPU_IRQ_STATE_ENABLE: 3438 mec_int_cntl = RREG32(mec_int_cntl_reg); 3439 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3440 TIME_STAMP_INT_ENABLE, 1); 3441 WREG32(mec_int_cntl_reg, mec_int_cntl); 3442 break; 3443 default: 3444 break; 3445 } 3446 } 3447 3448 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3449 struct amdgpu_irq_src *source, 3450 unsigned type, 3451 enum amdgpu_interrupt_state state) 3452 { 3453 u32 cp_int_cntl; 3454 3455 switch (state) { 3456 case AMDGPU_IRQ_STATE_DISABLE: 3457 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3458 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3459 PRIV_REG_INT_ENABLE, 0); 3460 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3461 break; 3462 case AMDGPU_IRQ_STATE_ENABLE: 3463 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3464 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3465 PRIV_REG_INT_ENABLE, 1); 3466 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3467 break; 3468 default: 3469 break; 3470 } 3471 3472 return 0; 3473 } 3474 3475 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3476 struct amdgpu_irq_src *source, 3477 unsigned type, 3478 enum amdgpu_interrupt_state state) 3479 { 3480 u32 cp_int_cntl; 3481 3482 switch (state) { 3483 case AMDGPU_IRQ_STATE_DISABLE: 3484 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3485 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3486 PRIV_INSTR_INT_ENABLE, 0); 3487 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3488 break; 3489 case AMDGPU_IRQ_STATE_ENABLE: 3490 cp_int_cntl = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)); 3491 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 3492 PRIV_INSTR_INT_ENABLE, 1); 3493 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0), cp_int_cntl); 3494 break; 3495 default: 3496 break; 3497 } 3498 3499 return 0; 3500 } 3501 3502 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3503 struct amdgpu_irq_src *src, 3504 unsigned type, 3505 enum amdgpu_interrupt_state state) 3506 { 3507 switch (type) { 3508 case AMDGPU_CP_IRQ_GFX_EOP: 3509 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 3510 break; 3511 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3512 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 3513 break; 3514 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3515 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 3516 break; 3517 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3518 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 3519 break; 3520 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3521 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 3522 break; 3523 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3524 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 3525 break; 3526 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3527 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 3528 break; 3529 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3530 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 3531 break; 3532 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3533 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 3534 break; 3535 default: 3536 break; 3537 } 3538 return 0; 3539 } 3540 3541 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 3542 struct amdgpu_irq_src *source, 3543 struct amdgpu_iv_entry *entry) 3544 { 3545 int i; 3546 u8 me_id, pipe_id, queue_id; 3547 struct amdgpu_ring *ring; 3548 3549 DRM_DEBUG("IH: CP EOP\n"); 3550 me_id = (entry->ring_id & 0x0c) >> 2; 3551 pipe_id = (entry->ring_id & 0x03) >> 0; 3552 queue_id = (entry->ring_id & 0x70) >> 4; 3553 3554 switch (me_id) { 3555 case 0: 3556 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3557 break; 3558 case 1: 3559 case 2: 3560 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3561 ring = &adev->gfx.compute_ring[i]; 3562 /* Per-queue interrupt is supported for MEC starting from VI. 3563 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3564 */ 3565 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3566 amdgpu_fence_process(ring); 3567 } 3568 break; 3569 } 3570 return 0; 3571 } 3572 3573 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 3574 struct amdgpu_irq_src *source, 3575 struct amdgpu_iv_entry *entry) 3576 { 3577 DRM_ERROR("Illegal register access in command stream\n"); 3578 schedule_work(&adev->reset_work); 3579 return 0; 3580 } 3581 3582 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 3583 struct amdgpu_irq_src *source, 3584 struct amdgpu_iv_entry *entry) 3585 { 3586 DRM_ERROR("Illegal instruction in command stream\n"); 3587 schedule_work(&adev->reset_work); 3588 return 0; 3589 } 3590 3591 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 3592 struct amdgpu_irq_src *src, 3593 unsigned int type, 3594 enum amdgpu_interrupt_state state) 3595 { 3596 uint32_t tmp, target; 3597 struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data; 3598 3599 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); 3600 3601 if (ring->me == 1) 3602 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 3603 else 3604 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 3605 target += ring->pipe; 3606 3607 switch (type) { 3608 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 3609 if (state == AMDGPU_IRQ_STATE_DISABLE) { 3610 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL)); 3611 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 3612 GENERIC2_INT_ENABLE, 0); 3613 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp); 3614 3615 tmp = RREG32(target); 3616 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 3617 GENERIC2_INT_ENABLE, 0); 3618 WREG32(target, tmp); 3619 } else { 3620 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL)); 3621 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 3622 GENERIC2_INT_ENABLE, 1); 3623 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), tmp); 3624 3625 tmp = RREG32(target); 3626 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 3627 GENERIC2_INT_ENABLE, 1); 3628 WREG32(target, tmp); 3629 } 3630 break; 3631 default: 3632 BUG(); /* kiq only support GENERIC2_INT now */ 3633 break; 3634 } 3635 return 0; 3636 } 3637 3638 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, 3639 struct amdgpu_irq_src *source, 3640 struct amdgpu_iv_entry *entry) 3641 { 3642 u8 me_id, pipe_id, queue_id; 3643 struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data; 3644 3645 BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)); 3646 3647 me_id = (entry->ring_id & 0x0c) >> 2; 3648 pipe_id = (entry->ring_id & 0x03) >> 0; 3649 queue_id = (entry->ring_id & 0x70) >> 4; 3650 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 3651 me_id, pipe_id, queue_id); 3652 3653 amdgpu_fence_process(ring); 3654 return 0; 3655 } 3656 3657 const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 3658 .name = "gfx_v9_0", 3659 .early_init = gfx_v9_0_early_init, 3660 .late_init = gfx_v9_0_late_init, 3661 .sw_init = gfx_v9_0_sw_init, 3662 .sw_fini = gfx_v9_0_sw_fini, 3663 .hw_init = gfx_v9_0_hw_init, 3664 .hw_fini = gfx_v9_0_hw_fini, 3665 .suspend = gfx_v9_0_suspend, 3666 .resume = gfx_v9_0_resume, 3667 .is_idle = gfx_v9_0_is_idle, 3668 .wait_for_idle = gfx_v9_0_wait_for_idle, 3669 .soft_reset = gfx_v9_0_soft_reset, 3670 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 3671 .set_powergating_state = gfx_v9_0_set_powergating_state, 3672 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 3673 }; 3674 3675 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 3676 .type = AMDGPU_RING_TYPE_GFX, 3677 .align_mask = 0xff, 3678 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3679 .support_64bit_ptrs = true, 3680 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 3681 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 3682 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 3683 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 3684 5 + /* COND_EXEC */ 3685 7 + /* PIPELINE_SYNC */ 3686 46 + /* VM_FLUSH */ 3687 8 + /* FENCE for VM_FLUSH */ 3688 20 + /* GDS switch */ 3689 4 + /* double SWITCH_BUFFER, 3690 the first COND_EXEC jump to the place just 3691 prior to this double SWITCH_BUFFER */ 3692 5 + /* COND_EXEC */ 3693 7 + /* HDP_flush */ 3694 4 + /* VGT_flush */ 3695 14 + /* CE_META */ 3696 31 + /* DE_META */ 3697 3 + /* CNTX_CTRL */ 3698 5 + /* HDP_INVL */ 3699 8 + 8 + /* FENCE x2 */ 3700 2, /* SWITCH_BUFFER */ 3701 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 3702 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 3703 .emit_fence = gfx_v9_0_ring_emit_fence, 3704 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 3705 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 3706 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 3707 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 3708 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 3709 .test_ring = gfx_v9_0_ring_test_ring, 3710 .test_ib = gfx_v9_0_ring_test_ib, 3711 .insert_nop = amdgpu_ring_insert_nop, 3712 .pad_ib = amdgpu_ring_generic_pad_ib, 3713 .emit_switch_buffer = gfx_v9_ring_emit_sb, 3714 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 3715 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 3716 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 3717 }; 3718 3719 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 3720 .type = AMDGPU_RING_TYPE_COMPUTE, 3721 .align_mask = 0xff, 3722 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3723 .support_64bit_ptrs = true, 3724 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 3725 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 3726 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 3727 .emit_frame_size = 3728 20 + /* gfx_v9_0_ring_emit_gds_switch */ 3729 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 3730 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 3731 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 3732 64 + /* gfx_v9_0_ring_emit_vm_flush */ 3733 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 3734 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 3735 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 3736 .emit_fence = gfx_v9_0_ring_emit_fence, 3737 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 3738 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 3739 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 3740 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 3741 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 3742 .test_ring = gfx_v9_0_ring_test_ring, 3743 .test_ib = gfx_v9_0_ring_test_ib, 3744 .insert_nop = amdgpu_ring_insert_nop, 3745 .pad_ib = amdgpu_ring_generic_pad_ib, 3746 }; 3747 3748 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 3749 .type = AMDGPU_RING_TYPE_KIQ, 3750 .align_mask = 0xff, 3751 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3752 .support_64bit_ptrs = true, 3753 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 3754 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 3755 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 3756 .emit_frame_size = 3757 20 + /* gfx_v9_0_ring_emit_gds_switch */ 3758 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 3759 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 3760 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 3761 64 + /* gfx_v9_0_ring_emit_vm_flush */ 3762 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 3763 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 3764 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 3765 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 3766 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 3767 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 3768 .test_ring = gfx_v9_0_ring_test_ring, 3769 .test_ib = gfx_v9_0_ring_test_ib, 3770 .insert_nop = amdgpu_ring_insert_nop, 3771 .pad_ib = amdgpu_ring_generic_pad_ib, 3772 .emit_rreg = gfx_v9_0_ring_emit_rreg, 3773 .emit_wreg = gfx_v9_0_ring_emit_wreg, 3774 }; 3775 3776 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 3777 { 3778 int i; 3779 3780 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 3781 3782 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3783 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 3784 3785 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3786 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 3787 } 3788 3789 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { 3790 .set = gfx_v9_0_kiq_set_interrupt_state, 3791 .process = gfx_v9_0_kiq_irq, 3792 }; 3793 3794 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 3795 .set = gfx_v9_0_set_eop_interrupt_state, 3796 .process = gfx_v9_0_eop_irq, 3797 }; 3798 3799 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 3800 .set = gfx_v9_0_set_priv_reg_fault_state, 3801 .process = gfx_v9_0_priv_reg_irq, 3802 }; 3803 3804 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 3805 .set = gfx_v9_0_set_priv_inst_fault_state, 3806 .process = gfx_v9_0_priv_inst_irq, 3807 }; 3808 3809 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 3810 { 3811 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3812 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 3813 3814 adev->gfx.priv_reg_irq.num_types = 1; 3815 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 3816 3817 adev->gfx.priv_inst_irq.num_types = 1; 3818 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 3819 3820 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 3821 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; 3822 } 3823 3824 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 3825 { 3826 switch (adev->asic_type) { 3827 case CHIP_VEGA10: 3828 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 3829 break; 3830 default: 3831 break; 3832 } 3833 } 3834 3835 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 3836 { 3837 /* init asci gds info */ 3838 adev->gds.mem.total_size = RREG32(SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)); 3839 adev->gds.gws.total_size = 64; 3840 adev->gds.oa.total_size = 16; 3841 3842 if (adev->gds.mem.total_size == 64 * 1024) { 3843 adev->gds.mem.gfx_partition_size = 4096; 3844 adev->gds.mem.cs_partition_size = 4096; 3845 3846 adev->gds.gws.gfx_partition_size = 4; 3847 adev->gds.gws.cs_partition_size = 4; 3848 3849 adev->gds.oa.gfx_partition_size = 4; 3850 adev->gds.oa.cs_partition_size = 1; 3851 } else { 3852 adev->gds.mem.gfx_partition_size = 1024; 3853 adev->gds.mem.cs_partition_size = 1024; 3854 3855 adev->gds.gws.gfx_partition_size = 16; 3856 adev->gds.gws.cs_partition_size = 16; 3857 3858 adev->gds.oa.gfx_partition_size = 4; 3859 adev->gds.oa.cs_partition_size = 4; 3860 } 3861 } 3862 3863 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3864 { 3865 u32 data, mask; 3866 3867 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG)); 3868 data |= RREG32(SOC15_REG_OFFSET(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG)); 3869 3870 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3871 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3872 3873 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 3874 3875 return (~data) & mask; 3876 } 3877 3878 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 3879 struct amdgpu_cu_info *cu_info) 3880 { 3881 int i, j, k, counter, active_cu_number = 0; 3882 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3883 3884 if (!adev || !cu_info) 3885 return -EINVAL; 3886 3887 memset(cu_info, 0, sizeof(*cu_info)); 3888 3889 mutex_lock(&adev->grbm_idx_mutex); 3890 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3891 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3892 mask = 1; 3893 ao_bitmap = 0; 3894 counter = 0; 3895 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 3896 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 3897 cu_info->bitmap[i][j] = bitmap; 3898 3899 for (k = 0; k < 16; k ++) { 3900 if (bitmap & mask) { 3901 if (counter < 2) 3902 ao_bitmap |= mask; 3903 counter ++; 3904 } 3905 mask <<= 1; 3906 } 3907 active_cu_number += counter; 3908 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3909 } 3910 } 3911 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3912 mutex_unlock(&adev->grbm_idx_mutex); 3913 3914 cu_info->number = active_cu_number; 3915 cu_info->ao_cu_mask = ao_cu_mask; 3916 3917 return 0; 3918 } 3919 3920 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) 3921 { 3922 int r, j; 3923 u32 tmp; 3924 bool use_doorbell = true; 3925 u64 hqd_gpu_addr; 3926 u64 mqd_gpu_addr; 3927 u64 eop_gpu_addr; 3928 u64 wb_gpu_addr; 3929 u32 *buf; 3930 struct v9_mqd *mqd; 3931 struct amdgpu_device *adev; 3932 3933 adev = ring->adev; 3934 if (ring->mqd_obj == NULL) { 3935 r = amdgpu_bo_create(adev, 3936 sizeof(struct v9_mqd), 3937 PAGE_SIZE,true, 3938 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, 3939 NULL, &ring->mqd_obj); 3940 if (r) { 3941 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3942 return r; 3943 } 3944 } 3945 3946 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3947 if (unlikely(r != 0)) { 3948 gfx_v9_0_cp_compute_fini(adev); 3949 return r; 3950 } 3951 3952 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 3953 &mqd_gpu_addr); 3954 if (r) { 3955 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 3956 gfx_v9_0_cp_compute_fini(adev); 3957 return r; 3958 } 3959 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 3960 if (r) { 3961 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 3962 gfx_v9_0_cp_compute_fini(adev); 3963 return r; 3964 } 3965 3966 /* init the mqd struct */ 3967 memset(buf, 0, sizeof(struct v9_mqd)); 3968 3969 mqd = (struct v9_mqd *)buf; 3970 mqd->header = 0xC0310800; 3971 mqd->compute_pipelinestat_enable = 0x00000001; 3972 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3973 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3974 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3975 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3976 mqd->compute_misc_reserved = 0x00000003; 3977 mutex_lock(&adev->srbm_mutex); 3978 soc15_grbm_select(adev, ring->me, 3979 ring->pipe, 3980 ring->queue, 0); 3981 /* disable wptr polling */ 3982 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL)); 3983 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3984 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp); 3985 3986 /* write the EOP addr */ 3987 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */ 3988 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE); 3989 eop_gpu_addr >>= 8; 3990 3991 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR), lower_32_bits(eop_gpu_addr)); 3992 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI), upper_32_bits(eop_gpu_addr)); 3993 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr); 3994 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr); 3995 3996 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3997 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL)); 3998 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3999 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 4000 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_CONTROL), tmp); 4001 4002 /* enable doorbell? */ 4003 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); 4004 if (use_doorbell) 4005 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 4006 else 4007 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); 4008 4009 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), tmp); 4010 mqd->cp_hqd_pq_doorbell_control = tmp; 4011 4012 /* disable the queue if it's active */ 4013 ring->wptr = 0; 4014 mqd->cp_hqd_dequeue_request = 0; 4015 mqd->cp_hqd_pq_rptr = 0; 4016 mqd->cp_hqd_pq_wptr_lo = 0; 4017 mqd->cp_hqd_pq_wptr_hi = 0; 4018 if (RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1) { 4019 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), 1); 4020 for (j = 0; j < adev->usec_timeout; j++) { 4021 if (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)) & 1)) 4022 break; 4023 udelay(1); 4024 } 4025 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), mqd->cp_hqd_dequeue_request); 4026 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR), mqd->cp_hqd_pq_rptr); 4027 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo); 4028 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi); 4029 } 4030 4031 /* set the pointer to the MQD */ 4032 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 4033 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 4034 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR), mqd->cp_mqd_base_addr_lo); 4035 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR_HI), mqd->cp_mqd_base_addr_hi); 4036 4037 /* set MQD vmid to 0 */ 4038 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL)); 4039 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4040 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MQD_CONTROL), tmp); 4041 mqd->cp_mqd_control = tmp; 4042 4043 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4044 hqd_gpu_addr = ring->gpu_addr >> 8; 4045 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4046 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4047 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE), mqd->cp_hqd_pq_base_lo); 4048 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI), mqd->cp_hqd_pq_base_hi); 4049 4050 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4051 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL)); 4052 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4053 (order_base_2(ring->ring_size / 4) - 1)); 4054 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4055 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4056 #ifdef __BIG_ENDIAN 4057 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4058 #endif 4059 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4060 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 4061 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4062 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4063 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_CONTROL), tmp); 4064 mqd->cp_hqd_pq_control = tmp; 4065 4066 /* set the wb address wether it's enabled or not */ 4067 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 4068 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4069 mqd->cp_hqd_pq_rptr_report_addr_hi = 4070 upper_32_bits(wb_gpu_addr) & 0xffff; 4071 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR), 4072 mqd->cp_hqd_pq_rptr_report_addr_lo); 4073 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI), 4074 mqd->cp_hqd_pq_rptr_report_addr_hi); 4075 4076 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4077 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4078 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4079 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4080 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 4081 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4082 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 4083 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4084 4085 /* enable the doorbell if requested */ 4086 if (use_doorbell) { 4087 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER), 4088 (AMDGPU_DOORBELL64_KIQ * 2) << 2); 4089 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER), 4090 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2); 4091 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)); 4092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4093 DOORBELL_OFFSET, ring->doorbell_index); 4094 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 4095 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); 4096 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); 4097 mqd->cp_hqd_pq_doorbell_control = tmp; 4098 4099 } else { 4100 mqd->cp_hqd_pq_doorbell_control = 0; 4101 } 4102 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), 4103 mqd->cp_hqd_pq_doorbell_control); 4104 4105 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4106 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), mqd->cp_hqd_pq_wptr_lo); 4107 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), mqd->cp_hqd_pq_wptr_hi); 4108 4109 /* set the vmid for the queue */ 4110 mqd->cp_hqd_vmid = 0; 4111 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_VMID), mqd->cp_hqd_vmid); 4112 4113 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE)); 4114 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 4115 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PERSISTENT_STATE), tmp); 4116 mqd->cp_hqd_persistent_state = tmp; 4117 4118 /* activate the queue */ 4119 mqd->cp_hqd_active = 1; 4120 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), mqd->cp_hqd_active); 4121 4122 soc15_grbm_select(adev, 0, 0, 0, 0); 4123 mutex_unlock(&adev->srbm_mutex); 4124 4125 amdgpu_bo_kunmap(ring->mqd_obj); 4126 amdgpu_bo_unreserve(ring->mqd_obj); 4127 4128 if (use_doorbell) { 4129 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS)); 4130 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4131 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp); 4132 } 4133 4134 return 0; 4135 } 4136 4137 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4138 { 4139 .type = AMD_IP_BLOCK_TYPE_GFX, 4140 .major = 9, 4141 .minor = 0, 4142 .rev = 0, 4143 .funcs = &gfx_v9_0_ip_funcs, 4144 }; 4145