1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_atomfirmware.h" 31 32 #include "gc/gc_9_0_offset.h" 33 #include "gc/gc_9_0_sh_mask.h" 34 #include "vega10_enum.h" 35 #include "hdp/hdp_4_0_offset.h" 36 37 #include "soc15_common.h" 38 #include "clearstate_gfx9.h" 39 #include "v9_structs.h" 40 41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 42 43 #define GFX9_NUM_GFX_RINGS 1 44 #define GFX9_MEC_HPD_SIZE 4096 45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 47 48 #define mmPWR_MISC_CNTL_STATUS 0x0183 49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 54 55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 57 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 61 62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 75 76 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 79 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 89 90 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 91 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 92 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 93 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 94 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 95 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 96 97 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 98 { 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 116 }; 117 118 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 119 { 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 141 }; 142 143 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 144 { 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 156 }; 157 158 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 159 { 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 184 }; 185 186 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 187 { 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 195 }; 196 197 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 198 { 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 218 }; 219 220 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 221 { 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 224 }; 225 226 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 227 { 228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 244 }; 245 246 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 247 { 248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 261 }; 262 263 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 264 { 265 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 266 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 267 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 268 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 269 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 270 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 271 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 272 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 273 }; 274 275 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 276 { 277 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 278 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 279 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 280 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 281 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 282 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 283 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 284 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 285 }; 286 287 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 288 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 289 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 290 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 291 292 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 293 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 294 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 295 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 296 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 297 struct amdgpu_cu_info *cu_info); 298 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 299 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 300 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 301 302 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 303 { 304 switch (adev->asic_type) { 305 case CHIP_VEGA10: 306 soc15_program_register_sequence(adev, 307 golden_settings_gc_9_0, 308 ARRAY_SIZE(golden_settings_gc_9_0)); 309 soc15_program_register_sequence(adev, 310 golden_settings_gc_9_0_vg10, 311 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 312 break; 313 case CHIP_VEGA12: 314 soc15_program_register_sequence(adev, 315 golden_settings_gc_9_2_1, 316 ARRAY_SIZE(golden_settings_gc_9_2_1)); 317 soc15_program_register_sequence(adev, 318 golden_settings_gc_9_2_1_vg12, 319 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 320 break; 321 case CHIP_VEGA20: 322 soc15_program_register_sequence(adev, 323 golden_settings_gc_9_0, 324 ARRAY_SIZE(golden_settings_gc_9_0)); 325 soc15_program_register_sequence(adev, 326 golden_settings_gc_9_0_vg20, 327 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 328 break; 329 case CHIP_RAVEN: 330 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 331 ARRAY_SIZE(golden_settings_gc_9_1)); 332 if (adev->rev_id >= 8) 333 soc15_program_register_sequence(adev, 334 golden_settings_gc_9_1_rv2, 335 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 336 else 337 soc15_program_register_sequence(adev, 338 golden_settings_gc_9_1_rv1, 339 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 340 break; 341 default: 342 break; 343 } 344 345 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 346 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 347 } 348 349 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 350 { 351 adev->gfx.scratch.num_reg = 8; 352 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 353 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 354 } 355 356 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 357 bool wc, uint32_t reg, uint32_t val) 358 { 359 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 360 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 361 WRITE_DATA_DST_SEL(0) | 362 (wc ? WR_CONFIRM : 0)); 363 amdgpu_ring_write(ring, reg); 364 amdgpu_ring_write(ring, 0); 365 amdgpu_ring_write(ring, val); 366 } 367 368 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 369 int mem_space, int opt, uint32_t addr0, 370 uint32_t addr1, uint32_t ref, uint32_t mask, 371 uint32_t inv) 372 { 373 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 374 amdgpu_ring_write(ring, 375 /* memory (1) or register (0) */ 376 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 377 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 378 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 379 WAIT_REG_MEM_ENGINE(eng_sel))); 380 381 if (mem_space) 382 BUG_ON(addr0 & 0x3); /* Dword align */ 383 amdgpu_ring_write(ring, addr0); 384 amdgpu_ring_write(ring, addr1); 385 amdgpu_ring_write(ring, ref); 386 amdgpu_ring_write(ring, mask); 387 amdgpu_ring_write(ring, inv); /* poll interval */ 388 } 389 390 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 391 { 392 struct amdgpu_device *adev = ring->adev; 393 uint32_t scratch; 394 uint32_t tmp = 0; 395 unsigned i; 396 int r; 397 398 r = amdgpu_gfx_scratch_get(adev, &scratch); 399 if (r) 400 return r; 401 402 WREG32(scratch, 0xCAFEDEAD); 403 r = amdgpu_ring_alloc(ring, 3); 404 if (r) 405 goto error_free_scratch; 406 407 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 408 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 409 amdgpu_ring_write(ring, 0xDEADBEEF); 410 amdgpu_ring_commit(ring); 411 412 for (i = 0; i < adev->usec_timeout; i++) { 413 tmp = RREG32(scratch); 414 if (tmp == 0xDEADBEEF) 415 break; 416 DRM_UDELAY(1); 417 } 418 419 if (i >= adev->usec_timeout) 420 r = -ETIMEDOUT; 421 422 error_free_scratch: 423 amdgpu_gfx_scratch_free(adev, scratch); 424 return r; 425 } 426 427 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 428 { 429 struct amdgpu_device *adev = ring->adev; 430 struct amdgpu_ib ib; 431 struct dma_fence *f = NULL; 432 433 unsigned index; 434 uint64_t gpu_addr; 435 uint32_t tmp; 436 long r; 437 438 r = amdgpu_device_wb_get(adev, &index); 439 if (r) 440 return r; 441 442 gpu_addr = adev->wb.gpu_addr + (index * 4); 443 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 444 memset(&ib, 0, sizeof(ib)); 445 r = amdgpu_ib_get(adev, NULL, 16, &ib); 446 if (r) 447 goto err1; 448 449 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 450 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 451 ib.ptr[2] = lower_32_bits(gpu_addr); 452 ib.ptr[3] = upper_32_bits(gpu_addr); 453 ib.ptr[4] = 0xDEADBEEF; 454 ib.length_dw = 5; 455 456 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 457 if (r) 458 goto err2; 459 460 r = dma_fence_wait_timeout(f, false, timeout); 461 if (r == 0) { 462 r = -ETIMEDOUT; 463 goto err2; 464 } else if (r < 0) { 465 goto err2; 466 } 467 468 tmp = adev->wb.wb[index]; 469 if (tmp == 0xDEADBEEF) 470 r = 0; 471 else 472 r = -EINVAL; 473 474 err2: 475 amdgpu_ib_free(adev, &ib, NULL); 476 dma_fence_put(f); 477 err1: 478 amdgpu_device_wb_free(adev, index); 479 return r; 480 } 481 482 483 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 484 { 485 release_firmware(adev->gfx.pfp_fw); 486 adev->gfx.pfp_fw = NULL; 487 release_firmware(adev->gfx.me_fw); 488 adev->gfx.me_fw = NULL; 489 release_firmware(adev->gfx.ce_fw); 490 adev->gfx.ce_fw = NULL; 491 release_firmware(adev->gfx.rlc_fw); 492 adev->gfx.rlc_fw = NULL; 493 release_firmware(adev->gfx.mec_fw); 494 adev->gfx.mec_fw = NULL; 495 release_firmware(adev->gfx.mec2_fw); 496 adev->gfx.mec2_fw = NULL; 497 498 kfree(adev->gfx.rlc.register_list_format); 499 } 500 501 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 502 { 503 const struct rlc_firmware_header_v2_1 *rlc_hdr; 504 505 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 506 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 507 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 508 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 509 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 510 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 511 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 512 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 513 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 514 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 515 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 516 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 517 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 518 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 519 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 520 } 521 522 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 523 { 524 adev->gfx.me_fw_write_wait = false; 525 adev->gfx.mec_fw_write_wait = false; 526 527 switch (adev->asic_type) { 528 case CHIP_VEGA10: 529 if ((adev->gfx.me_fw_version >= 0x0000009c) && 530 (adev->gfx.me_feature_version >= 42) && 531 (adev->gfx.pfp_fw_version >= 0x000000b1) && 532 (adev->gfx.pfp_feature_version >= 42)) 533 adev->gfx.me_fw_write_wait = true; 534 535 if ((adev->gfx.mec_fw_version >= 0x00000193) && 536 (adev->gfx.mec_feature_version >= 42)) 537 adev->gfx.mec_fw_write_wait = true; 538 break; 539 case CHIP_VEGA12: 540 if ((adev->gfx.me_fw_version >= 0x0000009c) && 541 (adev->gfx.me_feature_version >= 44) && 542 (adev->gfx.pfp_fw_version >= 0x000000b2) && 543 (adev->gfx.pfp_feature_version >= 44)) 544 adev->gfx.me_fw_write_wait = true; 545 546 if ((adev->gfx.mec_fw_version >= 0x00000196) && 547 (adev->gfx.mec_feature_version >= 44)) 548 adev->gfx.mec_fw_write_wait = true; 549 break; 550 case CHIP_VEGA20: 551 if ((adev->gfx.me_fw_version >= 0x0000009c) && 552 (adev->gfx.me_feature_version >= 44) && 553 (adev->gfx.pfp_fw_version >= 0x000000b2) && 554 (adev->gfx.pfp_feature_version >= 44)) 555 adev->gfx.me_fw_write_wait = true; 556 557 if ((adev->gfx.mec_fw_version >= 0x00000197) && 558 (adev->gfx.mec_feature_version >= 44)) 559 adev->gfx.mec_fw_write_wait = true; 560 break; 561 case CHIP_RAVEN: 562 if ((adev->gfx.me_fw_version >= 0x0000009c) && 563 (adev->gfx.me_feature_version >= 42) && 564 (adev->gfx.pfp_fw_version >= 0x000000b1) && 565 (adev->gfx.pfp_feature_version >= 42)) 566 adev->gfx.me_fw_write_wait = true; 567 568 if ((adev->gfx.mec_fw_version >= 0x00000192) && 569 (adev->gfx.mec_feature_version >= 42)) 570 adev->gfx.mec_fw_write_wait = true; 571 break; 572 default: 573 break; 574 } 575 } 576 577 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 578 { 579 const char *chip_name; 580 char fw_name[30]; 581 int err; 582 struct amdgpu_firmware_info *info = NULL; 583 const struct common_firmware_header *header = NULL; 584 const struct gfx_firmware_header_v1_0 *cp_hdr; 585 const struct rlc_firmware_header_v2_0 *rlc_hdr; 586 unsigned int *tmp = NULL; 587 unsigned int i = 0; 588 uint16_t version_major; 589 uint16_t version_minor; 590 591 DRM_DEBUG("\n"); 592 593 switch (adev->asic_type) { 594 case CHIP_VEGA10: 595 chip_name = "vega10"; 596 break; 597 case CHIP_VEGA12: 598 chip_name = "vega12"; 599 break; 600 case CHIP_VEGA20: 601 chip_name = "vega20"; 602 break; 603 case CHIP_RAVEN: 604 if (adev->rev_id >= 8) 605 chip_name = "raven2"; 606 else if (adev->pdev->device == 0x15d8) 607 chip_name = "picasso"; 608 else 609 chip_name = "raven"; 610 break; 611 default: 612 BUG(); 613 } 614 615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 616 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 617 if (err) 618 goto out; 619 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 620 if (err) 621 goto out; 622 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 623 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 624 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 625 626 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 627 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 628 if (err) 629 goto out; 630 err = amdgpu_ucode_validate(adev->gfx.me_fw); 631 if (err) 632 goto out; 633 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 634 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 635 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 636 637 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 638 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 639 if (err) 640 goto out; 641 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 642 if (err) 643 goto out; 644 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 645 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 646 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 647 648 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 649 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 650 if (err) 651 goto out; 652 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 653 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 654 655 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 656 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 657 if (version_major == 2 && version_minor == 1) 658 adev->gfx.rlc.is_rlc_v2_1 = true; 659 660 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 661 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 662 adev->gfx.rlc.save_and_restore_offset = 663 le32_to_cpu(rlc_hdr->save_and_restore_offset); 664 adev->gfx.rlc.clear_state_descriptor_offset = 665 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 666 adev->gfx.rlc.avail_scratch_ram_locations = 667 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 668 adev->gfx.rlc.reg_restore_list_size = 669 le32_to_cpu(rlc_hdr->reg_restore_list_size); 670 adev->gfx.rlc.reg_list_format_start = 671 le32_to_cpu(rlc_hdr->reg_list_format_start); 672 adev->gfx.rlc.reg_list_format_separate_start = 673 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 674 adev->gfx.rlc.starting_offsets_start = 675 le32_to_cpu(rlc_hdr->starting_offsets_start); 676 adev->gfx.rlc.reg_list_format_size_bytes = 677 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 678 adev->gfx.rlc.reg_list_size_bytes = 679 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 680 adev->gfx.rlc.register_list_format = 681 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 682 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 683 if (!adev->gfx.rlc.register_list_format) { 684 err = -ENOMEM; 685 goto out; 686 } 687 688 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 689 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 690 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 691 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 692 693 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 694 695 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 696 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 697 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 698 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 699 700 if (adev->gfx.rlc.is_rlc_v2_1) 701 gfx_v9_0_init_rlc_ext_microcode(adev); 702 703 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 704 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 705 if (err) 706 goto out; 707 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 708 if (err) 709 goto out; 710 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 711 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 712 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 713 714 715 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 716 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 717 if (!err) { 718 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 719 if (err) 720 goto out; 721 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 722 adev->gfx.mec2_fw->data; 723 adev->gfx.mec2_fw_version = 724 le32_to_cpu(cp_hdr->header.ucode_version); 725 adev->gfx.mec2_feature_version = 726 le32_to_cpu(cp_hdr->ucode_feature_version); 727 } else { 728 err = 0; 729 adev->gfx.mec2_fw = NULL; 730 } 731 732 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 733 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 734 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 735 info->fw = adev->gfx.pfp_fw; 736 header = (const struct common_firmware_header *)info->fw->data; 737 adev->firmware.fw_size += 738 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 739 740 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 741 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 742 info->fw = adev->gfx.me_fw; 743 header = (const struct common_firmware_header *)info->fw->data; 744 adev->firmware.fw_size += 745 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 746 747 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 748 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 749 info->fw = adev->gfx.ce_fw; 750 header = (const struct common_firmware_header *)info->fw->data; 751 adev->firmware.fw_size += 752 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 753 754 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 755 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 756 info->fw = adev->gfx.rlc_fw; 757 header = (const struct common_firmware_header *)info->fw->data; 758 adev->firmware.fw_size += 759 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 760 761 if (adev->gfx.rlc.is_rlc_v2_1 && 762 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 763 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 764 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 765 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 766 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 767 info->fw = adev->gfx.rlc_fw; 768 adev->firmware.fw_size += 769 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 770 771 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 772 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 773 info->fw = adev->gfx.rlc_fw; 774 adev->firmware.fw_size += 775 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 776 777 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 778 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 779 info->fw = adev->gfx.rlc_fw; 780 adev->firmware.fw_size += 781 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 782 } 783 784 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 785 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 786 info->fw = adev->gfx.mec_fw; 787 header = (const struct common_firmware_header *)info->fw->data; 788 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 789 adev->firmware.fw_size += 790 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 791 792 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 793 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 794 info->fw = adev->gfx.mec_fw; 795 adev->firmware.fw_size += 796 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 797 798 if (adev->gfx.mec2_fw) { 799 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 800 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 801 info->fw = adev->gfx.mec2_fw; 802 header = (const struct common_firmware_header *)info->fw->data; 803 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 804 adev->firmware.fw_size += 805 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 806 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 807 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 808 info->fw = adev->gfx.mec2_fw; 809 adev->firmware.fw_size += 810 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 811 } 812 813 } 814 815 out: 816 gfx_v9_0_check_fw_write_wait(adev); 817 if (err) { 818 dev_err(adev->dev, 819 "gfx9: Failed to load firmware \"%s\"\n", 820 fw_name); 821 release_firmware(adev->gfx.pfp_fw); 822 adev->gfx.pfp_fw = NULL; 823 release_firmware(adev->gfx.me_fw); 824 adev->gfx.me_fw = NULL; 825 release_firmware(adev->gfx.ce_fw); 826 adev->gfx.ce_fw = NULL; 827 release_firmware(adev->gfx.rlc_fw); 828 adev->gfx.rlc_fw = NULL; 829 release_firmware(adev->gfx.mec_fw); 830 adev->gfx.mec_fw = NULL; 831 release_firmware(adev->gfx.mec2_fw); 832 adev->gfx.mec2_fw = NULL; 833 } 834 return err; 835 } 836 837 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 838 { 839 u32 count = 0; 840 const struct cs_section_def *sect = NULL; 841 const struct cs_extent_def *ext = NULL; 842 843 /* begin clear state */ 844 count += 2; 845 /* context control state */ 846 count += 3; 847 848 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 849 for (ext = sect->section; ext->extent != NULL; ++ext) { 850 if (sect->id == SECT_CONTEXT) 851 count += 2 + ext->reg_count; 852 else 853 return 0; 854 } 855 } 856 857 /* end clear state */ 858 count += 2; 859 /* clear state */ 860 count += 2; 861 862 return count; 863 } 864 865 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 866 volatile u32 *buffer) 867 { 868 u32 count = 0, i; 869 const struct cs_section_def *sect = NULL; 870 const struct cs_extent_def *ext = NULL; 871 872 if (adev->gfx.rlc.cs_data == NULL) 873 return; 874 if (buffer == NULL) 875 return; 876 877 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 878 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 879 880 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 881 buffer[count++] = cpu_to_le32(0x80000000); 882 buffer[count++] = cpu_to_le32(0x80000000); 883 884 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 885 for (ext = sect->section; ext->extent != NULL; ++ext) { 886 if (sect->id == SECT_CONTEXT) { 887 buffer[count++] = 888 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 889 buffer[count++] = cpu_to_le32(ext->reg_index - 890 PACKET3_SET_CONTEXT_REG_START); 891 for (i = 0; i < ext->reg_count; i++) 892 buffer[count++] = cpu_to_le32(ext->extent[i]); 893 } else { 894 return; 895 } 896 } 897 } 898 899 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 900 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 901 902 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 903 buffer[count++] = cpu_to_le32(0); 904 } 905 906 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 907 { 908 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 909 uint32_t pg_always_on_cu_num = 2; 910 uint32_t always_on_cu_num; 911 uint32_t i, j, k; 912 uint32_t mask, cu_bitmap, counter; 913 914 if (adev->flags & AMD_IS_APU) 915 always_on_cu_num = 4; 916 else if (adev->asic_type == CHIP_VEGA12) 917 always_on_cu_num = 8; 918 else 919 always_on_cu_num = 12; 920 921 mutex_lock(&adev->grbm_idx_mutex); 922 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 923 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 924 mask = 1; 925 cu_bitmap = 0; 926 counter = 0; 927 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 928 929 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 930 if (cu_info->bitmap[i][j] & mask) { 931 if (counter == pg_always_on_cu_num) 932 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 933 if (counter < always_on_cu_num) 934 cu_bitmap |= mask; 935 else 936 break; 937 counter++; 938 } 939 mask <<= 1; 940 } 941 942 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 943 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 944 } 945 } 946 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 947 mutex_unlock(&adev->grbm_idx_mutex); 948 } 949 950 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 951 { 952 uint32_t data; 953 954 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 955 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 956 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 957 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 958 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 959 960 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 961 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 962 963 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 964 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 965 966 mutex_lock(&adev->grbm_idx_mutex); 967 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 968 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 969 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 970 971 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 972 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 973 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 974 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 975 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 976 977 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 978 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 979 data &= 0x0000FFFF; 980 data |= 0x00C00000; 981 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 982 983 /* 984 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 985 * programmed in gfx_v9_0_init_always_on_cu_mask() 986 */ 987 988 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 989 * but used for RLC_LB_CNTL configuration */ 990 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 991 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 992 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 993 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 994 mutex_unlock(&adev->grbm_idx_mutex); 995 996 gfx_v9_0_init_always_on_cu_mask(adev); 997 } 998 999 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1000 { 1001 uint32_t data; 1002 1003 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1004 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1005 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1006 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1007 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1008 1009 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1010 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1011 1012 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1013 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1014 1015 mutex_lock(&adev->grbm_idx_mutex); 1016 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1017 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1018 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1019 1020 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1021 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1022 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1023 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1024 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1025 1026 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1027 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1028 data &= 0x0000FFFF; 1029 data |= 0x00C00000; 1030 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1031 1032 /* 1033 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1034 * programmed in gfx_v9_0_init_always_on_cu_mask() 1035 */ 1036 1037 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1038 * but used for RLC_LB_CNTL configuration */ 1039 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1040 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1041 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1042 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1043 mutex_unlock(&adev->grbm_idx_mutex); 1044 1045 gfx_v9_0_init_always_on_cu_mask(adev); 1046 } 1047 1048 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1049 { 1050 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1051 } 1052 1053 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1054 { 1055 return 5; 1056 } 1057 1058 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1059 { 1060 const struct cs_section_def *cs_data; 1061 int r; 1062 1063 adev->gfx.rlc.cs_data = gfx9_cs_data; 1064 1065 cs_data = adev->gfx.rlc.cs_data; 1066 1067 if (cs_data) { 1068 /* init clear state block */ 1069 r = amdgpu_gfx_rlc_init_csb(adev); 1070 if (r) 1071 return r; 1072 } 1073 1074 if (adev->asic_type == CHIP_RAVEN) { 1075 /* TODO: double check the cp_table_size for RV */ 1076 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1077 r = amdgpu_gfx_rlc_init_cpt(adev); 1078 if (r) 1079 return r; 1080 } 1081 1082 switch (adev->asic_type) { 1083 case CHIP_RAVEN: 1084 gfx_v9_0_init_lbpw(adev); 1085 break; 1086 case CHIP_VEGA20: 1087 gfx_v9_4_init_lbpw(adev); 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev) 1097 { 1098 int r; 1099 1100 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1101 if (unlikely(r != 0)) 1102 return r; 1103 1104 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 1105 AMDGPU_GEM_DOMAIN_VRAM); 1106 if (!r) 1107 adev->gfx.rlc.clear_state_gpu_addr = 1108 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 1109 1110 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1111 1112 return r; 1113 } 1114 1115 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev) 1116 { 1117 int r; 1118 1119 if (!adev->gfx.rlc.clear_state_obj) 1120 return; 1121 1122 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 1123 if (likely(r == 0)) { 1124 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 1125 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1126 } 1127 } 1128 1129 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1130 { 1131 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1132 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1133 } 1134 1135 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1136 { 1137 int r; 1138 u32 *hpd; 1139 const __le32 *fw_data; 1140 unsigned fw_size; 1141 u32 *fw; 1142 size_t mec_hpd_size; 1143 1144 const struct gfx_firmware_header_v1_0 *mec_hdr; 1145 1146 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1147 1148 /* take ownership of the relevant compute queues */ 1149 amdgpu_gfx_compute_queue_acquire(adev); 1150 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1151 1152 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1153 AMDGPU_GEM_DOMAIN_VRAM, 1154 &adev->gfx.mec.hpd_eop_obj, 1155 &adev->gfx.mec.hpd_eop_gpu_addr, 1156 (void **)&hpd); 1157 if (r) { 1158 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1159 gfx_v9_0_mec_fini(adev); 1160 return r; 1161 } 1162 1163 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1164 1165 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1166 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1167 1168 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1169 1170 fw_data = (const __le32 *) 1171 (adev->gfx.mec_fw->data + 1172 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1173 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 1174 1175 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1176 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1177 &adev->gfx.mec.mec_fw_obj, 1178 &adev->gfx.mec.mec_fw_gpu_addr, 1179 (void **)&fw); 1180 if (r) { 1181 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1182 gfx_v9_0_mec_fini(adev); 1183 return r; 1184 } 1185 1186 memcpy(fw, fw_data, fw_size); 1187 1188 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1189 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1190 1191 return 0; 1192 } 1193 1194 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1195 { 1196 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1197 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1198 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1199 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1200 (SQ_IND_INDEX__FORCE_READ_MASK)); 1201 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1202 } 1203 1204 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1205 uint32_t wave, uint32_t thread, 1206 uint32_t regno, uint32_t num, uint32_t *out) 1207 { 1208 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1209 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1210 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1211 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1212 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1213 (SQ_IND_INDEX__FORCE_READ_MASK) | 1214 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1215 while (num--) 1216 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1217 } 1218 1219 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1220 { 1221 /* type 1 wave data */ 1222 dst[(*no_fields)++] = 1; 1223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1231 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1232 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1233 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1234 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1235 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1236 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1237 } 1238 1239 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1240 uint32_t wave, uint32_t start, 1241 uint32_t size, uint32_t *dst) 1242 { 1243 wave_read_regs( 1244 adev, simd, wave, 0, 1245 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1246 } 1247 1248 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1249 uint32_t wave, uint32_t thread, 1250 uint32_t start, uint32_t size, 1251 uint32_t *dst) 1252 { 1253 wave_read_regs( 1254 adev, simd, wave, thread, 1255 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1256 } 1257 1258 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1259 u32 me, u32 pipe, u32 q) 1260 { 1261 soc15_grbm_select(adev, me, pipe, q, 0); 1262 } 1263 1264 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1265 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1266 .select_se_sh = &gfx_v9_0_select_se_sh, 1267 .read_wave_data = &gfx_v9_0_read_wave_data, 1268 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1269 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1270 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q 1271 }; 1272 1273 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1274 { 1275 u32 gb_addr_config; 1276 int err; 1277 1278 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1279 1280 switch (adev->asic_type) { 1281 case CHIP_VEGA10: 1282 adev->gfx.config.max_hw_contexts = 8; 1283 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1284 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1285 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1286 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1287 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1288 break; 1289 case CHIP_VEGA12: 1290 adev->gfx.config.max_hw_contexts = 8; 1291 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1292 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1293 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1294 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1295 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1296 DRM_INFO("fix gfx.config for vega12\n"); 1297 break; 1298 case CHIP_VEGA20: 1299 adev->gfx.config.max_hw_contexts = 8; 1300 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1301 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1302 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1303 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1304 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1305 gb_addr_config &= ~0xf3e777ff; 1306 gb_addr_config |= 0x22014042; 1307 /* check vbios table if gpu info is not available */ 1308 err = amdgpu_atomfirmware_get_gfx_info(adev); 1309 if (err) 1310 return err; 1311 break; 1312 case CHIP_RAVEN: 1313 adev->gfx.config.max_hw_contexts = 8; 1314 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1315 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1316 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1317 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1318 if (adev->rev_id >= 8) 1319 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1320 else 1321 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1322 break; 1323 default: 1324 BUG(); 1325 break; 1326 } 1327 1328 adev->gfx.config.gb_addr_config = gb_addr_config; 1329 1330 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1331 REG_GET_FIELD( 1332 adev->gfx.config.gb_addr_config, 1333 GB_ADDR_CONFIG, 1334 NUM_PIPES); 1335 1336 adev->gfx.config.max_tile_pipes = 1337 adev->gfx.config.gb_addr_config_fields.num_pipes; 1338 1339 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1340 REG_GET_FIELD( 1341 adev->gfx.config.gb_addr_config, 1342 GB_ADDR_CONFIG, 1343 NUM_BANKS); 1344 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1345 REG_GET_FIELD( 1346 adev->gfx.config.gb_addr_config, 1347 GB_ADDR_CONFIG, 1348 MAX_COMPRESSED_FRAGS); 1349 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1350 REG_GET_FIELD( 1351 adev->gfx.config.gb_addr_config, 1352 GB_ADDR_CONFIG, 1353 NUM_RB_PER_SE); 1354 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1355 REG_GET_FIELD( 1356 adev->gfx.config.gb_addr_config, 1357 GB_ADDR_CONFIG, 1358 NUM_SHADER_ENGINES); 1359 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1360 REG_GET_FIELD( 1361 adev->gfx.config.gb_addr_config, 1362 GB_ADDR_CONFIG, 1363 PIPE_INTERLEAVE_SIZE)); 1364 1365 return 0; 1366 } 1367 1368 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1369 struct amdgpu_ngg_buf *ngg_buf, 1370 int size_se, 1371 int default_size_se) 1372 { 1373 int r; 1374 1375 if (size_se < 0) { 1376 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1377 return -EINVAL; 1378 } 1379 size_se = size_se ? size_se : default_size_se; 1380 1381 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1382 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1383 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1384 &ngg_buf->bo, 1385 &ngg_buf->gpu_addr, 1386 NULL); 1387 if (r) { 1388 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1389 return r; 1390 } 1391 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1392 1393 return r; 1394 } 1395 1396 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1397 { 1398 int i; 1399 1400 for (i = 0; i < NGG_BUF_MAX; i++) 1401 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1402 &adev->gfx.ngg.buf[i].gpu_addr, 1403 NULL); 1404 1405 memset(&adev->gfx.ngg.buf[0], 0, 1406 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1407 1408 adev->gfx.ngg.init = false; 1409 1410 return 0; 1411 } 1412 1413 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1414 { 1415 int r; 1416 1417 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1418 return 0; 1419 1420 /* GDS reserve memory: 64 bytes alignment */ 1421 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1422 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1423 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1424 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); 1425 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 1426 1427 /* Primitive Buffer */ 1428 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1429 amdgpu_prim_buf_per_se, 1430 64 * 1024); 1431 if (r) { 1432 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1433 goto err; 1434 } 1435 1436 /* Position Buffer */ 1437 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1438 amdgpu_pos_buf_per_se, 1439 256 * 1024); 1440 if (r) { 1441 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1442 goto err; 1443 } 1444 1445 /* Control Sideband */ 1446 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1447 amdgpu_cntl_sb_buf_per_se, 1448 256); 1449 if (r) { 1450 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1451 goto err; 1452 } 1453 1454 /* Parameter Cache, not created by default */ 1455 if (amdgpu_param_buf_per_se <= 0) 1456 goto out; 1457 1458 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1459 amdgpu_param_buf_per_se, 1460 512 * 1024); 1461 if (r) { 1462 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1463 goto err; 1464 } 1465 1466 out: 1467 adev->gfx.ngg.init = true; 1468 return 0; 1469 err: 1470 gfx_v9_0_ngg_fini(adev); 1471 return r; 1472 } 1473 1474 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1475 { 1476 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1477 int r; 1478 u32 data, base; 1479 1480 if (!amdgpu_ngg) 1481 return 0; 1482 1483 /* Program buffer size */ 1484 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, 1485 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); 1486 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, 1487 adev->gfx.ngg.buf[NGG_POS].size >> 8); 1488 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1489 1490 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, 1491 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); 1492 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, 1493 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); 1494 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1495 1496 /* Program buffer base address */ 1497 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1498 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1499 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1500 1501 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1502 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1503 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1504 1505 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1506 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1507 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1508 1509 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1510 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1511 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1512 1513 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1514 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1515 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1516 1517 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1518 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1519 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1520 1521 /* Clear GDS reserved memory */ 1522 r = amdgpu_ring_alloc(ring, 17); 1523 if (r) { 1524 DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n", 1525 ring->name, r); 1526 return r; 1527 } 1528 1529 gfx_v9_0_write_data_to_reg(ring, 0, false, 1530 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 1531 (adev->gds.mem.total_size + 1532 adev->gfx.ngg.gds_reserve_size)); 1533 1534 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1535 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1536 PACKET3_DMA_DATA_DST_SEL(1) | 1537 PACKET3_DMA_DATA_SRC_SEL(2))); 1538 amdgpu_ring_write(ring, 0); 1539 amdgpu_ring_write(ring, 0); 1540 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1541 amdgpu_ring_write(ring, 0); 1542 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 1543 adev->gfx.ngg.gds_reserve_size); 1544 1545 gfx_v9_0_write_data_to_reg(ring, 0, false, 1546 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); 1547 1548 amdgpu_ring_commit(ring); 1549 1550 return 0; 1551 } 1552 1553 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1554 int mec, int pipe, int queue) 1555 { 1556 int r; 1557 unsigned irq_type; 1558 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1559 1560 ring = &adev->gfx.compute_ring[ring_id]; 1561 1562 /* mec0 is me1 */ 1563 ring->me = mec + 1; 1564 ring->pipe = pipe; 1565 ring->queue = queue; 1566 1567 ring->ring_obj = NULL; 1568 ring->use_doorbell = true; 1569 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1570 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1571 + (ring_id * GFX9_MEC_HPD_SIZE); 1572 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1573 1574 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1575 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1576 + ring->pipe; 1577 1578 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1579 r = amdgpu_ring_init(adev, ring, 1024, 1580 &adev->gfx.eop_irq, irq_type); 1581 if (r) 1582 return r; 1583 1584 1585 return 0; 1586 } 1587 1588 static int gfx_v9_0_sw_init(void *handle) 1589 { 1590 int i, j, k, r, ring_id; 1591 struct amdgpu_ring *ring; 1592 struct amdgpu_kiq *kiq; 1593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1594 1595 switch (adev->asic_type) { 1596 case CHIP_VEGA10: 1597 case CHIP_VEGA12: 1598 case CHIP_VEGA20: 1599 case CHIP_RAVEN: 1600 adev->gfx.mec.num_mec = 2; 1601 break; 1602 default: 1603 adev->gfx.mec.num_mec = 1; 1604 break; 1605 } 1606 1607 adev->gfx.mec.num_pipe_per_mec = 4; 1608 adev->gfx.mec.num_queue_per_pipe = 8; 1609 1610 /* EOP Event */ 1611 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1612 if (r) 1613 return r; 1614 1615 /* Privileged reg */ 1616 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1617 &adev->gfx.priv_reg_irq); 1618 if (r) 1619 return r; 1620 1621 /* Privileged inst */ 1622 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1623 &adev->gfx.priv_inst_irq); 1624 if (r) 1625 return r; 1626 1627 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1628 1629 gfx_v9_0_scratch_init(adev); 1630 1631 r = gfx_v9_0_init_microcode(adev); 1632 if (r) { 1633 DRM_ERROR("Failed to load gfx firmware!\n"); 1634 return r; 1635 } 1636 1637 r = adev->gfx.rlc.funcs->init(adev); 1638 if (r) { 1639 DRM_ERROR("Failed to init rlc BOs!\n"); 1640 return r; 1641 } 1642 1643 r = gfx_v9_0_mec_init(adev); 1644 if (r) { 1645 DRM_ERROR("Failed to init MEC BOs!\n"); 1646 return r; 1647 } 1648 1649 /* set up the gfx ring */ 1650 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1651 ring = &adev->gfx.gfx_ring[i]; 1652 ring->ring_obj = NULL; 1653 if (!i) 1654 sprintf(ring->name, "gfx"); 1655 else 1656 sprintf(ring->name, "gfx_%d", i); 1657 ring->use_doorbell = true; 1658 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1659 r = amdgpu_ring_init(adev, ring, 1024, 1660 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1661 if (r) 1662 return r; 1663 } 1664 1665 /* set up the compute queues - allocate horizontally across pipes */ 1666 ring_id = 0; 1667 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1668 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1669 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1670 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 1671 continue; 1672 1673 r = gfx_v9_0_compute_ring_init(adev, 1674 ring_id, 1675 i, k, j); 1676 if (r) 1677 return r; 1678 1679 ring_id++; 1680 } 1681 } 1682 } 1683 1684 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 1685 if (r) { 1686 DRM_ERROR("Failed to init KIQ BOs!\n"); 1687 return r; 1688 } 1689 1690 kiq = &adev->gfx.kiq; 1691 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1692 if (r) 1693 return r; 1694 1695 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1696 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 1697 if (r) 1698 return r; 1699 1700 adev->gfx.ce_ram_size = 0x8000; 1701 1702 r = gfx_v9_0_gpu_early_init(adev); 1703 if (r) 1704 return r; 1705 1706 r = gfx_v9_0_ngg_init(adev); 1707 if (r) 1708 return r; 1709 1710 return 0; 1711 } 1712 1713 1714 static int gfx_v9_0_sw_fini(void *handle) 1715 { 1716 int i; 1717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1718 1719 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1720 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1721 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1722 1723 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1724 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1725 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1726 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1727 1728 amdgpu_gfx_compute_mqd_sw_fini(adev); 1729 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1730 amdgpu_gfx_kiq_fini(adev); 1731 1732 gfx_v9_0_mec_fini(adev); 1733 gfx_v9_0_ngg_fini(adev); 1734 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1735 &adev->gfx.rlc.clear_state_gpu_addr, 1736 (void **)&adev->gfx.rlc.cs_ptr); 1737 if (adev->asic_type == CHIP_RAVEN) { 1738 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1739 &adev->gfx.rlc.cp_table_gpu_addr, 1740 (void **)&adev->gfx.rlc.cp_table_ptr); 1741 } 1742 gfx_v9_0_free_microcode(adev); 1743 1744 return 0; 1745 } 1746 1747 1748 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1749 { 1750 /* TODO */ 1751 } 1752 1753 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1754 { 1755 u32 data; 1756 1757 if (instance == 0xffffffff) 1758 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1759 else 1760 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1761 1762 if (se_num == 0xffffffff) 1763 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1764 else 1765 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1766 1767 if (sh_num == 0xffffffff) 1768 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1769 else 1770 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1771 1772 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1773 } 1774 1775 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1776 { 1777 u32 data, mask; 1778 1779 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1780 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1781 1782 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1783 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1784 1785 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1786 adev->gfx.config.max_sh_per_se); 1787 1788 return (~data) & mask; 1789 } 1790 1791 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1792 { 1793 int i, j; 1794 u32 data; 1795 u32 active_rbs = 0; 1796 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1797 adev->gfx.config.max_sh_per_se; 1798 1799 mutex_lock(&adev->grbm_idx_mutex); 1800 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1801 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1802 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1803 data = gfx_v9_0_get_rb_active_bitmap(adev); 1804 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1805 rb_bitmap_width_per_sh); 1806 } 1807 } 1808 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1809 mutex_unlock(&adev->grbm_idx_mutex); 1810 1811 adev->gfx.config.backend_enable_mask = active_rbs; 1812 adev->gfx.config.num_rbs = hweight32(active_rbs); 1813 } 1814 1815 #define DEFAULT_SH_MEM_BASES (0x6000) 1816 #define FIRST_COMPUTE_VMID (8) 1817 #define LAST_COMPUTE_VMID (16) 1818 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1819 { 1820 int i; 1821 uint32_t sh_mem_config; 1822 uint32_t sh_mem_bases; 1823 1824 /* 1825 * Configure apertures: 1826 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1827 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1828 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1829 */ 1830 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1831 1832 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1833 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1834 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1835 1836 mutex_lock(&adev->srbm_mutex); 1837 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1838 soc15_grbm_select(adev, 0, 0, 0, i); 1839 /* CP and shaders */ 1840 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1841 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1842 } 1843 soc15_grbm_select(adev, 0, 0, 0, 0); 1844 mutex_unlock(&adev->srbm_mutex); 1845 } 1846 1847 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 1848 { 1849 u32 tmp; 1850 int i; 1851 1852 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1853 1854 gfx_v9_0_tiling_mode_table_init(adev); 1855 1856 gfx_v9_0_setup_rb(adev); 1857 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1858 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 1859 1860 /* XXX SH_MEM regs */ 1861 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1862 mutex_lock(&adev->srbm_mutex); 1863 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { 1864 soc15_grbm_select(adev, 0, 0, 0, i); 1865 /* CP and shaders */ 1866 if (i == 0) { 1867 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1868 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1869 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1870 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1871 } else { 1872 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1873 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1874 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1875 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1876 (adev->gmc.private_aperture_start >> 48)); 1877 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1878 (adev->gmc.shared_aperture_start >> 48)); 1879 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1880 } 1881 } 1882 soc15_grbm_select(adev, 0, 0, 0, 0); 1883 1884 mutex_unlock(&adev->srbm_mutex); 1885 1886 gfx_v9_0_init_compute_vmid(adev); 1887 1888 mutex_lock(&adev->grbm_idx_mutex); 1889 /* 1890 * making sure that the following register writes will be broadcasted 1891 * to all the shaders 1892 */ 1893 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1894 1895 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1896 (adev->gfx.config.sc_prim_fifo_size_frontend << 1897 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1898 (adev->gfx.config.sc_prim_fifo_size_backend << 1899 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1900 (adev->gfx.config.sc_hiz_tile_fifo_size << 1901 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1902 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1903 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1904 mutex_unlock(&adev->grbm_idx_mutex); 1905 1906 } 1907 1908 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1909 { 1910 u32 i, j, k; 1911 u32 mask; 1912 1913 mutex_lock(&adev->grbm_idx_mutex); 1914 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1915 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1916 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1917 for (k = 0; k < adev->usec_timeout; k++) { 1918 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1919 break; 1920 udelay(1); 1921 } 1922 if (k == adev->usec_timeout) { 1923 gfx_v9_0_select_se_sh(adev, 0xffffffff, 1924 0xffffffff, 0xffffffff); 1925 mutex_unlock(&adev->grbm_idx_mutex); 1926 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1927 i, j); 1928 return; 1929 } 1930 } 1931 } 1932 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1933 mutex_unlock(&adev->grbm_idx_mutex); 1934 1935 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1936 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1937 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1938 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1939 for (k = 0; k < adev->usec_timeout; k++) { 1940 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1941 break; 1942 udelay(1); 1943 } 1944 } 1945 1946 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1947 bool enable) 1948 { 1949 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1950 1951 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1952 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1953 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1954 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1955 1956 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1957 } 1958 1959 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 1960 { 1961 /* csib */ 1962 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 1963 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1964 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 1965 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1966 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 1967 adev->gfx.rlc.clear_state_size); 1968 } 1969 1970 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 1971 int indirect_offset, 1972 int list_size, 1973 int *unique_indirect_regs, 1974 int unique_indirect_reg_count, 1975 int *indirect_start_offsets, 1976 int *indirect_start_offsets_count, 1977 int max_start_offsets_count) 1978 { 1979 int idx; 1980 1981 for (; indirect_offset < list_size; indirect_offset++) { 1982 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 1983 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 1984 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 1985 1986 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 1987 indirect_offset += 2; 1988 1989 /* look for the matching indice */ 1990 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 1991 if (unique_indirect_regs[idx] == 1992 register_list_format[indirect_offset] || 1993 !unique_indirect_regs[idx]) 1994 break; 1995 } 1996 1997 BUG_ON(idx >= unique_indirect_reg_count); 1998 1999 if (!unique_indirect_regs[idx]) 2000 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2001 2002 indirect_offset++; 2003 } 2004 } 2005 } 2006 2007 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2008 { 2009 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2010 int unique_indirect_reg_count = 0; 2011 2012 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2013 int indirect_start_offsets_count = 0; 2014 2015 int list_size = 0; 2016 int i = 0, j = 0; 2017 u32 tmp = 0; 2018 2019 u32 *register_list_format = 2020 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2021 if (!register_list_format) 2022 return -ENOMEM; 2023 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 2024 adev->gfx.rlc.reg_list_format_size_bytes); 2025 2026 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2027 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2028 gfx_v9_1_parse_ind_reg_list(register_list_format, 2029 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2030 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2031 unique_indirect_regs, 2032 unique_indirect_reg_count, 2033 indirect_start_offsets, 2034 &indirect_start_offsets_count, 2035 ARRAY_SIZE(indirect_start_offsets)); 2036 2037 /* enable auto inc in case it is disabled */ 2038 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2039 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2040 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2041 2042 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2043 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2044 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2045 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2046 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2047 adev->gfx.rlc.register_restore[i]); 2048 2049 /* load indirect register */ 2050 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2051 adev->gfx.rlc.reg_list_format_start); 2052 2053 /* direct register portion */ 2054 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2055 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2056 register_list_format[i]); 2057 2058 /* indirect register portion */ 2059 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2060 if (register_list_format[i] == 0xFFFFFFFF) { 2061 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2062 continue; 2063 } 2064 2065 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2066 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2067 2068 for (j = 0; j < unique_indirect_reg_count; j++) { 2069 if (register_list_format[i] == unique_indirect_regs[j]) { 2070 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2071 break; 2072 } 2073 } 2074 2075 BUG_ON(j >= unique_indirect_reg_count); 2076 2077 i++; 2078 } 2079 2080 /* set save/restore list size */ 2081 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2082 list_size = list_size >> 1; 2083 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2084 adev->gfx.rlc.reg_restore_list_size); 2085 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2086 2087 /* write the starting offsets to RLC scratch ram */ 2088 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2089 adev->gfx.rlc.starting_offsets_start); 2090 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2091 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2092 indirect_start_offsets[i]); 2093 2094 /* load unique indirect regs*/ 2095 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2096 if (unique_indirect_regs[i] != 0) { 2097 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2098 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2099 unique_indirect_regs[i] & 0x3FFFF); 2100 2101 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2102 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2103 unique_indirect_regs[i] >> 20); 2104 } 2105 } 2106 2107 kfree(register_list_format); 2108 return 0; 2109 } 2110 2111 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2112 { 2113 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2114 } 2115 2116 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2117 bool enable) 2118 { 2119 uint32_t data = 0; 2120 uint32_t default_data = 0; 2121 2122 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2123 if (enable == true) { 2124 /* enable GFXIP control over CGPG */ 2125 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2126 if(default_data != data) 2127 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2128 2129 /* update status */ 2130 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2131 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2132 if(default_data != data) 2133 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2134 } else { 2135 /* restore GFXIP control over GCPG */ 2136 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2137 if(default_data != data) 2138 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2139 } 2140 } 2141 2142 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2143 { 2144 uint32_t data = 0; 2145 2146 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2147 AMD_PG_SUPPORT_GFX_SMG | 2148 AMD_PG_SUPPORT_GFX_DMG)) { 2149 /* init IDLE_POLL_COUNT = 60 */ 2150 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2151 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2152 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2153 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2154 2155 /* init RLC PG Delay */ 2156 data = 0; 2157 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2158 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2159 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2160 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2161 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2162 2163 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2164 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2165 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2166 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2167 2168 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2169 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2170 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2171 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2172 2173 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2174 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2175 2176 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2177 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2178 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2179 2180 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2181 } 2182 } 2183 2184 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2185 bool enable) 2186 { 2187 uint32_t data = 0; 2188 uint32_t default_data = 0; 2189 2190 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2191 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2192 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2193 enable ? 1 : 0); 2194 if (default_data != data) 2195 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2196 } 2197 2198 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2199 bool enable) 2200 { 2201 uint32_t data = 0; 2202 uint32_t default_data = 0; 2203 2204 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2205 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2206 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2207 enable ? 1 : 0); 2208 if(default_data != data) 2209 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2210 } 2211 2212 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2213 bool enable) 2214 { 2215 uint32_t data = 0; 2216 uint32_t default_data = 0; 2217 2218 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2219 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2220 CP_PG_DISABLE, 2221 enable ? 0 : 1); 2222 if(default_data != data) 2223 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2224 } 2225 2226 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2227 bool enable) 2228 { 2229 uint32_t data, default_data; 2230 2231 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2232 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2233 GFX_POWER_GATING_ENABLE, 2234 enable ? 1 : 0); 2235 if(default_data != data) 2236 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2237 } 2238 2239 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2240 bool enable) 2241 { 2242 uint32_t data, default_data; 2243 2244 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2245 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2246 GFX_PIPELINE_PG_ENABLE, 2247 enable ? 1 : 0); 2248 if(default_data != data) 2249 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2250 2251 if (!enable) 2252 /* read any GFX register to wake up GFX */ 2253 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2254 } 2255 2256 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2257 bool enable) 2258 { 2259 uint32_t data, default_data; 2260 2261 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2262 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2263 STATIC_PER_CU_PG_ENABLE, 2264 enable ? 1 : 0); 2265 if(default_data != data) 2266 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2267 } 2268 2269 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2270 bool enable) 2271 { 2272 uint32_t data, default_data; 2273 2274 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2275 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2276 DYN_PER_CU_PG_ENABLE, 2277 enable ? 1 : 0); 2278 if(default_data != data) 2279 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2280 } 2281 2282 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2283 { 2284 gfx_v9_0_init_csb(adev); 2285 2286 /* 2287 * Rlc save restore list is workable since v2_1. 2288 * And it's needed by gfxoff feature. 2289 */ 2290 if (adev->gfx.rlc.is_rlc_v2_1) { 2291 gfx_v9_1_init_rlc_save_restore_list(adev); 2292 gfx_v9_0_enable_save_restore_machine(adev); 2293 } 2294 2295 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2296 AMD_PG_SUPPORT_GFX_SMG | 2297 AMD_PG_SUPPORT_GFX_DMG | 2298 AMD_PG_SUPPORT_CP | 2299 AMD_PG_SUPPORT_GDS | 2300 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2301 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2302 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2303 gfx_v9_0_init_gfx_power_gating(adev); 2304 } 2305 } 2306 2307 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2308 { 2309 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2310 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2311 gfx_v9_0_wait_for_rlc_serdes(adev); 2312 } 2313 2314 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2315 { 2316 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2317 udelay(50); 2318 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2319 udelay(50); 2320 } 2321 2322 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2323 { 2324 #ifdef AMDGPU_RLC_DEBUG_RETRY 2325 u32 rlc_ucode_ver; 2326 #endif 2327 2328 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2329 2330 /* carrizo do enable cp interrupt after cp inited */ 2331 if (!(adev->flags & AMD_IS_APU)) 2332 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2333 2334 udelay(50); 2335 2336 #ifdef AMDGPU_RLC_DEBUG_RETRY 2337 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2338 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2339 if(rlc_ucode_ver == 0x108) { 2340 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2341 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2342 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2343 * default is 0x9C4 to create a 100us interval */ 2344 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2345 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2346 * to disable the page fault retry interrupts, default is 2347 * 0x100 (256) */ 2348 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2349 } 2350 #endif 2351 } 2352 2353 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2354 { 2355 const struct rlc_firmware_header_v2_0 *hdr; 2356 const __le32 *fw_data; 2357 unsigned i, fw_size; 2358 2359 if (!adev->gfx.rlc_fw) 2360 return -EINVAL; 2361 2362 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2363 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2364 2365 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2366 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2367 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2368 2369 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2370 RLCG_UCODE_LOADING_START_ADDRESS); 2371 for (i = 0; i < fw_size; i++) 2372 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2373 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2374 2375 return 0; 2376 } 2377 2378 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2379 { 2380 int r; 2381 2382 if (amdgpu_sriov_vf(adev)) { 2383 gfx_v9_0_init_csb(adev); 2384 return 0; 2385 } 2386 2387 adev->gfx.rlc.funcs->stop(adev); 2388 2389 /* disable CG */ 2390 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2391 2392 adev->gfx.rlc.funcs->reset(adev); 2393 2394 gfx_v9_0_init_pg(adev); 2395 2396 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2397 /* legacy rlc firmware loading */ 2398 r = gfx_v9_0_rlc_load_microcode(adev); 2399 if (r) 2400 return r; 2401 } 2402 2403 switch (adev->asic_type) { 2404 case CHIP_RAVEN: 2405 if (amdgpu_lbpw == 0) 2406 gfx_v9_0_enable_lbpw(adev, false); 2407 else 2408 gfx_v9_0_enable_lbpw(adev, true); 2409 break; 2410 case CHIP_VEGA20: 2411 if (amdgpu_lbpw > 0) 2412 gfx_v9_0_enable_lbpw(adev, true); 2413 else 2414 gfx_v9_0_enable_lbpw(adev, false); 2415 break; 2416 default: 2417 break; 2418 } 2419 2420 adev->gfx.rlc.funcs->start(adev); 2421 2422 return 0; 2423 } 2424 2425 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2426 { 2427 int i; 2428 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2429 2430 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2431 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2432 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2433 if (!enable) { 2434 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2435 adev->gfx.gfx_ring[i].sched.ready = false; 2436 } 2437 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2438 udelay(50); 2439 } 2440 2441 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2442 { 2443 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2444 const struct gfx_firmware_header_v1_0 *ce_hdr; 2445 const struct gfx_firmware_header_v1_0 *me_hdr; 2446 const __le32 *fw_data; 2447 unsigned i, fw_size; 2448 2449 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2450 return -EINVAL; 2451 2452 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2453 adev->gfx.pfp_fw->data; 2454 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2455 adev->gfx.ce_fw->data; 2456 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2457 adev->gfx.me_fw->data; 2458 2459 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2460 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2461 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2462 2463 gfx_v9_0_cp_gfx_enable(adev, false); 2464 2465 /* PFP */ 2466 fw_data = (const __le32 *) 2467 (adev->gfx.pfp_fw->data + 2468 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2469 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2470 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2471 for (i = 0; i < fw_size; i++) 2472 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2473 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2474 2475 /* CE */ 2476 fw_data = (const __le32 *) 2477 (adev->gfx.ce_fw->data + 2478 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2479 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2480 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2481 for (i = 0; i < fw_size; i++) 2482 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2483 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2484 2485 /* ME */ 2486 fw_data = (const __le32 *) 2487 (adev->gfx.me_fw->data + 2488 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2489 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2490 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2491 for (i = 0; i < fw_size; i++) 2492 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2493 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2494 2495 return 0; 2496 } 2497 2498 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2499 { 2500 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2501 const struct cs_section_def *sect = NULL; 2502 const struct cs_extent_def *ext = NULL; 2503 int r, i, tmp; 2504 2505 /* init the CP */ 2506 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2507 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2508 2509 gfx_v9_0_cp_gfx_enable(adev, true); 2510 2511 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 2512 if (r) { 2513 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2514 return r; 2515 } 2516 2517 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2518 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2519 2520 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2521 amdgpu_ring_write(ring, 0x80000000); 2522 amdgpu_ring_write(ring, 0x80000000); 2523 2524 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2525 for (ext = sect->section; ext->extent != NULL; ++ext) { 2526 if (sect->id == SECT_CONTEXT) { 2527 amdgpu_ring_write(ring, 2528 PACKET3(PACKET3_SET_CONTEXT_REG, 2529 ext->reg_count)); 2530 amdgpu_ring_write(ring, 2531 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2532 for (i = 0; i < ext->reg_count; i++) 2533 amdgpu_ring_write(ring, ext->extent[i]); 2534 } 2535 } 2536 } 2537 2538 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2539 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2540 2541 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2542 amdgpu_ring_write(ring, 0); 2543 2544 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2545 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2546 amdgpu_ring_write(ring, 0x8000); 2547 amdgpu_ring_write(ring, 0x8000); 2548 2549 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 2550 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 2551 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 2552 amdgpu_ring_write(ring, tmp); 2553 amdgpu_ring_write(ring, 0); 2554 2555 amdgpu_ring_commit(ring); 2556 2557 return 0; 2558 } 2559 2560 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2561 { 2562 struct amdgpu_ring *ring; 2563 u32 tmp; 2564 u32 rb_bufsz; 2565 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2566 2567 /* Set the write pointer delay */ 2568 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2569 2570 /* set the RB to use vmid 0 */ 2571 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2572 2573 /* Set ring buffer size */ 2574 ring = &adev->gfx.gfx_ring[0]; 2575 rb_bufsz = order_base_2(ring->ring_size / 8); 2576 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2577 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2578 #ifdef __BIG_ENDIAN 2579 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2580 #endif 2581 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2582 2583 /* Initialize the ring buffer's write pointers */ 2584 ring->wptr = 0; 2585 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2586 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2587 2588 /* set the wb address wether it's enabled or not */ 2589 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2590 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2591 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2592 2593 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2594 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2595 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2596 2597 mdelay(1); 2598 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2599 2600 rb_addr = ring->gpu_addr >> 8; 2601 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2602 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2603 2604 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2605 if (ring->use_doorbell) { 2606 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2607 DOORBELL_OFFSET, ring->doorbell_index); 2608 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2609 DOORBELL_EN, 1); 2610 } else { 2611 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2612 } 2613 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2614 2615 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2616 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2617 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2618 2619 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2620 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2621 2622 2623 /* start the ring */ 2624 gfx_v9_0_cp_gfx_start(adev); 2625 ring->sched.ready = true; 2626 2627 return 0; 2628 } 2629 2630 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2631 { 2632 int i; 2633 2634 if (enable) { 2635 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2636 } else { 2637 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2638 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2639 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2640 adev->gfx.compute_ring[i].sched.ready = false; 2641 adev->gfx.kiq.ring.sched.ready = false; 2642 } 2643 udelay(50); 2644 } 2645 2646 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2647 { 2648 const struct gfx_firmware_header_v1_0 *mec_hdr; 2649 const __le32 *fw_data; 2650 unsigned i; 2651 u32 tmp; 2652 2653 if (!adev->gfx.mec_fw) 2654 return -EINVAL; 2655 2656 gfx_v9_0_cp_compute_enable(adev, false); 2657 2658 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2659 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2660 2661 fw_data = (const __le32 *) 2662 (adev->gfx.mec_fw->data + 2663 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2664 tmp = 0; 2665 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2666 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2667 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2668 2669 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2670 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2671 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2672 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2673 2674 /* MEC1 */ 2675 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2676 mec_hdr->jt_offset); 2677 for (i = 0; i < mec_hdr->jt_size; i++) 2678 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2679 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2680 2681 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2682 adev->gfx.mec_fw_version); 2683 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2684 2685 return 0; 2686 } 2687 2688 /* KIQ functions */ 2689 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2690 { 2691 uint32_t tmp; 2692 struct amdgpu_device *adev = ring->adev; 2693 2694 /* tell RLC which is KIQ queue */ 2695 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2696 tmp &= 0xffffff00; 2697 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2698 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2699 tmp |= 0x80; 2700 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2701 } 2702 2703 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) 2704 { 2705 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 2706 uint64_t queue_mask = 0; 2707 int r, i; 2708 2709 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 2710 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 2711 continue; 2712 2713 /* This situation may be hit in the future if a new HW 2714 * generation exposes more than 64 queues. If so, the 2715 * definition of queue_mask needs updating */ 2716 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 2717 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 2718 break; 2719 } 2720 2721 queue_mask |= (1ull << i); 2722 } 2723 2724 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); 2725 if (r) { 2726 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2727 return r; 2728 } 2729 2730 /* set resources */ 2731 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2732 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2733 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2734 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 2735 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 2736 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 2737 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 2738 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 2739 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 2740 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2741 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2742 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2743 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2744 2745 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2746 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2747 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2748 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2749 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2750 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2751 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2752 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2753 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2754 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 2755 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2756 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2757 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2758 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2759 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2760 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2761 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2762 } 2763 2764 r = amdgpu_ring_test_helper(kiq_ring); 2765 if (r) 2766 DRM_ERROR("KCQ enable failed\n"); 2767 2768 return r; 2769 } 2770 2771 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2772 { 2773 struct amdgpu_device *adev = ring->adev; 2774 struct v9_mqd *mqd = ring->mqd_ptr; 2775 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2776 uint32_t tmp; 2777 2778 mqd->header = 0xC0310800; 2779 mqd->compute_pipelinestat_enable = 0x00000001; 2780 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2781 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2782 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2783 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2784 mqd->compute_misc_reserved = 0x00000003; 2785 2786 mqd->dynamic_cu_mask_addr_lo = 2787 lower_32_bits(ring->mqd_gpu_addr 2788 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2789 mqd->dynamic_cu_mask_addr_hi = 2790 upper_32_bits(ring->mqd_gpu_addr 2791 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2792 2793 eop_base_addr = ring->eop_gpu_addr >> 8; 2794 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2795 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2796 2797 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2798 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2799 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2800 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2801 2802 mqd->cp_hqd_eop_control = tmp; 2803 2804 /* enable doorbell? */ 2805 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2806 2807 if (ring->use_doorbell) { 2808 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2809 DOORBELL_OFFSET, ring->doorbell_index); 2810 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2811 DOORBELL_EN, 1); 2812 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2813 DOORBELL_SOURCE, 0); 2814 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2815 DOORBELL_HIT, 0); 2816 } else { 2817 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2818 DOORBELL_EN, 0); 2819 } 2820 2821 mqd->cp_hqd_pq_doorbell_control = tmp; 2822 2823 /* disable the queue if it's active */ 2824 ring->wptr = 0; 2825 mqd->cp_hqd_dequeue_request = 0; 2826 mqd->cp_hqd_pq_rptr = 0; 2827 mqd->cp_hqd_pq_wptr_lo = 0; 2828 mqd->cp_hqd_pq_wptr_hi = 0; 2829 2830 /* set the pointer to the MQD */ 2831 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2832 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2833 2834 /* set MQD vmid to 0 */ 2835 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2836 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2837 mqd->cp_mqd_control = tmp; 2838 2839 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2840 hqd_gpu_addr = ring->gpu_addr >> 8; 2841 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2842 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2843 2844 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2845 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2846 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2847 (order_base_2(ring->ring_size / 4) - 1)); 2848 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2849 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2850 #ifdef __BIG_ENDIAN 2851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2852 #endif 2853 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2854 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2857 mqd->cp_hqd_pq_control = tmp; 2858 2859 /* set the wb address whether it's enabled or not */ 2860 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2861 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2862 mqd->cp_hqd_pq_rptr_report_addr_hi = 2863 upper_32_bits(wb_gpu_addr) & 0xffff; 2864 2865 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2866 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2867 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2868 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2869 2870 tmp = 0; 2871 /* enable the doorbell if requested */ 2872 if (ring->use_doorbell) { 2873 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2875 DOORBELL_OFFSET, ring->doorbell_index); 2876 2877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2878 DOORBELL_EN, 1); 2879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2880 DOORBELL_SOURCE, 0); 2881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2882 DOORBELL_HIT, 0); 2883 } 2884 2885 mqd->cp_hqd_pq_doorbell_control = tmp; 2886 2887 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2888 ring->wptr = 0; 2889 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2890 2891 /* set the vmid for the queue */ 2892 mqd->cp_hqd_vmid = 0; 2893 2894 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2895 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2896 mqd->cp_hqd_persistent_state = tmp; 2897 2898 /* set MIN_IB_AVAIL_SIZE */ 2899 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2900 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2901 mqd->cp_hqd_ib_control = tmp; 2902 2903 /* activate the queue */ 2904 mqd->cp_hqd_active = 1; 2905 2906 return 0; 2907 } 2908 2909 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2910 { 2911 struct amdgpu_device *adev = ring->adev; 2912 struct v9_mqd *mqd = ring->mqd_ptr; 2913 int j; 2914 2915 /* disable wptr polling */ 2916 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2917 2918 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2919 mqd->cp_hqd_eop_base_addr_lo); 2920 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2921 mqd->cp_hqd_eop_base_addr_hi); 2922 2923 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2924 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2925 mqd->cp_hqd_eop_control); 2926 2927 /* enable doorbell? */ 2928 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2929 mqd->cp_hqd_pq_doorbell_control); 2930 2931 /* disable the queue if it's active */ 2932 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2933 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2934 for (j = 0; j < adev->usec_timeout; j++) { 2935 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2936 break; 2937 udelay(1); 2938 } 2939 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2940 mqd->cp_hqd_dequeue_request); 2941 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 2942 mqd->cp_hqd_pq_rptr); 2943 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2944 mqd->cp_hqd_pq_wptr_lo); 2945 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2946 mqd->cp_hqd_pq_wptr_hi); 2947 } 2948 2949 /* set the pointer to the MQD */ 2950 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 2951 mqd->cp_mqd_base_addr_lo); 2952 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 2953 mqd->cp_mqd_base_addr_hi); 2954 2955 /* set MQD vmid to 0 */ 2956 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 2957 mqd->cp_mqd_control); 2958 2959 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2960 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 2961 mqd->cp_hqd_pq_base_lo); 2962 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 2963 mqd->cp_hqd_pq_base_hi); 2964 2965 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2966 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 2967 mqd->cp_hqd_pq_control); 2968 2969 /* set the wb address whether it's enabled or not */ 2970 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2971 mqd->cp_hqd_pq_rptr_report_addr_lo); 2972 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2973 mqd->cp_hqd_pq_rptr_report_addr_hi); 2974 2975 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2976 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 2977 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2978 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2979 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2980 2981 /* enable the doorbell if requested */ 2982 if (ring->use_doorbell) { 2983 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 2984 (adev->doorbell_index.kiq * 2) << 2); 2985 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 2986 (adev->doorbell_index.userqueue_end * 2) << 2); 2987 } 2988 2989 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2990 mqd->cp_hqd_pq_doorbell_control); 2991 2992 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2993 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2994 mqd->cp_hqd_pq_wptr_lo); 2995 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2996 mqd->cp_hqd_pq_wptr_hi); 2997 2998 /* set the vmid for the queue */ 2999 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3000 3001 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3002 mqd->cp_hqd_persistent_state); 3003 3004 /* activate the queue */ 3005 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3006 mqd->cp_hqd_active); 3007 3008 if (ring->use_doorbell) 3009 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3010 3011 return 0; 3012 } 3013 3014 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3015 { 3016 struct amdgpu_device *adev = ring->adev; 3017 int j; 3018 3019 /* disable the queue if it's active */ 3020 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3021 3022 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3023 3024 for (j = 0; j < adev->usec_timeout; j++) { 3025 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3026 break; 3027 udelay(1); 3028 } 3029 3030 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3031 DRM_DEBUG("KIQ dequeue request failed.\n"); 3032 3033 /* Manual disable if dequeue request times out */ 3034 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 3035 } 3036 3037 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3038 0); 3039 } 3040 3041 WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3042 WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3043 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3044 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3045 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3046 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3047 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3048 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3049 3050 return 0; 3051 } 3052 3053 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3054 { 3055 struct amdgpu_device *adev = ring->adev; 3056 struct v9_mqd *mqd = ring->mqd_ptr; 3057 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3058 3059 gfx_v9_0_kiq_setting(ring); 3060 3061 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3062 /* reset MQD to a clean status */ 3063 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3064 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3065 3066 /* reset ring buffer */ 3067 ring->wptr = 0; 3068 amdgpu_ring_clear_ring(ring); 3069 3070 mutex_lock(&adev->srbm_mutex); 3071 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3072 gfx_v9_0_kiq_init_register(ring); 3073 soc15_grbm_select(adev, 0, 0, 0, 0); 3074 mutex_unlock(&adev->srbm_mutex); 3075 } else { 3076 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3077 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3078 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3079 mutex_lock(&adev->srbm_mutex); 3080 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3081 gfx_v9_0_mqd_init(ring); 3082 gfx_v9_0_kiq_init_register(ring); 3083 soc15_grbm_select(adev, 0, 0, 0, 0); 3084 mutex_unlock(&adev->srbm_mutex); 3085 3086 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3087 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3088 } 3089 3090 return 0; 3091 } 3092 3093 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3094 { 3095 struct amdgpu_device *adev = ring->adev; 3096 struct v9_mqd *mqd = ring->mqd_ptr; 3097 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3098 3099 if (!adev->in_gpu_reset && !adev->in_suspend) { 3100 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3101 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3102 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3103 mutex_lock(&adev->srbm_mutex); 3104 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3105 gfx_v9_0_mqd_init(ring); 3106 soc15_grbm_select(adev, 0, 0, 0, 0); 3107 mutex_unlock(&adev->srbm_mutex); 3108 3109 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3110 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3111 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3112 /* reset MQD to a clean status */ 3113 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3114 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3115 3116 /* reset ring buffer */ 3117 ring->wptr = 0; 3118 amdgpu_ring_clear_ring(ring); 3119 } else { 3120 amdgpu_ring_clear_ring(ring); 3121 } 3122 3123 return 0; 3124 } 3125 3126 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3127 { 3128 struct amdgpu_ring *ring; 3129 int r; 3130 3131 ring = &adev->gfx.kiq.ring; 3132 3133 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3134 if (unlikely(r != 0)) 3135 return r; 3136 3137 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3138 if (unlikely(r != 0)) 3139 return r; 3140 3141 gfx_v9_0_kiq_init_queue(ring); 3142 amdgpu_bo_kunmap(ring->mqd_obj); 3143 ring->mqd_ptr = NULL; 3144 amdgpu_bo_unreserve(ring->mqd_obj); 3145 ring->sched.ready = true; 3146 return 0; 3147 } 3148 3149 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3150 { 3151 struct amdgpu_ring *ring = NULL; 3152 int r = 0, i; 3153 3154 gfx_v9_0_cp_compute_enable(adev, true); 3155 3156 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3157 ring = &adev->gfx.compute_ring[i]; 3158 3159 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3160 if (unlikely(r != 0)) 3161 goto done; 3162 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3163 if (!r) { 3164 r = gfx_v9_0_kcq_init_queue(ring); 3165 amdgpu_bo_kunmap(ring->mqd_obj); 3166 ring->mqd_ptr = NULL; 3167 } 3168 amdgpu_bo_unreserve(ring->mqd_obj); 3169 if (r) 3170 goto done; 3171 } 3172 3173 r = gfx_v9_0_kiq_kcq_enable(adev); 3174 done: 3175 return r; 3176 } 3177 3178 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3179 { 3180 int r, i; 3181 struct amdgpu_ring *ring; 3182 3183 if (!(adev->flags & AMD_IS_APU)) 3184 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3185 3186 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3187 /* legacy firmware loading */ 3188 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3189 if (r) 3190 return r; 3191 3192 r = gfx_v9_0_cp_compute_load_microcode(adev); 3193 if (r) 3194 return r; 3195 } 3196 3197 r = gfx_v9_0_kiq_resume(adev); 3198 if (r) 3199 return r; 3200 3201 r = gfx_v9_0_cp_gfx_resume(adev); 3202 if (r) 3203 return r; 3204 3205 r = gfx_v9_0_kcq_resume(adev); 3206 if (r) 3207 return r; 3208 3209 ring = &adev->gfx.gfx_ring[0]; 3210 r = amdgpu_ring_test_helper(ring); 3211 if (r) 3212 return r; 3213 3214 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3215 ring = &adev->gfx.compute_ring[i]; 3216 amdgpu_ring_test_helper(ring); 3217 } 3218 3219 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3220 3221 return 0; 3222 } 3223 3224 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3225 { 3226 gfx_v9_0_cp_gfx_enable(adev, enable); 3227 gfx_v9_0_cp_compute_enable(adev, enable); 3228 } 3229 3230 static int gfx_v9_0_hw_init(void *handle) 3231 { 3232 int r; 3233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3234 3235 gfx_v9_0_init_golden_registers(adev); 3236 3237 gfx_v9_0_constants_init(adev); 3238 3239 r = gfx_v9_0_csb_vram_pin(adev); 3240 if (r) 3241 return r; 3242 3243 r = adev->gfx.rlc.funcs->resume(adev); 3244 if (r) 3245 return r; 3246 3247 r = gfx_v9_0_cp_resume(adev); 3248 if (r) 3249 return r; 3250 3251 r = gfx_v9_0_ngg_en(adev); 3252 if (r) 3253 return r; 3254 3255 return r; 3256 } 3257 3258 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev) 3259 { 3260 int r, i; 3261 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3262 3263 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); 3264 if (r) 3265 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3266 3267 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3268 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3269 3270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3271 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3272 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 3273 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3274 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 3275 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3276 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3277 amdgpu_ring_write(kiq_ring, 0); 3278 amdgpu_ring_write(kiq_ring, 0); 3279 amdgpu_ring_write(kiq_ring, 0); 3280 } 3281 r = amdgpu_ring_test_helper(kiq_ring); 3282 if (r) 3283 DRM_ERROR("KCQ disable failed\n"); 3284 3285 return r; 3286 } 3287 3288 static int gfx_v9_0_hw_fini(void *handle) 3289 { 3290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3291 3292 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3293 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3294 3295 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3296 gfx_v9_0_kcq_disable(adev); 3297 3298 if (amdgpu_sriov_vf(adev)) { 3299 gfx_v9_0_cp_gfx_enable(adev, false); 3300 /* must disable polling for SRIOV when hw finished, otherwise 3301 * CPC engine may still keep fetching WB address which is already 3302 * invalid after sw finished and trigger DMAR reading error in 3303 * hypervisor side. 3304 */ 3305 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3306 return 0; 3307 } 3308 3309 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3310 * otherwise KIQ is hanging when binding back 3311 */ 3312 if (!adev->in_gpu_reset && !adev->in_suspend) { 3313 mutex_lock(&adev->srbm_mutex); 3314 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3315 adev->gfx.kiq.ring.pipe, 3316 adev->gfx.kiq.ring.queue, 0); 3317 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3318 soc15_grbm_select(adev, 0, 0, 0, 0); 3319 mutex_unlock(&adev->srbm_mutex); 3320 } 3321 3322 gfx_v9_0_cp_enable(adev, false); 3323 adev->gfx.rlc.funcs->stop(adev); 3324 3325 gfx_v9_0_csb_vram_unpin(adev); 3326 3327 return 0; 3328 } 3329 3330 static int gfx_v9_0_suspend(void *handle) 3331 { 3332 return gfx_v9_0_hw_fini(handle); 3333 } 3334 3335 static int gfx_v9_0_resume(void *handle) 3336 { 3337 return gfx_v9_0_hw_init(handle); 3338 } 3339 3340 static bool gfx_v9_0_is_idle(void *handle) 3341 { 3342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3343 3344 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3345 GRBM_STATUS, GUI_ACTIVE)) 3346 return false; 3347 else 3348 return true; 3349 } 3350 3351 static int gfx_v9_0_wait_for_idle(void *handle) 3352 { 3353 unsigned i; 3354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3355 3356 for (i = 0; i < adev->usec_timeout; i++) { 3357 if (gfx_v9_0_is_idle(handle)) 3358 return 0; 3359 udelay(1); 3360 } 3361 return -ETIMEDOUT; 3362 } 3363 3364 static int gfx_v9_0_soft_reset(void *handle) 3365 { 3366 u32 grbm_soft_reset = 0; 3367 u32 tmp; 3368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3369 3370 /* GRBM_STATUS */ 3371 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3372 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3373 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3374 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3375 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3376 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3377 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3378 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3379 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3380 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3381 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3382 } 3383 3384 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3385 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3386 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3387 } 3388 3389 /* GRBM_STATUS2 */ 3390 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3391 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3392 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3393 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3394 3395 3396 if (grbm_soft_reset) { 3397 /* stop the rlc */ 3398 adev->gfx.rlc.funcs->stop(adev); 3399 3400 /* Disable GFX parsing/prefetching */ 3401 gfx_v9_0_cp_gfx_enable(adev, false); 3402 3403 /* Disable MEC parsing/prefetching */ 3404 gfx_v9_0_cp_compute_enable(adev, false); 3405 3406 if (grbm_soft_reset) { 3407 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3408 tmp |= grbm_soft_reset; 3409 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3410 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3411 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3412 3413 udelay(50); 3414 3415 tmp &= ~grbm_soft_reset; 3416 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3417 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3418 } 3419 3420 /* Wait a little for things to settle down */ 3421 udelay(50); 3422 } 3423 return 0; 3424 } 3425 3426 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3427 { 3428 uint64_t clock; 3429 3430 mutex_lock(&adev->gfx.gpu_clock_mutex); 3431 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3432 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3433 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3434 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3435 return clock; 3436 } 3437 3438 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3439 uint32_t vmid, 3440 uint32_t gds_base, uint32_t gds_size, 3441 uint32_t gws_base, uint32_t gws_size, 3442 uint32_t oa_base, uint32_t oa_size) 3443 { 3444 struct amdgpu_device *adev = ring->adev; 3445 3446 /* GDS Base */ 3447 gfx_v9_0_write_data_to_reg(ring, 0, false, 3448 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3449 gds_base); 3450 3451 /* GDS Size */ 3452 gfx_v9_0_write_data_to_reg(ring, 0, false, 3453 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3454 gds_size); 3455 3456 /* GWS */ 3457 gfx_v9_0_write_data_to_reg(ring, 0, false, 3458 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3459 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3460 3461 /* OA */ 3462 gfx_v9_0_write_data_to_reg(ring, 0, false, 3463 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3464 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3465 } 3466 3467 static int gfx_v9_0_early_init(void *handle) 3468 { 3469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3470 3471 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3472 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3473 gfx_v9_0_set_ring_funcs(adev); 3474 gfx_v9_0_set_irq_funcs(adev); 3475 gfx_v9_0_set_gds_init(adev); 3476 gfx_v9_0_set_rlc_funcs(adev); 3477 3478 return 0; 3479 } 3480 3481 static int gfx_v9_0_late_init(void *handle) 3482 { 3483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3484 int r; 3485 3486 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3487 if (r) 3488 return r; 3489 3490 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3491 if (r) 3492 return r; 3493 3494 return 0; 3495 } 3496 3497 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 3498 { 3499 uint32_t rlc_setting; 3500 3501 /* if RLC is not enabled, do nothing */ 3502 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3503 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3504 return false; 3505 3506 return true; 3507 } 3508 3509 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 3510 { 3511 uint32_t data; 3512 unsigned i; 3513 3514 data = RLC_SAFE_MODE__CMD_MASK; 3515 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3516 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3517 3518 /* wait for RLC_SAFE_MODE */ 3519 for (i = 0; i < adev->usec_timeout; i++) { 3520 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3521 break; 3522 udelay(1); 3523 } 3524 } 3525 3526 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 3527 { 3528 uint32_t data; 3529 3530 data = RLC_SAFE_MODE__CMD_MASK; 3531 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3532 } 3533 3534 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3535 bool enable) 3536 { 3537 amdgpu_gfx_rlc_enter_safe_mode(adev); 3538 3539 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3540 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3541 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3542 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3543 } else { 3544 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3545 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3546 } 3547 3548 amdgpu_gfx_rlc_exit_safe_mode(adev); 3549 } 3550 3551 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3552 bool enable) 3553 { 3554 /* TODO: double check if we need to perform under safe mode */ 3555 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3556 3557 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3558 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3559 else 3560 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3561 3562 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3563 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3564 else 3565 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3566 3567 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3568 } 3569 3570 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3571 bool enable) 3572 { 3573 uint32_t data, def; 3574 3575 /* It is disabled by HW by default */ 3576 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3577 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3578 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3579 3580 if (adev->asic_type != CHIP_VEGA12) 3581 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3582 3583 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3584 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3585 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3586 3587 /* only for Vega10 & Raven1 */ 3588 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3589 3590 if (def != data) 3591 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3592 3593 /* MGLS is a global flag to control all MGLS in GFX */ 3594 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3595 /* 2 - RLC memory Light sleep */ 3596 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3597 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3598 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3599 if (def != data) 3600 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3601 } 3602 /* 3 - CP memory Light sleep */ 3603 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3604 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3605 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3606 if (def != data) 3607 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3608 } 3609 } 3610 } else { 3611 /* 1 - MGCG_OVERRIDE */ 3612 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3613 3614 if (adev->asic_type != CHIP_VEGA12) 3615 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3616 3617 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3618 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3619 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3620 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3621 3622 if (def != data) 3623 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3624 3625 /* 2 - disable MGLS in RLC */ 3626 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3627 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3628 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3629 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3630 } 3631 3632 /* 3 - disable MGLS in CP */ 3633 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3634 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3635 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3636 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3637 } 3638 } 3639 } 3640 3641 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3642 bool enable) 3643 { 3644 uint32_t data, def; 3645 3646 amdgpu_gfx_rlc_enter_safe_mode(adev); 3647 3648 /* Enable 3D CGCG/CGLS */ 3649 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3650 /* write cmd to clear cgcg/cgls ov */ 3651 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3652 /* unset CGCG override */ 3653 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3654 /* update CGCG and CGLS override bits */ 3655 if (def != data) 3656 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3657 3658 /* enable 3Dcgcg FSM(0x0000363f) */ 3659 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3660 3661 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3662 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3663 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3664 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3665 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3666 if (def != data) 3667 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3668 3669 /* set IDLE_POLL_COUNT(0x00900100) */ 3670 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3671 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3672 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3673 if (def != data) 3674 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3675 } else { 3676 /* Disable CGCG/CGLS */ 3677 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3678 /* disable cgcg, cgls should be disabled */ 3679 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3680 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3681 /* disable cgcg and cgls in FSM */ 3682 if (def != data) 3683 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3684 } 3685 3686 amdgpu_gfx_rlc_exit_safe_mode(adev); 3687 } 3688 3689 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3690 bool enable) 3691 { 3692 uint32_t def, data; 3693 3694 amdgpu_gfx_rlc_enter_safe_mode(adev); 3695 3696 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3697 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3698 /* unset CGCG override */ 3699 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3700 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3701 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3702 else 3703 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3704 /* update CGCG and CGLS override bits */ 3705 if (def != data) 3706 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3707 3708 /* enable cgcg FSM(0x0000363F) */ 3709 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3710 3711 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3712 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3713 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3714 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3715 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3716 if (def != data) 3717 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3718 3719 /* set IDLE_POLL_COUNT(0x00900100) */ 3720 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3721 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3722 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3723 if (def != data) 3724 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3725 } else { 3726 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3727 /* reset CGCG/CGLS bits */ 3728 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3729 /* disable cgcg and cgls in FSM */ 3730 if (def != data) 3731 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3732 } 3733 3734 amdgpu_gfx_rlc_exit_safe_mode(adev); 3735 } 3736 3737 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3738 bool enable) 3739 { 3740 if (enable) { 3741 /* CGCG/CGLS should be enabled after MGCG/MGLS 3742 * === MGCG + MGLS === 3743 */ 3744 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3745 /* === CGCG /CGLS for GFX 3D Only === */ 3746 gfx_v9_0_update_3d_clock_gating(adev, enable); 3747 /* === CGCG + CGLS === */ 3748 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3749 } else { 3750 /* CGCG/CGLS should be disabled before MGCG/MGLS 3751 * === CGCG + CGLS === 3752 */ 3753 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3754 /* === CGCG /CGLS for GFX 3D Only === */ 3755 gfx_v9_0_update_3d_clock_gating(adev, enable); 3756 /* === MGCG + MGLS === */ 3757 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3758 } 3759 return 0; 3760 } 3761 3762 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3763 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 3764 .set_safe_mode = gfx_v9_0_set_safe_mode, 3765 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 3766 .init = gfx_v9_0_rlc_init, 3767 .get_csb_size = gfx_v9_0_get_csb_size, 3768 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 3769 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 3770 .resume = gfx_v9_0_rlc_resume, 3771 .stop = gfx_v9_0_rlc_stop, 3772 .reset = gfx_v9_0_rlc_reset, 3773 .start = gfx_v9_0_rlc_start 3774 }; 3775 3776 static int gfx_v9_0_set_powergating_state(void *handle, 3777 enum amd_powergating_state state) 3778 { 3779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3780 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3781 3782 switch (adev->asic_type) { 3783 case CHIP_RAVEN: 3784 if (!enable) { 3785 amdgpu_gfx_off_ctrl(adev, false); 3786 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 3787 } 3788 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3789 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3790 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3791 } else { 3792 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3793 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3794 } 3795 3796 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3797 gfx_v9_0_enable_cp_power_gating(adev, true); 3798 else 3799 gfx_v9_0_enable_cp_power_gating(adev, false); 3800 3801 /* update gfx cgpg state */ 3802 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3803 3804 /* update mgcg state */ 3805 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3806 3807 if (enable) 3808 amdgpu_gfx_off_ctrl(adev, true); 3809 break; 3810 case CHIP_VEGA12: 3811 if (!enable) { 3812 amdgpu_gfx_off_ctrl(adev, false); 3813 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 3814 } else { 3815 amdgpu_gfx_off_ctrl(adev, true); 3816 } 3817 break; 3818 default: 3819 break; 3820 } 3821 3822 return 0; 3823 } 3824 3825 static int gfx_v9_0_set_clockgating_state(void *handle, 3826 enum amd_clockgating_state state) 3827 { 3828 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3829 3830 if (amdgpu_sriov_vf(adev)) 3831 return 0; 3832 3833 switch (adev->asic_type) { 3834 case CHIP_VEGA10: 3835 case CHIP_VEGA12: 3836 case CHIP_VEGA20: 3837 case CHIP_RAVEN: 3838 gfx_v9_0_update_gfx_clock_gating(adev, 3839 state == AMD_CG_STATE_GATE ? true : false); 3840 break; 3841 default: 3842 break; 3843 } 3844 return 0; 3845 } 3846 3847 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3848 { 3849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3850 int data; 3851 3852 if (amdgpu_sriov_vf(adev)) 3853 *flags = 0; 3854 3855 /* AMD_CG_SUPPORT_GFX_MGCG */ 3856 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3857 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3858 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3859 3860 /* AMD_CG_SUPPORT_GFX_CGCG */ 3861 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3862 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3863 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3864 3865 /* AMD_CG_SUPPORT_GFX_CGLS */ 3866 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3867 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3868 3869 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 3870 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3871 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 3872 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 3873 3874 /* AMD_CG_SUPPORT_GFX_CP_LS */ 3875 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3876 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 3877 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 3878 3879 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3880 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3881 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3882 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3883 3884 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3885 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3886 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3887 } 3888 3889 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3890 { 3891 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 3892 } 3893 3894 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3895 { 3896 struct amdgpu_device *adev = ring->adev; 3897 u64 wptr; 3898 3899 /* XXX check if swapping is necessary on BE */ 3900 if (ring->use_doorbell) { 3901 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3902 } else { 3903 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 3904 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 3905 } 3906 3907 return wptr; 3908 } 3909 3910 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3911 { 3912 struct amdgpu_device *adev = ring->adev; 3913 3914 if (ring->use_doorbell) { 3915 /* XXX check if swapping is necessary on BE */ 3916 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3917 WDOORBELL64(ring->doorbell_index, ring->wptr); 3918 } else { 3919 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3920 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3921 } 3922 } 3923 3924 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3925 { 3926 struct amdgpu_device *adev = ring->adev; 3927 u32 ref_and_mask, reg_mem_engine; 3928 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 3929 3930 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3931 switch (ring->me) { 3932 case 1: 3933 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3934 break; 3935 case 2: 3936 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3937 break; 3938 default: 3939 return; 3940 } 3941 reg_mem_engine = 0; 3942 } else { 3943 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3944 reg_mem_engine = 1; /* pfp */ 3945 } 3946 3947 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3948 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 3949 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 3950 ref_and_mask, ref_and_mask, 0x20); 3951 } 3952 3953 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3954 struct amdgpu_job *job, 3955 struct amdgpu_ib *ib, 3956 bool ctx_switch) 3957 { 3958 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3959 u32 header, control = 0; 3960 3961 if (ib->flags & AMDGPU_IB_FLAG_CE) 3962 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3963 else 3964 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3965 3966 control |= ib->length_dw | (vmid << 24); 3967 3968 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3969 control |= INDIRECT_BUFFER_PRE_ENB(1); 3970 3971 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 3972 gfx_v9_0_ring_emit_de_meta(ring); 3973 } 3974 3975 amdgpu_ring_write(ring, header); 3976 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3977 amdgpu_ring_write(ring, 3978 #ifdef __BIG_ENDIAN 3979 (2 << 0) | 3980 #endif 3981 lower_32_bits(ib->gpu_addr)); 3982 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3983 amdgpu_ring_write(ring, control); 3984 } 3985 3986 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3987 struct amdgpu_job *job, 3988 struct amdgpu_ib *ib, 3989 bool ctx_switch) 3990 { 3991 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3992 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 3993 3994 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3995 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3996 amdgpu_ring_write(ring, 3997 #ifdef __BIG_ENDIAN 3998 (2 << 0) | 3999 #endif 4000 lower_32_bits(ib->gpu_addr)); 4001 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4002 amdgpu_ring_write(ring, control); 4003 } 4004 4005 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4006 u64 seq, unsigned flags) 4007 { 4008 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4009 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4010 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 4011 4012 /* RELEASE_MEM - flush caches, send int */ 4013 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4014 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 4015 EOP_TC_NC_ACTION_EN) : 4016 (EOP_TCL1_ACTION_EN | 4017 EOP_TC_ACTION_EN | 4018 EOP_TC_WB_ACTION_EN | 4019 EOP_TC_MD_ACTION_EN)) | 4020 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4021 EVENT_INDEX(5))); 4022 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 4023 4024 /* 4025 * the address should be Qword aligned if 64bit write, Dword 4026 * aligned if only send 32bit data low (discard data high) 4027 */ 4028 if (write64bit) 4029 BUG_ON(addr & 0x7); 4030 else 4031 BUG_ON(addr & 0x3); 4032 amdgpu_ring_write(ring, lower_32_bits(addr)); 4033 amdgpu_ring_write(ring, upper_32_bits(addr)); 4034 amdgpu_ring_write(ring, lower_32_bits(seq)); 4035 amdgpu_ring_write(ring, upper_32_bits(seq)); 4036 amdgpu_ring_write(ring, 0); 4037 } 4038 4039 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4040 { 4041 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4042 uint32_t seq = ring->fence_drv.sync_seq; 4043 uint64_t addr = ring->fence_drv.gpu_addr; 4044 4045 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 4046 lower_32_bits(addr), upper_32_bits(addr), 4047 seq, 0xffffffff, 4); 4048 } 4049 4050 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4051 unsigned vmid, uint64_t pd_addr) 4052 { 4053 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4054 4055 /* compute doesn't have PFP */ 4056 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4057 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4058 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4059 amdgpu_ring_write(ring, 0x0); 4060 } 4061 } 4062 4063 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4064 { 4065 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 4066 } 4067 4068 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4069 { 4070 u64 wptr; 4071 4072 /* XXX check if swapping is necessary on BE */ 4073 if (ring->use_doorbell) 4074 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4075 else 4076 BUG(); 4077 return wptr; 4078 } 4079 4080 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring, 4081 bool acquire) 4082 { 4083 struct amdgpu_device *adev = ring->adev; 4084 int pipe_num, tmp, reg; 4085 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1; 4086 4087 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; 4088 4089 /* first me only has 2 entries, GFX and HP3D */ 4090 if (ring->me > 0) 4091 pipe_num -= 2; 4092 4093 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; 4094 tmp = RREG32(reg); 4095 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent); 4096 WREG32(reg, tmp); 4097 } 4098 4099 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev, 4100 struct amdgpu_ring *ring, 4101 bool acquire) 4102 { 4103 int i, pipe; 4104 bool reserve; 4105 struct amdgpu_ring *iring; 4106 4107 mutex_lock(&adev->gfx.pipe_reserve_mutex); 4108 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0); 4109 if (acquire) 4110 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4111 else 4112 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4113 4114 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { 4115 /* Clear all reservations - everyone reacquires all resources */ 4116 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) 4117 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], 4118 true); 4119 4120 for (i = 0; i < adev->gfx.num_compute_rings; ++i) 4121 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], 4122 true); 4123 } else { 4124 /* Lower all pipes without a current reservation */ 4125 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 4126 iring = &adev->gfx.gfx_ring[i]; 4127 pipe = amdgpu_gfx_queue_to_bit(adev, 4128 iring->me, 4129 iring->pipe, 4130 0); 4131 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4132 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4133 } 4134 4135 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 4136 iring = &adev->gfx.compute_ring[i]; 4137 pipe = amdgpu_gfx_queue_to_bit(adev, 4138 iring->me, 4139 iring->pipe, 4140 0); 4141 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4142 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4143 } 4144 } 4145 4146 mutex_unlock(&adev->gfx.pipe_reserve_mutex); 4147 } 4148 4149 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev, 4150 struct amdgpu_ring *ring, 4151 bool acquire) 4152 { 4153 uint32_t pipe_priority = acquire ? 0x2 : 0x0; 4154 uint32_t queue_priority = acquire ? 0xf : 0x0; 4155 4156 mutex_lock(&adev->srbm_mutex); 4157 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4158 4159 WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); 4160 WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); 4161 4162 soc15_grbm_select(adev, 0, 0, 0, 0); 4163 mutex_unlock(&adev->srbm_mutex); 4164 } 4165 4166 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring, 4167 enum drm_sched_priority priority) 4168 { 4169 struct amdgpu_device *adev = ring->adev; 4170 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; 4171 4172 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) 4173 return; 4174 4175 gfx_v9_0_hqd_set_priority(adev, ring, acquire); 4176 gfx_v9_0_pipe_reserve_resources(adev, ring, acquire); 4177 } 4178 4179 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4180 { 4181 struct amdgpu_device *adev = ring->adev; 4182 4183 /* XXX check if swapping is necessary on BE */ 4184 if (ring->use_doorbell) { 4185 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4186 WDOORBELL64(ring->doorbell_index, ring->wptr); 4187 } else{ 4188 BUG(); /* only DOORBELL method supported on gfx9 now */ 4189 } 4190 } 4191 4192 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4193 u64 seq, unsigned int flags) 4194 { 4195 struct amdgpu_device *adev = ring->adev; 4196 4197 /* we only allocate 32bit for each seq wb address */ 4198 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4199 4200 /* write fence seq to the "addr" */ 4201 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4202 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4203 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4204 amdgpu_ring_write(ring, lower_32_bits(addr)); 4205 amdgpu_ring_write(ring, upper_32_bits(addr)); 4206 amdgpu_ring_write(ring, lower_32_bits(seq)); 4207 4208 if (flags & AMDGPU_FENCE_FLAG_INT) { 4209 /* set register to trigger INT */ 4210 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4211 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4212 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4213 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4214 amdgpu_ring_write(ring, 0); 4215 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4216 } 4217 } 4218 4219 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 4220 { 4221 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4222 amdgpu_ring_write(ring, 0); 4223 } 4224 4225 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 4226 { 4227 struct v9_ce_ib_state ce_payload = {0}; 4228 uint64_t csa_addr; 4229 int cnt; 4230 4231 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4232 csa_addr = amdgpu_csa_vaddr(ring->adev); 4233 4234 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4235 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4236 WRITE_DATA_DST_SEL(8) | 4237 WR_CONFIRM) | 4238 WRITE_DATA_CACHE_POLICY(0)); 4239 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4240 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4241 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 4242 } 4243 4244 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 4245 { 4246 struct v9_de_ib_state de_payload = {0}; 4247 uint64_t csa_addr, gds_addr; 4248 int cnt; 4249 4250 csa_addr = amdgpu_csa_vaddr(ring->adev); 4251 gds_addr = csa_addr + 4096; 4252 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4253 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4254 4255 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4256 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4257 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4258 WRITE_DATA_DST_SEL(8) | 4259 WR_CONFIRM) | 4260 WRITE_DATA_CACHE_POLICY(0)); 4261 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4262 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4263 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 4264 } 4265 4266 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4267 { 4268 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4269 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4270 } 4271 4272 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4273 { 4274 uint32_t dw2 = 0; 4275 4276 if (amdgpu_sriov_vf(ring->adev)) 4277 gfx_v9_0_ring_emit_ce_meta(ring); 4278 4279 gfx_v9_0_ring_emit_tmz(ring, true); 4280 4281 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4282 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4283 /* set load_global_config & load_global_uconfig */ 4284 dw2 |= 0x8001; 4285 /* set load_cs_sh_regs */ 4286 dw2 |= 0x01000000; 4287 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4288 dw2 |= 0x10002; 4289 4290 /* set load_ce_ram if preamble presented */ 4291 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4292 dw2 |= 0x10000000; 4293 } else { 4294 /* still load_ce_ram if this is the first time preamble presented 4295 * although there is no context switch happens. 4296 */ 4297 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4298 dw2 |= 0x10000000; 4299 } 4300 4301 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4302 amdgpu_ring_write(ring, dw2); 4303 amdgpu_ring_write(ring, 0); 4304 } 4305 4306 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4307 { 4308 unsigned ret; 4309 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4310 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4311 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4312 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4313 ret = ring->wptr & ring->buf_mask; 4314 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4315 return ret; 4316 } 4317 4318 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4319 { 4320 unsigned cur; 4321 BUG_ON(offset > ring->buf_mask); 4322 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4323 4324 cur = (ring->wptr & ring->buf_mask) - 1; 4325 if (likely(cur > offset)) 4326 ring->ring[offset] = cur - offset; 4327 else 4328 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 4329 } 4330 4331 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4332 { 4333 struct amdgpu_device *adev = ring->adev; 4334 4335 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4336 amdgpu_ring_write(ring, 0 | /* src: register*/ 4337 (5 << 8) | /* dst: memory */ 4338 (1 << 20)); /* write confirm */ 4339 amdgpu_ring_write(ring, reg); 4340 amdgpu_ring_write(ring, 0); 4341 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4342 adev->virt.reg_val_offs * 4)); 4343 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4344 adev->virt.reg_val_offs * 4)); 4345 } 4346 4347 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4348 uint32_t val) 4349 { 4350 uint32_t cmd = 0; 4351 4352 switch (ring->funcs->type) { 4353 case AMDGPU_RING_TYPE_GFX: 4354 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4355 break; 4356 case AMDGPU_RING_TYPE_KIQ: 4357 cmd = (1 << 16); /* no inc addr */ 4358 break; 4359 default: 4360 cmd = WR_CONFIRM; 4361 break; 4362 } 4363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4364 amdgpu_ring_write(ring, cmd); 4365 amdgpu_ring_write(ring, reg); 4366 amdgpu_ring_write(ring, 0); 4367 amdgpu_ring_write(ring, val); 4368 } 4369 4370 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4371 uint32_t val, uint32_t mask) 4372 { 4373 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4374 } 4375 4376 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4377 uint32_t reg0, uint32_t reg1, 4378 uint32_t ref, uint32_t mask) 4379 { 4380 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4381 struct amdgpu_device *adev = ring->adev; 4382 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 4383 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 4384 4385 if (fw_version_ok) 4386 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4387 ref, mask, 0x20); 4388 else 4389 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4390 ref, mask); 4391 } 4392 4393 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4394 { 4395 struct amdgpu_device *adev = ring->adev; 4396 uint32_t value = 0; 4397 4398 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4399 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4400 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4401 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4402 WREG32(mmSQ_CMD, value); 4403 } 4404 4405 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4406 enum amdgpu_interrupt_state state) 4407 { 4408 switch (state) { 4409 case AMDGPU_IRQ_STATE_DISABLE: 4410 case AMDGPU_IRQ_STATE_ENABLE: 4411 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4412 TIME_STAMP_INT_ENABLE, 4413 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4414 break; 4415 default: 4416 break; 4417 } 4418 } 4419 4420 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4421 int me, int pipe, 4422 enum amdgpu_interrupt_state state) 4423 { 4424 u32 mec_int_cntl, mec_int_cntl_reg; 4425 4426 /* 4427 * amdgpu controls only the first MEC. That's why this function only 4428 * handles the setting of interrupts for this specific MEC. All other 4429 * pipes' interrupts are set by amdkfd. 4430 */ 4431 4432 if (me == 1) { 4433 switch (pipe) { 4434 case 0: 4435 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4436 break; 4437 case 1: 4438 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4439 break; 4440 case 2: 4441 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4442 break; 4443 case 3: 4444 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4445 break; 4446 default: 4447 DRM_DEBUG("invalid pipe %d\n", pipe); 4448 return; 4449 } 4450 } else { 4451 DRM_DEBUG("invalid me %d\n", me); 4452 return; 4453 } 4454 4455 switch (state) { 4456 case AMDGPU_IRQ_STATE_DISABLE: 4457 mec_int_cntl = RREG32(mec_int_cntl_reg); 4458 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4459 TIME_STAMP_INT_ENABLE, 0); 4460 WREG32(mec_int_cntl_reg, mec_int_cntl); 4461 break; 4462 case AMDGPU_IRQ_STATE_ENABLE: 4463 mec_int_cntl = RREG32(mec_int_cntl_reg); 4464 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4465 TIME_STAMP_INT_ENABLE, 1); 4466 WREG32(mec_int_cntl_reg, mec_int_cntl); 4467 break; 4468 default: 4469 break; 4470 } 4471 } 4472 4473 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4474 struct amdgpu_irq_src *source, 4475 unsigned type, 4476 enum amdgpu_interrupt_state state) 4477 { 4478 switch (state) { 4479 case AMDGPU_IRQ_STATE_DISABLE: 4480 case AMDGPU_IRQ_STATE_ENABLE: 4481 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4482 PRIV_REG_INT_ENABLE, 4483 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4484 break; 4485 default: 4486 break; 4487 } 4488 4489 return 0; 4490 } 4491 4492 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4493 struct amdgpu_irq_src *source, 4494 unsigned type, 4495 enum amdgpu_interrupt_state state) 4496 { 4497 switch (state) { 4498 case AMDGPU_IRQ_STATE_DISABLE: 4499 case AMDGPU_IRQ_STATE_ENABLE: 4500 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4501 PRIV_INSTR_INT_ENABLE, 4502 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4503 default: 4504 break; 4505 } 4506 4507 return 0; 4508 } 4509 4510 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4511 struct amdgpu_irq_src *src, 4512 unsigned type, 4513 enum amdgpu_interrupt_state state) 4514 { 4515 switch (type) { 4516 case AMDGPU_CP_IRQ_GFX_EOP: 4517 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4518 break; 4519 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4520 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4521 break; 4522 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4523 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4524 break; 4525 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4526 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4527 break; 4528 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4529 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4530 break; 4531 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4532 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4533 break; 4534 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4535 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4536 break; 4537 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4538 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4539 break; 4540 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4541 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4542 break; 4543 default: 4544 break; 4545 } 4546 return 0; 4547 } 4548 4549 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4550 struct amdgpu_irq_src *source, 4551 struct amdgpu_iv_entry *entry) 4552 { 4553 int i; 4554 u8 me_id, pipe_id, queue_id; 4555 struct amdgpu_ring *ring; 4556 4557 DRM_DEBUG("IH: CP EOP\n"); 4558 me_id = (entry->ring_id & 0x0c) >> 2; 4559 pipe_id = (entry->ring_id & 0x03) >> 0; 4560 queue_id = (entry->ring_id & 0x70) >> 4; 4561 4562 switch (me_id) { 4563 case 0: 4564 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4565 break; 4566 case 1: 4567 case 2: 4568 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4569 ring = &adev->gfx.compute_ring[i]; 4570 /* Per-queue interrupt is supported for MEC starting from VI. 4571 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4572 */ 4573 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4574 amdgpu_fence_process(ring); 4575 } 4576 break; 4577 } 4578 return 0; 4579 } 4580 4581 static void gfx_v9_0_fault(struct amdgpu_device *adev, 4582 struct amdgpu_iv_entry *entry) 4583 { 4584 u8 me_id, pipe_id, queue_id; 4585 struct amdgpu_ring *ring; 4586 int i; 4587 4588 me_id = (entry->ring_id & 0x0c) >> 2; 4589 pipe_id = (entry->ring_id & 0x03) >> 0; 4590 queue_id = (entry->ring_id & 0x70) >> 4; 4591 4592 switch (me_id) { 4593 case 0: 4594 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4595 break; 4596 case 1: 4597 case 2: 4598 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4599 ring = &adev->gfx.compute_ring[i]; 4600 if (ring->me == me_id && ring->pipe == pipe_id && 4601 ring->queue == queue_id) 4602 drm_sched_fault(&ring->sched); 4603 } 4604 break; 4605 } 4606 } 4607 4608 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4609 struct amdgpu_irq_src *source, 4610 struct amdgpu_iv_entry *entry) 4611 { 4612 DRM_ERROR("Illegal register access in command stream\n"); 4613 gfx_v9_0_fault(adev, entry); 4614 return 0; 4615 } 4616 4617 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4618 struct amdgpu_irq_src *source, 4619 struct amdgpu_iv_entry *entry) 4620 { 4621 DRM_ERROR("Illegal instruction in command stream\n"); 4622 gfx_v9_0_fault(adev, entry); 4623 return 0; 4624 } 4625 4626 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4627 .name = "gfx_v9_0", 4628 .early_init = gfx_v9_0_early_init, 4629 .late_init = gfx_v9_0_late_init, 4630 .sw_init = gfx_v9_0_sw_init, 4631 .sw_fini = gfx_v9_0_sw_fini, 4632 .hw_init = gfx_v9_0_hw_init, 4633 .hw_fini = gfx_v9_0_hw_fini, 4634 .suspend = gfx_v9_0_suspend, 4635 .resume = gfx_v9_0_resume, 4636 .is_idle = gfx_v9_0_is_idle, 4637 .wait_for_idle = gfx_v9_0_wait_for_idle, 4638 .soft_reset = gfx_v9_0_soft_reset, 4639 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4640 .set_powergating_state = gfx_v9_0_set_powergating_state, 4641 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4642 }; 4643 4644 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4645 .type = AMDGPU_RING_TYPE_GFX, 4646 .align_mask = 0xff, 4647 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4648 .support_64bit_ptrs = true, 4649 .vmhub = AMDGPU_GFXHUB, 4650 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4651 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4652 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4653 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4654 5 + /* COND_EXEC */ 4655 7 + /* PIPELINE_SYNC */ 4656 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4657 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4658 2 + /* VM_FLUSH */ 4659 8 + /* FENCE for VM_FLUSH */ 4660 20 + /* GDS switch */ 4661 4 + /* double SWITCH_BUFFER, 4662 the first COND_EXEC jump to the place just 4663 prior to this double SWITCH_BUFFER */ 4664 5 + /* COND_EXEC */ 4665 7 + /* HDP_flush */ 4666 4 + /* VGT_flush */ 4667 14 + /* CE_META */ 4668 31 + /* DE_META */ 4669 3 + /* CNTX_CTRL */ 4670 5 + /* HDP_INVL */ 4671 8 + 8 + /* FENCE x2 */ 4672 2, /* SWITCH_BUFFER */ 4673 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4674 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4675 .emit_fence = gfx_v9_0_ring_emit_fence, 4676 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4677 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4678 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4679 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4680 .test_ring = gfx_v9_0_ring_test_ring, 4681 .test_ib = gfx_v9_0_ring_test_ib, 4682 .insert_nop = amdgpu_ring_insert_nop, 4683 .pad_ib = amdgpu_ring_generic_pad_ib, 4684 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4685 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4686 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4687 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4688 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4689 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4690 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4691 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4692 .soft_recovery = gfx_v9_0_ring_soft_recovery, 4693 }; 4694 4695 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4696 .type = AMDGPU_RING_TYPE_COMPUTE, 4697 .align_mask = 0xff, 4698 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4699 .support_64bit_ptrs = true, 4700 .vmhub = AMDGPU_GFXHUB, 4701 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4702 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4703 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4704 .emit_frame_size = 4705 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4706 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4707 5 + /* hdp invalidate */ 4708 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4709 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4710 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4711 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4712 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4713 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4714 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4715 .emit_fence = gfx_v9_0_ring_emit_fence, 4716 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4717 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4718 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4719 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4720 .test_ring = gfx_v9_0_ring_test_ring, 4721 .test_ib = gfx_v9_0_ring_test_ib, 4722 .insert_nop = amdgpu_ring_insert_nop, 4723 .pad_ib = amdgpu_ring_generic_pad_ib, 4724 .set_priority = gfx_v9_0_ring_set_priority_compute, 4725 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4726 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4727 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4728 }; 4729 4730 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4731 .type = AMDGPU_RING_TYPE_KIQ, 4732 .align_mask = 0xff, 4733 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4734 .support_64bit_ptrs = true, 4735 .vmhub = AMDGPU_GFXHUB, 4736 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4737 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4738 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4739 .emit_frame_size = 4740 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4741 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4742 5 + /* hdp invalidate */ 4743 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4744 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4745 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4746 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4747 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4748 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4749 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4750 .test_ring = gfx_v9_0_ring_test_ring, 4751 .insert_nop = amdgpu_ring_insert_nop, 4752 .pad_ib = amdgpu_ring_generic_pad_ib, 4753 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4754 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4755 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4756 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4757 }; 4758 4759 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4760 { 4761 int i; 4762 4763 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4764 4765 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4766 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4767 4768 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4769 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 4770 } 4771 4772 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 4773 .set = gfx_v9_0_set_eop_interrupt_state, 4774 .process = gfx_v9_0_eop_irq, 4775 }; 4776 4777 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 4778 .set = gfx_v9_0_set_priv_reg_fault_state, 4779 .process = gfx_v9_0_priv_reg_irq, 4780 }; 4781 4782 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 4783 .set = gfx_v9_0_set_priv_inst_fault_state, 4784 .process = gfx_v9_0_priv_inst_irq, 4785 }; 4786 4787 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 4788 { 4789 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4790 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 4791 4792 adev->gfx.priv_reg_irq.num_types = 1; 4793 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 4794 4795 adev->gfx.priv_inst_irq.num_types = 1; 4796 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 4797 } 4798 4799 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 4800 { 4801 switch (adev->asic_type) { 4802 case CHIP_VEGA10: 4803 case CHIP_VEGA12: 4804 case CHIP_VEGA20: 4805 case CHIP_RAVEN: 4806 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4807 break; 4808 default: 4809 break; 4810 } 4811 } 4812 4813 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4814 { 4815 /* init asci gds info */ 4816 switch (adev->asic_type) { 4817 case CHIP_VEGA10: 4818 case CHIP_VEGA12: 4819 case CHIP_VEGA20: 4820 adev->gds.mem.total_size = 0x10000; 4821 break; 4822 case CHIP_RAVEN: 4823 adev->gds.mem.total_size = 0x1000; 4824 break; 4825 default: 4826 adev->gds.mem.total_size = 0x10000; 4827 break; 4828 } 4829 4830 adev->gds.gws.total_size = 64; 4831 adev->gds.oa.total_size = 16; 4832 4833 if (adev->gds.mem.total_size == 64 * 1024) { 4834 adev->gds.mem.gfx_partition_size = 4096; 4835 adev->gds.mem.cs_partition_size = 4096; 4836 4837 adev->gds.gws.gfx_partition_size = 4; 4838 adev->gds.gws.cs_partition_size = 4; 4839 4840 adev->gds.oa.gfx_partition_size = 4; 4841 adev->gds.oa.cs_partition_size = 1; 4842 } else { 4843 adev->gds.mem.gfx_partition_size = 1024; 4844 adev->gds.mem.cs_partition_size = 1024; 4845 4846 adev->gds.gws.gfx_partition_size = 16; 4847 adev->gds.gws.cs_partition_size = 16; 4848 4849 adev->gds.oa.gfx_partition_size = 4; 4850 adev->gds.oa.cs_partition_size = 4; 4851 } 4852 } 4853 4854 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4855 u32 bitmap) 4856 { 4857 u32 data; 4858 4859 if (!bitmap) 4860 return; 4861 4862 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4863 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4864 4865 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 4866 } 4867 4868 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4869 { 4870 u32 data, mask; 4871 4872 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 4873 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 4874 4875 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4876 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4877 4878 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4879 4880 return (~data) & mask; 4881 } 4882 4883 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 4884 struct amdgpu_cu_info *cu_info) 4885 { 4886 int i, j, k, counter, active_cu_number = 0; 4887 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4888 unsigned disable_masks[4 * 2]; 4889 4890 if (!adev || !cu_info) 4891 return -EINVAL; 4892 4893 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 4894 4895 mutex_lock(&adev->grbm_idx_mutex); 4896 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4897 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4898 mask = 1; 4899 ao_bitmap = 0; 4900 counter = 0; 4901 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4902 if (i < 4 && j < 2) 4903 gfx_v9_0_set_user_cu_inactive_bitmap( 4904 adev, disable_masks[i * 2 + j]); 4905 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4906 cu_info->bitmap[i][j] = bitmap; 4907 4908 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4909 if (bitmap & mask) { 4910 if (counter < adev->gfx.config.max_cu_per_sh) 4911 ao_bitmap |= mask; 4912 counter ++; 4913 } 4914 mask <<= 1; 4915 } 4916 active_cu_number += counter; 4917 if (i < 2 && j < 2) 4918 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4919 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4920 } 4921 } 4922 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4923 mutex_unlock(&adev->grbm_idx_mutex); 4924 4925 cu_info->number = active_cu_number; 4926 cu_info->ao_cu_mask = ao_cu_mask; 4927 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4928 4929 return 0; 4930 } 4931 4932 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4933 { 4934 .type = AMD_IP_BLOCK_TYPE_GFX, 4935 .major = 9, 4936 .minor = 0, 4937 .rev = 0, 4938 .funcs = &gfx_v9_0_ip_funcs, 4939 }; 4940