1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "gfx_v9_4.h" 51 #include "gfx_v9_0.h" 52 53 #include "asic_reg/pwr/pwr_10_0_offset.h" 54 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 55 #include "asic_reg/gc/gc_9_0_default.h" 56 57 #define GFX9_NUM_GFX_RINGS 1 58 #define GFX9_MEC_HPD_SIZE 4096 59 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 60 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 61 62 #define mmGCEA_PROBE_MAP 0x070c 63 #define mmGCEA_PROBE_MAP_BASE_IDX 0 64 65 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 66 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 67 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 68 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 71 72 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 73 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 74 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 75 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 78 79 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 80 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 81 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 82 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 85 86 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 87 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 88 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 89 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 92 93 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 94 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 95 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 96 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 100 101 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 102 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 103 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 104 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 107 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 108 109 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 110 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 113 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 114 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 115 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 117 118 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 119 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 120 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 121 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 124 125 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 126 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 127 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 128 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 129 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 130 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 131 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 132 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 133 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 134 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 135 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 136 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 137 138 enum ta_ras_gfx_subblock { 139 /*CPC*/ 140 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 141 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 142 TA_RAS_BLOCK__GFX_CPC_UCODE, 143 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 144 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 145 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 146 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 147 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 148 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 149 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 150 /* CPF*/ 151 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 152 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 153 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 154 TA_RAS_BLOCK__GFX_CPF_TAG, 155 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 156 /* CPG*/ 157 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 158 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 159 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 160 TA_RAS_BLOCK__GFX_CPG_TAG, 161 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 162 /* GDS*/ 163 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 164 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 165 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 166 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 167 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 168 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 169 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 170 /* SPI*/ 171 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 172 /* SQ*/ 173 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 174 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 175 TA_RAS_BLOCK__GFX_SQ_LDS_D, 176 TA_RAS_BLOCK__GFX_SQ_LDS_I, 177 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 178 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 179 /* SQC (3 ranges)*/ 180 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 181 /* SQC range 0*/ 182 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 183 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 184 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 185 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 186 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 187 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 188 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 189 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 190 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 191 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 192 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 193 /* SQC range 1*/ 194 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 195 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 196 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 197 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 198 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 199 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 200 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 201 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 202 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 203 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 204 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 205 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 206 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 207 /* SQC range 2*/ 208 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 210 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 212 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 213 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 217 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 219 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 220 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 221 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 222 /* TA*/ 223 TA_RAS_BLOCK__GFX_TA_INDEX_START, 224 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 225 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 226 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 227 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 228 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 229 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 230 /* TCA*/ 231 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 232 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 233 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 234 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 235 /* TCC (5 sub-ranges)*/ 236 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 237 /* TCC range 0*/ 238 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 239 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 240 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 241 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 242 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 243 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 244 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 245 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 246 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 247 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 248 /* TCC range 1*/ 249 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 250 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 251 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 252 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 253 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 254 /* TCC range 2*/ 255 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 256 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 257 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 258 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 259 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 260 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 261 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 262 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 263 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 264 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 265 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 266 /* TCC range 3*/ 267 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 268 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 269 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 270 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 271 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 272 /* TCC range 4*/ 273 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 274 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 275 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 276 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 277 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 278 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 279 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 280 /* TCI*/ 281 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 282 /* TCP*/ 283 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 284 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 285 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 286 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 287 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 288 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 289 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 290 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 291 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 292 /* TD*/ 293 TA_RAS_BLOCK__GFX_TD_INDEX_START, 294 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 295 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 296 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 297 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 298 /* EA (3 sub-ranges)*/ 299 TA_RAS_BLOCK__GFX_EA_INDEX_START, 300 /* EA range 0*/ 301 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 302 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 303 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 304 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 305 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 306 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 307 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 308 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 309 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 310 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 311 /* EA range 1*/ 312 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 313 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 314 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 315 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 316 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 317 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 318 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 319 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 320 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 321 /* EA range 2*/ 322 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 323 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 324 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 325 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 326 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 327 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 328 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 329 /* UTC VM L2 bank*/ 330 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 331 /* UTC VM walker*/ 332 TA_RAS_BLOCK__UTC_VML2_WALKER, 333 /* UTC ATC L2 2MB cache*/ 334 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 335 /* UTC ATC L2 4KB cache*/ 336 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 337 TA_RAS_BLOCK__GFX_MAX 338 }; 339 340 struct ras_gfx_subblock { 341 unsigned char *name; 342 int ta_subblock; 343 int hw_supported_error_type; 344 int sw_supported_error_type; 345 }; 346 347 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 348 [AMDGPU_RAS_BLOCK__##subblock] = { \ 349 #subblock, \ 350 TA_RAS_BLOCK__##subblock, \ 351 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 352 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 353 } 354 355 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 356 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 357 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 358 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 359 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 360 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 361 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 362 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 363 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 364 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 365 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 366 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 367 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 368 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 369 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 370 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 371 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 372 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 373 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 375 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 378 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 379 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 380 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 381 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 382 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 383 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 384 0, 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 386 0), 387 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 388 0, 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 390 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 392 0, 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 394 0), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 396 1), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 398 0, 0, 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 400 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 402 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 404 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 406 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 408 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 410 0, 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 412 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 416 0, 0, 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 422 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 428 0, 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 430 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 432 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 434 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 436 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 438 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 439 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 440 1), 441 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 442 1), 443 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 444 1), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 446 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 448 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 461 0), 462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 464 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 466 0, 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 468 0), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 478 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 480 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 481 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 485 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 502 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 503 }; 504 505 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 506 { 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 527 }; 528 529 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 530 { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 549 }; 550 551 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 552 { 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 564 }; 565 566 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 567 { 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 592 }; 593 594 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 595 { 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 603 }; 604 605 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 606 { 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 626 }; 627 628 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 629 { 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 642 }; 643 644 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 645 { 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 649 }; 650 651 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 652 { 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 669 }; 670 671 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 672 { 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 686 }; 687 688 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 689 { 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 701 }; 702 703 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 704 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 705 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 706 }; 707 708 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 709 { 710 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 711 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 712 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 713 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 714 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 715 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 716 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 717 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 718 }; 719 720 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 721 { 722 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 723 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 724 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 725 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 726 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 727 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 728 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 729 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 730 }; 731 732 static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 733 { 734 static void *scratch_reg0; 735 static void *scratch_reg1; 736 static void *scratch_reg2; 737 static void *scratch_reg3; 738 static void *spare_int; 739 static uint32_t grbm_cntl; 740 static uint32_t grbm_idx; 741 742 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 743 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 744 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 745 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 746 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 747 748 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 749 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 750 751 if (amdgpu_sriov_runtime(adev)) { 752 pr_err("shouldn't call rlcg write register during runtime\n"); 753 return; 754 } 755 756 if (offset == grbm_cntl || offset == grbm_idx) { 757 if (offset == grbm_cntl) 758 writel(v, scratch_reg2); 759 else if (offset == grbm_idx) 760 writel(v, scratch_reg3); 761 762 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); 763 } else { 764 uint32_t i = 0; 765 uint32_t retries = 50000; 766 767 writel(v, scratch_reg0); 768 writel(offset | 0x80000000, scratch_reg1); 769 writel(1, spare_int); 770 for (i = 0; i < retries; i++) { 771 u32 tmp; 772 773 tmp = readl(scratch_reg1); 774 if (!(tmp & 0x80000000)) 775 break; 776 777 udelay(10); 778 } 779 if (i >= retries) 780 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 781 } 782 783 } 784 785 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 786 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 787 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 788 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 789 790 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 791 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 792 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 793 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 794 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 795 struct amdgpu_cu_info *cu_info); 796 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 797 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 798 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 799 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 800 void *ras_error_status); 801 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 802 void *inject_if); 803 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 804 805 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 806 uint64_t queue_mask) 807 { 808 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 809 amdgpu_ring_write(kiq_ring, 810 PACKET3_SET_RESOURCES_VMID_MASK(0) | 811 /* vmid_mask:0* queue_type:0 (KIQ) */ 812 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 813 amdgpu_ring_write(kiq_ring, 814 lower_32_bits(queue_mask)); /* queue mask lo */ 815 amdgpu_ring_write(kiq_ring, 816 upper_32_bits(queue_mask)); /* queue mask hi */ 817 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 818 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 819 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 820 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 821 } 822 823 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 824 struct amdgpu_ring *ring) 825 { 826 struct amdgpu_device *adev = kiq_ring->adev; 827 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 828 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 829 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 830 831 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 832 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 833 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 834 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 835 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 836 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 837 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 838 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 839 /*queue_type: normal compute queue */ 840 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 841 /* alloc format: all_on_one_pipe */ 842 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 843 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 844 /* num_queues: must be 1 */ 845 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 846 amdgpu_ring_write(kiq_ring, 847 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 848 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 849 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 850 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 851 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 852 } 853 854 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 855 struct amdgpu_ring *ring, 856 enum amdgpu_unmap_queues_action action, 857 u64 gpu_addr, u64 seq) 858 { 859 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 860 861 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 862 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 863 PACKET3_UNMAP_QUEUES_ACTION(action) | 864 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 865 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 866 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 867 amdgpu_ring_write(kiq_ring, 868 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 869 870 if (action == PREEMPT_QUEUES_NO_UNMAP) { 871 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 872 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 873 amdgpu_ring_write(kiq_ring, seq); 874 } else { 875 amdgpu_ring_write(kiq_ring, 0); 876 amdgpu_ring_write(kiq_ring, 0); 877 amdgpu_ring_write(kiq_ring, 0); 878 } 879 } 880 881 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 882 struct amdgpu_ring *ring, 883 u64 addr, 884 u64 seq) 885 { 886 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 887 888 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 889 amdgpu_ring_write(kiq_ring, 890 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 891 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 892 PACKET3_QUERY_STATUS_COMMAND(2)); 893 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 894 amdgpu_ring_write(kiq_ring, 895 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 896 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 897 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 898 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 899 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 900 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 901 } 902 903 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 904 uint16_t pasid, uint32_t flush_type, 905 bool all_hub) 906 { 907 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 908 amdgpu_ring_write(kiq_ring, 909 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 910 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 911 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 912 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 913 } 914 915 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 916 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 917 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 918 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 919 .kiq_query_status = gfx_v9_0_kiq_query_status, 920 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 921 .set_resources_size = 8, 922 .map_queues_size = 7, 923 .unmap_queues_size = 6, 924 .query_status_size = 7, 925 .invalidate_tlbs_size = 2, 926 }; 927 928 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 929 { 930 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 931 } 932 933 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 934 { 935 switch (adev->asic_type) { 936 case CHIP_VEGA10: 937 soc15_program_register_sequence(adev, 938 golden_settings_gc_9_0, 939 ARRAY_SIZE(golden_settings_gc_9_0)); 940 soc15_program_register_sequence(adev, 941 golden_settings_gc_9_0_vg10, 942 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 943 break; 944 case CHIP_VEGA12: 945 soc15_program_register_sequence(adev, 946 golden_settings_gc_9_2_1, 947 ARRAY_SIZE(golden_settings_gc_9_2_1)); 948 soc15_program_register_sequence(adev, 949 golden_settings_gc_9_2_1_vg12, 950 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 951 break; 952 case CHIP_VEGA20: 953 soc15_program_register_sequence(adev, 954 golden_settings_gc_9_0, 955 ARRAY_SIZE(golden_settings_gc_9_0)); 956 soc15_program_register_sequence(adev, 957 golden_settings_gc_9_0_vg20, 958 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 959 break; 960 case CHIP_ARCTURUS: 961 soc15_program_register_sequence(adev, 962 golden_settings_gc_9_4_1_arct, 963 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 964 break; 965 case CHIP_RAVEN: 966 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 967 ARRAY_SIZE(golden_settings_gc_9_1)); 968 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 969 soc15_program_register_sequence(adev, 970 golden_settings_gc_9_1_rv2, 971 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 972 else 973 soc15_program_register_sequence(adev, 974 golden_settings_gc_9_1_rv1, 975 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 976 break; 977 case CHIP_RENOIR: 978 soc15_program_register_sequence(adev, 979 golden_settings_gc_9_1_rn, 980 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 981 return; /* for renoir, don't need common goldensetting */ 982 default: 983 break; 984 } 985 986 if (adev->asic_type != CHIP_ARCTURUS) 987 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 988 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 989 } 990 991 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 992 { 993 adev->gfx.scratch.num_reg = 8; 994 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 995 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 996 } 997 998 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 999 bool wc, uint32_t reg, uint32_t val) 1000 { 1001 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1002 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 1003 WRITE_DATA_DST_SEL(0) | 1004 (wc ? WR_CONFIRM : 0)); 1005 amdgpu_ring_write(ring, reg); 1006 amdgpu_ring_write(ring, 0); 1007 amdgpu_ring_write(ring, val); 1008 } 1009 1010 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 1011 int mem_space, int opt, uint32_t addr0, 1012 uint32_t addr1, uint32_t ref, uint32_t mask, 1013 uint32_t inv) 1014 { 1015 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1016 amdgpu_ring_write(ring, 1017 /* memory (1) or register (0) */ 1018 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 1019 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 1020 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 1021 WAIT_REG_MEM_ENGINE(eng_sel))); 1022 1023 if (mem_space) 1024 BUG_ON(addr0 & 0x3); /* Dword align */ 1025 amdgpu_ring_write(ring, addr0); 1026 amdgpu_ring_write(ring, addr1); 1027 amdgpu_ring_write(ring, ref); 1028 amdgpu_ring_write(ring, mask); 1029 amdgpu_ring_write(ring, inv); /* poll interval */ 1030 } 1031 1032 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1033 { 1034 struct amdgpu_device *adev = ring->adev; 1035 uint32_t scratch; 1036 uint32_t tmp = 0; 1037 unsigned i; 1038 int r; 1039 1040 r = amdgpu_gfx_scratch_get(adev, &scratch); 1041 if (r) 1042 return r; 1043 1044 WREG32(scratch, 0xCAFEDEAD); 1045 r = amdgpu_ring_alloc(ring, 3); 1046 if (r) 1047 goto error_free_scratch; 1048 1049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1050 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 1051 amdgpu_ring_write(ring, 0xDEADBEEF); 1052 amdgpu_ring_commit(ring); 1053 1054 for (i = 0; i < adev->usec_timeout; i++) { 1055 tmp = RREG32(scratch); 1056 if (tmp == 0xDEADBEEF) 1057 break; 1058 udelay(1); 1059 } 1060 1061 if (i >= adev->usec_timeout) 1062 r = -ETIMEDOUT; 1063 1064 error_free_scratch: 1065 amdgpu_gfx_scratch_free(adev, scratch); 1066 return r; 1067 } 1068 1069 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1070 { 1071 struct amdgpu_device *adev = ring->adev; 1072 struct amdgpu_ib ib; 1073 struct dma_fence *f = NULL; 1074 1075 unsigned index; 1076 uint64_t gpu_addr; 1077 uint32_t tmp; 1078 long r; 1079 1080 r = amdgpu_device_wb_get(adev, &index); 1081 if (r) 1082 return r; 1083 1084 gpu_addr = adev->wb.gpu_addr + (index * 4); 1085 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1086 memset(&ib, 0, sizeof(ib)); 1087 r = amdgpu_ib_get(adev, NULL, 16, 1088 AMDGPU_IB_POOL_DIRECT, &ib); 1089 if (r) 1090 goto err1; 1091 1092 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1093 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1094 ib.ptr[2] = lower_32_bits(gpu_addr); 1095 ib.ptr[3] = upper_32_bits(gpu_addr); 1096 ib.ptr[4] = 0xDEADBEEF; 1097 ib.length_dw = 5; 1098 1099 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1100 if (r) 1101 goto err2; 1102 1103 r = dma_fence_wait_timeout(f, false, timeout); 1104 if (r == 0) { 1105 r = -ETIMEDOUT; 1106 goto err2; 1107 } else if (r < 0) { 1108 goto err2; 1109 } 1110 1111 tmp = adev->wb.wb[index]; 1112 if (tmp == 0xDEADBEEF) 1113 r = 0; 1114 else 1115 r = -EINVAL; 1116 1117 err2: 1118 amdgpu_ib_free(adev, &ib, NULL); 1119 dma_fence_put(f); 1120 err1: 1121 amdgpu_device_wb_free(adev, index); 1122 return r; 1123 } 1124 1125 1126 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1127 { 1128 release_firmware(adev->gfx.pfp_fw); 1129 adev->gfx.pfp_fw = NULL; 1130 release_firmware(adev->gfx.me_fw); 1131 adev->gfx.me_fw = NULL; 1132 release_firmware(adev->gfx.ce_fw); 1133 adev->gfx.ce_fw = NULL; 1134 release_firmware(adev->gfx.rlc_fw); 1135 adev->gfx.rlc_fw = NULL; 1136 release_firmware(adev->gfx.mec_fw); 1137 adev->gfx.mec_fw = NULL; 1138 release_firmware(adev->gfx.mec2_fw); 1139 adev->gfx.mec2_fw = NULL; 1140 1141 kfree(adev->gfx.rlc.register_list_format); 1142 } 1143 1144 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 1145 { 1146 const struct rlc_firmware_header_v2_1 *rlc_hdr; 1147 1148 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1149 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 1150 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 1151 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 1152 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 1153 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 1154 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 1155 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 1156 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 1157 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 1158 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 1159 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 1160 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 1161 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 1162 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 1163 } 1164 1165 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1166 { 1167 adev->gfx.me_fw_write_wait = false; 1168 adev->gfx.mec_fw_write_wait = false; 1169 1170 if ((adev->asic_type != CHIP_ARCTURUS) && 1171 ((adev->gfx.mec_fw_version < 0x000001a5) || 1172 (adev->gfx.mec_feature_version < 46) || 1173 (adev->gfx.pfp_fw_version < 0x000000b7) || 1174 (adev->gfx.pfp_feature_version < 46))) 1175 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1176 1177 switch (adev->asic_type) { 1178 case CHIP_VEGA10: 1179 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1180 (adev->gfx.me_feature_version >= 42) && 1181 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1182 (adev->gfx.pfp_feature_version >= 42)) 1183 adev->gfx.me_fw_write_wait = true; 1184 1185 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1186 (adev->gfx.mec_feature_version >= 42)) 1187 adev->gfx.mec_fw_write_wait = true; 1188 break; 1189 case CHIP_VEGA12: 1190 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1191 (adev->gfx.me_feature_version >= 44) && 1192 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1193 (adev->gfx.pfp_feature_version >= 44)) 1194 adev->gfx.me_fw_write_wait = true; 1195 1196 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1197 (adev->gfx.mec_feature_version >= 44)) 1198 adev->gfx.mec_fw_write_wait = true; 1199 break; 1200 case CHIP_VEGA20: 1201 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1202 (adev->gfx.me_feature_version >= 44) && 1203 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1204 (adev->gfx.pfp_feature_version >= 44)) 1205 adev->gfx.me_fw_write_wait = true; 1206 1207 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1208 (adev->gfx.mec_feature_version >= 44)) 1209 adev->gfx.mec_fw_write_wait = true; 1210 break; 1211 case CHIP_RAVEN: 1212 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1213 (adev->gfx.me_feature_version >= 42) && 1214 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1215 (adev->gfx.pfp_feature_version >= 42)) 1216 adev->gfx.me_fw_write_wait = true; 1217 1218 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1219 (adev->gfx.mec_feature_version >= 42)) 1220 adev->gfx.mec_fw_write_wait = true; 1221 break; 1222 default: 1223 adev->gfx.me_fw_write_wait = true; 1224 adev->gfx.mec_fw_write_wait = true; 1225 break; 1226 } 1227 } 1228 1229 struct amdgpu_gfxoff_quirk { 1230 u16 chip_vendor; 1231 u16 chip_device; 1232 u16 subsys_vendor; 1233 u16 subsys_device; 1234 u8 revision; 1235 }; 1236 1237 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1238 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1239 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1240 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1241 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1242 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1243 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1244 { 0, 0, 0, 0, 0 }, 1245 }; 1246 1247 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1248 { 1249 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1250 1251 while (p && p->chip_device != 0) { 1252 if (pdev->vendor == p->chip_vendor && 1253 pdev->device == p->chip_device && 1254 pdev->subsystem_vendor == p->subsys_vendor && 1255 pdev->subsystem_device == p->subsys_device && 1256 pdev->revision == p->revision) { 1257 return true; 1258 } 1259 ++p; 1260 } 1261 return false; 1262 } 1263 1264 static bool is_raven_kicker(struct amdgpu_device *adev) 1265 { 1266 if (adev->pm.fw_version >= 0x41e2b) 1267 return true; 1268 else 1269 return false; 1270 } 1271 1272 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1273 { 1274 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1275 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1276 1277 switch (adev->asic_type) { 1278 case CHIP_VEGA10: 1279 case CHIP_VEGA12: 1280 case CHIP_VEGA20: 1281 break; 1282 case CHIP_RAVEN: 1283 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1284 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1285 ((!is_raven_kicker(adev) && 1286 adev->gfx.rlc_fw_version < 531) || 1287 (adev->gfx.rlc_feature_version < 1) || 1288 !adev->gfx.rlc.is_rlc_v2_1)) 1289 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1290 1291 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1292 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1293 AMD_PG_SUPPORT_CP | 1294 AMD_PG_SUPPORT_RLC_SMU_HS; 1295 break; 1296 case CHIP_RENOIR: 1297 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1298 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1299 AMD_PG_SUPPORT_CP | 1300 AMD_PG_SUPPORT_RLC_SMU_HS; 1301 break; 1302 default: 1303 break; 1304 } 1305 } 1306 1307 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1308 const char *chip_name) 1309 { 1310 char fw_name[30]; 1311 int err; 1312 struct amdgpu_firmware_info *info = NULL; 1313 const struct common_firmware_header *header = NULL; 1314 const struct gfx_firmware_header_v1_0 *cp_hdr; 1315 1316 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1317 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 1318 if (err) 1319 goto out; 1320 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 1321 if (err) 1322 goto out; 1323 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1324 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1325 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1326 1327 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1328 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 1329 if (err) 1330 goto out; 1331 err = amdgpu_ucode_validate(adev->gfx.me_fw); 1332 if (err) 1333 goto out; 1334 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1335 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1336 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1337 1338 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1339 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 1340 if (err) 1341 goto out; 1342 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 1343 if (err) 1344 goto out; 1345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1346 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1347 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1348 1349 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1350 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 1351 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 1352 info->fw = adev->gfx.pfp_fw; 1353 header = (const struct common_firmware_header *)info->fw->data; 1354 adev->firmware.fw_size += 1355 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1356 1357 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 1358 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 1359 info->fw = adev->gfx.me_fw; 1360 header = (const struct common_firmware_header *)info->fw->data; 1361 adev->firmware.fw_size += 1362 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1363 1364 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 1365 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 1366 info->fw = adev->gfx.ce_fw; 1367 header = (const struct common_firmware_header *)info->fw->data; 1368 adev->firmware.fw_size += 1369 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1370 } 1371 1372 out: 1373 if (err) { 1374 dev_err(adev->dev, 1375 "gfx9: Failed to load firmware \"%s\"\n", 1376 fw_name); 1377 release_firmware(adev->gfx.pfp_fw); 1378 adev->gfx.pfp_fw = NULL; 1379 release_firmware(adev->gfx.me_fw); 1380 adev->gfx.me_fw = NULL; 1381 release_firmware(adev->gfx.ce_fw); 1382 adev->gfx.ce_fw = NULL; 1383 } 1384 return err; 1385 } 1386 1387 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1388 const char *chip_name) 1389 { 1390 char fw_name[30]; 1391 int err; 1392 struct amdgpu_firmware_info *info = NULL; 1393 const struct common_firmware_header *header = NULL; 1394 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1395 unsigned int *tmp = NULL; 1396 unsigned int i = 0; 1397 uint16_t version_major; 1398 uint16_t version_minor; 1399 uint32_t smu_version; 1400 1401 /* 1402 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1403 * instead of picasso_rlc.bin. 1404 * Judgment method: 1405 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1406 * or revision >= 0xD8 && revision <= 0xDF 1407 * otherwise is PCO FP5 1408 */ 1409 if (!strcmp(chip_name, "picasso") && 1410 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1411 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1412 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1413 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1414 (smu_version >= 0x41e2b)) 1415 /** 1416 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1417 */ 1418 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1419 else 1420 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1421 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1422 if (err) 1423 goto out; 1424 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1425 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1426 1427 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1428 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1429 if (version_major == 2 && version_minor == 1) 1430 adev->gfx.rlc.is_rlc_v2_1 = true; 1431 1432 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 1433 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 1434 adev->gfx.rlc.save_and_restore_offset = 1435 le32_to_cpu(rlc_hdr->save_and_restore_offset); 1436 adev->gfx.rlc.clear_state_descriptor_offset = 1437 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 1438 adev->gfx.rlc.avail_scratch_ram_locations = 1439 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 1440 adev->gfx.rlc.reg_restore_list_size = 1441 le32_to_cpu(rlc_hdr->reg_restore_list_size); 1442 adev->gfx.rlc.reg_list_format_start = 1443 le32_to_cpu(rlc_hdr->reg_list_format_start); 1444 adev->gfx.rlc.reg_list_format_separate_start = 1445 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 1446 adev->gfx.rlc.starting_offsets_start = 1447 le32_to_cpu(rlc_hdr->starting_offsets_start); 1448 adev->gfx.rlc.reg_list_format_size_bytes = 1449 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 1450 adev->gfx.rlc.reg_list_size_bytes = 1451 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 1452 adev->gfx.rlc.register_list_format = 1453 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 1454 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 1455 if (!adev->gfx.rlc.register_list_format) { 1456 err = -ENOMEM; 1457 goto out; 1458 } 1459 1460 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1461 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 1462 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 1463 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 1464 1465 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 1466 1467 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1468 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 1469 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 1470 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 1471 1472 if (adev->gfx.rlc.is_rlc_v2_1) 1473 gfx_v9_0_init_rlc_ext_microcode(adev); 1474 1475 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1476 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 1477 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 1478 info->fw = adev->gfx.rlc_fw; 1479 header = (const struct common_firmware_header *)info->fw->data; 1480 adev->firmware.fw_size += 1481 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1482 1483 if (adev->gfx.rlc.is_rlc_v2_1 && 1484 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 1485 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 1486 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 1487 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 1488 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 1489 info->fw = adev->gfx.rlc_fw; 1490 adev->firmware.fw_size += 1491 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 1492 1493 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 1494 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 1495 info->fw = adev->gfx.rlc_fw; 1496 adev->firmware.fw_size += 1497 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 1498 1499 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 1500 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 1501 info->fw = adev->gfx.rlc_fw; 1502 adev->firmware.fw_size += 1503 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 1504 } 1505 } 1506 1507 out: 1508 if (err) { 1509 dev_err(adev->dev, 1510 "gfx9: Failed to load firmware \"%s\"\n", 1511 fw_name); 1512 release_firmware(adev->gfx.rlc_fw); 1513 adev->gfx.rlc_fw = NULL; 1514 } 1515 return err; 1516 } 1517 1518 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1519 { 1520 if (adev->asic_type == CHIP_ARCTURUS || 1521 adev->asic_type == CHIP_RENOIR) 1522 return false; 1523 1524 return true; 1525 } 1526 1527 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1528 const char *chip_name) 1529 { 1530 char fw_name[30]; 1531 int err; 1532 struct amdgpu_firmware_info *info = NULL; 1533 const struct common_firmware_header *header = NULL; 1534 const struct gfx_firmware_header_v1_0 *cp_hdr; 1535 1536 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1537 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1538 if (err) 1539 goto out; 1540 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1541 if (err) 1542 goto out; 1543 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1544 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1545 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1546 1547 1548 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1549 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1550 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1551 if (!err) { 1552 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1553 if (err) 1554 goto out; 1555 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1556 adev->gfx.mec2_fw->data; 1557 adev->gfx.mec2_fw_version = 1558 le32_to_cpu(cp_hdr->header.ucode_version); 1559 adev->gfx.mec2_feature_version = 1560 le32_to_cpu(cp_hdr->ucode_feature_version); 1561 } else { 1562 err = 0; 1563 adev->gfx.mec2_fw = NULL; 1564 } 1565 } 1566 1567 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1568 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 1569 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 1570 info->fw = adev->gfx.mec_fw; 1571 header = (const struct common_firmware_header *)info->fw->data; 1572 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1573 adev->firmware.fw_size += 1574 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1575 1576 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 1577 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 1578 info->fw = adev->gfx.mec_fw; 1579 adev->firmware.fw_size += 1580 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1581 1582 if (adev->gfx.mec2_fw) { 1583 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 1584 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 1585 info->fw = adev->gfx.mec2_fw; 1586 header = (const struct common_firmware_header *)info->fw->data; 1587 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1588 adev->firmware.fw_size += 1589 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1590 1591 /* TODO: Determine if MEC2 JT FW loading can be removed 1592 for all GFX V9 asic and above */ 1593 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1594 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 1595 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 1596 info->fw = adev->gfx.mec2_fw; 1597 adev->firmware.fw_size += 1598 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 1599 PAGE_SIZE); 1600 } 1601 } 1602 } 1603 1604 out: 1605 gfx_v9_0_check_if_need_gfxoff(adev); 1606 gfx_v9_0_check_fw_write_wait(adev); 1607 if (err) { 1608 dev_err(adev->dev, 1609 "gfx9: Failed to load firmware \"%s\"\n", 1610 fw_name); 1611 release_firmware(adev->gfx.mec_fw); 1612 adev->gfx.mec_fw = NULL; 1613 release_firmware(adev->gfx.mec2_fw); 1614 adev->gfx.mec2_fw = NULL; 1615 } 1616 return err; 1617 } 1618 1619 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1620 { 1621 const char *chip_name; 1622 int r; 1623 1624 DRM_DEBUG("\n"); 1625 1626 switch (adev->asic_type) { 1627 case CHIP_VEGA10: 1628 chip_name = "vega10"; 1629 break; 1630 case CHIP_VEGA12: 1631 chip_name = "vega12"; 1632 break; 1633 case CHIP_VEGA20: 1634 chip_name = "vega20"; 1635 break; 1636 case CHIP_RAVEN: 1637 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1638 chip_name = "raven2"; 1639 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1640 chip_name = "picasso"; 1641 else 1642 chip_name = "raven"; 1643 break; 1644 case CHIP_ARCTURUS: 1645 chip_name = "arcturus"; 1646 break; 1647 case CHIP_RENOIR: 1648 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1649 chip_name = "renoir"; 1650 else 1651 chip_name = "green_sardine"; 1652 break; 1653 default: 1654 BUG(); 1655 } 1656 1657 /* No CPG in Arcturus */ 1658 if (adev->gfx.num_gfx_rings) { 1659 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); 1660 if (r) 1661 return r; 1662 } 1663 1664 r = gfx_v9_0_init_rlc_microcode(adev, chip_name); 1665 if (r) 1666 return r; 1667 1668 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); 1669 if (r) 1670 return r; 1671 1672 return r; 1673 } 1674 1675 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1676 { 1677 u32 count = 0; 1678 const struct cs_section_def *sect = NULL; 1679 const struct cs_extent_def *ext = NULL; 1680 1681 /* begin clear state */ 1682 count += 2; 1683 /* context control state */ 1684 count += 3; 1685 1686 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1687 for (ext = sect->section; ext->extent != NULL; ++ext) { 1688 if (sect->id == SECT_CONTEXT) 1689 count += 2 + ext->reg_count; 1690 else 1691 return 0; 1692 } 1693 } 1694 1695 /* end clear state */ 1696 count += 2; 1697 /* clear state */ 1698 count += 2; 1699 1700 return count; 1701 } 1702 1703 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1704 volatile u32 *buffer) 1705 { 1706 u32 count = 0, i; 1707 const struct cs_section_def *sect = NULL; 1708 const struct cs_extent_def *ext = NULL; 1709 1710 if (adev->gfx.rlc.cs_data == NULL) 1711 return; 1712 if (buffer == NULL) 1713 return; 1714 1715 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1716 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1717 1718 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1719 buffer[count++] = cpu_to_le32(0x80000000); 1720 buffer[count++] = cpu_to_le32(0x80000000); 1721 1722 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1723 for (ext = sect->section; ext->extent != NULL; ++ext) { 1724 if (sect->id == SECT_CONTEXT) { 1725 buffer[count++] = 1726 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1727 buffer[count++] = cpu_to_le32(ext->reg_index - 1728 PACKET3_SET_CONTEXT_REG_START); 1729 for (i = 0; i < ext->reg_count; i++) 1730 buffer[count++] = cpu_to_le32(ext->extent[i]); 1731 } else { 1732 return; 1733 } 1734 } 1735 } 1736 1737 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1738 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1739 1740 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1741 buffer[count++] = cpu_to_le32(0); 1742 } 1743 1744 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1745 { 1746 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1747 uint32_t pg_always_on_cu_num = 2; 1748 uint32_t always_on_cu_num; 1749 uint32_t i, j, k; 1750 uint32_t mask, cu_bitmap, counter; 1751 1752 if (adev->flags & AMD_IS_APU) 1753 always_on_cu_num = 4; 1754 else if (adev->asic_type == CHIP_VEGA12) 1755 always_on_cu_num = 8; 1756 else 1757 always_on_cu_num = 12; 1758 1759 mutex_lock(&adev->grbm_idx_mutex); 1760 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1761 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1762 mask = 1; 1763 cu_bitmap = 0; 1764 counter = 0; 1765 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1766 1767 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1768 if (cu_info->bitmap[i][j] & mask) { 1769 if (counter == pg_always_on_cu_num) 1770 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1771 if (counter < always_on_cu_num) 1772 cu_bitmap |= mask; 1773 else 1774 break; 1775 counter++; 1776 } 1777 mask <<= 1; 1778 } 1779 1780 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1781 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1782 } 1783 } 1784 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1785 mutex_unlock(&adev->grbm_idx_mutex); 1786 } 1787 1788 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1789 { 1790 uint32_t data; 1791 1792 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1793 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1794 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1795 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1796 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1797 1798 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1799 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1800 1801 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1802 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1803 1804 mutex_lock(&adev->grbm_idx_mutex); 1805 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1806 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1807 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1808 1809 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1810 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1811 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1812 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1813 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1814 1815 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1816 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1817 data &= 0x0000FFFF; 1818 data |= 0x00C00000; 1819 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1820 1821 /* 1822 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1823 * programmed in gfx_v9_0_init_always_on_cu_mask() 1824 */ 1825 1826 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1827 * but used for RLC_LB_CNTL configuration */ 1828 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1829 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1830 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1831 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1832 mutex_unlock(&adev->grbm_idx_mutex); 1833 1834 gfx_v9_0_init_always_on_cu_mask(adev); 1835 } 1836 1837 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1838 { 1839 uint32_t data; 1840 1841 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1842 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1843 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1844 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1845 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1846 1847 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1848 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1849 1850 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1851 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1852 1853 mutex_lock(&adev->grbm_idx_mutex); 1854 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1855 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1856 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1857 1858 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1859 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1860 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1861 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1862 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1863 1864 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1865 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1866 data &= 0x0000FFFF; 1867 data |= 0x00C00000; 1868 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1869 1870 /* 1871 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1872 * programmed in gfx_v9_0_init_always_on_cu_mask() 1873 */ 1874 1875 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1876 * but used for RLC_LB_CNTL configuration */ 1877 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1878 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1879 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1880 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1881 mutex_unlock(&adev->grbm_idx_mutex); 1882 1883 gfx_v9_0_init_always_on_cu_mask(adev); 1884 } 1885 1886 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1887 { 1888 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1889 } 1890 1891 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1892 { 1893 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1894 return 5; 1895 else 1896 return 4; 1897 } 1898 1899 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1900 { 1901 const struct cs_section_def *cs_data; 1902 int r; 1903 1904 adev->gfx.rlc.cs_data = gfx9_cs_data; 1905 1906 cs_data = adev->gfx.rlc.cs_data; 1907 1908 if (cs_data) { 1909 /* init clear state block */ 1910 r = amdgpu_gfx_rlc_init_csb(adev); 1911 if (r) 1912 return r; 1913 } 1914 1915 if (adev->flags & AMD_IS_APU) { 1916 /* TODO: double check the cp_table_size for RV */ 1917 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1918 r = amdgpu_gfx_rlc_init_cpt(adev); 1919 if (r) 1920 return r; 1921 } 1922 1923 switch (adev->asic_type) { 1924 case CHIP_RAVEN: 1925 gfx_v9_0_init_lbpw(adev); 1926 break; 1927 case CHIP_VEGA20: 1928 gfx_v9_4_init_lbpw(adev); 1929 break; 1930 default: 1931 break; 1932 } 1933 1934 /* init spm vmid with 0xf */ 1935 if (adev->gfx.rlc.funcs->update_spm_vmid) 1936 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1937 1938 return 0; 1939 } 1940 1941 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1942 { 1943 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1944 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1945 } 1946 1947 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1948 { 1949 int r; 1950 u32 *hpd; 1951 const __le32 *fw_data; 1952 unsigned fw_size; 1953 u32 *fw; 1954 size_t mec_hpd_size; 1955 1956 const struct gfx_firmware_header_v1_0 *mec_hdr; 1957 1958 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1959 1960 /* take ownership of the relevant compute queues */ 1961 amdgpu_gfx_compute_queue_acquire(adev); 1962 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1963 if (mec_hpd_size) { 1964 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1965 AMDGPU_GEM_DOMAIN_VRAM, 1966 &adev->gfx.mec.hpd_eop_obj, 1967 &adev->gfx.mec.hpd_eop_gpu_addr, 1968 (void **)&hpd); 1969 if (r) { 1970 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1971 gfx_v9_0_mec_fini(adev); 1972 return r; 1973 } 1974 1975 memset(hpd, 0, mec_hpd_size); 1976 1977 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1978 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1979 } 1980 1981 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1982 1983 fw_data = (const __le32 *) 1984 (adev->gfx.mec_fw->data + 1985 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1986 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1987 1988 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1989 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1990 &adev->gfx.mec.mec_fw_obj, 1991 &adev->gfx.mec.mec_fw_gpu_addr, 1992 (void **)&fw); 1993 if (r) { 1994 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1995 gfx_v9_0_mec_fini(adev); 1996 return r; 1997 } 1998 1999 memcpy(fw, fw_data, fw_size); 2000 2001 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2002 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2003 2004 return 0; 2005 } 2006 2007 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2008 { 2009 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 2010 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2011 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2012 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2013 (SQ_IND_INDEX__FORCE_READ_MASK)); 2014 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 2015 } 2016 2017 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2018 uint32_t wave, uint32_t thread, 2019 uint32_t regno, uint32_t num, uint32_t *out) 2020 { 2021 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 2022 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2023 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2024 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2025 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2026 (SQ_IND_INDEX__FORCE_READ_MASK) | 2027 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2028 while (num--) 2029 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 2030 } 2031 2032 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2033 { 2034 /* type 1 wave data */ 2035 dst[(*no_fields)++] = 1; 2036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2050 } 2051 2052 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 2053 uint32_t wave, uint32_t start, 2054 uint32_t size, uint32_t *dst) 2055 { 2056 wave_read_regs( 2057 adev, simd, wave, 0, 2058 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 2059 } 2060 2061 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 2062 uint32_t wave, uint32_t thread, 2063 uint32_t start, uint32_t size, 2064 uint32_t *dst) 2065 { 2066 wave_read_regs( 2067 adev, simd, wave, thread, 2068 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 2069 } 2070 2071 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 2072 u32 me, u32 pipe, u32 q, u32 vm) 2073 { 2074 soc15_grbm_select(adev, me, pipe, q, vm); 2075 } 2076 2077 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 2078 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2079 .select_se_sh = &gfx_v9_0_select_se_sh, 2080 .read_wave_data = &gfx_v9_0_read_wave_data, 2081 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2082 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2083 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2084 .ras_error_inject = &gfx_v9_0_ras_error_inject, 2085 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 2086 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 2087 }; 2088 2089 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { 2090 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2091 .select_se_sh = &gfx_v9_0_select_se_sh, 2092 .read_wave_data = &gfx_v9_0_read_wave_data, 2093 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2094 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2095 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2096 .ras_error_inject = &gfx_v9_4_ras_error_inject, 2097 .query_ras_error_count = &gfx_v9_4_query_ras_error_count, 2098 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count, 2099 .query_ras_error_status = &gfx_v9_4_query_ras_error_status, 2100 }; 2101 2102 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 2103 { 2104 u32 gb_addr_config; 2105 int err; 2106 2107 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 2108 2109 switch (adev->asic_type) { 2110 case CHIP_VEGA10: 2111 adev->gfx.config.max_hw_contexts = 8; 2112 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2113 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2114 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2115 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2116 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 2117 break; 2118 case CHIP_VEGA12: 2119 adev->gfx.config.max_hw_contexts = 8; 2120 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2121 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2122 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2123 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2124 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 2125 DRM_INFO("fix gfx.config for vega12\n"); 2126 break; 2127 case CHIP_VEGA20: 2128 adev->gfx.config.max_hw_contexts = 8; 2129 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2130 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2131 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2132 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2133 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2134 gb_addr_config &= ~0xf3e777ff; 2135 gb_addr_config |= 0x22014042; 2136 /* check vbios table if gpu info is not available */ 2137 err = amdgpu_atomfirmware_get_gfx_info(adev); 2138 if (err) 2139 return err; 2140 break; 2141 case CHIP_RAVEN: 2142 adev->gfx.config.max_hw_contexts = 8; 2143 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2144 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2145 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2146 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2147 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 2148 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 2149 else 2150 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 2151 break; 2152 case CHIP_ARCTURUS: 2153 adev->gfx.funcs = &gfx_v9_4_gfx_funcs; 2154 adev->gfx.config.max_hw_contexts = 8; 2155 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2156 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2157 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2158 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2159 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2160 gb_addr_config &= ~0xf3e777ff; 2161 gb_addr_config |= 0x22014042; 2162 break; 2163 case CHIP_RENOIR: 2164 adev->gfx.config.max_hw_contexts = 8; 2165 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2166 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2167 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 2168 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2169 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2170 gb_addr_config &= ~0xf3e777ff; 2171 gb_addr_config |= 0x22010042; 2172 break; 2173 default: 2174 BUG(); 2175 break; 2176 } 2177 2178 adev->gfx.config.gb_addr_config = gb_addr_config; 2179 2180 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2181 REG_GET_FIELD( 2182 adev->gfx.config.gb_addr_config, 2183 GB_ADDR_CONFIG, 2184 NUM_PIPES); 2185 2186 adev->gfx.config.max_tile_pipes = 2187 adev->gfx.config.gb_addr_config_fields.num_pipes; 2188 2189 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2190 REG_GET_FIELD( 2191 adev->gfx.config.gb_addr_config, 2192 GB_ADDR_CONFIG, 2193 NUM_BANKS); 2194 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2195 REG_GET_FIELD( 2196 adev->gfx.config.gb_addr_config, 2197 GB_ADDR_CONFIG, 2198 MAX_COMPRESSED_FRAGS); 2199 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2200 REG_GET_FIELD( 2201 adev->gfx.config.gb_addr_config, 2202 GB_ADDR_CONFIG, 2203 NUM_RB_PER_SE); 2204 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2205 REG_GET_FIELD( 2206 adev->gfx.config.gb_addr_config, 2207 GB_ADDR_CONFIG, 2208 NUM_SHADER_ENGINES); 2209 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2210 REG_GET_FIELD( 2211 adev->gfx.config.gb_addr_config, 2212 GB_ADDR_CONFIG, 2213 PIPE_INTERLEAVE_SIZE)); 2214 2215 return 0; 2216 } 2217 2218 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2219 int mec, int pipe, int queue) 2220 { 2221 unsigned irq_type; 2222 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2223 unsigned int hw_prio; 2224 2225 ring = &adev->gfx.compute_ring[ring_id]; 2226 2227 /* mec0 is me1 */ 2228 ring->me = mec + 1; 2229 ring->pipe = pipe; 2230 ring->queue = queue; 2231 2232 ring->ring_obj = NULL; 2233 ring->use_doorbell = true; 2234 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2235 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2236 + (ring_id * GFX9_MEC_HPD_SIZE); 2237 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2238 2239 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2240 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2241 + ring->pipe; 2242 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2243 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 2244 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2245 return amdgpu_ring_init(adev, ring, 1024, 2246 &adev->gfx.eop_irq, irq_type, hw_prio); 2247 } 2248 2249 static int gfx_v9_0_sw_init(void *handle) 2250 { 2251 int i, j, k, r, ring_id; 2252 struct amdgpu_ring *ring; 2253 struct amdgpu_kiq *kiq; 2254 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2255 2256 switch (adev->asic_type) { 2257 case CHIP_VEGA10: 2258 case CHIP_VEGA12: 2259 case CHIP_VEGA20: 2260 case CHIP_RAVEN: 2261 case CHIP_ARCTURUS: 2262 case CHIP_RENOIR: 2263 adev->gfx.mec.num_mec = 2; 2264 break; 2265 default: 2266 adev->gfx.mec.num_mec = 1; 2267 break; 2268 } 2269 2270 adev->gfx.mec.num_pipe_per_mec = 4; 2271 adev->gfx.mec.num_queue_per_pipe = 8; 2272 2273 /* EOP Event */ 2274 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2275 if (r) 2276 return r; 2277 2278 /* Privileged reg */ 2279 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2280 &adev->gfx.priv_reg_irq); 2281 if (r) 2282 return r; 2283 2284 /* Privileged inst */ 2285 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2286 &adev->gfx.priv_inst_irq); 2287 if (r) 2288 return r; 2289 2290 /* ECC error */ 2291 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2292 &adev->gfx.cp_ecc_error_irq); 2293 if (r) 2294 return r; 2295 2296 /* FUE error */ 2297 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2298 &adev->gfx.cp_ecc_error_irq); 2299 if (r) 2300 return r; 2301 2302 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2303 2304 gfx_v9_0_scratch_init(adev); 2305 2306 r = gfx_v9_0_init_microcode(adev); 2307 if (r) { 2308 DRM_ERROR("Failed to load gfx firmware!\n"); 2309 return r; 2310 } 2311 2312 r = adev->gfx.rlc.funcs->init(adev); 2313 if (r) { 2314 DRM_ERROR("Failed to init rlc BOs!\n"); 2315 return r; 2316 } 2317 2318 r = gfx_v9_0_mec_init(adev); 2319 if (r) { 2320 DRM_ERROR("Failed to init MEC BOs!\n"); 2321 return r; 2322 } 2323 2324 /* set up the gfx ring */ 2325 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2326 ring = &adev->gfx.gfx_ring[i]; 2327 ring->ring_obj = NULL; 2328 if (!i) 2329 sprintf(ring->name, "gfx"); 2330 else 2331 sprintf(ring->name, "gfx_%d", i); 2332 ring->use_doorbell = true; 2333 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2334 r = amdgpu_ring_init(adev, ring, 1024, 2335 &adev->gfx.eop_irq, 2336 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2337 AMDGPU_RING_PRIO_DEFAULT); 2338 if (r) 2339 return r; 2340 } 2341 2342 /* set up the compute queues - allocate horizontally across pipes */ 2343 ring_id = 0; 2344 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2345 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2346 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2347 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2348 continue; 2349 2350 r = gfx_v9_0_compute_ring_init(adev, 2351 ring_id, 2352 i, k, j); 2353 if (r) 2354 return r; 2355 2356 ring_id++; 2357 } 2358 } 2359 } 2360 2361 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2362 if (r) { 2363 DRM_ERROR("Failed to init KIQ BOs!\n"); 2364 return r; 2365 } 2366 2367 kiq = &adev->gfx.kiq; 2368 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2369 if (r) 2370 return r; 2371 2372 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2373 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2374 if (r) 2375 return r; 2376 2377 adev->gfx.ce_ram_size = 0x8000; 2378 2379 r = gfx_v9_0_gpu_early_init(adev); 2380 if (r) 2381 return r; 2382 2383 return 0; 2384 } 2385 2386 2387 static int gfx_v9_0_sw_fini(void *handle) 2388 { 2389 int i; 2390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2391 2392 amdgpu_gfx_ras_fini(adev); 2393 2394 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2395 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2396 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2397 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2398 2399 amdgpu_gfx_mqd_sw_fini(adev); 2400 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2401 amdgpu_gfx_kiq_fini(adev); 2402 2403 gfx_v9_0_mec_fini(adev); 2404 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 2405 if (adev->flags & AMD_IS_APU) { 2406 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2407 &adev->gfx.rlc.cp_table_gpu_addr, 2408 (void **)&adev->gfx.rlc.cp_table_ptr); 2409 } 2410 gfx_v9_0_free_microcode(adev); 2411 2412 return 0; 2413 } 2414 2415 2416 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2417 { 2418 /* TODO */ 2419 } 2420 2421 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2422 u32 instance) 2423 { 2424 u32 data; 2425 2426 if (instance == 0xffffffff) 2427 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2428 else 2429 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2430 2431 if (se_num == 0xffffffff) 2432 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2433 else 2434 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2435 2436 if (sh_num == 0xffffffff) 2437 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2438 else 2439 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2440 2441 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2442 } 2443 2444 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2445 { 2446 u32 data, mask; 2447 2448 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2449 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2450 2451 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2452 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2453 2454 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2455 adev->gfx.config.max_sh_per_se); 2456 2457 return (~data) & mask; 2458 } 2459 2460 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2461 { 2462 int i, j; 2463 u32 data; 2464 u32 active_rbs = 0; 2465 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2466 adev->gfx.config.max_sh_per_se; 2467 2468 mutex_lock(&adev->grbm_idx_mutex); 2469 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2470 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2471 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2472 data = gfx_v9_0_get_rb_active_bitmap(adev); 2473 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2474 rb_bitmap_width_per_sh); 2475 } 2476 } 2477 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2478 mutex_unlock(&adev->grbm_idx_mutex); 2479 2480 adev->gfx.config.backend_enable_mask = active_rbs; 2481 adev->gfx.config.num_rbs = hweight32(active_rbs); 2482 } 2483 2484 #define DEFAULT_SH_MEM_BASES (0x6000) 2485 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2486 { 2487 int i; 2488 uint32_t sh_mem_config; 2489 uint32_t sh_mem_bases; 2490 2491 /* 2492 * Configure apertures: 2493 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2494 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2495 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2496 */ 2497 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2498 2499 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2500 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2501 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2502 2503 mutex_lock(&adev->srbm_mutex); 2504 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2505 soc15_grbm_select(adev, 0, 0, 0, i); 2506 /* CP and shaders */ 2507 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2508 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2509 } 2510 soc15_grbm_select(adev, 0, 0, 0, 0); 2511 mutex_unlock(&adev->srbm_mutex); 2512 2513 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2514 acccess. These should be enabled by FW for target VMIDs. */ 2515 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2516 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2517 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2518 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2519 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2520 } 2521 } 2522 2523 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2524 { 2525 int vmid; 2526 2527 /* 2528 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2529 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2530 * the driver can enable them for graphics. VMID0 should maintain 2531 * access so that HWS firmware can save/restore entries. 2532 */ 2533 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2534 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2535 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2536 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2537 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2538 } 2539 } 2540 2541 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2542 { 2543 uint32_t tmp; 2544 2545 switch (adev->asic_type) { 2546 case CHIP_ARCTURUS: 2547 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2548 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2549 DISABLE_BARRIER_WAITCNT, 1); 2550 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2551 break; 2552 default: 2553 break; 2554 } 2555 } 2556 2557 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2558 { 2559 u32 tmp; 2560 int i; 2561 2562 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2563 2564 gfx_v9_0_tiling_mode_table_init(adev); 2565 2566 gfx_v9_0_setup_rb(adev); 2567 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2568 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2569 2570 /* XXX SH_MEM regs */ 2571 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2572 mutex_lock(&adev->srbm_mutex); 2573 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2574 soc15_grbm_select(adev, 0, 0, 0, i); 2575 /* CP and shaders */ 2576 if (i == 0) { 2577 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2578 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2579 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2580 !!adev->gmc.noretry); 2581 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2582 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2583 } else { 2584 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2585 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2586 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2587 !!adev->gmc.noretry); 2588 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2589 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2590 (adev->gmc.private_aperture_start >> 48)); 2591 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2592 (adev->gmc.shared_aperture_start >> 48)); 2593 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2594 } 2595 } 2596 soc15_grbm_select(adev, 0, 0, 0, 0); 2597 2598 mutex_unlock(&adev->srbm_mutex); 2599 2600 gfx_v9_0_init_compute_vmid(adev); 2601 gfx_v9_0_init_gds_vmid(adev); 2602 gfx_v9_0_init_sq_config(adev); 2603 } 2604 2605 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2606 { 2607 u32 i, j, k; 2608 u32 mask; 2609 2610 mutex_lock(&adev->grbm_idx_mutex); 2611 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2612 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2613 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2614 for (k = 0; k < adev->usec_timeout; k++) { 2615 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2616 break; 2617 udelay(1); 2618 } 2619 if (k == adev->usec_timeout) { 2620 gfx_v9_0_select_se_sh(adev, 0xffffffff, 2621 0xffffffff, 0xffffffff); 2622 mutex_unlock(&adev->grbm_idx_mutex); 2623 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2624 i, j); 2625 return; 2626 } 2627 } 2628 } 2629 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2630 mutex_unlock(&adev->grbm_idx_mutex); 2631 2632 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2633 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2634 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2635 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2636 for (k = 0; k < adev->usec_timeout; k++) { 2637 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2638 break; 2639 udelay(1); 2640 } 2641 } 2642 2643 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2644 bool enable) 2645 { 2646 u32 tmp; 2647 2648 /* don't toggle interrupts that are only applicable 2649 * to me0 pipe0 on AISCs that have me0 removed */ 2650 if (!adev->gfx.num_gfx_rings) 2651 return; 2652 2653 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2654 2655 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2657 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2658 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2659 2660 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2661 } 2662 2663 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2664 { 2665 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2666 /* csib */ 2667 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2668 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2669 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2670 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2671 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2672 adev->gfx.rlc.clear_state_size); 2673 } 2674 2675 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2676 int indirect_offset, 2677 int list_size, 2678 int *unique_indirect_regs, 2679 int unique_indirect_reg_count, 2680 int *indirect_start_offsets, 2681 int *indirect_start_offsets_count, 2682 int max_start_offsets_count) 2683 { 2684 int idx; 2685 2686 for (; indirect_offset < list_size; indirect_offset++) { 2687 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2688 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2689 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2690 2691 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2692 indirect_offset += 2; 2693 2694 /* look for the matching indice */ 2695 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2696 if (unique_indirect_regs[idx] == 2697 register_list_format[indirect_offset] || 2698 !unique_indirect_regs[idx]) 2699 break; 2700 } 2701 2702 BUG_ON(idx >= unique_indirect_reg_count); 2703 2704 if (!unique_indirect_regs[idx]) 2705 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2706 2707 indirect_offset++; 2708 } 2709 } 2710 } 2711 2712 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2713 { 2714 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2715 int unique_indirect_reg_count = 0; 2716 2717 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2718 int indirect_start_offsets_count = 0; 2719 2720 int list_size = 0; 2721 int i = 0, j = 0; 2722 u32 tmp = 0; 2723 2724 u32 *register_list_format = 2725 kmemdup(adev->gfx.rlc.register_list_format, 2726 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2727 if (!register_list_format) 2728 return -ENOMEM; 2729 2730 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2731 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2732 gfx_v9_1_parse_ind_reg_list(register_list_format, 2733 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2734 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2735 unique_indirect_regs, 2736 unique_indirect_reg_count, 2737 indirect_start_offsets, 2738 &indirect_start_offsets_count, 2739 ARRAY_SIZE(indirect_start_offsets)); 2740 2741 /* enable auto inc in case it is disabled */ 2742 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2743 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2744 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2745 2746 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2748 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2749 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2750 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2751 adev->gfx.rlc.register_restore[i]); 2752 2753 /* load indirect register */ 2754 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2755 adev->gfx.rlc.reg_list_format_start); 2756 2757 /* direct register portion */ 2758 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2759 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2760 register_list_format[i]); 2761 2762 /* indirect register portion */ 2763 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2764 if (register_list_format[i] == 0xFFFFFFFF) { 2765 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2766 continue; 2767 } 2768 2769 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2770 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2771 2772 for (j = 0; j < unique_indirect_reg_count; j++) { 2773 if (register_list_format[i] == unique_indirect_regs[j]) { 2774 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2775 break; 2776 } 2777 } 2778 2779 BUG_ON(j >= unique_indirect_reg_count); 2780 2781 i++; 2782 } 2783 2784 /* set save/restore list size */ 2785 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2786 list_size = list_size >> 1; 2787 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2788 adev->gfx.rlc.reg_restore_list_size); 2789 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2790 2791 /* write the starting offsets to RLC scratch ram */ 2792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2793 adev->gfx.rlc.starting_offsets_start); 2794 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2795 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2796 indirect_start_offsets[i]); 2797 2798 /* load unique indirect regs*/ 2799 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2800 if (unique_indirect_regs[i] != 0) { 2801 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2802 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2803 unique_indirect_regs[i] & 0x3FFFF); 2804 2805 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2806 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2807 unique_indirect_regs[i] >> 20); 2808 } 2809 } 2810 2811 kfree(register_list_format); 2812 return 0; 2813 } 2814 2815 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2816 { 2817 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2818 } 2819 2820 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2821 bool enable) 2822 { 2823 uint32_t data = 0; 2824 uint32_t default_data = 0; 2825 2826 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2827 if (enable) { 2828 /* enable GFXIP control over CGPG */ 2829 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2830 if(default_data != data) 2831 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2832 2833 /* update status */ 2834 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2835 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2836 if(default_data != data) 2837 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2838 } else { 2839 /* restore GFXIP control over GCPG */ 2840 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2841 if(default_data != data) 2842 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2843 } 2844 } 2845 2846 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2847 { 2848 uint32_t data = 0; 2849 2850 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2851 AMD_PG_SUPPORT_GFX_SMG | 2852 AMD_PG_SUPPORT_GFX_DMG)) { 2853 /* init IDLE_POLL_COUNT = 60 */ 2854 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2855 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2856 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2857 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2858 2859 /* init RLC PG Delay */ 2860 data = 0; 2861 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2862 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2863 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2864 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2865 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2866 2867 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2868 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2869 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2870 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2871 2872 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2873 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2874 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2875 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2876 2877 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2878 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2879 2880 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2881 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2882 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2883 if (adev->asic_type != CHIP_RENOIR) 2884 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2885 } 2886 } 2887 2888 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2889 bool enable) 2890 { 2891 uint32_t data = 0; 2892 uint32_t default_data = 0; 2893 2894 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2895 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2896 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2897 enable ? 1 : 0); 2898 if (default_data != data) 2899 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2900 } 2901 2902 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2903 bool enable) 2904 { 2905 uint32_t data = 0; 2906 uint32_t default_data = 0; 2907 2908 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2909 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2910 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2911 enable ? 1 : 0); 2912 if(default_data != data) 2913 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2914 } 2915 2916 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2917 bool enable) 2918 { 2919 uint32_t data = 0; 2920 uint32_t default_data = 0; 2921 2922 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2923 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2924 CP_PG_DISABLE, 2925 enable ? 0 : 1); 2926 if(default_data != data) 2927 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2928 } 2929 2930 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2931 bool enable) 2932 { 2933 uint32_t data, default_data; 2934 2935 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2936 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2937 GFX_POWER_GATING_ENABLE, 2938 enable ? 1 : 0); 2939 if(default_data != data) 2940 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2941 } 2942 2943 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2944 bool enable) 2945 { 2946 uint32_t data, default_data; 2947 2948 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2949 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2950 GFX_PIPELINE_PG_ENABLE, 2951 enable ? 1 : 0); 2952 if(default_data != data) 2953 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2954 2955 if (!enable) 2956 /* read any GFX register to wake up GFX */ 2957 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2958 } 2959 2960 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2961 bool enable) 2962 { 2963 uint32_t data, default_data; 2964 2965 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2966 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2967 STATIC_PER_CU_PG_ENABLE, 2968 enable ? 1 : 0); 2969 if(default_data != data) 2970 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2971 } 2972 2973 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2974 bool enable) 2975 { 2976 uint32_t data, default_data; 2977 2978 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2979 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2980 DYN_PER_CU_PG_ENABLE, 2981 enable ? 1 : 0); 2982 if(default_data != data) 2983 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2984 } 2985 2986 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2987 { 2988 gfx_v9_0_init_csb(adev); 2989 2990 /* 2991 * Rlc save restore list is workable since v2_1. 2992 * And it's needed by gfxoff feature. 2993 */ 2994 if (adev->gfx.rlc.is_rlc_v2_1) { 2995 if (adev->asic_type == CHIP_VEGA12 || 2996 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2997 gfx_v9_1_init_rlc_save_restore_list(adev); 2998 gfx_v9_0_enable_save_restore_machine(adev); 2999 } 3000 3001 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3002 AMD_PG_SUPPORT_GFX_SMG | 3003 AMD_PG_SUPPORT_GFX_DMG | 3004 AMD_PG_SUPPORT_CP | 3005 AMD_PG_SUPPORT_GDS | 3006 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3007 WREG32(mmRLC_JUMP_TABLE_RESTORE, 3008 adev->gfx.rlc.cp_table_gpu_addr >> 8); 3009 gfx_v9_0_init_gfx_power_gating(adev); 3010 } 3011 } 3012 3013 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 3014 { 3015 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 3016 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3017 gfx_v9_0_wait_for_rlc_serdes(adev); 3018 } 3019 3020 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 3021 { 3022 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3023 udelay(50); 3024 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 3025 udelay(50); 3026 } 3027 3028 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 3029 { 3030 #ifdef AMDGPU_RLC_DEBUG_RETRY 3031 u32 rlc_ucode_ver; 3032 #endif 3033 3034 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 3035 udelay(50); 3036 3037 /* carrizo do enable cp interrupt after cp inited */ 3038 if (!(adev->flags & AMD_IS_APU)) { 3039 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3040 udelay(50); 3041 } 3042 3043 #ifdef AMDGPU_RLC_DEBUG_RETRY 3044 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 3045 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 3046 if(rlc_ucode_ver == 0x108) { 3047 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 3048 rlc_ucode_ver, adev->gfx.rlc_fw_version); 3049 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 3050 * default is 0x9C4 to create a 100us interval */ 3051 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 3052 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 3053 * to disable the page fault retry interrupts, default is 3054 * 0x100 (256) */ 3055 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 3056 } 3057 #endif 3058 } 3059 3060 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 3061 { 3062 const struct rlc_firmware_header_v2_0 *hdr; 3063 const __le32 *fw_data; 3064 unsigned i, fw_size; 3065 3066 if (!adev->gfx.rlc_fw) 3067 return -EINVAL; 3068 3069 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3070 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3071 3072 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 3073 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3074 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3075 3076 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 3077 RLCG_UCODE_LOADING_START_ADDRESS); 3078 for (i = 0; i < fw_size; i++) 3079 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3080 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3081 3082 return 0; 3083 } 3084 3085 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 3086 { 3087 int r; 3088 3089 if (amdgpu_sriov_vf(adev)) { 3090 gfx_v9_0_init_csb(adev); 3091 return 0; 3092 } 3093 3094 adev->gfx.rlc.funcs->stop(adev); 3095 3096 /* disable CG */ 3097 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 3098 3099 gfx_v9_0_init_pg(adev); 3100 3101 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3102 /* legacy rlc firmware loading */ 3103 r = gfx_v9_0_rlc_load_microcode(adev); 3104 if (r) 3105 return r; 3106 } 3107 3108 switch (adev->asic_type) { 3109 case CHIP_RAVEN: 3110 if (amdgpu_lbpw == 0) 3111 gfx_v9_0_enable_lbpw(adev, false); 3112 else 3113 gfx_v9_0_enable_lbpw(adev, true); 3114 break; 3115 case CHIP_VEGA20: 3116 if (amdgpu_lbpw > 0) 3117 gfx_v9_0_enable_lbpw(adev, true); 3118 else 3119 gfx_v9_0_enable_lbpw(adev, false); 3120 break; 3121 default: 3122 break; 3123 } 3124 3125 adev->gfx.rlc.funcs->start(adev); 3126 3127 return 0; 3128 } 3129 3130 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3131 { 3132 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 3133 3134 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3136 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 3137 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 3138 udelay(50); 3139 } 3140 3141 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3142 { 3143 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3144 const struct gfx_firmware_header_v1_0 *ce_hdr; 3145 const struct gfx_firmware_header_v1_0 *me_hdr; 3146 const __le32 *fw_data; 3147 unsigned i, fw_size; 3148 3149 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3150 return -EINVAL; 3151 3152 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3153 adev->gfx.pfp_fw->data; 3154 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3155 adev->gfx.ce_fw->data; 3156 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3157 adev->gfx.me_fw->data; 3158 3159 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3160 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3161 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3162 3163 gfx_v9_0_cp_gfx_enable(adev, false); 3164 3165 /* PFP */ 3166 fw_data = (const __le32 *) 3167 (adev->gfx.pfp_fw->data + 3168 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3169 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3170 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3171 for (i = 0; i < fw_size; i++) 3172 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3173 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3174 3175 /* CE */ 3176 fw_data = (const __le32 *) 3177 (adev->gfx.ce_fw->data + 3178 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3179 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3180 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3181 for (i = 0; i < fw_size; i++) 3182 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3183 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3184 3185 /* ME */ 3186 fw_data = (const __le32 *) 3187 (adev->gfx.me_fw->data + 3188 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3189 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3190 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3191 for (i = 0; i < fw_size; i++) 3192 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3193 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3194 3195 return 0; 3196 } 3197 3198 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3199 { 3200 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3201 const struct cs_section_def *sect = NULL; 3202 const struct cs_extent_def *ext = NULL; 3203 int r, i, tmp; 3204 3205 /* init the CP */ 3206 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3207 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3208 3209 gfx_v9_0_cp_gfx_enable(adev, true); 3210 3211 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3212 if (r) { 3213 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3214 return r; 3215 } 3216 3217 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3218 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3219 3220 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3221 amdgpu_ring_write(ring, 0x80000000); 3222 amdgpu_ring_write(ring, 0x80000000); 3223 3224 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3225 for (ext = sect->section; ext->extent != NULL; ++ext) { 3226 if (sect->id == SECT_CONTEXT) { 3227 amdgpu_ring_write(ring, 3228 PACKET3(PACKET3_SET_CONTEXT_REG, 3229 ext->reg_count)); 3230 amdgpu_ring_write(ring, 3231 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3232 for (i = 0; i < ext->reg_count; i++) 3233 amdgpu_ring_write(ring, ext->extent[i]); 3234 } 3235 } 3236 } 3237 3238 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3239 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3240 3241 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3242 amdgpu_ring_write(ring, 0); 3243 3244 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3245 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3246 amdgpu_ring_write(ring, 0x8000); 3247 amdgpu_ring_write(ring, 0x8000); 3248 3249 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3250 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3251 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3252 amdgpu_ring_write(ring, tmp); 3253 amdgpu_ring_write(ring, 0); 3254 3255 amdgpu_ring_commit(ring); 3256 3257 return 0; 3258 } 3259 3260 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3261 { 3262 struct amdgpu_ring *ring; 3263 u32 tmp; 3264 u32 rb_bufsz; 3265 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3266 3267 /* Set the write pointer delay */ 3268 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3269 3270 /* set the RB to use vmid 0 */ 3271 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3272 3273 /* Set ring buffer size */ 3274 ring = &adev->gfx.gfx_ring[0]; 3275 rb_bufsz = order_base_2(ring->ring_size / 8); 3276 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3277 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3278 #ifdef __BIG_ENDIAN 3279 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3280 #endif 3281 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3282 3283 /* Initialize the ring buffer's write pointers */ 3284 ring->wptr = 0; 3285 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3286 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3287 3288 /* set the wb address wether it's enabled or not */ 3289 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3290 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3291 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3292 3293 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3294 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3295 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3296 3297 mdelay(1); 3298 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3299 3300 rb_addr = ring->gpu_addr >> 8; 3301 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3302 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3303 3304 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3305 if (ring->use_doorbell) { 3306 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3307 DOORBELL_OFFSET, ring->doorbell_index); 3308 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3309 DOORBELL_EN, 1); 3310 } else { 3311 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3312 } 3313 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3314 3315 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3316 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3317 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3318 3319 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3320 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3321 3322 3323 /* start the ring */ 3324 gfx_v9_0_cp_gfx_start(adev); 3325 ring->sched.ready = true; 3326 3327 return 0; 3328 } 3329 3330 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3331 { 3332 if (enable) { 3333 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3334 } else { 3335 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3336 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3337 adev->gfx.kiq.ring.sched.ready = false; 3338 } 3339 udelay(50); 3340 } 3341 3342 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3343 { 3344 const struct gfx_firmware_header_v1_0 *mec_hdr; 3345 const __le32 *fw_data; 3346 unsigned i; 3347 u32 tmp; 3348 3349 if (!adev->gfx.mec_fw) 3350 return -EINVAL; 3351 3352 gfx_v9_0_cp_compute_enable(adev, false); 3353 3354 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3355 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3356 3357 fw_data = (const __le32 *) 3358 (adev->gfx.mec_fw->data + 3359 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3360 tmp = 0; 3361 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3362 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3363 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3364 3365 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3366 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3367 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3368 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3369 3370 /* MEC1 */ 3371 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3372 mec_hdr->jt_offset); 3373 for (i = 0; i < mec_hdr->jt_size; i++) 3374 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3375 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3376 3377 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3378 adev->gfx.mec_fw_version); 3379 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3380 3381 return 0; 3382 } 3383 3384 /* KIQ functions */ 3385 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3386 { 3387 uint32_t tmp; 3388 struct amdgpu_device *adev = ring->adev; 3389 3390 /* tell RLC which is KIQ queue */ 3391 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3392 tmp &= 0xffffff00; 3393 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3394 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3395 tmp |= 0x80; 3396 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3397 } 3398 3399 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3400 { 3401 struct amdgpu_device *adev = ring->adev; 3402 3403 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3404 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3405 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3406 mqd->cp_hqd_queue_priority = 3407 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3408 } 3409 } 3410 } 3411 3412 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3413 { 3414 struct amdgpu_device *adev = ring->adev; 3415 struct v9_mqd *mqd = ring->mqd_ptr; 3416 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3417 uint32_t tmp; 3418 3419 mqd->header = 0xC0310800; 3420 mqd->compute_pipelinestat_enable = 0x00000001; 3421 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3422 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3423 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3424 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3425 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3426 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3427 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3428 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3429 mqd->compute_misc_reserved = 0x00000003; 3430 3431 mqd->dynamic_cu_mask_addr_lo = 3432 lower_32_bits(ring->mqd_gpu_addr 3433 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3434 mqd->dynamic_cu_mask_addr_hi = 3435 upper_32_bits(ring->mqd_gpu_addr 3436 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3437 3438 eop_base_addr = ring->eop_gpu_addr >> 8; 3439 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3440 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3441 3442 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3443 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3444 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3445 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3446 3447 mqd->cp_hqd_eop_control = tmp; 3448 3449 /* enable doorbell? */ 3450 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3451 3452 if (ring->use_doorbell) { 3453 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3454 DOORBELL_OFFSET, ring->doorbell_index); 3455 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3456 DOORBELL_EN, 1); 3457 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3458 DOORBELL_SOURCE, 0); 3459 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3460 DOORBELL_HIT, 0); 3461 } else { 3462 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3463 DOORBELL_EN, 0); 3464 } 3465 3466 mqd->cp_hqd_pq_doorbell_control = tmp; 3467 3468 /* disable the queue if it's active */ 3469 ring->wptr = 0; 3470 mqd->cp_hqd_dequeue_request = 0; 3471 mqd->cp_hqd_pq_rptr = 0; 3472 mqd->cp_hqd_pq_wptr_lo = 0; 3473 mqd->cp_hqd_pq_wptr_hi = 0; 3474 3475 /* set the pointer to the MQD */ 3476 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3477 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3478 3479 /* set MQD vmid to 0 */ 3480 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3481 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3482 mqd->cp_mqd_control = tmp; 3483 3484 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3485 hqd_gpu_addr = ring->gpu_addr >> 8; 3486 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3487 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3488 3489 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3490 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3491 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3492 (order_base_2(ring->ring_size / 4) - 1)); 3493 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3494 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3495 #ifdef __BIG_ENDIAN 3496 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3497 #endif 3498 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3502 mqd->cp_hqd_pq_control = tmp; 3503 3504 /* set the wb address whether it's enabled or not */ 3505 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3506 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3507 mqd->cp_hqd_pq_rptr_report_addr_hi = 3508 upper_32_bits(wb_gpu_addr) & 0xffff; 3509 3510 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3511 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3512 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3513 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3514 3515 tmp = 0; 3516 /* enable the doorbell if requested */ 3517 if (ring->use_doorbell) { 3518 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3519 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3520 DOORBELL_OFFSET, ring->doorbell_index); 3521 3522 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3523 DOORBELL_EN, 1); 3524 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3525 DOORBELL_SOURCE, 0); 3526 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3527 DOORBELL_HIT, 0); 3528 } 3529 3530 mqd->cp_hqd_pq_doorbell_control = tmp; 3531 3532 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3533 ring->wptr = 0; 3534 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3535 3536 /* set the vmid for the queue */ 3537 mqd->cp_hqd_vmid = 0; 3538 3539 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3540 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3541 mqd->cp_hqd_persistent_state = tmp; 3542 3543 /* set MIN_IB_AVAIL_SIZE */ 3544 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3545 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3546 mqd->cp_hqd_ib_control = tmp; 3547 3548 /* set static priority for a queue/ring */ 3549 gfx_v9_0_mqd_set_priority(ring, mqd); 3550 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3551 3552 /* map_queues packet doesn't need activate the queue, 3553 * so only kiq need set this field. 3554 */ 3555 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3556 mqd->cp_hqd_active = 1; 3557 3558 return 0; 3559 } 3560 3561 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3562 { 3563 struct amdgpu_device *adev = ring->adev; 3564 struct v9_mqd *mqd = ring->mqd_ptr; 3565 int j; 3566 3567 /* disable wptr polling */ 3568 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3569 3570 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3571 mqd->cp_hqd_eop_base_addr_lo); 3572 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3573 mqd->cp_hqd_eop_base_addr_hi); 3574 3575 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3576 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3577 mqd->cp_hqd_eop_control); 3578 3579 /* enable doorbell? */ 3580 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3581 mqd->cp_hqd_pq_doorbell_control); 3582 3583 /* disable the queue if it's active */ 3584 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3585 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3586 for (j = 0; j < adev->usec_timeout; j++) { 3587 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3588 break; 3589 udelay(1); 3590 } 3591 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3592 mqd->cp_hqd_dequeue_request); 3593 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3594 mqd->cp_hqd_pq_rptr); 3595 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3596 mqd->cp_hqd_pq_wptr_lo); 3597 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3598 mqd->cp_hqd_pq_wptr_hi); 3599 } 3600 3601 /* set the pointer to the MQD */ 3602 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3603 mqd->cp_mqd_base_addr_lo); 3604 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3605 mqd->cp_mqd_base_addr_hi); 3606 3607 /* set MQD vmid to 0 */ 3608 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3609 mqd->cp_mqd_control); 3610 3611 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3612 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3613 mqd->cp_hqd_pq_base_lo); 3614 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3615 mqd->cp_hqd_pq_base_hi); 3616 3617 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3618 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3619 mqd->cp_hqd_pq_control); 3620 3621 /* set the wb address whether it's enabled or not */ 3622 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3623 mqd->cp_hqd_pq_rptr_report_addr_lo); 3624 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3625 mqd->cp_hqd_pq_rptr_report_addr_hi); 3626 3627 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3628 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3629 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3630 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3631 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3632 3633 /* enable the doorbell if requested */ 3634 if (ring->use_doorbell) { 3635 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3636 (adev->doorbell_index.kiq * 2) << 2); 3637 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3638 (adev->doorbell_index.userqueue_end * 2) << 2); 3639 } 3640 3641 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3642 mqd->cp_hqd_pq_doorbell_control); 3643 3644 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3645 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3646 mqd->cp_hqd_pq_wptr_lo); 3647 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3648 mqd->cp_hqd_pq_wptr_hi); 3649 3650 /* set the vmid for the queue */ 3651 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3652 3653 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3654 mqd->cp_hqd_persistent_state); 3655 3656 /* activate the queue */ 3657 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3658 mqd->cp_hqd_active); 3659 3660 if (ring->use_doorbell) 3661 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3662 3663 return 0; 3664 } 3665 3666 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3667 { 3668 struct amdgpu_device *adev = ring->adev; 3669 int j; 3670 3671 /* disable the queue if it's active */ 3672 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3673 3674 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3675 3676 for (j = 0; j < adev->usec_timeout; j++) { 3677 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3678 break; 3679 udelay(1); 3680 } 3681 3682 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3683 DRM_DEBUG("KIQ dequeue request failed.\n"); 3684 3685 /* Manual disable if dequeue request times out */ 3686 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3687 } 3688 3689 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3690 0); 3691 } 3692 3693 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3694 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3695 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3696 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3697 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3698 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3699 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3700 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3701 3702 return 0; 3703 } 3704 3705 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3706 { 3707 struct amdgpu_device *adev = ring->adev; 3708 struct v9_mqd *mqd = ring->mqd_ptr; 3709 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3710 3711 gfx_v9_0_kiq_setting(ring); 3712 3713 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3714 /* reset MQD to a clean status */ 3715 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3716 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3717 3718 /* reset ring buffer */ 3719 ring->wptr = 0; 3720 amdgpu_ring_clear_ring(ring); 3721 3722 mutex_lock(&adev->srbm_mutex); 3723 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3724 gfx_v9_0_kiq_init_register(ring); 3725 soc15_grbm_select(adev, 0, 0, 0, 0); 3726 mutex_unlock(&adev->srbm_mutex); 3727 } else { 3728 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3729 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3730 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3731 mutex_lock(&adev->srbm_mutex); 3732 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3733 gfx_v9_0_mqd_init(ring); 3734 gfx_v9_0_kiq_init_register(ring); 3735 soc15_grbm_select(adev, 0, 0, 0, 0); 3736 mutex_unlock(&adev->srbm_mutex); 3737 3738 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3739 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3740 } 3741 3742 return 0; 3743 } 3744 3745 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3746 { 3747 struct amdgpu_device *adev = ring->adev; 3748 struct v9_mqd *mqd = ring->mqd_ptr; 3749 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3750 3751 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3752 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3753 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3754 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3755 mutex_lock(&adev->srbm_mutex); 3756 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3757 gfx_v9_0_mqd_init(ring); 3758 soc15_grbm_select(adev, 0, 0, 0, 0); 3759 mutex_unlock(&adev->srbm_mutex); 3760 3761 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3762 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3763 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3764 /* reset MQD to a clean status */ 3765 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3766 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3767 3768 /* reset ring buffer */ 3769 ring->wptr = 0; 3770 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 3771 amdgpu_ring_clear_ring(ring); 3772 } else { 3773 amdgpu_ring_clear_ring(ring); 3774 } 3775 3776 return 0; 3777 } 3778 3779 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3780 { 3781 struct amdgpu_ring *ring; 3782 int r; 3783 3784 ring = &adev->gfx.kiq.ring; 3785 3786 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3787 if (unlikely(r != 0)) 3788 return r; 3789 3790 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3791 if (unlikely(r != 0)) 3792 return r; 3793 3794 gfx_v9_0_kiq_init_queue(ring); 3795 amdgpu_bo_kunmap(ring->mqd_obj); 3796 ring->mqd_ptr = NULL; 3797 amdgpu_bo_unreserve(ring->mqd_obj); 3798 ring->sched.ready = true; 3799 return 0; 3800 } 3801 3802 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3803 { 3804 struct amdgpu_ring *ring = NULL; 3805 int r = 0, i; 3806 3807 gfx_v9_0_cp_compute_enable(adev, true); 3808 3809 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3810 ring = &adev->gfx.compute_ring[i]; 3811 3812 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3813 if (unlikely(r != 0)) 3814 goto done; 3815 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3816 if (!r) { 3817 r = gfx_v9_0_kcq_init_queue(ring); 3818 amdgpu_bo_kunmap(ring->mqd_obj); 3819 ring->mqd_ptr = NULL; 3820 } 3821 amdgpu_bo_unreserve(ring->mqd_obj); 3822 if (r) 3823 goto done; 3824 } 3825 3826 r = amdgpu_gfx_enable_kcq(adev); 3827 done: 3828 return r; 3829 } 3830 3831 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3832 { 3833 int r, i; 3834 struct amdgpu_ring *ring; 3835 3836 if (!(adev->flags & AMD_IS_APU)) 3837 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3838 3839 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3840 if (adev->gfx.num_gfx_rings) { 3841 /* legacy firmware loading */ 3842 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3843 if (r) 3844 return r; 3845 } 3846 3847 r = gfx_v9_0_cp_compute_load_microcode(adev); 3848 if (r) 3849 return r; 3850 } 3851 3852 r = gfx_v9_0_kiq_resume(adev); 3853 if (r) 3854 return r; 3855 3856 if (adev->gfx.num_gfx_rings) { 3857 r = gfx_v9_0_cp_gfx_resume(adev); 3858 if (r) 3859 return r; 3860 } 3861 3862 r = gfx_v9_0_kcq_resume(adev); 3863 if (r) 3864 return r; 3865 3866 if (adev->gfx.num_gfx_rings) { 3867 ring = &adev->gfx.gfx_ring[0]; 3868 r = amdgpu_ring_test_helper(ring); 3869 if (r) 3870 return r; 3871 } 3872 3873 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3874 ring = &adev->gfx.compute_ring[i]; 3875 amdgpu_ring_test_helper(ring); 3876 } 3877 3878 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3879 3880 return 0; 3881 } 3882 3883 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3884 { 3885 u32 tmp; 3886 3887 if (adev->asic_type != CHIP_ARCTURUS) 3888 return; 3889 3890 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3891 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3892 adev->df.hash_status.hash_64k); 3893 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3894 adev->df.hash_status.hash_2m); 3895 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3896 adev->df.hash_status.hash_1g); 3897 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3898 } 3899 3900 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3901 { 3902 if (adev->gfx.num_gfx_rings) 3903 gfx_v9_0_cp_gfx_enable(adev, enable); 3904 gfx_v9_0_cp_compute_enable(adev, enable); 3905 } 3906 3907 static int gfx_v9_0_hw_init(void *handle) 3908 { 3909 int r; 3910 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3911 3912 if (!amdgpu_sriov_vf(adev)) 3913 gfx_v9_0_init_golden_registers(adev); 3914 3915 gfx_v9_0_constants_init(adev); 3916 3917 gfx_v9_0_init_tcp_config(adev); 3918 3919 r = adev->gfx.rlc.funcs->resume(adev); 3920 if (r) 3921 return r; 3922 3923 r = gfx_v9_0_cp_resume(adev); 3924 if (r) 3925 return r; 3926 3927 return r; 3928 } 3929 3930 static int gfx_v9_0_hw_fini(void *handle) 3931 { 3932 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3933 3934 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3935 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3936 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3937 3938 /* DF freeze and kcq disable will fail */ 3939 if (!amdgpu_ras_intr_triggered()) 3940 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3941 amdgpu_gfx_disable_kcq(adev); 3942 3943 if (amdgpu_sriov_vf(adev)) { 3944 gfx_v9_0_cp_gfx_enable(adev, false); 3945 /* must disable polling for SRIOV when hw finished, otherwise 3946 * CPC engine may still keep fetching WB address which is already 3947 * invalid after sw finished and trigger DMAR reading error in 3948 * hypervisor side. 3949 */ 3950 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3951 return 0; 3952 } 3953 3954 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3955 * otherwise KIQ is hanging when binding back 3956 */ 3957 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3958 mutex_lock(&adev->srbm_mutex); 3959 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3960 adev->gfx.kiq.ring.pipe, 3961 adev->gfx.kiq.ring.queue, 0); 3962 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3963 soc15_grbm_select(adev, 0, 0, 0, 0); 3964 mutex_unlock(&adev->srbm_mutex); 3965 } 3966 3967 gfx_v9_0_cp_enable(adev, false); 3968 adev->gfx.rlc.funcs->stop(adev); 3969 3970 return 0; 3971 } 3972 3973 static int gfx_v9_0_suspend(void *handle) 3974 { 3975 return gfx_v9_0_hw_fini(handle); 3976 } 3977 3978 static int gfx_v9_0_resume(void *handle) 3979 { 3980 return gfx_v9_0_hw_init(handle); 3981 } 3982 3983 static bool gfx_v9_0_is_idle(void *handle) 3984 { 3985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3986 3987 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3988 GRBM_STATUS, GUI_ACTIVE)) 3989 return false; 3990 else 3991 return true; 3992 } 3993 3994 static int gfx_v9_0_wait_for_idle(void *handle) 3995 { 3996 unsigned i; 3997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3998 3999 for (i = 0; i < adev->usec_timeout; i++) { 4000 if (gfx_v9_0_is_idle(handle)) 4001 return 0; 4002 udelay(1); 4003 } 4004 return -ETIMEDOUT; 4005 } 4006 4007 static int gfx_v9_0_soft_reset(void *handle) 4008 { 4009 u32 grbm_soft_reset = 0; 4010 u32 tmp; 4011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4012 4013 /* GRBM_STATUS */ 4014 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 4015 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4016 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4017 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4018 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4019 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4020 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 4021 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4022 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4023 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4024 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4025 } 4026 4027 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4028 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4029 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4030 } 4031 4032 /* GRBM_STATUS2 */ 4033 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 4034 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4035 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4036 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4037 4038 4039 if (grbm_soft_reset) { 4040 /* stop the rlc */ 4041 adev->gfx.rlc.funcs->stop(adev); 4042 4043 if (adev->gfx.num_gfx_rings) 4044 /* Disable GFX parsing/prefetching */ 4045 gfx_v9_0_cp_gfx_enable(adev, false); 4046 4047 /* Disable MEC parsing/prefetching */ 4048 gfx_v9_0_cp_compute_enable(adev, false); 4049 4050 if (grbm_soft_reset) { 4051 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4052 tmp |= grbm_soft_reset; 4053 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4054 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4055 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4056 4057 udelay(50); 4058 4059 tmp &= ~grbm_soft_reset; 4060 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4061 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4062 } 4063 4064 /* Wait a little for things to settle down */ 4065 udelay(50); 4066 } 4067 return 0; 4068 } 4069 4070 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 4071 { 4072 signed long r, cnt = 0; 4073 unsigned long flags; 4074 uint32_t seq, reg_val_offs = 0; 4075 uint64_t value = 0; 4076 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4077 struct amdgpu_ring *ring = &kiq->ring; 4078 4079 BUG_ON(!ring->funcs->emit_rreg); 4080 4081 spin_lock_irqsave(&kiq->ring_lock, flags); 4082 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 4083 pr_err("critical bug! too many kiq readers\n"); 4084 goto failed_unlock; 4085 } 4086 amdgpu_ring_alloc(ring, 32); 4087 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4088 amdgpu_ring_write(ring, 9 | /* src: register*/ 4089 (5 << 8) | /* dst: memory */ 4090 (1 << 16) | /* count sel */ 4091 (1 << 20)); /* write confirm */ 4092 amdgpu_ring_write(ring, 0); 4093 amdgpu_ring_write(ring, 0); 4094 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4095 reg_val_offs * 4)); 4096 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4097 reg_val_offs * 4)); 4098 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 4099 if (r) 4100 goto failed_undo; 4101 4102 amdgpu_ring_commit(ring); 4103 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4104 4105 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4106 4107 /* don't wait anymore for gpu reset case because this way may 4108 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 4109 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 4110 * never return if we keep waiting in virt_kiq_rreg, which cause 4111 * gpu_recover() hang there. 4112 * 4113 * also don't wait anymore for IRQ context 4114 * */ 4115 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) 4116 goto failed_kiq_read; 4117 4118 might_sleep(); 4119 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 4120 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 4121 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4122 } 4123 4124 if (cnt > MAX_KIQ_REG_TRY) 4125 goto failed_kiq_read; 4126 4127 mb(); 4128 value = (uint64_t)adev->wb.wb[reg_val_offs] | 4129 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 4130 amdgpu_device_wb_free(adev, reg_val_offs); 4131 return value; 4132 4133 failed_undo: 4134 amdgpu_ring_undo(ring); 4135 failed_unlock: 4136 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4137 failed_kiq_read: 4138 if (reg_val_offs) 4139 amdgpu_device_wb_free(adev, reg_val_offs); 4140 pr_err("failed to read gpu clock\n"); 4141 return ~0; 4142 } 4143 4144 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4145 { 4146 uint64_t clock; 4147 4148 amdgpu_gfx_off_ctrl(adev, false); 4149 mutex_lock(&adev->gfx.gpu_clock_mutex); 4150 if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) { 4151 clock = gfx_v9_0_kiq_read_clock(adev); 4152 } else { 4153 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4154 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4155 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4156 } 4157 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4158 amdgpu_gfx_off_ctrl(adev, true); 4159 return clock; 4160 } 4161 4162 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4163 uint32_t vmid, 4164 uint32_t gds_base, uint32_t gds_size, 4165 uint32_t gws_base, uint32_t gws_size, 4166 uint32_t oa_base, uint32_t oa_size) 4167 { 4168 struct amdgpu_device *adev = ring->adev; 4169 4170 /* GDS Base */ 4171 gfx_v9_0_write_data_to_reg(ring, 0, false, 4172 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4173 gds_base); 4174 4175 /* GDS Size */ 4176 gfx_v9_0_write_data_to_reg(ring, 0, false, 4177 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4178 gds_size); 4179 4180 /* GWS */ 4181 gfx_v9_0_write_data_to_reg(ring, 0, false, 4182 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4183 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4184 4185 /* OA */ 4186 gfx_v9_0_write_data_to_reg(ring, 0, false, 4187 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4188 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4189 } 4190 4191 static const u32 vgpr_init_compute_shader[] = 4192 { 4193 0xb07c0000, 0xbe8000ff, 4194 0x000000f8, 0xbf110800, 4195 0x7e000280, 0x7e020280, 4196 0x7e040280, 0x7e060280, 4197 0x7e080280, 0x7e0a0280, 4198 0x7e0c0280, 0x7e0e0280, 4199 0x80808800, 0xbe803200, 4200 0xbf84fff5, 0xbf9c0000, 4201 0xd28c0001, 0x0001007f, 4202 0xd28d0001, 0x0002027e, 4203 0x10020288, 0xb8810904, 4204 0xb7814000, 0xd1196a01, 4205 0x00000301, 0xbe800087, 4206 0xbefc00c1, 0xd89c4000, 4207 0x00020201, 0xd89cc080, 4208 0x00040401, 0x320202ff, 4209 0x00000800, 0x80808100, 4210 0xbf84fff8, 0x7e020280, 4211 0xbf810000, 0x00000000, 4212 }; 4213 4214 static const u32 sgpr_init_compute_shader[] = 4215 { 4216 0xb07c0000, 0xbe8000ff, 4217 0x0000005f, 0xbee50080, 4218 0xbe812c65, 0xbe822c65, 4219 0xbe832c65, 0xbe842c65, 4220 0xbe852c65, 0xb77c0005, 4221 0x80808500, 0xbf84fff8, 4222 0xbe800080, 0xbf810000, 4223 }; 4224 4225 static const u32 vgpr_init_compute_shader_arcturus[] = { 4226 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4227 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4228 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4229 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4230 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4231 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4232 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4233 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4234 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4235 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4236 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4237 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4238 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4239 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4240 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4241 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4242 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4243 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4244 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4245 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4246 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4247 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4248 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4249 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4250 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4251 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4252 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4253 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4254 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4255 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4256 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4257 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4258 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4259 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4260 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4261 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4262 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4263 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4264 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4265 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4266 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4267 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4268 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4269 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4270 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4271 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4272 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4273 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4274 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4275 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4276 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4277 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4278 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4279 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4280 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4281 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4282 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4283 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4284 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4285 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4286 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4287 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4288 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4289 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4290 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4291 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4292 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4293 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4294 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4295 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4296 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4297 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4298 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4299 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4300 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4301 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4302 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4303 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4304 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4305 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4306 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4307 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4308 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4309 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4310 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4311 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4312 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4313 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4314 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4315 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4316 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4317 0xbf84fff8, 0xbf810000, 4318 }; 4319 4320 /* When below register arrays changed, please update gpr_reg_size, 4321 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4322 to cover all gfx9 ASICs */ 4323 static const struct soc15_reg_entry vgpr_init_regs[] = { 4324 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4325 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4326 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4327 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4328 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4329 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4330 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4331 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4332 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4333 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4334 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4335 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4336 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4337 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4338 }; 4339 4340 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4341 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4342 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4343 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4344 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4345 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4346 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4347 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4348 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4349 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4350 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4351 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4352 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4353 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4354 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4355 }; 4356 4357 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4358 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4359 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4360 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4361 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4362 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4366 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4367 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4368 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4369 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4370 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4371 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4372 }; 4373 4374 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4375 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4376 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4377 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4378 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4379 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4380 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4381 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4382 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4383 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4384 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4385 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4386 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4387 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4388 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4389 }; 4390 4391 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4392 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4393 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4394 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4395 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4396 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4397 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4398 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4399 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4400 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4401 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4402 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4403 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4404 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4405 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4406 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4407 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4408 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4409 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4410 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4411 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4412 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4413 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4414 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4415 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4416 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4417 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4418 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4419 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4420 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4421 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4422 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4423 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4424 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4425 }; 4426 4427 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4428 { 4429 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4430 int i, r; 4431 4432 /* only support when RAS is enabled */ 4433 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4434 return 0; 4435 4436 r = amdgpu_ring_alloc(ring, 7); 4437 if (r) { 4438 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4439 ring->name, r); 4440 return r; 4441 } 4442 4443 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4444 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4445 4446 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4447 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4448 PACKET3_DMA_DATA_DST_SEL(1) | 4449 PACKET3_DMA_DATA_SRC_SEL(2) | 4450 PACKET3_DMA_DATA_ENGINE(0))); 4451 amdgpu_ring_write(ring, 0); 4452 amdgpu_ring_write(ring, 0); 4453 amdgpu_ring_write(ring, 0); 4454 amdgpu_ring_write(ring, 0); 4455 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4456 adev->gds.gds_size); 4457 4458 amdgpu_ring_commit(ring); 4459 4460 for (i = 0; i < adev->usec_timeout; i++) { 4461 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4462 break; 4463 udelay(1); 4464 } 4465 4466 if (i >= adev->usec_timeout) 4467 r = -ETIMEDOUT; 4468 4469 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4470 4471 return r; 4472 } 4473 4474 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4475 { 4476 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4477 struct amdgpu_ib ib; 4478 struct dma_fence *f = NULL; 4479 int r, i; 4480 unsigned total_size, vgpr_offset, sgpr_offset; 4481 u64 gpu_addr; 4482 4483 int compute_dim_x = adev->gfx.config.max_shader_engines * 4484 adev->gfx.config.max_cu_per_sh * 4485 adev->gfx.config.max_sh_per_se; 4486 int sgpr_work_group_size = 5; 4487 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4488 int vgpr_init_shader_size; 4489 const u32 *vgpr_init_shader_ptr; 4490 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4491 4492 /* only support when RAS is enabled */ 4493 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4494 return 0; 4495 4496 /* bail if the compute ring is not ready */ 4497 if (!ring->sched.ready) 4498 return 0; 4499 4500 if (adev->asic_type == CHIP_ARCTURUS) { 4501 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4502 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4503 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4504 } else { 4505 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4506 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4507 vgpr_init_regs_ptr = vgpr_init_regs; 4508 } 4509 4510 total_size = 4511 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4512 total_size += 4513 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4514 total_size += 4515 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4516 total_size = ALIGN(total_size, 256); 4517 vgpr_offset = total_size; 4518 total_size += ALIGN(vgpr_init_shader_size, 256); 4519 sgpr_offset = total_size; 4520 total_size += sizeof(sgpr_init_compute_shader); 4521 4522 /* allocate an indirect buffer to put the commands in */ 4523 memset(&ib, 0, sizeof(ib)); 4524 r = amdgpu_ib_get(adev, NULL, total_size, 4525 AMDGPU_IB_POOL_DIRECT, &ib); 4526 if (r) { 4527 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4528 return r; 4529 } 4530 4531 /* load the compute shaders */ 4532 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4533 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4534 4535 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4536 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4537 4538 /* init the ib length to 0 */ 4539 ib.length_dw = 0; 4540 4541 /* VGPR */ 4542 /* write the register state for the compute dispatch */ 4543 for (i = 0; i < gpr_reg_size; i++) { 4544 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4545 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4546 - PACKET3_SET_SH_REG_START; 4547 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4548 } 4549 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4550 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4551 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4552 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4553 - PACKET3_SET_SH_REG_START; 4554 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4555 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4556 4557 /* write dispatch packet */ 4558 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4559 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4560 ib.ptr[ib.length_dw++] = 1; /* y */ 4561 ib.ptr[ib.length_dw++] = 1; /* z */ 4562 ib.ptr[ib.length_dw++] = 4563 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4564 4565 /* write CS partial flush packet */ 4566 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4567 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4568 4569 /* SGPR1 */ 4570 /* write the register state for the compute dispatch */ 4571 for (i = 0; i < gpr_reg_size; i++) { 4572 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4573 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4574 - PACKET3_SET_SH_REG_START; 4575 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4576 } 4577 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4578 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4579 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4580 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4581 - PACKET3_SET_SH_REG_START; 4582 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4583 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4584 4585 /* write dispatch packet */ 4586 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4587 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4588 ib.ptr[ib.length_dw++] = 1; /* y */ 4589 ib.ptr[ib.length_dw++] = 1; /* z */ 4590 ib.ptr[ib.length_dw++] = 4591 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4592 4593 /* write CS partial flush packet */ 4594 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4595 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4596 4597 /* SGPR2 */ 4598 /* write the register state for the compute dispatch */ 4599 for (i = 0; i < gpr_reg_size; i++) { 4600 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4601 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4602 - PACKET3_SET_SH_REG_START; 4603 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4604 } 4605 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4606 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4607 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4608 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4609 - PACKET3_SET_SH_REG_START; 4610 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4611 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4612 4613 /* write dispatch packet */ 4614 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4615 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4616 ib.ptr[ib.length_dw++] = 1; /* y */ 4617 ib.ptr[ib.length_dw++] = 1; /* z */ 4618 ib.ptr[ib.length_dw++] = 4619 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4620 4621 /* write CS partial flush packet */ 4622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4623 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4624 4625 /* shedule the ib on the ring */ 4626 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4627 if (r) { 4628 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4629 goto fail; 4630 } 4631 4632 /* wait for the GPU to finish processing the IB */ 4633 r = dma_fence_wait(f, false); 4634 if (r) { 4635 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4636 goto fail; 4637 } 4638 4639 fail: 4640 amdgpu_ib_free(adev, &ib, NULL); 4641 dma_fence_put(f); 4642 4643 return r; 4644 } 4645 4646 static int gfx_v9_0_early_init(void *handle) 4647 { 4648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4649 4650 if (adev->asic_type == CHIP_ARCTURUS) 4651 adev->gfx.num_gfx_rings = 0; 4652 else 4653 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4654 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4655 AMDGPU_MAX_COMPUTE_RINGS); 4656 gfx_v9_0_set_kiq_pm4_funcs(adev); 4657 gfx_v9_0_set_ring_funcs(adev); 4658 gfx_v9_0_set_irq_funcs(adev); 4659 gfx_v9_0_set_gds_init(adev); 4660 gfx_v9_0_set_rlc_funcs(adev); 4661 4662 return 0; 4663 } 4664 4665 static int gfx_v9_0_ecc_late_init(void *handle) 4666 { 4667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4668 int r; 4669 4670 /* 4671 * Temp workaround to fix the issue that CP firmware fails to 4672 * update read pointer when CPDMA is writing clearing operation 4673 * to GDS in suspend/resume sequence on several cards. So just 4674 * limit this operation in cold boot sequence. 4675 */ 4676 if (!adev->in_suspend) { 4677 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4678 if (r) 4679 return r; 4680 } 4681 4682 /* requires IBs so do in late init after IB pool is initialized */ 4683 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4684 if (r) 4685 return r; 4686 4687 if (adev->gfx.funcs && 4688 adev->gfx.funcs->reset_ras_error_count) 4689 adev->gfx.funcs->reset_ras_error_count(adev); 4690 4691 r = amdgpu_gfx_ras_late_init(adev); 4692 if (r) 4693 return r; 4694 4695 return 0; 4696 } 4697 4698 static int gfx_v9_0_late_init(void *handle) 4699 { 4700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4701 int r; 4702 4703 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4704 if (r) 4705 return r; 4706 4707 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4708 if (r) 4709 return r; 4710 4711 r = gfx_v9_0_ecc_late_init(handle); 4712 if (r) 4713 return r; 4714 4715 return 0; 4716 } 4717 4718 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4719 { 4720 uint32_t rlc_setting; 4721 4722 /* if RLC is not enabled, do nothing */ 4723 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4724 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4725 return false; 4726 4727 return true; 4728 } 4729 4730 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4731 { 4732 uint32_t data; 4733 unsigned i; 4734 4735 data = RLC_SAFE_MODE__CMD_MASK; 4736 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4737 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4738 4739 /* wait for RLC_SAFE_MODE */ 4740 for (i = 0; i < adev->usec_timeout; i++) { 4741 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4742 break; 4743 udelay(1); 4744 } 4745 } 4746 4747 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4748 { 4749 uint32_t data; 4750 4751 data = RLC_SAFE_MODE__CMD_MASK; 4752 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4753 } 4754 4755 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4756 bool enable) 4757 { 4758 amdgpu_gfx_rlc_enter_safe_mode(adev); 4759 4760 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4761 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4762 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4763 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4764 } else { 4765 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4766 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4767 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4768 } 4769 4770 amdgpu_gfx_rlc_exit_safe_mode(adev); 4771 } 4772 4773 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4774 bool enable) 4775 { 4776 /* TODO: double check if we need to perform under safe mode */ 4777 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4778 4779 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4780 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4781 else 4782 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4783 4784 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4785 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4786 else 4787 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4788 4789 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4790 } 4791 4792 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4793 bool enable) 4794 { 4795 uint32_t data, def; 4796 4797 amdgpu_gfx_rlc_enter_safe_mode(adev); 4798 4799 /* It is disabled by HW by default */ 4800 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4801 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4802 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4803 4804 if (adev->asic_type != CHIP_VEGA12) 4805 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4806 4807 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4808 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4809 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4810 4811 /* only for Vega10 & Raven1 */ 4812 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4813 4814 if (def != data) 4815 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4816 4817 /* MGLS is a global flag to control all MGLS in GFX */ 4818 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4819 /* 2 - RLC memory Light sleep */ 4820 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4821 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4822 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4823 if (def != data) 4824 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4825 } 4826 /* 3 - CP memory Light sleep */ 4827 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4828 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4829 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4830 if (def != data) 4831 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4832 } 4833 } 4834 } else { 4835 /* 1 - MGCG_OVERRIDE */ 4836 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4837 4838 if (adev->asic_type != CHIP_VEGA12) 4839 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4840 4841 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4842 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4843 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4844 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4845 4846 if (def != data) 4847 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4848 4849 /* 2 - disable MGLS in RLC */ 4850 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4851 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4852 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4853 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4854 } 4855 4856 /* 3 - disable MGLS in CP */ 4857 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4858 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4859 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4860 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4861 } 4862 } 4863 4864 amdgpu_gfx_rlc_exit_safe_mode(adev); 4865 } 4866 4867 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4868 bool enable) 4869 { 4870 uint32_t data, def; 4871 4872 if (adev->asic_type == CHIP_ARCTURUS) 4873 return; 4874 4875 amdgpu_gfx_rlc_enter_safe_mode(adev); 4876 4877 /* Enable 3D CGCG/CGLS */ 4878 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4879 /* write cmd to clear cgcg/cgls ov */ 4880 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4881 /* unset CGCG override */ 4882 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4883 /* update CGCG and CGLS override bits */ 4884 if (def != data) 4885 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4886 4887 /* enable 3Dcgcg FSM(0x0000363f) */ 4888 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4889 4890 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4891 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4892 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4893 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4894 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4895 if (def != data) 4896 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4897 4898 /* set IDLE_POLL_COUNT(0x00900100) */ 4899 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4900 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4901 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4902 if (def != data) 4903 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4904 } else { 4905 /* Disable CGCG/CGLS */ 4906 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4907 /* disable cgcg, cgls should be disabled */ 4908 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4909 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4910 /* disable cgcg and cgls in FSM */ 4911 if (def != data) 4912 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4913 } 4914 4915 amdgpu_gfx_rlc_exit_safe_mode(adev); 4916 } 4917 4918 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4919 bool enable) 4920 { 4921 uint32_t def, data; 4922 4923 amdgpu_gfx_rlc_enter_safe_mode(adev); 4924 4925 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4926 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4927 /* unset CGCG override */ 4928 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4929 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4930 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4931 else 4932 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4933 /* update CGCG and CGLS override bits */ 4934 if (def != data) 4935 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4936 4937 /* enable cgcg FSM(0x0000363F) */ 4938 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4939 4940 if (adev->asic_type == CHIP_ARCTURUS) 4941 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4942 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4943 else 4944 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4945 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4946 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4947 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4948 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4949 if (def != data) 4950 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4951 4952 /* set IDLE_POLL_COUNT(0x00900100) */ 4953 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4954 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4955 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4956 if (def != data) 4957 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4958 } else { 4959 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4960 /* reset CGCG/CGLS bits */ 4961 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4962 /* disable cgcg and cgls in FSM */ 4963 if (def != data) 4964 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4965 } 4966 4967 amdgpu_gfx_rlc_exit_safe_mode(adev); 4968 } 4969 4970 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4971 bool enable) 4972 { 4973 if (enable) { 4974 /* CGCG/CGLS should be enabled after MGCG/MGLS 4975 * === MGCG + MGLS === 4976 */ 4977 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4978 /* === CGCG /CGLS for GFX 3D Only === */ 4979 gfx_v9_0_update_3d_clock_gating(adev, enable); 4980 /* === CGCG + CGLS === */ 4981 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4982 } else { 4983 /* CGCG/CGLS should be disabled before MGCG/MGLS 4984 * === CGCG + CGLS === 4985 */ 4986 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4987 /* === CGCG /CGLS for GFX 3D Only === */ 4988 gfx_v9_0_update_3d_clock_gating(adev, enable); 4989 /* === MGCG + MGLS === */ 4990 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4991 } 4992 return 0; 4993 } 4994 4995 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4996 { 4997 u32 reg, data; 4998 4999 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 5000 if (amdgpu_sriov_is_pp_one_vf(adev)) 5001 data = RREG32_NO_KIQ(reg); 5002 else 5003 data = RREG32(reg); 5004 5005 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 5006 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 5007 5008 if (amdgpu_sriov_is_pp_one_vf(adev)) 5009 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 5010 else 5011 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 5012 } 5013 5014 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 5015 uint32_t offset, 5016 struct soc15_reg_rlcg *entries, int arr_size) 5017 { 5018 int i; 5019 uint32_t reg; 5020 5021 if (!entries) 5022 return false; 5023 5024 for (i = 0; i < arr_size; i++) { 5025 const struct soc15_reg_rlcg *entry; 5026 5027 entry = &entries[i]; 5028 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 5029 if (offset == reg) 5030 return true; 5031 } 5032 5033 return false; 5034 } 5035 5036 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 5037 { 5038 return gfx_v9_0_check_rlcg_range(adev, offset, 5039 (void *)rlcg_access_gc_9_0, 5040 ARRAY_SIZE(rlcg_access_gc_9_0)); 5041 } 5042 5043 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 5044 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 5045 .set_safe_mode = gfx_v9_0_set_safe_mode, 5046 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 5047 .init = gfx_v9_0_rlc_init, 5048 .get_csb_size = gfx_v9_0_get_csb_size, 5049 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 5050 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 5051 .resume = gfx_v9_0_rlc_resume, 5052 .stop = gfx_v9_0_rlc_stop, 5053 .reset = gfx_v9_0_rlc_reset, 5054 .start = gfx_v9_0_rlc_start, 5055 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 5056 .rlcg_wreg = gfx_v9_0_rlcg_wreg, 5057 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 5058 }; 5059 5060 static int gfx_v9_0_set_powergating_state(void *handle, 5061 enum amd_powergating_state state) 5062 { 5063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5064 bool enable = (state == AMD_PG_STATE_GATE); 5065 5066 switch (adev->asic_type) { 5067 case CHIP_RAVEN: 5068 case CHIP_RENOIR: 5069 if (!enable) 5070 amdgpu_gfx_off_ctrl(adev, false); 5071 5072 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5073 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 5074 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 5075 } else { 5076 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 5077 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 5078 } 5079 5080 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5081 gfx_v9_0_enable_cp_power_gating(adev, true); 5082 else 5083 gfx_v9_0_enable_cp_power_gating(adev, false); 5084 5085 /* update gfx cgpg state */ 5086 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 5087 5088 /* update mgcg state */ 5089 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 5090 5091 if (enable) 5092 amdgpu_gfx_off_ctrl(adev, true); 5093 break; 5094 case CHIP_VEGA12: 5095 amdgpu_gfx_off_ctrl(adev, enable); 5096 break; 5097 default: 5098 break; 5099 } 5100 5101 return 0; 5102 } 5103 5104 static int gfx_v9_0_set_clockgating_state(void *handle, 5105 enum amd_clockgating_state state) 5106 { 5107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5108 5109 if (amdgpu_sriov_vf(adev)) 5110 return 0; 5111 5112 switch (adev->asic_type) { 5113 case CHIP_VEGA10: 5114 case CHIP_VEGA12: 5115 case CHIP_VEGA20: 5116 case CHIP_RAVEN: 5117 case CHIP_ARCTURUS: 5118 case CHIP_RENOIR: 5119 gfx_v9_0_update_gfx_clock_gating(adev, 5120 state == AMD_CG_STATE_GATE); 5121 break; 5122 default: 5123 break; 5124 } 5125 return 0; 5126 } 5127 5128 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 5129 { 5130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5131 int data; 5132 5133 if (amdgpu_sriov_vf(adev)) 5134 *flags = 0; 5135 5136 /* AMD_CG_SUPPORT_GFX_MGCG */ 5137 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5138 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5139 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5140 5141 /* AMD_CG_SUPPORT_GFX_CGCG */ 5142 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5143 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5144 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5145 5146 /* AMD_CG_SUPPORT_GFX_CGLS */ 5147 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5148 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5149 5150 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5151 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5152 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5153 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5154 5155 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5156 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5157 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5158 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5159 5160 if (adev->asic_type != CHIP_ARCTURUS) { 5161 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5162 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5163 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5164 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5165 5166 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5167 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5168 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5169 } 5170 } 5171 5172 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5173 { 5174 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 5175 } 5176 5177 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5178 { 5179 struct amdgpu_device *adev = ring->adev; 5180 u64 wptr; 5181 5182 /* XXX check if swapping is necessary on BE */ 5183 if (ring->use_doorbell) { 5184 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 5185 } else { 5186 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5187 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5188 } 5189 5190 return wptr; 5191 } 5192 5193 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5194 { 5195 struct amdgpu_device *adev = ring->adev; 5196 5197 if (ring->use_doorbell) { 5198 /* XXX check if swapping is necessary on BE */ 5199 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5200 WDOORBELL64(ring->doorbell_index, ring->wptr); 5201 } else { 5202 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5203 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5204 } 5205 } 5206 5207 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5208 { 5209 struct amdgpu_device *adev = ring->adev; 5210 u32 ref_and_mask, reg_mem_engine; 5211 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5212 5213 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5214 switch (ring->me) { 5215 case 1: 5216 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5217 break; 5218 case 2: 5219 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5220 break; 5221 default: 5222 return; 5223 } 5224 reg_mem_engine = 0; 5225 } else { 5226 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5227 reg_mem_engine = 1; /* pfp */ 5228 } 5229 5230 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5231 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5232 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5233 ref_and_mask, ref_and_mask, 0x20); 5234 } 5235 5236 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5237 struct amdgpu_job *job, 5238 struct amdgpu_ib *ib, 5239 uint32_t flags) 5240 { 5241 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5242 u32 header, control = 0; 5243 5244 if (ib->flags & AMDGPU_IB_FLAG_CE) 5245 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5246 else 5247 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5248 5249 control |= ib->length_dw | (vmid << 24); 5250 5251 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5252 control |= INDIRECT_BUFFER_PRE_ENB(1); 5253 5254 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5255 gfx_v9_0_ring_emit_de_meta(ring); 5256 } 5257 5258 amdgpu_ring_write(ring, header); 5259 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5260 amdgpu_ring_write(ring, 5261 #ifdef __BIG_ENDIAN 5262 (2 << 0) | 5263 #endif 5264 lower_32_bits(ib->gpu_addr)); 5265 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5266 amdgpu_ring_write(ring, control); 5267 } 5268 5269 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5270 struct amdgpu_job *job, 5271 struct amdgpu_ib *ib, 5272 uint32_t flags) 5273 { 5274 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5275 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5276 5277 /* Currently, there is a high possibility to get wave ID mismatch 5278 * between ME and GDS, leading to a hw deadlock, because ME generates 5279 * different wave IDs than the GDS expects. This situation happens 5280 * randomly when at least 5 compute pipes use GDS ordered append. 5281 * The wave IDs generated by ME are also wrong after suspend/resume. 5282 * Those are probably bugs somewhere else in the kernel driver. 5283 * 5284 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5285 * GDS to 0 for this ring (me/pipe). 5286 */ 5287 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5288 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5289 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5290 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5291 } 5292 5293 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5294 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5295 amdgpu_ring_write(ring, 5296 #ifdef __BIG_ENDIAN 5297 (2 << 0) | 5298 #endif 5299 lower_32_bits(ib->gpu_addr)); 5300 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5301 amdgpu_ring_write(ring, control); 5302 } 5303 5304 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5305 u64 seq, unsigned flags) 5306 { 5307 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5308 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5309 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5310 5311 /* RELEASE_MEM - flush caches, send int */ 5312 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5313 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 5314 EOP_TC_NC_ACTION_EN) : 5315 (EOP_TCL1_ACTION_EN | 5316 EOP_TC_ACTION_EN | 5317 EOP_TC_WB_ACTION_EN | 5318 EOP_TC_MD_ACTION_EN)) | 5319 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5320 EVENT_INDEX(5))); 5321 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5322 5323 /* 5324 * the address should be Qword aligned if 64bit write, Dword 5325 * aligned if only send 32bit data low (discard data high) 5326 */ 5327 if (write64bit) 5328 BUG_ON(addr & 0x7); 5329 else 5330 BUG_ON(addr & 0x3); 5331 amdgpu_ring_write(ring, lower_32_bits(addr)); 5332 amdgpu_ring_write(ring, upper_32_bits(addr)); 5333 amdgpu_ring_write(ring, lower_32_bits(seq)); 5334 amdgpu_ring_write(ring, upper_32_bits(seq)); 5335 amdgpu_ring_write(ring, 0); 5336 } 5337 5338 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5339 { 5340 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5341 uint32_t seq = ring->fence_drv.sync_seq; 5342 uint64_t addr = ring->fence_drv.gpu_addr; 5343 5344 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5345 lower_32_bits(addr), upper_32_bits(addr), 5346 seq, 0xffffffff, 4); 5347 } 5348 5349 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5350 unsigned vmid, uint64_t pd_addr) 5351 { 5352 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5353 5354 /* compute doesn't have PFP */ 5355 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5356 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5357 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5358 amdgpu_ring_write(ring, 0x0); 5359 } 5360 } 5361 5362 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5363 { 5364 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 5365 } 5366 5367 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5368 { 5369 u64 wptr; 5370 5371 /* XXX check if swapping is necessary on BE */ 5372 if (ring->use_doorbell) 5373 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 5374 else 5375 BUG(); 5376 return wptr; 5377 } 5378 5379 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5380 { 5381 struct amdgpu_device *adev = ring->adev; 5382 5383 /* XXX check if swapping is necessary on BE */ 5384 if (ring->use_doorbell) { 5385 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5386 WDOORBELL64(ring->doorbell_index, ring->wptr); 5387 } else{ 5388 BUG(); /* only DOORBELL method supported on gfx9 now */ 5389 } 5390 } 5391 5392 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5393 u64 seq, unsigned int flags) 5394 { 5395 struct amdgpu_device *adev = ring->adev; 5396 5397 /* we only allocate 32bit for each seq wb address */ 5398 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5399 5400 /* write fence seq to the "addr" */ 5401 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5402 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5403 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5404 amdgpu_ring_write(ring, lower_32_bits(addr)); 5405 amdgpu_ring_write(ring, upper_32_bits(addr)); 5406 amdgpu_ring_write(ring, lower_32_bits(seq)); 5407 5408 if (flags & AMDGPU_FENCE_FLAG_INT) { 5409 /* set register to trigger INT */ 5410 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5411 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5412 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5413 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5414 amdgpu_ring_write(ring, 0); 5415 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5416 } 5417 } 5418 5419 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5420 { 5421 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5422 amdgpu_ring_write(ring, 0); 5423 } 5424 5425 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 5426 { 5427 struct v9_ce_ib_state ce_payload = {0}; 5428 uint64_t csa_addr; 5429 int cnt; 5430 5431 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5432 csa_addr = amdgpu_csa_vaddr(ring->adev); 5433 5434 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5435 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5436 WRITE_DATA_DST_SEL(8) | 5437 WR_CONFIRM) | 5438 WRITE_DATA_CACHE_POLICY(0)); 5439 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5440 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5441 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 5442 } 5443 5444 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 5445 { 5446 struct v9_de_ib_state de_payload = {0}; 5447 uint64_t csa_addr, gds_addr; 5448 int cnt; 5449 5450 csa_addr = amdgpu_csa_vaddr(ring->adev); 5451 gds_addr = csa_addr + 4096; 5452 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5453 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5454 5455 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5456 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5457 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5458 WRITE_DATA_DST_SEL(8) | 5459 WR_CONFIRM) | 5460 WRITE_DATA_CACHE_POLICY(0)); 5461 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5462 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5463 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 5464 } 5465 5466 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5467 bool secure) 5468 { 5469 uint32_t v = secure ? FRAME_TMZ : 0; 5470 5471 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5472 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5473 } 5474 5475 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5476 { 5477 uint32_t dw2 = 0; 5478 5479 if (amdgpu_sriov_vf(ring->adev)) 5480 gfx_v9_0_ring_emit_ce_meta(ring); 5481 5482 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5483 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5484 /* set load_global_config & load_global_uconfig */ 5485 dw2 |= 0x8001; 5486 /* set load_cs_sh_regs */ 5487 dw2 |= 0x01000000; 5488 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5489 dw2 |= 0x10002; 5490 5491 /* set load_ce_ram if preamble presented */ 5492 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5493 dw2 |= 0x10000000; 5494 } else { 5495 /* still load_ce_ram if this is the first time preamble presented 5496 * although there is no context switch happens. 5497 */ 5498 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5499 dw2 |= 0x10000000; 5500 } 5501 5502 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5503 amdgpu_ring_write(ring, dw2); 5504 amdgpu_ring_write(ring, 0); 5505 } 5506 5507 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5508 { 5509 unsigned ret; 5510 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5511 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5512 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5513 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5514 ret = ring->wptr & ring->buf_mask; 5515 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5516 return ret; 5517 } 5518 5519 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5520 { 5521 unsigned cur; 5522 BUG_ON(offset > ring->buf_mask); 5523 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5524 5525 cur = (ring->wptr & ring->buf_mask) - 1; 5526 if (likely(cur > offset)) 5527 ring->ring[offset] = cur - offset; 5528 else 5529 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5530 } 5531 5532 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5533 uint32_t reg_val_offs) 5534 { 5535 struct amdgpu_device *adev = ring->adev; 5536 5537 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5538 amdgpu_ring_write(ring, 0 | /* src: register*/ 5539 (5 << 8) | /* dst: memory */ 5540 (1 << 20)); /* write confirm */ 5541 amdgpu_ring_write(ring, reg); 5542 amdgpu_ring_write(ring, 0); 5543 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5544 reg_val_offs * 4)); 5545 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5546 reg_val_offs * 4)); 5547 } 5548 5549 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5550 uint32_t val) 5551 { 5552 uint32_t cmd = 0; 5553 5554 switch (ring->funcs->type) { 5555 case AMDGPU_RING_TYPE_GFX: 5556 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5557 break; 5558 case AMDGPU_RING_TYPE_KIQ: 5559 cmd = (1 << 16); /* no inc addr */ 5560 break; 5561 default: 5562 cmd = WR_CONFIRM; 5563 break; 5564 } 5565 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5566 amdgpu_ring_write(ring, cmd); 5567 amdgpu_ring_write(ring, reg); 5568 amdgpu_ring_write(ring, 0); 5569 amdgpu_ring_write(ring, val); 5570 } 5571 5572 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5573 uint32_t val, uint32_t mask) 5574 { 5575 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5576 } 5577 5578 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5579 uint32_t reg0, uint32_t reg1, 5580 uint32_t ref, uint32_t mask) 5581 { 5582 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5583 struct amdgpu_device *adev = ring->adev; 5584 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5585 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5586 5587 if (fw_version_ok) 5588 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5589 ref, mask, 0x20); 5590 else 5591 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5592 ref, mask); 5593 } 5594 5595 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5596 { 5597 struct amdgpu_device *adev = ring->adev; 5598 uint32_t value = 0; 5599 5600 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5601 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5602 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5603 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5604 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5605 } 5606 5607 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5608 enum amdgpu_interrupt_state state) 5609 { 5610 switch (state) { 5611 case AMDGPU_IRQ_STATE_DISABLE: 5612 case AMDGPU_IRQ_STATE_ENABLE: 5613 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5614 TIME_STAMP_INT_ENABLE, 5615 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5616 break; 5617 default: 5618 break; 5619 } 5620 } 5621 5622 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5623 int me, int pipe, 5624 enum amdgpu_interrupt_state state) 5625 { 5626 u32 mec_int_cntl, mec_int_cntl_reg; 5627 5628 /* 5629 * amdgpu controls only the first MEC. That's why this function only 5630 * handles the setting of interrupts for this specific MEC. All other 5631 * pipes' interrupts are set by amdkfd. 5632 */ 5633 5634 if (me == 1) { 5635 switch (pipe) { 5636 case 0: 5637 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5638 break; 5639 case 1: 5640 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5641 break; 5642 case 2: 5643 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5644 break; 5645 case 3: 5646 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5647 break; 5648 default: 5649 DRM_DEBUG("invalid pipe %d\n", pipe); 5650 return; 5651 } 5652 } else { 5653 DRM_DEBUG("invalid me %d\n", me); 5654 return; 5655 } 5656 5657 switch (state) { 5658 case AMDGPU_IRQ_STATE_DISABLE: 5659 mec_int_cntl = RREG32(mec_int_cntl_reg); 5660 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5661 TIME_STAMP_INT_ENABLE, 0); 5662 WREG32(mec_int_cntl_reg, mec_int_cntl); 5663 break; 5664 case AMDGPU_IRQ_STATE_ENABLE: 5665 mec_int_cntl = RREG32(mec_int_cntl_reg); 5666 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5667 TIME_STAMP_INT_ENABLE, 1); 5668 WREG32(mec_int_cntl_reg, mec_int_cntl); 5669 break; 5670 default: 5671 break; 5672 } 5673 } 5674 5675 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5676 struct amdgpu_irq_src *source, 5677 unsigned type, 5678 enum amdgpu_interrupt_state state) 5679 { 5680 switch (state) { 5681 case AMDGPU_IRQ_STATE_DISABLE: 5682 case AMDGPU_IRQ_STATE_ENABLE: 5683 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5684 PRIV_REG_INT_ENABLE, 5685 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5686 break; 5687 default: 5688 break; 5689 } 5690 5691 return 0; 5692 } 5693 5694 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5695 struct amdgpu_irq_src *source, 5696 unsigned type, 5697 enum amdgpu_interrupt_state state) 5698 { 5699 switch (state) { 5700 case AMDGPU_IRQ_STATE_DISABLE: 5701 case AMDGPU_IRQ_STATE_ENABLE: 5702 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5703 PRIV_INSTR_INT_ENABLE, 5704 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5705 break; 5706 default: 5707 break; 5708 } 5709 5710 return 0; 5711 } 5712 5713 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5714 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5715 CP_ECC_ERROR_INT_ENABLE, 1) 5716 5717 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5718 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5719 CP_ECC_ERROR_INT_ENABLE, 0) 5720 5721 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5722 struct amdgpu_irq_src *source, 5723 unsigned type, 5724 enum amdgpu_interrupt_state state) 5725 { 5726 switch (state) { 5727 case AMDGPU_IRQ_STATE_DISABLE: 5728 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5729 CP_ECC_ERROR_INT_ENABLE, 0); 5730 DISABLE_ECC_ON_ME_PIPE(1, 0); 5731 DISABLE_ECC_ON_ME_PIPE(1, 1); 5732 DISABLE_ECC_ON_ME_PIPE(1, 2); 5733 DISABLE_ECC_ON_ME_PIPE(1, 3); 5734 break; 5735 5736 case AMDGPU_IRQ_STATE_ENABLE: 5737 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5738 CP_ECC_ERROR_INT_ENABLE, 1); 5739 ENABLE_ECC_ON_ME_PIPE(1, 0); 5740 ENABLE_ECC_ON_ME_PIPE(1, 1); 5741 ENABLE_ECC_ON_ME_PIPE(1, 2); 5742 ENABLE_ECC_ON_ME_PIPE(1, 3); 5743 break; 5744 default: 5745 break; 5746 } 5747 5748 return 0; 5749 } 5750 5751 5752 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5753 struct amdgpu_irq_src *src, 5754 unsigned type, 5755 enum amdgpu_interrupt_state state) 5756 { 5757 switch (type) { 5758 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5759 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5760 break; 5761 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5762 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5763 break; 5764 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5765 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5766 break; 5767 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5768 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5769 break; 5770 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5771 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5772 break; 5773 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5774 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5775 break; 5776 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5777 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5778 break; 5779 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5780 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5781 break; 5782 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5783 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5784 break; 5785 default: 5786 break; 5787 } 5788 return 0; 5789 } 5790 5791 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5792 struct amdgpu_irq_src *source, 5793 struct amdgpu_iv_entry *entry) 5794 { 5795 int i; 5796 u8 me_id, pipe_id, queue_id; 5797 struct amdgpu_ring *ring; 5798 5799 DRM_DEBUG("IH: CP EOP\n"); 5800 me_id = (entry->ring_id & 0x0c) >> 2; 5801 pipe_id = (entry->ring_id & 0x03) >> 0; 5802 queue_id = (entry->ring_id & 0x70) >> 4; 5803 5804 switch (me_id) { 5805 case 0: 5806 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5807 break; 5808 case 1: 5809 case 2: 5810 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5811 ring = &adev->gfx.compute_ring[i]; 5812 /* Per-queue interrupt is supported for MEC starting from VI. 5813 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5814 */ 5815 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5816 amdgpu_fence_process(ring); 5817 } 5818 break; 5819 } 5820 return 0; 5821 } 5822 5823 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5824 struct amdgpu_iv_entry *entry) 5825 { 5826 u8 me_id, pipe_id, queue_id; 5827 struct amdgpu_ring *ring; 5828 int i; 5829 5830 me_id = (entry->ring_id & 0x0c) >> 2; 5831 pipe_id = (entry->ring_id & 0x03) >> 0; 5832 queue_id = (entry->ring_id & 0x70) >> 4; 5833 5834 switch (me_id) { 5835 case 0: 5836 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5837 break; 5838 case 1: 5839 case 2: 5840 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5841 ring = &adev->gfx.compute_ring[i]; 5842 if (ring->me == me_id && ring->pipe == pipe_id && 5843 ring->queue == queue_id) 5844 drm_sched_fault(&ring->sched); 5845 } 5846 break; 5847 } 5848 } 5849 5850 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5851 struct amdgpu_irq_src *source, 5852 struct amdgpu_iv_entry *entry) 5853 { 5854 DRM_ERROR("Illegal register access in command stream\n"); 5855 gfx_v9_0_fault(adev, entry); 5856 return 0; 5857 } 5858 5859 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5860 struct amdgpu_irq_src *source, 5861 struct amdgpu_iv_entry *entry) 5862 { 5863 DRM_ERROR("Illegal instruction in command stream\n"); 5864 gfx_v9_0_fault(adev, entry); 5865 return 0; 5866 } 5867 5868 5869 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5870 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5871 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5872 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5873 }, 5874 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5875 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5876 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5877 }, 5878 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5879 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5880 0, 0 5881 }, 5882 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5883 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5884 0, 0 5885 }, 5886 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5887 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5888 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5889 }, 5890 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5891 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5892 0, 0 5893 }, 5894 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5895 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5896 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5897 }, 5898 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5899 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5900 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5901 }, 5902 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5903 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5904 0, 0 5905 }, 5906 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5907 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5908 0, 0 5909 }, 5910 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5911 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5912 0, 0 5913 }, 5914 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5915 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5916 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5917 }, 5918 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5919 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5920 0, 0 5921 }, 5922 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5923 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5924 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5925 }, 5926 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5927 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5928 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5929 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5930 }, 5931 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5932 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5933 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5934 0, 0 5935 }, 5936 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5937 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5938 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5939 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5940 }, 5941 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5942 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5943 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5944 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5945 }, 5946 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5947 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5948 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5949 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5950 }, 5951 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5952 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5953 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5954 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5955 }, 5956 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5957 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5958 0, 0 5959 }, 5960 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5961 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5962 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5963 }, 5964 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5965 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5966 0, 0 5967 }, 5968 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5969 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5970 0, 0 5971 }, 5972 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5973 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 5974 0, 0 5975 }, 5976 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5977 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 5978 0, 0 5979 }, 5980 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5981 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 5982 0, 0 5983 }, 5984 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5985 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 5986 0, 0 5987 }, 5988 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5989 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 5990 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 5991 }, 5992 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5993 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 5994 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 5995 }, 5996 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5997 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 5998 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 5999 }, 6000 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6001 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6002 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6003 }, 6004 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6005 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6006 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6007 }, 6008 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6009 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6010 0, 0 6011 }, 6012 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6013 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6014 0, 0 6015 }, 6016 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6017 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6018 0, 0 6019 }, 6020 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6021 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6022 0, 0 6023 }, 6024 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6025 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6026 0, 0 6027 }, 6028 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6029 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6030 0, 0 6031 }, 6032 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6033 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6034 0, 0 6035 }, 6036 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6037 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6038 0, 0 6039 }, 6040 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6041 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6042 0, 0 6043 }, 6044 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6045 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6046 0, 0 6047 }, 6048 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6049 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6050 0, 0 6051 }, 6052 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6053 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6054 0, 0 6055 }, 6056 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6057 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6058 0, 0 6059 }, 6060 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6061 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6062 0, 0 6063 }, 6064 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6065 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6066 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6067 }, 6068 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6069 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6070 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6071 }, 6072 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6073 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6074 0, 0 6075 }, 6076 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6077 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6078 0, 0 6079 }, 6080 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6081 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6082 0, 0 6083 }, 6084 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6085 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6086 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6087 }, 6088 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6089 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6090 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6091 }, 6092 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6093 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6094 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6095 }, 6096 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6097 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6098 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6099 }, 6100 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6101 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6102 0, 0 6103 }, 6104 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6105 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6106 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6107 }, 6108 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6109 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6110 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6111 }, 6112 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6113 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6114 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6115 }, 6116 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6117 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6118 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6119 }, 6120 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6121 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6122 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6123 }, 6124 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6125 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6126 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6127 }, 6128 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6129 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6130 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6131 }, 6132 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6133 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6134 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6135 }, 6136 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6137 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6138 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6139 }, 6140 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6141 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6142 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6143 }, 6144 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6145 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6146 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6147 }, 6148 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6149 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6150 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6151 }, 6152 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6153 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6154 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6155 }, 6156 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6157 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6158 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6159 }, 6160 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6161 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6162 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6163 }, 6164 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6165 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6166 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6167 }, 6168 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6169 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6170 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6171 }, 6172 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6173 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6174 0, 0 6175 }, 6176 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6177 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6178 0, 0 6179 }, 6180 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6181 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6182 0, 0 6183 }, 6184 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6185 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6186 0, 0 6187 }, 6188 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6189 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6190 0, 0 6191 }, 6192 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6193 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6194 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6195 }, 6196 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6197 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6198 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6199 }, 6200 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6201 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6202 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6203 }, 6204 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6205 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6206 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6207 }, 6208 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6209 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6210 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6211 }, 6212 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6213 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6214 0, 0 6215 }, 6216 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6217 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6218 0, 0 6219 }, 6220 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6221 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6222 0, 0 6223 }, 6224 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6225 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6226 0, 0 6227 }, 6228 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6229 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6230 0, 0 6231 }, 6232 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6233 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6234 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6235 }, 6236 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6237 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6238 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6239 }, 6240 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6241 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6242 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6243 }, 6244 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6245 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6246 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6247 }, 6248 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6249 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6250 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6251 }, 6252 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6253 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6254 0, 0 6255 }, 6256 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6257 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6258 0, 0 6259 }, 6260 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6261 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6262 0, 0 6263 }, 6264 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6265 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6266 0, 0 6267 }, 6268 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6269 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6270 0, 0 6271 }, 6272 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6273 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6274 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6275 }, 6276 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6277 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6278 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6279 }, 6280 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6281 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6282 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6283 }, 6284 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6285 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6286 0, 0 6287 }, 6288 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6289 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6290 0, 0 6291 }, 6292 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6293 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6294 0, 0 6295 }, 6296 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6297 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6298 0, 0 6299 }, 6300 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6301 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6302 0, 0 6303 }, 6304 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6305 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6306 0, 0 6307 } 6308 }; 6309 6310 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6311 void *inject_if) 6312 { 6313 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6314 int ret; 6315 struct ta_ras_trigger_error_input block_info = { 0 }; 6316 6317 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6318 return -EINVAL; 6319 6320 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6321 return -EINVAL; 6322 6323 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6324 return -EPERM; 6325 6326 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6327 info->head.type)) { 6328 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6329 ras_gfx_subblocks[info->head.sub_block_index].name, 6330 info->head.type); 6331 return -EPERM; 6332 } 6333 6334 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6335 info->head.type)) { 6336 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6337 ras_gfx_subblocks[info->head.sub_block_index].name, 6338 info->head.type); 6339 return -EPERM; 6340 } 6341 6342 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6343 block_info.sub_block_index = 6344 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6345 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6346 block_info.address = info->address; 6347 block_info.value = info->value; 6348 6349 mutex_lock(&adev->grbm_idx_mutex); 6350 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6351 mutex_unlock(&adev->grbm_idx_mutex); 6352 6353 return ret; 6354 } 6355 6356 static const char *vml2_mems[] = { 6357 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6358 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6359 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6360 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6361 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6362 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6363 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6364 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6365 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6366 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6367 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6368 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6369 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6370 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6371 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6372 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6373 }; 6374 6375 static const char *vml2_walker_mems[] = { 6376 "UTC_VML2_CACHE_PDE0_MEM0", 6377 "UTC_VML2_CACHE_PDE0_MEM1", 6378 "UTC_VML2_CACHE_PDE1_MEM0", 6379 "UTC_VML2_CACHE_PDE1_MEM1", 6380 "UTC_VML2_CACHE_PDE2_MEM0", 6381 "UTC_VML2_CACHE_PDE2_MEM1", 6382 "UTC_VML2_RDIF_LOG_FIFO", 6383 }; 6384 6385 static const char *atc_l2_cache_2m_mems[] = { 6386 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6387 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6388 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6389 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6390 }; 6391 6392 static const char *atc_l2_cache_4k_mems[] = { 6393 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6394 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6395 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6396 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6397 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6398 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6399 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6400 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6401 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6402 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6403 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6404 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6405 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6406 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6407 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6408 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6409 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6410 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6411 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6412 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6413 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6414 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6415 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6416 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6417 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6418 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6419 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6420 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6421 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6422 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6423 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6424 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6425 }; 6426 6427 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6428 struct ras_err_data *err_data) 6429 { 6430 uint32_t i, data; 6431 uint32_t sec_count, ded_count; 6432 6433 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6434 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6435 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6436 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6437 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6438 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6439 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6440 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6441 6442 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6443 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6444 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6445 6446 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6447 if (sec_count) { 6448 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6449 "SEC %d\n", i, vml2_mems[i], sec_count); 6450 err_data->ce_count += sec_count; 6451 } 6452 6453 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6454 if (ded_count) { 6455 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6456 "DED %d\n", i, vml2_mems[i], ded_count); 6457 err_data->ue_count += ded_count; 6458 } 6459 } 6460 6461 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6462 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6463 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6464 6465 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6466 SEC_COUNT); 6467 if (sec_count) { 6468 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6469 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6470 err_data->ce_count += sec_count; 6471 } 6472 6473 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6474 DED_COUNT); 6475 if (ded_count) { 6476 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6477 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6478 err_data->ue_count += ded_count; 6479 } 6480 } 6481 6482 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6483 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6484 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6485 6486 sec_count = (data & 0x00006000L) >> 0xd; 6487 if (sec_count) { 6488 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6489 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6490 sec_count); 6491 err_data->ce_count += sec_count; 6492 } 6493 } 6494 6495 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6496 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6497 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6498 6499 sec_count = (data & 0x00006000L) >> 0xd; 6500 if (sec_count) { 6501 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6502 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6503 sec_count); 6504 err_data->ce_count += sec_count; 6505 } 6506 6507 ded_count = (data & 0x00018000L) >> 0xf; 6508 if (ded_count) { 6509 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6510 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6511 ded_count); 6512 err_data->ue_count += ded_count; 6513 } 6514 } 6515 6516 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6517 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6518 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6519 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6520 6521 return 0; 6522 } 6523 6524 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6525 const struct soc15_reg_entry *reg, 6526 uint32_t se_id, uint32_t inst_id, uint32_t value, 6527 uint32_t *sec_count, uint32_t *ded_count) 6528 { 6529 uint32_t i; 6530 uint32_t sec_cnt, ded_cnt; 6531 6532 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6533 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6534 gfx_v9_0_ras_fields[i].seg != reg->seg || 6535 gfx_v9_0_ras_fields[i].inst != reg->inst) 6536 continue; 6537 6538 sec_cnt = (value & 6539 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6540 gfx_v9_0_ras_fields[i].sec_count_shift; 6541 if (sec_cnt) { 6542 dev_info(adev->dev, "GFX SubBlock %s, " 6543 "Instance[%d][%d], SEC %d\n", 6544 gfx_v9_0_ras_fields[i].name, 6545 se_id, inst_id, 6546 sec_cnt); 6547 *sec_count += sec_cnt; 6548 } 6549 6550 ded_cnt = (value & 6551 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6552 gfx_v9_0_ras_fields[i].ded_count_shift; 6553 if (ded_cnt) { 6554 dev_info(adev->dev, "GFX SubBlock %s, " 6555 "Instance[%d][%d], DED %d\n", 6556 gfx_v9_0_ras_fields[i].name, 6557 se_id, inst_id, 6558 ded_cnt); 6559 *ded_count += ded_cnt; 6560 } 6561 } 6562 6563 return 0; 6564 } 6565 6566 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6567 { 6568 int i, j, k; 6569 6570 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6571 return; 6572 6573 /* read back registers to clear the counters */ 6574 mutex_lock(&adev->grbm_idx_mutex); 6575 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6576 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6577 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6578 gfx_v9_0_select_se_sh(adev, j, 0x0, k); 6579 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6580 } 6581 } 6582 } 6583 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6584 mutex_unlock(&adev->grbm_idx_mutex); 6585 6586 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6587 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6588 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6589 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6590 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6591 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6592 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6593 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6594 6595 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6596 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6597 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6598 } 6599 6600 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6601 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6602 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6603 } 6604 6605 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6606 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6607 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6608 } 6609 6610 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6611 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6612 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6613 } 6614 6615 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6616 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6617 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6618 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6619 } 6620 6621 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6622 void *ras_error_status) 6623 { 6624 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6625 uint32_t sec_count = 0, ded_count = 0; 6626 uint32_t i, j, k; 6627 uint32_t reg_value; 6628 6629 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6630 return -EINVAL; 6631 6632 err_data->ue_count = 0; 6633 err_data->ce_count = 0; 6634 6635 mutex_lock(&adev->grbm_idx_mutex); 6636 6637 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6638 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6639 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6640 gfx_v9_0_select_se_sh(adev, j, 0, k); 6641 reg_value = 6642 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6643 if (reg_value) 6644 gfx_v9_0_ras_error_count(adev, 6645 &gfx_v9_0_edc_counter_regs[i], 6646 j, k, reg_value, 6647 &sec_count, &ded_count); 6648 } 6649 } 6650 } 6651 6652 err_data->ce_count += sec_count; 6653 err_data->ue_count += ded_count; 6654 6655 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6656 mutex_unlock(&adev->grbm_idx_mutex); 6657 6658 gfx_v9_0_query_utc_edc_status(adev, err_data); 6659 6660 return 0; 6661 } 6662 6663 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6664 { 6665 const unsigned int cp_coher_cntl = 6666 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6667 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6668 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6669 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6670 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6671 6672 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6673 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6674 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6675 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6676 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6677 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6678 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6679 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6680 } 6681 6682 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6683 uint32_t pipe, bool enable) 6684 { 6685 struct amdgpu_device *adev = ring->adev; 6686 uint32_t val; 6687 uint32_t wcl_cs_reg; 6688 6689 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6690 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6691 6692 switch (pipe) { 6693 case 0: 6694 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6695 break; 6696 case 1: 6697 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6698 break; 6699 case 2: 6700 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6701 break; 6702 case 3: 6703 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6704 break; 6705 default: 6706 DRM_DEBUG("invalid pipe %d\n", pipe); 6707 return; 6708 } 6709 6710 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6711 6712 } 6713 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6714 { 6715 struct amdgpu_device *adev = ring->adev; 6716 uint32_t val; 6717 int i; 6718 6719 6720 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6721 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6722 * around 25% of gpu resources. 6723 */ 6724 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6725 amdgpu_ring_emit_wreg(ring, 6726 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6727 val); 6728 6729 /* Restrict waves for normal/low priority compute queues as well 6730 * to get best QoS for high priority compute jobs. 6731 * 6732 * amdgpu controls only 1st ME(0-3 CS pipes). 6733 */ 6734 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6735 if (i != ring->pipe) 6736 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6737 6738 } 6739 } 6740 6741 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6742 .name = "gfx_v9_0", 6743 .early_init = gfx_v9_0_early_init, 6744 .late_init = gfx_v9_0_late_init, 6745 .sw_init = gfx_v9_0_sw_init, 6746 .sw_fini = gfx_v9_0_sw_fini, 6747 .hw_init = gfx_v9_0_hw_init, 6748 .hw_fini = gfx_v9_0_hw_fini, 6749 .suspend = gfx_v9_0_suspend, 6750 .resume = gfx_v9_0_resume, 6751 .is_idle = gfx_v9_0_is_idle, 6752 .wait_for_idle = gfx_v9_0_wait_for_idle, 6753 .soft_reset = gfx_v9_0_soft_reset, 6754 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6755 .set_powergating_state = gfx_v9_0_set_powergating_state, 6756 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6757 }; 6758 6759 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6760 .type = AMDGPU_RING_TYPE_GFX, 6761 .align_mask = 0xff, 6762 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6763 .support_64bit_ptrs = true, 6764 .vmhub = AMDGPU_GFXHUB_0, 6765 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6766 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6767 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6768 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6769 5 + /* COND_EXEC */ 6770 7 + /* PIPELINE_SYNC */ 6771 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6772 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6773 2 + /* VM_FLUSH */ 6774 8 + /* FENCE for VM_FLUSH */ 6775 20 + /* GDS switch */ 6776 4 + /* double SWITCH_BUFFER, 6777 the first COND_EXEC jump to the place just 6778 prior to this double SWITCH_BUFFER */ 6779 5 + /* COND_EXEC */ 6780 7 + /* HDP_flush */ 6781 4 + /* VGT_flush */ 6782 14 + /* CE_META */ 6783 31 + /* DE_META */ 6784 3 + /* CNTX_CTRL */ 6785 5 + /* HDP_INVL */ 6786 8 + 8 + /* FENCE x2 */ 6787 2 + /* SWITCH_BUFFER */ 6788 7, /* gfx_v9_0_emit_mem_sync */ 6789 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6790 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6791 .emit_fence = gfx_v9_0_ring_emit_fence, 6792 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6793 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6794 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6795 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6796 .test_ring = gfx_v9_0_ring_test_ring, 6797 .test_ib = gfx_v9_0_ring_test_ib, 6798 .insert_nop = amdgpu_ring_insert_nop, 6799 .pad_ib = amdgpu_ring_generic_pad_ib, 6800 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6801 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6802 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6803 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6804 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6805 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6806 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6807 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6808 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6809 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6810 }; 6811 6812 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6813 .type = AMDGPU_RING_TYPE_COMPUTE, 6814 .align_mask = 0xff, 6815 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6816 .support_64bit_ptrs = true, 6817 .vmhub = AMDGPU_GFXHUB_0, 6818 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6819 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6820 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6821 .emit_frame_size = 6822 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6823 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6824 5 + /* hdp invalidate */ 6825 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6826 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6827 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6828 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6829 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6830 7 + /* gfx_v9_0_emit_mem_sync */ 6831 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6832 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6833 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6834 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6835 .emit_fence = gfx_v9_0_ring_emit_fence, 6836 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6837 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6838 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6839 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6840 .test_ring = gfx_v9_0_ring_test_ring, 6841 .test_ib = gfx_v9_0_ring_test_ib, 6842 .insert_nop = amdgpu_ring_insert_nop, 6843 .pad_ib = amdgpu_ring_generic_pad_ib, 6844 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6845 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6846 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6847 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6848 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6849 }; 6850 6851 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6852 .type = AMDGPU_RING_TYPE_KIQ, 6853 .align_mask = 0xff, 6854 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6855 .support_64bit_ptrs = true, 6856 .vmhub = AMDGPU_GFXHUB_0, 6857 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6858 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6859 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6860 .emit_frame_size = 6861 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6862 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6863 5 + /* hdp invalidate */ 6864 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6865 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6866 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6867 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6868 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6869 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6870 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6871 .test_ring = gfx_v9_0_ring_test_ring, 6872 .insert_nop = amdgpu_ring_insert_nop, 6873 .pad_ib = amdgpu_ring_generic_pad_ib, 6874 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6875 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6876 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6877 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6878 }; 6879 6880 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6881 { 6882 int i; 6883 6884 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6885 6886 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6887 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6888 6889 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6890 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6891 } 6892 6893 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6894 .set = gfx_v9_0_set_eop_interrupt_state, 6895 .process = gfx_v9_0_eop_irq, 6896 }; 6897 6898 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6899 .set = gfx_v9_0_set_priv_reg_fault_state, 6900 .process = gfx_v9_0_priv_reg_irq, 6901 }; 6902 6903 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6904 .set = gfx_v9_0_set_priv_inst_fault_state, 6905 .process = gfx_v9_0_priv_inst_irq, 6906 }; 6907 6908 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6909 .set = gfx_v9_0_set_cp_ecc_error_state, 6910 .process = amdgpu_gfx_cp_ecc_error_irq, 6911 }; 6912 6913 6914 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6915 { 6916 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6917 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 6918 6919 adev->gfx.priv_reg_irq.num_types = 1; 6920 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 6921 6922 adev->gfx.priv_inst_irq.num_types = 1; 6923 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 6924 6925 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 6926 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 6927 } 6928 6929 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 6930 { 6931 switch (adev->asic_type) { 6932 case CHIP_VEGA10: 6933 case CHIP_VEGA12: 6934 case CHIP_VEGA20: 6935 case CHIP_RAVEN: 6936 case CHIP_ARCTURUS: 6937 case CHIP_RENOIR: 6938 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 6939 break; 6940 default: 6941 break; 6942 } 6943 } 6944 6945 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 6946 { 6947 /* init asci gds info */ 6948 switch (adev->asic_type) { 6949 case CHIP_VEGA10: 6950 case CHIP_VEGA12: 6951 case CHIP_VEGA20: 6952 adev->gds.gds_size = 0x10000; 6953 break; 6954 case CHIP_RAVEN: 6955 case CHIP_ARCTURUS: 6956 adev->gds.gds_size = 0x1000; 6957 break; 6958 default: 6959 adev->gds.gds_size = 0x10000; 6960 break; 6961 } 6962 6963 switch (adev->asic_type) { 6964 case CHIP_VEGA10: 6965 case CHIP_VEGA20: 6966 adev->gds.gds_compute_max_wave_id = 0x7ff; 6967 break; 6968 case CHIP_VEGA12: 6969 adev->gds.gds_compute_max_wave_id = 0x27f; 6970 break; 6971 case CHIP_RAVEN: 6972 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 6973 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 6974 else 6975 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 6976 break; 6977 case CHIP_ARCTURUS: 6978 adev->gds.gds_compute_max_wave_id = 0xfff; 6979 break; 6980 default: 6981 /* this really depends on the chip */ 6982 adev->gds.gds_compute_max_wave_id = 0x7ff; 6983 break; 6984 } 6985 6986 adev->gds.gws_size = 64; 6987 adev->gds.oa_size = 16; 6988 } 6989 6990 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 6991 u32 bitmap) 6992 { 6993 u32 data; 6994 6995 if (!bitmap) 6996 return; 6997 6998 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6999 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7000 7001 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7002 } 7003 7004 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7005 { 7006 u32 data, mask; 7007 7008 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7009 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7010 7011 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7012 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7013 7014 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7015 7016 return (~data) & mask; 7017 } 7018 7019 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7020 struct amdgpu_cu_info *cu_info) 7021 { 7022 int i, j, k, counter, active_cu_number = 0; 7023 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7024 unsigned disable_masks[4 * 4]; 7025 7026 if (!adev || !cu_info) 7027 return -EINVAL; 7028 7029 /* 7030 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7031 */ 7032 if (adev->gfx.config.max_shader_engines * 7033 adev->gfx.config.max_sh_per_se > 16) 7034 return -EINVAL; 7035 7036 amdgpu_gfx_parse_disable_cu(disable_masks, 7037 adev->gfx.config.max_shader_engines, 7038 adev->gfx.config.max_sh_per_se); 7039 7040 mutex_lock(&adev->grbm_idx_mutex); 7041 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7042 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7043 mask = 1; 7044 ao_bitmap = 0; 7045 counter = 0; 7046 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 7047 gfx_v9_0_set_user_cu_inactive_bitmap( 7048 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7049 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7050 7051 /* 7052 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7053 * 4x4 size array, and it's usually suitable for Vega 7054 * ASICs which has 4*2 SE/SH layout. 7055 * But for Arcturus, SE/SH layout is changed to 8*1. 7056 * To mostly reduce the impact, we make it compatible 7057 * with current bitmap array as below: 7058 * SE4,SH0 --> bitmap[0][1] 7059 * SE5,SH0 --> bitmap[1][1] 7060 * SE6,SH0 --> bitmap[2][1] 7061 * SE7,SH0 --> bitmap[3][1] 7062 */ 7063 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 7064 7065 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7066 if (bitmap & mask) { 7067 if (counter < adev->gfx.config.max_cu_per_sh) 7068 ao_bitmap |= mask; 7069 counter ++; 7070 } 7071 mask <<= 1; 7072 } 7073 active_cu_number += counter; 7074 if (i < 2 && j < 2) 7075 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7076 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7077 } 7078 } 7079 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7080 mutex_unlock(&adev->grbm_idx_mutex); 7081 7082 cu_info->number = active_cu_number; 7083 cu_info->ao_cu_mask = ao_cu_mask; 7084 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7085 7086 return 0; 7087 } 7088 7089 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7090 { 7091 .type = AMD_IP_BLOCK_TYPE_GFX, 7092 .major = 9, 7093 .minor = 0, 7094 .rev = 0, 7095 .funcs = &gfx_v9_0_ip_funcs, 7096 }; 7097