1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 31 #include "vega10/soc15ip.h" 32 #include "vega10/GC/gc_9_0_offset.h" 33 #include "vega10/GC/gc_9_0_sh_mask.h" 34 #include "vega10/vega10_enum.h" 35 #include "vega10/HDP/hdp_4_0_offset.h" 36 37 #include "soc15_common.h" 38 #include "clearstate_gfx9.h" 39 #include "v9_structs.h" 40 41 #define GFX9_NUM_GFX_RINGS 1 42 #define GFX9_MEC_HPD_SIZE 2048 43 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 44 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 45 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34 46 47 #define mmPWR_MISC_CNTL_STATUS 0x0183 48 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 49 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 50 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 51 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 52 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 53 54 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 55 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 56 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 57 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 59 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 60 61 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 64 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 65 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 66 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 67 68 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 69 { 70 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), 71 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), 73 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) }, 74 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), 75 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), 76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), 77 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) }, 78 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), 79 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), 80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), 81 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) }, 82 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), 83 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), 84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), 85 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) }, 86 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), 87 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), 88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), 89 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) }, 90 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), 91 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), 92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), 93 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) }, 94 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), 95 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), 96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), 97 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) }, 98 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), 99 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), 100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), 101 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) }, 102 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), 103 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), 104 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), 105 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) }, 106 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), 107 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), 108 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), 109 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) }, 110 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), 111 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), 112 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), 113 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) }, 114 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), 115 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), 116 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), 117 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) }, 118 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), 119 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), 120 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), 121 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, 122 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), 123 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), 124 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), 125 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) }, 126 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), 127 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), 128 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), 129 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) }, 130 { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), 131 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), 132 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), 133 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) } 134 }; 135 136 static const u32 golden_settings_gc_9_0[] = 137 { 138 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, 139 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, 140 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, 141 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, 142 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 143 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, 144 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 146 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 147 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, 148 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, 149 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, 150 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, 151 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, 152 SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000, 153 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107, 154 SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000, 155 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 156 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, 157 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, 158 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, 159 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff, 160 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 161 }; 162 163 static const u32 golden_settings_gc_9_0_vg10[] = 164 { 165 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, 166 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 167 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, 168 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, 169 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, 170 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 171 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800 172 }; 173 174 static const u32 golden_settings_gc_9_1[] = 175 { 176 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104, 177 SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080, 178 SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080, 179 SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080, 180 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, 181 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 182 SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080, 183 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 184 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 185 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 186 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080, 187 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080, 188 SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080, 189 SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080, 190 SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080, 191 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 192 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000, 193 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120, 194 SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000, 195 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff, 196 SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080 197 }; 198 199 static const u32 golden_settings_gc_9_1_rv1[] = 200 { 201 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 202 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042, 203 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042, 204 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000, 205 SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000, 206 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 208 }; 209 210 static const u32 golden_settings_gc_9_x_common[] = 211 { 212 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000, 213 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382 214 }; 215 216 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 217 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 218 219 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 220 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 221 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 222 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 223 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 224 struct amdgpu_cu_info *cu_info); 225 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 226 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 227 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 228 229 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 230 { 231 switch (adev->asic_type) { 232 case CHIP_VEGA10: 233 amdgpu_program_register_sequence(adev, 234 golden_settings_gc_9_0, 235 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 236 amdgpu_program_register_sequence(adev, 237 golden_settings_gc_9_0_vg10, 238 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 239 break; 240 case CHIP_RAVEN: 241 amdgpu_program_register_sequence(adev, 242 golden_settings_gc_9_1, 243 (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); 244 amdgpu_program_register_sequence(adev, 245 golden_settings_gc_9_1_rv1, 246 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 247 break; 248 default: 249 break; 250 } 251 252 amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common, 253 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 254 } 255 256 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 257 { 258 adev->gfx.scratch.num_reg = 8; 259 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 260 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 261 } 262 263 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 264 bool wc, uint32_t reg, uint32_t val) 265 { 266 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 267 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 268 WRITE_DATA_DST_SEL(0) | 269 (wc ? WR_CONFIRM : 0)); 270 amdgpu_ring_write(ring, reg); 271 amdgpu_ring_write(ring, 0); 272 amdgpu_ring_write(ring, val); 273 } 274 275 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 276 int mem_space, int opt, uint32_t addr0, 277 uint32_t addr1, uint32_t ref, uint32_t mask, 278 uint32_t inv) 279 { 280 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 281 amdgpu_ring_write(ring, 282 /* memory (1) or register (0) */ 283 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 284 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 285 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 286 WAIT_REG_MEM_ENGINE(eng_sel))); 287 288 if (mem_space) 289 BUG_ON(addr0 & 0x3); /* Dword align */ 290 amdgpu_ring_write(ring, addr0); 291 amdgpu_ring_write(ring, addr1); 292 amdgpu_ring_write(ring, ref); 293 amdgpu_ring_write(ring, mask); 294 amdgpu_ring_write(ring, inv); /* poll interval */ 295 } 296 297 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 298 { 299 struct amdgpu_device *adev = ring->adev; 300 uint32_t scratch; 301 uint32_t tmp = 0; 302 unsigned i; 303 int r; 304 305 r = amdgpu_gfx_scratch_get(adev, &scratch); 306 if (r) { 307 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 308 return r; 309 } 310 WREG32(scratch, 0xCAFEDEAD); 311 r = amdgpu_ring_alloc(ring, 3); 312 if (r) { 313 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 314 ring->idx, r); 315 amdgpu_gfx_scratch_free(adev, scratch); 316 return r; 317 } 318 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 319 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 320 amdgpu_ring_write(ring, 0xDEADBEEF); 321 amdgpu_ring_commit(ring); 322 323 for (i = 0; i < adev->usec_timeout; i++) { 324 tmp = RREG32(scratch); 325 if (tmp == 0xDEADBEEF) 326 break; 327 DRM_UDELAY(1); 328 } 329 if (i < adev->usec_timeout) { 330 DRM_INFO("ring test on %d succeeded in %d usecs\n", 331 ring->idx, i); 332 } else { 333 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 334 ring->idx, scratch, tmp); 335 r = -EINVAL; 336 } 337 amdgpu_gfx_scratch_free(adev, scratch); 338 return r; 339 } 340 341 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 342 { 343 struct amdgpu_device *adev = ring->adev; 344 struct amdgpu_ib ib; 345 struct dma_fence *f = NULL; 346 uint32_t scratch; 347 uint32_t tmp = 0; 348 long r; 349 350 r = amdgpu_gfx_scratch_get(adev, &scratch); 351 if (r) { 352 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 353 return r; 354 } 355 WREG32(scratch, 0xCAFEDEAD); 356 memset(&ib, 0, sizeof(ib)); 357 r = amdgpu_ib_get(adev, NULL, 256, &ib); 358 if (r) { 359 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 360 goto err1; 361 } 362 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 363 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 364 ib.ptr[2] = 0xDEADBEEF; 365 ib.length_dw = 3; 366 367 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 368 if (r) 369 goto err2; 370 371 r = dma_fence_wait_timeout(f, false, timeout); 372 if (r == 0) { 373 DRM_ERROR("amdgpu: IB test timed out.\n"); 374 r = -ETIMEDOUT; 375 goto err2; 376 } else if (r < 0) { 377 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 378 goto err2; 379 } 380 tmp = RREG32(scratch); 381 if (tmp == 0xDEADBEEF) { 382 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 383 r = 0; 384 } else { 385 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 386 scratch, tmp); 387 r = -EINVAL; 388 } 389 err2: 390 amdgpu_ib_free(adev, &ib, NULL); 391 dma_fence_put(f); 392 err1: 393 amdgpu_gfx_scratch_free(adev, scratch); 394 return r; 395 } 396 397 398 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 399 { 400 release_firmware(adev->gfx.pfp_fw); 401 adev->gfx.pfp_fw = NULL; 402 release_firmware(adev->gfx.me_fw); 403 adev->gfx.me_fw = NULL; 404 release_firmware(adev->gfx.ce_fw); 405 adev->gfx.ce_fw = NULL; 406 release_firmware(adev->gfx.rlc_fw); 407 adev->gfx.rlc_fw = NULL; 408 release_firmware(adev->gfx.mec_fw); 409 adev->gfx.mec_fw = NULL; 410 release_firmware(adev->gfx.mec2_fw); 411 adev->gfx.mec2_fw = NULL; 412 413 kfree(adev->gfx.rlc.register_list_format); 414 } 415 416 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 417 { 418 const char *chip_name; 419 char fw_name[30]; 420 int err; 421 struct amdgpu_firmware_info *info = NULL; 422 const struct common_firmware_header *header = NULL; 423 const struct gfx_firmware_header_v1_0 *cp_hdr; 424 const struct rlc_firmware_header_v2_0 *rlc_hdr; 425 unsigned int *tmp = NULL; 426 unsigned int i = 0; 427 428 DRM_DEBUG("\n"); 429 430 switch (adev->asic_type) { 431 case CHIP_VEGA10: 432 chip_name = "vega10"; 433 break; 434 case CHIP_RAVEN: 435 chip_name = "raven"; 436 break; 437 default: 438 BUG(); 439 } 440 441 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 442 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 443 if (err) 444 goto out; 445 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 446 if (err) 447 goto out; 448 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 449 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 450 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 451 452 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 453 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 454 if (err) 455 goto out; 456 err = amdgpu_ucode_validate(adev->gfx.me_fw); 457 if (err) 458 goto out; 459 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 460 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 461 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 462 463 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 464 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 465 if (err) 466 goto out; 467 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 468 if (err) 469 goto out; 470 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 471 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 472 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 473 474 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 475 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 476 if (err) 477 goto out; 478 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 479 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 480 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 481 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 482 adev->gfx.rlc.save_and_restore_offset = 483 le32_to_cpu(rlc_hdr->save_and_restore_offset); 484 adev->gfx.rlc.clear_state_descriptor_offset = 485 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 486 adev->gfx.rlc.avail_scratch_ram_locations = 487 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 488 adev->gfx.rlc.reg_restore_list_size = 489 le32_to_cpu(rlc_hdr->reg_restore_list_size); 490 adev->gfx.rlc.reg_list_format_start = 491 le32_to_cpu(rlc_hdr->reg_list_format_start); 492 adev->gfx.rlc.reg_list_format_separate_start = 493 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 494 adev->gfx.rlc.starting_offsets_start = 495 le32_to_cpu(rlc_hdr->starting_offsets_start); 496 adev->gfx.rlc.reg_list_format_size_bytes = 497 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 498 adev->gfx.rlc.reg_list_size_bytes = 499 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 500 adev->gfx.rlc.register_list_format = 501 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 502 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 503 if (!adev->gfx.rlc.register_list_format) { 504 err = -ENOMEM; 505 goto out; 506 } 507 508 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 509 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 510 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 511 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 512 513 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 514 515 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 516 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 517 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 518 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 519 520 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 521 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 522 if (err) 523 goto out; 524 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 525 if (err) 526 goto out; 527 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 528 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 529 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 530 531 532 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 533 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 534 if (!err) { 535 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 536 if (err) 537 goto out; 538 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 539 adev->gfx.mec2_fw->data; 540 adev->gfx.mec2_fw_version = 541 le32_to_cpu(cp_hdr->header.ucode_version); 542 adev->gfx.mec2_feature_version = 543 le32_to_cpu(cp_hdr->ucode_feature_version); 544 } else { 545 err = 0; 546 adev->gfx.mec2_fw = NULL; 547 } 548 549 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 550 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 551 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 552 info->fw = adev->gfx.pfp_fw; 553 header = (const struct common_firmware_header *)info->fw->data; 554 adev->firmware.fw_size += 555 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 556 557 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 558 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 559 info->fw = adev->gfx.me_fw; 560 header = (const struct common_firmware_header *)info->fw->data; 561 adev->firmware.fw_size += 562 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 563 564 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 565 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 566 info->fw = adev->gfx.ce_fw; 567 header = (const struct common_firmware_header *)info->fw->data; 568 adev->firmware.fw_size += 569 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 570 571 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 572 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 573 info->fw = adev->gfx.rlc_fw; 574 header = (const struct common_firmware_header *)info->fw->data; 575 adev->firmware.fw_size += 576 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 577 578 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 579 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 580 info->fw = adev->gfx.mec_fw; 581 header = (const struct common_firmware_header *)info->fw->data; 582 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 583 adev->firmware.fw_size += 584 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 585 586 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 587 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 588 info->fw = adev->gfx.mec_fw; 589 adev->firmware.fw_size += 590 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 591 592 if (adev->gfx.mec2_fw) { 593 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 594 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 595 info->fw = adev->gfx.mec2_fw; 596 header = (const struct common_firmware_header *)info->fw->data; 597 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 598 adev->firmware.fw_size += 599 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 600 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 601 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 602 info->fw = adev->gfx.mec2_fw; 603 adev->firmware.fw_size += 604 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 605 } 606 607 } 608 609 out: 610 if (err) { 611 dev_err(adev->dev, 612 "gfx9: Failed to load firmware \"%s\"\n", 613 fw_name); 614 release_firmware(adev->gfx.pfp_fw); 615 adev->gfx.pfp_fw = NULL; 616 release_firmware(adev->gfx.me_fw); 617 adev->gfx.me_fw = NULL; 618 release_firmware(adev->gfx.ce_fw); 619 adev->gfx.ce_fw = NULL; 620 release_firmware(adev->gfx.rlc_fw); 621 adev->gfx.rlc_fw = NULL; 622 release_firmware(adev->gfx.mec_fw); 623 adev->gfx.mec_fw = NULL; 624 release_firmware(adev->gfx.mec2_fw); 625 adev->gfx.mec2_fw = NULL; 626 } 627 return err; 628 } 629 630 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 631 { 632 u32 count = 0; 633 const struct cs_section_def *sect = NULL; 634 const struct cs_extent_def *ext = NULL; 635 636 /* begin clear state */ 637 count += 2; 638 /* context control state */ 639 count += 3; 640 641 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 642 for (ext = sect->section; ext->extent != NULL; ++ext) { 643 if (sect->id == SECT_CONTEXT) 644 count += 2 + ext->reg_count; 645 else 646 return 0; 647 } 648 } 649 650 /* end clear state */ 651 count += 2; 652 /* clear state */ 653 count += 2; 654 655 return count; 656 } 657 658 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 659 volatile u32 *buffer) 660 { 661 u32 count = 0, i; 662 const struct cs_section_def *sect = NULL; 663 const struct cs_extent_def *ext = NULL; 664 665 if (adev->gfx.rlc.cs_data == NULL) 666 return; 667 if (buffer == NULL) 668 return; 669 670 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 671 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 672 673 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 674 buffer[count++] = cpu_to_le32(0x80000000); 675 buffer[count++] = cpu_to_le32(0x80000000); 676 677 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 678 for (ext = sect->section; ext->extent != NULL; ++ext) { 679 if (sect->id == SECT_CONTEXT) { 680 buffer[count++] = 681 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 682 buffer[count++] = cpu_to_le32(ext->reg_index - 683 PACKET3_SET_CONTEXT_REG_START); 684 for (i = 0; i < ext->reg_count; i++) 685 buffer[count++] = cpu_to_le32(ext->extent[i]); 686 } else { 687 return; 688 } 689 } 690 } 691 692 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 693 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 694 695 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 696 buffer[count++] = cpu_to_le32(0); 697 } 698 699 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 700 { 701 uint32_t data; 702 703 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 704 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 705 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 706 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 707 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 708 709 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 710 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 711 712 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 713 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 714 715 mutex_lock(&adev->grbm_idx_mutex); 716 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 717 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 718 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 719 720 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 721 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 722 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 723 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 724 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 725 726 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 727 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 728 data &= 0x0000FFFF; 729 data |= 0x00C00000; 730 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 731 732 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */ 733 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF); 734 735 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 736 * but used for RLC_LB_CNTL configuration */ 737 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 738 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 739 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 740 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 741 mutex_unlock(&adev->grbm_idx_mutex); 742 } 743 744 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 745 { 746 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 747 } 748 749 static void rv_init_cp_jump_table(struct amdgpu_device *adev) 750 { 751 const __le32 *fw_data; 752 volatile u32 *dst_ptr; 753 int me, i, max_me = 5; 754 u32 bo_offset = 0; 755 u32 table_offset, table_size; 756 757 /* write the cp table buffer */ 758 dst_ptr = adev->gfx.rlc.cp_table_ptr; 759 for (me = 0; me < max_me; me++) { 760 if (me == 0) { 761 const struct gfx_firmware_header_v1_0 *hdr = 762 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 763 fw_data = (const __le32 *) 764 (adev->gfx.ce_fw->data + 765 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 766 table_offset = le32_to_cpu(hdr->jt_offset); 767 table_size = le32_to_cpu(hdr->jt_size); 768 } else if (me == 1) { 769 const struct gfx_firmware_header_v1_0 *hdr = 770 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 771 fw_data = (const __le32 *) 772 (adev->gfx.pfp_fw->data + 773 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 774 table_offset = le32_to_cpu(hdr->jt_offset); 775 table_size = le32_to_cpu(hdr->jt_size); 776 } else if (me == 2) { 777 const struct gfx_firmware_header_v1_0 *hdr = 778 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 779 fw_data = (const __le32 *) 780 (adev->gfx.me_fw->data + 781 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 782 table_offset = le32_to_cpu(hdr->jt_offset); 783 table_size = le32_to_cpu(hdr->jt_size); 784 } else if (me == 3) { 785 const struct gfx_firmware_header_v1_0 *hdr = 786 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 787 fw_data = (const __le32 *) 788 (adev->gfx.mec_fw->data + 789 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 790 table_offset = le32_to_cpu(hdr->jt_offset); 791 table_size = le32_to_cpu(hdr->jt_size); 792 } else if (me == 4) { 793 const struct gfx_firmware_header_v1_0 *hdr = 794 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 795 fw_data = (const __le32 *) 796 (adev->gfx.mec2_fw->data + 797 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 798 table_offset = le32_to_cpu(hdr->jt_offset); 799 table_size = le32_to_cpu(hdr->jt_size); 800 } 801 802 for (i = 0; i < table_size; i ++) { 803 dst_ptr[bo_offset + i] = 804 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 805 } 806 807 bo_offset += table_size; 808 } 809 } 810 811 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) 812 { 813 /* clear state block */ 814 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 815 &adev->gfx.rlc.clear_state_gpu_addr, 816 (void **)&adev->gfx.rlc.cs_ptr); 817 818 /* jump table block */ 819 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 820 &adev->gfx.rlc.cp_table_gpu_addr, 821 (void **)&adev->gfx.rlc.cp_table_ptr); 822 } 823 824 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 825 { 826 volatile u32 *dst_ptr; 827 u32 dws; 828 const struct cs_section_def *cs_data; 829 int r; 830 831 adev->gfx.rlc.cs_data = gfx9_cs_data; 832 833 cs_data = adev->gfx.rlc.cs_data; 834 835 if (cs_data) { 836 /* clear state block */ 837 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); 838 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 839 AMDGPU_GEM_DOMAIN_VRAM, 840 &adev->gfx.rlc.clear_state_obj, 841 &adev->gfx.rlc.clear_state_gpu_addr, 842 (void **)&adev->gfx.rlc.cs_ptr); 843 if (r) { 844 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", 845 r); 846 gfx_v9_0_rlc_fini(adev); 847 return r; 848 } 849 /* set up the cs buffer */ 850 dst_ptr = adev->gfx.rlc.cs_ptr; 851 gfx_v9_0_get_csb_buffer(adev, dst_ptr); 852 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 853 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 854 } 855 856 if (adev->asic_type == CHIP_RAVEN) { 857 /* TODO: double check the cp_table_size for RV */ 858 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 859 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, 860 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 861 &adev->gfx.rlc.cp_table_obj, 862 &adev->gfx.rlc.cp_table_gpu_addr, 863 (void **)&adev->gfx.rlc.cp_table_ptr); 864 if (r) { 865 dev_err(adev->dev, 866 "(%d) failed to create cp table bo\n", r); 867 gfx_v9_0_rlc_fini(adev); 868 return r; 869 } 870 871 rv_init_cp_jump_table(adev); 872 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 873 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 874 875 gfx_v9_0_init_lbpw(adev); 876 } 877 878 return 0; 879 } 880 881 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 882 { 883 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 884 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 885 } 886 887 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 888 { 889 int r; 890 u32 *hpd; 891 const __le32 *fw_data; 892 unsigned fw_size; 893 u32 *fw; 894 size_t mec_hpd_size; 895 896 const struct gfx_firmware_header_v1_0 *mec_hdr; 897 898 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 899 900 /* take ownership of the relevant compute queues */ 901 amdgpu_gfx_compute_queue_acquire(adev); 902 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 903 904 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 905 AMDGPU_GEM_DOMAIN_GTT, 906 &adev->gfx.mec.hpd_eop_obj, 907 &adev->gfx.mec.hpd_eop_gpu_addr, 908 (void **)&hpd); 909 if (r) { 910 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 911 gfx_v9_0_mec_fini(adev); 912 return r; 913 } 914 915 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 916 917 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 918 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 919 920 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 921 922 fw_data = (const __le32 *) 923 (adev->gfx.mec_fw->data + 924 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 925 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 926 927 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 928 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 929 &adev->gfx.mec.mec_fw_obj, 930 &adev->gfx.mec.mec_fw_gpu_addr, 931 (void **)&fw); 932 if (r) { 933 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 934 gfx_v9_0_mec_fini(adev); 935 return r; 936 } 937 938 memcpy(fw, fw_data, fw_size); 939 940 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 941 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 942 943 return 0; 944 } 945 946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 947 { 948 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 949 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 950 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 951 (address << SQ_IND_INDEX__INDEX__SHIFT) | 952 (SQ_IND_INDEX__FORCE_READ_MASK)); 953 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 954 } 955 956 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 957 uint32_t wave, uint32_t thread, 958 uint32_t regno, uint32_t num, uint32_t *out) 959 { 960 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 961 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 962 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 963 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 964 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 965 (SQ_IND_INDEX__FORCE_READ_MASK) | 966 (SQ_IND_INDEX__AUTO_INCR_MASK)); 967 while (num--) 968 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 969 } 970 971 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 972 { 973 /* type 1 wave data */ 974 dst[(*no_fields)++] = 1; 975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 989 } 990 991 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 992 uint32_t wave, uint32_t start, 993 uint32_t size, uint32_t *dst) 994 { 995 wave_read_regs( 996 adev, simd, wave, 0, 997 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 998 } 999 1000 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1001 uint32_t wave, uint32_t thread, 1002 uint32_t start, uint32_t size, 1003 uint32_t *dst) 1004 { 1005 wave_read_regs( 1006 adev, simd, wave, thread, 1007 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1008 } 1009 1010 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1011 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1012 .select_se_sh = &gfx_v9_0_select_se_sh, 1013 .read_wave_data = &gfx_v9_0_read_wave_data, 1014 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1015 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1016 }; 1017 1018 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1019 { 1020 u32 gb_addr_config; 1021 1022 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1023 1024 switch (adev->asic_type) { 1025 case CHIP_VEGA10: 1026 adev->gfx.config.max_hw_contexts = 8; 1027 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1028 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1029 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1030 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1031 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1032 break; 1033 case CHIP_RAVEN: 1034 adev->gfx.config.max_hw_contexts = 8; 1035 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1036 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1037 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1038 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1039 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1040 break; 1041 default: 1042 BUG(); 1043 break; 1044 } 1045 1046 adev->gfx.config.gb_addr_config = gb_addr_config; 1047 1048 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1049 REG_GET_FIELD( 1050 adev->gfx.config.gb_addr_config, 1051 GB_ADDR_CONFIG, 1052 NUM_PIPES); 1053 1054 adev->gfx.config.max_tile_pipes = 1055 adev->gfx.config.gb_addr_config_fields.num_pipes; 1056 1057 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1058 REG_GET_FIELD( 1059 adev->gfx.config.gb_addr_config, 1060 GB_ADDR_CONFIG, 1061 NUM_BANKS); 1062 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1063 REG_GET_FIELD( 1064 adev->gfx.config.gb_addr_config, 1065 GB_ADDR_CONFIG, 1066 MAX_COMPRESSED_FRAGS); 1067 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1068 REG_GET_FIELD( 1069 adev->gfx.config.gb_addr_config, 1070 GB_ADDR_CONFIG, 1071 NUM_RB_PER_SE); 1072 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1073 REG_GET_FIELD( 1074 adev->gfx.config.gb_addr_config, 1075 GB_ADDR_CONFIG, 1076 NUM_SHADER_ENGINES); 1077 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1078 REG_GET_FIELD( 1079 adev->gfx.config.gb_addr_config, 1080 GB_ADDR_CONFIG, 1081 PIPE_INTERLEAVE_SIZE)); 1082 } 1083 1084 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1085 struct amdgpu_ngg_buf *ngg_buf, 1086 int size_se, 1087 int default_size_se) 1088 { 1089 int r; 1090 1091 if (size_se < 0) { 1092 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1093 return -EINVAL; 1094 } 1095 size_se = size_se ? size_se : default_size_se; 1096 1097 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1098 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1099 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1100 &ngg_buf->bo, 1101 &ngg_buf->gpu_addr, 1102 NULL); 1103 if (r) { 1104 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1105 return r; 1106 } 1107 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1108 1109 return r; 1110 } 1111 1112 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1113 { 1114 int i; 1115 1116 for (i = 0; i < NGG_BUF_MAX; i++) 1117 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1118 &adev->gfx.ngg.buf[i].gpu_addr, 1119 NULL); 1120 1121 memset(&adev->gfx.ngg.buf[0], 0, 1122 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1123 1124 adev->gfx.ngg.init = false; 1125 1126 return 0; 1127 } 1128 1129 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1130 { 1131 int r; 1132 1133 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1134 return 0; 1135 1136 /* GDS reserve memory: 64 bytes alignment */ 1137 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1138 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1139 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1140 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; 1141 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; 1142 1143 /* Primitive Buffer */ 1144 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1145 amdgpu_prim_buf_per_se, 1146 64 * 1024); 1147 if (r) { 1148 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1149 goto err; 1150 } 1151 1152 /* Position Buffer */ 1153 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1154 amdgpu_pos_buf_per_se, 1155 256 * 1024); 1156 if (r) { 1157 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1158 goto err; 1159 } 1160 1161 /* Control Sideband */ 1162 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1163 amdgpu_cntl_sb_buf_per_se, 1164 256); 1165 if (r) { 1166 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1167 goto err; 1168 } 1169 1170 /* Parameter Cache, not created by default */ 1171 if (amdgpu_param_buf_per_se <= 0) 1172 goto out; 1173 1174 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1175 amdgpu_param_buf_per_se, 1176 512 * 1024); 1177 if (r) { 1178 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1179 goto err; 1180 } 1181 1182 out: 1183 adev->gfx.ngg.init = true; 1184 return 0; 1185 err: 1186 gfx_v9_0_ngg_fini(adev); 1187 return r; 1188 } 1189 1190 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1191 { 1192 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1193 int r; 1194 u32 data, base; 1195 1196 if (!amdgpu_ngg) 1197 return 0; 1198 1199 /* Program buffer size */ 1200 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, 1201 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); 1202 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, 1203 adev->gfx.ngg.buf[NGG_POS].size >> 8); 1204 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1205 1206 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, 1207 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); 1208 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, 1209 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); 1210 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1211 1212 /* Program buffer base address */ 1213 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1214 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1215 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1216 1217 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1218 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1219 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1220 1221 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1222 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1223 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1224 1225 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1226 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1227 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1228 1229 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1230 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1231 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1232 1233 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1234 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1235 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1236 1237 /* Clear GDS reserved memory */ 1238 r = amdgpu_ring_alloc(ring, 17); 1239 if (r) { 1240 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", 1241 ring->idx, r); 1242 return r; 1243 } 1244 1245 gfx_v9_0_write_data_to_reg(ring, 0, false, 1246 amdgpu_gds_reg_offset[0].mem_size, 1247 (adev->gds.mem.total_size + 1248 adev->gfx.ngg.gds_reserve_size) >> 1249 AMDGPU_GDS_SHIFT); 1250 1251 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1252 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1253 PACKET3_DMA_DATA_SRC_SEL(2))); 1254 amdgpu_ring_write(ring, 0); 1255 amdgpu_ring_write(ring, 0); 1256 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1257 amdgpu_ring_write(ring, 0); 1258 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); 1259 1260 1261 gfx_v9_0_write_data_to_reg(ring, 0, false, 1262 amdgpu_gds_reg_offset[0].mem_size, 0); 1263 1264 amdgpu_ring_commit(ring); 1265 1266 return 0; 1267 } 1268 1269 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1270 int mec, int pipe, int queue) 1271 { 1272 int r; 1273 unsigned irq_type; 1274 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1275 1276 ring = &adev->gfx.compute_ring[ring_id]; 1277 1278 /* mec0 is me1 */ 1279 ring->me = mec + 1; 1280 ring->pipe = pipe; 1281 ring->queue = queue; 1282 1283 ring->ring_obj = NULL; 1284 ring->use_doorbell = true; 1285 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; 1286 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1287 + (ring_id * GFX9_MEC_HPD_SIZE); 1288 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1289 1290 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1291 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1292 + ring->pipe; 1293 1294 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1295 r = amdgpu_ring_init(adev, ring, 1024, 1296 &adev->gfx.eop_irq, irq_type); 1297 if (r) 1298 return r; 1299 1300 1301 return 0; 1302 } 1303 1304 static int gfx_v9_0_sw_init(void *handle) 1305 { 1306 int i, j, k, r, ring_id; 1307 struct amdgpu_ring *ring; 1308 struct amdgpu_kiq *kiq; 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1310 1311 switch (adev->asic_type) { 1312 case CHIP_VEGA10: 1313 case CHIP_RAVEN: 1314 adev->gfx.mec.num_mec = 2; 1315 break; 1316 default: 1317 adev->gfx.mec.num_mec = 1; 1318 break; 1319 } 1320 1321 adev->gfx.mec.num_pipe_per_mec = 4; 1322 adev->gfx.mec.num_queue_per_pipe = 8; 1323 1324 /* KIQ event */ 1325 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); 1326 if (r) 1327 return r; 1328 1329 /* EOP Event */ 1330 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); 1331 if (r) 1332 return r; 1333 1334 /* Privileged reg */ 1335 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, 1336 &adev->gfx.priv_reg_irq); 1337 if (r) 1338 return r; 1339 1340 /* Privileged inst */ 1341 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, 1342 &adev->gfx.priv_inst_irq); 1343 if (r) 1344 return r; 1345 1346 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1347 1348 gfx_v9_0_scratch_init(adev); 1349 1350 r = gfx_v9_0_init_microcode(adev); 1351 if (r) { 1352 DRM_ERROR("Failed to load gfx firmware!\n"); 1353 return r; 1354 } 1355 1356 r = gfx_v9_0_rlc_init(adev); 1357 if (r) { 1358 DRM_ERROR("Failed to init rlc BOs!\n"); 1359 return r; 1360 } 1361 1362 r = gfx_v9_0_mec_init(adev); 1363 if (r) { 1364 DRM_ERROR("Failed to init MEC BOs!\n"); 1365 return r; 1366 } 1367 1368 /* set up the gfx ring */ 1369 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1370 ring = &adev->gfx.gfx_ring[i]; 1371 ring->ring_obj = NULL; 1372 if (!i) 1373 sprintf(ring->name, "gfx"); 1374 else 1375 sprintf(ring->name, "gfx_%d", i); 1376 ring->use_doorbell = true; 1377 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; 1378 r = amdgpu_ring_init(adev, ring, 1024, 1379 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1380 if (r) 1381 return r; 1382 } 1383 1384 /* set up the compute queues - allocate horizontally across pipes */ 1385 ring_id = 0; 1386 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1387 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1388 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1389 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 1390 continue; 1391 1392 r = gfx_v9_0_compute_ring_init(adev, 1393 ring_id, 1394 i, k, j); 1395 if (r) 1396 return r; 1397 1398 ring_id++; 1399 } 1400 } 1401 } 1402 1403 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 1404 if (r) { 1405 DRM_ERROR("Failed to init KIQ BOs!\n"); 1406 return r; 1407 } 1408 1409 kiq = &adev->gfx.kiq; 1410 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1411 if (r) 1412 return r; 1413 1414 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1415 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 1416 if (r) 1417 return r; 1418 1419 /* reserve GDS, GWS and OA resource for gfx */ 1420 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 1421 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 1422 &adev->gds.gds_gfx_bo, NULL, NULL); 1423 if (r) 1424 return r; 1425 1426 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 1427 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 1428 &adev->gds.gws_gfx_bo, NULL, NULL); 1429 if (r) 1430 return r; 1431 1432 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 1433 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 1434 &adev->gds.oa_gfx_bo, NULL, NULL); 1435 if (r) 1436 return r; 1437 1438 adev->gfx.ce_ram_size = 0x8000; 1439 1440 gfx_v9_0_gpu_early_init(adev); 1441 1442 r = gfx_v9_0_ngg_init(adev); 1443 if (r) 1444 return r; 1445 1446 return 0; 1447 } 1448 1449 1450 static int gfx_v9_0_sw_fini(void *handle) 1451 { 1452 int i; 1453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1454 1455 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1456 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1457 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1458 1459 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1460 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1461 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1462 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1463 1464 amdgpu_gfx_compute_mqd_sw_fini(adev); 1465 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1466 amdgpu_gfx_kiq_fini(adev); 1467 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); 1468 1469 gfx_v9_0_mec_fini(adev); 1470 gfx_v9_0_ngg_fini(adev); 1471 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1472 &adev->gfx.rlc.clear_state_gpu_addr, 1473 (void **)&adev->gfx.rlc.cs_ptr); 1474 if (adev->asic_type == CHIP_RAVEN) { 1475 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1476 &adev->gfx.rlc.cp_table_gpu_addr, 1477 (void **)&adev->gfx.rlc.cp_table_ptr); 1478 } 1479 gfx_v9_0_free_microcode(adev); 1480 1481 return 0; 1482 } 1483 1484 1485 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1486 { 1487 /* TODO */ 1488 } 1489 1490 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1491 { 1492 u32 data; 1493 1494 if (instance == 0xffffffff) 1495 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1496 else 1497 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1498 1499 if (se_num == 0xffffffff) 1500 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1501 else 1502 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1503 1504 if (sh_num == 0xffffffff) 1505 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1506 else 1507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1508 1509 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1510 } 1511 1512 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1513 { 1514 u32 data, mask; 1515 1516 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1517 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1518 1519 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1520 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1521 1522 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1523 adev->gfx.config.max_sh_per_se); 1524 1525 return (~data) & mask; 1526 } 1527 1528 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1529 { 1530 int i, j; 1531 u32 data; 1532 u32 active_rbs = 0; 1533 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1534 adev->gfx.config.max_sh_per_se; 1535 1536 mutex_lock(&adev->grbm_idx_mutex); 1537 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1538 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1539 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1540 data = gfx_v9_0_get_rb_active_bitmap(adev); 1541 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1542 rb_bitmap_width_per_sh); 1543 } 1544 } 1545 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1546 mutex_unlock(&adev->grbm_idx_mutex); 1547 1548 adev->gfx.config.backend_enable_mask = active_rbs; 1549 adev->gfx.config.num_rbs = hweight32(active_rbs); 1550 } 1551 1552 #define DEFAULT_SH_MEM_BASES (0x6000) 1553 #define FIRST_COMPUTE_VMID (8) 1554 #define LAST_COMPUTE_VMID (16) 1555 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1556 { 1557 int i; 1558 uint32_t sh_mem_config; 1559 uint32_t sh_mem_bases; 1560 1561 /* 1562 * Configure apertures: 1563 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1564 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1565 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1566 */ 1567 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1568 1569 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1570 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1571 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1572 1573 mutex_lock(&adev->srbm_mutex); 1574 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1575 soc15_grbm_select(adev, 0, 0, 0, i); 1576 /* CP and shaders */ 1577 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1578 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1579 } 1580 soc15_grbm_select(adev, 0, 0, 0, 0); 1581 mutex_unlock(&adev->srbm_mutex); 1582 } 1583 1584 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 1585 { 1586 u32 tmp; 1587 int i; 1588 1589 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1590 1591 gfx_v9_0_tiling_mode_table_init(adev); 1592 1593 gfx_v9_0_setup_rb(adev); 1594 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1595 1596 /* XXX SH_MEM regs */ 1597 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1598 mutex_lock(&adev->srbm_mutex); 1599 for (i = 0; i < 16; i++) { 1600 soc15_grbm_select(adev, 0, 0, 0, i); 1601 /* CP and shaders */ 1602 tmp = 0; 1603 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 1604 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1605 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1606 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1607 } 1608 soc15_grbm_select(adev, 0, 0, 0, 0); 1609 1610 mutex_unlock(&adev->srbm_mutex); 1611 1612 gfx_v9_0_init_compute_vmid(adev); 1613 1614 mutex_lock(&adev->grbm_idx_mutex); 1615 /* 1616 * making sure that the following register writes will be broadcasted 1617 * to all the shaders 1618 */ 1619 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1620 1621 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1622 (adev->gfx.config.sc_prim_fifo_size_frontend << 1623 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1624 (adev->gfx.config.sc_prim_fifo_size_backend << 1625 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1626 (adev->gfx.config.sc_hiz_tile_fifo_size << 1627 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1628 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1629 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1630 mutex_unlock(&adev->grbm_idx_mutex); 1631 1632 } 1633 1634 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1635 { 1636 u32 i, j, k; 1637 u32 mask; 1638 1639 mutex_lock(&adev->grbm_idx_mutex); 1640 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1641 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1642 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1643 for (k = 0; k < adev->usec_timeout; k++) { 1644 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1645 break; 1646 udelay(1); 1647 } 1648 } 1649 } 1650 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1651 mutex_unlock(&adev->grbm_idx_mutex); 1652 1653 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1654 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1655 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1656 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1657 for (k = 0; k < adev->usec_timeout; k++) { 1658 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1659 break; 1660 udelay(1); 1661 } 1662 } 1663 1664 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1665 bool enable) 1666 { 1667 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1668 1669 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1670 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1671 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1672 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1673 1674 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1675 } 1676 1677 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 1678 { 1679 /* csib */ 1680 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 1681 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1682 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 1683 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1684 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 1685 adev->gfx.rlc.clear_state_size); 1686 } 1687 1688 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format, 1689 int indirect_offset, 1690 int list_size, 1691 int *unique_indirect_regs, 1692 int *unique_indirect_reg_count, 1693 int max_indirect_reg_count, 1694 int *indirect_start_offsets, 1695 int *indirect_start_offsets_count, 1696 int max_indirect_start_offsets_count) 1697 { 1698 int idx; 1699 bool new_entry = true; 1700 1701 for (; indirect_offset < list_size; indirect_offset++) { 1702 1703 if (new_entry) { 1704 new_entry = false; 1705 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 1706 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 1707 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count); 1708 } 1709 1710 if (register_list_format[indirect_offset] == 0xFFFFFFFF) { 1711 new_entry = true; 1712 continue; 1713 } 1714 1715 indirect_offset += 2; 1716 1717 /* look for the matching indice */ 1718 for (idx = 0; idx < *unique_indirect_reg_count; idx++) { 1719 if (unique_indirect_regs[idx] == 1720 register_list_format[indirect_offset]) 1721 break; 1722 } 1723 1724 if (idx >= *unique_indirect_reg_count) { 1725 unique_indirect_regs[*unique_indirect_reg_count] = 1726 register_list_format[indirect_offset]; 1727 idx = *unique_indirect_reg_count; 1728 *unique_indirect_reg_count = *unique_indirect_reg_count + 1; 1729 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count); 1730 } 1731 1732 register_list_format[indirect_offset] = idx; 1733 } 1734 } 1735 1736 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) 1737 { 1738 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1739 int unique_indirect_reg_count = 0; 1740 1741 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1742 int indirect_start_offsets_count = 0; 1743 1744 int list_size = 0; 1745 int i = 0; 1746 u32 tmp = 0; 1747 1748 u32 *register_list_format = 1749 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 1750 if (!register_list_format) 1751 return -ENOMEM; 1752 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 1753 adev->gfx.rlc.reg_list_format_size_bytes); 1754 1755 /* setup unique_indirect_regs array and indirect_start_offsets array */ 1756 gfx_v9_0_parse_ind_reg_list(register_list_format, 1757 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, 1758 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 1759 unique_indirect_regs, 1760 &unique_indirect_reg_count, 1761 ARRAY_SIZE(unique_indirect_regs), 1762 indirect_start_offsets, 1763 &indirect_start_offsets_count, 1764 ARRAY_SIZE(indirect_start_offsets)); 1765 1766 /* enable auto inc in case it is disabled */ 1767 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1768 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1769 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1770 1771 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 1772 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 1773 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 1774 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1776 adev->gfx.rlc.register_restore[i]); 1777 1778 /* load direct register */ 1779 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0); 1780 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1782 adev->gfx.rlc.register_restore[i]); 1783 1784 /* load indirect register */ 1785 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1786 adev->gfx.rlc.reg_list_format_start); 1787 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) 1788 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1789 register_list_format[i]); 1790 1791 /* set save/restore list size */ 1792 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 1793 list_size = list_size >> 1; 1794 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1795 adev->gfx.rlc.reg_restore_list_size); 1796 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 1797 1798 /* write the starting offsets to RLC scratch ram */ 1799 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1800 adev->gfx.rlc.starting_offsets_start); 1801 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 1802 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1803 indirect_start_offsets[i]); 1804 1805 /* load unique indirect regs*/ 1806 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 1807 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i, 1808 unique_indirect_regs[i] & 0x3FFFF); 1809 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i, 1810 unique_indirect_regs[i] >> 20); 1811 } 1812 1813 kfree(register_list_format); 1814 return 0; 1815 } 1816 1817 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 1818 { 1819 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 1820 } 1821 1822 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 1823 bool enable) 1824 { 1825 uint32_t data = 0; 1826 uint32_t default_data = 0; 1827 1828 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 1829 if (enable == true) { 1830 /* enable GFXIP control over CGPG */ 1831 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1832 if(default_data != data) 1833 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1834 1835 /* update status */ 1836 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 1837 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 1838 if(default_data != data) 1839 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1840 } else { 1841 /* restore GFXIP control over GCPG */ 1842 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1843 if(default_data != data) 1844 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1845 } 1846 } 1847 1848 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 1849 { 1850 uint32_t data = 0; 1851 1852 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1853 AMD_PG_SUPPORT_GFX_SMG | 1854 AMD_PG_SUPPORT_GFX_DMG)) { 1855 /* init IDLE_POLL_COUNT = 60 */ 1856 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 1857 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 1858 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 1859 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 1860 1861 /* init RLC PG Delay */ 1862 data = 0; 1863 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 1864 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 1865 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 1866 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 1867 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 1868 1869 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 1870 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 1871 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 1872 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 1873 1874 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 1875 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 1876 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 1877 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 1878 1879 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 1880 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 1881 1882 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 1883 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 1884 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 1885 1886 pwr_10_0_gfxip_control_over_cgpg(adev, true); 1887 } 1888 } 1889 1890 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 1891 bool enable) 1892 { 1893 uint32_t data = 0; 1894 uint32_t default_data = 0; 1895 1896 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1897 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1898 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 1899 enable ? 1 : 0); 1900 if (default_data != data) 1901 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1902 } 1903 1904 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 1905 bool enable) 1906 { 1907 uint32_t data = 0; 1908 uint32_t default_data = 0; 1909 1910 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1911 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1912 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 1913 enable ? 1 : 0); 1914 if(default_data != data) 1915 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1916 } 1917 1918 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 1919 bool enable) 1920 { 1921 uint32_t data = 0; 1922 uint32_t default_data = 0; 1923 1924 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1925 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1926 CP_PG_DISABLE, 1927 enable ? 0 : 1); 1928 if(default_data != data) 1929 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1930 } 1931 1932 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 1933 bool enable) 1934 { 1935 uint32_t data, default_data; 1936 1937 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1938 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1939 GFX_POWER_GATING_ENABLE, 1940 enable ? 1 : 0); 1941 if(default_data != data) 1942 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1943 } 1944 1945 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 1946 bool enable) 1947 { 1948 uint32_t data, default_data; 1949 1950 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1951 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1952 GFX_PIPELINE_PG_ENABLE, 1953 enable ? 1 : 0); 1954 if(default_data != data) 1955 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1956 1957 if (!enable) 1958 /* read any GFX register to wake up GFX */ 1959 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 1960 } 1961 1962 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 1963 bool enable) 1964 { 1965 uint32_t data, default_data; 1966 1967 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1968 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1969 STATIC_PER_CU_PG_ENABLE, 1970 enable ? 1 : 0); 1971 if(default_data != data) 1972 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1973 } 1974 1975 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 1976 bool enable) 1977 { 1978 uint32_t data, default_data; 1979 1980 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1981 data = REG_SET_FIELD(data, RLC_PG_CNTL, 1982 DYN_PER_CU_PG_ENABLE, 1983 enable ? 1 : 0); 1984 if(default_data != data) 1985 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1986 } 1987 1988 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 1989 { 1990 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1991 AMD_PG_SUPPORT_GFX_SMG | 1992 AMD_PG_SUPPORT_GFX_DMG | 1993 AMD_PG_SUPPORT_CP | 1994 AMD_PG_SUPPORT_GDS | 1995 AMD_PG_SUPPORT_RLC_SMU_HS)) { 1996 gfx_v9_0_init_csb(adev); 1997 gfx_v9_0_init_rlc_save_restore_list(adev); 1998 gfx_v9_0_enable_save_restore_machine(adev); 1999 2000 if (adev->asic_type == CHIP_RAVEN) { 2001 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2002 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2003 gfx_v9_0_init_gfx_power_gating(adev); 2004 2005 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 2006 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 2007 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 2008 } else { 2009 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 2010 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 2011 } 2012 2013 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 2014 gfx_v9_0_enable_cp_power_gating(adev, true); 2015 else 2016 gfx_v9_0_enable_cp_power_gating(adev, false); 2017 } 2018 } 2019 } 2020 2021 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2022 { 2023 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2024 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2025 gfx_v9_0_wait_for_rlc_serdes(adev); 2026 } 2027 2028 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2029 { 2030 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2031 udelay(50); 2032 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2033 udelay(50); 2034 } 2035 2036 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2037 { 2038 #ifdef AMDGPU_RLC_DEBUG_RETRY 2039 u32 rlc_ucode_ver; 2040 #endif 2041 2042 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2043 2044 /* carrizo do enable cp interrupt after cp inited */ 2045 if (!(adev->flags & AMD_IS_APU)) 2046 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2047 2048 udelay(50); 2049 2050 #ifdef AMDGPU_RLC_DEBUG_RETRY 2051 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2052 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2053 if(rlc_ucode_ver == 0x108) { 2054 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2055 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2056 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2057 * default is 0x9C4 to create a 100us interval */ 2058 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2059 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2060 * to disable the page fault retry interrupts, default is 2061 * 0x100 (256) */ 2062 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2063 } 2064 #endif 2065 } 2066 2067 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2068 { 2069 const struct rlc_firmware_header_v2_0 *hdr; 2070 const __le32 *fw_data; 2071 unsigned i, fw_size; 2072 2073 if (!adev->gfx.rlc_fw) 2074 return -EINVAL; 2075 2076 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2077 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2078 2079 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2080 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2081 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2082 2083 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2084 RLCG_UCODE_LOADING_START_ADDRESS); 2085 for (i = 0; i < fw_size; i++) 2086 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2087 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2088 2089 return 0; 2090 } 2091 2092 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2093 { 2094 int r; 2095 2096 if (amdgpu_sriov_vf(adev)) { 2097 gfx_v9_0_init_csb(adev); 2098 return 0; 2099 } 2100 2101 gfx_v9_0_rlc_stop(adev); 2102 2103 /* disable CG */ 2104 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2105 2106 /* disable PG */ 2107 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 2108 2109 gfx_v9_0_rlc_reset(adev); 2110 2111 gfx_v9_0_init_pg(adev); 2112 2113 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2114 /* legacy rlc firmware loading */ 2115 r = gfx_v9_0_rlc_load_microcode(adev); 2116 if (r) 2117 return r; 2118 } 2119 2120 if (adev->asic_type == CHIP_RAVEN) { 2121 if (amdgpu_lbpw != 0) 2122 gfx_v9_0_enable_lbpw(adev, true); 2123 else 2124 gfx_v9_0_enable_lbpw(adev, false); 2125 } 2126 2127 gfx_v9_0_rlc_start(adev); 2128 2129 return 0; 2130 } 2131 2132 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2133 { 2134 int i; 2135 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2136 2137 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2139 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2140 if (!enable) { 2141 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2142 adev->gfx.gfx_ring[i].ready = false; 2143 } 2144 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2145 udelay(50); 2146 } 2147 2148 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2149 { 2150 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2151 const struct gfx_firmware_header_v1_0 *ce_hdr; 2152 const struct gfx_firmware_header_v1_0 *me_hdr; 2153 const __le32 *fw_data; 2154 unsigned i, fw_size; 2155 2156 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2157 return -EINVAL; 2158 2159 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2160 adev->gfx.pfp_fw->data; 2161 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2162 adev->gfx.ce_fw->data; 2163 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2164 adev->gfx.me_fw->data; 2165 2166 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2167 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2168 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2169 2170 gfx_v9_0_cp_gfx_enable(adev, false); 2171 2172 /* PFP */ 2173 fw_data = (const __le32 *) 2174 (adev->gfx.pfp_fw->data + 2175 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2176 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2177 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2178 for (i = 0; i < fw_size; i++) 2179 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2180 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2181 2182 /* CE */ 2183 fw_data = (const __le32 *) 2184 (adev->gfx.ce_fw->data + 2185 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2186 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2187 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2188 for (i = 0; i < fw_size; i++) 2189 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2190 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2191 2192 /* ME */ 2193 fw_data = (const __le32 *) 2194 (adev->gfx.me_fw->data + 2195 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2196 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2197 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2198 for (i = 0; i < fw_size; i++) 2199 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2200 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2201 2202 return 0; 2203 } 2204 2205 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2206 { 2207 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2208 const struct cs_section_def *sect = NULL; 2209 const struct cs_extent_def *ext = NULL; 2210 int r, i, tmp; 2211 2212 /* init the CP */ 2213 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2214 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2215 2216 gfx_v9_0_cp_gfx_enable(adev, true); 2217 2218 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 2219 if (r) { 2220 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2221 return r; 2222 } 2223 2224 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2225 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2226 2227 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2228 amdgpu_ring_write(ring, 0x80000000); 2229 amdgpu_ring_write(ring, 0x80000000); 2230 2231 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2232 for (ext = sect->section; ext->extent != NULL; ++ext) { 2233 if (sect->id == SECT_CONTEXT) { 2234 amdgpu_ring_write(ring, 2235 PACKET3(PACKET3_SET_CONTEXT_REG, 2236 ext->reg_count)); 2237 amdgpu_ring_write(ring, 2238 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2239 for (i = 0; i < ext->reg_count; i++) 2240 amdgpu_ring_write(ring, ext->extent[i]); 2241 } 2242 } 2243 } 2244 2245 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2246 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2247 2248 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2249 amdgpu_ring_write(ring, 0); 2250 2251 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2252 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2253 amdgpu_ring_write(ring, 0x8000); 2254 amdgpu_ring_write(ring, 0x8000); 2255 2256 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 2257 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 2258 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 2259 amdgpu_ring_write(ring, tmp); 2260 amdgpu_ring_write(ring, 0); 2261 2262 amdgpu_ring_commit(ring); 2263 2264 return 0; 2265 } 2266 2267 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2268 { 2269 struct amdgpu_ring *ring; 2270 u32 tmp; 2271 u32 rb_bufsz; 2272 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2273 2274 /* Set the write pointer delay */ 2275 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2276 2277 /* set the RB to use vmid 0 */ 2278 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2279 2280 /* Set ring buffer size */ 2281 ring = &adev->gfx.gfx_ring[0]; 2282 rb_bufsz = order_base_2(ring->ring_size / 8); 2283 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2284 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2285 #ifdef __BIG_ENDIAN 2286 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2287 #endif 2288 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2289 2290 /* Initialize the ring buffer's write pointers */ 2291 ring->wptr = 0; 2292 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2293 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2294 2295 /* set the wb address wether it's enabled or not */ 2296 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2297 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2298 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2299 2300 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2301 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2302 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2303 2304 mdelay(1); 2305 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2306 2307 rb_addr = ring->gpu_addr >> 8; 2308 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2309 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2310 2311 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2312 if (ring->use_doorbell) { 2313 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2314 DOORBELL_OFFSET, ring->doorbell_index); 2315 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2316 DOORBELL_EN, 1); 2317 } else { 2318 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2319 } 2320 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2321 2322 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2323 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2324 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2325 2326 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2327 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2328 2329 2330 /* start the ring */ 2331 gfx_v9_0_cp_gfx_start(adev); 2332 ring->ready = true; 2333 2334 return 0; 2335 } 2336 2337 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2338 { 2339 int i; 2340 2341 if (enable) { 2342 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2343 } else { 2344 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2345 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2346 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2347 adev->gfx.compute_ring[i].ready = false; 2348 adev->gfx.kiq.ring.ready = false; 2349 } 2350 udelay(50); 2351 } 2352 2353 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2354 { 2355 const struct gfx_firmware_header_v1_0 *mec_hdr; 2356 const __le32 *fw_data; 2357 unsigned i; 2358 u32 tmp; 2359 2360 if (!adev->gfx.mec_fw) 2361 return -EINVAL; 2362 2363 gfx_v9_0_cp_compute_enable(adev, false); 2364 2365 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2366 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2367 2368 fw_data = (const __le32 *) 2369 (adev->gfx.mec_fw->data + 2370 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2371 tmp = 0; 2372 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2373 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2374 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2375 2376 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2377 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2378 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2379 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2380 2381 /* MEC1 */ 2382 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2383 mec_hdr->jt_offset); 2384 for (i = 0; i < mec_hdr->jt_size; i++) 2385 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2386 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2387 2388 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2389 adev->gfx.mec_fw_version); 2390 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2391 2392 return 0; 2393 } 2394 2395 /* KIQ functions */ 2396 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2397 { 2398 uint32_t tmp; 2399 struct amdgpu_device *adev = ring->adev; 2400 2401 /* tell RLC which is KIQ queue */ 2402 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2403 tmp &= 0xffffff00; 2404 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2405 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2406 tmp |= 0x80; 2407 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2408 } 2409 2410 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) 2411 { 2412 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 2413 uint32_t scratch, tmp = 0; 2414 uint64_t queue_mask = 0; 2415 int r, i; 2416 2417 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 2418 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 2419 continue; 2420 2421 /* This situation may be hit in the future if a new HW 2422 * generation exposes more than 64 queues. If so, the 2423 * definition of queue_mask needs updating */ 2424 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 2425 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 2426 break; 2427 } 2428 2429 queue_mask |= (1ull << i); 2430 } 2431 2432 r = amdgpu_gfx_scratch_get(adev, &scratch); 2433 if (r) { 2434 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2435 return r; 2436 } 2437 WREG32(scratch, 0xCAFEDEAD); 2438 2439 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); 2440 if (r) { 2441 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2442 amdgpu_gfx_scratch_free(adev, scratch); 2443 return r; 2444 } 2445 2446 /* set resources */ 2447 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2448 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2449 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2450 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 2451 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 2452 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 2453 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 2454 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 2455 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 2456 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2457 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2458 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2459 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2460 2461 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2462 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2463 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2464 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2465 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2466 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2467 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2468 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2469 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2470 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 2471 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2472 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2473 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2474 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2475 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2476 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2477 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2478 } 2479 /* write to scratch for completion */ 2480 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2481 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2482 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2483 amdgpu_ring_commit(kiq_ring); 2484 2485 for (i = 0; i < adev->usec_timeout; i++) { 2486 tmp = RREG32(scratch); 2487 if (tmp == 0xDEADBEEF) 2488 break; 2489 DRM_UDELAY(1); 2490 } 2491 if (i >= adev->usec_timeout) { 2492 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", 2493 scratch, tmp); 2494 r = -EINVAL; 2495 } 2496 amdgpu_gfx_scratch_free(adev, scratch); 2497 2498 return r; 2499 } 2500 2501 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2502 { 2503 struct amdgpu_device *adev = ring->adev; 2504 struct v9_mqd *mqd = ring->mqd_ptr; 2505 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2506 uint32_t tmp; 2507 2508 mqd->header = 0xC0310800; 2509 mqd->compute_pipelinestat_enable = 0x00000001; 2510 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2511 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2512 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2513 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2514 mqd->compute_misc_reserved = 0x00000003; 2515 2516 mqd->dynamic_cu_mask_addr_lo = 2517 lower_32_bits(ring->mqd_gpu_addr 2518 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2519 mqd->dynamic_cu_mask_addr_hi = 2520 upper_32_bits(ring->mqd_gpu_addr 2521 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2522 2523 eop_base_addr = ring->eop_gpu_addr >> 8; 2524 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2525 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2526 2527 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2528 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2529 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2530 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2531 2532 mqd->cp_hqd_eop_control = tmp; 2533 2534 /* enable doorbell? */ 2535 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2536 2537 if (ring->use_doorbell) { 2538 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2539 DOORBELL_OFFSET, ring->doorbell_index); 2540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2541 DOORBELL_EN, 1); 2542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2543 DOORBELL_SOURCE, 0); 2544 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2545 DOORBELL_HIT, 0); 2546 } else { 2547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2548 DOORBELL_EN, 0); 2549 } 2550 2551 mqd->cp_hqd_pq_doorbell_control = tmp; 2552 2553 /* disable the queue if it's active */ 2554 ring->wptr = 0; 2555 mqd->cp_hqd_dequeue_request = 0; 2556 mqd->cp_hqd_pq_rptr = 0; 2557 mqd->cp_hqd_pq_wptr_lo = 0; 2558 mqd->cp_hqd_pq_wptr_hi = 0; 2559 2560 /* set the pointer to the MQD */ 2561 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2562 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2563 2564 /* set MQD vmid to 0 */ 2565 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2566 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2567 mqd->cp_mqd_control = tmp; 2568 2569 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2570 hqd_gpu_addr = ring->gpu_addr >> 8; 2571 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2572 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2573 2574 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2575 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2577 (order_base_2(ring->ring_size / 4) - 1)); 2578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2579 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2580 #ifdef __BIG_ENDIAN 2581 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2582 #endif 2583 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2585 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2587 mqd->cp_hqd_pq_control = tmp; 2588 2589 /* set the wb address whether it's enabled or not */ 2590 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2591 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2592 mqd->cp_hqd_pq_rptr_report_addr_hi = 2593 upper_32_bits(wb_gpu_addr) & 0xffff; 2594 2595 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2596 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2597 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2598 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2599 2600 tmp = 0; 2601 /* enable the doorbell if requested */ 2602 if (ring->use_doorbell) { 2603 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2604 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2605 DOORBELL_OFFSET, ring->doorbell_index); 2606 2607 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2608 DOORBELL_EN, 1); 2609 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2610 DOORBELL_SOURCE, 0); 2611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2612 DOORBELL_HIT, 0); 2613 } 2614 2615 mqd->cp_hqd_pq_doorbell_control = tmp; 2616 2617 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2618 ring->wptr = 0; 2619 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2620 2621 /* set the vmid for the queue */ 2622 mqd->cp_hqd_vmid = 0; 2623 2624 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2625 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2626 mqd->cp_hqd_persistent_state = tmp; 2627 2628 /* set MIN_IB_AVAIL_SIZE */ 2629 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2630 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2631 mqd->cp_hqd_ib_control = tmp; 2632 2633 /* activate the queue */ 2634 mqd->cp_hqd_active = 1; 2635 2636 return 0; 2637 } 2638 2639 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2640 { 2641 struct amdgpu_device *adev = ring->adev; 2642 struct v9_mqd *mqd = ring->mqd_ptr; 2643 int j; 2644 2645 /* disable wptr polling */ 2646 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2647 2648 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2649 mqd->cp_hqd_eop_base_addr_lo); 2650 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2651 mqd->cp_hqd_eop_base_addr_hi); 2652 2653 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2654 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2655 mqd->cp_hqd_eop_control); 2656 2657 /* enable doorbell? */ 2658 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2659 mqd->cp_hqd_pq_doorbell_control); 2660 2661 /* disable the queue if it's active */ 2662 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2663 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2664 for (j = 0; j < adev->usec_timeout; j++) { 2665 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2666 break; 2667 udelay(1); 2668 } 2669 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2670 mqd->cp_hqd_dequeue_request); 2671 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 2672 mqd->cp_hqd_pq_rptr); 2673 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2674 mqd->cp_hqd_pq_wptr_lo); 2675 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2676 mqd->cp_hqd_pq_wptr_hi); 2677 } 2678 2679 /* set the pointer to the MQD */ 2680 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 2681 mqd->cp_mqd_base_addr_lo); 2682 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 2683 mqd->cp_mqd_base_addr_hi); 2684 2685 /* set MQD vmid to 0 */ 2686 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 2687 mqd->cp_mqd_control); 2688 2689 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2690 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 2691 mqd->cp_hqd_pq_base_lo); 2692 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 2693 mqd->cp_hqd_pq_base_hi); 2694 2695 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2696 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 2697 mqd->cp_hqd_pq_control); 2698 2699 /* set the wb address whether it's enabled or not */ 2700 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2701 mqd->cp_hqd_pq_rptr_report_addr_lo); 2702 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2703 mqd->cp_hqd_pq_rptr_report_addr_hi); 2704 2705 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2706 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 2707 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2708 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2709 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2710 2711 /* enable the doorbell if requested */ 2712 if (ring->use_doorbell) { 2713 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 2714 (AMDGPU_DOORBELL64_KIQ *2) << 2); 2715 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 2716 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); 2717 } 2718 2719 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2720 mqd->cp_hqd_pq_doorbell_control); 2721 2722 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2723 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2724 mqd->cp_hqd_pq_wptr_lo); 2725 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2726 mqd->cp_hqd_pq_wptr_hi); 2727 2728 /* set the vmid for the queue */ 2729 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 2730 2731 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 2732 mqd->cp_hqd_persistent_state); 2733 2734 /* activate the queue */ 2735 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 2736 mqd->cp_hqd_active); 2737 2738 if (ring->use_doorbell) 2739 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2740 2741 return 0; 2742 } 2743 2744 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 2745 { 2746 struct amdgpu_device *adev = ring->adev; 2747 struct v9_mqd *mqd = ring->mqd_ptr; 2748 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2749 2750 gfx_v9_0_kiq_setting(ring); 2751 2752 if (adev->in_sriov_reset) { /* for GPU_RESET case */ 2753 /* reset MQD to a clean status */ 2754 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2755 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2756 2757 /* reset ring buffer */ 2758 ring->wptr = 0; 2759 amdgpu_ring_clear_ring(ring); 2760 2761 mutex_lock(&adev->srbm_mutex); 2762 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2763 gfx_v9_0_kiq_init_register(ring); 2764 soc15_grbm_select(adev, 0, 0, 0, 0); 2765 mutex_unlock(&adev->srbm_mutex); 2766 } else { 2767 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2768 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2769 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2770 mutex_lock(&adev->srbm_mutex); 2771 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2772 gfx_v9_0_mqd_init(ring); 2773 gfx_v9_0_kiq_init_register(ring); 2774 soc15_grbm_select(adev, 0, 0, 0, 0); 2775 mutex_unlock(&adev->srbm_mutex); 2776 2777 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2778 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2779 } 2780 2781 return 0; 2782 } 2783 2784 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 2785 { 2786 struct amdgpu_device *adev = ring->adev; 2787 struct v9_mqd *mqd = ring->mqd_ptr; 2788 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2789 2790 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { 2791 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2792 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2793 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2794 mutex_lock(&adev->srbm_mutex); 2795 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2796 gfx_v9_0_mqd_init(ring); 2797 soc15_grbm_select(adev, 0, 0, 0, 0); 2798 mutex_unlock(&adev->srbm_mutex); 2799 2800 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2801 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2802 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ 2803 /* reset MQD to a clean status */ 2804 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2805 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2806 2807 /* reset ring buffer */ 2808 ring->wptr = 0; 2809 amdgpu_ring_clear_ring(ring); 2810 } else { 2811 amdgpu_ring_clear_ring(ring); 2812 } 2813 2814 return 0; 2815 } 2816 2817 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 2818 { 2819 struct amdgpu_ring *ring = NULL; 2820 int r = 0, i; 2821 2822 gfx_v9_0_cp_compute_enable(adev, true); 2823 2824 ring = &adev->gfx.kiq.ring; 2825 2826 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2827 if (unlikely(r != 0)) 2828 goto done; 2829 2830 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2831 if (!r) { 2832 r = gfx_v9_0_kiq_init_queue(ring); 2833 amdgpu_bo_kunmap(ring->mqd_obj); 2834 ring->mqd_ptr = NULL; 2835 } 2836 amdgpu_bo_unreserve(ring->mqd_obj); 2837 if (r) 2838 goto done; 2839 2840 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2841 ring = &adev->gfx.compute_ring[i]; 2842 2843 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2844 if (unlikely(r != 0)) 2845 goto done; 2846 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2847 if (!r) { 2848 r = gfx_v9_0_kcq_init_queue(ring); 2849 amdgpu_bo_kunmap(ring->mqd_obj); 2850 ring->mqd_ptr = NULL; 2851 } 2852 amdgpu_bo_unreserve(ring->mqd_obj); 2853 if (r) 2854 goto done; 2855 } 2856 2857 r = gfx_v9_0_kiq_kcq_enable(adev); 2858 done: 2859 return r; 2860 } 2861 2862 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 2863 { 2864 int r, i; 2865 struct amdgpu_ring *ring; 2866 2867 if (!(adev->flags & AMD_IS_APU)) 2868 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2869 2870 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2871 /* legacy firmware loading */ 2872 r = gfx_v9_0_cp_gfx_load_microcode(adev); 2873 if (r) 2874 return r; 2875 2876 r = gfx_v9_0_cp_compute_load_microcode(adev); 2877 if (r) 2878 return r; 2879 } 2880 2881 r = gfx_v9_0_cp_gfx_resume(adev); 2882 if (r) 2883 return r; 2884 2885 r = gfx_v9_0_kiq_resume(adev); 2886 if (r) 2887 return r; 2888 2889 ring = &adev->gfx.gfx_ring[0]; 2890 r = amdgpu_ring_test_ring(ring); 2891 if (r) { 2892 ring->ready = false; 2893 return r; 2894 } 2895 2896 ring = &adev->gfx.kiq.ring; 2897 ring->ready = true; 2898 r = amdgpu_ring_test_ring(ring); 2899 if (r) 2900 ring->ready = false; 2901 2902 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2903 ring = &adev->gfx.compute_ring[i]; 2904 2905 ring->ready = true; 2906 r = amdgpu_ring_test_ring(ring); 2907 if (r) 2908 ring->ready = false; 2909 } 2910 2911 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2912 2913 return 0; 2914 } 2915 2916 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 2917 { 2918 gfx_v9_0_cp_gfx_enable(adev, enable); 2919 gfx_v9_0_cp_compute_enable(adev, enable); 2920 } 2921 2922 static int gfx_v9_0_hw_init(void *handle) 2923 { 2924 int r; 2925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2926 2927 gfx_v9_0_init_golden_registers(adev); 2928 2929 gfx_v9_0_gpu_init(adev); 2930 2931 r = gfx_v9_0_rlc_resume(adev); 2932 if (r) 2933 return r; 2934 2935 r = gfx_v9_0_cp_resume(adev); 2936 if (r) 2937 return r; 2938 2939 r = gfx_v9_0_ngg_en(adev); 2940 if (r) 2941 return r; 2942 2943 return r; 2944 } 2945 2946 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) 2947 { 2948 struct amdgpu_device *adev = kiq_ring->adev; 2949 uint32_t scratch, tmp = 0; 2950 int r, i; 2951 2952 r = amdgpu_gfx_scratch_get(adev, &scratch); 2953 if (r) { 2954 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2955 return r; 2956 } 2957 WREG32(scratch, 0xCAFEDEAD); 2958 2959 r = amdgpu_ring_alloc(kiq_ring, 10); 2960 if (r) { 2961 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2962 amdgpu_gfx_scratch_free(adev, scratch); 2963 return r; 2964 } 2965 2966 /* unmap queues */ 2967 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 2968 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2969 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 2970 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 2971 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 2972 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 2973 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 2974 amdgpu_ring_write(kiq_ring, 0); 2975 amdgpu_ring_write(kiq_ring, 0); 2976 amdgpu_ring_write(kiq_ring, 0); 2977 /* write to scratch for completion */ 2978 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2979 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2980 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2981 amdgpu_ring_commit(kiq_ring); 2982 2983 for (i = 0; i < adev->usec_timeout; i++) { 2984 tmp = RREG32(scratch); 2985 if (tmp == 0xDEADBEEF) 2986 break; 2987 DRM_UDELAY(1); 2988 } 2989 if (i >= adev->usec_timeout) { 2990 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); 2991 r = -EINVAL; 2992 } 2993 amdgpu_gfx_scratch_free(adev, scratch); 2994 return r; 2995 } 2996 2997 2998 static int gfx_v9_0_hw_fini(void *handle) 2999 { 3000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3001 int i; 3002 3003 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3004 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3005 3006 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3007 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3008 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); 3009 3010 if (amdgpu_sriov_vf(adev)) { 3011 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3012 return 0; 3013 } 3014 gfx_v9_0_cp_enable(adev, false); 3015 gfx_v9_0_rlc_stop(adev); 3016 3017 return 0; 3018 } 3019 3020 static int gfx_v9_0_suspend(void *handle) 3021 { 3022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3023 3024 adev->gfx.in_suspend = true; 3025 return gfx_v9_0_hw_fini(adev); 3026 } 3027 3028 static int gfx_v9_0_resume(void *handle) 3029 { 3030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3031 int r; 3032 3033 r = gfx_v9_0_hw_init(adev); 3034 adev->gfx.in_suspend = false; 3035 return r; 3036 } 3037 3038 static bool gfx_v9_0_is_idle(void *handle) 3039 { 3040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3041 3042 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3043 GRBM_STATUS, GUI_ACTIVE)) 3044 return false; 3045 else 3046 return true; 3047 } 3048 3049 static int gfx_v9_0_wait_for_idle(void *handle) 3050 { 3051 unsigned i; 3052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3053 3054 for (i = 0; i < adev->usec_timeout; i++) { 3055 if (gfx_v9_0_is_idle(handle)) 3056 return 0; 3057 udelay(1); 3058 } 3059 return -ETIMEDOUT; 3060 } 3061 3062 static int gfx_v9_0_soft_reset(void *handle) 3063 { 3064 u32 grbm_soft_reset = 0; 3065 u32 tmp; 3066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3067 3068 /* GRBM_STATUS */ 3069 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3070 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3071 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3072 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3073 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3074 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3075 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3076 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3077 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3078 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3079 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3080 } 3081 3082 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3083 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3084 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3085 } 3086 3087 /* GRBM_STATUS2 */ 3088 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3089 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3090 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3091 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3092 3093 3094 if (grbm_soft_reset) { 3095 /* stop the rlc */ 3096 gfx_v9_0_rlc_stop(adev); 3097 3098 /* Disable GFX parsing/prefetching */ 3099 gfx_v9_0_cp_gfx_enable(adev, false); 3100 3101 /* Disable MEC parsing/prefetching */ 3102 gfx_v9_0_cp_compute_enable(adev, false); 3103 3104 if (grbm_soft_reset) { 3105 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3106 tmp |= grbm_soft_reset; 3107 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3108 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3109 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3110 3111 udelay(50); 3112 3113 tmp &= ~grbm_soft_reset; 3114 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3115 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3116 } 3117 3118 /* Wait a little for things to settle down */ 3119 udelay(50); 3120 } 3121 return 0; 3122 } 3123 3124 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3125 { 3126 uint64_t clock; 3127 3128 mutex_lock(&adev->gfx.gpu_clock_mutex); 3129 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3130 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3131 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3132 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3133 return clock; 3134 } 3135 3136 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3137 uint32_t vmid, 3138 uint32_t gds_base, uint32_t gds_size, 3139 uint32_t gws_base, uint32_t gws_size, 3140 uint32_t oa_base, uint32_t oa_size) 3141 { 3142 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 3143 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 3144 3145 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 3146 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 3147 3148 oa_base = oa_base >> AMDGPU_OA_SHIFT; 3149 oa_size = oa_size >> AMDGPU_OA_SHIFT; 3150 3151 /* GDS Base */ 3152 gfx_v9_0_write_data_to_reg(ring, 0, false, 3153 amdgpu_gds_reg_offset[vmid].mem_base, 3154 gds_base); 3155 3156 /* GDS Size */ 3157 gfx_v9_0_write_data_to_reg(ring, 0, false, 3158 amdgpu_gds_reg_offset[vmid].mem_size, 3159 gds_size); 3160 3161 /* GWS */ 3162 gfx_v9_0_write_data_to_reg(ring, 0, false, 3163 amdgpu_gds_reg_offset[vmid].gws, 3164 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3165 3166 /* OA */ 3167 gfx_v9_0_write_data_to_reg(ring, 0, false, 3168 amdgpu_gds_reg_offset[vmid].oa, 3169 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3170 } 3171 3172 static int gfx_v9_0_early_init(void *handle) 3173 { 3174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3175 3176 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3177 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3178 gfx_v9_0_set_ring_funcs(adev); 3179 gfx_v9_0_set_irq_funcs(adev); 3180 gfx_v9_0_set_gds_init(adev); 3181 gfx_v9_0_set_rlc_funcs(adev); 3182 3183 return 0; 3184 } 3185 3186 static int gfx_v9_0_late_init(void *handle) 3187 { 3188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3189 int r; 3190 3191 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3192 if (r) 3193 return r; 3194 3195 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3196 if (r) 3197 return r; 3198 3199 return 0; 3200 } 3201 3202 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3203 { 3204 uint32_t rlc_setting, data; 3205 unsigned i; 3206 3207 if (adev->gfx.rlc.in_safe_mode) 3208 return; 3209 3210 /* if RLC is not enabled, do nothing */ 3211 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3212 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3213 return; 3214 3215 if (adev->cg_flags & 3216 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | 3217 AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3218 data = RLC_SAFE_MODE__CMD_MASK; 3219 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3220 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3221 3222 /* wait for RLC_SAFE_MODE */ 3223 for (i = 0; i < adev->usec_timeout; i++) { 3224 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3225 break; 3226 udelay(1); 3227 } 3228 adev->gfx.rlc.in_safe_mode = true; 3229 } 3230 } 3231 3232 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3233 { 3234 uint32_t rlc_setting, data; 3235 3236 if (!adev->gfx.rlc.in_safe_mode) 3237 return; 3238 3239 /* if RLC is not enabled, do nothing */ 3240 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3241 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3242 return; 3243 3244 if (adev->cg_flags & 3245 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 3246 /* 3247 * Try to exit safe mode only if it is already in safe 3248 * mode. 3249 */ 3250 data = RLC_SAFE_MODE__CMD_MASK; 3251 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3252 adev->gfx.rlc.in_safe_mode = false; 3253 } 3254 } 3255 3256 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3257 bool enable) 3258 { 3259 /* TODO: double check if we need to perform under safe mdoe */ 3260 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3261 3262 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3263 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3264 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3265 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3266 } else { 3267 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3268 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3269 } 3270 3271 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3272 } 3273 3274 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3275 bool enable) 3276 { 3277 /* TODO: double check if we need to perform under safe mode */ 3278 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3279 3280 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3281 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3282 else 3283 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3284 3285 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3286 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3287 else 3288 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3289 3290 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3291 } 3292 3293 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3294 bool enable) 3295 { 3296 uint32_t data, def; 3297 3298 /* It is disabled by HW by default */ 3299 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3300 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3301 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3302 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3303 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3304 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3305 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3306 3307 /* only for Vega10 & Raven1 */ 3308 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3309 3310 if (def != data) 3311 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3312 3313 /* MGLS is a global flag to control all MGLS in GFX */ 3314 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3315 /* 2 - RLC memory Light sleep */ 3316 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3317 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3318 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3319 if (def != data) 3320 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3321 } 3322 /* 3 - CP memory Light sleep */ 3323 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3324 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3325 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3326 if (def != data) 3327 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3328 } 3329 } 3330 } else { 3331 /* 1 - MGCG_OVERRIDE */ 3332 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3333 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3334 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3335 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3336 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3337 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3338 if (def != data) 3339 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3340 3341 /* 2 - disable MGLS in RLC */ 3342 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3343 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3344 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3345 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3346 } 3347 3348 /* 3 - disable MGLS in CP */ 3349 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3350 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3351 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3352 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3353 } 3354 } 3355 } 3356 3357 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3358 bool enable) 3359 { 3360 uint32_t data, def; 3361 3362 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3363 3364 /* Enable 3D CGCG/CGLS */ 3365 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3366 /* write cmd to clear cgcg/cgls ov */ 3367 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3368 /* unset CGCG override */ 3369 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3370 /* update CGCG and CGLS override bits */ 3371 if (def != data) 3372 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3373 /* enable 3Dcgcg FSM(0x0020003f) */ 3374 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3375 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3376 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3377 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3378 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3379 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3380 if (def != data) 3381 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3382 3383 /* set IDLE_POLL_COUNT(0x00900100) */ 3384 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3385 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3386 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3387 if (def != data) 3388 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3389 } else { 3390 /* Disable CGCG/CGLS */ 3391 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3392 /* disable cgcg, cgls should be disabled */ 3393 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3394 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3395 /* disable cgcg and cgls in FSM */ 3396 if (def != data) 3397 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3398 } 3399 3400 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3401 } 3402 3403 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3404 bool enable) 3405 { 3406 uint32_t def, data; 3407 3408 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3409 3410 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3411 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3412 /* unset CGCG override */ 3413 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3414 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3415 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3416 else 3417 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3418 /* update CGCG and CGLS override bits */ 3419 if (def != data) 3420 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3421 3422 /* enable cgcg FSM(0x0020003F) */ 3423 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3424 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3425 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3426 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3427 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3428 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3429 if (def != data) 3430 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3431 3432 /* set IDLE_POLL_COUNT(0x00900100) */ 3433 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3434 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3435 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3436 if (def != data) 3437 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3438 } else { 3439 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3440 /* reset CGCG/CGLS bits */ 3441 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3442 /* disable cgcg and cgls in FSM */ 3443 if (def != data) 3444 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3445 } 3446 3447 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3448 } 3449 3450 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3451 bool enable) 3452 { 3453 if (enable) { 3454 /* CGCG/CGLS should be enabled after MGCG/MGLS 3455 * === MGCG + MGLS === 3456 */ 3457 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3458 /* === CGCG /CGLS for GFX 3D Only === */ 3459 gfx_v9_0_update_3d_clock_gating(adev, enable); 3460 /* === CGCG + CGLS === */ 3461 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3462 } else { 3463 /* CGCG/CGLS should be disabled before MGCG/MGLS 3464 * === CGCG + CGLS === 3465 */ 3466 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3467 /* === CGCG /CGLS for GFX 3D Only === */ 3468 gfx_v9_0_update_3d_clock_gating(adev, enable); 3469 /* === MGCG + MGLS === */ 3470 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3471 } 3472 return 0; 3473 } 3474 3475 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3476 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3477 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 3478 }; 3479 3480 static int gfx_v9_0_set_powergating_state(void *handle, 3481 enum amd_powergating_state state) 3482 { 3483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3484 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3485 3486 switch (adev->asic_type) { 3487 case CHIP_RAVEN: 3488 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3489 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3490 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3491 } else { 3492 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3493 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3494 } 3495 3496 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3497 gfx_v9_0_enable_cp_power_gating(adev, true); 3498 else 3499 gfx_v9_0_enable_cp_power_gating(adev, false); 3500 3501 /* update gfx cgpg state */ 3502 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3503 3504 /* update mgcg state */ 3505 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3506 break; 3507 default: 3508 break; 3509 } 3510 3511 return 0; 3512 } 3513 3514 static int gfx_v9_0_set_clockgating_state(void *handle, 3515 enum amd_clockgating_state state) 3516 { 3517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3518 3519 if (amdgpu_sriov_vf(adev)) 3520 return 0; 3521 3522 switch (adev->asic_type) { 3523 case CHIP_VEGA10: 3524 case CHIP_RAVEN: 3525 gfx_v9_0_update_gfx_clock_gating(adev, 3526 state == AMD_CG_STATE_GATE ? true : false); 3527 break; 3528 default: 3529 break; 3530 } 3531 return 0; 3532 } 3533 3534 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3535 { 3536 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3537 int data; 3538 3539 if (amdgpu_sriov_vf(adev)) 3540 *flags = 0; 3541 3542 /* AMD_CG_SUPPORT_GFX_MGCG */ 3543 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3544 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3545 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3546 3547 /* AMD_CG_SUPPORT_GFX_CGCG */ 3548 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3549 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3550 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3551 3552 /* AMD_CG_SUPPORT_GFX_CGLS */ 3553 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3554 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3555 3556 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 3557 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3558 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 3559 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 3560 3561 /* AMD_CG_SUPPORT_GFX_CP_LS */ 3562 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3563 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 3564 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 3565 3566 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3567 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3568 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3569 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3570 3571 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3572 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3573 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3574 } 3575 3576 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3577 { 3578 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 3579 } 3580 3581 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3582 { 3583 struct amdgpu_device *adev = ring->adev; 3584 u64 wptr; 3585 3586 /* XXX check if swapping is necessary on BE */ 3587 if (ring->use_doorbell) { 3588 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3589 } else { 3590 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 3591 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 3592 } 3593 3594 return wptr; 3595 } 3596 3597 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3598 { 3599 struct amdgpu_device *adev = ring->adev; 3600 3601 if (ring->use_doorbell) { 3602 /* XXX check if swapping is necessary on BE */ 3603 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3604 WDOORBELL64(ring->doorbell_index, ring->wptr); 3605 } else { 3606 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3607 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3608 } 3609 } 3610 3611 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3612 { 3613 u32 ref_and_mask, reg_mem_engine; 3614 const struct nbio_hdp_flush_reg *nbio_hf_reg; 3615 3616 if (ring->adev->flags & AMD_IS_APU) 3617 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg; 3618 else 3619 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 3620 3621 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3622 switch (ring->me) { 3623 case 1: 3624 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3625 break; 3626 case 2: 3627 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3628 break; 3629 default: 3630 return; 3631 } 3632 reg_mem_engine = 0; 3633 } else { 3634 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3635 reg_mem_engine = 1; /* pfp */ 3636 } 3637 3638 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3639 nbio_hf_reg->hdp_flush_req_offset, 3640 nbio_hf_reg->hdp_flush_done_offset, 3641 ref_and_mask, ref_and_mask, 0x20); 3642 } 3643 3644 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 3645 { 3646 gfx_v9_0_write_data_to_reg(ring, 0, true, 3647 SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 3648 } 3649 3650 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3651 struct amdgpu_ib *ib, 3652 unsigned vm_id, bool ctx_switch) 3653 { 3654 u32 header, control = 0; 3655 3656 if (ib->flags & AMDGPU_IB_FLAG_CE) 3657 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3658 else 3659 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3660 3661 control |= ib->length_dw | (vm_id << 24); 3662 3663 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3664 control |= INDIRECT_BUFFER_PRE_ENB(1); 3665 3666 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 3667 gfx_v9_0_ring_emit_de_meta(ring); 3668 } 3669 3670 amdgpu_ring_write(ring, header); 3671 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3672 amdgpu_ring_write(ring, 3673 #ifdef __BIG_ENDIAN 3674 (2 << 0) | 3675 #endif 3676 lower_32_bits(ib->gpu_addr)); 3677 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3678 amdgpu_ring_write(ring, control); 3679 } 3680 3681 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3682 struct amdgpu_ib *ib, 3683 unsigned vm_id, bool ctx_switch) 3684 { 3685 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 3686 3687 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3688 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3689 amdgpu_ring_write(ring, 3690 #ifdef __BIG_ENDIAN 3691 (2 << 0) | 3692 #endif 3693 lower_32_bits(ib->gpu_addr)); 3694 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3695 amdgpu_ring_write(ring, control); 3696 } 3697 3698 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3699 u64 seq, unsigned flags) 3700 { 3701 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3702 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3703 3704 /* RELEASE_MEM - flush caches, send int */ 3705 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3706 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3707 EOP_TC_ACTION_EN | 3708 EOP_TC_WB_ACTION_EN | 3709 EOP_TC_MD_ACTION_EN | 3710 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3711 EVENT_INDEX(5))); 3712 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3713 3714 /* 3715 * the address should be Qword aligned if 64bit write, Dword 3716 * aligned if only send 32bit data low (discard data high) 3717 */ 3718 if (write64bit) 3719 BUG_ON(addr & 0x7); 3720 else 3721 BUG_ON(addr & 0x3); 3722 amdgpu_ring_write(ring, lower_32_bits(addr)); 3723 amdgpu_ring_write(ring, upper_32_bits(addr)); 3724 amdgpu_ring_write(ring, lower_32_bits(seq)); 3725 amdgpu_ring_write(ring, upper_32_bits(seq)); 3726 amdgpu_ring_write(ring, 0); 3727 } 3728 3729 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3730 { 3731 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3732 uint32_t seq = ring->fence_drv.sync_seq; 3733 uint64_t addr = ring->fence_drv.gpu_addr; 3734 3735 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 3736 lower_32_bits(addr), upper_32_bits(addr), 3737 seq, 0xffffffff, 4); 3738 } 3739 3740 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3741 unsigned vm_id, uint64_t pd_addr) 3742 { 3743 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 3744 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3745 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 3746 unsigned eng = ring->vm_inv_eng; 3747 3748 pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr); 3749 pd_addr |= AMDGPU_PTE_VALID; 3750 3751 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3752 hub->ctx0_ptb_addr_lo32 + (2 * vm_id), 3753 lower_32_bits(pd_addr)); 3754 3755 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3756 hub->ctx0_ptb_addr_hi32 + (2 * vm_id), 3757 upper_32_bits(pd_addr)); 3758 3759 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3760 hub->vm_inv_eng0_req + eng, req); 3761 3762 /* wait for the invalidate to complete */ 3763 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + 3764 eng, 0, 1 << vm_id, 1 << vm_id, 0x20); 3765 3766 /* compute doesn't have PFP */ 3767 if (usepfp) { 3768 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3769 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3770 amdgpu_ring_write(ring, 0x0); 3771 } 3772 } 3773 3774 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3775 { 3776 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3777 } 3778 3779 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3780 { 3781 u64 wptr; 3782 3783 /* XXX check if swapping is necessary on BE */ 3784 if (ring->use_doorbell) 3785 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3786 else 3787 BUG(); 3788 return wptr; 3789 } 3790 3791 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 3792 { 3793 struct amdgpu_device *adev = ring->adev; 3794 3795 /* XXX check if swapping is necessary on BE */ 3796 if (ring->use_doorbell) { 3797 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3798 WDOORBELL64(ring->doorbell_index, ring->wptr); 3799 } else{ 3800 BUG(); /* only DOORBELL method supported on gfx9 now */ 3801 } 3802 } 3803 3804 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3805 u64 seq, unsigned int flags) 3806 { 3807 /* we only allocate 32bit for each seq wb address */ 3808 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 3809 3810 /* write fence seq to the "addr" */ 3811 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3812 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3813 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3814 amdgpu_ring_write(ring, lower_32_bits(addr)); 3815 amdgpu_ring_write(ring, upper_32_bits(addr)); 3816 amdgpu_ring_write(ring, lower_32_bits(seq)); 3817 3818 if (flags & AMDGPU_FENCE_FLAG_INT) { 3819 /* set register to trigger INT */ 3820 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3821 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3822 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3823 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 3824 amdgpu_ring_write(ring, 0); 3825 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3826 } 3827 } 3828 3829 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 3830 { 3831 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3832 amdgpu_ring_write(ring, 0); 3833 } 3834 3835 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 3836 { 3837 struct v9_ce_ib_state ce_payload = {0}; 3838 uint64_t csa_addr; 3839 int cnt; 3840 3841 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 3842 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3843 3844 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3845 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 3846 WRITE_DATA_DST_SEL(8) | 3847 WR_CONFIRM) | 3848 WRITE_DATA_CACHE_POLICY(0)); 3849 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3850 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3851 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 3852 } 3853 3854 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 3855 { 3856 struct v9_de_ib_state de_payload = {0}; 3857 uint64_t csa_addr, gds_addr; 3858 int cnt; 3859 3860 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3861 gds_addr = csa_addr + 4096; 3862 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 3863 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 3864 3865 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 3866 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3867 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 3868 WRITE_DATA_DST_SEL(8) | 3869 WR_CONFIRM) | 3870 WRITE_DATA_CACHE_POLICY(0)); 3871 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3872 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3873 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 3874 } 3875 3876 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 3877 { 3878 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 3879 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 3880 } 3881 3882 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3883 { 3884 uint32_t dw2 = 0; 3885 3886 if (amdgpu_sriov_vf(ring->adev)) 3887 gfx_v9_0_ring_emit_ce_meta(ring); 3888 3889 gfx_v9_0_ring_emit_tmz(ring, true); 3890 3891 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3892 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3893 /* set load_global_config & load_global_uconfig */ 3894 dw2 |= 0x8001; 3895 /* set load_cs_sh_regs */ 3896 dw2 |= 0x01000000; 3897 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 3898 dw2 |= 0x10002; 3899 3900 /* set load_ce_ram if preamble presented */ 3901 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 3902 dw2 |= 0x10000000; 3903 } else { 3904 /* still load_ce_ram if this is the first time preamble presented 3905 * although there is no context switch happens. 3906 */ 3907 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 3908 dw2 |= 0x10000000; 3909 } 3910 3911 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3912 amdgpu_ring_write(ring, dw2); 3913 amdgpu_ring_write(ring, 0); 3914 } 3915 3916 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 3917 { 3918 unsigned ret; 3919 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 3920 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 3921 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 3922 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 3923 ret = ring->wptr & ring->buf_mask; 3924 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 3925 return ret; 3926 } 3927 3928 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 3929 { 3930 unsigned cur; 3931 BUG_ON(offset > ring->buf_mask); 3932 BUG_ON(ring->ring[offset] != 0x55aa55aa); 3933 3934 cur = (ring->wptr & ring->buf_mask) - 1; 3935 if (likely(cur > offset)) 3936 ring->ring[offset] = cur - offset; 3937 else 3938 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 3939 } 3940 3941 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 3942 { 3943 struct amdgpu_device *adev = ring->adev; 3944 3945 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3946 amdgpu_ring_write(ring, 0 | /* src: register*/ 3947 (5 << 8) | /* dst: memory */ 3948 (1 << 20)); /* write confirm */ 3949 amdgpu_ring_write(ring, reg); 3950 amdgpu_ring_write(ring, 0); 3951 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3952 adev->virt.reg_val_offs * 4)); 3953 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3954 adev->virt.reg_val_offs * 4)); 3955 } 3956 3957 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3958 uint32_t val) 3959 { 3960 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3961 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ 3962 amdgpu_ring_write(ring, reg); 3963 amdgpu_ring_write(ring, 0); 3964 amdgpu_ring_write(ring, val); 3965 } 3966 3967 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3968 enum amdgpu_interrupt_state state) 3969 { 3970 switch (state) { 3971 case AMDGPU_IRQ_STATE_DISABLE: 3972 case AMDGPU_IRQ_STATE_ENABLE: 3973 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 3974 TIME_STAMP_INT_ENABLE, 3975 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3976 break; 3977 default: 3978 break; 3979 } 3980 } 3981 3982 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3983 int me, int pipe, 3984 enum amdgpu_interrupt_state state) 3985 { 3986 u32 mec_int_cntl, mec_int_cntl_reg; 3987 3988 /* 3989 * amdgpu controls only the first MEC. That's why this function only 3990 * handles the setting of interrupts for this specific MEC. All other 3991 * pipes' interrupts are set by amdkfd. 3992 */ 3993 3994 if (me == 1) { 3995 switch (pipe) { 3996 case 0: 3997 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 3998 break; 3999 case 1: 4000 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4001 break; 4002 case 2: 4003 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4004 break; 4005 case 3: 4006 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4007 break; 4008 default: 4009 DRM_DEBUG("invalid pipe %d\n", pipe); 4010 return; 4011 } 4012 } else { 4013 DRM_DEBUG("invalid me %d\n", me); 4014 return; 4015 } 4016 4017 switch (state) { 4018 case AMDGPU_IRQ_STATE_DISABLE: 4019 mec_int_cntl = RREG32(mec_int_cntl_reg); 4020 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4021 TIME_STAMP_INT_ENABLE, 0); 4022 WREG32(mec_int_cntl_reg, mec_int_cntl); 4023 break; 4024 case AMDGPU_IRQ_STATE_ENABLE: 4025 mec_int_cntl = RREG32(mec_int_cntl_reg); 4026 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4027 TIME_STAMP_INT_ENABLE, 1); 4028 WREG32(mec_int_cntl_reg, mec_int_cntl); 4029 break; 4030 default: 4031 break; 4032 } 4033 } 4034 4035 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4036 struct amdgpu_irq_src *source, 4037 unsigned type, 4038 enum amdgpu_interrupt_state state) 4039 { 4040 switch (state) { 4041 case AMDGPU_IRQ_STATE_DISABLE: 4042 case AMDGPU_IRQ_STATE_ENABLE: 4043 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4044 PRIV_REG_INT_ENABLE, 4045 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4046 break; 4047 default: 4048 break; 4049 } 4050 4051 return 0; 4052 } 4053 4054 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4055 struct amdgpu_irq_src *source, 4056 unsigned type, 4057 enum amdgpu_interrupt_state state) 4058 { 4059 switch (state) { 4060 case AMDGPU_IRQ_STATE_DISABLE: 4061 case AMDGPU_IRQ_STATE_ENABLE: 4062 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4063 PRIV_INSTR_INT_ENABLE, 4064 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4065 default: 4066 break; 4067 } 4068 4069 return 0; 4070 } 4071 4072 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4073 struct amdgpu_irq_src *src, 4074 unsigned type, 4075 enum amdgpu_interrupt_state state) 4076 { 4077 switch (type) { 4078 case AMDGPU_CP_IRQ_GFX_EOP: 4079 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4080 break; 4081 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4082 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4083 break; 4084 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4085 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4086 break; 4087 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4088 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4089 break; 4090 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4091 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4092 break; 4093 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4094 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4095 break; 4096 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4097 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4098 break; 4099 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4100 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4101 break; 4102 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4103 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4104 break; 4105 default: 4106 break; 4107 } 4108 return 0; 4109 } 4110 4111 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4112 struct amdgpu_irq_src *source, 4113 struct amdgpu_iv_entry *entry) 4114 { 4115 int i; 4116 u8 me_id, pipe_id, queue_id; 4117 struct amdgpu_ring *ring; 4118 4119 DRM_DEBUG("IH: CP EOP\n"); 4120 me_id = (entry->ring_id & 0x0c) >> 2; 4121 pipe_id = (entry->ring_id & 0x03) >> 0; 4122 queue_id = (entry->ring_id & 0x70) >> 4; 4123 4124 switch (me_id) { 4125 case 0: 4126 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4127 break; 4128 case 1: 4129 case 2: 4130 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4131 ring = &adev->gfx.compute_ring[i]; 4132 /* Per-queue interrupt is supported for MEC starting from VI. 4133 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4134 */ 4135 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4136 amdgpu_fence_process(ring); 4137 } 4138 break; 4139 } 4140 return 0; 4141 } 4142 4143 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4144 struct amdgpu_irq_src *source, 4145 struct amdgpu_iv_entry *entry) 4146 { 4147 DRM_ERROR("Illegal register access in command stream\n"); 4148 schedule_work(&adev->reset_work); 4149 return 0; 4150 } 4151 4152 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4153 struct amdgpu_irq_src *source, 4154 struct amdgpu_iv_entry *entry) 4155 { 4156 DRM_ERROR("Illegal instruction in command stream\n"); 4157 schedule_work(&adev->reset_work); 4158 return 0; 4159 } 4160 4161 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4162 struct amdgpu_irq_src *src, 4163 unsigned int type, 4164 enum amdgpu_interrupt_state state) 4165 { 4166 uint32_t tmp, target; 4167 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4168 4169 if (ring->me == 1) 4170 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4171 else 4172 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4173 target += ring->pipe; 4174 4175 switch (type) { 4176 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4177 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4178 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4179 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4180 GENERIC2_INT_ENABLE, 0); 4181 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4182 4183 tmp = RREG32(target); 4184 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4185 GENERIC2_INT_ENABLE, 0); 4186 WREG32(target, tmp); 4187 } else { 4188 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4189 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4190 GENERIC2_INT_ENABLE, 1); 4191 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4192 4193 tmp = RREG32(target); 4194 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4195 GENERIC2_INT_ENABLE, 1); 4196 WREG32(target, tmp); 4197 } 4198 break; 4199 default: 4200 BUG(); /* kiq only support GENERIC2_INT now */ 4201 break; 4202 } 4203 return 0; 4204 } 4205 4206 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, 4207 struct amdgpu_irq_src *source, 4208 struct amdgpu_iv_entry *entry) 4209 { 4210 u8 me_id, pipe_id, queue_id; 4211 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4212 4213 me_id = (entry->ring_id & 0x0c) >> 2; 4214 pipe_id = (entry->ring_id & 0x03) >> 0; 4215 queue_id = (entry->ring_id & 0x70) >> 4; 4216 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 4217 me_id, pipe_id, queue_id); 4218 4219 amdgpu_fence_process(ring); 4220 return 0; 4221 } 4222 4223 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4224 .name = "gfx_v9_0", 4225 .early_init = gfx_v9_0_early_init, 4226 .late_init = gfx_v9_0_late_init, 4227 .sw_init = gfx_v9_0_sw_init, 4228 .sw_fini = gfx_v9_0_sw_fini, 4229 .hw_init = gfx_v9_0_hw_init, 4230 .hw_fini = gfx_v9_0_hw_fini, 4231 .suspend = gfx_v9_0_suspend, 4232 .resume = gfx_v9_0_resume, 4233 .is_idle = gfx_v9_0_is_idle, 4234 .wait_for_idle = gfx_v9_0_wait_for_idle, 4235 .soft_reset = gfx_v9_0_soft_reset, 4236 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4237 .set_powergating_state = gfx_v9_0_set_powergating_state, 4238 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4239 }; 4240 4241 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4242 .type = AMDGPU_RING_TYPE_GFX, 4243 .align_mask = 0xff, 4244 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4245 .support_64bit_ptrs = true, 4246 .vmhub = AMDGPU_GFXHUB, 4247 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4248 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4249 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4250 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4251 5 + /* COND_EXEC */ 4252 7 + /* PIPELINE_SYNC */ 4253 24 + /* VM_FLUSH */ 4254 8 + /* FENCE for VM_FLUSH */ 4255 20 + /* GDS switch */ 4256 4 + /* double SWITCH_BUFFER, 4257 the first COND_EXEC jump to the place just 4258 prior to this double SWITCH_BUFFER */ 4259 5 + /* COND_EXEC */ 4260 7 + /* HDP_flush */ 4261 4 + /* VGT_flush */ 4262 14 + /* CE_META */ 4263 31 + /* DE_META */ 4264 3 + /* CNTX_CTRL */ 4265 5 + /* HDP_INVL */ 4266 8 + 8 + /* FENCE x2 */ 4267 2, /* SWITCH_BUFFER */ 4268 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4269 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4270 .emit_fence = gfx_v9_0_ring_emit_fence, 4271 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4272 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4273 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4274 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4275 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4276 .test_ring = gfx_v9_0_ring_test_ring, 4277 .test_ib = gfx_v9_0_ring_test_ib, 4278 .insert_nop = amdgpu_ring_insert_nop, 4279 .pad_ib = amdgpu_ring_generic_pad_ib, 4280 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4281 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4282 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4283 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4284 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4285 }; 4286 4287 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4288 .type = AMDGPU_RING_TYPE_COMPUTE, 4289 .align_mask = 0xff, 4290 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4291 .support_64bit_ptrs = true, 4292 .vmhub = AMDGPU_GFXHUB, 4293 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4294 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4295 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4296 .emit_frame_size = 4297 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4298 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4299 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4300 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4301 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4302 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4303 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4304 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4305 .emit_fence = gfx_v9_0_ring_emit_fence, 4306 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4307 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4308 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4309 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4310 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4311 .test_ring = gfx_v9_0_ring_test_ring, 4312 .test_ib = gfx_v9_0_ring_test_ib, 4313 .insert_nop = amdgpu_ring_insert_nop, 4314 .pad_ib = amdgpu_ring_generic_pad_ib, 4315 }; 4316 4317 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4318 .type = AMDGPU_RING_TYPE_KIQ, 4319 .align_mask = 0xff, 4320 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4321 .support_64bit_ptrs = true, 4322 .vmhub = AMDGPU_GFXHUB, 4323 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4324 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4325 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4326 .emit_frame_size = 4327 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4328 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4329 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4330 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4331 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4332 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4333 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4334 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4335 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4336 .test_ring = gfx_v9_0_ring_test_ring, 4337 .test_ib = gfx_v9_0_ring_test_ib, 4338 .insert_nop = amdgpu_ring_insert_nop, 4339 .pad_ib = amdgpu_ring_generic_pad_ib, 4340 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4341 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4342 }; 4343 4344 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4345 { 4346 int i; 4347 4348 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4349 4350 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4351 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4352 4353 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4354 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 4355 } 4356 4357 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { 4358 .set = gfx_v9_0_kiq_set_interrupt_state, 4359 .process = gfx_v9_0_kiq_irq, 4360 }; 4361 4362 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 4363 .set = gfx_v9_0_set_eop_interrupt_state, 4364 .process = gfx_v9_0_eop_irq, 4365 }; 4366 4367 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 4368 .set = gfx_v9_0_set_priv_reg_fault_state, 4369 .process = gfx_v9_0_priv_reg_irq, 4370 }; 4371 4372 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 4373 .set = gfx_v9_0_set_priv_inst_fault_state, 4374 .process = gfx_v9_0_priv_inst_irq, 4375 }; 4376 4377 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 4378 { 4379 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4380 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 4381 4382 adev->gfx.priv_reg_irq.num_types = 1; 4383 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 4384 4385 adev->gfx.priv_inst_irq.num_types = 1; 4386 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 4387 4388 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 4389 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; 4390 } 4391 4392 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 4393 { 4394 switch (adev->asic_type) { 4395 case CHIP_VEGA10: 4396 case CHIP_RAVEN: 4397 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4398 break; 4399 default: 4400 break; 4401 } 4402 } 4403 4404 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4405 { 4406 /* init asci gds info */ 4407 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4408 adev->gds.gws.total_size = 64; 4409 adev->gds.oa.total_size = 16; 4410 4411 if (adev->gds.mem.total_size == 64 * 1024) { 4412 adev->gds.mem.gfx_partition_size = 4096; 4413 adev->gds.mem.cs_partition_size = 4096; 4414 4415 adev->gds.gws.gfx_partition_size = 4; 4416 adev->gds.gws.cs_partition_size = 4; 4417 4418 adev->gds.oa.gfx_partition_size = 4; 4419 adev->gds.oa.cs_partition_size = 1; 4420 } else { 4421 adev->gds.mem.gfx_partition_size = 1024; 4422 adev->gds.mem.cs_partition_size = 1024; 4423 4424 adev->gds.gws.gfx_partition_size = 16; 4425 adev->gds.gws.cs_partition_size = 16; 4426 4427 adev->gds.oa.gfx_partition_size = 4; 4428 adev->gds.oa.cs_partition_size = 4; 4429 } 4430 } 4431 4432 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4433 u32 bitmap) 4434 { 4435 u32 data; 4436 4437 if (!bitmap) 4438 return; 4439 4440 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4441 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4442 4443 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 4444 } 4445 4446 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4447 { 4448 u32 data, mask; 4449 4450 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 4451 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 4452 4453 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4454 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4455 4456 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4457 4458 return (~data) & mask; 4459 } 4460 4461 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 4462 struct amdgpu_cu_info *cu_info) 4463 { 4464 int i, j, k, counter, active_cu_number = 0; 4465 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4466 unsigned disable_masks[4 * 2]; 4467 4468 if (!adev || !cu_info) 4469 return -EINVAL; 4470 4471 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 4472 4473 mutex_lock(&adev->grbm_idx_mutex); 4474 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4476 mask = 1; 4477 ao_bitmap = 0; 4478 counter = 0; 4479 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4480 if (i < 4 && j < 2) 4481 gfx_v9_0_set_user_cu_inactive_bitmap( 4482 adev, disable_masks[i * 2 + j]); 4483 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4484 cu_info->bitmap[i][j] = bitmap; 4485 4486 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4487 if (bitmap & mask) { 4488 if (counter < adev->gfx.config.max_cu_per_sh) 4489 ao_bitmap |= mask; 4490 counter ++; 4491 } 4492 mask <<= 1; 4493 } 4494 active_cu_number += counter; 4495 if (i < 2 && j < 2) 4496 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4497 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4498 } 4499 } 4500 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4501 mutex_unlock(&adev->grbm_idx_mutex); 4502 4503 cu_info->number = active_cu_number; 4504 cu_info->ao_cu_mask = ao_cu_mask; 4505 4506 return 0; 4507 } 4508 4509 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4510 { 4511 .type = AMD_IP_BLOCK_TYPE_GFX, 4512 .major = 9, 4513 .minor = 0, 4514 .rev = 0, 4515 .funcs = &gfx_v9_0_ip_funcs, 4516 }; 4517