1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 30 #include "vega10/soc15ip.h" 31 #include "vega10/GC/gc_9_0_offset.h" 32 #include "vega10/GC/gc_9_0_sh_mask.h" 33 #include "vega10/vega10_enum.h" 34 #include "vega10/HDP/hdp_4_0_offset.h" 35 36 #include "soc15_common.h" 37 #include "clearstate_gfx9.h" 38 #include "v9_structs.h" 39 40 #define GFX9_NUM_GFX_RINGS 1 41 #define GFX9_NUM_COMPUTE_RINGS 8 42 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 43 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 44 #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34 45 46 #define mmPWR_MISC_CNTL_STATUS 0x0183 47 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 48 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 49 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 52 53 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 54 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 56 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 57 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 59 60 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 61 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 62 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 63 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 64 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 65 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 66 67 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 68 { 69 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 70 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)}, 71 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE), 72 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)}, 73 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE), 74 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)}, 75 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE), 76 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)}, 77 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE), 78 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)}, 79 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE), 80 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)}, 81 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE), 82 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)}, 83 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE), 84 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)}, 85 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE), 86 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)}, 87 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE), 88 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)}, 89 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE), 90 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)}, 91 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE), 92 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)}, 93 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE), 94 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)}, 95 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE), 96 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)}, 97 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE), 98 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)}, 99 {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE), 100 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)} 101 }; 102 103 static const u32 golden_settings_gc_9_0[] = 104 { 105 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00ffeff, 0x00000400, 106 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 107 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 108 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 109 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 110 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68, 111 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197, 112 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff 113 }; 114 115 static const u32 golden_settings_gc_9_0_vg10[] = 116 { 117 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107, 118 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000, 119 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042, 120 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042, 121 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000, 122 SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000, 123 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800, 124 SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1),0x0000000f, 0x00000007 125 }; 126 127 static const u32 golden_settings_gc_9_1[] = 128 { 129 SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104, 130 SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420, 131 SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000, 132 SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024, 133 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001, 134 SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000, 135 SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000, 136 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000, 137 SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120, 138 SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff 139 }; 140 141 static const u32 golden_settings_gc_9_1_rv1[] = 142 { 143 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x26013042, 144 SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x26013042, 145 SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x00048000, 146 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 147 }; 148 149 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 150 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x26013042 151 152 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 153 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 154 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 155 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 156 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 157 struct amdgpu_cu_info *cu_info); 158 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 159 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 160 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 161 162 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 163 { 164 switch (adev->asic_type) { 165 case CHIP_VEGA10: 166 amdgpu_program_register_sequence(adev, 167 golden_settings_gc_9_0, 168 (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); 169 amdgpu_program_register_sequence(adev, 170 golden_settings_gc_9_0_vg10, 171 (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 172 break; 173 case CHIP_RAVEN: 174 amdgpu_program_register_sequence(adev, 175 golden_settings_gc_9_1, 176 (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); 177 amdgpu_program_register_sequence(adev, 178 golden_settings_gc_9_1_rv1, 179 (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 180 break; 181 default: 182 break; 183 } 184 } 185 186 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 187 { 188 adev->gfx.scratch.num_reg = 7; 189 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 190 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 191 } 192 193 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 194 bool wc, uint32_t reg, uint32_t val) 195 { 196 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 197 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 198 WRITE_DATA_DST_SEL(0) | 199 (wc ? WR_CONFIRM : 0)); 200 amdgpu_ring_write(ring, reg); 201 amdgpu_ring_write(ring, 0); 202 amdgpu_ring_write(ring, val); 203 } 204 205 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 206 int mem_space, int opt, uint32_t addr0, 207 uint32_t addr1, uint32_t ref, uint32_t mask, 208 uint32_t inv) 209 { 210 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 211 amdgpu_ring_write(ring, 212 /* memory (1) or register (0) */ 213 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 214 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 215 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 216 WAIT_REG_MEM_ENGINE(eng_sel))); 217 218 if (mem_space) 219 BUG_ON(addr0 & 0x3); /* Dword align */ 220 amdgpu_ring_write(ring, addr0); 221 amdgpu_ring_write(ring, addr1); 222 amdgpu_ring_write(ring, ref); 223 amdgpu_ring_write(ring, mask); 224 amdgpu_ring_write(ring, inv); /* poll interval */ 225 } 226 227 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 228 { 229 struct amdgpu_device *adev = ring->adev; 230 uint32_t scratch; 231 uint32_t tmp = 0; 232 unsigned i; 233 int r; 234 235 r = amdgpu_gfx_scratch_get(adev, &scratch); 236 if (r) { 237 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 238 return r; 239 } 240 WREG32(scratch, 0xCAFEDEAD); 241 r = amdgpu_ring_alloc(ring, 3); 242 if (r) { 243 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 244 ring->idx, r); 245 amdgpu_gfx_scratch_free(adev, scratch); 246 return r; 247 } 248 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 249 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 250 amdgpu_ring_write(ring, 0xDEADBEEF); 251 amdgpu_ring_commit(ring); 252 253 for (i = 0; i < adev->usec_timeout; i++) { 254 tmp = RREG32(scratch); 255 if (tmp == 0xDEADBEEF) 256 break; 257 DRM_UDELAY(1); 258 } 259 if (i < adev->usec_timeout) { 260 DRM_INFO("ring test on %d succeeded in %d usecs\n", 261 ring->idx, i); 262 } else { 263 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 264 ring->idx, scratch, tmp); 265 r = -EINVAL; 266 } 267 amdgpu_gfx_scratch_free(adev, scratch); 268 return r; 269 } 270 271 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 272 { 273 struct amdgpu_device *adev = ring->adev; 274 struct amdgpu_ib ib; 275 struct dma_fence *f = NULL; 276 uint32_t scratch; 277 uint32_t tmp = 0; 278 long r; 279 280 r = amdgpu_gfx_scratch_get(adev, &scratch); 281 if (r) { 282 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 283 return r; 284 } 285 WREG32(scratch, 0xCAFEDEAD); 286 memset(&ib, 0, sizeof(ib)); 287 r = amdgpu_ib_get(adev, NULL, 256, &ib); 288 if (r) { 289 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 290 goto err1; 291 } 292 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 293 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 294 ib.ptr[2] = 0xDEADBEEF; 295 ib.length_dw = 3; 296 297 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 298 if (r) 299 goto err2; 300 301 r = dma_fence_wait_timeout(f, false, timeout); 302 if (r == 0) { 303 DRM_ERROR("amdgpu: IB test timed out.\n"); 304 r = -ETIMEDOUT; 305 goto err2; 306 } else if (r < 0) { 307 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 308 goto err2; 309 } 310 tmp = RREG32(scratch); 311 if (tmp == 0xDEADBEEF) { 312 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 313 r = 0; 314 } else { 315 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 316 scratch, tmp); 317 r = -EINVAL; 318 } 319 err2: 320 amdgpu_ib_free(adev, &ib, NULL); 321 dma_fence_put(f); 322 err1: 323 amdgpu_gfx_scratch_free(adev, scratch); 324 return r; 325 } 326 327 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 328 { 329 const char *chip_name; 330 char fw_name[30]; 331 int err; 332 struct amdgpu_firmware_info *info = NULL; 333 const struct common_firmware_header *header = NULL; 334 const struct gfx_firmware_header_v1_0 *cp_hdr; 335 const struct rlc_firmware_header_v2_0 *rlc_hdr; 336 unsigned int *tmp = NULL; 337 unsigned int i = 0; 338 339 DRM_DEBUG("\n"); 340 341 switch (adev->asic_type) { 342 case CHIP_VEGA10: 343 chip_name = "vega10"; 344 break; 345 case CHIP_RAVEN: 346 chip_name = "raven"; 347 break; 348 default: 349 BUG(); 350 } 351 352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 353 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 354 if (err) 355 goto out; 356 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 357 if (err) 358 goto out; 359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 360 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 361 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 362 363 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 364 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 365 if (err) 366 goto out; 367 err = amdgpu_ucode_validate(adev->gfx.me_fw); 368 if (err) 369 goto out; 370 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 371 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 372 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 373 374 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 375 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 376 if (err) 377 goto out; 378 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 379 if (err) 380 goto out; 381 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 382 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 383 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 384 385 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 386 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 387 if (err) 388 goto out; 389 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 390 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 391 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 392 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 393 adev->gfx.rlc.save_and_restore_offset = 394 le32_to_cpu(rlc_hdr->save_and_restore_offset); 395 adev->gfx.rlc.clear_state_descriptor_offset = 396 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 397 adev->gfx.rlc.avail_scratch_ram_locations = 398 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 399 adev->gfx.rlc.reg_restore_list_size = 400 le32_to_cpu(rlc_hdr->reg_restore_list_size); 401 adev->gfx.rlc.reg_list_format_start = 402 le32_to_cpu(rlc_hdr->reg_list_format_start); 403 adev->gfx.rlc.reg_list_format_separate_start = 404 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 405 adev->gfx.rlc.starting_offsets_start = 406 le32_to_cpu(rlc_hdr->starting_offsets_start); 407 adev->gfx.rlc.reg_list_format_size_bytes = 408 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 409 adev->gfx.rlc.reg_list_size_bytes = 410 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 411 adev->gfx.rlc.register_list_format = 412 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 413 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 414 if (!adev->gfx.rlc.register_list_format) { 415 err = -ENOMEM; 416 goto out; 417 } 418 419 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 420 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 421 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 422 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 423 424 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 425 426 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 427 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 428 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 429 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 430 431 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 432 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 433 if (err) 434 goto out; 435 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 436 if (err) 437 goto out; 438 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 439 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 440 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 441 442 443 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 444 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 445 if (!err) { 446 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 447 if (err) 448 goto out; 449 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 450 adev->gfx.mec2_fw->data; 451 adev->gfx.mec2_fw_version = 452 le32_to_cpu(cp_hdr->header.ucode_version); 453 adev->gfx.mec2_feature_version = 454 le32_to_cpu(cp_hdr->ucode_feature_version); 455 } else { 456 err = 0; 457 adev->gfx.mec2_fw = NULL; 458 } 459 460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 461 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 462 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 463 info->fw = adev->gfx.pfp_fw; 464 header = (const struct common_firmware_header *)info->fw->data; 465 adev->firmware.fw_size += 466 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 467 468 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 469 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 470 info->fw = adev->gfx.me_fw; 471 header = (const struct common_firmware_header *)info->fw->data; 472 adev->firmware.fw_size += 473 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 474 475 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 476 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 477 info->fw = adev->gfx.ce_fw; 478 header = (const struct common_firmware_header *)info->fw->data; 479 adev->firmware.fw_size += 480 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 481 482 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 483 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 484 info->fw = adev->gfx.rlc_fw; 485 header = (const struct common_firmware_header *)info->fw->data; 486 adev->firmware.fw_size += 487 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 488 489 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 490 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 491 info->fw = adev->gfx.mec_fw; 492 header = (const struct common_firmware_header *)info->fw->data; 493 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 494 adev->firmware.fw_size += 495 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 496 497 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 498 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 499 info->fw = adev->gfx.mec_fw; 500 adev->firmware.fw_size += 501 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 502 503 if (adev->gfx.mec2_fw) { 504 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 505 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 506 info->fw = adev->gfx.mec2_fw; 507 header = (const struct common_firmware_header *)info->fw->data; 508 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 509 adev->firmware.fw_size += 510 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 511 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 512 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 513 info->fw = adev->gfx.mec2_fw; 514 adev->firmware.fw_size += 515 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 516 } 517 518 } 519 520 out: 521 if (err) { 522 dev_err(adev->dev, 523 "gfx9: Failed to load firmware \"%s\"\n", 524 fw_name); 525 release_firmware(adev->gfx.pfp_fw); 526 adev->gfx.pfp_fw = NULL; 527 release_firmware(adev->gfx.me_fw); 528 adev->gfx.me_fw = NULL; 529 release_firmware(adev->gfx.ce_fw); 530 adev->gfx.ce_fw = NULL; 531 release_firmware(adev->gfx.rlc_fw); 532 adev->gfx.rlc_fw = NULL; 533 release_firmware(adev->gfx.mec_fw); 534 adev->gfx.mec_fw = NULL; 535 release_firmware(adev->gfx.mec2_fw); 536 adev->gfx.mec2_fw = NULL; 537 } 538 return err; 539 } 540 541 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 542 { 543 u32 count = 0; 544 const struct cs_section_def *sect = NULL; 545 const struct cs_extent_def *ext = NULL; 546 547 /* begin clear state */ 548 count += 2; 549 /* context control state */ 550 count += 3; 551 552 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 553 for (ext = sect->section; ext->extent != NULL; ++ext) { 554 if (sect->id == SECT_CONTEXT) 555 count += 2 + ext->reg_count; 556 else 557 return 0; 558 } 559 } 560 561 /* end clear state */ 562 count += 2; 563 /* clear state */ 564 count += 2; 565 566 return count; 567 } 568 569 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 570 volatile u32 *buffer) 571 { 572 u32 count = 0, i; 573 const struct cs_section_def *sect = NULL; 574 const struct cs_extent_def *ext = NULL; 575 576 if (adev->gfx.rlc.cs_data == NULL) 577 return; 578 if (buffer == NULL) 579 return; 580 581 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 582 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 583 584 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 585 buffer[count++] = cpu_to_le32(0x80000000); 586 buffer[count++] = cpu_to_le32(0x80000000); 587 588 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 589 for (ext = sect->section; ext->extent != NULL; ++ext) { 590 if (sect->id == SECT_CONTEXT) { 591 buffer[count++] = 592 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 593 buffer[count++] = cpu_to_le32(ext->reg_index - 594 PACKET3_SET_CONTEXT_REG_START); 595 for (i = 0; i < ext->reg_count; i++) 596 buffer[count++] = cpu_to_le32(ext->extent[i]); 597 } else { 598 return; 599 } 600 } 601 } 602 603 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 604 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 605 606 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 607 buffer[count++] = cpu_to_le32(0); 608 } 609 610 static void rv_init_cp_jump_table(struct amdgpu_device *adev) 611 { 612 const __le32 *fw_data; 613 volatile u32 *dst_ptr; 614 int me, i, max_me = 5; 615 u32 bo_offset = 0; 616 u32 table_offset, table_size; 617 618 /* write the cp table buffer */ 619 dst_ptr = adev->gfx.rlc.cp_table_ptr; 620 for (me = 0; me < max_me; me++) { 621 if (me == 0) { 622 const struct gfx_firmware_header_v1_0 *hdr = 623 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 624 fw_data = (const __le32 *) 625 (adev->gfx.ce_fw->data + 626 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 627 table_offset = le32_to_cpu(hdr->jt_offset); 628 table_size = le32_to_cpu(hdr->jt_size); 629 } else if (me == 1) { 630 const struct gfx_firmware_header_v1_0 *hdr = 631 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 632 fw_data = (const __le32 *) 633 (adev->gfx.pfp_fw->data + 634 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 635 table_offset = le32_to_cpu(hdr->jt_offset); 636 table_size = le32_to_cpu(hdr->jt_size); 637 } else if (me == 2) { 638 const struct gfx_firmware_header_v1_0 *hdr = 639 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 640 fw_data = (const __le32 *) 641 (adev->gfx.me_fw->data + 642 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 643 table_offset = le32_to_cpu(hdr->jt_offset); 644 table_size = le32_to_cpu(hdr->jt_size); 645 } else if (me == 3) { 646 const struct gfx_firmware_header_v1_0 *hdr = 647 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 648 fw_data = (const __le32 *) 649 (adev->gfx.mec_fw->data + 650 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 651 table_offset = le32_to_cpu(hdr->jt_offset); 652 table_size = le32_to_cpu(hdr->jt_size); 653 } else if (me == 4) { 654 const struct gfx_firmware_header_v1_0 *hdr = 655 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 656 fw_data = (const __le32 *) 657 (adev->gfx.mec2_fw->data + 658 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 659 table_offset = le32_to_cpu(hdr->jt_offset); 660 table_size = le32_to_cpu(hdr->jt_size); 661 } 662 663 for (i = 0; i < table_size; i ++) { 664 dst_ptr[bo_offset + i] = 665 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 666 } 667 668 bo_offset += table_size; 669 } 670 } 671 672 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) 673 { 674 /* clear state block */ 675 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 676 &adev->gfx.rlc.clear_state_gpu_addr, 677 (void **)&adev->gfx.rlc.cs_ptr); 678 679 /* jump table block */ 680 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 681 &adev->gfx.rlc.cp_table_gpu_addr, 682 (void **)&adev->gfx.rlc.cp_table_ptr); 683 } 684 685 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 686 { 687 volatile u32 *dst_ptr; 688 u32 dws; 689 const struct cs_section_def *cs_data; 690 int r; 691 692 adev->gfx.rlc.cs_data = gfx9_cs_data; 693 694 cs_data = adev->gfx.rlc.cs_data; 695 696 if (cs_data) { 697 /* clear state block */ 698 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); 699 if (adev->gfx.rlc.clear_state_obj == NULL) { 700 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE, 701 AMDGPU_GEM_DOMAIN_VRAM, 702 &adev->gfx.rlc.clear_state_obj, 703 &adev->gfx.rlc.clear_state_gpu_addr, 704 (void **)&adev->gfx.rlc.cs_ptr); 705 if (r) { 706 dev_err(adev->dev, 707 "(%d) failed to create rlc csb bo\n", r); 708 gfx_v9_0_rlc_fini(adev); 709 return r; 710 } 711 } 712 /* set up the cs buffer */ 713 dst_ptr = adev->gfx.rlc.cs_ptr; 714 gfx_v9_0_get_csb_buffer(adev, dst_ptr); 715 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 716 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 717 } 718 719 if (adev->asic_type == CHIP_RAVEN) { 720 /* TODO: double check the cp_table_size for RV */ 721 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 722 if (adev->gfx.rlc.cp_table_obj == NULL) { 723 r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size, 724 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 725 &adev->gfx.rlc.cp_table_obj, 726 &adev->gfx.rlc.cp_table_gpu_addr, 727 (void **)&adev->gfx.rlc.cp_table_ptr); 728 if (r) { 729 dev_err(adev->dev, 730 "(%d) failed to create cp table bo\n", r); 731 gfx_v9_0_rlc_fini(adev); 732 return r; 733 } 734 } 735 736 rv_init_cp_jump_table(adev); 737 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 738 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 739 } 740 741 return 0; 742 } 743 744 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 745 { 746 int r; 747 748 if (adev->gfx.mec.hpd_eop_obj) { 749 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true); 750 if (unlikely(r != 0)) 751 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 752 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 753 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 754 755 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 756 adev->gfx.mec.hpd_eop_obj = NULL; 757 } 758 if (adev->gfx.mec.mec_fw_obj) { 759 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true); 760 if (unlikely(r != 0)) 761 dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r); 762 amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj); 763 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 764 765 amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj); 766 adev->gfx.mec.mec_fw_obj = NULL; 767 } 768 } 769 770 #define MEC_HPD_SIZE 2048 771 772 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 773 { 774 int r; 775 u32 *hpd; 776 const __le32 *fw_data; 777 unsigned fw_size; 778 u32 *fw; 779 780 const struct gfx_firmware_header_v1_0 *mec_hdr; 781 782 /* 783 * we assign only 1 pipe because all other pipes will 784 * be handled by KFD 785 */ 786 adev->gfx.mec.num_mec = 1; 787 adev->gfx.mec.num_pipe = 1; 788 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 789 790 if (adev->gfx.mec.hpd_eop_obj == NULL) { 791 r = amdgpu_bo_create(adev, 792 adev->gfx.mec.num_queue * MEC_HPD_SIZE, 793 PAGE_SIZE, true, 794 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 795 &adev->gfx.mec.hpd_eop_obj); 796 if (r) { 797 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 798 return r; 799 } 800 } 801 802 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 803 if (unlikely(r != 0)) { 804 gfx_v9_0_mec_fini(adev); 805 return r; 806 } 807 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 808 &adev->gfx.mec.hpd_eop_gpu_addr); 809 if (r) { 810 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 811 gfx_v9_0_mec_fini(adev); 812 return r; 813 } 814 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 815 if (r) { 816 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 817 gfx_v9_0_mec_fini(adev); 818 return r; 819 } 820 821 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 822 823 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 824 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 825 826 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 827 828 fw_data = (const __le32 *) 829 (adev->gfx.mec_fw->data + 830 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 831 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 832 833 if (adev->gfx.mec.mec_fw_obj == NULL) { 834 r = amdgpu_bo_create(adev, 835 mec_hdr->header.ucode_size_bytes, 836 PAGE_SIZE, true, 837 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 838 &adev->gfx.mec.mec_fw_obj); 839 if (r) { 840 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 841 return r; 842 } 843 } 844 845 r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false); 846 if (unlikely(r != 0)) { 847 gfx_v9_0_mec_fini(adev); 848 return r; 849 } 850 r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT, 851 &adev->gfx.mec.mec_fw_gpu_addr); 852 if (r) { 853 dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r); 854 gfx_v9_0_mec_fini(adev); 855 return r; 856 } 857 r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw); 858 if (r) { 859 dev_warn(adev->dev, "(%d) map firmware bo failed\n", r); 860 gfx_v9_0_mec_fini(adev); 861 return r; 862 } 863 memcpy(fw, fw_data, fw_size); 864 865 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 866 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 867 868 869 return 0; 870 } 871 872 static void gfx_v9_0_kiq_fini(struct amdgpu_device *adev) 873 { 874 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 875 876 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 877 } 878 879 static int gfx_v9_0_kiq_init(struct amdgpu_device *adev) 880 { 881 int r; 882 u32 *hpd; 883 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 884 885 r = amdgpu_bo_create_kernel(adev, MEC_HPD_SIZE, PAGE_SIZE, 886 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 887 &kiq->eop_gpu_addr, (void **)&hpd); 888 if (r) { 889 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 890 return r; 891 } 892 893 memset(hpd, 0, MEC_HPD_SIZE); 894 895 r = amdgpu_bo_reserve(kiq->eop_obj, true); 896 if (unlikely(r != 0)) 897 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 898 amdgpu_bo_kunmap(kiq->eop_obj); 899 amdgpu_bo_unreserve(kiq->eop_obj); 900 901 return 0; 902 } 903 904 static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, 905 struct amdgpu_ring *ring, 906 struct amdgpu_irq_src *irq) 907 { 908 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 909 int r = 0; 910 911 mutex_init(&kiq->ring_mutex); 912 913 r = amdgpu_wb_get(adev, &adev->virt.reg_val_offs); 914 if (r) 915 return r; 916 917 ring->adev = NULL; 918 ring->ring_obj = NULL; 919 ring->use_doorbell = true; 920 ring->doorbell_index = AMDGPU_DOORBELL_KIQ; 921 if (adev->gfx.mec2_fw) { 922 ring->me = 2; 923 ring->pipe = 0; 924 } else { 925 ring->me = 1; 926 ring->pipe = 1; 927 } 928 929 ring->queue = 0; 930 ring->eop_gpu_addr = kiq->eop_gpu_addr; 931 sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); 932 r = amdgpu_ring_init(adev, ring, 1024, 933 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); 934 if (r) 935 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 936 937 return r; 938 } 939 static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, 940 struct amdgpu_irq_src *irq) 941 { 942 amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); 943 amdgpu_ring_fini(ring); 944 } 945 946 /* create MQD for each compute queue */ 947 static int gfx_v9_0_compute_mqd_sw_init(struct amdgpu_device *adev) 948 { 949 struct amdgpu_ring *ring = NULL; 950 int r, i; 951 952 /* create MQD for KIQ */ 953 ring = &adev->gfx.kiq.ring; 954 if (!ring->mqd_obj) { 955 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, 956 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 957 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 958 if (r) { 959 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 960 return r; 961 } 962 963 /* prepare MQD backup */ 964 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL); 965 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) 966 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 967 } 968 969 /* create MQD for each KCQ */ 970 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 971 ring = &adev->gfx.compute_ring[i]; 972 if (!ring->mqd_obj) { 973 r = amdgpu_bo_create_kernel(adev, sizeof(struct v9_mqd), PAGE_SIZE, 974 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 975 &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 976 if (r) { 977 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 978 return r; 979 } 980 981 /* prepare MQD backup */ 982 adev->gfx.mec.mqd_backup[i] = kmalloc(sizeof(struct v9_mqd), GFP_KERNEL); 983 if (!adev->gfx.mec.mqd_backup[i]) 984 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 985 } 986 } 987 988 return 0; 989 } 990 991 static void gfx_v9_0_compute_mqd_sw_fini(struct amdgpu_device *adev) 992 { 993 struct amdgpu_ring *ring = NULL; 994 int i; 995 996 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 997 ring = &adev->gfx.compute_ring[i]; 998 kfree(adev->gfx.mec.mqd_backup[i]); 999 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 1000 } 1001 1002 ring = &adev->gfx.kiq.ring; 1003 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); 1004 amdgpu_bo_free_kernel(&ring->mqd_obj, &ring->mqd_gpu_addr, (void **)&ring->mqd_ptr); 1005 } 1006 1007 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1008 { 1009 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1010 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1011 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1012 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1013 (SQ_IND_INDEX__FORCE_READ_MASK)); 1014 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1015 } 1016 1017 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1018 uint32_t wave, uint32_t thread, 1019 uint32_t regno, uint32_t num, uint32_t *out) 1020 { 1021 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1022 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1023 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1024 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1025 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1026 (SQ_IND_INDEX__FORCE_READ_MASK) | 1027 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1028 while (num--) 1029 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1030 } 1031 1032 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1033 { 1034 /* type 1 wave data */ 1035 dst[(*no_fields)++] = 1; 1036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1050 } 1051 1052 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1053 uint32_t wave, uint32_t start, 1054 uint32_t size, uint32_t *dst) 1055 { 1056 wave_read_regs( 1057 adev, simd, wave, 0, 1058 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1059 } 1060 1061 1062 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1063 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1064 .select_se_sh = &gfx_v9_0_select_se_sh, 1065 .read_wave_data = &gfx_v9_0_read_wave_data, 1066 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1067 }; 1068 1069 static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1070 { 1071 u32 gb_addr_config; 1072 1073 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1074 1075 switch (adev->asic_type) { 1076 case CHIP_VEGA10: 1077 adev->gfx.config.max_hw_contexts = 8; 1078 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1079 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1080 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1081 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1082 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1083 break; 1084 case CHIP_RAVEN: 1085 adev->gfx.config.max_hw_contexts = 8; 1086 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1087 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1088 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1089 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1090 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1091 break; 1092 default: 1093 BUG(); 1094 break; 1095 } 1096 1097 adev->gfx.config.gb_addr_config = gb_addr_config; 1098 1099 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1100 REG_GET_FIELD( 1101 adev->gfx.config.gb_addr_config, 1102 GB_ADDR_CONFIG, 1103 NUM_PIPES); 1104 1105 adev->gfx.config.max_tile_pipes = 1106 adev->gfx.config.gb_addr_config_fields.num_pipes; 1107 1108 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1109 REG_GET_FIELD( 1110 adev->gfx.config.gb_addr_config, 1111 GB_ADDR_CONFIG, 1112 NUM_BANKS); 1113 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1114 REG_GET_FIELD( 1115 adev->gfx.config.gb_addr_config, 1116 GB_ADDR_CONFIG, 1117 MAX_COMPRESSED_FRAGS); 1118 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1119 REG_GET_FIELD( 1120 adev->gfx.config.gb_addr_config, 1121 GB_ADDR_CONFIG, 1122 NUM_RB_PER_SE); 1123 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1124 REG_GET_FIELD( 1125 adev->gfx.config.gb_addr_config, 1126 GB_ADDR_CONFIG, 1127 NUM_SHADER_ENGINES); 1128 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1129 REG_GET_FIELD( 1130 adev->gfx.config.gb_addr_config, 1131 GB_ADDR_CONFIG, 1132 PIPE_INTERLEAVE_SIZE)); 1133 } 1134 1135 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1136 struct amdgpu_ngg_buf *ngg_buf, 1137 int size_se, 1138 int default_size_se) 1139 { 1140 int r; 1141 1142 if (size_se < 0) { 1143 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1144 return -EINVAL; 1145 } 1146 size_se = size_se ? size_se : default_size_se; 1147 1148 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1149 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1150 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1151 &ngg_buf->bo, 1152 &ngg_buf->gpu_addr, 1153 NULL); 1154 if (r) { 1155 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1156 return r; 1157 } 1158 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1159 1160 return r; 1161 } 1162 1163 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1164 { 1165 int i; 1166 1167 for (i = 0; i < NGG_BUF_MAX; i++) 1168 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1169 &adev->gfx.ngg.buf[i].gpu_addr, 1170 NULL); 1171 1172 memset(&adev->gfx.ngg.buf[0], 0, 1173 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1174 1175 adev->gfx.ngg.init = false; 1176 1177 return 0; 1178 } 1179 1180 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1181 { 1182 int r; 1183 1184 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1185 return 0; 1186 1187 /* GDS reserve memory: 64 bytes alignment */ 1188 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1189 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1190 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1191 adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base; 1192 adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; 1193 1194 /* Primitive Buffer */ 1195 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1196 amdgpu_prim_buf_per_se, 1197 64 * 1024); 1198 if (r) { 1199 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1200 goto err; 1201 } 1202 1203 /* Position Buffer */ 1204 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1205 amdgpu_pos_buf_per_se, 1206 256 * 1024); 1207 if (r) { 1208 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1209 goto err; 1210 } 1211 1212 /* Control Sideband */ 1213 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1214 amdgpu_cntl_sb_buf_per_se, 1215 256); 1216 if (r) { 1217 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1218 goto err; 1219 } 1220 1221 /* Parameter Cache, not created by default */ 1222 if (amdgpu_param_buf_per_se <= 0) 1223 goto out; 1224 1225 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1226 amdgpu_param_buf_per_se, 1227 512 * 1024); 1228 if (r) { 1229 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1230 goto err; 1231 } 1232 1233 out: 1234 adev->gfx.ngg.init = true; 1235 return 0; 1236 err: 1237 gfx_v9_0_ngg_fini(adev); 1238 return r; 1239 } 1240 1241 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1242 { 1243 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1244 int r; 1245 u32 data; 1246 u32 size; 1247 u32 base; 1248 1249 if (!amdgpu_ngg) 1250 return 0; 1251 1252 /* Program buffer size */ 1253 data = 0; 1254 size = adev->gfx.ngg.buf[NGG_PRIM].size / 256; 1255 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size); 1256 1257 size = adev->gfx.ngg.buf[NGG_POS].size / 256; 1258 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size); 1259 1260 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1261 1262 data = 0; 1263 size = adev->gfx.ngg.buf[NGG_CNTL].size / 256; 1264 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size); 1265 1266 size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024; 1267 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size); 1268 1269 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1270 1271 /* Program buffer base address */ 1272 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1273 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1274 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1275 1276 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1277 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1278 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1279 1280 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1281 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1282 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1283 1284 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1285 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1286 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1287 1288 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1289 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1290 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1291 1292 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1293 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1294 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1295 1296 /* Clear GDS reserved memory */ 1297 r = amdgpu_ring_alloc(ring, 17); 1298 if (r) { 1299 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", 1300 ring->idx, r); 1301 return r; 1302 } 1303 1304 gfx_v9_0_write_data_to_reg(ring, 0, false, 1305 amdgpu_gds_reg_offset[0].mem_size, 1306 (adev->gds.mem.total_size + 1307 adev->gfx.ngg.gds_reserve_size) >> 1308 AMDGPU_GDS_SHIFT); 1309 1310 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1311 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1312 PACKET3_DMA_DATA_SRC_SEL(2))); 1313 amdgpu_ring_write(ring, 0); 1314 amdgpu_ring_write(ring, 0); 1315 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1316 amdgpu_ring_write(ring, 0); 1317 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); 1318 1319 1320 gfx_v9_0_write_data_to_reg(ring, 0, false, 1321 amdgpu_gds_reg_offset[0].mem_size, 0); 1322 1323 amdgpu_ring_commit(ring); 1324 1325 return 0; 1326 } 1327 1328 static int gfx_v9_0_sw_init(void *handle) 1329 { 1330 int i, r; 1331 struct amdgpu_ring *ring; 1332 struct amdgpu_kiq *kiq; 1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1334 1335 /* KIQ event */ 1336 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq); 1337 if (r) 1338 return r; 1339 1340 /* EOP Event */ 1341 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq); 1342 if (r) 1343 return r; 1344 1345 /* Privileged reg */ 1346 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184, 1347 &adev->gfx.priv_reg_irq); 1348 if (r) 1349 return r; 1350 1351 /* Privileged inst */ 1352 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185, 1353 &adev->gfx.priv_inst_irq); 1354 if (r) 1355 return r; 1356 1357 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1358 1359 gfx_v9_0_scratch_init(adev); 1360 1361 r = gfx_v9_0_init_microcode(adev); 1362 if (r) { 1363 DRM_ERROR("Failed to load gfx firmware!\n"); 1364 return r; 1365 } 1366 1367 r = gfx_v9_0_rlc_init(adev); 1368 if (r) { 1369 DRM_ERROR("Failed to init rlc BOs!\n"); 1370 return r; 1371 } 1372 1373 r = gfx_v9_0_mec_init(adev); 1374 if (r) { 1375 DRM_ERROR("Failed to init MEC BOs!\n"); 1376 return r; 1377 } 1378 1379 /* set up the gfx ring */ 1380 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1381 ring = &adev->gfx.gfx_ring[i]; 1382 ring->ring_obj = NULL; 1383 sprintf(ring->name, "gfx"); 1384 ring->use_doorbell = true; 1385 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; 1386 r = amdgpu_ring_init(adev, ring, 1024, 1387 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1388 if (r) 1389 return r; 1390 } 1391 1392 /* set up the compute queues */ 1393 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1394 unsigned irq_type; 1395 1396 /* max 32 queues per MEC */ 1397 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 1398 DRM_ERROR("Too many (%d) compute rings!\n", i); 1399 break; 1400 } 1401 ring = &adev->gfx.compute_ring[i]; 1402 ring->ring_obj = NULL; 1403 ring->use_doorbell = true; 1404 ring->doorbell_index = (AMDGPU_DOORBELL64_MEC_RING0 + i) << 1; 1405 ring->me = 1; /* first MEC */ 1406 ring->pipe = i / 8; 1407 ring->queue = i % 8; 1408 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 1409 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1410 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 1411 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1412 r = amdgpu_ring_init(adev, ring, 1024, 1413 &adev->gfx.eop_irq, irq_type); 1414 if (r) 1415 return r; 1416 } 1417 1418 if (amdgpu_sriov_vf(adev)) { 1419 r = gfx_v9_0_kiq_init(adev); 1420 if (r) { 1421 DRM_ERROR("Failed to init KIQ BOs!\n"); 1422 return r; 1423 } 1424 1425 kiq = &adev->gfx.kiq; 1426 r = gfx_v9_0_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1427 if (r) 1428 return r; 1429 1430 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1431 r = gfx_v9_0_compute_mqd_sw_init(adev); 1432 if (r) 1433 return r; 1434 } 1435 1436 /* reserve GDS, GWS and OA resource for gfx */ 1437 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 1438 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 1439 &adev->gds.gds_gfx_bo, NULL, NULL); 1440 if (r) 1441 return r; 1442 1443 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 1444 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 1445 &adev->gds.gws_gfx_bo, NULL, NULL); 1446 if (r) 1447 return r; 1448 1449 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 1450 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 1451 &adev->gds.oa_gfx_bo, NULL, NULL); 1452 if (r) 1453 return r; 1454 1455 adev->gfx.ce_ram_size = 0x8000; 1456 1457 gfx_v9_0_gpu_early_init(adev); 1458 1459 r = gfx_v9_0_ngg_init(adev); 1460 if (r) 1461 return r; 1462 1463 return 0; 1464 } 1465 1466 1467 static int gfx_v9_0_sw_fini(void *handle) 1468 { 1469 int i; 1470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1471 1472 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1473 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1474 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1475 1476 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1477 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1478 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1479 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1480 1481 if (amdgpu_sriov_vf(adev)) { 1482 gfx_v9_0_compute_mqd_sw_fini(adev); 1483 gfx_v9_0_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1484 gfx_v9_0_kiq_fini(adev); 1485 } 1486 1487 gfx_v9_0_mec_fini(adev); 1488 gfx_v9_0_ngg_fini(adev); 1489 1490 return 0; 1491 } 1492 1493 1494 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1495 { 1496 /* TODO */ 1497 } 1498 1499 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1500 { 1501 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1502 1503 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { 1504 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1505 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1506 } else if (se_num == 0xffffffff) { 1507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1508 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1509 } else if (sh_num == 0xffffffff) { 1510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1511 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1512 } else { 1513 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1514 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1515 } 1516 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1517 } 1518 1519 static u32 gfx_v9_0_create_bitmask(u32 bit_width) 1520 { 1521 return (u32)((1ULL << bit_width) - 1); 1522 } 1523 1524 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1525 { 1526 u32 data, mask; 1527 1528 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1529 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1530 1531 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1532 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1533 1534 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se / 1535 adev->gfx.config.max_sh_per_se); 1536 1537 return (~data) & mask; 1538 } 1539 1540 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1541 { 1542 int i, j; 1543 u32 data; 1544 u32 active_rbs = 0; 1545 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1546 adev->gfx.config.max_sh_per_se; 1547 1548 mutex_lock(&adev->grbm_idx_mutex); 1549 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1550 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1551 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1552 data = gfx_v9_0_get_rb_active_bitmap(adev); 1553 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1554 rb_bitmap_width_per_sh); 1555 } 1556 } 1557 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1558 mutex_unlock(&adev->grbm_idx_mutex); 1559 1560 adev->gfx.config.backend_enable_mask = active_rbs; 1561 adev->gfx.config.num_rbs = hweight32(active_rbs); 1562 } 1563 1564 #define DEFAULT_SH_MEM_BASES (0x6000) 1565 #define FIRST_COMPUTE_VMID (8) 1566 #define LAST_COMPUTE_VMID (16) 1567 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1568 { 1569 int i; 1570 uint32_t sh_mem_config; 1571 uint32_t sh_mem_bases; 1572 1573 /* 1574 * Configure apertures: 1575 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1576 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1577 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1578 */ 1579 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1580 1581 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1582 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1583 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1584 1585 mutex_lock(&adev->srbm_mutex); 1586 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1587 soc15_grbm_select(adev, 0, 0, 0, i); 1588 /* CP and shaders */ 1589 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1590 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1591 } 1592 soc15_grbm_select(adev, 0, 0, 0, 0); 1593 mutex_unlock(&adev->srbm_mutex); 1594 } 1595 1596 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 1597 { 1598 u32 tmp; 1599 int i; 1600 1601 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1602 1603 gfx_v9_0_tiling_mode_table_init(adev); 1604 1605 gfx_v9_0_setup_rb(adev); 1606 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1607 1608 /* XXX SH_MEM regs */ 1609 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1610 mutex_lock(&adev->srbm_mutex); 1611 for (i = 0; i < 16; i++) { 1612 soc15_grbm_select(adev, 0, 0, 0, i); 1613 /* CP and shaders */ 1614 tmp = 0; 1615 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 1616 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1617 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1618 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1619 } 1620 soc15_grbm_select(adev, 0, 0, 0, 0); 1621 1622 mutex_unlock(&adev->srbm_mutex); 1623 1624 gfx_v9_0_init_compute_vmid(adev); 1625 1626 mutex_lock(&adev->grbm_idx_mutex); 1627 /* 1628 * making sure that the following register writes will be broadcasted 1629 * to all the shaders 1630 */ 1631 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1632 1633 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1634 (adev->gfx.config.sc_prim_fifo_size_frontend << 1635 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1636 (adev->gfx.config.sc_prim_fifo_size_backend << 1637 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1638 (adev->gfx.config.sc_hiz_tile_fifo_size << 1639 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1640 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1641 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1642 mutex_unlock(&adev->grbm_idx_mutex); 1643 1644 } 1645 1646 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1647 { 1648 u32 i, j, k; 1649 u32 mask; 1650 1651 mutex_lock(&adev->grbm_idx_mutex); 1652 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1653 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1654 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1655 for (k = 0; k < adev->usec_timeout; k++) { 1656 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1657 break; 1658 udelay(1); 1659 } 1660 } 1661 } 1662 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1663 mutex_unlock(&adev->grbm_idx_mutex); 1664 1665 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1666 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1667 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1668 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1669 for (k = 0; k < adev->usec_timeout; k++) { 1670 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1671 break; 1672 udelay(1); 1673 } 1674 } 1675 1676 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1677 bool enable) 1678 { 1679 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1680 1681 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1682 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1683 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1684 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1685 1686 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1687 } 1688 1689 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 1690 { 1691 /* csib */ 1692 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 1693 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1694 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 1695 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1696 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 1697 adev->gfx.rlc.clear_state_size); 1698 } 1699 1700 static void gfx_v9_0_parse_ind_reg_list(int *register_list_format, 1701 int indirect_offset, 1702 int list_size, 1703 int *unique_indirect_regs, 1704 int *unique_indirect_reg_count, 1705 int max_indirect_reg_count, 1706 int *indirect_start_offsets, 1707 int *indirect_start_offsets_count, 1708 int max_indirect_start_offsets_count) 1709 { 1710 int idx; 1711 bool new_entry = true; 1712 1713 for (; indirect_offset < list_size; indirect_offset++) { 1714 1715 if (new_entry) { 1716 new_entry = false; 1717 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 1718 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 1719 BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count); 1720 } 1721 1722 if (register_list_format[indirect_offset] == 0xFFFFFFFF) { 1723 new_entry = true; 1724 continue; 1725 } 1726 1727 indirect_offset += 2; 1728 1729 /* look for the matching indice */ 1730 for (idx = 0; idx < *unique_indirect_reg_count; idx++) { 1731 if (unique_indirect_regs[idx] == 1732 register_list_format[indirect_offset]) 1733 break; 1734 } 1735 1736 if (idx >= *unique_indirect_reg_count) { 1737 unique_indirect_regs[*unique_indirect_reg_count] = 1738 register_list_format[indirect_offset]; 1739 idx = *unique_indirect_reg_count; 1740 *unique_indirect_reg_count = *unique_indirect_reg_count + 1; 1741 BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count); 1742 } 1743 1744 register_list_format[indirect_offset] = idx; 1745 } 1746 } 1747 1748 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) 1749 { 1750 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1751 int unique_indirect_reg_count = 0; 1752 1753 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1754 int indirect_start_offsets_count = 0; 1755 1756 int list_size = 0; 1757 int i = 0; 1758 u32 tmp = 0; 1759 1760 u32 *register_list_format = 1761 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 1762 if (!register_list_format) 1763 return -ENOMEM; 1764 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 1765 adev->gfx.rlc.reg_list_format_size_bytes); 1766 1767 /* setup unique_indirect_regs array and indirect_start_offsets array */ 1768 gfx_v9_0_parse_ind_reg_list(register_list_format, 1769 GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, 1770 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 1771 unique_indirect_regs, 1772 &unique_indirect_reg_count, 1773 sizeof(unique_indirect_regs)/sizeof(int), 1774 indirect_start_offsets, 1775 &indirect_start_offsets_count, 1776 sizeof(indirect_start_offsets)/sizeof(int)); 1777 1778 /* enable auto inc in case it is disabled */ 1779 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1780 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1781 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1782 1783 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 1784 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 1785 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 1786 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1787 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1788 adev->gfx.rlc.register_restore[i]); 1789 1790 /* load direct register */ 1791 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0); 1792 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1794 adev->gfx.rlc.register_restore[i]); 1795 1796 /* load indirect register */ 1797 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1798 adev->gfx.rlc.reg_list_format_start); 1799 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) 1800 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1801 register_list_format[i]); 1802 1803 /* set save/restore list size */ 1804 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 1805 list_size = list_size >> 1; 1806 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1807 adev->gfx.rlc.reg_restore_list_size); 1808 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 1809 1810 /* write the starting offsets to RLC scratch ram */ 1811 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1812 adev->gfx.rlc.starting_offsets_start); 1813 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++) 1814 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1815 indirect_start_offsets[i]); 1816 1817 /* load unique indirect regs*/ 1818 for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) { 1819 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i, 1820 unique_indirect_regs[i] & 0x3FFFF); 1821 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i, 1822 unique_indirect_regs[i] >> 20); 1823 } 1824 1825 kfree(register_list_format); 1826 return 0; 1827 } 1828 1829 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 1830 { 1831 u32 tmp = 0; 1832 1833 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1834 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1835 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1836 } 1837 1838 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 1839 bool enable) 1840 { 1841 uint32_t data = 0; 1842 uint32_t default_data = 0; 1843 1844 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 1845 if (enable == true) { 1846 /* enable GFXIP control over CGPG */ 1847 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1848 if(default_data != data) 1849 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1850 1851 /* update status */ 1852 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 1853 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 1854 if(default_data != data) 1855 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1856 } else { 1857 /* restore GFXIP control over GCPG */ 1858 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 1859 if(default_data != data) 1860 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 1861 } 1862 } 1863 1864 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 1865 { 1866 uint32_t data = 0; 1867 1868 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 1869 AMD_PG_SUPPORT_GFX_SMG | 1870 AMD_PG_SUPPORT_GFX_DMG)) { 1871 /* init IDLE_POLL_COUNT = 60 */ 1872 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 1873 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 1874 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 1875 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 1876 1877 /* init RLC PG Delay */ 1878 data = 0; 1879 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 1880 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 1881 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 1882 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 1883 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 1884 1885 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 1886 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 1887 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 1888 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 1889 1890 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 1891 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 1892 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 1893 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 1894 1895 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 1896 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 1897 1898 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 1899 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 1900 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 1901 1902 pwr_10_0_gfxip_control_over_cgpg(adev, true); 1903 } 1904 } 1905 1906 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 1907 bool enable) 1908 { 1909 uint32_t data = 0; 1910 uint32_t default_data = 0; 1911 1912 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1913 1914 if (enable == true) { 1915 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 1916 if (default_data != data) 1917 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1918 } else { 1919 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 1920 if(default_data != data) 1921 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1922 } 1923 } 1924 1925 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 1926 bool enable) 1927 { 1928 uint32_t data = 0; 1929 uint32_t default_data = 0; 1930 1931 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1932 1933 if (enable == true) { 1934 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 1935 if(default_data != data) 1936 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1937 } else { 1938 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 1939 if(default_data != data) 1940 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1941 } 1942 } 1943 1944 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 1945 bool enable) 1946 { 1947 uint32_t data = 0; 1948 uint32_t default_data = 0; 1949 1950 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1951 1952 if (enable == true) { 1953 data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK; 1954 if(default_data != data) 1955 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1956 } else { 1957 data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK; 1958 if(default_data != data) 1959 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1960 } 1961 } 1962 1963 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 1964 bool enable) 1965 { 1966 uint32_t data, default_data; 1967 1968 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1969 if (enable == true) 1970 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 1971 else 1972 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 1973 if(default_data != data) 1974 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1975 } 1976 1977 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 1978 bool enable) 1979 { 1980 uint32_t data, default_data; 1981 1982 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 1983 if (enable == true) 1984 data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; 1985 else 1986 data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK; 1987 if(default_data != data) 1988 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 1989 1990 if (!enable) 1991 /* read any GFX register to wake up GFX */ 1992 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 1993 } 1994 1995 void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 1996 bool enable) 1997 { 1998 uint32_t data, default_data; 1999 2000 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2001 if (enable == true) 2002 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2003 else 2004 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2005 if(default_data != data) 2006 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2007 } 2008 2009 void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2010 bool enable) 2011 { 2012 uint32_t data, default_data; 2013 2014 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2015 if (enable == true) 2016 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2017 else 2018 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2019 if(default_data != data) 2020 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2021 } 2022 2023 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2024 { 2025 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2026 AMD_PG_SUPPORT_GFX_SMG | 2027 AMD_PG_SUPPORT_GFX_DMG | 2028 AMD_PG_SUPPORT_CP | 2029 AMD_PG_SUPPORT_GDS | 2030 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2031 gfx_v9_0_init_csb(adev); 2032 gfx_v9_0_init_rlc_save_restore_list(adev); 2033 gfx_v9_0_enable_save_restore_machine(adev); 2034 2035 if (adev->asic_type == CHIP_RAVEN) { 2036 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2037 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2038 gfx_v9_0_init_gfx_power_gating(adev); 2039 2040 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 2041 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 2042 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 2043 } else { 2044 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 2045 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 2046 } 2047 2048 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 2049 gfx_v9_0_enable_cp_power_gating(adev, true); 2050 else 2051 gfx_v9_0_enable_cp_power_gating(adev, false); 2052 } 2053 } 2054 } 2055 2056 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2057 { 2058 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2059 2060 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2061 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 2062 2063 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2064 2065 gfx_v9_0_wait_for_rlc_serdes(adev); 2066 } 2067 2068 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2069 { 2070 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2071 udelay(50); 2072 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2073 udelay(50); 2074 } 2075 2076 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2077 { 2078 #ifdef AMDGPU_RLC_DEBUG_RETRY 2079 u32 rlc_ucode_ver; 2080 #endif 2081 2082 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2083 2084 /* carrizo do enable cp interrupt after cp inited */ 2085 if (!(adev->flags & AMD_IS_APU)) 2086 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2087 2088 udelay(50); 2089 2090 #ifdef AMDGPU_RLC_DEBUG_RETRY 2091 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2092 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2093 if(rlc_ucode_ver == 0x108) { 2094 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2095 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2096 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2097 * default is 0x9C4 to create a 100us interval */ 2098 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2099 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2100 * to disable the page fault retry interrupts, default is 2101 * 0x100 (256) */ 2102 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2103 } 2104 #endif 2105 } 2106 2107 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2108 { 2109 const struct rlc_firmware_header_v2_0 *hdr; 2110 const __le32 *fw_data; 2111 unsigned i, fw_size; 2112 2113 if (!adev->gfx.rlc_fw) 2114 return -EINVAL; 2115 2116 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2117 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2118 2119 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2120 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2121 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2122 2123 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2124 RLCG_UCODE_LOADING_START_ADDRESS); 2125 for (i = 0; i < fw_size; i++) 2126 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2127 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2128 2129 return 0; 2130 } 2131 2132 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2133 { 2134 int r; 2135 2136 if (amdgpu_sriov_vf(adev)) 2137 return 0; 2138 2139 gfx_v9_0_rlc_stop(adev); 2140 2141 /* disable CG */ 2142 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2143 2144 /* disable PG */ 2145 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 2146 2147 gfx_v9_0_rlc_reset(adev); 2148 2149 gfx_v9_0_init_pg(adev); 2150 2151 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2152 /* legacy rlc firmware loading */ 2153 r = gfx_v9_0_rlc_load_microcode(adev); 2154 if (r) 2155 return r; 2156 } 2157 2158 gfx_v9_0_rlc_start(adev); 2159 2160 return 0; 2161 } 2162 2163 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2164 { 2165 int i; 2166 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2167 2168 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2169 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2170 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2171 if (!enable) { 2172 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2173 adev->gfx.gfx_ring[i].ready = false; 2174 } 2175 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2176 udelay(50); 2177 } 2178 2179 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2180 { 2181 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2182 const struct gfx_firmware_header_v1_0 *ce_hdr; 2183 const struct gfx_firmware_header_v1_0 *me_hdr; 2184 const __le32 *fw_data; 2185 unsigned i, fw_size; 2186 2187 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2188 return -EINVAL; 2189 2190 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2191 adev->gfx.pfp_fw->data; 2192 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2193 adev->gfx.ce_fw->data; 2194 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2195 adev->gfx.me_fw->data; 2196 2197 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2198 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2199 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2200 2201 gfx_v9_0_cp_gfx_enable(adev, false); 2202 2203 /* PFP */ 2204 fw_data = (const __le32 *) 2205 (adev->gfx.pfp_fw->data + 2206 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2207 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2208 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2209 for (i = 0; i < fw_size; i++) 2210 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2211 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2212 2213 /* CE */ 2214 fw_data = (const __le32 *) 2215 (adev->gfx.ce_fw->data + 2216 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2217 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2218 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2219 for (i = 0; i < fw_size; i++) 2220 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2221 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2222 2223 /* ME */ 2224 fw_data = (const __le32 *) 2225 (adev->gfx.me_fw->data + 2226 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2227 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2228 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2229 for (i = 0; i < fw_size; i++) 2230 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2231 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2232 2233 return 0; 2234 } 2235 2236 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2237 { 2238 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2239 const struct cs_section_def *sect = NULL; 2240 const struct cs_extent_def *ext = NULL; 2241 int r, i; 2242 2243 /* init the CP */ 2244 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2245 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2246 2247 gfx_v9_0_cp_gfx_enable(adev, true); 2248 2249 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4); 2250 if (r) { 2251 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2252 return r; 2253 } 2254 2255 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2256 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2257 2258 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2259 amdgpu_ring_write(ring, 0x80000000); 2260 amdgpu_ring_write(ring, 0x80000000); 2261 2262 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2263 for (ext = sect->section; ext->extent != NULL; ++ext) { 2264 if (sect->id == SECT_CONTEXT) { 2265 amdgpu_ring_write(ring, 2266 PACKET3(PACKET3_SET_CONTEXT_REG, 2267 ext->reg_count)); 2268 amdgpu_ring_write(ring, 2269 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2270 for (i = 0; i < ext->reg_count; i++) 2271 amdgpu_ring_write(ring, ext->extent[i]); 2272 } 2273 } 2274 } 2275 2276 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2277 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2278 2279 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2280 amdgpu_ring_write(ring, 0); 2281 2282 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2283 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2284 amdgpu_ring_write(ring, 0x8000); 2285 amdgpu_ring_write(ring, 0x8000); 2286 2287 amdgpu_ring_commit(ring); 2288 2289 return 0; 2290 } 2291 2292 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2293 { 2294 struct amdgpu_ring *ring; 2295 u32 tmp; 2296 u32 rb_bufsz; 2297 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2298 2299 /* Set the write pointer delay */ 2300 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2301 2302 /* set the RB to use vmid 0 */ 2303 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2304 2305 /* Set ring buffer size */ 2306 ring = &adev->gfx.gfx_ring[0]; 2307 rb_bufsz = order_base_2(ring->ring_size / 8); 2308 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2309 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2310 #ifdef __BIG_ENDIAN 2311 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2312 #endif 2313 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2314 2315 /* Initialize the ring buffer's write pointers */ 2316 ring->wptr = 0; 2317 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2318 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2319 2320 /* set the wb address wether it's enabled or not */ 2321 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2322 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2323 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2324 2325 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2326 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2327 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2328 2329 mdelay(1); 2330 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2331 2332 rb_addr = ring->gpu_addr >> 8; 2333 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2334 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2335 2336 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2337 if (ring->use_doorbell) { 2338 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2339 DOORBELL_OFFSET, ring->doorbell_index); 2340 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2341 DOORBELL_EN, 1); 2342 } else { 2343 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2344 } 2345 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2346 2347 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2348 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2349 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2350 2351 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2352 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2353 2354 2355 /* start the ring */ 2356 gfx_v9_0_cp_gfx_start(adev); 2357 ring->ready = true; 2358 2359 return 0; 2360 } 2361 2362 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2363 { 2364 int i; 2365 2366 if (enable) { 2367 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2368 } else { 2369 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2370 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2371 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2372 adev->gfx.compute_ring[i].ready = false; 2373 adev->gfx.kiq.ring.ready = false; 2374 } 2375 udelay(50); 2376 } 2377 2378 static int gfx_v9_0_cp_compute_start(struct amdgpu_device *adev) 2379 { 2380 gfx_v9_0_cp_compute_enable(adev, true); 2381 2382 return 0; 2383 } 2384 2385 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2386 { 2387 const struct gfx_firmware_header_v1_0 *mec_hdr; 2388 const __le32 *fw_data; 2389 unsigned i; 2390 u32 tmp; 2391 2392 if (!adev->gfx.mec_fw) 2393 return -EINVAL; 2394 2395 gfx_v9_0_cp_compute_enable(adev, false); 2396 2397 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2398 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2399 2400 fw_data = (const __le32 *) 2401 (adev->gfx.mec_fw->data + 2402 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2403 tmp = 0; 2404 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2405 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2406 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2407 2408 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2409 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2410 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2411 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2412 2413 /* MEC1 */ 2414 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2415 mec_hdr->jt_offset); 2416 for (i = 0; i < mec_hdr->jt_size; i++) 2417 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2418 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2419 2420 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2421 adev->gfx.mec_fw_version); 2422 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2423 2424 return 0; 2425 } 2426 2427 static void gfx_v9_0_cp_compute_fini(struct amdgpu_device *adev) 2428 { 2429 int i, r; 2430 2431 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2432 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2433 2434 if (ring->mqd_obj) { 2435 r = amdgpu_bo_reserve(ring->mqd_obj, true); 2436 if (unlikely(r != 0)) 2437 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 2438 2439 amdgpu_bo_unpin(ring->mqd_obj); 2440 amdgpu_bo_unreserve(ring->mqd_obj); 2441 2442 amdgpu_bo_unref(&ring->mqd_obj); 2443 ring->mqd_obj = NULL; 2444 } 2445 } 2446 } 2447 2448 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring); 2449 2450 static int gfx_v9_0_cp_compute_resume(struct amdgpu_device *adev) 2451 { 2452 int i, r; 2453 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2454 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2455 if (gfx_v9_0_init_queue(ring)) 2456 dev_warn(adev->dev, "compute queue %d init failed!\n", i); 2457 } 2458 2459 r = gfx_v9_0_cp_compute_start(adev); 2460 if (r) 2461 return r; 2462 2463 return 0; 2464 } 2465 2466 /* KIQ functions */ 2467 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2468 { 2469 uint32_t tmp; 2470 struct amdgpu_device *adev = ring->adev; 2471 2472 /* tell RLC which is KIQ queue */ 2473 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2474 tmp &= 0xffffff00; 2475 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2476 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2477 tmp |= 0x80; 2478 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2479 } 2480 2481 static int gfx_v9_0_kiq_enable(struct amdgpu_ring *ring) 2482 { 2483 struct amdgpu_device *adev = ring->adev; 2484 uint32_t scratch, tmp = 0; 2485 int r, i; 2486 2487 r = amdgpu_gfx_scratch_get(adev, &scratch); 2488 if (r) { 2489 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2490 return r; 2491 } 2492 WREG32(scratch, 0xCAFEDEAD); 2493 2494 r = amdgpu_ring_alloc(ring, 8); 2495 if (r) { 2496 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2497 amdgpu_gfx_scratch_free(adev, scratch); 2498 return r; 2499 } 2500 amdgpu_ring_alloc(ring, 11); 2501 /* set resources */ 2502 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2503 amdgpu_ring_write(ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2504 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2505 amdgpu_ring_write(ring, 0x000000FF); /* queue mask lo */ 2506 amdgpu_ring_write(ring, 0); /* queue mask hi */ 2507 amdgpu_ring_write(ring, 0); /* gws mask lo */ 2508 amdgpu_ring_write(ring, 0); /* gws mask hi */ 2509 amdgpu_ring_write(ring, 0); /* oac mask */ 2510 amdgpu_ring_write(ring, 0); /* gds heap base:0, gds heap size:0 */ 2511 /* write to scratch for completion */ 2512 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2513 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2514 amdgpu_ring_write(ring, 0xDEADBEEF); 2515 amdgpu_ring_commit(ring); 2516 2517 for (i = 0; i < adev->usec_timeout; i++) { 2518 tmp = RREG32(scratch); 2519 if (tmp == 0xDEADBEEF) 2520 break; 2521 DRM_UDELAY(1); 2522 } 2523 if (i >= adev->usec_timeout) { 2524 DRM_ERROR("KIQ enable failed (scratch(0x%04X)=0x%08X)\n", 2525 scratch, tmp); 2526 r = -EINVAL; 2527 } 2528 amdgpu_gfx_scratch_free(adev, scratch); 2529 2530 return r; 2531 } 2532 2533 static int gfx_v9_0_map_queue_enable(struct amdgpu_ring *kiq_ring, 2534 struct amdgpu_ring *ring) 2535 { 2536 struct amdgpu_device *adev = kiq_ring->adev; 2537 uint64_t mqd_addr, wptr_addr; 2538 uint32_t scratch, tmp = 0; 2539 int r, i; 2540 2541 r = amdgpu_gfx_scratch_get(adev, &scratch); 2542 if (r) { 2543 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2544 return r; 2545 } 2546 WREG32(scratch, 0xCAFEDEAD); 2547 2548 r = amdgpu_ring_alloc(kiq_ring, 10); 2549 if (r) { 2550 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2551 amdgpu_gfx_scratch_free(adev, scratch); 2552 return r; 2553 } 2554 2555 mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2556 wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2557 2558 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2559 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2560 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2561 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2562 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2563 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2564 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2565 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2566 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2567 PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */ 2568 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2569 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2570 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2571 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2572 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2573 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2574 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2575 /* write to scratch for completion */ 2576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2577 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2578 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2579 amdgpu_ring_commit(kiq_ring); 2580 2581 for (i = 0; i < adev->usec_timeout; i++) { 2582 tmp = RREG32(scratch); 2583 if (tmp == 0xDEADBEEF) 2584 break; 2585 DRM_UDELAY(1); 2586 } 2587 if (i >= adev->usec_timeout) { 2588 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", 2589 scratch, tmp); 2590 r = -EINVAL; 2591 } 2592 amdgpu_gfx_scratch_free(adev, scratch); 2593 2594 return r; 2595 } 2596 2597 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2598 { 2599 struct amdgpu_device *adev = ring->adev; 2600 struct v9_mqd *mqd = ring->mqd_ptr; 2601 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2602 uint32_t tmp; 2603 2604 mqd->header = 0xC0310800; 2605 mqd->compute_pipelinestat_enable = 0x00000001; 2606 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2607 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2608 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2609 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2610 mqd->compute_misc_reserved = 0x00000003; 2611 2612 eop_base_addr = ring->eop_gpu_addr >> 8; 2613 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2614 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2615 2616 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2617 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2618 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2619 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 2620 2621 mqd->cp_hqd_eop_control = tmp; 2622 2623 /* enable doorbell? */ 2624 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2625 2626 if (ring->use_doorbell) { 2627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2628 DOORBELL_OFFSET, ring->doorbell_index); 2629 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2630 DOORBELL_EN, 1); 2631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2632 DOORBELL_SOURCE, 0); 2633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2634 DOORBELL_HIT, 0); 2635 } 2636 else 2637 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2638 DOORBELL_EN, 0); 2639 2640 mqd->cp_hqd_pq_doorbell_control = tmp; 2641 2642 /* disable the queue if it's active */ 2643 ring->wptr = 0; 2644 mqd->cp_hqd_dequeue_request = 0; 2645 mqd->cp_hqd_pq_rptr = 0; 2646 mqd->cp_hqd_pq_wptr_lo = 0; 2647 mqd->cp_hqd_pq_wptr_hi = 0; 2648 2649 /* set the pointer to the MQD */ 2650 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2651 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2652 2653 /* set MQD vmid to 0 */ 2654 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2655 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2656 mqd->cp_mqd_control = tmp; 2657 2658 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2659 hqd_gpu_addr = ring->gpu_addr >> 8; 2660 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2661 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2662 2663 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2664 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2665 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2666 (order_base_2(ring->ring_size / 4) - 1)); 2667 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2668 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2669 #ifdef __BIG_ENDIAN 2670 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2671 #endif 2672 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2673 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2674 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2675 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2676 mqd->cp_hqd_pq_control = tmp; 2677 2678 /* set the wb address whether it's enabled or not */ 2679 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2680 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2681 mqd->cp_hqd_pq_rptr_report_addr_hi = 2682 upper_32_bits(wb_gpu_addr) & 0xffff; 2683 2684 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2685 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2686 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2687 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2688 2689 tmp = 0; 2690 /* enable the doorbell if requested */ 2691 if (ring->use_doorbell) { 2692 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2693 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2694 DOORBELL_OFFSET, ring->doorbell_index); 2695 2696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2697 DOORBELL_EN, 1); 2698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2699 DOORBELL_SOURCE, 0); 2700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2701 DOORBELL_HIT, 0); 2702 } 2703 2704 mqd->cp_hqd_pq_doorbell_control = tmp; 2705 2706 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2707 ring->wptr = 0; 2708 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2709 2710 /* set the vmid for the queue */ 2711 mqd->cp_hqd_vmid = 0; 2712 2713 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2714 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2715 mqd->cp_hqd_persistent_state = tmp; 2716 2717 /* set MIN_IB_AVAIL_SIZE */ 2718 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2719 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2720 mqd->cp_hqd_ib_control = tmp; 2721 2722 /* activate the queue */ 2723 mqd->cp_hqd_active = 1; 2724 2725 return 0; 2726 } 2727 2728 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2729 { 2730 struct amdgpu_device *adev = ring->adev; 2731 struct v9_mqd *mqd = ring->mqd_ptr; 2732 int j; 2733 2734 /* disable wptr polling */ 2735 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2736 2737 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2738 mqd->cp_hqd_eop_base_addr_lo); 2739 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2740 mqd->cp_hqd_eop_base_addr_hi); 2741 2742 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2743 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2744 mqd->cp_hqd_eop_control); 2745 2746 /* enable doorbell? */ 2747 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2748 mqd->cp_hqd_pq_doorbell_control); 2749 2750 /* disable the queue if it's active */ 2751 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2752 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2753 for (j = 0; j < adev->usec_timeout; j++) { 2754 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2755 break; 2756 udelay(1); 2757 } 2758 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2759 mqd->cp_hqd_dequeue_request); 2760 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 2761 mqd->cp_hqd_pq_rptr); 2762 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2763 mqd->cp_hqd_pq_wptr_lo); 2764 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2765 mqd->cp_hqd_pq_wptr_hi); 2766 } 2767 2768 /* set the pointer to the MQD */ 2769 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 2770 mqd->cp_mqd_base_addr_lo); 2771 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 2772 mqd->cp_mqd_base_addr_hi); 2773 2774 /* set MQD vmid to 0 */ 2775 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 2776 mqd->cp_mqd_control); 2777 2778 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2779 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 2780 mqd->cp_hqd_pq_base_lo); 2781 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 2782 mqd->cp_hqd_pq_base_hi); 2783 2784 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2785 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 2786 mqd->cp_hqd_pq_control); 2787 2788 /* set the wb address whether it's enabled or not */ 2789 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2790 mqd->cp_hqd_pq_rptr_report_addr_lo); 2791 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2792 mqd->cp_hqd_pq_rptr_report_addr_hi); 2793 2794 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2795 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 2796 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2797 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2798 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2799 2800 /* enable the doorbell if requested */ 2801 if (ring->use_doorbell) { 2802 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 2803 (AMDGPU_DOORBELL64_KIQ *2) << 2); 2804 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 2805 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); 2806 } 2807 2808 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2809 mqd->cp_hqd_pq_doorbell_control); 2810 2811 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2812 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2813 mqd->cp_hqd_pq_wptr_lo); 2814 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2815 mqd->cp_hqd_pq_wptr_hi); 2816 2817 /* set the vmid for the queue */ 2818 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 2819 2820 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 2821 mqd->cp_hqd_persistent_state); 2822 2823 /* activate the queue */ 2824 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 2825 mqd->cp_hqd_active); 2826 2827 if (ring->use_doorbell) 2828 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2829 2830 return 0; 2831 } 2832 2833 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 2834 { 2835 struct amdgpu_device *adev = ring->adev; 2836 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 2837 struct v9_mqd *mqd = ring->mqd_ptr; 2838 bool is_kiq = (ring->funcs->type == AMDGPU_RING_TYPE_KIQ); 2839 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2840 int r; 2841 2842 if (is_kiq) { 2843 gfx_v9_0_kiq_setting(&kiq->ring); 2844 } else { 2845 mqd_idx = ring - &adev->gfx.compute_ring[0]; 2846 } 2847 2848 if (!adev->gfx.in_reset) { 2849 memset((void *)mqd, 0, sizeof(*mqd)); 2850 mutex_lock(&adev->srbm_mutex); 2851 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2852 gfx_v9_0_mqd_init(ring); 2853 if (is_kiq) 2854 gfx_v9_0_kiq_init_register(ring); 2855 soc15_grbm_select(adev, 0, 0, 0, 0); 2856 mutex_unlock(&adev->srbm_mutex); 2857 2858 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2859 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2860 } else { /* for GPU_RESET case */ 2861 /* reset MQD to a clean status */ 2862 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2863 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2864 2865 /* reset ring buffer */ 2866 ring->wptr = 0; 2867 amdgpu_ring_clear_ring(ring); 2868 2869 if (is_kiq) { 2870 mutex_lock(&adev->srbm_mutex); 2871 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2872 gfx_v9_0_kiq_init_register(ring); 2873 soc15_grbm_select(adev, 0, 0, 0, 0); 2874 mutex_unlock(&adev->srbm_mutex); 2875 } 2876 } 2877 2878 if (is_kiq) 2879 r = gfx_v9_0_kiq_enable(ring); 2880 else 2881 r = gfx_v9_0_map_queue_enable(&kiq->ring, ring); 2882 2883 return r; 2884 } 2885 2886 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 2887 { 2888 struct amdgpu_ring *ring = NULL; 2889 int r = 0, i; 2890 2891 gfx_v9_0_cp_compute_enable(adev, true); 2892 2893 ring = &adev->gfx.kiq.ring; 2894 2895 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2896 if (unlikely(r != 0)) 2897 goto done; 2898 2899 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2900 if (!r) { 2901 r = gfx_v9_0_kiq_init_queue(ring); 2902 amdgpu_bo_kunmap(ring->mqd_obj); 2903 ring->mqd_ptr = NULL; 2904 } 2905 amdgpu_bo_unreserve(ring->mqd_obj); 2906 if (r) 2907 goto done; 2908 2909 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2910 ring = &adev->gfx.compute_ring[i]; 2911 2912 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2913 if (unlikely(r != 0)) 2914 goto done; 2915 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2916 if (!r) { 2917 r = gfx_v9_0_kiq_init_queue(ring); 2918 amdgpu_bo_kunmap(ring->mqd_obj); 2919 ring->mqd_ptr = NULL; 2920 } 2921 amdgpu_bo_unreserve(ring->mqd_obj); 2922 if (r) 2923 goto done; 2924 } 2925 2926 done: 2927 return r; 2928 } 2929 2930 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 2931 { 2932 int r,i; 2933 struct amdgpu_ring *ring; 2934 2935 if (!(adev->flags & AMD_IS_APU)) 2936 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2937 2938 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2939 /* legacy firmware loading */ 2940 r = gfx_v9_0_cp_gfx_load_microcode(adev); 2941 if (r) 2942 return r; 2943 2944 r = gfx_v9_0_cp_compute_load_microcode(adev); 2945 if (r) 2946 return r; 2947 } 2948 2949 r = gfx_v9_0_cp_gfx_resume(adev); 2950 if (r) 2951 return r; 2952 2953 if (amdgpu_sriov_vf(adev)) 2954 r = gfx_v9_0_kiq_resume(adev); 2955 else 2956 r = gfx_v9_0_cp_compute_resume(adev); 2957 if (r) 2958 return r; 2959 2960 ring = &adev->gfx.gfx_ring[0]; 2961 r = amdgpu_ring_test_ring(ring); 2962 if (r) { 2963 ring->ready = false; 2964 return r; 2965 } 2966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2967 ring = &adev->gfx.compute_ring[i]; 2968 2969 ring->ready = true; 2970 r = amdgpu_ring_test_ring(ring); 2971 if (r) 2972 ring->ready = false; 2973 } 2974 2975 if (amdgpu_sriov_vf(adev)) { 2976 ring = &adev->gfx.kiq.ring; 2977 ring->ready = true; 2978 r = amdgpu_ring_test_ring(ring); 2979 if (r) 2980 ring->ready = false; 2981 } 2982 2983 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2984 2985 return 0; 2986 } 2987 2988 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 2989 { 2990 gfx_v9_0_cp_gfx_enable(adev, enable); 2991 gfx_v9_0_cp_compute_enable(adev, enable); 2992 } 2993 2994 static int gfx_v9_0_hw_init(void *handle) 2995 { 2996 int r; 2997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2998 2999 gfx_v9_0_init_golden_registers(adev); 3000 3001 gfx_v9_0_gpu_init(adev); 3002 3003 r = gfx_v9_0_rlc_resume(adev); 3004 if (r) 3005 return r; 3006 3007 r = gfx_v9_0_cp_resume(adev); 3008 if (r) 3009 return r; 3010 3011 r = gfx_v9_0_ngg_en(adev); 3012 if (r) 3013 return r; 3014 3015 return r; 3016 } 3017 3018 static int gfx_v9_0_hw_fini(void *handle) 3019 { 3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3021 3022 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3023 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3024 if (amdgpu_sriov_vf(adev)) { 3025 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3026 return 0; 3027 } 3028 gfx_v9_0_cp_enable(adev, false); 3029 gfx_v9_0_rlc_stop(adev); 3030 gfx_v9_0_cp_compute_fini(adev); 3031 3032 return 0; 3033 } 3034 3035 static int gfx_v9_0_suspend(void *handle) 3036 { 3037 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3038 3039 return gfx_v9_0_hw_fini(adev); 3040 } 3041 3042 static int gfx_v9_0_resume(void *handle) 3043 { 3044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3045 3046 return gfx_v9_0_hw_init(adev); 3047 } 3048 3049 static bool gfx_v9_0_is_idle(void *handle) 3050 { 3051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3052 3053 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3054 GRBM_STATUS, GUI_ACTIVE)) 3055 return false; 3056 else 3057 return true; 3058 } 3059 3060 static int gfx_v9_0_wait_for_idle(void *handle) 3061 { 3062 unsigned i; 3063 u32 tmp; 3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3065 3066 for (i = 0; i < adev->usec_timeout; i++) { 3067 /* read MC_STATUS */ 3068 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3069 GRBM_STATUS__GUI_ACTIVE_MASK; 3070 3071 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3072 return 0; 3073 udelay(1); 3074 } 3075 return -ETIMEDOUT; 3076 } 3077 3078 static int gfx_v9_0_soft_reset(void *handle) 3079 { 3080 u32 grbm_soft_reset = 0; 3081 u32 tmp; 3082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3083 3084 /* GRBM_STATUS */ 3085 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3086 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3087 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3088 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3089 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3090 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3091 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3092 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3093 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3094 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3095 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3096 } 3097 3098 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3099 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3100 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3101 } 3102 3103 /* GRBM_STATUS2 */ 3104 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3105 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3106 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3107 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3108 3109 3110 if (grbm_soft_reset) { 3111 /* stop the rlc */ 3112 gfx_v9_0_rlc_stop(adev); 3113 3114 /* Disable GFX parsing/prefetching */ 3115 gfx_v9_0_cp_gfx_enable(adev, false); 3116 3117 /* Disable MEC parsing/prefetching */ 3118 gfx_v9_0_cp_compute_enable(adev, false); 3119 3120 if (grbm_soft_reset) { 3121 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3122 tmp |= grbm_soft_reset; 3123 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3124 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3125 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3126 3127 udelay(50); 3128 3129 tmp &= ~grbm_soft_reset; 3130 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3131 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3132 } 3133 3134 /* Wait a little for things to settle down */ 3135 udelay(50); 3136 } 3137 return 0; 3138 } 3139 3140 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3141 { 3142 uint64_t clock; 3143 3144 mutex_lock(&adev->gfx.gpu_clock_mutex); 3145 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3146 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3147 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3148 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3149 return clock; 3150 } 3151 3152 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3153 uint32_t vmid, 3154 uint32_t gds_base, uint32_t gds_size, 3155 uint32_t gws_base, uint32_t gws_size, 3156 uint32_t oa_base, uint32_t oa_size) 3157 { 3158 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 3159 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 3160 3161 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 3162 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 3163 3164 oa_base = oa_base >> AMDGPU_OA_SHIFT; 3165 oa_size = oa_size >> AMDGPU_OA_SHIFT; 3166 3167 /* GDS Base */ 3168 gfx_v9_0_write_data_to_reg(ring, 0, false, 3169 amdgpu_gds_reg_offset[vmid].mem_base, 3170 gds_base); 3171 3172 /* GDS Size */ 3173 gfx_v9_0_write_data_to_reg(ring, 0, false, 3174 amdgpu_gds_reg_offset[vmid].mem_size, 3175 gds_size); 3176 3177 /* GWS */ 3178 gfx_v9_0_write_data_to_reg(ring, 0, false, 3179 amdgpu_gds_reg_offset[vmid].gws, 3180 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3181 3182 /* OA */ 3183 gfx_v9_0_write_data_to_reg(ring, 0, false, 3184 amdgpu_gds_reg_offset[vmid].oa, 3185 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3186 } 3187 3188 static int gfx_v9_0_early_init(void *handle) 3189 { 3190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3191 3192 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3193 adev->gfx.num_compute_rings = GFX9_NUM_COMPUTE_RINGS; 3194 gfx_v9_0_set_ring_funcs(adev); 3195 gfx_v9_0_set_irq_funcs(adev); 3196 gfx_v9_0_set_gds_init(adev); 3197 gfx_v9_0_set_rlc_funcs(adev); 3198 3199 return 0; 3200 } 3201 3202 static int gfx_v9_0_late_init(void *handle) 3203 { 3204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3205 int r; 3206 3207 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3208 if (r) 3209 return r; 3210 3211 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3212 if (r) 3213 return r; 3214 3215 return 0; 3216 } 3217 3218 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3219 { 3220 uint32_t rlc_setting, data; 3221 unsigned i; 3222 3223 if (adev->gfx.rlc.in_safe_mode) 3224 return; 3225 3226 /* if RLC is not enabled, do nothing */ 3227 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3228 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3229 return; 3230 3231 if (adev->cg_flags & 3232 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | 3233 AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3234 data = RLC_SAFE_MODE__CMD_MASK; 3235 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3236 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3237 3238 /* wait for RLC_SAFE_MODE */ 3239 for (i = 0; i < adev->usec_timeout; i++) { 3240 if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3241 break; 3242 udelay(1); 3243 } 3244 adev->gfx.rlc.in_safe_mode = true; 3245 } 3246 } 3247 3248 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3249 { 3250 uint32_t rlc_setting, data; 3251 3252 if (!adev->gfx.rlc.in_safe_mode) 3253 return; 3254 3255 /* if RLC is not enabled, do nothing */ 3256 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3257 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3258 return; 3259 3260 if (adev->cg_flags & 3261 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 3262 /* 3263 * Try to exit safe mode only if it is already in safe 3264 * mode. 3265 */ 3266 data = RLC_SAFE_MODE__CMD_MASK; 3267 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3268 adev->gfx.rlc.in_safe_mode = false; 3269 } 3270 } 3271 3272 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3273 bool enable) 3274 { 3275 /* TODO: double check if we need to perform under safe mdoe */ 3276 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3277 3278 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3279 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3280 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3281 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3282 } else { 3283 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3284 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3285 } 3286 3287 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3288 } 3289 3290 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3291 bool enable) 3292 { 3293 /* TODO: double check if we need to perform under safe mode */ 3294 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3295 3296 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3297 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3298 else 3299 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3300 3301 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3302 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3303 else 3304 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3305 3306 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3307 } 3308 3309 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3310 bool enable) 3311 { 3312 uint32_t data, def; 3313 3314 /* It is disabled by HW by default */ 3315 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3316 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3317 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3318 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3319 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3320 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3321 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3322 3323 /* only for Vega10 & Raven1 */ 3324 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3325 3326 if (def != data) 3327 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3328 3329 /* MGLS is a global flag to control all MGLS in GFX */ 3330 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3331 /* 2 - RLC memory Light sleep */ 3332 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3333 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3334 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3335 if (def != data) 3336 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3337 } 3338 /* 3 - CP memory Light sleep */ 3339 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3340 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3341 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3342 if (def != data) 3343 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3344 } 3345 } 3346 } else { 3347 /* 1 - MGCG_OVERRIDE */ 3348 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3349 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK | 3350 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3351 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3352 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3353 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3354 if (def != data) 3355 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3356 3357 /* 2 - disable MGLS in RLC */ 3358 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3359 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3360 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3361 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3362 } 3363 3364 /* 3 - disable MGLS in CP */ 3365 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3366 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3367 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3368 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3369 } 3370 } 3371 } 3372 3373 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3374 bool enable) 3375 { 3376 uint32_t data, def; 3377 3378 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3379 3380 /* Enable 3D CGCG/CGLS */ 3381 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3382 /* write cmd to clear cgcg/cgls ov */ 3383 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3384 /* unset CGCG override */ 3385 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3386 /* update CGCG and CGLS override bits */ 3387 if (def != data) 3388 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3389 /* enable 3Dcgcg FSM(0x0020003f) */ 3390 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3391 data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3392 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3393 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3394 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3395 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3396 if (def != data) 3397 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3398 3399 /* set IDLE_POLL_COUNT(0x00900100) */ 3400 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3401 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3402 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3403 if (def != data) 3404 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3405 } else { 3406 /* Disable CGCG/CGLS */ 3407 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3408 /* disable cgcg, cgls should be disabled */ 3409 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3410 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3411 /* disable cgcg and cgls in FSM */ 3412 if (def != data) 3413 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3414 } 3415 3416 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3417 } 3418 3419 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3420 bool enable) 3421 { 3422 uint32_t def, data; 3423 3424 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3425 3426 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3427 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3428 /* unset CGCG override */ 3429 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3430 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3431 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3432 else 3433 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3434 /* update CGCG and CGLS override bits */ 3435 if (def != data) 3436 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3437 3438 /* enable cgcg FSM(0x0020003F) */ 3439 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3440 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3441 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3442 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3443 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3444 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3445 if (def != data) 3446 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3447 3448 /* set IDLE_POLL_COUNT(0x00900100) */ 3449 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3450 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3451 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3452 if (def != data) 3453 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3454 } else { 3455 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3456 /* reset CGCG/CGLS bits */ 3457 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3458 /* disable cgcg and cgls in FSM */ 3459 if (def != data) 3460 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3461 } 3462 3463 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3464 } 3465 3466 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3467 bool enable) 3468 { 3469 if (enable) { 3470 /* CGCG/CGLS should be enabled after MGCG/MGLS 3471 * === MGCG + MGLS === 3472 */ 3473 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3474 /* === CGCG /CGLS for GFX 3D Only === */ 3475 gfx_v9_0_update_3d_clock_gating(adev, enable); 3476 /* === CGCG + CGLS === */ 3477 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3478 } else { 3479 /* CGCG/CGLS should be disabled before MGCG/MGLS 3480 * === CGCG + CGLS === 3481 */ 3482 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3483 /* === CGCG /CGLS for GFX 3D Only === */ 3484 gfx_v9_0_update_3d_clock_gating(adev, enable); 3485 /* === MGCG + MGLS === */ 3486 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3487 } 3488 return 0; 3489 } 3490 3491 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3492 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3493 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 3494 }; 3495 3496 static int gfx_v9_0_set_powergating_state(void *handle, 3497 enum amd_powergating_state state) 3498 { 3499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3500 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3501 3502 switch (adev->asic_type) { 3503 case CHIP_RAVEN: 3504 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3505 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3506 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3507 } else { 3508 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3509 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3510 } 3511 3512 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3513 gfx_v9_0_enable_cp_power_gating(adev, true); 3514 else 3515 gfx_v9_0_enable_cp_power_gating(adev, false); 3516 3517 /* update gfx cgpg state */ 3518 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3519 3520 /* update mgcg state */ 3521 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3522 break; 3523 default: 3524 break; 3525 } 3526 3527 return 0; 3528 } 3529 3530 static int gfx_v9_0_set_clockgating_state(void *handle, 3531 enum amd_clockgating_state state) 3532 { 3533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3534 3535 if (amdgpu_sriov_vf(adev)) 3536 return 0; 3537 3538 switch (adev->asic_type) { 3539 case CHIP_VEGA10: 3540 case CHIP_RAVEN: 3541 gfx_v9_0_update_gfx_clock_gating(adev, 3542 state == AMD_CG_STATE_GATE ? true : false); 3543 break; 3544 default: 3545 break; 3546 } 3547 return 0; 3548 } 3549 3550 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3551 { 3552 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3553 int data; 3554 3555 if (amdgpu_sriov_vf(adev)) 3556 *flags = 0; 3557 3558 /* AMD_CG_SUPPORT_GFX_MGCG */ 3559 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3560 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3561 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3562 3563 /* AMD_CG_SUPPORT_GFX_CGCG */ 3564 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3565 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3566 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3567 3568 /* AMD_CG_SUPPORT_GFX_CGLS */ 3569 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3570 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3571 3572 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 3573 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3574 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 3575 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 3576 3577 /* AMD_CG_SUPPORT_GFX_CP_LS */ 3578 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3579 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 3580 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 3581 3582 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3583 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3584 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3585 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3586 3587 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3588 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3589 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3590 } 3591 3592 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3593 { 3594 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 3595 } 3596 3597 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3598 { 3599 struct amdgpu_device *adev = ring->adev; 3600 u64 wptr; 3601 3602 /* XXX check if swapping is necessary on BE */ 3603 if (ring->use_doorbell) { 3604 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3605 } else { 3606 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 3607 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 3608 } 3609 3610 return wptr; 3611 } 3612 3613 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3614 { 3615 struct amdgpu_device *adev = ring->adev; 3616 3617 if (ring->use_doorbell) { 3618 /* XXX check if swapping is necessary on BE */ 3619 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3620 WDOORBELL64(ring->doorbell_index, ring->wptr); 3621 } else { 3622 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3623 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3624 } 3625 } 3626 3627 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3628 { 3629 u32 ref_and_mask, reg_mem_engine; 3630 struct nbio_hdp_flush_reg *nbio_hf_reg; 3631 3632 if (ring->adev->asic_type == CHIP_VEGA10) 3633 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 3634 3635 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3636 switch (ring->me) { 3637 case 1: 3638 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3639 break; 3640 case 2: 3641 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3642 break; 3643 default: 3644 return; 3645 } 3646 reg_mem_engine = 0; 3647 } else { 3648 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3649 reg_mem_engine = 1; /* pfp */ 3650 } 3651 3652 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3653 nbio_hf_reg->hdp_flush_req_offset, 3654 nbio_hf_reg->hdp_flush_done_offset, 3655 ref_and_mask, ref_and_mask, 0x20); 3656 } 3657 3658 static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 3659 { 3660 gfx_v9_0_write_data_to_reg(ring, 0, true, 3661 SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1); 3662 } 3663 3664 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3665 struct amdgpu_ib *ib, 3666 unsigned vm_id, bool ctx_switch) 3667 { 3668 u32 header, control = 0; 3669 3670 if (ib->flags & AMDGPU_IB_FLAG_CE) 3671 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3672 else 3673 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3674 3675 control |= ib->length_dw | (vm_id << 24); 3676 3677 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3678 control |= INDIRECT_BUFFER_PRE_ENB(1); 3679 3680 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 3681 gfx_v9_0_ring_emit_de_meta(ring); 3682 } 3683 3684 amdgpu_ring_write(ring, header); 3685 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3686 amdgpu_ring_write(ring, 3687 #ifdef __BIG_ENDIAN 3688 (2 << 0) | 3689 #endif 3690 lower_32_bits(ib->gpu_addr)); 3691 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3692 amdgpu_ring_write(ring, control); 3693 } 3694 3695 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3696 struct amdgpu_ib *ib, 3697 unsigned vm_id, bool ctx_switch) 3698 { 3699 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 3700 3701 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3702 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3703 amdgpu_ring_write(ring, 3704 #ifdef __BIG_ENDIAN 3705 (2 << 0) | 3706 #endif 3707 lower_32_bits(ib->gpu_addr)); 3708 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3709 amdgpu_ring_write(ring, control); 3710 } 3711 3712 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3713 u64 seq, unsigned flags) 3714 { 3715 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3716 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3717 3718 /* RELEASE_MEM - flush caches, send int */ 3719 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3720 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3721 EOP_TC_ACTION_EN | 3722 EOP_TC_WB_ACTION_EN | 3723 EOP_TC_MD_ACTION_EN | 3724 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3725 EVENT_INDEX(5))); 3726 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3727 3728 /* 3729 * the address should be Qword aligned if 64bit write, Dword 3730 * aligned if only send 32bit data low (discard data high) 3731 */ 3732 if (write64bit) 3733 BUG_ON(addr & 0x7); 3734 else 3735 BUG_ON(addr & 0x3); 3736 amdgpu_ring_write(ring, lower_32_bits(addr)); 3737 amdgpu_ring_write(ring, upper_32_bits(addr)); 3738 amdgpu_ring_write(ring, lower_32_bits(seq)); 3739 amdgpu_ring_write(ring, upper_32_bits(seq)); 3740 amdgpu_ring_write(ring, 0); 3741 } 3742 3743 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3744 { 3745 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3746 uint32_t seq = ring->fence_drv.sync_seq; 3747 uint64_t addr = ring->fence_drv.gpu_addr; 3748 3749 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 3750 lower_32_bits(addr), upper_32_bits(addr), 3751 seq, 0xffffffff, 4); 3752 } 3753 3754 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3755 unsigned vm_id, uint64_t pd_addr) 3756 { 3757 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 3758 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3759 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id); 3760 unsigned eng = ring->vm_inv_eng; 3761 3762 pd_addr = pd_addr | 0x1; /* valid bit */ 3763 /* now only use physical base address of PDE and valid */ 3764 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 3765 3766 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3767 hub->ctx0_ptb_addr_lo32 + (2 * vm_id), 3768 lower_32_bits(pd_addr)); 3769 3770 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3771 hub->ctx0_ptb_addr_hi32 + (2 * vm_id), 3772 upper_32_bits(pd_addr)); 3773 3774 gfx_v9_0_write_data_to_reg(ring, usepfp, true, 3775 hub->vm_inv_eng0_req + eng, req); 3776 3777 /* wait for the invalidate to complete */ 3778 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack + 3779 eng, 0, 1 << vm_id, 1 << vm_id, 0x20); 3780 3781 /* compute doesn't have PFP */ 3782 if (usepfp) { 3783 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3784 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3785 amdgpu_ring_write(ring, 0x0); 3786 } 3787 } 3788 3789 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3790 { 3791 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3792 } 3793 3794 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3795 { 3796 u64 wptr; 3797 3798 /* XXX check if swapping is necessary on BE */ 3799 if (ring->use_doorbell) 3800 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3801 else 3802 BUG(); 3803 return wptr; 3804 } 3805 3806 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 3807 { 3808 struct amdgpu_device *adev = ring->adev; 3809 3810 /* XXX check if swapping is necessary on BE */ 3811 if (ring->use_doorbell) { 3812 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3813 WDOORBELL64(ring->doorbell_index, ring->wptr); 3814 } else{ 3815 BUG(); /* only DOORBELL method supported on gfx9 now */ 3816 } 3817 } 3818 3819 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3820 u64 seq, unsigned int flags) 3821 { 3822 /* we only allocate 32bit for each seq wb address */ 3823 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 3824 3825 /* write fence seq to the "addr" */ 3826 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3827 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3828 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3829 amdgpu_ring_write(ring, lower_32_bits(addr)); 3830 amdgpu_ring_write(ring, upper_32_bits(addr)); 3831 amdgpu_ring_write(ring, lower_32_bits(seq)); 3832 3833 if (flags & AMDGPU_FENCE_FLAG_INT) { 3834 /* set register to trigger INT */ 3835 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3836 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3837 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3838 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 3839 amdgpu_ring_write(ring, 0); 3840 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3841 } 3842 } 3843 3844 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 3845 { 3846 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3847 amdgpu_ring_write(ring, 0); 3848 } 3849 3850 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 3851 { 3852 static struct v9_ce_ib_state ce_payload = {0}; 3853 uint64_t csa_addr; 3854 int cnt; 3855 3856 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 3857 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3858 3859 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3860 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 3861 WRITE_DATA_DST_SEL(8) | 3862 WR_CONFIRM) | 3863 WRITE_DATA_CACHE_POLICY(0)); 3864 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3865 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 3866 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 3867 } 3868 3869 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 3870 { 3871 static struct v9_de_ib_state de_payload = {0}; 3872 uint64_t csa_addr, gds_addr; 3873 int cnt; 3874 3875 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 3876 gds_addr = csa_addr + 4096; 3877 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 3878 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 3879 3880 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 3881 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 3882 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 3883 WRITE_DATA_DST_SEL(8) | 3884 WR_CONFIRM) | 3885 WRITE_DATA_CACHE_POLICY(0)); 3886 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3887 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 3888 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 3889 } 3890 3891 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3892 { 3893 uint32_t dw2 = 0; 3894 3895 if (amdgpu_sriov_vf(ring->adev)) 3896 gfx_v9_0_ring_emit_ce_meta(ring); 3897 3898 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 3899 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 3900 /* set load_global_config & load_global_uconfig */ 3901 dw2 |= 0x8001; 3902 /* set load_cs_sh_regs */ 3903 dw2 |= 0x01000000; 3904 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 3905 dw2 |= 0x10002; 3906 3907 /* set load_ce_ram if preamble presented */ 3908 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 3909 dw2 |= 0x10000000; 3910 } else { 3911 /* still load_ce_ram if this is the first time preamble presented 3912 * although there is no context switch happens. 3913 */ 3914 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 3915 dw2 |= 0x10000000; 3916 } 3917 3918 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3919 amdgpu_ring_write(ring, dw2); 3920 amdgpu_ring_write(ring, 0); 3921 } 3922 3923 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 3924 { 3925 unsigned ret; 3926 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 3927 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 3928 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 3929 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 3930 ret = ring->wptr & ring->buf_mask; 3931 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 3932 return ret; 3933 } 3934 3935 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 3936 { 3937 unsigned cur; 3938 BUG_ON(offset > ring->buf_mask); 3939 BUG_ON(ring->ring[offset] != 0x55aa55aa); 3940 3941 cur = (ring->wptr & ring->buf_mask) - 1; 3942 if (likely(cur > offset)) 3943 ring->ring[offset] = cur - offset; 3944 else 3945 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 3946 } 3947 3948 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 3949 { 3950 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 3951 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 3952 } 3953 3954 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 3955 { 3956 struct amdgpu_device *adev = ring->adev; 3957 3958 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3959 amdgpu_ring_write(ring, 0 | /* src: register*/ 3960 (5 << 8) | /* dst: memory */ 3961 (1 << 20)); /* write confirm */ 3962 amdgpu_ring_write(ring, reg); 3963 amdgpu_ring_write(ring, 0); 3964 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3965 adev->virt.reg_val_offs * 4)); 3966 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3967 adev->virt.reg_val_offs * 4)); 3968 } 3969 3970 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3971 uint32_t val) 3972 { 3973 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3974 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ 3975 amdgpu_ring_write(ring, reg); 3976 amdgpu_ring_write(ring, 0); 3977 amdgpu_ring_write(ring, val); 3978 } 3979 3980 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3981 enum amdgpu_interrupt_state state) 3982 { 3983 switch (state) { 3984 case AMDGPU_IRQ_STATE_DISABLE: 3985 case AMDGPU_IRQ_STATE_ENABLE: 3986 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 3987 TIME_STAMP_INT_ENABLE, 3988 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3989 break; 3990 default: 3991 break; 3992 } 3993 } 3994 3995 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3996 int me, int pipe, 3997 enum amdgpu_interrupt_state state) 3998 { 3999 u32 mec_int_cntl, mec_int_cntl_reg; 4000 4001 /* 4002 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4003 * handles the setting of interrupts for this specific pipe. All other 4004 * pipes' interrupts are set by amdkfd. 4005 */ 4006 4007 if (me == 1) { 4008 switch (pipe) { 4009 case 0: 4010 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4011 break; 4012 default: 4013 DRM_DEBUG("invalid pipe %d\n", pipe); 4014 return; 4015 } 4016 } else { 4017 DRM_DEBUG("invalid me %d\n", me); 4018 return; 4019 } 4020 4021 switch (state) { 4022 case AMDGPU_IRQ_STATE_DISABLE: 4023 mec_int_cntl = RREG32(mec_int_cntl_reg); 4024 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4025 TIME_STAMP_INT_ENABLE, 0); 4026 WREG32(mec_int_cntl_reg, mec_int_cntl); 4027 break; 4028 case AMDGPU_IRQ_STATE_ENABLE: 4029 mec_int_cntl = RREG32(mec_int_cntl_reg); 4030 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4031 TIME_STAMP_INT_ENABLE, 1); 4032 WREG32(mec_int_cntl_reg, mec_int_cntl); 4033 break; 4034 default: 4035 break; 4036 } 4037 } 4038 4039 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4040 struct amdgpu_irq_src *source, 4041 unsigned type, 4042 enum amdgpu_interrupt_state state) 4043 { 4044 switch (state) { 4045 case AMDGPU_IRQ_STATE_DISABLE: 4046 case AMDGPU_IRQ_STATE_ENABLE: 4047 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4048 PRIV_REG_INT_ENABLE, 4049 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4050 break; 4051 default: 4052 break; 4053 } 4054 4055 return 0; 4056 } 4057 4058 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4059 struct amdgpu_irq_src *source, 4060 unsigned type, 4061 enum amdgpu_interrupt_state state) 4062 { 4063 switch (state) { 4064 case AMDGPU_IRQ_STATE_DISABLE: 4065 case AMDGPU_IRQ_STATE_ENABLE: 4066 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4067 PRIV_INSTR_INT_ENABLE, 4068 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4069 default: 4070 break; 4071 } 4072 4073 return 0; 4074 } 4075 4076 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4077 struct amdgpu_irq_src *src, 4078 unsigned type, 4079 enum amdgpu_interrupt_state state) 4080 { 4081 switch (type) { 4082 case AMDGPU_CP_IRQ_GFX_EOP: 4083 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4084 break; 4085 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4086 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4087 break; 4088 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4089 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4090 break; 4091 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4092 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4093 break; 4094 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4095 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4096 break; 4097 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4098 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4099 break; 4100 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4101 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4102 break; 4103 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4104 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4105 break; 4106 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4107 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4108 break; 4109 default: 4110 break; 4111 } 4112 return 0; 4113 } 4114 4115 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4116 struct amdgpu_irq_src *source, 4117 struct amdgpu_iv_entry *entry) 4118 { 4119 int i; 4120 u8 me_id, pipe_id, queue_id; 4121 struct amdgpu_ring *ring; 4122 4123 DRM_DEBUG("IH: CP EOP\n"); 4124 me_id = (entry->ring_id & 0x0c) >> 2; 4125 pipe_id = (entry->ring_id & 0x03) >> 0; 4126 queue_id = (entry->ring_id & 0x70) >> 4; 4127 4128 switch (me_id) { 4129 case 0: 4130 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4131 break; 4132 case 1: 4133 case 2: 4134 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4135 ring = &adev->gfx.compute_ring[i]; 4136 /* Per-queue interrupt is supported for MEC starting from VI. 4137 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4138 */ 4139 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4140 amdgpu_fence_process(ring); 4141 } 4142 break; 4143 } 4144 return 0; 4145 } 4146 4147 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4148 struct amdgpu_irq_src *source, 4149 struct amdgpu_iv_entry *entry) 4150 { 4151 DRM_ERROR("Illegal register access in command stream\n"); 4152 schedule_work(&adev->reset_work); 4153 return 0; 4154 } 4155 4156 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4157 struct amdgpu_irq_src *source, 4158 struct amdgpu_iv_entry *entry) 4159 { 4160 DRM_ERROR("Illegal instruction in command stream\n"); 4161 schedule_work(&adev->reset_work); 4162 return 0; 4163 } 4164 4165 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4166 struct amdgpu_irq_src *src, 4167 unsigned int type, 4168 enum amdgpu_interrupt_state state) 4169 { 4170 uint32_t tmp, target; 4171 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4172 4173 if (ring->me == 1) 4174 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4175 else 4176 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4177 target += ring->pipe; 4178 4179 switch (type) { 4180 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4181 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4182 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4183 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4184 GENERIC2_INT_ENABLE, 0); 4185 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4186 4187 tmp = RREG32(target); 4188 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4189 GENERIC2_INT_ENABLE, 0); 4190 WREG32(target, tmp); 4191 } else { 4192 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4193 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4194 GENERIC2_INT_ENABLE, 1); 4195 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4196 4197 tmp = RREG32(target); 4198 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4199 GENERIC2_INT_ENABLE, 1); 4200 WREG32(target, tmp); 4201 } 4202 break; 4203 default: 4204 BUG(); /* kiq only support GENERIC2_INT now */ 4205 break; 4206 } 4207 return 0; 4208 } 4209 4210 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, 4211 struct amdgpu_irq_src *source, 4212 struct amdgpu_iv_entry *entry) 4213 { 4214 u8 me_id, pipe_id, queue_id; 4215 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4216 4217 me_id = (entry->ring_id & 0x0c) >> 2; 4218 pipe_id = (entry->ring_id & 0x03) >> 0; 4219 queue_id = (entry->ring_id & 0x70) >> 4; 4220 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 4221 me_id, pipe_id, queue_id); 4222 4223 amdgpu_fence_process(ring); 4224 return 0; 4225 } 4226 4227 const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4228 .name = "gfx_v9_0", 4229 .early_init = gfx_v9_0_early_init, 4230 .late_init = gfx_v9_0_late_init, 4231 .sw_init = gfx_v9_0_sw_init, 4232 .sw_fini = gfx_v9_0_sw_fini, 4233 .hw_init = gfx_v9_0_hw_init, 4234 .hw_fini = gfx_v9_0_hw_fini, 4235 .suspend = gfx_v9_0_suspend, 4236 .resume = gfx_v9_0_resume, 4237 .is_idle = gfx_v9_0_is_idle, 4238 .wait_for_idle = gfx_v9_0_wait_for_idle, 4239 .soft_reset = gfx_v9_0_soft_reset, 4240 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4241 .set_powergating_state = gfx_v9_0_set_powergating_state, 4242 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4243 }; 4244 4245 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4246 .type = AMDGPU_RING_TYPE_GFX, 4247 .align_mask = 0xff, 4248 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4249 .support_64bit_ptrs = true, 4250 .vmhub = AMDGPU_GFXHUB, 4251 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4252 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4253 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4254 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4255 5 + /* COND_EXEC */ 4256 7 + /* PIPELINE_SYNC */ 4257 24 + /* VM_FLUSH */ 4258 8 + /* FENCE for VM_FLUSH */ 4259 20 + /* GDS switch */ 4260 4 + /* double SWITCH_BUFFER, 4261 the first COND_EXEC jump to the place just 4262 prior to this double SWITCH_BUFFER */ 4263 5 + /* COND_EXEC */ 4264 7 + /* HDP_flush */ 4265 4 + /* VGT_flush */ 4266 14 + /* CE_META */ 4267 31 + /* DE_META */ 4268 3 + /* CNTX_CTRL */ 4269 5 + /* HDP_INVL */ 4270 8 + 8 + /* FENCE x2 */ 4271 2, /* SWITCH_BUFFER */ 4272 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4273 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4274 .emit_fence = gfx_v9_0_ring_emit_fence, 4275 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4276 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4277 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4278 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4279 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4280 .test_ring = gfx_v9_0_ring_test_ring, 4281 .test_ib = gfx_v9_0_ring_test_ib, 4282 .insert_nop = amdgpu_ring_insert_nop, 4283 .pad_ib = amdgpu_ring_generic_pad_ib, 4284 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4285 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4286 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4287 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4288 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4289 }; 4290 4291 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4292 .type = AMDGPU_RING_TYPE_COMPUTE, 4293 .align_mask = 0xff, 4294 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4295 .support_64bit_ptrs = true, 4296 .vmhub = AMDGPU_GFXHUB, 4297 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4298 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4299 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4300 .emit_frame_size = 4301 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4302 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4303 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4304 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4305 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4306 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4307 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4308 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4309 .emit_fence = gfx_v9_0_ring_emit_fence, 4310 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4311 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4312 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4313 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4314 .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, 4315 .test_ring = gfx_v9_0_ring_test_ring, 4316 .test_ib = gfx_v9_0_ring_test_ib, 4317 .insert_nop = amdgpu_ring_insert_nop, 4318 .pad_ib = amdgpu_ring_generic_pad_ib, 4319 }; 4320 4321 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4322 .type = AMDGPU_RING_TYPE_KIQ, 4323 .align_mask = 0xff, 4324 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4325 .support_64bit_ptrs = true, 4326 .vmhub = AMDGPU_GFXHUB, 4327 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4328 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4329 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4330 .emit_frame_size = 4331 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4332 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4333 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ 4334 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4335 24 + /* gfx_v9_0_ring_emit_vm_flush */ 4336 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4337 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4338 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4339 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4340 .test_ring = gfx_v9_0_ring_test_ring, 4341 .test_ib = gfx_v9_0_ring_test_ib, 4342 .insert_nop = amdgpu_ring_insert_nop, 4343 .pad_ib = amdgpu_ring_generic_pad_ib, 4344 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4345 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4346 }; 4347 4348 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4349 { 4350 int i; 4351 4352 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4353 4354 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4355 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4356 4357 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4358 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 4359 } 4360 4361 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { 4362 .set = gfx_v9_0_kiq_set_interrupt_state, 4363 .process = gfx_v9_0_kiq_irq, 4364 }; 4365 4366 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 4367 .set = gfx_v9_0_set_eop_interrupt_state, 4368 .process = gfx_v9_0_eop_irq, 4369 }; 4370 4371 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 4372 .set = gfx_v9_0_set_priv_reg_fault_state, 4373 .process = gfx_v9_0_priv_reg_irq, 4374 }; 4375 4376 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 4377 .set = gfx_v9_0_set_priv_inst_fault_state, 4378 .process = gfx_v9_0_priv_inst_irq, 4379 }; 4380 4381 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 4382 { 4383 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4384 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 4385 4386 adev->gfx.priv_reg_irq.num_types = 1; 4387 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 4388 4389 adev->gfx.priv_inst_irq.num_types = 1; 4390 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 4391 4392 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 4393 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; 4394 } 4395 4396 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 4397 { 4398 switch (adev->asic_type) { 4399 case CHIP_VEGA10: 4400 case CHIP_RAVEN: 4401 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4402 break; 4403 default: 4404 break; 4405 } 4406 } 4407 4408 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4409 { 4410 /* init asci gds info */ 4411 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4412 adev->gds.gws.total_size = 64; 4413 adev->gds.oa.total_size = 16; 4414 4415 if (adev->gds.mem.total_size == 64 * 1024) { 4416 adev->gds.mem.gfx_partition_size = 4096; 4417 adev->gds.mem.cs_partition_size = 4096; 4418 4419 adev->gds.gws.gfx_partition_size = 4; 4420 adev->gds.gws.cs_partition_size = 4; 4421 4422 adev->gds.oa.gfx_partition_size = 4; 4423 adev->gds.oa.cs_partition_size = 1; 4424 } else { 4425 adev->gds.mem.gfx_partition_size = 1024; 4426 adev->gds.mem.cs_partition_size = 1024; 4427 4428 adev->gds.gws.gfx_partition_size = 16; 4429 adev->gds.gws.cs_partition_size = 16; 4430 4431 adev->gds.oa.gfx_partition_size = 4; 4432 adev->gds.oa.cs_partition_size = 4; 4433 } 4434 } 4435 4436 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4437 { 4438 u32 data, mask; 4439 4440 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 4441 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 4442 4443 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4444 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4445 4446 mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 4447 4448 return (~data) & mask; 4449 } 4450 4451 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 4452 struct amdgpu_cu_info *cu_info) 4453 { 4454 int i, j, k, counter, active_cu_number = 0; 4455 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4456 4457 if (!adev || !cu_info) 4458 return -EINVAL; 4459 4460 memset(cu_info, 0, sizeof(*cu_info)); 4461 4462 mutex_lock(&adev->grbm_idx_mutex); 4463 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4464 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4465 mask = 1; 4466 ao_bitmap = 0; 4467 counter = 0; 4468 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4469 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4470 cu_info->bitmap[i][j] = bitmap; 4471 4472 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4473 if (bitmap & mask) { 4474 if (counter < adev->gfx.config.max_cu_per_sh) 4475 ao_bitmap |= mask; 4476 counter ++; 4477 } 4478 mask <<= 1; 4479 } 4480 active_cu_number += counter; 4481 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4482 } 4483 } 4484 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4485 mutex_unlock(&adev->grbm_idx_mutex); 4486 4487 cu_info->number = active_cu_number; 4488 cu_info->ao_cu_mask = ao_cu_mask; 4489 4490 return 0; 4491 } 4492 4493 static int gfx_v9_0_init_queue(struct amdgpu_ring *ring) 4494 { 4495 int r, j; 4496 u32 tmp; 4497 bool use_doorbell = true; 4498 u64 hqd_gpu_addr; 4499 u64 mqd_gpu_addr; 4500 u64 eop_gpu_addr; 4501 u64 wb_gpu_addr; 4502 u32 *buf; 4503 struct v9_mqd *mqd; 4504 struct amdgpu_device *adev; 4505 4506 adev = ring->adev; 4507 if (ring->mqd_obj == NULL) { 4508 r = amdgpu_bo_create(adev, 4509 sizeof(struct v9_mqd), 4510 PAGE_SIZE,true, 4511 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, 4512 NULL, &ring->mqd_obj); 4513 if (r) { 4514 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 4515 return r; 4516 } 4517 } 4518 4519 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4520 if (unlikely(r != 0)) { 4521 gfx_v9_0_cp_compute_fini(adev); 4522 return r; 4523 } 4524 4525 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 4526 &mqd_gpu_addr); 4527 if (r) { 4528 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 4529 gfx_v9_0_cp_compute_fini(adev); 4530 return r; 4531 } 4532 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 4533 if (r) { 4534 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 4535 gfx_v9_0_cp_compute_fini(adev); 4536 return r; 4537 } 4538 4539 /* init the mqd struct */ 4540 memset(buf, 0, sizeof(struct v9_mqd)); 4541 4542 mqd = (struct v9_mqd *)buf; 4543 mqd->header = 0xC0310800; 4544 mqd->compute_pipelinestat_enable = 0x00000001; 4545 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4546 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4547 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4548 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4549 mqd->compute_misc_reserved = 0x00000003; 4550 mutex_lock(&adev->srbm_mutex); 4551 soc15_grbm_select(adev, ring->me, 4552 ring->pipe, 4553 ring->queue, 0); 4554 /* disable wptr polling */ 4555 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4556 4557 /* write the EOP addr */ 4558 BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */ 4559 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (ring->queue * MEC_HPD_SIZE); 4560 eop_gpu_addr >>= 8; 4561 4562 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, lower_32_bits(eop_gpu_addr)); 4563 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); 4564 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_gpu_addr); 4565 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_gpu_addr); 4566 4567 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4568 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 4569 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4570 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 4571 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, tmp); 4572 4573 /* enable doorbell? */ 4574 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 4575 if (use_doorbell) 4576 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 4577 else 4578 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); 4579 4580 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); 4581 mqd->cp_hqd_pq_doorbell_control = tmp; 4582 4583 /* disable the queue if it's active */ 4584 ring->wptr = 0; 4585 mqd->cp_hqd_dequeue_request = 0; 4586 mqd->cp_hqd_pq_rptr = 0; 4587 mqd->cp_hqd_pq_wptr_lo = 0; 4588 mqd->cp_hqd_pq_wptr_hi = 0; 4589 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 4590 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 4591 for (j = 0; j < adev->usec_timeout; j++) { 4592 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 4593 break; 4594 udelay(1); 4595 } 4596 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); 4597 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); 4598 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo); 4599 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi); 4600 } 4601 4602 /* set the pointer to the MQD */ 4603 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 4604 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 4605 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 4606 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 4607 4608 /* set MQD vmid to 0 */ 4609 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 4610 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4611 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, tmp); 4612 mqd->cp_mqd_control = tmp; 4613 4614 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4615 hqd_gpu_addr = ring->gpu_addr >> 8; 4616 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4617 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4618 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 4619 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 4620 4621 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4622 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 4623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4624 (order_base_2(ring->ring_size / 4) - 1)); 4625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4626 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4627 #ifdef __BIG_ENDIAN 4628 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4629 #endif 4630 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 4632 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4633 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4634 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, tmp); 4635 mqd->cp_hqd_pq_control = tmp; 4636 4637 /* set the wb address wether it's enabled or not */ 4638 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 4639 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4640 mqd->cp_hqd_pq_rptr_report_addr_hi = 4641 upper_32_bits(wb_gpu_addr) & 0xffff; 4642 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 4643 mqd->cp_hqd_pq_rptr_report_addr_lo); 4644 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4645 mqd->cp_hqd_pq_rptr_report_addr_hi); 4646 4647 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4648 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4649 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4650 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4651 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 4652 mqd->cp_hqd_pq_wptr_poll_addr_lo); 4653 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4654 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4655 4656 /* enable the doorbell if requested */ 4657 if (use_doorbell) { 4658 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 4659 (AMDGPU_DOORBELL64_KIQ * 2) << 2); 4660 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 4661 (AMDGPU_DOORBELL64_MEC_RING7 * 2) << 2); 4662 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 4663 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4664 DOORBELL_OFFSET, ring->doorbell_index); 4665 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 4666 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); 4667 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); 4668 mqd->cp_hqd_pq_doorbell_control = tmp; 4669 4670 } else { 4671 mqd->cp_hqd_pq_doorbell_control = 0; 4672 } 4673 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 4674 mqd->cp_hqd_pq_doorbell_control); 4675 4676 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4677 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, mqd->cp_hqd_pq_wptr_lo); 4678 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, mqd->cp_hqd_pq_wptr_hi); 4679 4680 /* set the vmid for the queue */ 4681 mqd->cp_hqd_vmid = 0; 4682 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 4683 4684 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 4685 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 4686 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, tmp); 4687 mqd->cp_hqd_persistent_state = tmp; 4688 4689 /* activate the queue */ 4690 mqd->cp_hqd_active = 1; 4691 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 4692 4693 soc15_grbm_select(adev, 0, 0, 0, 0); 4694 mutex_unlock(&adev->srbm_mutex); 4695 4696 amdgpu_bo_kunmap(ring->mqd_obj); 4697 amdgpu_bo_unreserve(ring->mqd_obj); 4698 4699 if (use_doorbell) 4700 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4701 4702 return 0; 4703 } 4704 4705 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4706 { 4707 .type = AMD_IP_BLOCK_TYPE_GFX, 4708 .major = 9, 4709 .minor = 0, 4710 .rev = 0, 4711 .funcs = &gfx_v9_0_ip_funcs, 4712 }; 4713