1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "amdgpu_ring_mux.h" 51 #include "gfx_v9_4.h" 52 #include "gfx_v9_0.h" 53 #include "gfx_v9_4_2.h" 54 55 #include "asic_reg/pwr/pwr_10_0_offset.h" 56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 57 #include "asic_reg/gc/gc_9_0_default.h" 58 59 #define GFX9_NUM_GFX_RINGS 1 60 #define GFX9_NUM_SW_GFX_RINGS 2 61 #define GFX9_MEC_HPD_SIZE 4096 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 114 115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 127 128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 133 134 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 144 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 146 147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 151 152 #define mmGOLDEN_TSC_COUNT_UPPER_Raven 0x007a 153 #define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0 154 #define mmGOLDEN_TSC_COUNT_LOWER_Raven 0x007b 155 #define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0 156 157 #define mmGOLDEN_TSC_COUNT_UPPER_Raven2 0x0068 158 #define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0 159 #define mmGOLDEN_TSC_COUNT_LOWER_Raven2 0x0069 160 #define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0 161 162 enum ta_ras_gfx_subblock { 163 /*CPC*/ 164 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 165 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 166 TA_RAS_BLOCK__GFX_CPC_UCODE, 167 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 168 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 169 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 170 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 171 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 172 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 173 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 174 /* CPF*/ 175 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 176 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 177 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 178 TA_RAS_BLOCK__GFX_CPF_TAG, 179 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 180 /* CPG*/ 181 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 182 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 183 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 184 TA_RAS_BLOCK__GFX_CPG_TAG, 185 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 186 /* GDS*/ 187 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 188 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 189 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 190 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 191 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 192 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 193 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 194 /* SPI*/ 195 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 196 /* SQ*/ 197 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 198 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 199 TA_RAS_BLOCK__GFX_SQ_LDS_D, 200 TA_RAS_BLOCK__GFX_SQ_LDS_I, 201 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 202 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 203 /* SQC (3 ranges)*/ 204 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 205 /* SQC range 0*/ 206 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 207 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 208 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 209 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 210 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 211 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 212 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 213 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 214 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 215 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 216 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 217 /* SQC range 1*/ 218 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 219 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 220 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 221 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 222 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 223 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 224 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 225 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 226 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 227 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 228 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 229 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 230 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 231 /* SQC range 2*/ 232 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 233 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 234 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 235 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 236 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 237 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 238 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 239 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 240 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 241 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 242 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 243 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 244 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 245 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 246 /* TA*/ 247 TA_RAS_BLOCK__GFX_TA_INDEX_START, 248 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 249 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 250 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 251 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 252 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 253 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 254 /* TCA*/ 255 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 256 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 257 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 258 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 259 /* TCC (5 sub-ranges)*/ 260 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 261 /* TCC range 0*/ 262 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 263 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 264 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 265 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 266 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 267 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 268 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 269 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 270 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 271 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 272 /* TCC range 1*/ 273 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 274 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 275 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 276 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 277 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 278 /* TCC range 2*/ 279 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 280 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 281 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 282 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 283 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 284 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 285 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 286 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 287 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 288 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 289 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 290 /* TCC range 3*/ 291 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 292 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 293 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 294 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 295 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 296 /* TCC range 4*/ 297 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 298 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 299 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 300 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 301 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 302 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 303 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 304 /* TCI*/ 305 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 306 /* TCP*/ 307 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 308 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 309 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 310 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 311 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 312 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 313 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 314 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 315 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 316 /* TD*/ 317 TA_RAS_BLOCK__GFX_TD_INDEX_START, 318 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 319 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 320 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 321 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 322 /* EA (3 sub-ranges)*/ 323 TA_RAS_BLOCK__GFX_EA_INDEX_START, 324 /* EA range 0*/ 325 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 326 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 327 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 328 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 329 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 330 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 331 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 332 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 333 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 334 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 335 /* EA range 1*/ 336 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 337 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 338 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 339 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 340 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 341 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 342 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 343 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 344 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 345 /* EA range 2*/ 346 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 347 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 348 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 349 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 350 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 351 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 352 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 353 /* UTC VM L2 bank*/ 354 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 355 /* UTC VM walker*/ 356 TA_RAS_BLOCK__UTC_VML2_WALKER, 357 /* UTC ATC L2 2MB cache*/ 358 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 359 /* UTC ATC L2 4KB cache*/ 360 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 361 TA_RAS_BLOCK__GFX_MAX 362 }; 363 364 struct ras_gfx_subblock { 365 unsigned char *name; 366 int ta_subblock; 367 int hw_supported_error_type; 368 int sw_supported_error_type; 369 }; 370 371 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 372 [AMDGPU_RAS_BLOCK__##subblock] = { \ 373 #subblock, \ 374 TA_RAS_BLOCK__##subblock, \ 375 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 376 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 377 } 378 379 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 380 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 382 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 383 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 384 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 386 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 387 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 388 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 390 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 391 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 392 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 393 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 394 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 395 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 396 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 397 0), 398 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 399 0), 400 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 402 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 404 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 406 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 408 0, 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 410 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 412 0, 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 416 0, 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 420 1), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 422 0, 0, 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 430 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 432 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 434 0, 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 436 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 438 0), 439 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 440 0, 0, 0), 441 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 442 0), 443 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 446 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 448 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 450 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 452 0, 0), 453 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 454 0), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 456 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 458 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 460 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 464 1), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 466 1), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 468 1), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 470 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 472 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 478 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 480 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 485 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 488 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 490 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 492 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 495 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 502 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 510 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 511 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 512 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 513 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 515 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 516 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 517 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 518 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 519 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 520 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 521 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 522 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 523 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 524 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 525 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 526 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 527 }; 528 529 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 530 { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 551 }; 552 553 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 554 { 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 573 }; 574 575 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 576 { 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 588 }; 589 590 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 591 { 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 616 }; 617 618 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 619 { 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 627 }; 628 629 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 630 { 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 650 }; 651 652 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 653 { 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 666 }; 667 668 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 669 { 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 673 }; 674 675 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 676 { 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 693 }; 694 695 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 696 { 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 710 }; 711 712 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 713 { 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 725 }; 726 727 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 728 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 729 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 730 }; 731 732 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 733 { 734 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 735 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 736 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 737 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 738 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 739 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 740 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 741 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 742 }; 743 744 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 745 { 746 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 747 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 748 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 749 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 750 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 751 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 752 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 753 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 754 }; 755 756 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 757 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 758 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 759 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 760 761 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 762 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 763 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 764 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 765 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 766 struct amdgpu_cu_info *cu_info); 767 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 768 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 769 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 770 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 771 void *ras_error_status); 772 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 773 void *inject_if); 774 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 775 776 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 777 uint64_t queue_mask) 778 { 779 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 780 amdgpu_ring_write(kiq_ring, 781 PACKET3_SET_RESOURCES_VMID_MASK(0) | 782 /* vmid_mask:0* queue_type:0 (KIQ) */ 783 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 784 amdgpu_ring_write(kiq_ring, 785 lower_32_bits(queue_mask)); /* queue mask lo */ 786 amdgpu_ring_write(kiq_ring, 787 upper_32_bits(queue_mask)); /* queue mask hi */ 788 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 789 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 790 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 791 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 792 } 793 794 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 795 struct amdgpu_ring *ring) 796 { 797 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 798 uint64_t wptr_addr = ring->wptr_gpu_addr; 799 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 800 801 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 802 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 803 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 804 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 805 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 806 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 807 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 808 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 809 /*queue_type: normal compute queue */ 810 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 811 /* alloc format: all_on_one_pipe */ 812 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 813 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 814 /* num_queues: must be 1 */ 815 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 816 amdgpu_ring_write(kiq_ring, 817 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 818 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 819 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 820 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 821 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 822 } 823 824 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 825 struct amdgpu_ring *ring, 826 enum amdgpu_unmap_queues_action action, 827 u64 gpu_addr, u64 seq) 828 { 829 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 830 831 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 832 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 833 PACKET3_UNMAP_QUEUES_ACTION(action) | 834 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 835 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 836 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 837 amdgpu_ring_write(kiq_ring, 838 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 839 840 if (action == PREEMPT_QUEUES_NO_UNMAP) { 841 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 842 amdgpu_ring_write(kiq_ring, 0); 843 amdgpu_ring_write(kiq_ring, 0); 844 845 } else { 846 amdgpu_ring_write(kiq_ring, 0); 847 amdgpu_ring_write(kiq_ring, 0); 848 amdgpu_ring_write(kiq_ring, 0); 849 } 850 } 851 852 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 853 struct amdgpu_ring *ring, 854 u64 addr, 855 u64 seq) 856 { 857 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 858 859 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 860 amdgpu_ring_write(kiq_ring, 861 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 862 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 863 PACKET3_QUERY_STATUS_COMMAND(2)); 864 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 865 amdgpu_ring_write(kiq_ring, 866 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 867 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 868 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 869 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 870 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 871 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 872 } 873 874 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 875 uint16_t pasid, uint32_t flush_type, 876 bool all_hub) 877 { 878 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 879 amdgpu_ring_write(kiq_ring, 880 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 881 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 882 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 883 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 884 } 885 886 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 887 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 888 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 889 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 890 .kiq_query_status = gfx_v9_0_kiq_query_status, 891 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 892 .set_resources_size = 8, 893 .map_queues_size = 7, 894 .unmap_queues_size = 6, 895 .query_status_size = 7, 896 .invalidate_tlbs_size = 2, 897 }; 898 899 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 900 { 901 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; 902 } 903 904 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 905 { 906 switch (adev->ip_versions[GC_HWIP][0]) { 907 case IP_VERSION(9, 0, 1): 908 soc15_program_register_sequence(adev, 909 golden_settings_gc_9_0, 910 ARRAY_SIZE(golden_settings_gc_9_0)); 911 soc15_program_register_sequence(adev, 912 golden_settings_gc_9_0_vg10, 913 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 914 break; 915 case IP_VERSION(9, 2, 1): 916 soc15_program_register_sequence(adev, 917 golden_settings_gc_9_2_1, 918 ARRAY_SIZE(golden_settings_gc_9_2_1)); 919 soc15_program_register_sequence(adev, 920 golden_settings_gc_9_2_1_vg12, 921 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 922 break; 923 case IP_VERSION(9, 4, 0): 924 soc15_program_register_sequence(adev, 925 golden_settings_gc_9_0, 926 ARRAY_SIZE(golden_settings_gc_9_0)); 927 soc15_program_register_sequence(adev, 928 golden_settings_gc_9_0_vg20, 929 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 930 break; 931 case IP_VERSION(9, 4, 1): 932 soc15_program_register_sequence(adev, 933 golden_settings_gc_9_4_1_arct, 934 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 935 break; 936 case IP_VERSION(9, 2, 2): 937 case IP_VERSION(9, 1, 0): 938 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 939 ARRAY_SIZE(golden_settings_gc_9_1)); 940 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 941 soc15_program_register_sequence(adev, 942 golden_settings_gc_9_1_rv2, 943 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 944 else 945 soc15_program_register_sequence(adev, 946 golden_settings_gc_9_1_rv1, 947 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 948 break; 949 case IP_VERSION(9, 3, 0): 950 soc15_program_register_sequence(adev, 951 golden_settings_gc_9_1_rn, 952 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 953 return; /* for renoir, don't need common goldensetting */ 954 case IP_VERSION(9, 4, 2): 955 gfx_v9_4_2_init_golden_registers(adev, 956 adev->smuio.funcs->get_die_id(adev)); 957 break; 958 default: 959 break; 960 } 961 962 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 963 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) 964 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 965 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 966 } 967 968 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 969 bool wc, uint32_t reg, uint32_t val) 970 { 971 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 972 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 973 WRITE_DATA_DST_SEL(0) | 974 (wc ? WR_CONFIRM : 0)); 975 amdgpu_ring_write(ring, reg); 976 amdgpu_ring_write(ring, 0); 977 amdgpu_ring_write(ring, val); 978 } 979 980 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 981 int mem_space, int opt, uint32_t addr0, 982 uint32_t addr1, uint32_t ref, uint32_t mask, 983 uint32_t inv) 984 { 985 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 986 amdgpu_ring_write(ring, 987 /* memory (1) or register (0) */ 988 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 989 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 990 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 991 WAIT_REG_MEM_ENGINE(eng_sel))); 992 993 if (mem_space) 994 BUG_ON(addr0 & 0x3); /* Dword align */ 995 amdgpu_ring_write(ring, addr0); 996 amdgpu_ring_write(ring, addr1); 997 amdgpu_ring_write(ring, ref); 998 amdgpu_ring_write(ring, mask); 999 amdgpu_ring_write(ring, inv); /* poll interval */ 1000 } 1001 1002 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1003 { 1004 struct amdgpu_device *adev = ring->adev; 1005 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1006 uint32_t tmp = 0; 1007 unsigned i; 1008 int r; 1009 1010 WREG32(scratch, 0xCAFEDEAD); 1011 r = amdgpu_ring_alloc(ring, 3); 1012 if (r) 1013 return r; 1014 1015 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1016 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1017 amdgpu_ring_write(ring, 0xDEADBEEF); 1018 amdgpu_ring_commit(ring); 1019 1020 for (i = 0; i < adev->usec_timeout; i++) { 1021 tmp = RREG32(scratch); 1022 if (tmp == 0xDEADBEEF) 1023 break; 1024 udelay(1); 1025 } 1026 1027 if (i >= adev->usec_timeout) 1028 r = -ETIMEDOUT; 1029 return r; 1030 } 1031 1032 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1033 { 1034 struct amdgpu_device *adev = ring->adev; 1035 struct amdgpu_ib ib; 1036 struct dma_fence *f = NULL; 1037 1038 unsigned index; 1039 uint64_t gpu_addr; 1040 uint32_t tmp; 1041 long r; 1042 1043 r = amdgpu_device_wb_get(adev, &index); 1044 if (r) 1045 return r; 1046 1047 gpu_addr = adev->wb.gpu_addr + (index * 4); 1048 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1049 memset(&ib, 0, sizeof(ib)); 1050 r = amdgpu_ib_get(adev, NULL, 16, 1051 AMDGPU_IB_POOL_DIRECT, &ib); 1052 if (r) 1053 goto err1; 1054 1055 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1056 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1057 ib.ptr[2] = lower_32_bits(gpu_addr); 1058 ib.ptr[3] = upper_32_bits(gpu_addr); 1059 ib.ptr[4] = 0xDEADBEEF; 1060 ib.length_dw = 5; 1061 1062 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1063 if (r) 1064 goto err2; 1065 1066 r = dma_fence_wait_timeout(f, false, timeout); 1067 if (r == 0) { 1068 r = -ETIMEDOUT; 1069 goto err2; 1070 } else if (r < 0) { 1071 goto err2; 1072 } 1073 1074 tmp = adev->wb.wb[index]; 1075 if (tmp == 0xDEADBEEF) 1076 r = 0; 1077 else 1078 r = -EINVAL; 1079 1080 err2: 1081 amdgpu_ib_free(adev, &ib, NULL); 1082 dma_fence_put(f); 1083 err1: 1084 amdgpu_device_wb_free(adev, index); 1085 return r; 1086 } 1087 1088 1089 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1090 { 1091 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1092 amdgpu_ucode_release(&adev->gfx.me_fw); 1093 amdgpu_ucode_release(&adev->gfx.ce_fw); 1094 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1095 amdgpu_ucode_release(&adev->gfx.mec_fw); 1096 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1097 1098 kfree(adev->gfx.rlc.register_list_format); 1099 } 1100 1101 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1102 { 1103 adev->gfx.me_fw_write_wait = false; 1104 adev->gfx.mec_fw_write_wait = false; 1105 1106 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 1107 ((adev->gfx.mec_fw_version < 0x000001a5) || 1108 (adev->gfx.mec_feature_version < 46) || 1109 (adev->gfx.pfp_fw_version < 0x000000b7) || 1110 (adev->gfx.pfp_feature_version < 46))) 1111 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1112 1113 switch (adev->ip_versions[GC_HWIP][0]) { 1114 case IP_VERSION(9, 0, 1): 1115 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1116 (adev->gfx.me_feature_version >= 42) && 1117 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1118 (adev->gfx.pfp_feature_version >= 42)) 1119 adev->gfx.me_fw_write_wait = true; 1120 1121 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1122 (adev->gfx.mec_feature_version >= 42)) 1123 adev->gfx.mec_fw_write_wait = true; 1124 break; 1125 case IP_VERSION(9, 2, 1): 1126 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1127 (adev->gfx.me_feature_version >= 44) && 1128 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1129 (adev->gfx.pfp_feature_version >= 44)) 1130 adev->gfx.me_fw_write_wait = true; 1131 1132 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1133 (adev->gfx.mec_feature_version >= 44)) 1134 adev->gfx.mec_fw_write_wait = true; 1135 break; 1136 case IP_VERSION(9, 4, 0): 1137 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1138 (adev->gfx.me_feature_version >= 44) && 1139 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1140 (adev->gfx.pfp_feature_version >= 44)) 1141 adev->gfx.me_fw_write_wait = true; 1142 1143 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1144 (adev->gfx.mec_feature_version >= 44)) 1145 adev->gfx.mec_fw_write_wait = true; 1146 break; 1147 case IP_VERSION(9, 1, 0): 1148 case IP_VERSION(9, 2, 2): 1149 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1150 (adev->gfx.me_feature_version >= 42) && 1151 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1152 (adev->gfx.pfp_feature_version >= 42)) 1153 adev->gfx.me_fw_write_wait = true; 1154 1155 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1156 (adev->gfx.mec_feature_version >= 42)) 1157 adev->gfx.mec_fw_write_wait = true; 1158 break; 1159 default: 1160 adev->gfx.me_fw_write_wait = true; 1161 adev->gfx.mec_fw_write_wait = true; 1162 break; 1163 } 1164 } 1165 1166 struct amdgpu_gfxoff_quirk { 1167 u16 chip_vendor; 1168 u16 chip_device; 1169 u16 subsys_vendor; 1170 u16 subsys_device; 1171 u8 revision; 1172 }; 1173 1174 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1175 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1176 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1177 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1178 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1179 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1180 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1181 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1182 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1183 { 0, 0, 0, 0, 0 }, 1184 }; 1185 1186 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1187 { 1188 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1189 1190 while (p && p->chip_device != 0) { 1191 if (pdev->vendor == p->chip_vendor && 1192 pdev->device == p->chip_device && 1193 pdev->subsystem_vendor == p->subsys_vendor && 1194 pdev->subsystem_device == p->subsys_device && 1195 pdev->revision == p->revision) { 1196 return true; 1197 } 1198 ++p; 1199 } 1200 return false; 1201 } 1202 1203 static bool is_raven_kicker(struct amdgpu_device *adev) 1204 { 1205 if (adev->pm.fw_version >= 0x41e2b) 1206 return true; 1207 else 1208 return false; 1209 } 1210 1211 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1212 { 1213 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && 1214 (adev->gfx.me_fw_version >= 0x000000a5) && 1215 (adev->gfx.me_feature_version >= 52)) 1216 return true; 1217 else 1218 return false; 1219 } 1220 1221 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1222 { 1223 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1224 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1225 1226 switch (adev->ip_versions[GC_HWIP][0]) { 1227 case IP_VERSION(9, 0, 1): 1228 case IP_VERSION(9, 2, 1): 1229 case IP_VERSION(9, 4, 0): 1230 break; 1231 case IP_VERSION(9, 2, 2): 1232 case IP_VERSION(9, 1, 0): 1233 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1234 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1235 ((!is_raven_kicker(adev) && 1236 adev->gfx.rlc_fw_version < 531) || 1237 (adev->gfx.rlc_feature_version < 1) || 1238 !adev->gfx.rlc.is_rlc_v2_1)) 1239 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1240 1241 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1242 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1243 AMD_PG_SUPPORT_CP | 1244 AMD_PG_SUPPORT_RLC_SMU_HS; 1245 break; 1246 case IP_VERSION(9, 3, 0): 1247 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1248 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1249 AMD_PG_SUPPORT_CP | 1250 AMD_PG_SUPPORT_RLC_SMU_HS; 1251 break; 1252 default: 1253 break; 1254 } 1255 } 1256 1257 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1258 char *chip_name) 1259 { 1260 char fw_name[30]; 1261 int err; 1262 1263 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1264 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 1265 if (err) 1266 goto out; 1267 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1268 1269 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1270 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 1271 if (err) 1272 goto out; 1273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1274 1275 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1276 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 1277 if (err) 1278 goto out; 1279 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1280 1281 out: 1282 if (err) { 1283 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1284 amdgpu_ucode_release(&adev->gfx.me_fw); 1285 amdgpu_ucode_release(&adev->gfx.ce_fw); 1286 } 1287 return err; 1288 } 1289 1290 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1291 char *chip_name) 1292 { 1293 char fw_name[30]; 1294 int err; 1295 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1296 uint16_t version_major; 1297 uint16_t version_minor; 1298 uint32_t smu_version; 1299 1300 /* 1301 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1302 * instead of picasso_rlc.bin. 1303 * Judgment method: 1304 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1305 * or revision >= 0xD8 && revision <= 0xDF 1306 * otherwise is PCO FP5 1307 */ 1308 if (!strcmp(chip_name, "picasso") && 1309 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1310 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1312 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1313 (smu_version >= 0x41e2b)) 1314 /** 1315 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1316 */ 1317 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1318 else 1319 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1320 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 1321 if (err) 1322 goto out; 1323 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1324 1325 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1326 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1327 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1328 out: 1329 if (err) 1330 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1331 1332 return err; 1333 } 1334 1335 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1336 { 1337 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1338 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1339 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) 1340 return false; 1341 1342 return true; 1343 } 1344 1345 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1346 char *chip_name) 1347 { 1348 char fw_name[30]; 1349 int err; 1350 1351 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); 1353 else 1354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1355 1356 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 1357 if (err) 1358 goto out; 1359 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1360 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1361 1362 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1363 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1364 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); 1365 else 1366 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1367 1368 /* ignore failures to load */ 1369 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 1370 if (!err) { 1371 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1372 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1373 } else { 1374 err = 0; 1375 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1376 } 1377 } else { 1378 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1379 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1380 } 1381 1382 gfx_v9_0_check_if_need_gfxoff(adev); 1383 gfx_v9_0_check_fw_write_wait(adev); 1384 1385 out: 1386 if (err) 1387 amdgpu_ucode_release(&adev->gfx.mec_fw); 1388 return err; 1389 } 1390 1391 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1392 { 1393 char ucode_prefix[30]; 1394 int r; 1395 1396 DRM_DEBUG("\n"); 1397 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 1398 1399 /* No CPG in Arcturus */ 1400 if (adev->gfx.num_gfx_rings) { 1401 r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); 1402 if (r) 1403 return r; 1404 } 1405 1406 r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); 1407 if (r) 1408 return r; 1409 1410 r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); 1411 if (r) 1412 return r; 1413 1414 return r; 1415 } 1416 1417 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1418 { 1419 u32 count = 0; 1420 const struct cs_section_def *sect = NULL; 1421 const struct cs_extent_def *ext = NULL; 1422 1423 /* begin clear state */ 1424 count += 2; 1425 /* context control state */ 1426 count += 3; 1427 1428 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1429 for (ext = sect->section; ext->extent != NULL; ++ext) { 1430 if (sect->id == SECT_CONTEXT) 1431 count += 2 + ext->reg_count; 1432 else 1433 return 0; 1434 } 1435 } 1436 1437 /* end clear state */ 1438 count += 2; 1439 /* clear state */ 1440 count += 2; 1441 1442 return count; 1443 } 1444 1445 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1446 volatile u32 *buffer) 1447 { 1448 u32 count = 0, i; 1449 const struct cs_section_def *sect = NULL; 1450 const struct cs_extent_def *ext = NULL; 1451 1452 if (adev->gfx.rlc.cs_data == NULL) 1453 return; 1454 if (buffer == NULL) 1455 return; 1456 1457 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1458 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1459 1460 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1461 buffer[count++] = cpu_to_le32(0x80000000); 1462 buffer[count++] = cpu_to_le32(0x80000000); 1463 1464 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1465 for (ext = sect->section; ext->extent != NULL; ++ext) { 1466 if (sect->id == SECT_CONTEXT) { 1467 buffer[count++] = 1468 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1469 buffer[count++] = cpu_to_le32(ext->reg_index - 1470 PACKET3_SET_CONTEXT_REG_START); 1471 for (i = 0; i < ext->reg_count; i++) 1472 buffer[count++] = cpu_to_le32(ext->extent[i]); 1473 } else { 1474 return; 1475 } 1476 } 1477 } 1478 1479 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1480 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1481 1482 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1483 buffer[count++] = cpu_to_le32(0); 1484 } 1485 1486 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1487 { 1488 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1489 uint32_t pg_always_on_cu_num = 2; 1490 uint32_t always_on_cu_num; 1491 uint32_t i, j, k; 1492 uint32_t mask, cu_bitmap, counter; 1493 1494 if (adev->flags & AMD_IS_APU) 1495 always_on_cu_num = 4; 1496 else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) 1497 always_on_cu_num = 8; 1498 else 1499 always_on_cu_num = 12; 1500 1501 mutex_lock(&adev->grbm_idx_mutex); 1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1504 mask = 1; 1505 cu_bitmap = 0; 1506 counter = 0; 1507 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 1508 1509 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1510 if (cu_info->bitmap[i][j] & mask) { 1511 if (counter == pg_always_on_cu_num) 1512 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1513 if (counter < always_on_cu_num) 1514 cu_bitmap |= mask; 1515 else 1516 break; 1517 counter++; 1518 } 1519 mask <<= 1; 1520 } 1521 1522 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1523 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1524 } 1525 } 1526 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1527 mutex_unlock(&adev->grbm_idx_mutex); 1528 } 1529 1530 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1531 { 1532 uint32_t data; 1533 1534 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1535 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1536 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1537 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1538 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1539 1540 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1541 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1542 1543 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1544 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1545 1546 mutex_lock(&adev->grbm_idx_mutex); 1547 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1548 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1549 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1550 1551 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1552 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1553 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1554 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1555 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1556 1557 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1558 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1559 data &= 0x0000FFFF; 1560 data |= 0x00C00000; 1561 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1562 1563 /* 1564 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1565 * programmed in gfx_v9_0_init_always_on_cu_mask() 1566 */ 1567 1568 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1569 * but used for RLC_LB_CNTL configuration */ 1570 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1571 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1572 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1573 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1574 mutex_unlock(&adev->grbm_idx_mutex); 1575 1576 gfx_v9_0_init_always_on_cu_mask(adev); 1577 } 1578 1579 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1580 { 1581 uint32_t data; 1582 1583 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1584 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1585 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1586 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1587 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1588 1589 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1590 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1591 1592 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1593 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1594 1595 mutex_lock(&adev->grbm_idx_mutex); 1596 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1597 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1598 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1599 1600 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1601 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1602 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1603 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1604 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1605 1606 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1607 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1608 data &= 0x0000FFFF; 1609 data |= 0x00C00000; 1610 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1611 1612 /* 1613 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1614 * programmed in gfx_v9_0_init_always_on_cu_mask() 1615 */ 1616 1617 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1618 * but used for RLC_LB_CNTL configuration */ 1619 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1620 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1621 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1622 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1623 mutex_unlock(&adev->grbm_idx_mutex); 1624 1625 gfx_v9_0_init_always_on_cu_mask(adev); 1626 } 1627 1628 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1629 { 1630 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1631 } 1632 1633 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1634 { 1635 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1636 return 5; 1637 else 1638 return 4; 1639 } 1640 1641 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1642 { 1643 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1644 1645 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 1646 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1647 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1648 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1649 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1650 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1651 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1652 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1653 adev->gfx.rlc.rlcg_reg_access_supported = true; 1654 } 1655 1656 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1657 { 1658 const struct cs_section_def *cs_data; 1659 int r; 1660 1661 adev->gfx.rlc.cs_data = gfx9_cs_data; 1662 1663 cs_data = adev->gfx.rlc.cs_data; 1664 1665 if (cs_data) { 1666 /* init clear state block */ 1667 r = amdgpu_gfx_rlc_init_csb(adev); 1668 if (r) 1669 return r; 1670 } 1671 1672 if (adev->flags & AMD_IS_APU) { 1673 /* TODO: double check the cp_table_size for RV */ 1674 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1675 r = amdgpu_gfx_rlc_init_cpt(adev); 1676 if (r) 1677 return r; 1678 } 1679 1680 switch (adev->ip_versions[GC_HWIP][0]) { 1681 case IP_VERSION(9, 2, 2): 1682 case IP_VERSION(9, 1, 0): 1683 gfx_v9_0_init_lbpw(adev); 1684 break; 1685 case IP_VERSION(9, 4, 0): 1686 gfx_v9_4_init_lbpw(adev); 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 /* init spm vmid with 0xf */ 1693 if (adev->gfx.rlc.funcs->update_spm_vmid) 1694 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1695 1696 return 0; 1697 } 1698 1699 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1700 { 1701 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1702 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1703 } 1704 1705 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1706 { 1707 int r; 1708 u32 *hpd; 1709 const __le32 *fw_data; 1710 unsigned fw_size; 1711 u32 *fw; 1712 size_t mec_hpd_size; 1713 1714 const struct gfx_firmware_header_v1_0 *mec_hdr; 1715 1716 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1717 1718 /* take ownership of the relevant compute queues */ 1719 amdgpu_gfx_compute_queue_acquire(adev); 1720 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1721 if (mec_hpd_size) { 1722 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1723 AMDGPU_GEM_DOMAIN_VRAM | 1724 AMDGPU_GEM_DOMAIN_GTT, 1725 &adev->gfx.mec.hpd_eop_obj, 1726 &adev->gfx.mec.hpd_eop_gpu_addr, 1727 (void **)&hpd); 1728 if (r) { 1729 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1730 gfx_v9_0_mec_fini(adev); 1731 return r; 1732 } 1733 1734 memset(hpd, 0, mec_hpd_size); 1735 1736 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1737 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1738 } 1739 1740 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1741 1742 fw_data = (const __le32 *) 1743 (adev->gfx.mec_fw->data + 1744 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1745 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1746 1747 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1748 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1749 &adev->gfx.mec.mec_fw_obj, 1750 &adev->gfx.mec.mec_fw_gpu_addr, 1751 (void **)&fw); 1752 if (r) { 1753 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1754 gfx_v9_0_mec_fini(adev); 1755 return r; 1756 } 1757 1758 memcpy(fw, fw_data, fw_size); 1759 1760 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1761 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1762 1763 return 0; 1764 } 1765 1766 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1767 { 1768 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1769 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1770 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1771 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1772 (SQ_IND_INDEX__FORCE_READ_MASK)); 1773 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1774 } 1775 1776 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1777 uint32_t wave, uint32_t thread, 1778 uint32_t regno, uint32_t num, uint32_t *out) 1779 { 1780 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1781 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1782 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1783 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1784 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1785 (SQ_IND_INDEX__FORCE_READ_MASK) | 1786 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1787 while (num--) 1788 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1789 } 1790 1791 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1792 { 1793 /* type 1 wave data */ 1794 dst[(*no_fields)++] = 1; 1795 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1796 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1797 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1798 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1799 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1800 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1801 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1802 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1803 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1804 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1805 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1806 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1807 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1808 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1809 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1810 } 1811 1812 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1813 uint32_t wave, uint32_t start, 1814 uint32_t size, uint32_t *dst) 1815 { 1816 wave_read_regs( 1817 adev, simd, wave, 0, 1818 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1819 } 1820 1821 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 1822 uint32_t wave, uint32_t thread, 1823 uint32_t start, uint32_t size, 1824 uint32_t *dst) 1825 { 1826 wave_read_regs( 1827 adev, simd, wave, thread, 1828 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1829 } 1830 1831 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1832 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 1833 { 1834 soc15_grbm_select(adev, me, pipe, q, vm, 0); 1835 } 1836 1837 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1838 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1839 .select_se_sh = &gfx_v9_0_select_se_sh, 1840 .read_wave_data = &gfx_v9_0_read_wave_data, 1841 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1842 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1843 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1844 }; 1845 1846 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1847 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1848 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1849 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1850 }; 1851 1852 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1853 .ras_block = { 1854 .hw_ops = &gfx_v9_0_ras_ops, 1855 }, 1856 }; 1857 1858 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1859 { 1860 u32 gb_addr_config; 1861 int err; 1862 1863 switch (adev->ip_versions[GC_HWIP][0]) { 1864 case IP_VERSION(9, 0, 1): 1865 adev->gfx.config.max_hw_contexts = 8; 1866 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1867 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1868 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1869 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1870 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1871 break; 1872 case IP_VERSION(9, 2, 1): 1873 adev->gfx.config.max_hw_contexts = 8; 1874 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1875 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1876 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1877 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1878 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1879 DRM_INFO("fix gfx.config for vega12\n"); 1880 break; 1881 case IP_VERSION(9, 4, 0): 1882 adev->gfx.ras = &gfx_v9_0_ras; 1883 adev->gfx.config.max_hw_contexts = 8; 1884 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1885 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1886 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1887 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1888 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1889 gb_addr_config &= ~0xf3e777ff; 1890 gb_addr_config |= 0x22014042; 1891 /* check vbios table if gpu info is not available */ 1892 err = amdgpu_atomfirmware_get_gfx_info(adev); 1893 if (err) 1894 return err; 1895 break; 1896 case IP_VERSION(9, 2, 2): 1897 case IP_VERSION(9, 1, 0): 1898 adev->gfx.config.max_hw_contexts = 8; 1899 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1900 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1901 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1902 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1903 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1904 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1905 else 1906 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1907 break; 1908 case IP_VERSION(9, 4, 1): 1909 adev->gfx.ras = &gfx_v9_4_ras; 1910 adev->gfx.config.max_hw_contexts = 8; 1911 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1912 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1913 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1914 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1915 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1916 gb_addr_config &= ~0xf3e777ff; 1917 gb_addr_config |= 0x22014042; 1918 break; 1919 case IP_VERSION(9, 3, 0): 1920 adev->gfx.config.max_hw_contexts = 8; 1921 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1922 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1923 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1924 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1925 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1926 gb_addr_config &= ~0xf3e777ff; 1927 gb_addr_config |= 0x22010042; 1928 break; 1929 case IP_VERSION(9, 4, 2): 1930 adev->gfx.ras = &gfx_v9_4_2_ras; 1931 adev->gfx.config.max_hw_contexts = 8; 1932 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1933 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1934 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1935 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1936 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1937 gb_addr_config &= ~0xf3e777ff; 1938 gb_addr_config |= 0x22014042; 1939 /* check vbios table if gpu info is not available */ 1940 err = amdgpu_atomfirmware_get_gfx_info(adev); 1941 if (err) 1942 return err; 1943 break; 1944 default: 1945 BUG(); 1946 break; 1947 } 1948 1949 adev->gfx.config.gb_addr_config = gb_addr_config; 1950 1951 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1952 REG_GET_FIELD( 1953 adev->gfx.config.gb_addr_config, 1954 GB_ADDR_CONFIG, 1955 NUM_PIPES); 1956 1957 adev->gfx.config.max_tile_pipes = 1958 adev->gfx.config.gb_addr_config_fields.num_pipes; 1959 1960 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1961 REG_GET_FIELD( 1962 adev->gfx.config.gb_addr_config, 1963 GB_ADDR_CONFIG, 1964 NUM_BANKS); 1965 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1966 REG_GET_FIELD( 1967 adev->gfx.config.gb_addr_config, 1968 GB_ADDR_CONFIG, 1969 MAX_COMPRESSED_FRAGS); 1970 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1971 REG_GET_FIELD( 1972 adev->gfx.config.gb_addr_config, 1973 GB_ADDR_CONFIG, 1974 NUM_RB_PER_SE); 1975 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1976 REG_GET_FIELD( 1977 adev->gfx.config.gb_addr_config, 1978 GB_ADDR_CONFIG, 1979 NUM_SHADER_ENGINES); 1980 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1981 REG_GET_FIELD( 1982 adev->gfx.config.gb_addr_config, 1983 GB_ADDR_CONFIG, 1984 PIPE_INTERLEAVE_SIZE)); 1985 1986 return 0; 1987 } 1988 1989 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1990 int mec, int pipe, int queue) 1991 { 1992 unsigned irq_type; 1993 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1994 unsigned int hw_prio; 1995 1996 ring = &adev->gfx.compute_ring[ring_id]; 1997 1998 /* mec0 is me1 */ 1999 ring->me = mec + 1; 2000 ring->pipe = pipe; 2001 ring->queue = queue; 2002 2003 ring->ring_obj = NULL; 2004 ring->use_doorbell = true; 2005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2007 + (ring_id * GFX9_MEC_HPD_SIZE); 2008 ring->vm_hub = AMDGPU_GFXHUB(0); 2009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2010 2011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2013 + ring->pipe; 2014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2015 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2017 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2018 hw_prio, NULL); 2019 } 2020 2021 static int gfx_v9_0_sw_init(void *handle) 2022 { 2023 int i, j, k, r, ring_id; 2024 struct amdgpu_ring *ring; 2025 struct amdgpu_kiq *kiq; 2026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2027 unsigned int hw_prio; 2028 2029 switch (adev->ip_versions[GC_HWIP][0]) { 2030 case IP_VERSION(9, 0, 1): 2031 case IP_VERSION(9, 2, 1): 2032 case IP_VERSION(9, 4, 0): 2033 case IP_VERSION(9, 2, 2): 2034 case IP_VERSION(9, 1, 0): 2035 case IP_VERSION(9, 4, 1): 2036 case IP_VERSION(9, 3, 0): 2037 case IP_VERSION(9, 4, 2): 2038 adev->gfx.mec.num_mec = 2; 2039 break; 2040 default: 2041 adev->gfx.mec.num_mec = 1; 2042 break; 2043 } 2044 2045 adev->gfx.mec.num_pipe_per_mec = 4; 2046 adev->gfx.mec.num_queue_per_pipe = 8; 2047 2048 /* EOP Event */ 2049 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2050 if (r) 2051 return r; 2052 2053 /* Privileged reg */ 2054 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2055 &adev->gfx.priv_reg_irq); 2056 if (r) 2057 return r; 2058 2059 /* Privileged inst */ 2060 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2061 &adev->gfx.priv_inst_irq); 2062 if (r) 2063 return r; 2064 2065 /* ECC error */ 2066 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2067 &adev->gfx.cp_ecc_error_irq); 2068 if (r) 2069 return r; 2070 2071 /* FUE error */ 2072 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2073 &adev->gfx.cp_ecc_error_irq); 2074 if (r) 2075 return r; 2076 2077 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2078 2079 if (adev->gfx.rlc.funcs) { 2080 if (adev->gfx.rlc.funcs->init) { 2081 r = adev->gfx.rlc.funcs->init(adev); 2082 if (r) { 2083 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2084 return r; 2085 } 2086 } 2087 } 2088 2089 r = gfx_v9_0_mec_init(adev); 2090 if (r) { 2091 DRM_ERROR("Failed to init MEC BOs!\n"); 2092 return r; 2093 } 2094 2095 /* set up the gfx ring */ 2096 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2097 ring = &adev->gfx.gfx_ring[i]; 2098 ring->ring_obj = NULL; 2099 if (!i) 2100 sprintf(ring->name, "gfx"); 2101 else 2102 sprintf(ring->name, "gfx_%d", i); 2103 ring->use_doorbell = true; 2104 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2105 2106 /* disable scheduler on the real ring */ 2107 ring->no_scheduler = true; 2108 ring->vm_hub = AMDGPU_GFXHUB(0); 2109 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2110 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2111 AMDGPU_RING_PRIO_DEFAULT, NULL); 2112 if (r) 2113 return r; 2114 } 2115 2116 /* set up the software rings */ 2117 if (adev->gfx.num_gfx_rings) { 2118 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2119 ring = &adev->gfx.sw_gfx_ring[i]; 2120 ring->ring_obj = NULL; 2121 sprintf(ring->name, amdgpu_sw_ring_name(i)); 2122 ring->use_doorbell = true; 2123 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2124 ring->is_sw_ring = true; 2125 hw_prio = amdgpu_sw_ring_priority(i); 2126 ring->vm_hub = AMDGPU_GFXHUB(0); 2127 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2128 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, 2129 NULL); 2130 if (r) 2131 return r; 2132 ring->wptr = 0; 2133 } 2134 2135 /* init the muxer and add software rings */ 2136 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], 2137 GFX9_NUM_SW_GFX_RINGS); 2138 if (r) { 2139 DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); 2140 return r; 2141 } 2142 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2143 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, 2144 &adev->gfx.sw_gfx_ring[i]); 2145 if (r) { 2146 DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); 2147 return r; 2148 } 2149 } 2150 } 2151 2152 /* set up the compute queues - allocate horizontally across pipes */ 2153 ring_id = 0; 2154 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2155 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2156 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2157 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 2158 k, j)) 2159 continue; 2160 2161 r = gfx_v9_0_compute_ring_init(adev, 2162 ring_id, 2163 i, k, j); 2164 if (r) 2165 return r; 2166 2167 ring_id++; 2168 } 2169 } 2170 } 2171 2172 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); 2173 if (r) { 2174 DRM_ERROR("Failed to init KIQ BOs!\n"); 2175 return r; 2176 } 2177 2178 kiq = &adev->gfx.kiq[0]; 2179 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); 2180 if (r) 2181 return r; 2182 2183 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2184 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0); 2185 if (r) 2186 return r; 2187 2188 adev->gfx.ce_ram_size = 0x8000; 2189 2190 r = gfx_v9_0_gpu_early_init(adev); 2191 if (r) 2192 return r; 2193 2194 if (amdgpu_gfx_ras_sw_init(adev)) { 2195 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 2196 return -EINVAL; 2197 } 2198 2199 return 0; 2200 } 2201 2202 2203 static int gfx_v9_0_sw_fini(void *handle) 2204 { 2205 int i; 2206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2207 2208 if (adev->gfx.num_gfx_rings) { 2209 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 2210 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); 2211 amdgpu_ring_mux_fini(&adev->gfx.muxer); 2212 } 2213 2214 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2215 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2216 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2217 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2218 2219 amdgpu_gfx_mqd_sw_fini(adev, 0); 2220 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); 2221 amdgpu_gfx_kiq_fini(adev, 0); 2222 2223 gfx_v9_0_mec_fini(adev); 2224 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2225 &adev->gfx.rlc.clear_state_gpu_addr, 2226 (void **)&adev->gfx.rlc.cs_ptr); 2227 if (adev->flags & AMD_IS_APU) { 2228 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2229 &adev->gfx.rlc.cp_table_gpu_addr, 2230 (void **)&adev->gfx.rlc.cp_table_ptr); 2231 } 2232 gfx_v9_0_free_microcode(adev); 2233 2234 return 0; 2235 } 2236 2237 2238 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2239 { 2240 /* TODO */ 2241 } 2242 2243 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2244 u32 instance, int xcc_id) 2245 { 2246 u32 data; 2247 2248 if (instance == 0xffffffff) 2249 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2250 else 2251 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2252 2253 if (se_num == 0xffffffff) 2254 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2255 else 2256 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2257 2258 if (sh_num == 0xffffffff) 2259 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2260 else 2261 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2262 2263 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2264 } 2265 2266 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2267 { 2268 u32 data, mask; 2269 2270 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2271 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2272 2273 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2274 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2275 2276 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2277 adev->gfx.config.max_sh_per_se); 2278 2279 return (~data) & mask; 2280 } 2281 2282 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2283 { 2284 int i, j; 2285 u32 data; 2286 u32 active_rbs = 0; 2287 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2288 adev->gfx.config.max_sh_per_se; 2289 2290 mutex_lock(&adev->grbm_idx_mutex); 2291 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2292 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2293 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2294 data = gfx_v9_0_get_rb_active_bitmap(adev); 2295 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2296 rb_bitmap_width_per_sh); 2297 } 2298 } 2299 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2300 mutex_unlock(&adev->grbm_idx_mutex); 2301 2302 adev->gfx.config.backend_enable_mask = active_rbs; 2303 adev->gfx.config.num_rbs = hweight32(active_rbs); 2304 } 2305 2306 #define DEFAULT_SH_MEM_BASES (0x6000) 2307 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2308 { 2309 int i; 2310 uint32_t sh_mem_config; 2311 uint32_t sh_mem_bases; 2312 2313 /* 2314 * Configure apertures: 2315 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2316 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2317 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2318 */ 2319 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2320 2321 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2322 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2323 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2324 2325 mutex_lock(&adev->srbm_mutex); 2326 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2327 soc15_grbm_select(adev, 0, 0, 0, i, 0); 2328 /* CP and shaders */ 2329 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2330 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2331 } 2332 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2333 mutex_unlock(&adev->srbm_mutex); 2334 2335 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2336 access. These should be enabled by FW for target VMIDs. */ 2337 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2338 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2339 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2340 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2341 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2342 } 2343 } 2344 2345 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2346 { 2347 int vmid; 2348 2349 /* 2350 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2351 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2352 * the driver can enable them for graphics. VMID0 should maintain 2353 * access so that HWS firmware can save/restore entries. 2354 */ 2355 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2356 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2357 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2358 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2359 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2360 } 2361 } 2362 2363 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2364 { 2365 uint32_t tmp; 2366 2367 switch (adev->ip_versions[GC_HWIP][0]) { 2368 case IP_VERSION(9, 4, 1): 2369 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2370 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2371 DISABLE_BARRIER_WAITCNT, 1); 2372 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2373 break; 2374 default: 2375 break; 2376 } 2377 } 2378 2379 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2380 { 2381 u32 tmp; 2382 int i; 2383 2384 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2385 2386 gfx_v9_0_tiling_mode_table_init(adev); 2387 2388 if (adev->gfx.num_gfx_rings) 2389 gfx_v9_0_setup_rb(adev); 2390 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2391 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2392 2393 /* XXX SH_MEM regs */ 2394 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2395 mutex_lock(&adev->srbm_mutex); 2396 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 2397 soc15_grbm_select(adev, 0, 0, 0, i, 0); 2398 /* CP and shaders */ 2399 if (i == 0) { 2400 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2401 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2402 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2403 !!adev->gmc.noretry); 2404 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2405 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2406 } else { 2407 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2408 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2409 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2410 !!adev->gmc.noretry); 2411 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2412 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2413 (adev->gmc.private_aperture_start >> 48)); 2414 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2415 (adev->gmc.shared_aperture_start >> 48)); 2416 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2417 } 2418 } 2419 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 2420 2421 mutex_unlock(&adev->srbm_mutex); 2422 2423 gfx_v9_0_init_compute_vmid(adev); 2424 gfx_v9_0_init_gds_vmid(adev); 2425 gfx_v9_0_init_sq_config(adev); 2426 } 2427 2428 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2429 { 2430 u32 i, j, k; 2431 u32 mask; 2432 2433 mutex_lock(&adev->grbm_idx_mutex); 2434 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2435 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2436 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2437 for (k = 0; k < adev->usec_timeout; k++) { 2438 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2439 break; 2440 udelay(1); 2441 } 2442 if (k == adev->usec_timeout) { 2443 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2444 0xffffffff, 0xffffffff, 0); 2445 mutex_unlock(&adev->grbm_idx_mutex); 2446 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2447 i, j); 2448 return; 2449 } 2450 } 2451 } 2452 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2453 mutex_unlock(&adev->grbm_idx_mutex); 2454 2455 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2456 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2457 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2458 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2459 for (k = 0; k < adev->usec_timeout; k++) { 2460 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2461 break; 2462 udelay(1); 2463 } 2464 } 2465 2466 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2467 bool enable) 2468 { 2469 u32 tmp; 2470 2471 /* These interrupts should be enabled to drive DS clock */ 2472 2473 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2474 2475 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2476 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2477 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2478 if(adev->gfx.num_gfx_rings) 2479 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2480 2481 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2482 } 2483 2484 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2485 { 2486 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2487 /* csib */ 2488 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2489 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2490 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2491 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2492 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2493 adev->gfx.rlc.clear_state_size); 2494 } 2495 2496 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2497 int indirect_offset, 2498 int list_size, 2499 int *unique_indirect_regs, 2500 int unique_indirect_reg_count, 2501 int *indirect_start_offsets, 2502 int *indirect_start_offsets_count, 2503 int max_start_offsets_count) 2504 { 2505 int idx; 2506 2507 for (; indirect_offset < list_size; indirect_offset++) { 2508 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2509 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2510 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2511 2512 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2513 indirect_offset += 2; 2514 2515 /* look for the matching indice */ 2516 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2517 if (unique_indirect_regs[idx] == 2518 register_list_format[indirect_offset] || 2519 !unique_indirect_regs[idx]) 2520 break; 2521 } 2522 2523 BUG_ON(idx >= unique_indirect_reg_count); 2524 2525 if (!unique_indirect_regs[idx]) 2526 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2527 2528 indirect_offset++; 2529 } 2530 } 2531 } 2532 2533 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2534 { 2535 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2536 int unique_indirect_reg_count = 0; 2537 2538 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2539 int indirect_start_offsets_count = 0; 2540 2541 int list_size = 0; 2542 int i = 0, j = 0; 2543 u32 tmp = 0; 2544 2545 u32 *register_list_format = 2546 kmemdup(adev->gfx.rlc.register_list_format, 2547 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2548 if (!register_list_format) 2549 return -ENOMEM; 2550 2551 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2552 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2553 gfx_v9_1_parse_ind_reg_list(register_list_format, 2554 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2555 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2556 unique_indirect_regs, 2557 unique_indirect_reg_count, 2558 indirect_start_offsets, 2559 &indirect_start_offsets_count, 2560 ARRAY_SIZE(indirect_start_offsets)); 2561 2562 /* enable auto inc in case it is disabled */ 2563 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2564 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2565 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2566 2567 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2568 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2569 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2570 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2571 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2572 adev->gfx.rlc.register_restore[i]); 2573 2574 /* load indirect register */ 2575 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2576 adev->gfx.rlc.reg_list_format_start); 2577 2578 /* direct register portion */ 2579 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2580 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2581 register_list_format[i]); 2582 2583 /* indirect register portion */ 2584 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2585 if (register_list_format[i] == 0xFFFFFFFF) { 2586 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2587 continue; 2588 } 2589 2590 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2591 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2592 2593 for (j = 0; j < unique_indirect_reg_count; j++) { 2594 if (register_list_format[i] == unique_indirect_regs[j]) { 2595 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2596 break; 2597 } 2598 } 2599 2600 BUG_ON(j >= unique_indirect_reg_count); 2601 2602 i++; 2603 } 2604 2605 /* set save/restore list size */ 2606 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2607 list_size = list_size >> 1; 2608 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2609 adev->gfx.rlc.reg_restore_list_size); 2610 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2611 2612 /* write the starting offsets to RLC scratch ram */ 2613 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2614 adev->gfx.rlc.starting_offsets_start); 2615 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2616 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2617 indirect_start_offsets[i]); 2618 2619 /* load unique indirect regs*/ 2620 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2621 if (unique_indirect_regs[i] != 0) { 2622 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2623 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2624 unique_indirect_regs[i] & 0x3FFFF); 2625 2626 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2627 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2628 unique_indirect_regs[i] >> 20); 2629 } 2630 } 2631 2632 kfree(register_list_format); 2633 return 0; 2634 } 2635 2636 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2637 { 2638 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2639 } 2640 2641 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2642 bool enable) 2643 { 2644 uint32_t data = 0; 2645 uint32_t default_data = 0; 2646 2647 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2648 if (enable) { 2649 /* enable GFXIP control over CGPG */ 2650 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2651 if(default_data != data) 2652 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2653 2654 /* update status */ 2655 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2656 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2657 if(default_data != data) 2658 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2659 } else { 2660 /* restore GFXIP control over GCPG */ 2661 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2662 if(default_data != data) 2663 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2664 } 2665 } 2666 2667 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2668 { 2669 uint32_t data = 0; 2670 2671 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2672 AMD_PG_SUPPORT_GFX_SMG | 2673 AMD_PG_SUPPORT_GFX_DMG)) { 2674 /* init IDLE_POLL_COUNT = 60 */ 2675 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2676 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2677 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2678 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2679 2680 /* init RLC PG Delay */ 2681 data = 0; 2682 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2683 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2684 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2685 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2686 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2687 2688 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2689 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2690 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2691 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2692 2693 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2694 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2695 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2696 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2697 2698 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2699 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2700 2701 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2702 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2703 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2704 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) 2705 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2706 } 2707 } 2708 2709 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2710 bool enable) 2711 { 2712 uint32_t data = 0; 2713 uint32_t default_data = 0; 2714 2715 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2716 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2717 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2718 enable ? 1 : 0); 2719 if (default_data != data) 2720 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2721 } 2722 2723 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2724 bool enable) 2725 { 2726 uint32_t data = 0; 2727 uint32_t default_data = 0; 2728 2729 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2730 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2731 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2732 enable ? 1 : 0); 2733 if(default_data != data) 2734 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2735 } 2736 2737 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2738 bool enable) 2739 { 2740 uint32_t data = 0; 2741 uint32_t default_data = 0; 2742 2743 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2744 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2745 CP_PG_DISABLE, 2746 enable ? 0 : 1); 2747 if(default_data != data) 2748 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2749 } 2750 2751 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2752 bool enable) 2753 { 2754 uint32_t data, default_data; 2755 2756 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2757 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2758 GFX_POWER_GATING_ENABLE, 2759 enable ? 1 : 0); 2760 if(default_data != data) 2761 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2762 } 2763 2764 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2765 bool enable) 2766 { 2767 uint32_t data, default_data; 2768 2769 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2770 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2771 GFX_PIPELINE_PG_ENABLE, 2772 enable ? 1 : 0); 2773 if(default_data != data) 2774 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2775 2776 if (!enable) 2777 /* read any GFX register to wake up GFX */ 2778 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2779 } 2780 2781 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2782 bool enable) 2783 { 2784 uint32_t data, default_data; 2785 2786 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2787 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2788 STATIC_PER_CU_PG_ENABLE, 2789 enable ? 1 : 0); 2790 if(default_data != data) 2791 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2792 } 2793 2794 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2795 bool enable) 2796 { 2797 uint32_t data, default_data; 2798 2799 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2800 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2801 DYN_PER_CU_PG_ENABLE, 2802 enable ? 1 : 0); 2803 if(default_data != data) 2804 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2805 } 2806 2807 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2808 { 2809 gfx_v9_0_init_csb(adev); 2810 2811 /* 2812 * Rlc save restore list is workable since v2_1. 2813 * And it's needed by gfxoff feature. 2814 */ 2815 if (adev->gfx.rlc.is_rlc_v2_1) { 2816 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || 2817 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2818 gfx_v9_1_init_rlc_save_restore_list(adev); 2819 gfx_v9_0_enable_save_restore_machine(adev); 2820 } 2821 2822 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2823 AMD_PG_SUPPORT_GFX_SMG | 2824 AMD_PG_SUPPORT_GFX_DMG | 2825 AMD_PG_SUPPORT_CP | 2826 AMD_PG_SUPPORT_GDS | 2827 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2828 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2829 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2830 gfx_v9_0_init_gfx_power_gating(adev); 2831 } 2832 } 2833 2834 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2835 { 2836 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2837 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2838 gfx_v9_0_wait_for_rlc_serdes(adev); 2839 } 2840 2841 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2842 { 2843 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2844 udelay(50); 2845 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2846 udelay(50); 2847 } 2848 2849 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2850 { 2851 #ifdef AMDGPU_RLC_DEBUG_RETRY 2852 u32 rlc_ucode_ver; 2853 #endif 2854 2855 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2856 udelay(50); 2857 2858 /* carrizo do enable cp interrupt after cp inited */ 2859 if (!(adev->flags & AMD_IS_APU)) { 2860 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2861 udelay(50); 2862 } 2863 2864 #ifdef AMDGPU_RLC_DEBUG_RETRY 2865 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2866 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2867 if(rlc_ucode_ver == 0x108) { 2868 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2869 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2870 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2871 * default is 0x9C4 to create a 100us interval */ 2872 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2873 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2874 * to disable the page fault retry interrupts, default is 2875 * 0x100 (256) */ 2876 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2877 } 2878 #endif 2879 } 2880 2881 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2882 { 2883 const struct rlc_firmware_header_v2_0 *hdr; 2884 const __le32 *fw_data; 2885 unsigned i, fw_size; 2886 2887 if (!adev->gfx.rlc_fw) 2888 return -EINVAL; 2889 2890 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2891 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2892 2893 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2894 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2895 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2896 2897 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2898 RLCG_UCODE_LOADING_START_ADDRESS); 2899 for (i = 0; i < fw_size; i++) 2900 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2901 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2902 2903 return 0; 2904 } 2905 2906 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2907 { 2908 int r; 2909 2910 if (amdgpu_sriov_vf(adev)) { 2911 gfx_v9_0_init_csb(adev); 2912 return 0; 2913 } 2914 2915 adev->gfx.rlc.funcs->stop(adev); 2916 2917 /* disable CG */ 2918 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2919 2920 gfx_v9_0_init_pg(adev); 2921 2922 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2923 /* legacy rlc firmware loading */ 2924 r = gfx_v9_0_rlc_load_microcode(adev); 2925 if (r) 2926 return r; 2927 } 2928 2929 switch (adev->ip_versions[GC_HWIP][0]) { 2930 case IP_VERSION(9, 2, 2): 2931 case IP_VERSION(9, 1, 0): 2932 if (amdgpu_lbpw == 0) 2933 gfx_v9_0_enable_lbpw(adev, false); 2934 else 2935 gfx_v9_0_enable_lbpw(adev, true); 2936 break; 2937 case IP_VERSION(9, 4, 0): 2938 if (amdgpu_lbpw > 0) 2939 gfx_v9_0_enable_lbpw(adev, true); 2940 else 2941 gfx_v9_0_enable_lbpw(adev, false); 2942 break; 2943 default: 2944 break; 2945 } 2946 2947 adev->gfx.rlc.funcs->start(adev); 2948 2949 return 0; 2950 } 2951 2952 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2953 { 2954 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2955 2956 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2957 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2958 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2959 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2960 udelay(50); 2961 } 2962 2963 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2964 { 2965 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2966 const struct gfx_firmware_header_v1_0 *ce_hdr; 2967 const struct gfx_firmware_header_v1_0 *me_hdr; 2968 const __le32 *fw_data; 2969 unsigned i, fw_size; 2970 2971 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2972 return -EINVAL; 2973 2974 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2975 adev->gfx.pfp_fw->data; 2976 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2977 adev->gfx.ce_fw->data; 2978 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2979 adev->gfx.me_fw->data; 2980 2981 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2982 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2983 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2984 2985 gfx_v9_0_cp_gfx_enable(adev, false); 2986 2987 /* PFP */ 2988 fw_data = (const __le32 *) 2989 (adev->gfx.pfp_fw->data + 2990 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2991 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2992 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2993 for (i = 0; i < fw_size; i++) 2994 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2995 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2996 2997 /* CE */ 2998 fw_data = (const __le32 *) 2999 (adev->gfx.ce_fw->data + 3000 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3001 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3002 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3003 for (i = 0; i < fw_size; i++) 3004 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3005 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3006 3007 /* ME */ 3008 fw_data = (const __le32 *) 3009 (adev->gfx.me_fw->data + 3010 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3011 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3012 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3013 for (i = 0; i < fw_size; i++) 3014 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3015 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3016 3017 return 0; 3018 } 3019 3020 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3021 { 3022 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3023 const struct cs_section_def *sect = NULL; 3024 const struct cs_extent_def *ext = NULL; 3025 int r, i, tmp; 3026 3027 /* init the CP */ 3028 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3029 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3030 3031 gfx_v9_0_cp_gfx_enable(adev, true); 3032 3033 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3034 if (r) { 3035 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3036 return r; 3037 } 3038 3039 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3040 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3041 3042 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3043 amdgpu_ring_write(ring, 0x80000000); 3044 amdgpu_ring_write(ring, 0x80000000); 3045 3046 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3047 for (ext = sect->section; ext->extent != NULL; ++ext) { 3048 if (sect->id == SECT_CONTEXT) { 3049 amdgpu_ring_write(ring, 3050 PACKET3(PACKET3_SET_CONTEXT_REG, 3051 ext->reg_count)); 3052 amdgpu_ring_write(ring, 3053 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3054 for (i = 0; i < ext->reg_count; i++) 3055 amdgpu_ring_write(ring, ext->extent[i]); 3056 } 3057 } 3058 } 3059 3060 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3061 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3062 3063 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3064 amdgpu_ring_write(ring, 0); 3065 3066 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3067 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3068 amdgpu_ring_write(ring, 0x8000); 3069 amdgpu_ring_write(ring, 0x8000); 3070 3071 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3072 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3073 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3074 amdgpu_ring_write(ring, tmp); 3075 amdgpu_ring_write(ring, 0); 3076 3077 amdgpu_ring_commit(ring); 3078 3079 return 0; 3080 } 3081 3082 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3083 { 3084 struct amdgpu_ring *ring; 3085 u32 tmp; 3086 u32 rb_bufsz; 3087 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3088 3089 /* Set the write pointer delay */ 3090 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3091 3092 /* set the RB to use vmid 0 */ 3093 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3094 3095 /* Set ring buffer size */ 3096 ring = &adev->gfx.gfx_ring[0]; 3097 rb_bufsz = order_base_2(ring->ring_size / 8); 3098 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3099 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3100 #ifdef __BIG_ENDIAN 3101 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3102 #endif 3103 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3104 3105 /* Initialize the ring buffer's write pointers */ 3106 ring->wptr = 0; 3107 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3108 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3109 3110 /* set the wb address wether it's enabled or not */ 3111 rptr_addr = ring->rptr_gpu_addr; 3112 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3113 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3114 3115 wptr_gpu_addr = ring->wptr_gpu_addr; 3116 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3117 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3118 3119 mdelay(1); 3120 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3121 3122 rb_addr = ring->gpu_addr >> 8; 3123 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3124 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3125 3126 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3127 if (ring->use_doorbell) { 3128 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3129 DOORBELL_OFFSET, ring->doorbell_index); 3130 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3131 DOORBELL_EN, 1); 3132 } else { 3133 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3134 } 3135 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3136 3137 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3138 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3139 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3140 3141 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3142 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3143 3144 3145 /* start the ring */ 3146 gfx_v9_0_cp_gfx_start(adev); 3147 ring->sched.ready = true; 3148 3149 return 0; 3150 } 3151 3152 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3153 { 3154 if (enable) { 3155 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3156 } else { 3157 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3158 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3159 adev->gfx.kiq[0].ring.sched.ready = false; 3160 } 3161 udelay(50); 3162 } 3163 3164 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3165 { 3166 const struct gfx_firmware_header_v1_0 *mec_hdr; 3167 const __le32 *fw_data; 3168 unsigned i; 3169 u32 tmp; 3170 3171 if (!adev->gfx.mec_fw) 3172 return -EINVAL; 3173 3174 gfx_v9_0_cp_compute_enable(adev, false); 3175 3176 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3177 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3178 3179 fw_data = (const __le32 *) 3180 (adev->gfx.mec_fw->data + 3181 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3182 tmp = 0; 3183 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3184 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3185 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3186 3187 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3188 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3189 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3190 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3191 3192 /* MEC1 */ 3193 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3194 mec_hdr->jt_offset); 3195 for (i = 0; i < mec_hdr->jt_size; i++) 3196 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3197 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3198 3199 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3200 adev->gfx.mec_fw_version); 3201 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3202 3203 return 0; 3204 } 3205 3206 /* KIQ functions */ 3207 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3208 { 3209 uint32_t tmp; 3210 struct amdgpu_device *adev = ring->adev; 3211 3212 /* tell RLC which is KIQ queue */ 3213 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3214 tmp &= 0xffffff00; 3215 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3216 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3217 tmp |= 0x80; 3218 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3219 } 3220 3221 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3222 { 3223 struct amdgpu_device *adev = ring->adev; 3224 3225 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3226 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3227 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3228 mqd->cp_hqd_queue_priority = 3229 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3230 } 3231 } 3232 } 3233 3234 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3235 { 3236 struct amdgpu_device *adev = ring->adev; 3237 struct v9_mqd *mqd = ring->mqd_ptr; 3238 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3239 uint32_t tmp; 3240 3241 mqd->header = 0xC0310800; 3242 mqd->compute_pipelinestat_enable = 0x00000001; 3243 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3244 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3245 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3246 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3247 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3248 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3249 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3250 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3251 mqd->compute_misc_reserved = 0x00000003; 3252 3253 mqd->dynamic_cu_mask_addr_lo = 3254 lower_32_bits(ring->mqd_gpu_addr 3255 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3256 mqd->dynamic_cu_mask_addr_hi = 3257 upper_32_bits(ring->mqd_gpu_addr 3258 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3259 3260 eop_base_addr = ring->eop_gpu_addr >> 8; 3261 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3262 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3263 3264 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3265 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3266 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3267 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3268 3269 mqd->cp_hqd_eop_control = tmp; 3270 3271 /* enable doorbell? */ 3272 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3273 3274 if (ring->use_doorbell) { 3275 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3276 DOORBELL_OFFSET, ring->doorbell_index); 3277 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3278 DOORBELL_EN, 1); 3279 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3280 DOORBELL_SOURCE, 0); 3281 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3282 DOORBELL_HIT, 0); 3283 } else { 3284 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3285 DOORBELL_EN, 0); 3286 } 3287 3288 mqd->cp_hqd_pq_doorbell_control = tmp; 3289 3290 /* disable the queue if it's active */ 3291 ring->wptr = 0; 3292 mqd->cp_hqd_dequeue_request = 0; 3293 mqd->cp_hqd_pq_rptr = 0; 3294 mqd->cp_hqd_pq_wptr_lo = 0; 3295 mqd->cp_hqd_pq_wptr_hi = 0; 3296 3297 /* set the pointer to the MQD */ 3298 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3299 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3300 3301 /* set MQD vmid to 0 */ 3302 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3303 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3304 mqd->cp_mqd_control = tmp; 3305 3306 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3307 hqd_gpu_addr = ring->gpu_addr >> 8; 3308 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3309 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3310 3311 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3312 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3313 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3314 (order_base_2(ring->ring_size / 4) - 1)); 3315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3316 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3317 #ifdef __BIG_ENDIAN 3318 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3319 #endif 3320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3323 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3324 mqd->cp_hqd_pq_control = tmp; 3325 3326 /* set the wb address whether it's enabled or not */ 3327 wb_gpu_addr = ring->rptr_gpu_addr; 3328 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3329 mqd->cp_hqd_pq_rptr_report_addr_hi = 3330 upper_32_bits(wb_gpu_addr) & 0xffff; 3331 3332 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3333 wb_gpu_addr = ring->wptr_gpu_addr; 3334 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3335 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3336 3337 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3338 ring->wptr = 0; 3339 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3340 3341 /* set the vmid for the queue */ 3342 mqd->cp_hqd_vmid = 0; 3343 3344 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3345 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3346 mqd->cp_hqd_persistent_state = tmp; 3347 3348 /* set MIN_IB_AVAIL_SIZE */ 3349 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3350 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3351 mqd->cp_hqd_ib_control = tmp; 3352 3353 /* set static priority for a queue/ring */ 3354 gfx_v9_0_mqd_set_priority(ring, mqd); 3355 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3356 3357 /* map_queues packet doesn't need activate the queue, 3358 * so only kiq need set this field. 3359 */ 3360 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3361 mqd->cp_hqd_active = 1; 3362 3363 return 0; 3364 } 3365 3366 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3367 { 3368 struct amdgpu_device *adev = ring->adev; 3369 struct v9_mqd *mqd = ring->mqd_ptr; 3370 int j; 3371 3372 /* disable wptr polling */ 3373 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3374 3375 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3376 mqd->cp_hqd_eop_base_addr_lo); 3377 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3378 mqd->cp_hqd_eop_base_addr_hi); 3379 3380 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3381 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3382 mqd->cp_hqd_eop_control); 3383 3384 /* enable doorbell? */ 3385 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3386 mqd->cp_hqd_pq_doorbell_control); 3387 3388 /* disable the queue if it's active */ 3389 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3390 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3391 for (j = 0; j < adev->usec_timeout; j++) { 3392 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3393 break; 3394 udelay(1); 3395 } 3396 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3397 mqd->cp_hqd_dequeue_request); 3398 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3399 mqd->cp_hqd_pq_rptr); 3400 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3401 mqd->cp_hqd_pq_wptr_lo); 3402 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3403 mqd->cp_hqd_pq_wptr_hi); 3404 } 3405 3406 /* set the pointer to the MQD */ 3407 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3408 mqd->cp_mqd_base_addr_lo); 3409 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3410 mqd->cp_mqd_base_addr_hi); 3411 3412 /* set MQD vmid to 0 */ 3413 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3414 mqd->cp_mqd_control); 3415 3416 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3417 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3418 mqd->cp_hqd_pq_base_lo); 3419 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3420 mqd->cp_hqd_pq_base_hi); 3421 3422 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3423 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3424 mqd->cp_hqd_pq_control); 3425 3426 /* set the wb address whether it's enabled or not */ 3427 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3428 mqd->cp_hqd_pq_rptr_report_addr_lo); 3429 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3430 mqd->cp_hqd_pq_rptr_report_addr_hi); 3431 3432 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3433 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3434 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3435 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3436 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3437 3438 /* enable the doorbell if requested */ 3439 if (ring->use_doorbell) { 3440 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3441 (adev->doorbell_index.kiq * 2) << 2); 3442 /* If GC has entered CGPG, ringing doorbell > first page 3443 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3444 * workaround this issue. And this change has to align with firmware 3445 * update. 3446 */ 3447 if (check_if_enlarge_doorbell_range(adev)) 3448 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3449 (adev->doorbell.size - 4)); 3450 else 3451 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3452 (adev->doorbell_index.userqueue_end * 2) << 2); 3453 } 3454 3455 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3456 mqd->cp_hqd_pq_doorbell_control); 3457 3458 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3459 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3460 mqd->cp_hqd_pq_wptr_lo); 3461 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3462 mqd->cp_hqd_pq_wptr_hi); 3463 3464 /* set the vmid for the queue */ 3465 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3466 3467 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3468 mqd->cp_hqd_persistent_state); 3469 3470 /* activate the queue */ 3471 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3472 mqd->cp_hqd_active); 3473 3474 if (ring->use_doorbell) 3475 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3476 3477 return 0; 3478 } 3479 3480 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3481 { 3482 struct amdgpu_device *adev = ring->adev; 3483 int j; 3484 3485 /* disable the queue if it's active */ 3486 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3487 3488 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3489 3490 for (j = 0; j < adev->usec_timeout; j++) { 3491 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3492 break; 3493 udelay(1); 3494 } 3495 3496 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3497 DRM_DEBUG("KIQ dequeue request failed.\n"); 3498 3499 /* Manual disable if dequeue request times out */ 3500 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3501 } 3502 3503 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3504 0); 3505 } 3506 3507 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3508 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3509 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3510 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3511 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3512 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3513 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3514 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3515 3516 return 0; 3517 } 3518 3519 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3520 { 3521 struct amdgpu_device *adev = ring->adev; 3522 struct v9_mqd *mqd = ring->mqd_ptr; 3523 struct v9_mqd *tmp_mqd; 3524 3525 gfx_v9_0_kiq_setting(ring); 3526 3527 /* GPU could be in bad state during probe, driver trigger the reset 3528 * after load the SMU, in this case , the mqd is not be initialized. 3529 * driver need to re-init the mqd. 3530 * check mqd->cp_hqd_pq_control since this value should not be 0 3531 */ 3532 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup; 3533 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3534 /* for GPU_RESET case , reset MQD to a clean status */ 3535 if (adev->gfx.kiq[0].mqd_backup) 3536 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation)); 3537 3538 /* reset ring buffer */ 3539 ring->wptr = 0; 3540 amdgpu_ring_clear_ring(ring); 3541 3542 mutex_lock(&adev->srbm_mutex); 3543 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3544 gfx_v9_0_kiq_init_register(ring); 3545 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3546 mutex_unlock(&adev->srbm_mutex); 3547 } else { 3548 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3549 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3550 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3551 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3552 amdgpu_ring_clear_ring(ring); 3553 mutex_lock(&adev->srbm_mutex); 3554 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3555 gfx_v9_0_mqd_init(ring); 3556 gfx_v9_0_kiq_init_register(ring); 3557 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3558 mutex_unlock(&adev->srbm_mutex); 3559 3560 if (adev->gfx.kiq[0].mqd_backup) 3561 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 3562 } 3563 3564 return 0; 3565 } 3566 3567 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3568 { 3569 struct amdgpu_device *adev = ring->adev; 3570 struct v9_mqd *mqd = ring->mqd_ptr; 3571 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3572 struct v9_mqd *tmp_mqd; 3573 3574 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3575 * is not be initialized before 3576 */ 3577 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3578 3579 if (!tmp_mqd->cp_hqd_pq_control || 3580 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3581 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3582 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3583 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3584 mutex_lock(&adev->srbm_mutex); 3585 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); 3586 gfx_v9_0_mqd_init(ring); 3587 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3588 mutex_unlock(&adev->srbm_mutex); 3589 3590 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3591 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3592 } else { 3593 /* restore MQD to a clean status */ 3594 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3595 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3596 /* reset ring buffer */ 3597 ring->wptr = 0; 3598 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3599 amdgpu_ring_clear_ring(ring); 3600 } 3601 3602 return 0; 3603 } 3604 3605 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3606 { 3607 struct amdgpu_ring *ring; 3608 int r; 3609 3610 ring = &adev->gfx.kiq[0].ring; 3611 3612 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3613 if (unlikely(r != 0)) 3614 return r; 3615 3616 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3617 if (unlikely(r != 0)) 3618 return r; 3619 3620 gfx_v9_0_kiq_init_queue(ring); 3621 amdgpu_bo_kunmap(ring->mqd_obj); 3622 ring->mqd_ptr = NULL; 3623 amdgpu_bo_unreserve(ring->mqd_obj); 3624 ring->sched.ready = true; 3625 return 0; 3626 } 3627 3628 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3629 { 3630 struct amdgpu_ring *ring = NULL; 3631 int r = 0, i; 3632 3633 gfx_v9_0_cp_compute_enable(adev, true); 3634 3635 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3636 ring = &adev->gfx.compute_ring[i]; 3637 3638 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3639 if (unlikely(r != 0)) 3640 goto done; 3641 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3642 if (!r) { 3643 r = gfx_v9_0_kcq_init_queue(ring); 3644 amdgpu_bo_kunmap(ring->mqd_obj); 3645 ring->mqd_ptr = NULL; 3646 } 3647 amdgpu_bo_unreserve(ring->mqd_obj); 3648 if (r) 3649 goto done; 3650 } 3651 3652 r = amdgpu_gfx_enable_kcq(adev, 0); 3653 done: 3654 return r; 3655 } 3656 3657 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3658 { 3659 int r, i; 3660 struct amdgpu_ring *ring; 3661 3662 if (!(adev->flags & AMD_IS_APU)) 3663 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3664 3665 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3666 if (adev->gfx.num_gfx_rings) { 3667 /* legacy firmware loading */ 3668 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3669 if (r) 3670 return r; 3671 } 3672 3673 r = gfx_v9_0_cp_compute_load_microcode(adev); 3674 if (r) 3675 return r; 3676 } 3677 3678 r = gfx_v9_0_kiq_resume(adev); 3679 if (r) 3680 return r; 3681 3682 if (adev->gfx.num_gfx_rings) { 3683 r = gfx_v9_0_cp_gfx_resume(adev); 3684 if (r) 3685 return r; 3686 } 3687 3688 r = gfx_v9_0_kcq_resume(adev); 3689 if (r) 3690 return r; 3691 3692 if (adev->gfx.num_gfx_rings) { 3693 ring = &adev->gfx.gfx_ring[0]; 3694 r = amdgpu_ring_test_helper(ring); 3695 if (r) 3696 return r; 3697 } 3698 3699 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3700 ring = &adev->gfx.compute_ring[i]; 3701 amdgpu_ring_test_helper(ring); 3702 } 3703 3704 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3705 3706 return 0; 3707 } 3708 3709 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3710 { 3711 u32 tmp; 3712 3713 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && 3714 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) 3715 return; 3716 3717 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3718 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3719 adev->df.hash_status.hash_64k); 3720 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3721 adev->df.hash_status.hash_2m); 3722 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3723 adev->df.hash_status.hash_1g); 3724 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3725 } 3726 3727 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3728 { 3729 if (adev->gfx.num_gfx_rings) 3730 gfx_v9_0_cp_gfx_enable(adev, enable); 3731 gfx_v9_0_cp_compute_enable(adev, enable); 3732 } 3733 3734 static int gfx_v9_0_hw_init(void *handle) 3735 { 3736 int r; 3737 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3738 3739 if (!amdgpu_sriov_vf(adev)) 3740 gfx_v9_0_init_golden_registers(adev); 3741 3742 gfx_v9_0_constants_init(adev); 3743 3744 gfx_v9_0_init_tcp_config(adev); 3745 3746 r = adev->gfx.rlc.funcs->resume(adev); 3747 if (r) 3748 return r; 3749 3750 r = gfx_v9_0_cp_resume(adev); 3751 if (r) 3752 return r; 3753 3754 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 3755 gfx_v9_4_2_set_power_brake_sequence(adev); 3756 3757 return r; 3758 } 3759 3760 static int gfx_v9_0_hw_fini(void *handle) 3761 { 3762 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3763 3764 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 3765 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3766 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3767 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3768 3769 /* DF freeze and kcq disable will fail */ 3770 if (!amdgpu_ras_intr_triggered()) 3771 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3772 amdgpu_gfx_disable_kcq(adev, 0); 3773 3774 if (amdgpu_sriov_vf(adev)) { 3775 gfx_v9_0_cp_gfx_enable(adev, false); 3776 /* must disable polling for SRIOV when hw finished, otherwise 3777 * CPC engine may still keep fetching WB address which is already 3778 * invalid after sw finished and trigger DMAR reading error in 3779 * hypervisor side. 3780 */ 3781 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3782 return 0; 3783 } 3784 3785 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3786 * otherwise KIQ is hanging when binding back 3787 */ 3788 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3789 mutex_lock(&adev->srbm_mutex); 3790 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me, 3791 adev->gfx.kiq[0].ring.pipe, 3792 adev->gfx.kiq[0].ring.queue, 0, 0); 3793 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring); 3794 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3795 mutex_unlock(&adev->srbm_mutex); 3796 } 3797 3798 gfx_v9_0_cp_enable(adev, false); 3799 3800 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3801 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3802 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { 3803 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3804 return 0; 3805 } 3806 3807 adev->gfx.rlc.funcs->stop(adev); 3808 return 0; 3809 } 3810 3811 static int gfx_v9_0_suspend(void *handle) 3812 { 3813 return gfx_v9_0_hw_fini(handle); 3814 } 3815 3816 static int gfx_v9_0_resume(void *handle) 3817 { 3818 return gfx_v9_0_hw_init(handle); 3819 } 3820 3821 static bool gfx_v9_0_is_idle(void *handle) 3822 { 3823 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3824 3825 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3826 GRBM_STATUS, GUI_ACTIVE)) 3827 return false; 3828 else 3829 return true; 3830 } 3831 3832 static int gfx_v9_0_wait_for_idle(void *handle) 3833 { 3834 unsigned i; 3835 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3836 3837 for (i = 0; i < adev->usec_timeout; i++) { 3838 if (gfx_v9_0_is_idle(handle)) 3839 return 0; 3840 udelay(1); 3841 } 3842 return -ETIMEDOUT; 3843 } 3844 3845 static int gfx_v9_0_soft_reset(void *handle) 3846 { 3847 u32 grbm_soft_reset = 0; 3848 u32 tmp; 3849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3850 3851 /* GRBM_STATUS */ 3852 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3853 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3854 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3855 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3856 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3857 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3858 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3859 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3860 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3861 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3862 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3863 } 3864 3865 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3866 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3867 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3868 } 3869 3870 /* GRBM_STATUS2 */ 3871 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3872 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3873 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3874 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3875 3876 3877 if (grbm_soft_reset) { 3878 /* stop the rlc */ 3879 adev->gfx.rlc.funcs->stop(adev); 3880 3881 if (adev->gfx.num_gfx_rings) 3882 /* Disable GFX parsing/prefetching */ 3883 gfx_v9_0_cp_gfx_enable(adev, false); 3884 3885 /* Disable MEC parsing/prefetching */ 3886 gfx_v9_0_cp_compute_enable(adev, false); 3887 3888 if (grbm_soft_reset) { 3889 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3890 tmp |= grbm_soft_reset; 3891 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3892 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3893 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3894 3895 udelay(50); 3896 3897 tmp &= ~grbm_soft_reset; 3898 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3899 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3900 } 3901 3902 /* Wait a little for things to settle down */ 3903 udelay(50); 3904 } 3905 return 0; 3906 } 3907 3908 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 3909 { 3910 signed long r, cnt = 0; 3911 unsigned long flags; 3912 uint32_t seq, reg_val_offs = 0; 3913 uint64_t value = 0; 3914 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 3915 struct amdgpu_ring *ring = &kiq->ring; 3916 3917 BUG_ON(!ring->funcs->emit_rreg); 3918 3919 spin_lock_irqsave(&kiq->ring_lock, flags); 3920 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 3921 pr_err("critical bug! too many kiq readers\n"); 3922 goto failed_unlock; 3923 } 3924 amdgpu_ring_alloc(ring, 32); 3925 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3926 amdgpu_ring_write(ring, 9 | /* src: register*/ 3927 (5 << 8) | /* dst: memory */ 3928 (1 << 16) | /* count sel */ 3929 (1 << 20)); /* write confirm */ 3930 amdgpu_ring_write(ring, 0); 3931 amdgpu_ring_write(ring, 0); 3932 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3933 reg_val_offs * 4)); 3934 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3935 reg_val_offs * 4)); 3936 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 3937 if (r) 3938 goto failed_undo; 3939 3940 amdgpu_ring_commit(ring); 3941 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3942 3943 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3944 3945 /* don't wait anymore for gpu reset case because this way may 3946 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 3947 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 3948 * never return if we keep waiting in virt_kiq_rreg, which cause 3949 * gpu_recover() hang there. 3950 * 3951 * also don't wait anymore for IRQ context 3952 * */ 3953 if (r < 1 && (amdgpu_in_reset(adev))) 3954 goto failed_kiq_read; 3955 3956 might_sleep(); 3957 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 3958 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 3959 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3960 } 3961 3962 if (cnt > MAX_KIQ_REG_TRY) 3963 goto failed_kiq_read; 3964 3965 mb(); 3966 value = (uint64_t)adev->wb.wb[reg_val_offs] | 3967 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 3968 amdgpu_device_wb_free(adev, reg_val_offs); 3969 return value; 3970 3971 failed_undo: 3972 amdgpu_ring_undo(ring); 3973 failed_unlock: 3974 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3975 failed_kiq_read: 3976 if (reg_val_offs) 3977 amdgpu_device_wb_free(adev, reg_val_offs); 3978 pr_err("failed to read gpu clock\n"); 3979 return ~0; 3980 } 3981 3982 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3983 { 3984 uint64_t clock, clock_lo, clock_hi, hi_check; 3985 3986 switch (adev->ip_versions[GC_HWIP][0]) { 3987 case IP_VERSION(9, 3, 0): 3988 preempt_disable(); 3989 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3990 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 3991 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3992 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 3993 * roughly every 42 seconds. 3994 */ 3995 if (hi_check != clock_hi) { 3996 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 3997 clock_hi = hi_check; 3998 } 3999 preempt_enable(); 4000 clock = clock_lo | (clock_hi << 32ULL); 4001 break; 4002 case IP_VERSION(9, 1, 0): 4003 case IP_VERSION(9, 2, 2): 4004 preempt_disable(); 4005 if (adev->rev_id >= 0x8) { 4006 clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4007 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4008 hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4009 } else { 4010 clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4011 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4012 hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4013 } 4014 /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4015 * roughly every 42 seconds. 4016 */ 4017 if (hi_check != clock_hi) { 4018 if (adev->rev_id >= 0x8) 4019 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4020 else 4021 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4022 clock_hi = hi_check; 4023 } 4024 preempt_enable(); 4025 clock = clock_lo | (clock_hi << 32ULL); 4026 break; 4027 default: 4028 amdgpu_gfx_off_ctrl(adev, false); 4029 mutex_lock(&adev->gfx.gpu_clock_mutex); 4030 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { 4031 clock = gfx_v9_0_kiq_read_clock(adev); 4032 } else { 4033 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4034 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4035 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4036 } 4037 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4038 amdgpu_gfx_off_ctrl(adev, true); 4039 break; 4040 } 4041 return clock; 4042 } 4043 4044 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4045 uint32_t vmid, 4046 uint32_t gds_base, uint32_t gds_size, 4047 uint32_t gws_base, uint32_t gws_size, 4048 uint32_t oa_base, uint32_t oa_size) 4049 { 4050 struct amdgpu_device *adev = ring->adev; 4051 4052 /* GDS Base */ 4053 gfx_v9_0_write_data_to_reg(ring, 0, false, 4054 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4055 gds_base); 4056 4057 /* GDS Size */ 4058 gfx_v9_0_write_data_to_reg(ring, 0, false, 4059 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4060 gds_size); 4061 4062 /* GWS */ 4063 gfx_v9_0_write_data_to_reg(ring, 0, false, 4064 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4065 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4066 4067 /* OA */ 4068 gfx_v9_0_write_data_to_reg(ring, 0, false, 4069 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4070 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4071 } 4072 4073 static const u32 vgpr_init_compute_shader[] = 4074 { 4075 0xb07c0000, 0xbe8000ff, 4076 0x000000f8, 0xbf110800, 4077 0x7e000280, 0x7e020280, 4078 0x7e040280, 0x7e060280, 4079 0x7e080280, 0x7e0a0280, 4080 0x7e0c0280, 0x7e0e0280, 4081 0x80808800, 0xbe803200, 4082 0xbf84fff5, 0xbf9c0000, 4083 0xd28c0001, 0x0001007f, 4084 0xd28d0001, 0x0002027e, 4085 0x10020288, 0xb8810904, 4086 0xb7814000, 0xd1196a01, 4087 0x00000301, 0xbe800087, 4088 0xbefc00c1, 0xd89c4000, 4089 0x00020201, 0xd89cc080, 4090 0x00040401, 0x320202ff, 4091 0x00000800, 0x80808100, 4092 0xbf84fff8, 0x7e020280, 4093 0xbf810000, 0x00000000, 4094 }; 4095 4096 static const u32 sgpr_init_compute_shader[] = 4097 { 4098 0xb07c0000, 0xbe8000ff, 4099 0x0000005f, 0xbee50080, 4100 0xbe812c65, 0xbe822c65, 4101 0xbe832c65, 0xbe842c65, 4102 0xbe852c65, 0xb77c0005, 4103 0x80808500, 0xbf84fff8, 4104 0xbe800080, 0xbf810000, 4105 }; 4106 4107 static const u32 vgpr_init_compute_shader_arcturus[] = { 4108 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4109 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4110 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4111 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4112 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4113 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4114 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4115 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4116 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4117 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4118 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4119 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4120 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4121 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4122 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4123 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4124 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4125 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4126 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4127 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4128 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4129 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4130 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4131 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4132 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4133 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4134 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4135 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4136 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4137 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4138 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4139 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4140 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4141 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4142 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4143 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4144 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4145 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4146 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4147 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4148 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4149 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4150 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4151 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4152 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4153 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4154 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4155 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4156 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4157 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4158 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4159 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4160 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4161 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4162 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4163 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4164 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4165 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4166 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4167 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4168 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4169 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4170 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4171 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4172 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4173 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4174 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4175 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4176 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4177 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4178 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4179 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4180 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4181 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4182 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4183 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4184 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4185 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4186 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4187 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4188 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4189 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4190 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4191 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4192 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4193 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4194 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4195 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4196 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4197 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4198 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4199 0xbf84fff8, 0xbf810000, 4200 }; 4201 4202 /* When below register arrays changed, please update gpr_reg_size, 4203 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4204 to cover all gfx9 ASICs */ 4205 static const struct soc15_reg_entry vgpr_init_regs[] = { 4206 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4207 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4208 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4209 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4210 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4211 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4212 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4213 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4214 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4215 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4216 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4217 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4218 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4219 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4220 }; 4221 4222 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4223 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4224 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4225 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4226 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4227 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4228 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4229 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4230 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4231 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4232 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4233 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4234 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4235 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4236 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4237 }; 4238 4239 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4240 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4241 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4242 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4243 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4244 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4245 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4246 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4247 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4248 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4249 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4250 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4251 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4252 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4253 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4254 }; 4255 4256 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4257 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4258 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4259 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4260 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4261 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4262 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4263 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4264 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4265 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4266 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4267 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4268 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4269 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4270 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4271 }; 4272 4273 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4274 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4275 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4276 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4277 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4278 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4279 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4280 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4281 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4282 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4283 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4284 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4285 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4286 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4287 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4288 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4289 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4290 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4291 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4292 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4293 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4294 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4295 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4296 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4297 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4298 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4299 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4300 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4301 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4302 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4303 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4304 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4305 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4306 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4307 }; 4308 4309 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4310 { 4311 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4312 int i, r; 4313 4314 /* only support when RAS is enabled */ 4315 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4316 return 0; 4317 4318 r = amdgpu_ring_alloc(ring, 7); 4319 if (r) { 4320 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4321 ring->name, r); 4322 return r; 4323 } 4324 4325 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4326 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4327 4328 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4329 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4330 PACKET3_DMA_DATA_DST_SEL(1) | 4331 PACKET3_DMA_DATA_SRC_SEL(2) | 4332 PACKET3_DMA_DATA_ENGINE(0))); 4333 amdgpu_ring_write(ring, 0); 4334 amdgpu_ring_write(ring, 0); 4335 amdgpu_ring_write(ring, 0); 4336 amdgpu_ring_write(ring, 0); 4337 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4338 adev->gds.gds_size); 4339 4340 amdgpu_ring_commit(ring); 4341 4342 for (i = 0; i < adev->usec_timeout; i++) { 4343 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4344 break; 4345 udelay(1); 4346 } 4347 4348 if (i >= adev->usec_timeout) 4349 r = -ETIMEDOUT; 4350 4351 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4352 4353 return r; 4354 } 4355 4356 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4357 { 4358 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4359 struct amdgpu_ib ib; 4360 struct dma_fence *f = NULL; 4361 int r, i; 4362 unsigned total_size, vgpr_offset, sgpr_offset; 4363 u64 gpu_addr; 4364 4365 int compute_dim_x = adev->gfx.config.max_shader_engines * 4366 adev->gfx.config.max_cu_per_sh * 4367 adev->gfx.config.max_sh_per_se; 4368 int sgpr_work_group_size = 5; 4369 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4370 int vgpr_init_shader_size; 4371 const u32 *vgpr_init_shader_ptr; 4372 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4373 4374 /* only support when RAS is enabled */ 4375 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4376 return 0; 4377 4378 /* bail if the compute ring is not ready */ 4379 if (!ring->sched.ready) 4380 return 0; 4381 4382 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 4383 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4384 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4385 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4386 } else { 4387 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4388 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4389 vgpr_init_regs_ptr = vgpr_init_regs; 4390 } 4391 4392 total_size = 4393 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4394 total_size += 4395 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4396 total_size += 4397 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4398 total_size = ALIGN(total_size, 256); 4399 vgpr_offset = total_size; 4400 total_size += ALIGN(vgpr_init_shader_size, 256); 4401 sgpr_offset = total_size; 4402 total_size += sizeof(sgpr_init_compute_shader); 4403 4404 /* allocate an indirect buffer to put the commands in */ 4405 memset(&ib, 0, sizeof(ib)); 4406 r = amdgpu_ib_get(adev, NULL, total_size, 4407 AMDGPU_IB_POOL_DIRECT, &ib); 4408 if (r) { 4409 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4410 return r; 4411 } 4412 4413 /* load the compute shaders */ 4414 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4415 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4416 4417 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4418 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4419 4420 /* init the ib length to 0 */ 4421 ib.length_dw = 0; 4422 4423 /* VGPR */ 4424 /* write the register state for the compute dispatch */ 4425 for (i = 0; i < gpr_reg_size; i++) { 4426 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4427 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4428 - PACKET3_SET_SH_REG_START; 4429 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4430 } 4431 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4432 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4433 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4434 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4435 - PACKET3_SET_SH_REG_START; 4436 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4437 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4438 4439 /* write dispatch packet */ 4440 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4441 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4442 ib.ptr[ib.length_dw++] = 1; /* y */ 4443 ib.ptr[ib.length_dw++] = 1; /* z */ 4444 ib.ptr[ib.length_dw++] = 4445 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4446 4447 /* write CS partial flush packet */ 4448 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4449 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4450 4451 /* SGPR1 */ 4452 /* write the register state for the compute dispatch */ 4453 for (i = 0; i < gpr_reg_size; i++) { 4454 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4455 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4456 - PACKET3_SET_SH_REG_START; 4457 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4458 } 4459 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4460 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4461 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4462 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4463 - PACKET3_SET_SH_REG_START; 4464 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4465 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4466 4467 /* write dispatch packet */ 4468 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4469 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4470 ib.ptr[ib.length_dw++] = 1; /* y */ 4471 ib.ptr[ib.length_dw++] = 1; /* z */ 4472 ib.ptr[ib.length_dw++] = 4473 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4474 4475 /* write CS partial flush packet */ 4476 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4477 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4478 4479 /* SGPR2 */ 4480 /* write the register state for the compute dispatch */ 4481 for (i = 0; i < gpr_reg_size; i++) { 4482 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4483 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4484 - PACKET3_SET_SH_REG_START; 4485 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4486 } 4487 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4488 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4489 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4490 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4491 - PACKET3_SET_SH_REG_START; 4492 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4493 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4494 4495 /* write dispatch packet */ 4496 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4497 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4498 ib.ptr[ib.length_dw++] = 1; /* y */ 4499 ib.ptr[ib.length_dw++] = 1; /* z */ 4500 ib.ptr[ib.length_dw++] = 4501 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4502 4503 /* write CS partial flush packet */ 4504 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4505 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4506 4507 /* shedule the ib on the ring */ 4508 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4509 if (r) { 4510 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4511 goto fail; 4512 } 4513 4514 /* wait for the GPU to finish processing the IB */ 4515 r = dma_fence_wait(f, false); 4516 if (r) { 4517 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4518 goto fail; 4519 } 4520 4521 fail: 4522 amdgpu_ib_free(adev, &ib, NULL); 4523 dma_fence_put(f); 4524 4525 return r; 4526 } 4527 4528 static int gfx_v9_0_early_init(void *handle) 4529 { 4530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4531 4532 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 4533 4534 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 4535 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4536 adev->gfx.num_gfx_rings = 0; 4537 else 4538 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4539 adev->gfx.xcc_mask = 1; 4540 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4541 AMDGPU_MAX_COMPUTE_RINGS); 4542 gfx_v9_0_set_kiq_pm4_funcs(adev); 4543 gfx_v9_0_set_ring_funcs(adev); 4544 gfx_v9_0_set_irq_funcs(adev); 4545 gfx_v9_0_set_gds_init(adev); 4546 gfx_v9_0_set_rlc_funcs(adev); 4547 4548 /* init rlcg reg access ctrl */ 4549 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4550 4551 return gfx_v9_0_init_microcode(adev); 4552 } 4553 4554 static int gfx_v9_0_ecc_late_init(void *handle) 4555 { 4556 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4557 int r; 4558 4559 /* 4560 * Temp workaround to fix the issue that CP firmware fails to 4561 * update read pointer when CPDMA is writing clearing operation 4562 * to GDS in suspend/resume sequence on several cards. So just 4563 * limit this operation in cold boot sequence. 4564 */ 4565 if ((!adev->in_suspend) && 4566 (adev->gds.gds_size)) { 4567 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4568 if (r) 4569 return r; 4570 } 4571 4572 /* requires IBs so do in late init after IB pool is initialized */ 4573 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4574 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4575 else 4576 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4577 4578 if (r) 4579 return r; 4580 4581 if (adev->gfx.ras && 4582 adev->gfx.ras->enable_watchdog_timer) 4583 adev->gfx.ras->enable_watchdog_timer(adev); 4584 4585 return 0; 4586 } 4587 4588 static int gfx_v9_0_late_init(void *handle) 4589 { 4590 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4591 int r; 4592 4593 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4594 if (r) 4595 return r; 4596 4597 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4598 if (r) 4599 return r; 4600 4601 r = gfx_v9_0_ecc_late_init(handle); 4602 if (r) 4603 return r; 4604 4605 return 0; 4606 } 4607 4608 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4609 { 4610 uint32_t rlc_setting; 4611 4612 /* if RLC is not enabled, do nothing */ 4613 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4614 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4615 return false; 4616 4617 return true; 4618 } 4619 4620 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 4621 { 4622 uint32_t data; 4623 unsigned i; 4624 4625 data = RLC_SAFE_MODE__CMD_MASK; 4626 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4627 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4628 4629 /* wait for RLC_SAFE_MODE */ 4630 for (i = 0; i < adev->usec_timeout; i++) { 4631 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4632 break; 4633 udelay(1); 4634 } 4635 } 4636 4637 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 4638 { 4639 uint32_t data; 4640 4641 data = RLC_SAFE_MODE__CMD_MASK; 4642 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4643 } 4644 4645 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4646 bool enable) 4647 { 4648 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4649 4650 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4651 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4652 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4653 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4654 } else { 4655 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4656 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4657 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4658 } 4659 4660 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4661 } 4662 4663 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4664 bool enable) 4665 { 4666 /* TODO: double check if we need to perform under safe mode */ 4667 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4668 4669 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4670 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4671 else 4672 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4673 4674 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4675 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4676 else 4677 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4678 4679 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4680 } 4681 4682 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4683 bool enable) 4684 { 4685 uint32_t data, def; 4686 4687 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4688 4689 /* It is disabled by HW by default */ 4690 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4691 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4692 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4693 4694 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4695 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4696 4697 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4698 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4699 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4700 4701 /* only for Vega10 & Raven1 */ 4702 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4703 4704 if (def != data) 4705 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4706 4707 /* MGLS is a global flag to control all MGLS in GFX */ 4708 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4709 /* 2 - RLC memory Light sleep */ 4710 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4711 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4712 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4713 if (def != data) 4714 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4715 } 4716 /* 3 - CP memory Light sleep */ 4717 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4718 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4719 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4720 if (def != data) 4721 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4722 } 4723 } 4724 } else { 4725 /* 1 - MGCG_OVERRIDE */ 4726 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4727 4728 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4729 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4730 4731 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4732 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4733 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4734 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4735 4736 if (def != data) 4737 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4738 4739 /* 2 - disable MGLS in RLC */ 4740 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4741 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4742 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4743 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4744 } 4745 4746 /* 3 - disable MGLS in CP */ 4747 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4748 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4749 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4750 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4751 } 4752 } 4753 4754 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4755 } 4756 4757 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4758 bool enable) 4759 { 4760 uint32_t data, def; 4761 4762 if (!adev->gfx.num_gfx_rings) 4763 return; 4764 4765 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4766 4767 /* Enable 3D CGCG/CGLS */ 4768 if (enable) { 4769 /* write cmd to clear cgcg/cgls ov */ 4770 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4771 /* unset CGCG override */ 4772 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4773 /* update CGCG and CGLS override bits */ 4774 if (def != data) 4775 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4776 4777 /* enable 3Dcgcg FSM(0x0000363f) */ 4778 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4779 4780 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4781 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4782 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4783 else 4784 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4785 4786 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4787 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4788 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4789 if (def != data) 4790 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4791 4792 /* set IDLE_POLL_COUNT(0x00900100) */ 4793 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4794 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4795 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4796 if (def != data) 4797 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4798 } else { 4799 /* Disable CGCG/CGLS */ 4800 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4801 /* disable cgcg, cgls should be disabled */ 4802 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4803 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4804 /* disable cgcg and cgls in FSM */ 4805 if (def != data) 4806 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4807 } 4808 4809 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4810 } 4811 4812 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4813 bool enable) 4814 { 4815 uint32_t def, data; 4816 4817 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 4818 4819 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4820 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4821 /* unset CGCG override */ 4822 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4823 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4824 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4825 else 4826 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4827 /* update CGCG and CGLS override bits */ 4828 if (def != data) 4829 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4830 4831 /* enable cgcg FSM(0x0000363F) */ 4832 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4833 4834 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) 4835 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4836 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4837 else 4838 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4839 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4840 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4841 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4842 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4843 if (def != data) 4844 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4845 4846 /* set IDLE_POLL_COUNT(0x00900100) */ 4847 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4848 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4849 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4850 if (def != data) 4851 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4852 } else { 4853 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4854 /* reset CGCG/CGLS bits */ 4855 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4856 /* disable cgcg and cgls in FSM */ 4857 if (def != data) 4858 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4859 } 4860 4861 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 4862 } 4863 4864 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4865 bool enable) 4866 { 4867 if (enable) { 4868 /* CGCG/CGLS should be enabled after MGCG/MGLS 4869 * === MGCG + MGLS === 4870 */ 4871 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4872 /* === CGCG /CGLS for GFX 3D Only === */ 4873 gfx_v9_0_update_3d_clock_gating(adev, enable); 4874 /* === CGCG + CGLS === */ 4875 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4876 } else { 4877 /* CGCG/CGLS should be disabled before MGCG/MGLS 4878 * === CGCG + CGLS === 4879 */ 4880 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4881 /* === CGCG /CGLS for GFX 3D Only === */ 4882 gfx_v9_0_update_3d_clock_gating(adev, enable); 4883 /* === MGCG + MGLS === */ 4884 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4885 } 4886 return 0; 4887 } 4888 4889 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4890 { 4891 u32 reg, data; 4892 4893 amdgpu_gfx_off_ctrl(adev, false); 4894 4895 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 4896 if (amdgpu_sriov_is_pp_one_vf(adev)) 4897 data = RREG32_NO_KIQ(reg); 4898 else 4899 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4900 4901 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4902 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4903 4904 if (amdgpu_sriov_is_pp_one_vf(adev)) 4905 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 4906 else 4907 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4908 4909 amdgpu_gfx_off_ctrl(adev, true); 4910 } 4911 4912 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4913 uint32_t offset, 4914 struct soc15_reg_rlcg *entries, int arr_size) 4915 { 4916 int i; 4917 uint32_t reg; 4918 4919 if (!entries) 4920 return false; 4921 4922 for (i = 0; i < arr_size; i++) { 4923 const struct soc15_reg_rlcg *entry; 4924 4925 entry = &entries[i]; 4926 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4927 if (offset == reg) 4928 return true; 4929 } 4930 4931 return false; 4932 } 4933 4934 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4935 { 4936 return gfx_v9_0_check_rlcg_range(adev, offset, 4937 (void *)rlcg_access_gc_9_0, 4938 ARRAY_SIZE(rlcg_access_gc_9_0)); 4939 } 4940 4941 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 4942 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 4943 .set_safe_mode = gfx_v9_0_set_safe_mode, 4944 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 4945 .init = gfx_v9_0_rlc_init, 4946 .get_csb_size = gfx_v9_0_get_csb_size, 4947 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 4948 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 4949 .resume = gfx_v9_0_rlc_resume, 4950 .stop = gfx_v9_0_rlc_stop, 4951 .reset = gfx_v9_0_rlc_reset, 4952 .start = gfx_v9_0_rlc_start, 4953 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 4954 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 4955 }; 4956 4957 static int gfx_v9_0_set_powergating_state(void *handle, 4958 enum amd_powergating_state state) 4959 { 4960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4961 bool enable = (state == AMD_PG_STATE_GATE); 4962 4963 switch (adev->ip_versions[GC_HWIP][0]) { 4964 case IP_VERSION(9, 2, 2): 4965 case IP_VERSION(9, 1, 0): 4966 case IP_VERSION(9, 3, 0): 4967 if (!enable) 4968 amdgpu_gfx_off_ctrl(adev, false); 4969 4970 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4971 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 4972 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 4973 } else { 4974 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 4975 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 4976 } 4977 4978 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4979 gfx_v9_0_enable_cp_power_gating(adev, true); 4980 else 4981 gfx_v9_0_enable_cp_power_gating(adev, false); 4982 4983 /* update gfx cgpg state */ 4984 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 4985 4986 /* update mgcg state */ 4987 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 4988 4989 if (enable) 4990 amdgpu_gfx_off_ctrl(adev, true); 4991 break; 4992 case IP_VERSION(9, 2, 1): 4993 amdgpu_gfx_off_ctrl(adev, enable); 4994 break; 4995 default: 4996 break; 4997 } 4998 4999 return 0; 5000 } 5001 5002 static int gfx_v9_0_set_clockgating_state(void *handle, 5003 enum amd_clockgating_state state) 5004 { 5005 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5006 5007 if (amdgpu_sriov_vf(adev)) 5008 return 0; 5009 5010 switch (adev->ip_versions[GC_HWIP][0]) { 5011 case IP_VERSION(9, 0, 1): 5012 case IP_VERSION(9, 2, 1): 5013 case IP_VERSION(9, 4, 0): 5014 case IP_VERSION(9, 2, 2): 5015 case IP_VERSION(9, 1, 0): 5016 case IP_VERSION(9, 4, 1): 5017 case IP_VERSION(9, 3, 0): 5018 case IP_VERSION(9, 4, 2): 5019 gfx_v9_0_update_gfx_clock_gating(adev, 5020 state == AMD_CG_STATE_GATE); 5021 break; 5022 default: 5023 break; 5024 } 5025 return 0; 5026 } 5027 5028 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5029 { 5030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5031 int data; 5032 5033 if (amdgpu_sriov_vf(adev)) 5034 *flags = 0; 5035 5036 /* AMD_CG_SUPPORT_GFX_MGCG */ 5037 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5038 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5039 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5040 5041 /* AMD_CG_SUPPORT_GFX_CGCG */ 5042 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5043 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5044 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5045 5046 /* AMD_CG_SUPPORT_GFX_CGLS */ 5047 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5048 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5049 5050 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5051 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5052 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5053 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5054 5055 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5056 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5057 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5058 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5059 5060 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { 5061 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5062 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5063 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5064 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5065 5066 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5067 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5068 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5069 } 5070 } 5071 5072 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5073 { 5074 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5075 } 5076 5077 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5078 { 5079 struct amdgpu_device *adev = ring->adev; 5080 u64 wptr; 5081 5082 /* XXX check if swapping is necessary on BE */ 5083 if (ring->use_doorbell) { 5084 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5085 } else { 5086 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5087 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5088 } 5089 5090 return wptr; 5091 } 5092 5093 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5094 { 5095 struct amdgpu_device *adev = ring->adev; 5096 5097 if (ring->use_doorbell) { 5098 /* XXX check if swapping is necessary on BE */ 5099 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5100 WDOORBELL64(ring->doorbell_index, ring->wptr); 5101 } else { 5102 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5103 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5104 } 5105 } 5106 5107 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5108 { 5109 struct amdgpu_device *adev = ring->adev; 5110 u32 ref_and_mask, reg_mem_engine; 5111 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5112 5113 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5114 switch (ring->me) { 5115 case 1: 5116 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5117 break; 5118 case 2: 5119 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5120 break; 5121 default: 5122 return; 5123 } 5124 reg_mem_engine = 0; 5125 } else { 5126 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5127 reg_mem_engine = 1; /* pfp */ 5128 } 5129 5130 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5131 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5132 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5133 ref_and_mask, ref_and_mask, 0x20); 5134 } 5135 5136 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5137 struct amdgpu_job *job, 5138 struct amdgpu_ib *ib, 5139 uint32_t flags) 5140 { 5141 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5142 u32 header, control = 0; 5143 5144 if (ib->flags & AMDGPU_IB_FLAG_CE) 5145 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5146 else 5147 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5148 5149 control |= ib->length_dw | (vmid << 24); 5150 5151 if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 5152 control |= INDIRECT_BUFFER_PRE_ENB(1); 5153 5154 if (flags & AMDGPU_IB_PREEMPTED) 5155 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5156 5157 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5158 gfx_v9_0_ring_emit_de_meta(ring, 5159 (!amdgpu_sriov_vf(ring->adev) && 5160 flags & AMDGPU_IB_PREEMPTED) ? 5161 true : false); 5162 } 5163 5164 amdgpu_ring_write(ring, header); 5165 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5166 amdgpu_ring_write(ring, 5167 #ifdef __BIG_ENDIAN 5168 (2 << 0) | 5169 #endif 5170 lower_32_bits(ib->gpu_addr)); 5171 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5172 amdgpu_ring_write(ring, control); 5173 } 5174 5175 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5176 struct amdgpu_job *job, 5177 struct amdgpu_ib *ib, 5178 uint32_t flags) 5179 { 5180 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5181 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5182 5183 /* Currently, there is a high possibility to get wave ID mismatch 5184 * between ME and GDS, leading to a hw deadlock, because ME generates 5185 * different wave IDs than the GDS expects. This situation happens 5186 * randomly when at least 5 compute pipes use GDS ordered append. 5187 * The wave IDs generated by ME are also wrong after suspend/resume. 5188 * Those are probably bugs somewhere else in the kernel driver. 5189 * 5190 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5191 * GDS to 0 for this ring (me/pipe). 5192 */ 5193 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5194 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5195 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5196 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5197 } 5198 5199 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5200 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5201 amdgpu_ring_write(ring, 5202 #ifdef __BIG_ENDIAN 5203 (2 << 0) | 5204 #endif 5205 lower_32_bits(ib->gpu_addr)); 5206 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5207 amdgpu_ring_write(ring, control); 5208 } 5209 5210 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5211 u64 seq, unsigned flags) 5212 { 5213 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5214 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5215 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5216 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 5217 uint32_t dw2 = 0; 5218 5219 /* RELEASE_MEM - flush caches, send int */ 5220 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5221 5222 if (writeback) { 5223 dw2 = EOP_TC_NC_ACTION_EN; 5224 } else { 5225 dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | 5226 EOP_TC_MD_ACTION_EN; 5227 } 5228 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5229 EVENT_INDEX(5); 5230 if (exec) 5231 dw2 |= EOP_EXEC; 5232 5233 amdgpu_ring_write(ring, dw2); 5234 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5235 5236 /* 5237 * the address should be Qword aligned if 64bit write, Dword 5238 * aligned if only send 32bit data low (discard data high) 5239 */ 5240 if (write64bit) 5241 BUG_ON(addr & 0x7); 5242 else 5243 BUG_ON(addr & 0x3); 5244 amdgpu_ring_write(ring, lower_32_bits(addr)); 5245 amdgpu_ring_write(ring, upper_32_bits(addr)); 5246 amdgpu_ring_write(ring, lower_32_bits(seq)); 5247 amdgpu_ring_write(ring, upper_32_bits(seq)); 5248 amdgpu_ring_write(ring, 0); 5249 } 5250 5251 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5252 { 5253 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5254 uint32_t seq = ring->fence_drv.sync_seq; 5255 uint64_t addr = ring->fence_drv.gpu_addr; 5256 5257 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5258 lower_32_bits(addr), upper_32_bits(addr), 5259 seq, 0xffffffff, 4); 5260 } 5261 5262 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5263 unsigned vmid, uint64_t pd_addr) 5264 { 5265 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5266 5267 /* compute doesn't have PFP */ 5268 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5269 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5270 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5271 amdgpu_ring_write(ring, 0x0); 5272 } 5273 } 5274 5275 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5276 { 5277 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5278 } 5279 5280 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5281 { 5282 u64 wptr; 5283 5284 /* XXX check if swapping is necessary on BE */ 5285 if (ring->use_doorbell) 5286 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5287 else 5288 BUG(); 5289 return wptr; 5290 } 5291 5292 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5293 { 5294 struct amdgpu_device *adev = ring->adev; 5295 5296 /* XXX check if swapping is necessary on BE */ 5297 if (ring->use_doorbell) { 5298 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5299 WDOORBELL64(ring->doorbell_index, ring->wptr); 5300 } else{ 5301 BUG(); /* only DOORBELL method supported on gfx9 now */ 5302 } 5303 } 5304 5305 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5306 u64 seq, unsigned int flags) 5307 { 5308 struct amdgpu_device *adev = ring->adev; 5309 5310 /* we only allocate 32bit for each seq wb address */ 5311 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5312 5313 /* write fence seq to the "addr" */ 5314 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5315 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5316 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5317 amdgpu_ring_write(ring, lower_32_bits(addr)); 5318 amdgpu_ring_write(ring, upper_32_bits(addr)); 5319 amdgpu_ring_write(ring, lower_32_bits(seq)); 5320 5321 if (flags & AMDGPU_FENCE_FLAG_INT) { 5322 /* set register to trigger INT */ 5323 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5324 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5325 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5326 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5327 amdgpu_ring_write(ring, 0); 5328 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5329 } 5330 } 5331 5332 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5333 { 5334 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5335 amdgpu_ring_write(ring, 0); 5336 } 5337 5338 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 5339 { 5340 struct amdgpu_device *adev = ring->adev; 5341 struct v9_ce_ib_state ce_payload = {0}; 5342 uint64_t offset, ce_payload_gpu_addr; 5343 void *ce_payload_cpu_addr; 5344 int cnt; 5345 5346 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5347 5348 if (ring->is_mes_queue) { 5349 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5350 gfx[0].gfx_meta_data) + 5351 offsetof(struct v9_gfx_meta_data, ce_payload); 5352 ce_payload_gpu_addr = 5353 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5354 ce_payload_cpu_addr = 5355 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5356 } else { 5357 offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5358 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5359 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5360 } 5361 5362 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5363 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5364 WRITE_DATA_DST_SEL(8) | 5365 WR_CONFIRM) | 5366 WRITE_DATA_CACHE_POLICY(0)); 5367 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5368 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5369 5370 if (resume) 5371 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5372 sizeof(ce_payload) >> 2); 5373 else 5374 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 5375 sizeof(ce_payload) >> 2); 5376 } 5377 5378 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 5379 { 5380 int i, r = 0; 5381 struct amdgpu_device *adev = ring->adev; 5382 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 5383 struct amdgpu_ring *kiq_ring = &kiq->ring; 5384 unsigned long flags; 5385 5386 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5387 return -EINVAL; 5388 5389 spin_lock_irqsave(&kiq->ring_lock, flags); 5390 5391 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5392 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5393 return -ENOMEM; 5394 } 5395 5396 /* assert preemption condition */ 5397 amdgpu_ring_set_preempt_cond_exec(ring, false); 5398 5399 ring->trail_seq += 1; 5400 amdgpu_ring_alloc(ring, 13); 5401 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5402 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5403 /*reset the CP_VMID_PREEMPT after trailing fence*/ 5404 amdgpu_ring_emit_wreg(ring, 5405 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5406 0x0); 5407 5408 /* assert IB preemption, emit the trailing fence */ 5409 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5410 ring->trail_fence_gpu_addr, 5411 ring->trail_seq); 5412 5413 amdgpu_ring_commit(kiq_ring); 5414 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5415 5416 /* poll the trailing fence */ 5417 for (i = 0; i < adev->usec_timeout; i++) { 5418 if (ring->trail_seq == 5419 le32_to_cpu(*ring->trail_fence_cpu_addr)) 5420 break; 5421 udelay(1); 5422 } 5423 5424 if (i >= adev->usec_timeout) { 5425 r = -EINVAL; 5426 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5427 } 5428 5429 amdgpu_ring_commit(ring); 5430 5431 /* deassert preemption condition */ 5432 amdgpu_ring_set_preempt_cond_exec(ring, true); 5433 return r; 5434 } 5435 5436 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5437 { 5438 struct amdgpu_device *adev = ring->adev; 5439 struct v9_de_ib_state de_payload = {0}; 5440 uint64_t offset, gds_addr, de_payload_gpu_addr; 5441 void *de_payload_cpu_addr; 5442 int cnt; 5443 5444 if (ring->is_mes_queue) { 5445 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5446 gfx[0].gfx_meta_data) + 5447 offsetof(struct v9_gfx_meta_data, de_payload); 5448 de_payload_gpu_addr = 5449 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5450 de_payload_cpu_addr = 5451 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5452 5453 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5454 gfx[0].gds_backup) + 5455 offsetof(struct v9_gfx_meta_data, de_payload); 5456 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5457 } else { 5458 offset = offsetof(struct v9_gfx_meta_data, de_payload); 5459 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5460 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5461 5462 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5463 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5464 PAGE_SIZE); 5465 } 5466 5467 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5468 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5469 5470 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5471 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5472 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5473 WRITE_DATA_DST_SEL(8) | 5474 WR_CONFIRM) | 5475 WRITE_DATA_CACHE_POLICY(0)); 5476 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5477 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5478 5479 if (resume) 5480 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5481 sizeof(de_payload) >> 2); 5482 else 5483 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5484 sizeof(de_payload) >> 2); 5485 } 5486 5487 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5488 bool secure) 5489 { 5490 uint32_t v = secure ? FRAME_TMZ : 0; 5491 5492 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5493 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5494 } 5495 5496 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5497 { 5498 uint32_t dw2 = 0; 5499 5500 gfx_v9_0_ring_emit_ce_meta(ring, 5501 (!amdgpu_sriov_vf(ring->adev) && 5502 flags & AMDGPU_IB_PREEMPTED) ? true : false); 5503 5504 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5505 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5506 /* set load_global_config & load_global_uconfig */ 5507 dw2 |= 0x8001; 5508 /* set load_cs_sh_regs */ 5509 dw2 |= 0x01000000; 5510 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5511 dw2 |= 0x10002; 5512 5513 /* set load_ce_ram if preamble presented */ 5514 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5515 dw2 |= 0x10000000; 5516 } else { 5517 /* still load_ce_ram if this is the first time preamble presented 5518 * although there is no context switch happens. 5519 */ 5520 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5521 dw2 |= 0x10000000; 5522 } 5523 5524 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5525 amdgpu_ring_write(ring, dw2); 5526 amdgpu_ring_write(ring, 0); 5527 } 5528 5529 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5530 { 5531 unsigned ret; 5532 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5533 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5534 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5535 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5536 ret = ring->wptr & ring->buf_mask; 5537 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5538 return ret; 5539 } 5540 5541 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5542 { 5543 unsigned cur; 5544 BUG_ON(offset > ring->buf_mask); 5545 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5546 5547 cur = (ring->wptr - 1) & ring->buf_mask; 5548 if (likely(cur > offset)) 5549 ring->ring[offset] = cur - offset; 5550 else 5551 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5552 } 5553 5554 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5555 uint32_t reg_val_offs) 5556 { 5557 struct amdgpu_device *adev = ring->adev; 5558 5559 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5560 amdgpu_ring_write(ring, 0 | /* src: register*/ 5561 (5 << 8) | /* dst: memory */ 5562 (1 << 20)); /* write confirm */ 5563 amdgpu_ring_write(ring, reg); 5564 amdgpu_ring_write(ring, 0); 5565 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5566 reg_val_offs * 4)); 5567 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5568 reg_val_offs * 4)); 5569 } 5570 5571 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5572 uint32_t val) 5573 { 5574 uint32_t cmd = 0; 5575 5576 switch (ring->funcs->type) { 5577 case AMDGPU_RING_TYPE_GFX: 5578 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5579 break; 5580 case AMDGPU_RING_TYPE_KIQ: 5581 cmd = (1 << 16); /* no inc addr */ 5582 break; 5583 default: 5584 cmd = WR_CONFIRM; 5585 break; 5586 } 5587 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5588 amdgpu_ring_write(ring, cmd); 5589 amdgpu_ring_write(ring, reg); 5590 amdgpu_ring_write(ring, 0); 5591 amdgpu_ring_write(ring, val); 5592 } 5593 5594 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5595 uint32_t val, uint32_t mask) 5596 { 5597 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5598 } 5599 5600 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5601 uint32_t reg0, uint32_t reg1, 5602 uint32_t ref, uint32_t mask) 5603 { 5604 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5605 struct amdgpu_device *adev = ring->adev; 5606 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5607 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5608 5609 if (fw_version_ok) 5610 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5611 ref, mask, 0x20); 5612 else 5613 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5614 ref, mask); 5615 } 5616 5617 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5618 { 5619 struct amdgpu_device *adev = ring->adev; 5620 uint32_t value = 0; 5621 5622 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5623 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5624 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5625 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5626 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5627 } 5628 5629 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5630 enum amdgpu_interrupt_state state) 5631 { 5632 switch (state) { 5633 case AMDGPU_IRQ_STATE_DISABLE: 5634 case AMDGPU_IRQ_STATE_ENABLE: 5635 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5636 TIME_STAMP_INT_ENABLE, 5637 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5638 break; 5639 default: 5640 break; 5641 } 5642 } 5643 5644 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5645 int me, int pipe, 5646 enum amdgpu_interrupt_state state) 5647 { 5648 u32 mec_int_cntl, mec_int_cntl_reg; 5649 5650 /* 5651 * amdgpu controls only the first MEC. That's why this function only 5652 * handles the setting of interrupts for this specific MEC. All other 5653 * pipes' interrupts are set by amdkfd. 5654 */ 5655 5656 if (me == 1) { 5657 switch (pipe) { 5658 case 0: 5659 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5660 break; 5661 case 1: 5662 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5663 break; 5664 case 2: 5665 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5666 break; 5667 case 3: 5668 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5669 break; 5670 default: 5671 DRM_DEBUG("invalid pipe %d\n", pipe); 5672 return; 5673 } 5674 } else { 5675 DRM_DEBUG("invalid me %d\n", me); 5676 return; 5677 } 5678 5679 switch (state) { 5680 case AMDGPU_IRQ_STATE_DISABLE: 5681 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5682 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5683 TIME_STAMP_INT_ENABLE, 0); 5684 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5685 break; 5686 case AMDGPU_IRQ_STATE_ENABLE: 5687 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5688 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5689 TIME_STAMP_INT_ENABLE, 1); 5690 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5691 break; 5692 default: 5693 break; 5694 } 5695 } 5696 5697 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5698 struct amdgpu_irq_src *source, 5699 unsigned type, 5700 enum amdgpu_interrupt_state state) 5701 { 5702 switch (state) { 5703 case AMDGPU_IRQ_STATE_DISABLE: 5704 case AMDGPU_IRQ_STATE_ENABLE: 5705 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5706 PRIV_REG_INT_ENABLE, 5707 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5708 break; 5709 default: 5710 break; 5711 } 5712 5713 return 0; 5714 } 5715 5716 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5717 struct amdgpu_irq_src *source, 5718 unsigned type, 5719 enum amdgpu_interrupt_state state) 5720 { 5721 switch (state) { 5722 case AMDGPU_IRQ_STATE_DISABLE: 5723 case AMDGPU_IRQ_STATE_ENABLE: 5724 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5725 PRIV_INSTR_INT_ENABLE, 5726 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5727 break; 5728 default: 5729 break; 5730 } 5731 5732 return 0; 5733 } 5734 5735 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5736 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5737 CP_ECC_ERROR_INT_ENABLE, 1) 5738 5739 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5740 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5741 CP_ECC_ERROR_INT_ENABLE, 0) 5742 5743 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5744 struct amdgpu_irq_src *source, 5745 unsigned type, 5746 enum amdgpu_interrupt_state state) 5747 { 5748 switch (state) { 5749 case AMDGPU_IRQ_STATE_DISABLE: 5750 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5751 CP_ECC_ERROR_INT_ENABLE, 0); 5752 DISABLE_ECC_ON_ME_PIPE(1, 0); 5753 DISABLE_ECC_ON_ME_PIPE(1, 1); 5754 DISABLE_ECC_ON_ME_PIPE(1, 2); 5755 DISABLE_ECC_ON_ME_PIPE(1, 3); 5756 break; 5757 5758 case AMDGPU_IRQ_STATE_ENABLE: 5759 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5760 CP_ECC_ERROR_INT_ENABLE, 1); 5761 ENABLE_ECC_ON_ME_PIPE(1, 0); 5762 ENABLE_ECC_ON_ME_PIPE(1, 1); 5763 ENABLE_ECC_ON_ME_PIPE(1, 2); 5764 ENABLE_ECC_ON_ME_PIPE(1, 3); 5765 break; 5766 default: 5767 break; 5768 } 5769 5770 return 0; 5771 } 5772 5773 5774 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5775 struct amdgpu_irq_src *src, 5776 unsigned type, 5777 enum amdgpu_interrupt_state state) 5778 { 5779 switch (type) { 5780 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5781 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5782 break; 5783 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5784 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5785 break; 5786 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5787 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5788 break; 5789 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5790 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5791 break; 5792 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5793 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5794 break; 5795 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5796 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5797 break; 5798 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5799 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5800 break; 5801 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5802 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5803 break; 5804 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5805 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5806 break; 5807 default: 5808 break; 5809 } 5810 return 0; 5811 } 5812 5813 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5814 struct amdgpu_irq_src *source, 5815 struct amdgpu_iv_entry *entry) 5816 { 5817 int i; 5818 u8 me_id, pipe_id, queue_id; 5819 struct amdgpu_ring *ring; 5820 5821 DRM_DEBUG("IH: CP EOP\n"); 5822 me_id = (entry->ring_id & 0x0c) >> 2; 5823 pipe_id = (entry->ring_id & 0x03) >> 0; 5824 queue_id = (entry->ring_id & 0x70) >> 4; 5825 5826 switch (me_id) { 5827 case 0: 5828 if (adev->gfx.num_gfx_rings && 5829 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { 5830 /* Fence signals are handled on the software rings*/ 5831 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 5832 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); 5833 } 5834 break; 5835 case 1: 5836 case 2: 5837 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5838 ring = &adev->gfx.compute_ring[i]; 5839 /* Per-queue interrupt is supported for MEC starting from VI. 5840 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5841 */ 5842 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5843 amdgpu_fence_process(ring); 5844 } 5845 break; 5846 } 5847 return 0; 5848 } 5849 5850 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5851 struct amdgpu_iv_entry *entry) 5852 { 5853 u8 me_id, pipe_id, queue_id; 5854 struct amdgpu_ring *ring; 5855 int i; 5856 5857 me_id = (entry->ring_id & 0x0c) >> 2; 5858 pipe_id = (entry->ring_id & 0x03) >> 0; 5859 queue_id = (entry->ring_id & 0x70) >> 4; 5860 5861 switch (me_id) { 5862 case 0: 5863 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5864 break; 5865 case 1: 5866 case 2: 5867 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5868 ring = &adev->gfx.compute_ring[i]; 5869 if (ring->me == me_id && ring->pipe == pipe_id && 5870 ring->queue == queue_id) 5871 drm_sched_fault(&ring->sched); 5872 } 5873 break; 5874 } 5875 } 5876 5877 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5878 struct amdgpu_irq_src *source, 5879 struct amdgpu_iv_entry *entry) 5880 { 5881 DRM_ERROR("Illegal register access in command stream\n"); 5882 gfx_v9_0_fault(adev, entry); 5883 return 0; 5884 } 5885 5886 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5887 struct amdgpu_irq_src *source, 5888 struct amdgpu_iv_entry *entry) 5889 { 5890 DRM_ERROR("Illegal instruction in command stream\n"); 5891 gfx_v9_0_fault(adev, entry); 5892 return 0; 5893 } 5894 5895 5896 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5897 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5898 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5899 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5900 }, 5901 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5902 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5903 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5904 }, 5905 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5906 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5907 0, 0 5908 }, 5909 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5910 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5911 0, 0 5912 }, 5913 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5914 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5915 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5916 }, 5917 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5918 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5919 0, 0 5920 }, 5921 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5922 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5923 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5924 }, 5925 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5926 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5927 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5928 }, 5929 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5930 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5931 0, 0 5932 }, 5933 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5934 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5935 0, 0 5936 }, 5937 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5938 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5939 0, 0 5940 }, 5941 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5942 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5943 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5944 }, 5945 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5946 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5947 0, 0 5948 }, 5949 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5950 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5951 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5952 }, 5953 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5954 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5955 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5956 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5957 }, 5958 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5959 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5960 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5961 0, 0 5962 }, 5963 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5964 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5965 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5966 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5967 }, 5968 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5969 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5970 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5971 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5972 }, 5973 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5974 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5975 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5976 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5977 }, 5978 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5979 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5980 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5981 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5982 }, 5983 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5984 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5985 0, 0 5986 }, 5987 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5988 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5989 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5990 }, 5991 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5992 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5993 0, 0 5994 }, 5995 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5996 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5997 0, 0 5998 }, 5999 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6000 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 6001 0, 0 6002 }, 6003 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6004 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 6005 0, 0 6006 }, 6007 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6008 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 6009 0, 0 6010 }, 6011 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6012 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 6013 0, 0 6014 }, 6015 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6016 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 6017 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 6018 }, 6019 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6020 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 6021 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 6022 }, 6023 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6024 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 6025 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 6026 }, 6027 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6028 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6029 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6030 }, 6031 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6032 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6033 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6034 }, 6035 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6036 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6037 0, 0 6038 }, 6039 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6040 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6041 0, 0 6042 }, 6043 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6044 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6045 0, 0 6046 }, 6047 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6048 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6049 0, 0 6050 }, 6051 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6052 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6053 0, 0 6054 }, 6055 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6056 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6057 0, 0 6058 }, 6059 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6060 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6061 0, 0 6062 }, 6063 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6064 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6065 0, 0 6066 }, 6067 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6068 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6069 0, 0 6070 }, 6071 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6072 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6073 0, 0 6074 }, 6075 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6076 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6077 0, 0 6078 }, 6079 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6080 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6081 0, 0 6082 }, 6083 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6084 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6085 0, 0 6086 }, 6087 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6088 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6089 0, 0 6090 }, 6091 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6092 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6093 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6094 }, 6095 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6096 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6097 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6098 }, 6099 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6100 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6101 0, 0 6102 }, 6103 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6104 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6105 0, 0 6106 }, 6107 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6108 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6109 0, 0 6110 }, 6111 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6112 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6113 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6114 }, 6115 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6116 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6117 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6118 }, 6119 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6120 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6121 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6122 }, 6123 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6124 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6125 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6126 }, 6127 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6128 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6129 0, 0 6130 }, 6131 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6132 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6133 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6134 }, 6135 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6136 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6137 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6138 }, 6139 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6140 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6141 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6142 }, 6143 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6144 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6145 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6146 }, 6147 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6148 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6149 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6150 }, 6151 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6152 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6153 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6154 }, 6155 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6156 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6157 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6158 }, 6159 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6160 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6161 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6162 }, 6163 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6164 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6165 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6166 }, 6167 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6168 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6169 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6170 }, 6171 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6172 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6173 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6174 }, 6175 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6176 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6177 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6178 }, 6179 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6180 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6181 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6182 }, 6183 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6184 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6185 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6186 }, 6187 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6188 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6189 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6190 }, 6191 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6192 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6193 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6194 }, 6195 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6196 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6197 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6198 }, 6199 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6200 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6201 0, 0 6202 }, 6203 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6204 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6205 0, 0 6206 }, 6207 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6208 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6209 0, 0 6210 }, 6211 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6212 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6213 0, 0 6214 }, 6215 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6216 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6217 0, 0 6218 }, 6219 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6220 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6221 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6222 }, 6223 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6224 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6225 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6226 }, 6227 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6228 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6229 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6230 }, 6231 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6232 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6233 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6234 }, 6235 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6236 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6237 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6238 }, 6239 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6240 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6241 0, 0 6242 }, 6243 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6244 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6245 0, 0 6246 }, 6247 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6248 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6249 0, 0 6250 }, 6251 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6252 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6253 0, 0 6254 }, 6255 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6256 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6257 0, 0 6258 }, 6259 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6260 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6261 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6262 }, 6263 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6264 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6265 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6266 }, 6267 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6268 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6269 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6270 }, 6271 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6272 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6273 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6274 }, 6275 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6276 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6277 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6278 }, 6279 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6280 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6281 0, 0 6282 }, 6283 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6284 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6285 0, 0 6286 }, 6287 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6288 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6289 0, 0 6290 }, 6291 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6292 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6293 0, 0 6294 }, 6295 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6296 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6297 0, 0 6298 }, 6299 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6300 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6301 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6302 }, 6303 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6304 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6305 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6306 }, 6307 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6308 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6309 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6310 }, 6311 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6312 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6313 0, 0 6314 }, 6315 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6316 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6317 0, 0 6318 }, 6319 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6320 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6321 0, 0 6322 }, 6323 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6324 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6325 0, 0 6326 }, 6327 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6328 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6329 0, 0 6330 }, 6331 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6332 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6333 0, 0 6334 } 6335 }; 6336 6337 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6338 void *inject_if) 6339 { 6340 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6341 int ret; 6342 struct ta_ras_trigger_error_input block_info = { 0 }; 6343 6344 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6345 return -EINVAL; 6346 6347 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6348 return -EINVAL; 6349 6350 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6351 return -EPERM; 6352 6353 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6354 info->head.type)) { 6355 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6356 ras_gfx_subblocks[info->head.sub_block_index].name, 6357 info->head.type); 6358 return -EPERM; 6359 } 6360 6361 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6362 info->head.type)) { 6363 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6364 ras_gfx_subblocks[info->head.sub_block_index].name, 6365 info->head.type); 6366 return -EPERM; 6367 } 6368 6369 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6370 block_info.sub_block_index = 6371 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6372 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6373 block_info.address = info->address; 6374 block_info.value = info->value; 6375 6376 mutex_lock(&adev->grbm_idx_mutex); 6377 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6378 mutex_unlock(&adev->grbm_idx_mutex); 6379 6380 return ret; 6381 } 6382 6383 static const char *vml2_mems[] = { 6384 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6385 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6386 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6387 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6388 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6389 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6390 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6391 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6392 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6393 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6394 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6395 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6396 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6397 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6398 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6399 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6400 }; 6401 6402 static const char *vml2_walker_mems[] = { 6403 "UTC_VML2_CACHE_PDE0_MEM0", 6404 "UTC_VML2_CACHE_PDE0_MEM1", 6405 "UTC_VML2_CACHE_PDE1_MEM0", 6406 "UTC_VML2_CACHE_PDE1_MEM1", 6407 "UTC_VML2_CACHE_PDE2_MEM0", 6408 "UTC_VML2_CACHE_PDE2_MEM1", 6409 "UTC_VML2_RDIF_LOG_FIFO", 6410 }; 6411 6412 static const char *atc_l2_cache_2m_mems[] = { 6413 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6414 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6415 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6416 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6417 }; 6418 6419 static const char *atc_l2_cache_4k_mems[] = { 6420 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6421 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6422 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6423 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6424 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6425 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6426 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6427 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6428 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6429 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6430 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6431 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6432 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6433 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6434 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6435 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6436 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6437 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6438 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6439 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6440 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6441 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6442 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6443 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6444 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6445 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6446 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6447 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6448 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6449 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6450 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6451 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6452 }; 6453 6454 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6455 struct ras_err_data *err_data) 6456 { 6457 uint32_t i, data; 6458 uint32_t sec_count, ded_count; 6459 6460 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6461 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6462 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6463 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6464 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6465 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6466 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6467 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6468 6469 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6470 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6471 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6472 6473 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6474 if (sec_count) { 6475 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6476 "SEC %d\n", i, vml2_mems[i], sec_count); 6477 err_data->ce_count += sec_count; 6478 } 6479 6480 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6481 if (ded_count) { 6482 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6483 "DED %d\n", i, vml2_mems[i], ded_count); 6484 err_data->ue_count += ded_count; 6485 } 6486 } 6487 6488 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6489 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6490 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6491 6492 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6493 SEC_COUNT); 6494 if (sec_count) { 6495 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6496 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6497 err_data->ce_count += sec_count; 6498 } 6499 6500 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6501 DED_COUNT); 6502 if (ded_count) { 6503 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6504 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6505 err_data->ue_count += ded_count; 6506 } 6507 } 6508 6509 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6510 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6511 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6512 6513 sec_count = (data & 0x00006000L) >> 0xd; 6514 if (sec_count) { 6515 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6516 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6517 sec_count); 6518 err_data->ce_count += sec_count; 6519 } 6520 } 6521 6522 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6523 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6524 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6525 6526 sec_count = (data & 0x00006000L) >> 0xd; 6527 if (sec_count) { 6528 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6529 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6530 sec_count); 6531 err_data->ce_count += sec_count; 6532 } 6533 6534 ded_count = (data & 0x00018000L) >> 0xf; 6535 if (ded_count) { 6536 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6537 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6538 ded_count); 6539 err_data->ue_count += ded_count; 6540 } 6541 } 6542 6543 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6544 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6545 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6546 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6547 6548 return 0; 6549 } 6550 6551 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6552 const struct soc15_reg_entry *reg, 6553 uint32_t se_id, uint32_t inst_id, uint32_t value, 6554 uint32_t *sec_count, uint32_t *ded_count) 6555 { 6556 uint32_t i; 6557 uint32_t sec_cnt, ded_cnt; 6558 6559 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6560 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6561 gfx_v9_0_ras_fields[i].seg != reg->seg || 6562 gfx_v9_0_ras_fields[i].inst != reg->inst) 6563 continue; 6564 6565 sec_cnt = (value & 6566 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6567 gfx_v9_0_ras_fields[i].sec_count_shift; 6568 if (sec_cnt) { 6569 dev_info(adev->dev, "GFX SubBlock %s, " 6570 "Instance[%d][%d], SEC %d\n", 6571 gfx_v9_0_ras_fields[i].name, 6572 se_id, inst_id, 6573 sec_cnt); 6574 *sec_count += sec_cnt; 6575 } 6576 6577 ded_cnt = (value & 6578 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6579 gfx_v9_0_ras_fields[i].ded_count_shift; 6580 if (ded_cnt) { 6581 dev_info(adev->dev, "GFX SubBlock %s, " 6582 "Instance[%d][%d], DED %d\n", 6583 gfx_v9_0_ras_fields[i].name, 6584 se_id, inst_id, 6585 ded_cnt); 6586 *ded_count += ded_cnt; 6587 } 6588 } 6589 6590 return 0; 6591 } 6592 6593 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6594 { 6595 int i, j, k; 6596 6597 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6598 return; 6599 6600 /* read back registers to clear the counters */ 6601 mutex_lock(&adev->grbm_idx_mutex); 6602 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6603 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6604 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6605 amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0); 6606 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6607 } 6608 } 6609 } 6610 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6611 mutex_unlock(&adev->grbm_idx_mutex); 6612 6613 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6614 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6615 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6616 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6617 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6618 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6619 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6620 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6621 6622 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6623 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6624 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6625 } 6626 6627 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6628 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6629 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6630 } 6631 6632 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6633 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6634 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6635 } 6636 6637 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6638 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6639 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6640 } 6641 6642 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6643 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6644 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6645 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6646 } 6647 6648 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6649 void *ras_error_status) 6650 { 6651 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6652 uint32_t sec_count = 0, ded_count = 0; 6653 uint32_t i, j, k; 6654 uint32_t reg_value; 6655 6656 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6657 return; 6658 6659 err_data->ue_count = 0; 6660 err_data->ce_count = 0; 6661 6662 mutex_lock(&adev->grbm_idx_mutex); 6663 6664 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6665 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6666 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6667 amdgpu_gfx_select_se_sh(adev, j, 0, k, 0); 6668 reg_value = 6669 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6670 if (reg_value) 6671 gfx_v9_0_ras_error_count(adev, 6672 &gfx_v9_0_edc_counter_regs[i], 6673 j, k, reg_value, 6674 &sec_count, &ded_count); 6675 } 6676 } 6677 } 6678 6679 err_data->ce_count += sec_count; 6680 err_data->ue_count += ded_count; 6681 6682 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6683 mutex_unlock(&adev->grbm_idx_mutex); 6684 6685 gfx_v9_0_query_utc_edc_status(adev, err_data); 6686 } 6687 6688 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6689 { 6690 const unsigned int cp_coher_cntl = 6691 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6692 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6693 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6694 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6695 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6696 6697 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6698 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6699 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6700 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6701 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6702 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6703 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6704 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6705 } 6706 6707 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6708 uint32_t pipe, bool enable) 6709 { 6710 struct amdgpu_device *adev = ring->adev; 6711 uint32_t val; 6712 uint32_t wcl_cs_reg; 6713 6714 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6715 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6716 6717 switch (pipe) { 6718 case 0: 6719 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6720 break; 6721 case 1: 6722 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6723 break; 6724 case 2: 6725 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6726 break; 6727 case 3: 6728 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6729 break; 6730 default: 6731 DRM_DEBUG("invalid pipe %d\n", pipe); 6732 return; 6733 } 6734 6735 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6736 6737 } 6738 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6739 { 6740 struct amdgpu_device *adev = ring->adev; 6741 uint32_t val; 6742 int i; 6743 6744 6745 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6746 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6747 * around 25% of gpu resources. 6748 */ 6749 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6750 amdgpu_ring_emit_wreg(ring, 6751 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6752 val); 6753 6754 /* Restrict waves for normal/low priority compute queues as well 6755 * to get best QoS for high priority compute jobs. 6756 * 6757 * amdgpu controls only 1st ME(0-3 CS pipes). 6758 */ 6759 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6760 if (i != ring->pipe) 6761 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6762 6763 } 6764 } 6765 6766 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6767 .name = "gfx_v9_0", 6768 .early_init = gfx_v9_0_early_init, 6769 .late_init = gfx_v9_0_late_init, 6770 .sw_init = gfx_v9_0_sw_init, 6771 .sw_fini = gfx_v9_0_sw_fini, 6772 .hw_init = gfx_v9_0_hw_init, 6773 .hw_fini = gfx_v9_0_hw_fini, 6774 .suspend = gfx_v9_0_suspend, 6775 .resume = gfx_v9_0_resume, 6776 .is_idle = gfx_v9_0_is_idle, 6777 .wait_for_idle = gfx_v9_0_wait_for_idle, 6778 .soft_reset = gfx_v9_0_soft_reset, 6779 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6780 .set_powergating_state = gfx_v9_0_set_powergating_state, 6781 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6782 }; 6783 6784 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6785 .type = AMDGPU_RING_TYPE_GFX, 6786 .align_mask = 0xff, 6787 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6788 .support_64bit_ptrs = true, 6789 .secure_submission_supported = true, 6790 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6791 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6792 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6793 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6794 5 + /* COND_EXEC */ 6795 7 + /* PIPELINE_SYNC */ 6796 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6797 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6798 2 + /* VM_FLUSH */ 6799 8 + /* FENCE for VM_FLUSH */ 6800 20 + /* GDS switch */ 6801 4 + /* double SWITCH_BUFFER, 6802 the first COND_EXEC jump to the place just 6803 prior to this double SWITCH_BUFFER */ 6804 5 + /* COND_EXEC */ 6805 7 + /* HDP_flush */ 6806 4 + /* VGT_flush */ 6807 14 + /* CE_META */ 6808 31 + /* DE_META */ 6809 3 + /* CNTX_CTRL */ 6810 5 + /* HDP_INVL */ 6811 8 + 8 + /* FENCE x2 */ 6812 2 + /* SWITCH_BUFFER */ 6813 7, /* gfx_v9_0_emit_mem_sync */ 6814 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6815 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6816 .emit_fence = gfx_v9_0_ring_emit_fence, 6817 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6818 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6819 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6820 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6821 .test_ring = gfx_v9_0_ring_test_ring, 6822 .insert_nop = amdgpu_ring_insert_nop, 6823 .pad_ib = amdgpu_ring_generic_pad_ib, 6824 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6825 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6826 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6827 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6828 .preempt_ib = gfx_v9_0_ring_preempt_ib, 6829 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6830 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6831 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6832 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6833 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6834 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6835 }; 6836 6837 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 6838 .type = AMDGPU_RING_TYPE_GFX, 6839 .align_mask = 0xff, 6840 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6841 .support_64bit_ptrs = true, 6842 .secure_submission_supported = true, 6843 .get_rptr = amdgpu_sw_ring_get_rptr_gfx, 6844 .get_wptr = amdgpu_sw_ring_get_wptr_gfx, 6845 .set_wptr = amdgpu_sw_ring_set_wptr_gfx, 6846 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6847 5 + /* COND_EXEC */ 6848 7 + /* PIPELINE_SYNC */ 6849 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6850 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6851 2 + /* VM_FLUSH */ 6852 8 + /* FENCE for VM_FLUSH */ 6853 20 + /* GDS switch */ 6854 4 + /* double SWITCH_BUFFER, 6855 * the first COND_EXEC jump to the place just 6856 * prior to this double SWITCH_BUFFER 6857 */ 6858 5 + /* COND_EXEC */ 6859 7 + /* HDP_flush */ 6860 4 + /* VGT_flush */ 6861 14 + /* CE_META */ 6862 31 + /* DE_META */ 6863 3 + /* CNTX_CTRL */ 6864 5 + /* HDP_INVL */ 6865 8 + 8 + /* FENCE x2 */ 6866 2 + /* SWITCH_BUFFER */ 6867 7, /* gfx_v9_0_emit_mem_sync */ 6868 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6869 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6870 .emit_fence = gfx_v9_0_ring_emit_fence, 6871 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6872 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6873 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6874 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6875 .test_ring = gfx_v9_0_ring_test_ring, 6876 .test_ib = gfx_v9_0_ring_test_ib, 6877 .insert_nop = amdgpu_sw_ring_insert_nop, 6878 .pad_ib = amdgpu_ring_generic_pad_ib, 6879 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6880 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6881 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6882 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6883 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6884 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6885 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6886 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6887 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6888 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6889 }; 6890 6891 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6892 .type = AMDGPU_RING_TYPE_COMPUTE, 6893 .align_mask = 0xff, 6894 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6895 .support_64bit_ptrs = true, 6896 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6897 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6898 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6899 .emit_frame_size = 6900 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6901 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6902 5 + /* hdp invalidate */ 6903 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6904 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6905 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6906 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6907 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6908 7 + /* gfx_v9_0_emit_mem_sync */ 6909 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6910 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6911 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6912 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6913 .emit_fence = gfx_v9_0_ring_emit_fence, 6914 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6915 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6916 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6917 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6918 .test_ring = gfx_v9_0_ring_test_ring, 6919 .test_ib = gfx_v9_0_ring_test_ib, 6920 .insert_nop = amdgpu_ring_insert_nop, 6921 .pad_ib = amdgpu_ring_generic_pad_ib, 6922 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6923 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6924 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6925 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6926 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6927 }; 6928 6929 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6930 .type = AMDGPU_RING_TYPE_KIQ, 6931 .align_mask = 0xff, 6932 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6933 .support_64bit_ptrs = true, 6934 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6935 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6936 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6937 .emit_frame_size = 6938 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6939 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6940 5 + /* hdp invalidate */ 6941 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6942 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6943 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6944 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6945 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6946 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6947 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6948 .test_ring = gfx_v9_0_ring_test_ring, 6949 .insert_nop = amdgpu_ring_insert_nop, 6950 .pad_ib = amdgpu_ring_generic_pad_ib, 6951 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6952 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6953 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6954 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6955 }; 6956 6957 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6958 { 6959 int i; 6960 6961 adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6962 6963 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6964 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6965 6966 if (adev->gfx.num_gfx_rings) { 6967 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 6968 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; 6969 } 6970 6971 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6972 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6973 } 6974 6975 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6976 .set = gfx_v9_0_set_eop_interrupt_state, 6977 .process = gfx_v9_0_eop_irq, 6978 }; 6979 6980 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6981 .set = gfx_v9_0_set_priv_reg_fault_state, 6982 .process = gfx_v9_0_priv_reg_irq, 6983 }; 6984 6985 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6986 .set = gfx_v9_0_set_priv_inst_fault_state, 6987 .process = gfx_v9_0_priv_inst_irq, 6988 }; 6989 6990 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6991 .set = gfx_v9_0_set_cp_ecc_error_state, 6992 .process = amdgpu_gfx_cp_ecc_error_irq, 6993 }; 6994 6995 6996 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6997 { 6998 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6999 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 7000 7001 adev->gfx.priv_reg_irq.num_types = 1; 7002 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 7003 7004 adev->gfx.priv_inst_irq.num_types = 1; 7005 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 7006 7007 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 7008 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 7009 } 7010 7011 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 7012 { 7013 switch (adev->ip_versions[GC_HWIP][0]) { 7014 case IP_VERSION(9, 0, 1): 7015 case IP_VERSION(9, 2, 1): 7016 case IP_VERSION(9, 4, 0): 7017 case IP_VERSION(9, 2, 2): 7018 case IP_VERSION(9, 1, 0): 7019 case IP_VERSION(9, 4, 1): 7020 case IP_VERSION(9, 3, 0): 7021 case IP_VERSION(9, 4, 2): 7022 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 7023 break; 7024 default: 7025 break; 7026 } 7027 } 7028 7029 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 7030 { 7031 /* init asci gds info */ 7032 switch (adev->ip_versions[GC_HWIP][0]) { 7033 case IP_VERSION(9, 0, 1): 7034 case IP_VERSION(9, 2, 1): 7035 case IP_VERSION(9, 4, 0): 7036 adev->gds.gds_size = 0x10000; 7037 break; 7038 case IP_VERSION(9, 2, 2): 7039 case IP_VERSION(9, 1, 0): 7040 case IP_VERSION(9, 4, 1): 7041 adev->gds.gds_size = 0x1000; 7042 break; 7043 case IP_VERSION(9, 4, 2): 7044 /* aldebaran removed all the GDS internal memory, 7045 * only support GWS opcode in kernel, like barrier 7046 * semaphore.etc */ 7047 adev->gds.gds_size = 0; 7048 break; 7049 default: 7050 adev->gds.gds_size = 0x10000; 7051 break; 7052 } 7053 7054 switch (adev->ip_versions[GC_HWIP][0]) { 7055 case IP_VERSION(9, 0, 1): 7056 case IP_VERSION(9, 4, 0): 7057 adev->gds.gds_compute_max_wave_id = 0x7ff; 7058 break; 7059 case IP_VERSION(9, 2, 1): 7060 adev->gds.gds_compute_max_wave_id = 0x27f; 7061 break; 7062 case IP_VERSION(9, 2, 2): 7063 case IP_VERSION(9, 1, 0): 7064 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 7065 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 7066 else 7067 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 7068 break; 7069 case IP_VERSION(9, 4, 1): 7070 adev->gds.gds_compute_max_wave_id = 0xfff; 7071 break; 7072 case IP_VERSION(9, 4, 2): 7073 /* deprecated for Aldebaran, no usage at all */ 7074 adev->gds.gds_compute_max_wave_id = 0; 7075 break; 7076 default: 7077 /* this really depends on the chip */ 7078 adev->gds.gds_compute_max_wave_id = 0x7ff; 7079 break; 7080 } 7081 7082 adev->gds.gws_size = 64; 7083 adev->gds.oa_size = 16; 7084 } 7085 7086 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7087 u32 bitmap) 7088 { 7089 u32 data; 7090 7091 if (!bitmap) 7092 return; 7093 7094 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7095 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7096 7097 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7098 } 7099 7100 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7101 { 7102 u32 data, mask; 7103 7104 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7105 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7106 7107 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7108 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7109 7110 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7111 7112 return (~data) & mask; 7113 } 7114 7115 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7116 struct amdgpu_cu_info *cu_info) 7117 { 7118 int i, j, k, counter, active_cu_number = 0; 7119 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7120 unsigned disable_masks[4 * 4]; 7121 7122 if (!adev || !cu_info) 7123 return -EINVAL; 7124 7125 /* 7126 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7127 */ 7128 if (adev->gfx.config.max_shader_engines * 7129 adev->gfx.config.max_sh_per_se > 16) 7130 return -EINVAL; 7131 7132 amdgpu_gfx_parse_disable_cu(disable_masks, 7133 adev->gfx.config.max_shader_engines, 7134 adev->gfx.config.max_sh_per_se); 7135 7136 mutex_lock(&adev->grbm_idx_mutex); 7137 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7138 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7139 mask = 1; 7140 ao_bitmap = 0; 7141 counter = 0; 7142 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 7143 gfx_v9_0_set_user_cu_inactive_bitmap( 7144 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7145 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7146 7147 /* 7148 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7149 * 4x4 size array, and it's usually suitable for Vega 7150 * ASICs which has 4*2 SE/SH layout. 7151 * But for Arcturus, SE/SH layout is changed to 8*1. 7152 * To mostly reduce the impact, we make it compatible 7153 * with current bitmap array as below: 7154 * SE4,SH0 --> bitmap[0][1] 7155 * SE5,SH0 --> bitmap[1][1] 7156 * SE6,SH0 --> bitmap[2][1] 7157 * SE7,SH0 --> bitmap[3][1] 7158 */ 7159 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 7160 7161 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7162 if (bitmap & mask) { 7163 if (counter < adev->gfx.config.max_cu_per_sh) 7164 ao_bitmap |= mask; 7165 counter ++; 7166 } 7167 mask <<= 1; 7168 } 7169 active_cu_number += counter; 7170 if (i < 2 && j < 2) 7171 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7172 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7173 } 7174 } 7175 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7176 mutex_unlock(&adev->grbm_idx_mutex); 7177 7178 cu_info->number = active_cu_number; 7179 cu_info->ao_cu_mask = ao_cu_mask; 7180 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7181 7182 return 0; 7183 } 7184 7185 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7186 { 7187 .type = AMD_IP_BLOCK_TYPE_GFX, 7188 .major = 9, 7189 .minor = 0, 7190 .rev = 0, 7191 .funcs = &gfx_v9_0_ip_funcs, 7192 }; 7193