1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "amdgpu_ring_mux.h" 51 #include "gfx_v9_4.h" 52 #include "gfx_v9_0.h" 53 #include "gfx_v9_4_2.h" 54 55 #include "asic_reg/pwr/pwr_10_0_offset.h" 56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 57 #include "asic_reg/gc/gc_9_0_default.h" 58 59 #define GFX9_NUM_GFX_RINGS 1 60 #define GFX9_NUM_SW_GFX_RINGS 2 61 #define GFX9_MEC_HPD_SIZE 4096 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 114 115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 127 128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 133 134 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 144 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 146 147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 151 152 #define mmGOLDEN_TSC_COUNT_UPPER_Raven 0x007a 153 #define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0 154 #define mmGOLDEN_TSC_COUNT_LOWER_Raven 0x007b 155 #define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0 156 157 #define mmGOLDEN_TSC_COUNT_UPPER_Raven2 0x0068 158 #define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0 159 #define mmGOLDEN_TSC_COUNT_LOWER_Raven2 0x0069 160 #define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0 161 162 enum ta_ras_gfx_subblock { 163 /*CPC*/ 164 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 165 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 166 TA_RAS_BLOCK__GFX_CPC_UCODE, 167 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 168 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 169 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 170 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 171 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 172 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 173 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 174 /* CPF*/ 175 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 176 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 177 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 178 TA_RAS_BLOCK__GFX_CPF_TAG, 179 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 180 /* CPG*/ 181 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 182 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 183 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 184 TA_RAS_BLOCK__GFX_CPG_TAG, 185 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 186 /* GDS*/ 187 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 188 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 189 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 190 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 191 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 192 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 193 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 194 /* SPI*/ 195 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 196 /* SQ*/ 197 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 198 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 199 TA_RAS_BLOCK__GFX_SQ_LDS_D, 200 TA_RAS_BLOCK__GFX_SQ_LDS_I, 201 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 202 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 203 /* SQC (3 ranges)*/ 204 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 205 /* SQC range 0*/ 206 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 207 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 208 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 209 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 210 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 211 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 212 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 213 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 214 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 215 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 216 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 217 /* SQC range 1*/ 218 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 219 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 220 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 221 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 222 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 223 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 224 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 225 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 226 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 227 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 228 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 229 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 230 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 231 /* SQC range 2*/ 232 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 233 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 234 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 235 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 236 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 237 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 238 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 239 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 240 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 241 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 242 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 243 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 244 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 245 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 246 /* TA*/ 247 TA_RAS_BLOCK__GFX_TA_INDEX_START, 248 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 249 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 250 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 251 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 252 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 253 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 254 /* TCA*/ 255 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 256 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 257 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 258 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 259 /* TCC (5 sub-ranges)*/ 260 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 261 /* TCC range 0*/ 262 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 263 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 264 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 265 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 266 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 267 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 268 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 269 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 270 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 271 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 272 /* TCC range 1*/ 273 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 274 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 275 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 276 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 277 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 278 /* TCC range 2*/ 279 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 280 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 281 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 282 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 283 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 284 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 285 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 286 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 287 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 288 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 289 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 290 /* TCC range 3*/ 291 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 292 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 293 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 294 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 295 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 296 /* TCC range 4*/ 297 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 298 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 299 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 300 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 301 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 302 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 303 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 304 /* TCI*/ 305 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 306 /* TCP*/ 307 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 308 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 309 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 310 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 311 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 312 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 313 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 314 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 315 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 316 /* TD*/ 317 TA_RAS_BLOCK__GFX_TD_INDEX_START, 318 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 319 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 320 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 321 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 322 /* EA (3 sub-ranges)*/ 323 TA_RAS_BLOCK__GFX_EA_INDEX_START, 324 /* EA range 0*/ 325 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 326 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 327 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 328 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 329 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 330 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 331 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 332 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 333 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 334 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 335 /* EA range 1*/ 336 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 337 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 338 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 339 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 340 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 341 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 342 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 343 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 344 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 345 /* EA range 2*/ 346 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 347 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 348 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 349 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 350 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 351 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 352 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 353 /* UTC VM L2 bank*/ 354 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 355 /* UTC VM walker*/ 356 TA_RAS_BLOCK__UTC_VML2_WALKER, 357 /* UTC ATC L2 2MB cache*/ 358 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 359 /* UTC ATC L2 4KB cache*/ 360 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 361 TA_RAS_BLOCK__GFX_MAX 362 }; 363 364 struct ras_gfx_subblock { 365 unsigned char *name; 366 int ta_subblock; 367 int hw_supported_error_type; 368 int sw_supported_error_type; 369 }; 370 371 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 372 [AMDGPU_RAS_BLOCK__##subblock] = { \ 373 #subblock, \ 374 TA_RAS_BLOCK__##subblock, \ 375 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 376 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 377 } 378 379 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 380 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 382 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 383 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 384 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 386 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 387 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 388 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 390 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 391 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 392 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 393 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 394 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 395 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 396 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 397 0), 398 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 399 0), 400 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 402 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 404 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 406 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 408 0, 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 410 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 412 0, 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 416 0, 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 420 1), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 422 0, 0, 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 430 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 432 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 434 0, 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 436 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 438 0), 439 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 440 0, 0, 0), 441 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 442 0), 443 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 446 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 448 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 450 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 452 0, 0), 453 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 454 0), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 456 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 458 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 460 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 462 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 464 1), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 466 1), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 468 1), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 470 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 472 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 478 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 480 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 485 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 488 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 490 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 492 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 495 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 502 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 510 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 511 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 512 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 513 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 515 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 516 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 517 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 518 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 519 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 520 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 521 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 522 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 523 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 524 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 525 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 526 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 527 }; 528 529 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 530 { 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 551 }; 552 553 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 554 { 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 573 }; 574 575 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 576 { 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 588 }; 589 590 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 591 { 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 616 }; 617 618 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 619 { 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 627 }; 628 629 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 630 { 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 650 }; 651 652 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 653 { 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 666 }; 667 668 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 669 { 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 673 }; 674 675 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 676 { 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 693 }; 694 695 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 696 { 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 710 }; 711 712 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 713 { 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 725 }; 726 727 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 728 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 729 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 730 }; 731 732 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 733 { 734 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 735 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 736 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 737 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 738 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 739 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 740 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 741 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 742 }; 743 744 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 745 { 746 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 747 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 748 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 749 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 750 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 751 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 752 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 753 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 754 }; 755 756 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 757 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 758 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 759 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 760 761 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 762 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 763 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 764 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 765 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 766 struct amdgpu_cu_info *cu_info); 767 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 768 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 769 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 770 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 771 void *ras_error_status); 772 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 773 void *inject_if); 774 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 775 776 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 777 uint64_t queue_mask) 778 { 779 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 780 amdgpu_ring_write(kiq_ring, 781 PACKET3_SET_RESOURCES_VMID_MASK(0) | 782 /* vmid_mask:0* queue_type:0 (KIQ) */ 783 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 784 amdgpu_ring_write(kiq_ring, 785 lower_32_bits(queue_mask)); /* queue mask lo */ 786 amdgpu_ring_write(kiq_ring, 787 upper_32_bits(queue_mask)); /* queue mask hi */ 788 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 789 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 790 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 791 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 792 } 793 794 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 795 struct amdgpu_ring *ring) 796 { 797 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 798 uint64_t wptr_addr = ring->wptr_gpu_addr; 799 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 800 801 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 802 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 803 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 804 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 805 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 806 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 807 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 808 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 809 /*queue_type: normal compute queue */ 810 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 811 /* alloc format: all_on_one_pipe */ 812 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 813 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 814 /* num_queues: must be 1 */ 815 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 816 amdgpu_ring_write(kiq_ring, 817 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 818 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 819 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 820 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 821 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 822 } 823 824 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 825 struct amdgpu_ring *ring, 826 enum amdgpu_unmap_queues_action action, 827 u64 gpu_addr, u64 seq) 828 { 829 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 830 831 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 832 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 833 PACKET3_UNMAP_QUEUES_ACTION(action) | 834 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 835 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 836 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 837 amdgpu_ring_write(kiq_ring, 838 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 839 840 if (action == PREEMPT_QUEUES_NO_UNMAP) { 841 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 842 amdgpu_ring_write(kiq_ring, 0); 843 amdgpu_ring_write(kiq_ring, 0); 844 845 } else { 846 amdgpu_ring_write(kiq_ring, 0); 847 amdgpu_ring_write(kiq_ring, 0); 848 amdgpu_ring_write(kiq_ring, 0); 849 } 850 } 851 852 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 853 struct amdgpu_ring *ring, 854 u64 addr, 855 u64 seq) 856 { 857 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 858 859 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 860 amdgpu_ring_write(kiq_ring, 861 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 862 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 863 PACKET3_QUERY_STATUS_COMMAND(2)); 864 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 865 amdgpu_ring_write(kiq_ring, 866 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 867 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 868 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 869 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 870 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 871 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 872 } 873 874 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 875 uint16_t pasid, uint32_t flush_type, 876 bool all_hub) 877 { 878 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 879 amdgpu_ring_write(kiq_ring, 880 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 881 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 882 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 883 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 884 } 885 886 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 887 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 888 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 889 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 890 .kiq_query_status = gfx_v9_0_kiq_query_status, 891 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 892 .set_resources_size = 8, 893 .map_queues_size = 7, 894 .unmap_queues_size = 6, 895 .query_status_size = 7, 896 .invalidate_tlbs_size = 2, 897 }; 898 899 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 900 { 901 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 902 } 903 904 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 905 { 906 switch (adev->ip_versions[GC_HWIP][0]) { 907 case IP_VERSION(9, 0, 1): 908 soc15_program_register_sequence(adev, 909 golden_settings_gc_9_0, 910 ARRAY_SIZE(golden_settings_gc_9_0)); 911 soc15_program_register_sequence(adev, 912 golden_settings_gc_9_0_vg10, 913 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 914 break; 915 case IP_VERSION(9, 2, 1): 916 soc15_program_register_sequence(adev, 917 golden_settings_gc_9_2_1, 918 ARRAY_SIZE(golden_settings_gc_9_2_1)); 919 soc15_program_register_sequence(adev, 920 golden_settings_gc_9_2_1_vg12, 921 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 922 break; 923 case IP_VERSION(9, 4, 0): 924 soc15_program_register_sequence(adev, 925 golden_settings_gc_9_0, 926 ARRAY_SIZE(golden_settings_gc_9_0)); 927 soc15_program_register_sequence(adev, 928 golden_settings_gc_9_0_vg20, 929 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 930 break; 931 case IP_VERSION(9, 4, 1): 932 soc15_program_register_sequence(adev, 933 golden_settings_gc_9_4_1_arct, 934 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 935 break; 936 case IP_VERSION(9, 2, 2): 937 case IP_VERSION(9, 1, 0): 938 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 939 ARRAY_SIZE(golden_settings_gc_9_1)); 940 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 941 soc15_program_register_sequence(adev, 942 golden_settings_gc_9_1_rv2, 943 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 944 else 945 soc15_program_register_sequence(adev, 946 golden_settings_gc_9_1_rv1, 947 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 948 break; 949 case IP_VERSION(9, 3, 0): 950 soc15_program_register_sequence(adev, 951 golden_settings_gc_9_1_rn, 952 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 953 return; /* for renoir, don't need common goldensetting */ 954 case IP_VERSION(9, 4, 2): 955 gfx_v9_4_2_init_golden_registers(adev, 956 adev->smuio.funcs->get_die_id(adev)); 957 break; 958 default: 959 break; 960 } 961 962 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 963 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) 964 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 965 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 966 } 967 968 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 969 bool wc, uint32_t reg, uint32_t val) 970 { 971 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 972 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 973 WRITE_DATA_DST_SEL(0) | 974 (wc ? WR_CONFIRM : 0)); 975 amdgpu_ring_write(ring, reg); 976 amdgpu_ring_write(ring, 0); 977 amdgpu_ring_write(ring, val); 978 } 979 980 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 981 int mem_space, int opt, uint32_t addr0, 982 uint32_t addr1, uint32_t ref, uint32_t mask, 983 uint32_t inv) 984 { 985 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 986 amdgpu_ring_write(ring, 987 /* memory (1) or register (0) */ 988 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 989 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 990 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 991 WAIT_REG_MEM_ENGINE(eng_sel))); 992 993 if (mem_space) 994 BUG_ON(addr0 & 0x3); /* Dword align */ 995 amdgpu_ring_write(ring, addr0); 996 amdgpu_ring_write(ring, addr1); 997 amdgpu_ring_write(ring, ref); 998 amdgpu_ring_write(ring, mask); 999 amdgpu_ring_write(ring, inv); /* poll interval */ 1000 } 1001 1002 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1003 { 1004 struct amdgpu_device *adev = ring->adev; 1005 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1006 uint32_t tmp = 0; 1007 unsigned i; 1008 int r; 1009 1010 WREG32(scratch, 0xCAFEDEAD); 1011 r = amdgpu_ring_alloc(ring, 3); 1012 if (r) 1013 return r; 1014 1015 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1016 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1017 amdgpu_ring_write(ring, 0xDEADBEEF); 1018 amdgpu_ring_commit(ring); 1019 1020 for (i = 0; i < adev->usec_timeout; i++) { 1021 tmp = RREG32(scratch); 1022 if (tmp == 0xDEADBEEF) 1023 break; 1024 udelay(1); 1025 } 1026 1027 if (i >= adev->usec_timeout) 1028 r = -ETIMEDOUT; 1029 return r; 1030 } 1031 1032 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1033 { 1034 struct amdgpu_device *adev = ring->adev; 1035 struct amdgpu_ib ib; 1036 struct dma_fence *f = NULL; 1037 1038 unsigned index; 1039 uint64_t gpu_addr; 1040 uint32_t tmp; 1041 long r; 1042 1043 r = amdgpu_device_wb_get(adev, &index); 1044 if (r) 1045 return r; 1046 1047 gpu_addr = adev->wb.gpu_addr + (index * 4); 1048 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1049 memset(&ib, 0, sizeof(ib)); 1050 r = amdgpu_ib_get(adev, NULL, 16, 1051 AMDGPU_IB_POOL_DIRECT, &ib); 1052 if (r) 1053 goto err1; 1054 1055 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1056 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1057 ib.ptr[2] = lower_32_bits(gpu_addr); 1058 ib.ptr[3] = upper_32_bits(gpu_addr); 1059 ib.ptr[4] = 0xDEADBEEF; 1060 ib.length_dw = 5; 1061 1062 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1063 if (r) 1064 goto err2; 1065 1066 r = dma_fence_wait_timeout(f, false, timeout); 1067 if (r == 0) { 1068 r = -ETIMEDOUT; 1069 goto err2; 1070 } else if (r < 0) { 1071 goto err2; 1072 } 1073 1074 tmp = adev->wb.wb[index]; 1075 if (tmp == 0xDEADBEEF) 1076 r = 0; 1077 else 1078 r = -EINVAL; 1079 1080 err2: 1081 amdgpu_ib_free(adev, &ib, NULL); 1082 dma_fence_put(f); 1083 err1: 1084 amdgpu_device_wb_free(adev, index); 1085 return r; 1086 } 1087 1088 1089 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1090 { 1091 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1092 amdgpu_ucode_release(&adev->gfx.me_fw); 1093 amdgpu_ucode_release(&adev->gfx.ce_fw); 1094 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1095 amdgpu_ucode_release(&adev->gfx.mec_fw); 1096 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1097 1098 kfree(adev->gfx.rlc.register_list_format); 1099 } 1100 1101 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1102 { 1103 adev->gfx.me_fw_write_wait = false; 1104 adev->gfx.mec_fw_write_wait = false; 1105 1106 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 1107 ((adev->gfx.mec_fw_version < 0x000001a5) || 1108 (adev->gfx.mec_feature_version < 46) || 1109 (adev->gfx.pfp_fw_version < 0x000000b7) || 1110 (adev->gfx.pfp_feature_version < 46))) 1111 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1112 1113 switch (adev->ip_versions[GC_HWIP][0]) { 1114 case IP_VERSION(9, 0, 1): 1115 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1116 (adev->gfx.me_feature_version >= 42) && 1117 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1118 (adev->gfx.pfp_feature_version >= 42)) 1119 adev->gfx.me_fw_write_wait = true; 1120 1121 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1122 (adev->gfx.mec_feature_version >= 42)) 1123 adev->gfx.mec_fw_write_wait = true; 1124 break; 1125 case IP_VERSION(9, 2, 1): 1126 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1127 (adev->gfx.me_feature_version >= 44) && 1128 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1129 (adev->gfx.pfp_feature_version >= 44)) 1130 adev->gfx.me_fw_write_wait = true; 1131 1132 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1133 (adev->gfx.mec_feature_version >= 44)) 1134 adev->gfx.mec_fw_write_wait = true; 1135 break; 1136 case IP_VERSION(9, 4, 0): 1137 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1138 (adev->gfx.me_feature_version >= 44) && 1139 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1140 (adev->gfx.pfp_feature_version >= 44)) 1141 adev->gfx.me_fw_write_wait = true; 1142 1143 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1144 (adev->gfx.mec_feature_version >= 44)) 1145 adev->gfx.mec_fw_write_wait = true; 1146 break; 1147 case IP_VERSION(9, 1, 0): 1148 case IP_VERSION(9, 2, 2): 1149 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1150 (adev->gfx.me_feature_version >= 42) && 1151 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1152 (adev->gfx.pfp_feature_version >= 42)) 1153 adev->gfx.me_fw_write_wait = true; 1154 1155 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1156 (adev->gfx.mec_feature_version >= 42)) 1157 adev->gfx.mec_fw_write_wait = true; 1158 break; 1159 default: 1160 adev->gfx.me_fw_write_wait = true; 1161 adev->gfx.mec_fw_write_wait = true; 1162 break; 1163 } 1164 } 1165 1166 struct amdgpu_gfxoff_quirk { 1167 u16 chip_vendor; 1168 u16 chip_device; 1169 u16 subsys_vendor; 1170 u16 subsys_device; 1171 u8 revision; 1172 }; 1173 1174 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1175 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1176 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1177 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1178 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1179 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1180 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1181 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1182 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1183 { 0, 0, 0, 0, 0 }, 1184 }; 1185 1186 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1187 { 1188 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1189 1190 while (p && p->chip_device != 0) { 1191 if (pdev->vendor == p->chip_vendor && 1192 pdev->device == p->chip_device && 1193 pdev->subsystem_vendor == p->subsys_vendor && 1194 pdev->subsystem_device == p->subsys_device && 1195 pdev->revision == p->revision) { 1196 return true; 1197 } 1198 ++p; 1199 } 1200 return false; 1201 } 1202 1203 static bool is_raven_kicker(struct amdgpu_device *adev) 1204 { 1205 if (adev->pm.fw_version >= 0x41e2b) 1206 return true; 1207 else 1208 return false; 1209 } 1210 1211 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1212 { 1213 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && 1214 (adev->gfx.me_fw_version >= 0x000000a5) && 1215 (adev->gfx.me_feature_version >= 52)) 1216 return true; 1217 else 1218 return false; 1219 } 1220 1221 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1222 { 1223 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1224 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1225 1226 switch (adev->ip_versions[GC_HWIP][0]) { 1227 case IP_VERSION(9, 0, 1): 1228 case IP_VERSION(9, 2, 1): 1229 case IP_VERSION(9, 4, 0): 1230 break; 1231 case IP_VERSION(9, 2, 2): 1232 case IP_VERSION(9, 1, 0): 1233 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1234 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1235 ((!is_raven_kicker(adev) && 1236 adev->gfx.rlc_fw_version < 531) || 1237 (adev->gfx.rlc_feature_version < 1) || 1238 !adev->gfx.rlc.is_rlc_v2_1)) 1239 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1240 1241 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1242 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1243 AMD_PG_SUPPORT_CP | 1244 AMD_PG_SUPPORT_RLC_SMU_HS; 1245 break; 1246 case IP_VERSION(9, 3, 0): 1247 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1248 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1249 AMD_PG_SUPPORT_CP | 1250 AMD_PG_SUPPORT_RLC_SMU_HS; 1251 break; 1252 default: 1253 break; 1254 } 1255 } 1256 1257 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1258 char *chip_name) 1259 { 1260 char fw_name[30]; 1261 int err; 1262 1263 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1264 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 1265 if (err) 1266 goto out; 1267 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1268 1269 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1270 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 1271 if (err) 1272 goto out; 1273 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1274 1275 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1276 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 1277 if (err) 1278 goto out; 1279 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1280 1281 out: 1282 if (err) { 1283 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1284 amdgpu_ucode_release(&adev->gfx.me_fw); 1285 amdgpu_ucode_release(&adev->gfx.ce_fw); 1286 } 1287 return err; 1288 } 1289 1290 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1291 char *chip_name) 1292 { 1293 char fw_name[30]; 1294 int err; 1295 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1296 uint16_t version_major; 1297 uint16_t version_minor; 1298 uint32_t smu_version; 1299 1300 /* 1301 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1302 * instead of picasso_rlc.bin. 1303 * Judgment method: 1304 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1305 * or revision >= 0xD8 && revision <= 0xDF 1306 * otherwise is PCO FP5 1307 */ 1308 if (!strcmp(chip_name, "picasso") && 1309 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1310 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1312 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1313 (smu_version >= 0x41e2b)) 1314 /** 1315 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1316 */ 1317 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1318 else 1319 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1320 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 1321 if (err) 1322 goto out; 1323 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1324 1325 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1326 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1327 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1328 out: 1329 if (err) 1330 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1331 1332 return err; 1333 } 1334 1335 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1336 { 1337 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1338 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1339 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) 1340 return false; 1341 1342 return true; 1343 } 1344 1345 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1346 char *chip_name) 1347 { 1348 char fw_name[30]; 1349 int err; 1350 1351 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1352 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); 1353 else 1354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1355 1356 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 1357 if (err) 1358 goto out; 1359 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1360 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1361 1362 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1363 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1364 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); 1365 else 1366 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1367 1368 /* ignore failures to load */ 1369 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 1370 if (!err) { 1371 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1372 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1373 } else { 1374 err = 0; 1375 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1376 } 1377 } else { 1378 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1379 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1380 } 1381 1382 gfx_v9_0_check_if_need_gfxoff(adev); 1383 gfx_v9_0_check_fw_write_wait(adev); 1384 1385 out: 1386 if (err) 1387 amdgpu_ucode_release(&adev->gfx.mec_fw); 1388 return err; 1389 } 1390 1391 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1392 { 1393 char ucode_prefix[30]; 1394 int r; 1395 1396 DRM_DEBUG("\n"); 1397 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 1398 1399 /* No CPG in Arcturus */ 1400 if (adev->gfx.num_gfx_rings) { 1401 r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); 1402 if (r) 1403 return r; 1404 } 1405 1406 r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); 1407 if (r) 1408 return r; 1409 1410 r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); 1411 if (r) 1412 return r; 1413 1414 return r; 1415 } 1416 1417 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1418 { 1419 u32 count = 0; 1420 const struct cs_section_def *sect = NULL; 1421 const struct cs_extent_def *ext = NULL; 1422 1423 /* begin clear state */ 1424 count += 2; 1425 /* context control state */ 1426 count += 3; 1427 1428 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1429 for (ext = sect->section; ext->extent != NULL; ++ext) { 1430 if (sect->id == SECT_CONTEXT) 1431 count += 2 + ext->reg_count; 1432 else 1433 return 0; 1434 } 1435 } 1436 1437 /* end clear state */ 1438 count += 2; 1439 /* clear state */ 1440 count += 2; 1441 1442 return count; 1443 } 1444 1445 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1446 volatile u32 *buffer) 1447 { 1448 u32 count = 0, i; 1449 const struct cs_section_def *sect = NULL; 1450 const struct cs_extent_def *ext = NULL; 1451 1452 if (adev->gfx.rlc.cs_data == NULL) 1453 return; 1454 if (buffer == NULL) 1455 return; 1456 1457 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1458 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1459 1460 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1461 buffer[count++] = cpu_to_le32(0x80000000); 1462 buffer[count++] = cpu_to_le32(0x80000000); 1463 1464 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1465 for (ext = sect->section; ext->extent != NULL; ++ext) { 1466 if (sect->id == SECT_CONTEXT) { 1467 buffer[count++] = 1468 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1469 buffer[count++] = cpu_to_le32(ext->reg_index - 1470 PACKET3_SET_CONTEXT_REG_START); 1471 for (i = 0; i < ext->reg_count; i++) 1472 buffer[count++] = cpu_to_le32(ext->extent[i]); 1473 } else { 1474 return; 1475 } 1476 } 1477 } 1478 1479 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1480 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1481 1482 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1483 buffer[count++] = cpu_to_le32(0); 1484 } 1485 1486 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1487 { 1488 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1489 uint32_t pg_always_on_cu_num = 2; 1490 uint32_t always_on_cu_num; 1491 uint32_t i, j, k; 1492 uint32_t mask, cu_bitmap, counter; 1493 1494 if (adev->flags & AMD_IS_APU) 1495 always_on_cu_num = 4; 1496 else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) 1497 always_on_cu_num = 8; 1498 else 1499 always_on_cu_num = 12; 1500 1501 mutex_lock(&adev->grbm_idx_mutex); 1502 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1504 mask = 1; 1505 cu_bitmap = 0; 1506 counter = 0; 1507 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 1508 1509 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1510 if (cu_info->bitmap[i][j] & mask) { 1511 if (counter == pg_always_on_cu_num) 1512 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1513 if (counter < always_on_cu_num) 1514 cu_bitmap |= mask; 1515 else 1516 break; 1517 counter++; 1518 } 1519 mask <<= 1; 1520 } 1521 1522 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1523 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1524 } 1525 } 1526 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1527 mutex_unlock(&adev->grbm_idx_mutex); 1528 } 1529 1530 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1531 { 1532 uint32_t data; 1533 1534 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1535 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1536 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1537 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1538 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1539 1540 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1541 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1542 1543 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1544 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1545 1546 mutex_lock(&adev->grbm_idx_mutex); 1547 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1548 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1549 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1550 1551 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1552 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1553 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1554 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1555 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1556 1557 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1558 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1559 data &= 0x0000FFFF; 1560 data |= 0x00C00000; 1561 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1562 1563 /* 1564 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1565 * programmed in gfx_v9_0_init_always_on_cu_mask() 1566 */ 1567 1568 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1569 * but used for RLC_LB_CNTL configuration */ 1570 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1571 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1572 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1573 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1574 mutex_unlock(&adev->grbm_idx_mutex); 1575 1576 gfx_v9_0_init_always_on_cu_mask(adev); 1577 } 1578 1579 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1580 { 1581 uint32_t data; 1582 1583 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1584 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1585 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1586 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1587 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1588 1589 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1590 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1591 1592 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1593 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1594 1595 mutex_lock(&adev->grbm_idx_mutex); 1596 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1597 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1598 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1599 1600 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1601 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1602 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1603 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1604 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1605 1606 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1607 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1608 data &= 0x0000FFFF; 1609 data |= 0x00C00000; 1610 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1611 1612 /* 1613 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1614 * programmed in gfx_v9_0_init_always_on_cu_mask() 1615 */ 1616 1617 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1618 * but used for RLC_LB_CNTL configuration */ 1619 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1620 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1621 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1622 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1623 mutex_unlock(&adev->grbm_idx_mutex); 1624 1625 gfx_v9_0_init_always_on_cu_mask(adev); 1626 } 1627 1628 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1629 { 1630 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1631 } 1632 1633 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1634 { 1635 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1636 return 5; 1637 else 1638 return 4; 1639 } 1640 1641 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1642 { 1643 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1644 1645 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 1646 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1647 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1648 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1649 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1650 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1651 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1652 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1653 adev->gfx.rlc.rlcg_reg_access_supported = true; 1654 } 1655 1656 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1657 { 1658 const struct cs_section_def *cs_data; 1659 int r; 1660 1661 adev->gfx.rlc.cs_data = gfx9_cs_data; 1662 1663 cs_data = adev->gfx.rlc.cs_data; 1664 1665 if (cs_data) { 1666 /* init clear state block */ 1667 r = amdgpu_gfx_rlc_init_csb(adev); 1668 if (r) 1669 return r; 1670 } 1671 1672 if (adev->flags & AMD_IS_APU) { 1673 /* TODO: double check the cp_table_size for RV */ 1674 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1675 r = amdgpu_gfx_rlc_init_cpt(adev); 1676 if (r) 1677 return r; 1678 } 1679 1680 switch (adev->ip_versions[GC_HWIP][0]) { 1681 case IP_VERSION(9, 2, 2): 1682 case IP_VERSION(9, 1, 0): 1683 gfx_v9_0_init_lbpw(adev); 1684 break; 1685 case IP_VERSION(9, 4, 0): 1686 gfx_v9_4_init_lbpw(adev); 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 /* init spm vmid with 0xf */ 1693 if (adev->gfx.rlc.funcs->update_spm_vmid) 1694 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1695 1696 return 0; 1697 } 1698 1699 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1700 { 1701 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1702 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1703 } 1704 1705 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1706 { 1707 int r; 1708 u32 *hpd; 1709 const __le32 *fw_data; 1710 unsigned fw_size; 1711 u32 *fw; 1712 size_t mec_hpd_size; 1713 1714 const struct gfx_firmware_header_v1_0 *mec_hdr; 1715 1716 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1717 1718 /* take ownership of the relevant compute queues */ 1719 amdgpu_gfx_compute_queue_acquire(adev); 1720 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1721 if (mec_hpd_size) { 1722 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1723 AMDGPU_GEM_DOMAIN_VRAM | 1724 AMDGPU_GEM_DOMAIN_GTT, 1725 &adev->gfx.mec.hpd_eop_obj, 1726 &adev->gfx.mec.hpd_eop_gpu_addr, 1727 (void **)&hpd); 1728 if (r) { 1729 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1730 gfx_v9_0_mec_fini(adev); 1731 return r; 1732 } 1733 1734 memset(hpd, 0, mec_hpd_size); 1735 1736 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1737 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1738 } 1739 1740 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1741 1742 fw_data = (const __le32 *) 1743 (adev->gfx.mec_fw->data + 1744 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1745 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1746 1747 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1748 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1749 &adev->gfx.mec.mec_fw_obj, 1750 &adev->gfx.mec.mec_fw_gpu_addr, 1751 (void **)&fw); 1752 if (r) { 1753 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1754 gfx_v9_0_mec_fini(adev); 1755 return r; 1756 } 1757 1758 memcpy(fw, fw_data, fw_size); 1759 1760 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1761 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1762 1763 return 0; 1764 } 1765 1766 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1767 { 1768 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1769 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1770 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1771 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1772 (SQ_IND_INDEX__FORCE_READ_MASK)); 1773 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1774 } 1775 1776 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1777 uint32_t wave, uint32_t thread, 1778 uint32_t regno, uint32_t num, uint32_t *out) 1779 { 1780 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1781 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1782 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1783 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1784 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1785 (SQ_IND_INDEX__FORCE_READ_MASK) | 1786 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1787 while (num--) 1788 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1789 } 1790 1791 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1792 { 1793 /* type 1 wave data */ 1794 dst[(*no_fields)++] = 1; 1795 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1796 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1797 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1798 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1799 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1800 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1801 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1802 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1803 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1804 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1805 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1806 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1807 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1808 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1809 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1810 } 1811 1812 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1813 uint32_t wave, uint32_t start, 1814 uint32_t size, uint32_t *dst) 1815 { 1816 wave_read_regs( 1817 adev, simd, wave, 0, 1818 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1819 } 1820 1821 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1822 uint32_t wave, uint32_t thread, 1823 uint32_t start, uint32_t size, 1824 uint32_t *dst) 1825 { 1826 wave_read_regs( 1827 adev, simd, wave, thread, 1828 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1829 } 1830 1831 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1832 u32 me, u32 pipe, u32 q, u32 vm) 1833 { 1834 soc15_grbm_select(adev, me, pipe, q, vm); 1835 } 1836 1837 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1838 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1839 .select_se_sh = &gfx_v9_0_select_se_sh, 1840 .read_wave_data = &gfx_v9_0_read_wave_data, 1841 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1842 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1843 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1844 }; 1845 1846 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1847 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1848 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1849 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1850 }; 1851 1852 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1853 .ras_block = { 1854 .hw_ops = &gfx_v9_0_ras_ops, 1855 }, 1856 }; 1857 1858 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1859 { 1860 u32 gb_addr_config; 1861 int err; 1862 1863 switch (adev->ip_versions[GC_HWIP][0]) { 1864 case IP_VERSION(9, 0, 1): 1865 adev->gfx.config.max_hw_contexts = 8; 1866 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1867 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1868 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1869 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1870 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1871 break; 1872 case IP_VERSION(9, 2, 1): 1873 adev->gfx.config.max_hw_contexts = 8; 1874 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1875 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1876 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1877 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1878 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1879 DRM_INFO("fix gfx.config for vega12\n"); 1880 break; 1881 case IP_VERSION(9, 4, 0): 1882 adev->gfx.ras = &gfx_v9_0_ras; 1883 adev->gfx.config.max_hw_contexts = 8; 1884 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1885 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1886 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1887 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1888 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1889 gb_addr_config &= ~0xf3e777ff; 1890 gb_addr_config |= 0x22014042; 1891 /* check vbios table if gpu info is not available */ 1892 err = amdgpu_atomfirmware_get_gfx_info(adev); 1893 if (err) 1894 return err; 1895 break; 1896 case IP_VERSION(9, 2, 2): 1897 case IP_VERSION(9, 1, 0): 1898 adev->gfx.config.max_hw_contexts = 8; 1899 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1900 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1901 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1902 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1903 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1904 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1905 else 1906 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1907 break; 1908 case IP_VERSION(9, 4, 1): 1909 adev->gfx.ras = &gfx_v9_4_ras; 1910 adev->gfx.config.max_hw_contexts = 8; 1911 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1912 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1913 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1914 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1915 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1916 gb_addr_config &= ~0xf3e777ff; 1917 gb_addr_config |= 0x22014042; 1918 break; 1919 case IP_VERSION(9, 3, 0): 1920 adev->gfx.config.max_hw_contexts = 8; 1921 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1922 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1923 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1924 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1925 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1926 gb_addr_config &= ~0xf3e777ff; 1927 gb_addr_config |= 0x22010042; 1928 break; 1929 case IP_VERSION(9, 4, 2): 1930 adev->gfx.ras = &gfx_v9_4_2_ras; 1931 adev->gfx.config.max_hw_contexts = 8; 1932 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1933 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1934 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1935 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1936 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1937 gb_addr_config &= ~0xf3e777ff; 1938 gb_addr_config |= 0x22014042; 1939 /* check vbios table if gpu info is not available */ 1940 err = amdgpu_atomfirmware_get_gfx_info(adev); 1941 if (err) 1942 return err; 1943 break; 1944 default: 1945 BUG(); 1946 break; 1947 } 1948 1949 adev->gfx.config.gb_addr_config = gb_addr_config; 1950 1951 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1952 REG_GET_FIELD( 1953 adev->gfx.config.gb_addr_config, 1954 GB_ADDR_CONFIG, 1955 NUM_PIPES); 1956 1957 adev->gfx.config.max_tile_pipes = 1958 adev->gfx.config.gb_addr_config_fields.num_pipes; 1959 1960 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1961 REG_GET_FIELD( 1962 adev->gfx.config.gb_addr_config, 1963 GB_ADDR_CONFIG, 1964 NUM_BANKS); 1965 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1966 REG_GET_FIELD( 1967 adev->gfx.config.gb_addr_config, 1968 GB_ADDR_CONFIG, 1969 MAX_COMPRESSED_FRAGS); 1970 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1971 REG_GET_FIELD( 1972 adev->gfx.config.gb_addr_config, 1973 GB_ADDR_CONFIG, 1974 NUM_RB_PER_SE); 1975 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1976 REG_GET_FIELD( 1977 adev->gfx.config.gb_addr_config, 1978 GB_ADDR_CONFIG, 1979 NUM_SHADER_ENGINES); 1980 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1981 REG_GET_FIELD( 1982 adev->gfx.config.gb_addr_config, 1983 GB_ADDR_CONFIG, 1984 PIPE_INTERLEAVE_SIZE)); 1985 1986 return 0; 1987 } 1988 1989 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1990 int mec, int pipe, int queue) 1991 { 1992 unsigned irq_type; 1993 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1994 unsigned int hw_prio; 1995 1996 ring = &adev->gfx.compute_ring[ring_id]; 1997 1998 /* mec0 is me1 */ 1999 ring->me = mec + 1; 2000 ring->pipe = pipe; 2001 ring->queue = queue; 2002 2003 ring->ring_obj = NULL; 2004 ring->use_doorbell = true; 2005 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2007 + (ring_id * GFX9_MEC_HPD_SIZE); 2008 ring->vm_hub = AMDGPU_GFXHUB_0; 2009 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2010 2011 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2012 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2013 + ring->pipe; 2014 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2015 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2016 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2017 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2018 hw_prio, NULL); 2019 } 2020 2021 static int gfx_v9_0_sw_init(void *handle) 2022 { 2023 int i, j, k, r, ring_id; 2024 struct amdgpu_ring *ring; 2025 struct amdgpu_kiq *kiq; 2026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2027 unsigned int hw_prio; 2028 2029 switch (adev->ip_versions[GC_HWIP][0]) { 2030 case IP_VERSION(9, 0, 1): 2031 case IP_VERSION(9, 2, 1): 2032 case IP_VERSION(9, 4, 0): 2033 case IP_VERSION(9, 2, 2): 2034 case IP_VERSION(9, 1, 0): 2035 case IP_VERSION(9, 4, 1): 2036 case IP_VERSION(9, 3, 0): 2037 case IP_VERSION(9, 4, 2): 2038 adev->gfx.mec.num_mec = 2; 2039 break; 2040 default: 2041 adev->gfx.mec.num_mec = 1; 2042 break; 2043 } 2044 2045 adev->gfx.mec.num_pipe_per_mec = 4; 2046 adev->gfx.mec.num_queue_per_pipe = 8; 2047 2048 /* EOP Event */ 2049 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2050 if (r) 2051 return r; 2052 2053 /* Privileged reg */ 2054 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2055 &adev->gfx.priv_reg_irq); 2056 if (r) 2057 return r; 2058 2059 /* Privileged inst */ 2060 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2061 &adev->gfx.priv_inst_irq); 2062 if (r) 2063 return r; 2064 2065 /* ECC error */ 2066 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2067 &adev->gfx.cp_ecc_error_irq); 2068 if (r) 2069 return r; 2070 2071 /* FUE error */ 2072 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2073 &adev->gfx.cp_ecc_error_irq); 2074 if (r) 2075 return r; 2076 2077 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2078 2079 if (adev->gfx.rlc.funcs) { 2080 if (adev->gfx.rlc.funcs->init) { 2081 r = adev->gfx.rlc.funcs->init(adev); 2082 if (r) { 2083 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2084 return r; 2085 } 2086 } 2087 } 2088 2089 r = gfx_v9_0_mec_init(adev); 2090 if (r) { 2091 DRM_ERROR("Failed to init MEC BOs!\n"); 2092 return r; 2093 } 2094 2095 /* set up the gfx ring */ 2096 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2097 ring = &adev->gfx.gfx_ring[i]; 2098 ring->ring_obj = NULL; 2099 if (!i) 2100 sprintf(ring->name, "gfx"); 2101 else 2102 sprintf(ring->name, "gfx_%d", i); 2103 ring->use_doorbell = true; 2104 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2105 2106 /* disable scheduler on the real ring */ 2107 ring->no_scheduler = true; 2108 ring->vm_hub = AMDGPU_GFXHUB_0; 2109 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2110 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2111 AMDGPU_RING_PRIO_DEFAULT, NULL); 2112 if (r) 2113 return r; 2114 } 2115 2116 /* set up the software rings */ 2117 if (adev->gfx.num_gfx_rings) { 2118 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2119 ring = &adev->gfx.sw_gfx_ring[i]; 2120 ring->ring_obj = NULL; 2121 sprintf(ring->name, amdgpu_sw_ring_name(i)); 2122 ring->use_doorbell = true; 2123 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2124 ring->is_sw_ring = true; 2125 hw_prio = amdgpu_sw_ring_priority(i); 2126 ring->vm_hub = AMDGPU_GFXHUB_0; 2127 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2128 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, 2129 NULL); 2130 if (r) 2131 return r; 2132 ring->wptr = 0; 2133 } 2134 2135 /* init the muxer and add software rings */ 2136 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], 2137 GFX9_NUM_SW_GFX_RINGS); 2138 if (r) { 2139 DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); 2140 return r; 2141 } 2142 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2143 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, 2144 &adev->gfx.sw_gfx_ring[i]); 2145 if (r) { 2146 DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); 2147 return r; 2148 } 2149 } 2150 } 2151 2152 /* set up the compute queues - allocate horizontally across pipes */ 2153 ring_id = 0; 2154 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2155 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2156 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2157 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2158 continue; 2159 2160 r = gfx_v9_0_compute_ring_init(adev, 2161 ring_id, 2162 i, k, j); 2163 if (r) 2164 return r; 2165 2166 ring_id++; 2167 } 2168 } 2169 } 2170 2171 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2172 if (r) { 2173 DRM_ERROR("Failed to init KIQ BOs!\n"); 2174 return r; 2175 } 2176 2177 kiq = &adev->gfx.kiq; 2178 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2179 if (r) 2180 return r; 2181 2182 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2183 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2184 if (r) 2185 return r; 2186 2187 adev->gfx.ce_ram_size = 0x8000; 2188 2189 r = gfx_v9_0_gpu_early_init(adev); 2190 if (r) 2191 return r; 2192 2193 if (amdgpu_gfx_ras_sw_init(adev)) { 2194 dev_err(adev->dev, "Failed to initialize gfx ras block!\n"); 2195 return -EINVAL; 2196 } 2197 2198 return 0; 2199 } 2200 2201 2202 static int gfx_v9_0_sw_fini(void *handle) 2203 { 2204 int i; 2205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2206 2207 if (adev->gfx.num_gfx_rings) { 2208 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 2209 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); 2210 amdgpu_ring_mux_fini(&adev->gfx.muxer); 2211 } 2212 2213 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2214 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2215 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2216 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2217 2218 amdgpu_gfx_mqd_sw_fini(adev); 2219 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2220 amdgpu_gfx_kiq_fini(adev); 2221 2222 gfx_v9_0_mec_fini(adev); 2223 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2224 &adev->gfx.rlc.clear_state_gpu_addr, 2225 (void **)&adev->gfx.rlc.cs_ptr); 2226 if (adev->flags & AMD_IS_APU) { 2227 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2228 &adev->gfx.rlc.cp_table_gpu_addr, 2229 (void **)&adev->gfx.rlc.cp_table_ptr); 2230 } 2231 gfx_v9_0_free_microcode(adev); 2232 2233 return 0; 2234 } 2235 2236 2237 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2238 { 2239 /* TODO */ 2240 } 2241 2242 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2243 u32 instance) 2244 { 2245 u32 data; 2246 2247 if (instance == 0xffffffff) 2248 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2249 else 2250 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2251 2252 if (se_num == 0xffffffff) 2253 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2254 else 2255 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2256 2257 if (sh_num == 0xffffffff) 2258 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2259 else 2260 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2261 2262 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2263 } 2264 2265 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2266 { 2267 u32 data, mask; 2268 2269 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2270 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2271 2272 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2273 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2274 2275 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2276 adev->gfx.config.max_sh_per_se); 2277 2278 return (~data) & mask; 2279 } 2280 2281 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2282 { 2283 int i, j; 2284 u32 data; 2285 u32 active_rbs = 0; 2286 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2287 adev->gfx.config.max_sh_per_se; 2288 2289 mutex_lock(&adev->grbm_idx_mutex); 2290 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2291 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2292 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2293 data = gfx_v9_0_get_rb_active_bitmap(adev); 2294 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2295 rb_bitmap_width_per_sh); 2296 } 2297 } 2298 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2299 mutex_unlock(&adev->grbm_idx_mutex); 2300 2301 adev->gfx.config.backend_enable_mask = active_rbs; 2302 adev->gfx.config.num_rbs = hweight32(active_rbs); 2303 } 2304 2305 #define DEFAULT_SH_MEM_BASES (0x6000) 2306 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2307 { 2308 int i; 2309 uint32_t sh_mem_config; 2310 uint32_t sh_mem_bases; 2311 2312 /* 2313 * Configure apertures: 2314 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2315 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2316 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2317 */ 2318 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2319 2320 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2321 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2322 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2323 2324 mutex_lock(&adev->srbm_mutex); 2325 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2326 soc15_grbm_select(adev, 0, 0, 0, i); 2327 /* CP and shaders */ 2328 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2329 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2330 } 2331 soc15_grbm_select(adev, 0, 0, 0, 0); 2332 mutex_unlock(&adev->srbm_mutex); 2333 2334 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2335 access. These should be enabled by FW for target VMIDs. */ 2336 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2337 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2338 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2339 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2340 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2341 } 2342 } 2343 2344 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2345 { 2346 int vmid; 2347 2348 /* 2349 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2350 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2351 * the driver can enable them for graphics. VMID0 should maintain 2352 * access so that HWS firmware can save/restore entries. 2353 */ 2354 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2355 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2356 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2357 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2358 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2359 } 2360 } 2361 2362 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2363 { 2364 uint32_t tmp; 2365 2366 switch (adev->ip_versions[GC_HWIP][0]) { 2367 case IP_VERSION(9, 4, 1): 2368 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2369 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2370 DISABLE_BARRIER_WAITCNT, 1); 2371 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2372 break; 2373 default: 2374 break; 2375 } 2376 } 2377 2378 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2379 { 2380 u32 tmp; 2381 int i; 2382 2383 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2384 2385 gfx_v9_0_tiling_mode_table_init(adev); 2386 2387 if (adev->gfx.num_gfx_rings) 2388 gfx_v9_0_setup_rb(adev); 2389 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2390 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2391 2392 /* XXX SH_MEM regs */ 2393 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2394 mutex_lock(&adev->srbm_mutex); 2395 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2396 soc15_grbm_select(adev, 0, 0, 0, i); 2397 /* CP and shaders */ 2398 if (i == 0) { 2399 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2400 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2401 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2402 !!adev->gmc.noretry); 2403 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2404 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2405 } else { 2406 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2407 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2408 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2409 !!adev->gmc.noretry); 2410 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2411 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2412 (adev->gmc.private_aperture_start >> 48)); 2413 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2414 (adev->gmc.shared_aperture_start >> 48)); 2415 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2416 } 2417 } 2418 soc15_grbm_select(adev, 0, 0, 0, 0); 2419 2420 mutex_unlock(&adev->srbm_mutex); 2421 2422 gfx_v9_0_init_compute_vmid(adev); 2423 gfx_v9_0_init_gds_vmid(adev); 2424 gfx_v9_0_init_sq_config(adev); 2425 } 2426 2427 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2428 { 2429 u32 i, j, k; 2430 u32 mask; 2431 2432 mutex_lock(&adev->grbm_idx_mutex); 2433 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2434 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2435 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2436 for (k = 0; k < adev->usec_timeout; k++) { 2437 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2438 break; 2439 udelay(1); 2440 } 2441 if (k == adev->usec_timeout) { 2442 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2443 0xffffffff, 0xffffffff); 2444 mutex_unlock(&adev->grbm_idx_mutex); 2445 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2446 i, j); 2447 return; 2448 } 2449 } 2450 } 2451 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2452 mutex_unlock(&adev->grbm_idx_mutex); 2453 2454 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2455 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2456 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2457 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2458 for (k = 0; k < adev->usec_timeout; k++) { 2459 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2460 break; 2461 udelay(1); 2462 } 2463 } 2464 2465 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2466 bool enable) 2467 { 2468 u32 tmp; 2469 2470 /* These interrupts should be enabled to drive DS clock */ 2471 2472 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2473 2474 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2475 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2476 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2477 if(adev->gfx.num_gfx_rings) 2478 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2479 2480 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2481 } 2482 2483 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2484 { 2485 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2486 /* csib */ 2487 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2488 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2489 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2490 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2491 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2492 adev->gfx.rlc.clear_state_size); 2493 } 2494 2495 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2496 int indirect_offset, 2497 int list_size, 2498 int *unique_indirect_regs, 2499 int unique_indirect_reg_count, 2500 int *indirect_start_offsets, 2501 int *indirect_start_offsets_count, 2502 int max_start_offsets_count) 2503 { 2504 int idx; 2505 2506 for (; indirect_offset < list_size; indirect_offset++) { 2507 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2508 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2509 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2510 2511 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2512 indirect_offset += 2; 2513 2514 /* look for the matching indice */ 2515 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2516 if (unique_indirect_regs[idx] == 2517 register_list_format[indirect_offset] || 2518 !unique_indirect_regs[idx]) 2519 break; 2520 } 2521 2522 BUG_ON(idx >= unique_indirect_reg_count); 2523 2524 if (!unique_indirect_regs[idx]) 2525 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2526 2527 indirect_offset++; 2528 } 2529 } 2530 } 2531 2532 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2533 { 2534 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2535 int unique_indirect_reg_count = 0; 2536 2537 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2538 int indirect_start_offsets_count = 0; 2539 2540 int list_size = 0; 2541 int i = 0, j = 0; 2542 u32 tmp = 0; 2543 2544 u32 *register_list_format = 2545 kmemdup(adev->gfx.rlc.register_list_format, 2546 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2547 if (!register_list_format) 2548 return -ENOMEM; 2549 2550 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2551 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2552 gfx_v9_1_parse_ind_reg_list(register_list_format, 2553 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2554 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2555 unique_indirect_regs, 2556 unique_indirect_reg_count, 2557 indirect_start_offsets, 2558 &indirect_start_offsets_count, 2559 ARRAY_SIZE(indirect_start_offsets)); 2560 2561 /* enable auto inc in case it is disabled */ 2562 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2563 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2564 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2565 2566 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2567 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2568 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2569 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2570 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2571 adev->gfx.rlc.register_restore[i]); 2572 2573 /* load indirect register */ 2574 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2575 adev->gfx.rlc.reg_list_format_start); 2576 2577 /* direct register portion */ 2578 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2579 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2580 register_list_format[i]); 2581 2582 /* indirect register portion */ 2583 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2584 if (register_list_format[i] == 0xFFFFFFFF) { 2585 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2586 continue; 2587 } 2588 2589 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2590 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2591 2592 for (j = 0; j < unique_indirect_reg_count; j++) { 2593 if (register_list_format[i] == unique_indirect_regs[j]) { 2594 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2595 break; 2596 } 2597 } 2598 2599 BUG_ON(j >= unique_indirect_reg_count); 2600 2601 i++; 2602 } 2603 2604 /* set save/restore list size */ 2605 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2606 list_size = list_size >> 1; 2607 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2608 adev->gfx.rlc.reg_restore_list_size); 2609 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2610 2611 /* write the starting offsets to RLC scratch ram */ 2612 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2613 adev->gfx.rlc.starting_offsets_start); 2614 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2615 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2616 indirect_start_offsets[i]); 2617 2618 /* load unique indirect regs*/ 2619 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2620 if (unique_indirect_regs[i] != 0) { 2621 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2622 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2623 unique_indirect_regs[i] & 0x3FFFF); 2624 2625 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2626 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2627 unique_indirect_regs[i] >> 20); 2628 } 2629 } 2630 2631 kfree(register_list_format); 2632 return 0; 2633 } 2634 2635 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2636 { 2637 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2638 } 2639 2640 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2641 bool enable) 2642 { 2643 uint32_t data = 0; 2644 uint32_t default_data = 0; 2645 2646 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2647 if (enable) { 2648 /* enable GFXIP control over CGPG */ 2649 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2650 if(default_data != data) 2651 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2652 2653 /* update status */ 2654 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2655 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2656 if(default_data != data) 2657 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2658 } else { 2659 /* restore GFXIP control over GCPG */ 2660 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2661 if(default_data != data) 2662 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2663 } 2664 } 2665 2666 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2667 { 2668 uint32_t data = 0; 2669 2670 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2671 AMD_PG_SUPPORT_GFX_SMG | 2672 AMD_PG_SUPPORT_GFX_DMG)) { 2673 /* init IDLE_POLL_COUNT = 60 */ 2674 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2675 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2676 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2677 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2678 2679 /* init RLC PG Delay */ 2680 data = 0; 2681 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2682 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2683 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2684 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2685 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2686 2687 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2688 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2689 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2690 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2691 2692 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2693 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2694 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2695 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2696 2697 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2698 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2699 2700 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2701 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2702 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2703 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) 2704 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2705 } 2706 } 2707 2708 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2709 bool enable) 2710 { 2711 uint32_t data = 0; 2712 uint32_t default_data = 0; 2713 2714 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2715 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2716 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2717 enable ? 1 : 0); 2718 if (default_data != data) 2719 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2720 } 2721 2722 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2723 bool enable) 2724 { 2725 uint32_t data = 0; 2726 uint32_t default_data = 0; 2727 2728 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2729 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2730 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2731 enable ? 1 : 0); 2732 if(default_data != data) 2733 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2734 } 2735 2736 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2737 bool enable) 2738 { 2739 uint32_t data = 0; 2740 uint32_t default_data = 0; 2741 2742 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2743 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2744 CP_PG_DISABLE, 2745 enable ? 0 : 1); 2746 if(default_data != data) 2747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2748 } 2749 2750 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2751 bool enable) 2752 { 2753 uint32_t data, default_data; 2754 2755 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2756 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2757 GFX_POWER_GATING_ENABLE, 2758 enable ? 1 : 0); 2759 if(default_data != data) 2760 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2761 } 2762 2763 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2764 bool enable) 2765 { 2766 uint32_t data, default_data; 2767 2768 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2769 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2770 GFX_PIPELINE_PG_ENABLE, 2771 enable ? 1 : 0); 2772 if(default_data != data) 2773 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2774 2775 if (!enable) 2776 /* read any GFX register to wake up GFX */ 2777 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2778 } 2779 2780 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2781 bool enable) 2782 { 2783 uint32_t data, default_data; 2784 2785 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2786 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2787 STATIC_PER_CU_PG_ENABLE, 2788 enable ? 1 : 0); 2789 if(default_data != data) 2790 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2791 } 2792 2793 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2794 bool enable) 2795 { 2796 uint32_t data, default_data; 2797 2798 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2799 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2800 DYN_PER_CU_PG_ENABLE, 2801 enable ? 1 : 0); 2802 if(default_data != data) 2803 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2804 } 2805 2806 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2807 { 2808 gfx_v9_0_init_csb(adev); 2809 2810 /* 2811 * Rlc save restore list is workable since v2_1. 2812 * And it's needed by gfxoff feature. 2813 */ 2814 if (adev->gfx.rlc.is_rlc_v2_1) { 2815 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || 2816 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2817 gfx_v9_1_init_rlc_save_restore_list(adev); 2818 gfx_v9_0_enable_save_restore_machine(adev); 2819 } 2820 2821 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2822 AMD_PG_SUPPORT_GFX_SMG | 2823 AMD_PG_SUPPORT_GFX_DMG | 2824 AMD_PG_SUPPORT_CP | 2825 AMD_PG_SUPPORT_GDS | 2826 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2827 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2828 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2829 gfx_v9_0_init_gfx_power_gating(adev); 2830 } 2831 } 2832 2833 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2834 { 2835 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2836 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2837 gfx_v9_0_wait_for_rlc_serdes(adev); 2838 } 2839 2840 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2841 { 2842 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2843 udelay(50); 2844 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2845 udelay(50); 2846 } 2847 2848 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2849 { 2850 #ifdef AMDGPU_RLC_DEBUG_RETRY 2851 u32 rlc_ucode_ver; 2852 #endif 2853 2854 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2855 udelay(50); 2856 2857 /* carrizo do enable cp interrupt after cp inited */ 2858 if (!(adev->flags & AMD_IS_APU)) { 2859 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2860 udelay(50); 2861 } 2862 2863 #ifdef AMDGPU_RLC_DEBUG_RETRY 2864 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2865 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2866 if(rlc_ucode_ver == 0x108) { 2867 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2868 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2869 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2870 * default is 0x9C4 to create a 100us interval */ 2871 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2872 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2873 * to disable the page fault retry interrupts, default is 2874 * 0x100 (256) */ 2875 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2876 } 2877 #endif 2878 } 2879 2880 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2881 { 2882 const struct rlc_firmware_header_v2_0 *hdr; 2883 const __le32 *fw_data; 2884 unsigned i, fw_size; 2885 2886 if (!adev->gfx.rlc_fw) 2887 return -EINVAL; 2888 2889 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2890 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2891 2892 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2893 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2894 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2895 2896 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2897 RLCG_UCODE_LOADING_START_ADDRESS); 2898 for (i = 0; i < fw_size; i++) 2899 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2900 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2901 2902 return 0; 2903 } 2904 2905 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2906 { 2907 int r; 2908 2909 if (amdgpu_sriov_vf(adev)) { 2910 gfx_v9_0_init_csb(adev); 2911 return 0; 2912 } 2913 2914 adev->gfx.rlc.funcs->stop(adev); 2915 2916 /* disable CG */ 2917 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2918 2919 gfx_v9_0_init_pg(adev); 2920 2921 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2922 /* legacy rlc firmware loading */ 2923 r = gfx_v9_0_rlc_load_microcode(adev); 2924 if (r) 2925 return r; 2926 } 2927 2928 switch (adev->ip_versions[GC_HWIP][0]) { 2929 case IP_VERSION(9, 2, 2): 2930 case IP_VERSION(9, 1, 0): 2931 if (amdgpu_lbpw == 0) 2932 gfx_v9_0_enable_lbpw(adev, false); 2933 else 2934 gfx_v9_0_enable_lbpw(adev, true); 2935 break; 2936 case IP_VERSION(9, 4, 0): 2937 if (amdgpu_lbpw > 0) 2938 gfx_v9_0_enable_lbpw(adev, true); 2939 else 2940 gfx_v9_0_enable_lbpw(adev, false); 2941 break; 2942 default: 2943 break; 2944 } 2945 2946 adev->gfx.rlc.funcs->start(adev); 2947 2948 return 0; 2949 } 2950 2951 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2952 { 2953 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2954 2955 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2956 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2957 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2958 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2959 udelay(50); 2960 } 2961 2962 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2963 { 2964 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2965 const struct gfx_firmware_header_v1_0 *ce_hdr; 2966 const struct gfx_firmware_header_v1_0 *me_hdr; 2967 const __le32 *fw_data; 2968 unsigned i, fw_size; 2969 2970 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2971 return -EINVAL; 2972 2973 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2974 adev->gfx.pfp_fw->data; 2975 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2976 adev->gfx.ce_fw->data; 2977 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2978 adev->gfx.me_fw->data; 2979 2980 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2981 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2982 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2983 2984 gfx_v9_0_cp_gfx_enable(adev, false); 2985 2986 /* PFP */ 2987 fw_data = (const __le32 *) 2988 (adev->gfx.pfp_fw->data + 2989 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2990 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2991 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2992 for (i = 0; i < fw_size; i++) 2993 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2994 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2995 2996 /* CE */ 2997 fw_data = (const __le32 *) 2998 (adev->gfx.ce_fw->data + 2999 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3000 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3001 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3002 for (i = 0; i < fw_size; i++) 3003 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3004 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3005 3006 /* ME */ 3007 fw_data = (const __le32 *) 3008 (adev->gfx.me_fw->data + 3009 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3010 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3011 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3012 for (i = 0; i < fw_size; i++) 3013 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3014 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3015 3016 return 0; 3017 } 3018 3019 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3020 { 3021 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3022 const struct cs_section_def *sect = NULL; 3023 const struct cs_extent_def *ext = NULL; 3024 int r, i, tmp; 3025 3026 /* init the CP */ 3027 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3028 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3029 3030 gfx_v9_0_cp_gfx_enable(adev, true); 3031 3032 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3033 if (r) { 3034 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3035 return r; 3036 } 3037 3038 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3039 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3040 3041 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3042 amdgpu_ring_write(ring, 0x80000000); 3043 amdgpu_ring_write(ring, 0x80000000); 3044 3045 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3046 for (ext = sect->section; ext->extent != NULL; ++ext) { 3047 if (sect->id == SECT_CONTEXT) { 3048 amdgpu_ring_write(ring, 3049 PACKET3(PACKET3_SET_CONTEXT_REG, 3050 ext->reg_count)); 3051 amdgpu_ring_write(ring, 3052 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3053 for (i = 0; i < ext->reg_count; i++) 3054 amdgpu_ring_write(ring, ext->extent[i]); 3055 } 3056 } 3057 } 3058 3059 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3060 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3061 3062 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3063 amdgpu_ring_write(ring, 0); 3064 3065 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3066 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3067 amdgpu_ring_write(ring, 0x8000); 3068 amdgpu_ring_write(ring, 0x8000); 3069 3070 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3071 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3072 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3073 amdgpu_ring_write(ring, tmp); 3074 amdgpu_ring_write(ring, 0); 3075 3076 amdgpu_ring_commit(ring); 3077 3078 return 0; 3079 } 3080 3081 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3082 { 3083 struct amdgpu_ring *ring; 3084 u32 tmp; 3085 u32 rb_bufsz; 3086 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3087 3088 /* Set the write pointer delay */ 3089 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3090 3091 /* set the RB to use vmid 0 */ 3092 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3093 3094 /* Set ring buffer size */ 3095 ring = &adev->gfx.gfx_ring[0]; 3096 rb_bufsz = order_base_2(ring->ring_size / 8); 3097 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3098 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3099 #ifdef __BIG_ENDIAN 3100 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3101 #endif 3102 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3103 3104 /* Initialize the ring buffer's write pointers */ 3105 ring->wptr = 0; 3106 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3107 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3108 3109 /* set the wb address wether it's enabled or not */ 3110 rptr_addr = ring->rptr_gpu_addr; 3111 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3112 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3113 3114 wptr_gpu_addr = ring->wptr_gpu_addr; 3115 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3116 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3117 3118 mdelay(1); 3119 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3120 3121 rb_addr = ring->gpu_addr >> 8; 3122 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3123 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3124 3125 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3126 if (ring->use_doorbell) { 3127 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3128 DOORBELL_OFFSET, ring->doorbell_index); 3129 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3130 DOORBELL_EN, 1); 3131 } else { 3132 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3133 } 3134 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3135 3136 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3137 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3138 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3139 3140 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3141 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3142 3143 3144 /* start the ring */ 3145 gfx_v9_0_cp_gfx_start(adev); 3146 ring->sched.ready = true; 3147 3148 return 0; 3149 } 3150 3151 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3152 { 3153 if (enable) { 3154 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3155 } else { 3156 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3157 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3158 adev->gfx.kiq.ring.sched.ready = false; 3159 } 3160 udelay(50); 3161 } 3162 3163 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3164 { 3165 const struct gfx_firmware_header_v1_0 *mec_hdr; 3166 const __le32 *fw_data; 3167 unsigned i; 3168 u32 tmp; 3169 3170 if (!adev->gfx.mec_fw) 3171 return -EINVAL; 3172 3173 gfx_v9_0_cp_compute_enable(adev, false); 3174 3175 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3176 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3177 3178 fw_data = (const __le32 *) 3179 (adev->gfx.mec_fw->data + 3180 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3181 tmp = 0; 3182 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3183 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3184 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3185 3186 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3187 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3188 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3189 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3190 3191 /* MEC1 */ 3192 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3193 mec_hdr->jt_offset); 3194 for (i = 0; i < mec_hdr->jt_size; i++) 3195 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3196 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3197 3198 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3199 adev->gfx.mec_fw_version); 3200 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3201 3202 return 0; 3203 } 3204 3205 /* KIQ functions */ 3206 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3207 { 3208 uint32_t tmp; 3209 struct amdgpu_device *adev = ring->adev; 3210 3211 /* tell RLC which is KIQ queue */ 3212 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3213 tmp &= 0xffffff00; 3214 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3215 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3216 tmp |= 0x80; 3217 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3218 } 3219 3220 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3221 { 3222 struct amdgpu_device *adev = ring->adev; 3223 3224 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3225 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3226 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3227 mqd->cp_hqd_queue_priority = 3228 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3229 } 3230 } 3231 } 3232 3233 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3234 { 3235 struct amdgpu_device *adev = ring->adev; 3236 struct v9_mqd *mqd = ring->mqd_ptr; 3237 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3238 uint32_t tmp; 3239 3240 mqd->header = 0xC0310800; 3241 mqd->compute_pipelinestat_enable = 0x00000001; 3242 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3243 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3244 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3245 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3246 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3247 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3248 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3249 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3250 mqd->compute_misc_reserved = 0x00000003; 3251 3252 mqd->dynamic_cu_mask_addr_lo = 3253 lower_32_bits(ring->mqd_gpu_addr 3254 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3255 mqd->dynamic_cu_mask_addr_hi = 3256 upper_32_bits(ring->mqd_gpu_addr 3257 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3258 3259 eop_base_addr = ring->eop_gpu_addr >> 8; 3260 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3261 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3262 3263 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3264 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3265 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3266 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3267 3268 mqd->cp_hqd_eop_control = tmp; 3269 3270 /* enable doorbell? */ 3271 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3272 3273 if (ring->use_doorbell) { 3274 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3275 DOORBELL_OFFSET, ring->doorbell_index); 3276 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3277 DOORBELL_EN, 1); 3278 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3279 DOORBELL_SOURCE, 0); 3280 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3281 DOORBELL_HIT, 0); 3282 } else { 3283 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3284 DOORBELL_EN, 0); 3285 } 3286 3287 mqd->cp_hqd_pq_doorbell_control = tmp; 3288 3289 /* disable the queue if it's active */ 3290 ring->wptr = 0; 3291 mqd->cp_hqd_dequeue_request = 0; 3292 mqd->cp_hqd_pq_rptr = 0; 3293 mqd->cp_hqd_pq_wptr_lo = 0; 3294 mqd->cp_hqd_pq_wptr_hi = 0; 3295 3296 /* set the pointer to the MQD */ 3297 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3298 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3299 3300 /* set MQD vmid to 0 */ 3301 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3302 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3303 mqd->cp_mqd_control = tmp; 3304 3305 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3306 hqd_gpu_addr = ring->gpu_addr >> 8; 3307 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3308 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3309 3310 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3311 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3312 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3313 (order_base_2(ring->ring_size / 4) - 1)); 3314 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3315 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3316 #ifdef __BIG_ENDIAN 3317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3318 #endif 3319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3323 mqd->cp_hqd_pq_control = tmp; 3324 3325 /* set the wb address whether it's enabled or not */ 3326 wb_gpu_addr = ring->rptr_gpu_addr; 3327 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3328 mqd->cp_hqd_pq_rptr_report_addr_hi = 3329 upper_32_bits(wb_gpu_addr) & 0xffff; 3330 3331 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3332 wb_gpu_addr = ring->wptr_gpu_addr; 3333 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3334 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3335 3336 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3337 ring->wptr = 0; 3338 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3339 3340 /* set the vmid for the queue */ 3341 mqd->cp_hqd_vmid = 0; 3342 3343 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3344 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3345 mqd->cp_hqd_persistent_state = tmp; 3346 3347 /* set MIN_IB_AVAIL_SIZE */ 3348 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3349 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3350 mqd->cp_hqd_ib_control = tmp; 3351 3352 /* set static priority for a queue/ring */ 3353 gfx_v9_0_mqd_set_priority(ring, mqd); 3354 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3355 3356 /* map_queues packet doesn't need activate the queue, 3357 * so only kiq need set this field. 3358 */ 3359 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3360 mqd->cp_hqd_active = 1; 3361 3362 return 0; 3363 } 3364 3365 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3366 { 3367 struct amdgpu_device *adev = ring->adev; 3368 struct v9_mqd *mqd = ring->mqd_ptr; 3369 int j; 3370 3371 /* disable wptr polling */ 3372 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3373 3374 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3375 mqd->cp_hqd_eop_base_addr_lo); 3376 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3377 mqd->cp_hqd_eop_base_addr_hi); 3378 3379 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3380 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3381 mqd->cp_hqd_eop_control); 3382 3383 /* enable doorbell? */ 3384 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3385 mqd->cp_hqd_pq_doorbell_control); 3386 3387 /* disable the queue if it's active */ 3388 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3389 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3390 for (j = 0; j < adev->usec_timeout; j++) { 3391 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3392 break; 3393 udelay(1); 3394 } 3395 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3396 mqd->cp_hqd_dequeue_request); 3397 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3398 mqd->cp_hqd_pq_rptr); 3399 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3400 mqd->cp_hqd_pq_wptr_lo); 3401 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3402 mqd->cp_hqd_pq_wptr_hi); 3403 } 3404 3405 /* set the pointer to the MQD */ 3406 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3407 mqd->cp_mqd_base_addr_lo); 3408 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3409 mqd->cp_mqd_base_addr_hi); 3410 3411 /* set MQD vmid to 0 */ 3412 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3413 mqd->cp_mqd_control); 3414 3415 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3416 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3417 mqd->cp_hqd_pq_base_lo); 3418 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3419 mqd->cp_hqd_pq_base_hi); 3420 3421 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3422 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3423 mqd->cp_hqd_pq_control); 3424 3425 /* set the wb address whether it's enabled or not */ 3426 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3427 mqd->cp_hqd_pq_rptr_report_addr_lo); 3428 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3429 mqd->cp_hqd_pq_rptr_report_addr_hi); 3430 3431 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3432 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3433 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3434 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3435 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3436 3437 /* enable the doorbell if requested */ 3438 if (ring->use_doorbell) { 3439 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3440 (adev->doorbell_index.kiq * 2) << 2); 3441 /* If GC has entered CGPG, ringing doorbell > first page 3442 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3443 * workaround this issue. And this change has to align with firmware 3444 * update. 3445 */ 3446 if (check_if_enlarge_doorbell_range(adev)) 3447 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3448 (adev->doorbell.size - 4)); 3449 else 3450 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3451 (adev->doorbell_index.userqueue_end * 2) << 2); 3452 } 3453 3454 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3455 mqd->cp_hqd_pq_doorbell_control); 3456 3457 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3458 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3459 mqd->cp_hqd_pq_wptr_lo); 3460 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3461 mqd->cp_hqd_pq_wptr_hi); 3462 3463 /* set the vmid for the queue */ 3464 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3465 3466 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3467 mqd->cp_hqd_persistent_state); 3468 3469 /* activate the queue */ 3470 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3471 mqd->cp_hqd_active); 3472 3473 if (ring->use_doorbell) 3474 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3475 3476 return 0; 3477 } 3478 3479 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3480 { 3481 struct amdgpu_device *adev = ring->adev; 3482 int j; 3483 3484 /* disable the queue if it's active */ 3485 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3486 3487 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3488 3489 for (j = 0; j < adev->usec_timeout; j++) { 3490 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3491 break; 3492 udelay(1); 3493 } 3494 3495 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3496 DRM_DEBUG("KIQ dequeue request failed.\n"); 3497 3498 /* Manual disable if dequeue request times out */ 3499 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3500 } 3501 3502 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3503 0); 3504 } 3505 3506 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3507 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3508 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3509 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3510 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3511 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3512 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3513 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3514 3515 return 0; 3516 } 3517 3518 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3519 { 3520 struct amdgpu_device *adev = ring->adev; 3521 struct v9_mqd *mqd = ring->mqd_ptr; 3522 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3523 struct v9_mqd *tmp_mqd; 3524 3525 gfx_v9_0_kiq_setting(ring); 3526 3527 /* GPU could be in bad state during probe, driver trigger the reset 3528 * after load the SMU, in this case , the mqd is not be initialized. 3529 * driver need to re-init the mqd. 3530 * check mqd->cp_hqd_pq_control since this value should not be 0 3531 */ 3532 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3533 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3534 /* for GPU_RESET case , reset MQD to a clean status */ 3535 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3536 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3537 3538 /* reset ring buffer */ 3539 ring->wptr = 0; 3540 amdgpu_ring_clear_ring(ring); 3541 3542 mutex_lock(&adev->srbm_mutex); 3543 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3544 gfx_v9_0_kiq_init_register(ring); 3545 soc15_grbm_select(adev, 0, 0, 0, 0); 3546 mutex_unlock(&adev->srbm_mutex); 3547 } else { 3548 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3549 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3550 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3551 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3552 amdgpu_ring_clear_ring(ring); 3553 mutex_lock(&adev->srbm_mutex); 3554 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3555 gfx_v9_0_mqd_init(ring); 3556 gfx_v9_0_kiq_init_register(ring); 3557 soc15_grbm_select(adev, 0, 0, 0, 0); 3558 mutex_unlock(&adev->srbm_mutex); 3559 3560 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3561 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3562 } 3563 3564 return 0; 3565 } 3566 3567 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3568 { 3569 struct amdgpu_device *adev = ring->adev; 3570 struct v9_mqd *mqd = ring->mqd_ptr; 3571 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3572 struct v9_mqd *tmp_mqd; 3573 3574 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3575 * is not be initialized before 3576 */ 3577 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3578 3579 if (!tmp_mqd->cp_hqd_pq_control || 3580 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3581 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3582 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3583 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3584 mutex_lock(&adev->srbm_mutex); 3585 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3586 gfx_v9_0_mqd_init(ring); 3587 soc15_grbm_select(adev, 0, 0, 0, 0); 3588 mutex_unlock(&adev->srbm_mutex); 3589 3590 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3591 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3592 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3593 /* reset MQD to a clean status */ 3594 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3595 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3596 3597 /* reset ring buffer */ 3598 ring->wptr = 0; 3599 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3600 amdgpu_ring_clear_ring(ring); 3601 } else { 3602 amdgpu_ring_clear_ring(ring); 3603 } 3604 3605 return 0; 3606 } 3607 3608 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3609 { 3610 struct amdgpu_ring *ring; 3611 int r; 3612 3613 ring = &adev->gfx.kiq.ring; 3614 3615 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3616 if (unlikely(r != 0)) 3617 return r; 3618 3619 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3620 if (unlikely(r != 0)) 3621 return r; 3622 3623 gfx_v9_0_kiq_init_queue(ring); 3624 amdgpu_bo_kunmap(ring->mqd_obj); 3625 ring->mqd_ptr = NULL; 3626 amdgpu_bo_unreserve(ring->mqd_obj); 3627 ring->sched.ready = true; 3628 return 0; 3629 } 3630 3631 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3632 { 3633 struct amdgpu_ring *ring = NULL; 3634 int r = 0, i; 3635 3636 gfx_v9_0_cp_compute_enable(adev, true); 3637 3638 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3639 ring = &adev->gfx.compute_ring[i]; 3640 3641 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3642 if (unlikely(r != 0)) 3643 goto done; 3644 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3645 if (!r) { 3646 r = gfx_v9_0_kcq_init_queue(ring); 3647 amdgpu_bo_kunmap(ring->mqd_obj); 3648 ring->mqd_ptr = NULL; 3649 } 3650 amdgpu_bo_unreserve(ring->mqd_obj); 3651 if (r) 3652 goto done; 3653 } 3654 3655 r = amdgpu_gfx_enable_kcq(adev); 3656 done: 3657 return r; 3658 } 3659 3660 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3661 { 3662 int r, i; 3663 struct amdgpu_ring *ring; 3664 3665 if (!(adev->flags & AMD_IS_APU)) 3666 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3667 3668 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3669 if (adev->gfx.num_gfx_rings) { 3670 /* legacy firmware loading */ 3671 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3672 if (r) 3673 return r; 3674 } 3675 3676 r = gfx_v9_0_cp_compute_load_microcode(adev); 3677 if (r) 3678 return r; 3679 } 3680 3681 r = gfx_v9_0_kiq_resume(adev); 3682 if (r) 3683 return r; 3684 3685 if (adev->gfx.num_gfx_rings) { 3686 r = gfx_v9_0_cp_gfx_resume(adev); 3687 if (r) 3688 return r; 3689 } 3690 3691 r = gfx_v9_0_kcq_resume(adev); 3692 if (r) 3693 return r; 3694 3695 if (adev->gfx.num_gfx_rings) { 3696 ring = &adev->gfx.gfx_ring[0]; 3697 r = amdgpu_ring_test_helper(ring); 3698 if (r) 3699 return r; 3700 } 3701 3702 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3703 ring = &adev->gfx.compute_ring[i]; 3704 amdgpu_ring_test_helper(ring); 3705 } 3706 3707 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3708 3709 return 0; 3710 } 3711 3712 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3713 { 3714 u32 tmp; 3715 3716 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && 3717 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) 3718 return; 3719 3720 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3721 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3722 adev->df.hash_status.hash_64k); 3723 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3724 adev->df.hash_status.hash_2m); 3725 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3726 adev->df.hash_status.hash_1g); 3727 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3728 } 3729 3730 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3731 { 3732 if (adev->gfx.num_gfx_rings) 3733 gfx_v9_0_cp_gfx_enable(adev, enable); 3734 gfx_v9_0_cp_compute_enable(adev, enable); 3735 } 3736 3737 static int gfx_v9_0_hw_init(void *handle) 3738 { 3739 int r; 3740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3741 3742 if (!amdgpu_sriov_vf(adev)) 3743 gfx_v9_0_init_golden_registers(adev); 3744 3745 gfx_v9_0_constants_init(adev); 3746 3747 gfx_v9_0_init_tcp_config(adev); 3748 3749 r = adev->gfx.rlc.funcs->resume(adev); 3750 if (r) 3751 return r; 3752 3753 r = gfx_v9_0_cp_resume(adev); 3754 if (r) 3755 return r; 3756 3757 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 3758 gfx_v9_4_2_set_power_brake_sequence(adev); 3759 3760 return r; 3761 } 3762 3763 static int gfx_v9_0_hw_fini(void *handle) 3764 { 3765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3766 3767 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 3768 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3769 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3770 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3771 3772 /* DF freeze and kcq disable will fail */ 3773 if (!amdgpu_ras_intr_triggered()) 3774 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3775 amdgpu_gfx_disable_kcq(adev); 3776 3777 if (amdgpu_sriov_vf(adev)) { 3778 gfx_v9_0_cp_gfx_enable(adev, false); 3779 /* must disable polling for SRIOV when hw finished, otherwise 3780 * CPC engine may still keep fetching WB address which is already 3781 * invalid after sw finished and trigger DMAR reading error in 3782 * hypervisor side. 3783 */ 3784 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3785 return 0; 3786 } 3787 3788 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3789 * otherwise KIQ is hanging when binding back 3790 */ 3791 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3792 mutex_lock(&adev->srbm_mutex); 3793 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3794 adev->gfx.kiq.ring.pipe, 3795 adev->gfx.kiq.ring.queue, 0); 3796 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3797 soc15_grbm_select(adev, 0, 0, 0, 0); 3798 mutex_unlock(&adev->srbm_mutex); 3799 } 3800 3801 gfx_v9_0_cp_enable(adev, false); 3802 3803 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3804 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3805 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { 3806 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3807 return 0; 3808 } 3809 3810 adev->gfx.rlc.funcs->stop(adev); 3811 return 0; 3812 } 3813 3814 static int gfx_v9_0_suspend(void *handle) 3815 { 3816 return gfx_v9_0_hw_fini(handle); 3817 } 3818 3819 static int gfx_v9_0_resume(void *handle) 3820 { 3821 return gfx_v9_0_hw_init(handle); 3822 } 3823 3824 static bool gfx_v9_0_is_idle(void *handle) 3825 { 3826 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3827 3828 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3829 GRBM_STATUS, GUI_ACTIVE)) 3830 return false; 3831 else 3832 return true; 3833 } 3834 3835 static int gfx_v9_0_wait_for_idle(void *handle) 3836 { 3837 unsigned i; 3838 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3839 3840 for (i = 0; i < adev->usec_timeout; i++) { 3841 if (gfx_v9_0_is_idle(handle)) 3842 return 0; 3843 udelay(1); 3844 } 3845 return -ETIMEDOUT; 3846 } 3847 3848 static int gfx_v9_0_soft_reset(void *handle) 3849 { 3850 u32 grbm_soft_reset = 0; 3851 u32 tmp; 3852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3853 3854 /* GRBM_STATUS */ 3855 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3856 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3857 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3858 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3859 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3860 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3861 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3862 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3863 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3864 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3865 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3866 } 3867 3868 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3869 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3870 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3871 } 3872 3873 /* GRBM_STATUS2 */ 3874 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3875 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3876 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3877 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3878 3879 3880 if (grbm_soft_reset) { 3881 /* stop the rlc */ 3882 adev->gfx.rlc.funcs->stop(adev); 3883 3884 if (adev->gfx.num_gfx_rings) 3885 /* Disable GFX parsing/prefetching */ 3886 gfx_v9_0_cp_gfx_enable(adev, false); 3887 3888 /* Disable MEC parsing/prefetching */ 3889 gfx_v9_0_cp_compute_enable(adev, false); 3890 3891 if (grbm_soft_reset) { 3892 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3893 tmp |= grbm_soft_reset; 3894 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3895 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3896 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3897 3898 udelay(50); 3899 3900 tmp &= ~grbm_soft_reset; 3901 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3902 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3903 } 3904 3905 /* Wait a little for things to settle down */ 3906 udelay(50); 3907 } 3908 return 0; 3909 } 3910 3911 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 3912 { 3913 signed long r, cnt = 0; 3914 unsigned long flags; 3915 uint32_t seq, reg_val_offs = 0; 3916 uint64_t value = 0; 3917 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3918 struct amdgpu_ring *ring = &kiq->ring; 3919 3920 BUG_ON(!ring->funcs->emit_rreg); 3921 3922 spin_lock_irqsave(&kiq->ring_lock, flags); 3923 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 3924 pr_err("critical bug! too many kiq readers\n"); 3925 goto failed_unlock; 3926 } 3927 amdgpu_ring_alloc(ring, 32); 3928 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3929 amdgpu_ring_write(ring, 9 | /* src: register*/ 3930 (5 << 8) | /* dst: memory */ 3931 (1 << 16) | /* count sel */ 3932 (1 << 20)); /* write confirm */ 3933 amdgpu_ring_write(ring, 0); 3934 amdgpu_ring_write(ring, 0); 3935 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3936 reg_val_offs * 4)); 3937 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3938 reg_val_offs * 4)); 3939 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 3940 if (r) 3941 goto failed_undo; 3942 3943 amdgpu_ring_commit(ring); 3944 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3945 3946 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3947 3948 /* don't wait anymore for gpu reset case because this way may 3949 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 3950 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 3951 * never return if we keep waiting in virt_kiq_rreg, which cause 3952 * gpu_recover() hang there. 3953 * 3954 * also don't wait anymore for IRQ context 3955 * */ 3956 if (r < 1 && (amdgpu_in_reset(adev))) 3957 goto failed_kiq_read; 3958 3959 might_sleep(); 3960 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 3961 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 3962 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3963 } 3964 3965 if (cnt > MAX_KIQ_REG_TRY) 3966 goto failed_kiq_read; 3967 3968 mb(); 3969 value = (uint64_t)adev->wb.wb[reg_val_offs] | 3970 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 3971 amdgpu_device_wb_free(adev, reg_val_offs); 3972 return value; 3973 3974 failed_undo: 3975 amdgpu_ring_undo(ring); 3976 failed_unlock: 3977 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3978 failed_kiq_read: 3979 if (reg_val_offs) 3980 amdgpu_device_wb_free(adev, reg_val_offs); 3981 pr_err("failed to read gpu clock\n"); 3982 return ~0; 3983 } 3984 3985 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3986 { 3987 uint64_t clock, clock_lo, clock_hi, hi_check; 3988 3989 switch (adev->ip_versions[GC_HWIP][0]) { 3990 case IP_VERSION(9, 3, 0): 3991 preempt_disable(); 3992 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3993 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 3994 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3995 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 3996 * roughly every 42 seconds. 3997 */ 3998 if (hi_check != clock_hi) { 3999 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4000 clock_hi = hi_check; 4001 } 4002 preempt_enable(); 4003 clock = clock_lo | (clock_hi << 32ULL); 4004 break; 4005 case IP_VERSION(9, 1, 0): 4006 case IP_VERSION(9, 2, 2): 4007 preempt_disable(); 4008 if (adev->rev_id >= 0x8) { 4009 clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4010 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4011 hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2); 4012 } else { 4013 clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4014 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4015 hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven); 4016 } 4017 /* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over 4018 * roughly every 42 seconds. 4019 */ 4020 if (hi_check != clock_hi) { 4021 if (adev->rev_id >= 0x8) 4022 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2); 4023 else 4024 clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven); 4025 clock_hi = hi_check; 4026 } 4027 preempt_enable(); 4028 clock = clock_lo | (clock_hi << 32ULL); 4029 break; 4030 default: 4031 amdgpu_gfx_off_ctrl(adev, false); 4032 mutex_lock(&adev->gfx.gpu_clock_mutex); 4033 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { 4034 clock = gfx_v9_0_kiq_read_clock(adev); 4035 } else { 4036 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4037 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4038 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4039 } 4040 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4041 amdgpu_gfx_off_ctrl(adev, true); 4042 break; 4043 } 4044 return clock; 4045 } 4046 4047 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4048 uint32_t vmid, 4049 uint32_t gds_base, uint32_t gds_size, 4050 uint32_t gws_base, uint32_t gws_size, 4051 uint32_t oa_base, uint32_t oa_size) 4052 { 4053 struct amdgpu_device *adev = ring->adev; 4054 4055 /* GDS Base */ 4056 gfx_v9_0_write_data_to_reg(ring, 0, false, 4057 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4058 gds_base); 4059 4060 /* GDS Size */ 4061 gfx_v9_0_write_data_to_reg(ring, 0, false, 4062 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4063 gds_size); 4064 4065 /* GWS */ 4066 gfx_v9_0_write_data_to_reg(ring, 0, false, 4067 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4068 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4069 4070 /* OA */ 4071 gfx_v9_0_write_data_to_reg(ring, 0, false, 4072 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4073 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4074 } 4075 4076 static const u32 vgpr_init_compute_shader[] = 4077 { 4078 0xb07c0000, 0xbe8000ff, 4079 0x000000f8, 0xbf110800, 4080 0x7e000280, 0x7e020280, 4081 0x7e040280, 0x7e060280, 4082 0x7e080280, 0x7e0a0280, 4083 0x7e0c0280, 0x7e0e0280, 4084 0x80808800, 0xbe803200, 4085 0xbf84fff5, 0xbf9c0000, 4086 0xd28c0001, 0x0001007f, 4087 0xd28d0001, 0x0002027e, 4088 0x10020288, 0xb8810904, 4089 0xb7814000, 0xd1196a01, 4090 0x00000301, 0xbe800087, 4091 0xbefc00c1, 0xd89c4000, 4092 0x00020201, 0xd89cc080, 4093 0x00040401, 0x320202ff, 4094 0x00000800, 0x80808100, 4095 0xbf84fff8, 0x7e020280, 4096 0xbf810000, 0x00000000, 4097 }; 4098 4099 static const u32 sgpr_init_compute_shader[] = 4100 { 4101 0xb07c0000, 0xbe8000ff, 4102 0x0000005f, 0xbee50080, 4103 0xbe812c65, 0xbe822c65, 4104 0xbe832c65, 0xbe842c65, 4105 0xbe852c65, 0xb77c0005, 4106 0x80808500, 0xbf84fff8, 4107 0xbe800080, 0xbf810000, 4108 }; 4109 4110 static const u32 vgpr_init_compute_shader_arcturus[] = { 4111 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4112 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4113 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4114 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4115 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4116 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4117 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4118 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4119 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4120 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4121 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4122 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4123 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4124 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4125 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4126 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4127 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4128 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4129 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4130 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4131 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4132 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4133 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4134 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4135 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4136 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4137 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4138 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4139 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4140 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4141 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4142 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4143 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4144 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4145 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4146 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4147 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4148 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4149 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4150 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4151 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4152 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4153 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4154 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4155 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4156 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4157 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4158 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4159 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4160 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4161 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4162 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4163 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4164 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4165 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4166 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4167 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4168 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4169 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4170 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4171 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4172 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4173 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4174 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4175 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4176 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4177 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4178 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4179 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4180 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4181 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4182 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4183 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4184 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4185 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4186 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4187 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4188 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4189 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4190 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4191 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4192 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4193 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4194 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4195 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4196 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4197 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4198 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4199 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4200 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4201 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4202 0xbf84fff8, 0xbf810000, 4203 }; 4204 4205 /* When below register arrays changed, please update gpr_reg_size, 4206 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4207 to cover all gfx9 ASICs */ 4208 static const struct soc15_reg_entry vgpr_init_regs[] = { 4209 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4210 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4211 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4212 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4213 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4214 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4215 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4216 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4217 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4218 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4219 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4220 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4221 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4222 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4223 }; 4224 4225 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4226 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4227 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4228 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4229 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4230 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4231 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4232 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4233 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4234 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4235 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4236 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4237 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4238 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4239 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4240 }; 4241 4242 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4243 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4244 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4245 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4246 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4247 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4248 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4249 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4250 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4251 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4252 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4253 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4254 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4255 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4256 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4257 }; 4258 4259 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4260 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4261 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4262 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4263 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4264 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4265 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4266 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4267 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4268 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4269 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4270 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4271 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4272 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4273 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4274 }; 4275 4276 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4277 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4278 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4279 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4280 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4281 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4282 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4283 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4284 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4285 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4286 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4287 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4288 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4289 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4290 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4291 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4292 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4293 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4294 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4295 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4296 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4297 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4298 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4299 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4300 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4301 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4302 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4303 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4304 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4305 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4306 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4307 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4308 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4309 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4310 }; 4311 4312 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4313 { 4314 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4315 int i, r; 4316 4317 /* only support when RAS is enabled */ 4318 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4319 return 0; 4320 4321 r = amdgpu_ring_alloc(ring, 7); 4322 if (r) { 4323 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4324 ring->name, r); 4325 return r; 4326 } 4327 4328 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4329 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4330 4331 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4332 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4333 PACKET3_DMA_DATA_DST_SEL(1) | 4334 PACKET3_DMA_DATA_SRC_SEL(2) | 4335 PACKET3_DMA_DATA_ENGINE(0))); 4336 amdgpu_ring_write(ring, 0); 4337 amdgpu_ring_write(ring, 0); 4338 amdgpu_ring_write(ring, 0); 4339 amdgpu_ring_write(ring, 0); 4340 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4341 adev->gds.gds_size); 4342 4343 amdgpu_ring_commit(ring); 4344 4345 for (i = 0; i < adev->usec_timeout; i++) { 4346 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4347 break; 4348 udelay(1); 4349 } 4350 4351 if (i >= adev->usec_timeout) 4352 r = -ETIMEDOUT; 4353 4354 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4355 4356 return r; 4357 } 4358 4359 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4360 { 4361 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4362 struct amdgpu_ib ib; 4363 struct dma_fence *f = NULL; 4364 int r, i; 4365 unsigned total_size, vgpr_offset, sgpr_offset; 4366 u64 gpu_addr; 4367 4368 int compute_dim_x = adev->gfx.config.max_shader_engines * 4369 adev->gfx.config.max_cu_per_sh * 4370 adev->gfx.config.max_sh_per_se; 4371 int sgpr_work_group_size = 5; 4372 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4373 int vgpr_init_shader_size; 4374 const u32 *vgpr_init_shader_ptr; 4375 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4376 4377 /* only support when RAS is enabled */ 4378 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4379 return 0; 4380 4381 /* bail if the compute ring is not ready */ 4382 if (!ring->sched.ready) 4383 return 0; 4384 4385 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 4386 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4387 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4388 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4389 } else { 4390 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4391 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4392 vgpr_init_regs_ptr = vgpr_init_regs; 4393 } 4394 4395 total_size = 4396 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4397 total_size += 4398 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4399 total_size += 4400 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4401 total_size = ALIGN(total_size, 256); 4402 vgpr_offset = total_size; 4403 total_size += ALIGN(vgpr_init_shader_size, 256); 4404 sgpr_offset = total_size; 4405 total_size += sizeof(sgpr_init_compute_shader); 4406 4407 /* allocate an indirect buffer to put the commands in */ 4408 memset(&ib, 0, sizeof(ib)); 4409 r = amdgpu_ib_get(adev, NULL, total_size, 4410 AMDGPU_IB_POOL_DIRECT, &ib); 4411 if (r) { 4412 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4413 return r; 4414 } 4415 4416 /* load the compute shaders */ 4417 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4418 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4419 4420 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4421 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4422 4423 /* init the ib length to 0 */ 4424 ib.length_dw = 0; 4425 4426 /* VGPR */ 4427 /* write the register state for the compute dispatch */ 4428 for (i = 0; i < gpr_reg_size; i++) { 4429 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4430 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4431 - PACKET3_SET_SH_REG_START; 4432 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4433 } 4434 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4435 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4436 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4437 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4438 - PACKET3_SET_SH_REG_START; 4439 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4440 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4441 4442 /* write dispatch packet */ 4443 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4444 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4445 ib.ptr[ib.length_dw++] = 1; /* y */ 4446 ib.ptr[ib.length_dw++] = 1; /* z */ 4447 ib.ptr[ib.length_dw++] = 4448 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4449 4450 /* write CS partial flush packet */ 4451 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4452 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4453 4454 /* SGPR1 */ 4455 /* write the register state for the compute dispatch */ 4456 for (i = 0; i < gpr_reg_size; i++) { 4457 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4458 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4459 - PACKET3_SET_SH_REG_START; 4460 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4461 } 4462 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4463 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4464 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4465 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4466 - PACKET3_SET_SH_REG_START; 4467 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4468 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4469 4470 /* write dispatch packet */ 4471 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4472 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4473 ib.ptr[ib.length_dw++] = 1; /* y */ 4474 ib.ptr[ib.length_dw++] = 1; /* z */ 4475 ib.ptr[ib.length_dw++] = 4476 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4477 4478 /* write CS partial flush packet */ 4479 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4480 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4481 4482 /* SGPR2 */ 4483 /* write the register state for the compute dispatch */ 4484 for (i = 0; i < gpr_reg_size; i++) { 4485 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4486 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4487 - PACKET3_SET_SH_REG_START; 4488 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4489 } 4490 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4491 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4492 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4493 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4494 - PACKET3_SET_SH_REG_START; 4495 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4496 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4497 4498 /* write dispatch packet */ 4499 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4500 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4501 ib.ptr[ib.length_dw++] = 1; /* y */ 4502 ib.ptr[ib.length_dw++] = 1; /* z */ 4503 ib.ptr[ib.length_dw++] = 4504 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4505 4506 /* write CS partial flush packet */ 4507 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4508 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4509 4510 /* shedule the ib on the ring */ 4511 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4512 if (r) { 4513 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4514 goto fail; 4515 } 4516 4517 /* wait for the GPU to finish processing the IB */ 4518 r = dma_fence_wait(f, false); 4519 if (r) { 4520 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4521 goto fail; 4522 } 4523 4524 fail: 4525 amdgpu_ib_free(adev, &ib, NULL); 4526 dma_fence_put(f); 4527 4528 return r; 4529 } 4530 4531 static int gfx_v9_0_early_init(void *handle) 4532 { 4533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4534 4535 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 4536 4537 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 4538 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4539 adev->gfx.num_gfx_rings = 0; 4540 else 4541 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4542 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4543 AMDGPU_MAX_COMPUTE_RINGS); 4544 gfx_v9_0_set_kiq_pm4_funcs(adev); 4545 gfx_v9_0_set_ring_funcs(adev); 4546 gfx_v9_0_set_irq_funcs(adev); 4547 gfx_v9_0_set_gds_init(adev); 4548 gfx_v9_0_set_rlc_funcs(adev); 4549 4550 /* init rlcg reg access ctrl */ 4551 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4552 4553 return gfx_v9_0_init_microcode(adev); 4554 } 4555 4556 static int gfx_v9_0_ecc_late_init(void *handle) 4557 { 4558 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4559 int r; 4560 4561 /* 4562 * Temp workaround to fix the issue that CP firmware fails to 4563 * update read pointer when CPDMA is writing clearing operation 4564 * to GDS in suspend/resume sequence on several cards. So just 4565 * limit this operation in cold boot sequence. 4566 */ 4567 if ((!adev->in_suspend) && 4568 (adev->gds.gds_size)) { 4569 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4570 if (r) 4571 return r; 4572 } 4573 4574 /* requires IBs so do in late init after IB pool is initialized */ 4575 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4576 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4577 else 4578 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4579 4580 if (r) 4581 return r; 4582 4583 if (adev->gfx.ras && 4584 adev->gfx.ras->enable_watchdog_timer) 4585 adev->gfx.ras->enable_watchdog_timer(adev); 4586 4587 return 0; 4588 } 4589 4590 static int gfx_v9_0_late_init(void *handle) 4591 { 4592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4593 int r; 4594 4595 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4596 if (r) 4597 return r; 4598 4599 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4600 if (r) 4601 return r; 4602 4603 r = gfx_v9_0_ecc_late_init(handle); 4604 if (r) 4605 return r; 4606 4607 return 0; 4608 } 4609 4610 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4611 { 4612 uint32_t rlc_setting; 4613 4614 /* if RLC is not enabled, do nothing */ 4615 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4616 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4617 return false; 4618 4619 return true; 4620 } 4621 4622 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4623 { 4624 uint32_t data; 4625 unsigned i; 4626 4627 data = RLC_SAFE_MODE__CMD_MASK; 4628 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4629 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4630 4631 /* wait for RLC_SAFE_MODE */ 4632 for (i = 0; i < adev->usec_timeout; i++) { 4633 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4634 break; 4635 udelay(1); 4636 } 4637 } 4638 4639 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4640 { 4641 uint32_t data; 4642 4643 data = RLC_SAFE_MODE__CMD_MASK; 4644 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4645 } 4646 4647 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4648 bool enable) 4649 { 4650 amdgpu_gfx_rlc_enter_safe_mode(adev); 4651 4652 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4653 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4654 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4655 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4656 } else { 4657 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4658 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4659 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4660 } 4661 4662 amdgpu_gfx_rlc_exit_safe_mode(adev); 4663 } 4664 4665 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4666 bool enable) 4667 { 4668 /* TODO: double check if we need to perform under safe mode */ 4669 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4670 4671 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4672 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4673 else 4674 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4675 4676 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4677 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4678 else 4679 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4680 4681 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4682 } 4683 4684 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4685 bool enable) 4686 { 4687 uint32_t data, def; 4688 4689 amdgpu_gfx_rlc_enter_safe_mode(adev); 4690 4691 /* It is disabled by HW by default */ 4692 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4693 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4694 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4695 4696 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4697 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4698 4699 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4700 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4701 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4702 4703 /* only for Vega10 & Raven1 */ 4704 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4705 4706 if (def != data) 4707 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4708 4709 /* MGLS is a global flag to control all MGLS in GFX */ 4710 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4711 /* 2 - RLC memory Light sleep */ 4712 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4713 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4714 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4715 if (def != data) 4716 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4717 } 4718 /* 3 - CP memory Light sleep */ 4719 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4720 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4721 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4722 if (def != data) 4723 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4724 } 4725 } 4726 } else { 4727 /* 1 - MGCG_OVERRIDE */ 4728 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4729 4730 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4731 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4732 4733 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4734 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4735 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4736 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4737 4738 if (def != data) 4739 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4740 4741 /* 2 - disable MGLS in RLC */ 4742 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4743 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4744 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4745 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4746 } 4747 4748 /* 3 - disable MGLS in CP */ 4749 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4750 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4751 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4752 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4753 } 4754 } 4755 4756 amdgpu_gfx_rlc_exit_safe_mode(adev); 4757 } 4758 4759 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4760 bool enable) 4761 { 4762 uint32_t data, def; 4763 4764 if (!adev->gfx.num_gfx_rings) 4765 return; 4766 4767 amdgpu_gfx_rlc_enter_safe_mode(adev); 4768 4769 /* Enable 3D CGCG/CGLS */ 4770 if (enable) { 4771 /* write cmd to clear cgcg/cgls ov */ 4772 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4773 /* unset CGCG override */ 4774 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4775 /* update CGCG and CGLS override bits */ 4776 if (def != data) 4777 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4778 4779 /* enable 3Dcgcg FSM(0x0000363f) */ 4780 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4781 4782 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4783 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4784 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4785 else 4786 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4787 4788 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4789 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4790 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4791 if (def != data) 4792 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4793 4794 /* set IDLE_POLL_COUNT(0x00900100) */ 4795 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4796 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4797 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4798 if (def != data) 4799 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4800 } else { 4801 /* Disable CGCG/CGLS */ 4802 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4803 /* disable cgcg, cgls should be disabled */ 4804 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4805 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4806 /* disable cgcg and cgls in FSM */ 4807 if (def != data) 4808 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4809 } 4810 4811 amdgpu_gfx_rlc_exit_safe_mode(adev); 4812 } 4813 4814 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4815 bool enable) 4816 { 4817 uint32_t def, data; 4818 4819 amdgpu_gfx_rlc_enter_safe_mode(adev); 4820 4821 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4822 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4823 /* unset CGCG override */ 4824 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4825 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4826 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4827 else 4828 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4829 /* update CGCG and CGLS override bits */ 4830 if (def != data) 4831 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4832 4833 /* enable cgcg FSM(0x0000363F) */ 4834 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4835 4836 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) 4837 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4838 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4839 else 4840 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4841 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4842 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4843 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4844 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4845 if (def != data) 4846 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4847 4848 /* set IDLE_POLL_COUNT(0x00900100) */ 4849 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4850 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4851 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4852 if (def != data) 4853 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4854 } else { 4855 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4856 /* reset CGCG/CGLS bits */ 4857 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4858 /* disable cgcg and cgls in FSM */ 4859 if (def != data) 4860 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4861 } 4862 4863 amdgpu_gfx_rlc_exit_safe_mode(adev); 4864 } 4865 4866 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4867 bool enable) 4868 { 4869 if (enable) { 4870 /* CGCG/CGLS should be enabled after MGCG/MGLS 4871 * === MGCG + MGLS === 4872 */ 4873 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4874 /* === CGCG /CGLS for GFX 3D Only === */ 4875 gfx_v9_0_update_3d_clock_gating(adev, enable); 4876 /* === CGCG + CGLS === */ 4877 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4878 } else { 4879 /* CGCG/CGLS should be disabled before MGCG/MGLS 4880 * === CGCG + CGLS === 4881 */ 4882 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4883 /* === CGCG /CGLS for GFX 3D Only === */ 4884 gfx_v9_0_update_3d_clock_gating(adev, enable); 4885 /* === MGCG + MGLS === */ 4886 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4887 } 4888 return 0; 4889 } 4890 4891 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4892 { 4893 u32 reg, data; 4894 4895 amdgpu_gfx_off_ctrl(adev, false); 4896 4897 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 4898 if (amdgpu_sriov_is_pp_one_vf(adev)) 4899 data = RREG32_NO_KIQ(reg); 4900 else 4901 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4902 4903 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4904 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4905 4906 if (amdgpu_sriov_is_pp_one_vf(adev)) 4907 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 4908 else 4909 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4910 4911 amdgpu_gfx_off_ctrl(adev, true); 4912 } 4913 4914 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4915 uint32_t offset, 4916 struct soc15_reg_rlcg *entries, int arr_size) 4917 { 4918 int i; 4919 uint32_t reg; 4920 4921 if (!entries) 4922 return false; 4923 4924 for (i = 0; i < arr_size; i++) { 4925 const struct soc15_reg_rlcg *entry; 4926 4927 entry = &entries[i]; 4928 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4929 if (offset == reg) 4930 return true; 4931 } 4932 4933 return false; 4934 } 4935 4936 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4937 { 4938 return gfx_v9_0_check_rlcg_range(adev, offset, 4939 (void *)rlcg_access_gc_9_0, 4940 ARRAY_SIZE(rlcg_access_gc_9_0)); 4941 } 4942 4943 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 4944 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 4945 .set_safe_mode = gfx_v9_0_set_safe_mode, 4946 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 4947 .init = gfx_v9_0_rlc_init, 4948 .get_csb_size = gfx_v9_0_get_csb_size, 4949 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 4950 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 4951 .resume = gfx_v9_0_rlc_resume, 4952 .stop = gfx_v9_0_rlc_stop, 4953 .reset = gfx_v9_0_rlc_reset, 4954 .start = gfx_v9_0_rlc_start, 4955 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 4956 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 4957 }; 4958 4959 static int gfx_v9_0_set_powergating_state(void *handle, 4960 enum amd_powergating_state state) 4961 { 4962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4963 bool enable = (state == AMD_PG_STATE_GATE); 4964 4965 switch (adev->ip_versions[GC_HWIP][0]) { 4966 case IP_VERSION(9, 2, 2): 4967 case IP_VERSION(9, 1, 0): 4968 case IP_VERSION(9, 3, 0): 4969 if (!enable) 4970 amdgpu_gfx_off_ctrl(adev, false); 4971 4972 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4973 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 4974 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 4975 } else { 4976 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 4977 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 4978 } 4979 4980 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4981 gfx_v9_0_enable_cp_power_gating(adev, true); 4982 else 4983 gfx_v9_0_enable_cp_power_gating(adev, false); 4984 4985 /* update gfx cgpg state */ 4986 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 4987 4988 /* update mgcg state */ 4989 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 4990 4991 if (enable) 4992 amdgpu_gfx_off_ctrl(adev, true); 4993 break; 4994 case IP_VERSION(9, 2, 1): 4995 amdgpu_gfx_off_ctrl(adev, enable); 4996 break; 4997 default: 4998 break; 4999 } 5000 5001 return 0; 5002 } 5003 5004 static int gfx_v9_0_set_clockgating_state(void *handle, 5005 enum amd_clockgating_state state) 5006 { 5007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5008 5009 if (amdgpu_sriov_vf(adev)) 5010 return 0; 5011 5012 switch (adev->ip_versions[GC_HWIP][0]) { 5013 case IP_VERSION(9, 0, 1): 5014 case IP_VERSION(9, 2, 1): 5015 case IP_VERSION(9, 4, 0): 5016 case IP_VERSION(9, 2, 2): 5017 case IP_VERSION(9, 1, 0): 5018 case IP_VERSION(9, 4, 1): 5019 case IP_VERSION(9, 3, 0): 5020 case IP_VERSION(9, 4, 2): 5021 gfx_v9_0_update_gfx_clock_gating(adev, 5022 state == AMD_CG_STATE_GATE); 5023 break; 5024 default: 5025 break; 5026 } 5027 return 0; 5028 } 5029 5030 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5031 { 5032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5033 int data; 5034 5035 if (amdgpu_sriov_vf(adev)) 5036 *flags = 0; 5037 5038 /* AMD_CG_SUPPORT_GFX_MGCG */ 5039 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5040 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5041 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5042 5043 /* AMD_CG_SUPPORT_GFX_CGCG */ 5044 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5045 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5046 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5047 5048 /* AMD_CG_SUPPORT_GFX_CGLS */ 5049 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5050 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5051 5052 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5053 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5054 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5055 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5056 5057 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5058 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5059 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5060 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5061 5062 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { 5063 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5064 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5065 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5066 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5067 5068 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5069 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5070 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5071 } 5072 } 5073 5074 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5075 { 5076 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5077 } 5078 5079 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5080 { 5081 struct amdgpu_device *adev = ring->adev; 5082 u64 wptr; 5083 5084 /* XXX check if swapping is necessary on BE */ 5085 if (ring->use_doorbell) { 5086 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5087 } else { 5088 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5089 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5090 } 5091 5092 return wptr; 5093 } 5094 5095 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5096 { 5097 struct amdgpu_device *adev = ring->adev; 5098 5099 if (ring->use_doorbell) { 5100 /* XXX check if swapping is necessary on BE */ 5101 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5102 WDOORBELL64(ring->doorbell_index, ring->wptr); 5103 } else { 5104 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5105 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5106 } 5107 } 5108 5109 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5110 { 5111 struct amdgpu_device *adev = ring->adev; 5112 u32 ref_and_mask, reg_mem_engine; 5113 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5114 5115 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5116 switch (ring->me) { 5117 case 1: 5118 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5119 break; 5120 case 2: 5121 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5122 break; 5123 default: 5124 return; 5125 } 5126 reg_mem_engine = 0; 5127 } else { 5128 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5129 reg_mem_engine = 1; /* pfp */ 5130 } 5131 5132 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5133 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5134 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5135 ref_and_mask, ref_and_mask, 0x20); 5136 } 5137 5138 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5139 struct amdgpu_job *job, 5140 struct amdgpu_ib *ib, 5141 uint32_t flags) 5142 { 5143 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5144 u32 header, control = 0; 5145 5146 if (ib->flags & AMDGPU_IB_FLAG_CE) 5147 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5148 else 5149 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5150 5151 control |= ib->length_dw | (vmid << 24); 5152 5153 if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 5154 control |= INDIRECT_BUFFER_PRE_ENB(1); 5155 5156 if (flags & AMDGPU_IB_PREEMPTED) 5157 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5158 5159 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5160 gfx_v9_0_ring_emit_de_meta(ring, 5161 (!amdgpu_sriov_vf(ring->adev) && 5162 flags & AMDGPU_IB_PREEMPTED) ? 5163 true : false); 5164 } 5165 5166 amdgpu_ring_write(ring, header); 5167 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5168 amdgpu_ring_write(ring, 5169 #ifdef __BIG_ENDIAN 5170 (2 << 0) | 5171 #endif 5172 lower_32_bits(ib->gpu_addr)); 5173 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5174 amdgpu_ring_write(ring, control); 5175 } 5176 5177 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5178 struct amdgpu_job *job, 5179 struct amdgpu_ib *ib, 5180 uint32_t flags) 5181 { 5182 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5183 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5184 5185 /* Currently, there is a high possibility to get wave ID mismatch 5186 * between ME and GDS, leading to a hw deadlock, because ME generates 5187 * different wave IDs than the GDS expects. This situation happens 5188 * randomly when at least 5 compute pipes use GDS ordered append. 5189 * The wave IDs generated by ME are also wrong after suspend/resume. 5190 * Those are probably bugs somewhere else in the kernel driver. 5191 * 5192 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5193 * GDS to 0 for this ring (me/pipe). 5194 */ 5195 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5196 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5197 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5198 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5199 } 5200 5201 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5202 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5203 amdgpu_ring_write(ring, 5204 #ifdef __BIG_ENDIAN 5205 (2 << 0) | 5206 #endif 5207 lower_32_bits(ib->gpu_addr)); 5208 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5209 amdgpu_ring_write(ring, control); 5210 } 5211 5212 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5213 u64 seq, unsigned flags) 5214 { 5215 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5216 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5217 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5218 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 5219 uint32_t dw2 = 0; 5220 5221 /* RELEASE_MEM - flush caches, send int */ 5222 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5223 5224 if (writeback) { 5225 dw2 = EOP_TC_NC_ACTION_EN; 5226 } else { 5227 dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | 5228 EOP_TC_MD_ACTION_EN; 5229 } 5230 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5231 EVENT_INDEX(5); 5232 if (exec) 5233 dw2 |= EOP_EXEC; 5234 5235 amdgpu_ring_write(ring, dw2); 5236 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5237 5238 /* 5239 * the address should be Qword aligned if 64bit write, Dword 5240 * aligned if only send 32bit data low (discard data high) 5241 */ 5242 if (write64bit) 5243 BUG_ON(addr & 0x7); 5244 else 5245 BUG_ON(addr & 0x3); 5246 amdgpu_ring_write(ring, lower_32_bits(addr)); 5247 amdgpu_ring_write(ring, upper_32_bits(addr)); 5248 amdgpu_ring_write(ring, lower_32_bits(seq)); 5249 amdgpu_ring_write(ring, upper_32_bits(seq)); 5250 amdgpu_ring_write(ring, 0); 5251 } 5252 5253 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5254 { 5255 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5256 uint32_t seq = ring->fence_drv.sync_seq; 5257 uint64_t addr = ring->fence_drv.gpu_addr; 5258 5259 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5260 lower_32_bits(addr), upper_32_bits(addr), 5261 seq, 0xffffffff, 4); 5262 } 5263 5264 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5265 unsigned vmid, uint64_t pd_addr) 5266 { 5267 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5268 5269 /* compute doesn't have PFP */ 5270 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5271 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5272 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5273 amdgpu_ring_write(ring, 0x0); 5274 } 5275 } 5276 5277 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5278 { 5279 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5280 } 5281 5282 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5283 { 5284 u64 wptr; 5285 5286 /* XXX check if swapping is necessary on BE */ 5287 if (ring->use_doorbell) 5288 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5289 else 5290 BUG(); 5291 return wptr; 5292 } 5293 5294 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5295 { 5296 struct amdgpu_device *adev = ring->adev; 5297 5298 /* XXX check if swapping is necessary on BE */ 5299 if (ring->use_doorbell) { 5300 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5301 WDOORBELL64(ring->doorbell_index, ring->wptr); 5302 } else{ 5303 BUG(); /* only DOORBELL method supported on gfx9 now */ 5304 } 5305 } 5306 5307 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5308 u64 seq, unsigned int flags) 5309 { 5310 struct amdgpu_device *adev = ring->adev; 5311 5312 /* we only allocate 32bit for each seq wb address */ 5313 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5314 5315 /* write fence seq to the "addr" */ 5316 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5317 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5318 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5319 amdgpu_ring_write(ring, lower_32_bits(addr)); 5320 amdgpu_ring_write(ring, upper_32_bits(addr)); 5321 amdgpu_ring_write(ring, lower_32_bits(seq)); 5322 5323 if (flags & AMDGPU_FENCE_FLAG_INT) { 5324 /* set register to trigger INT */ 5325 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5326 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5327 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5328 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5329 amdgpu_ring_write(ring, 0); 5330 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5331 } 5332 } 5333 5334 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5335 { 5336 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5337 amdgpu_ring_write(ring, 0); 5338 } 5339 5340 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 5341 { 5342 struct amdgpu_device *adev = ring->adev; 5343 struct v9_ce_ib_state ce_payload = {0}; 5344 uint64_t offset, ce_payload_gpu_addr; 5345 void *ce_payload_cpu_addr; 5346 int cnt; 5347 5348 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5349 5350 if (ring->is_mes_queue) { 5351 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5352 gfx[0].gfx_meta_data) + 5353 offsetof(struct v9_gfx_meta_data, ce_payload); 5354 ce_payload_gpu_addr = 5355 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5356 ce_payload_cpu_addr = 5357 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5358 } else { 5359 offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5360 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5361 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5362 } 5363 5364 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5365 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5366 WRITE_DATA_DST_SEL(8) | 5367 WR_CONFIRM) | 5368 WRITE_DATA_CACHE_POLICY(0)); 5369 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5370 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5371 5372 if (resume) 5373 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5374 sizeof(ce_payload) >> 2); 5375 else 5376 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 5377 sizeof(ce_payload) >> 2); 5378 } 5379 5380 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 5381 { 5382 int i, r = 0; 5383 struct amdgpu_device *adev = ring->adev; 5384 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5385 struct amdgpu_ring *kiq_ring = &kiq->ring; 5386 unsigned long flags; 5387 5388 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5389 return -EINVAL; 5390 5391 spin_lock_irqsave(&kiq->ring_lock, flags); 5392 5393 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5394 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5395 return -ENOMEM; 5396 } 5397 5398 /* assert preemption condition */ 5399 amdgpu_ring_set_preempt_cond_exec(ring, false); 5400 5401 ring->trail_seq += 1; 5402 amdgpu_ring_alloc(ring, 13); 5403 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5404 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5405 /*reset the CP_VMID_PREEMPT after trailing fence*/ 5406 amdgpu_ring_emit_wreg(ring, 5407 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5408 0x0); 5409 5410 /* assert IB preemption, emit the trailing fence */ 5411 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5412 ring->trail_fence_gpu_addr, 5413 ring->trail_seq); 5414 5415 amdgpu_ring_commit(kiq_ring); 5416 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5417 5418 /* poll the trailing fence */ 5419 for (i = 0; i < adev->usec_timeout; i++) { 5420 if (ring->trail_seq == 5421 le32_to_cpu(*ring->trail_fence_cpu_addr)) 5422 break; 5423 udelay(1); 5424 } 5425 5426 if (i >= adev->usec_timeout) { 5427 r = -EINVAL; 5428 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5429 } 5430 5431 amdgpu_ring_commit(ring); 5432 5433 /* deassert preemption condition */ 5434 amdgpu_ring_set_preempt_cond_exec(ring, true); 5435 return r; 5436 } 5437 5438 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5439 { 5440 struct amdgpu_device *adev = ring->adev; 5441 struct v9_de_ib_state de_payload = {0}; 5442 uint64_t offset, gds_addr, de_payload_gpu_addr; 5443 void *de_payload_cpu_addr; 5444 int cnt; 5445 5446 if (ring->is_mes_queue) { 5447 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5448 gfx[0].gfx_meta_data) + 5449 offsetof(struct v9_gfx_meta_data, de_payload); 5450 de_payload_gpu_addr = 5451 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5452 de_payload_cpu_addr = 5453 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5454 5455 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5456 gfx[0].gds_backup) + 5457 offsetof(struct v9_gfx_meta_data, de_payload); 5458 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5459 } else { 5460 offset = offsetof(struct v9_gfx_meta_data, de_payload); 5461 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5462 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5463 5464 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5465 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5466 PAGE_SIZE); 5467 } 5468 5469 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5470 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5471 5472 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5473 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5474 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5475 WRITE_DATA_DST_SEL(8) | 5476 WR_CONFIRM) | 5477 WRITE_DATA_CACHE_POLICY(0)); 5478 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5479 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5480 5481 if (resume) 5482 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5483 sizeof(de_payload) >> 2); 5484 else 5485 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5486 sizeof(de_payload) >> 2); 5487 } 5488 5489 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5490 bool secure) 5491 { 5492 uint32_t v = secure ? FRAME_TMZ : 0; 5493 5494 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5495 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5496 } 5497 5498 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5499 { 5500 uint32_t dw2 = 0; 5501 5502 gfx_v9_0_ring_emit_ce_meta(ring, 5503 (!amdgpu_sriov_vf(ring->adev) && 5504 flags & AMDGPU_IB_PREEMPTED) ? true : false); 5505 5506 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5507 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5508 /* set load_global_config & load_global_uconfig */ 5509 dw2 |= 0x8001; 5510 /* set load_cs_sh_regs */ 5511 dw2 |= 0x01000000; 5512 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5513 dw2 |= 0x10002; 5514 5515 /* set load_ce_ram if preamble presented */ 5516 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5517 dw2 |= 0x10000000; 5518 } else { 5519 /* still load_ce_ram if this is the first time preamble presented 5520 * although there is no context switch happens. 5521 */ 5522 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5523 dw2 |= 0x10000000; 5524 } 5525 5526 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5527 amdgpu_ring_write(ring, dw2); 5528 amdgpu_ring_write(ring, 0); 5529 } 5530 5531 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5532 { 5533 unsigned ret; 5534 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5535 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5536 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5537 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5538 ret = ring->wptr & ring->buf_mask; 5539 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5540 return ret; 5541 } 5542 5543 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5544 { 5545 unsigned cur; 5546 BUG_ON(offset > ring->buf_mask); 5547 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5548 5549 cur = (ring->wptr - 1) & ring->buf_mask; 5550 if (likely(cur > offset)) 5551 ring->ring[offset] = cur - offset; 5552 else 5553 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5554 } 5555 5556 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5557 uint32_t reg_val_offs) 5558 { 5559 struct amdgpu_device *adev = ring->adev; 5560 5561 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5562 amdgpu_ring_write(ring, 0 | /* src: register*/ 5563 (5 << 8) | /* dst: memory */ 5564 (1 << 20)); /* write confirm */ 5565 amdgpu_ring_write(ring, reg); 5566 amdgpu_ring_write(ring, 0); 5567 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5568 reg_val_offs * 4)); 5569 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5570 reg_val_offs * 4)); 5571 } 5572 5573 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5574 uint32_t val) 5575 { 5576 uint32_t cmd = 0; 5577 5578 switch (ring->funcs->type) { 5579 case AMDGPU_RING_TYPE_GFX: 5580 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5581 break; 5582 case AMDGPU_RING_TYPE_KIQ: 5583 cmd = (1 << 16); /* no inc addr */ 5584 break; 5585 default: 5586 cmd = WR_CONFIRM; 5587 break; 5588 } 5589 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5590 amdgpu_ring_write(ring, cmd); 5591 amdgpu_ring_write(ring, reg); 5592 amdgpu_ring_write(ring, 0); 5593 amdgpu_ring_write(ring, val); 5594 } 5595 5596 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5597 uint32_t val, uint32_t mask) 5598 { 5599 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5600 } 5601 5602 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5603 uint32_t reg0, uint32_t reg1, 5604 uint32_t ref, uint32_t mask) 5605 { 5606 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5607 struct amdgpu_device *adev = ring->adev; 5608 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5609 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5610 5611 if (fw_version_ok) 5612 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5613 ref, mask, 0x20); 5614 else 5615 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5616 ref, mask); 5617 } 5618 5619 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5620 { 5621 struct amdgpu_device *adev = ring->adev; 5622 uint32_t value = 0; 5623 5624 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5625 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5626 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5627 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5628 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5629 } 5630 5631 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5632 enum amdgpu_interrupt_state state) 5633 { 5634 switch (state) { 5635 case AMDGPU_IRQ_STATE_DISABLE: 5636 case AMDGPU_IRQ_STATE_ENABLE: 5637 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5638 TIME_STAMP_INT_ENABLE, 5639 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5640 break; 5641 default: 5642 break; 5643 } 5644 } 5645 5646 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5647 int me, int pipe, 5648 enum amdgpu_interrupt_state state) 5649 { 5650 u32 mec_int_cntl, mec_int_cntl_reg; 5651 5652 /* 5653 * amdgpu controls only the first MEC. That's why this function only 5654 * handles the setting of interrupts for this specific MEC. All other 5655 * pipes' interrupts are set by amdkfd. 5656 */ 5657 5658 if (me == 1) { 5659 switch (pipe) { 5660 case 0: 5661 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5662 break; 5663 case 1: 5664 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5665 break; 5666 case 2: 5667 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5668 break; 5669 case 3: 5670 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5671 break; 5672 default: 5673 DRM_DEBUG("invalid pipe %d\n", pipe); 5674 return; 5675 } 5676 } else { 5677 DRM_DEBUG("invalid me %d\n", me); 5678 return; 5679 } 5680 5681 switch (state) { 5682 case AMDGPU_IRQ_STATE_DISABLE: 5683 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5684 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5685 TIME_STAMP_INT_ENABLE, 0); 5686 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5687 break; 5688 case AMDGPU_IRQ_STATE_ENABLE: 5689 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5690 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5691 TIME_STAMP_INT_ENABLE, 1); 5692 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5693 break; 5694 default: 5695 break; 5696 } 5697 } 5698 5699 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5700 struct amdgpu_irq_src *source, 5701 unsigned type, 5702 enum amdgpu_interrupt_state state) 5703 { 5704 switch (state) { 5705 case AMDGPU_IRQ_STATE_DISABLE: 5706 case AMDGPU_IRQ_STATE_ENABLE: 5707 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5708 PRIV_REG_INT_ENABLE, 5709 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5710 break; 5711 default: 5712 break; 5713 } 5714 5715 return 0; 5716 } 5717 5718 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5719 struct amdgpu_irq_src *source, 5720 unsigned type, 5721 enum amdgpu_interrupt_state state) 5722 { 5723 switch (state) { 5724 case AMDGPU_IRQ_STATE_DISABLE: 5725 case AMDGPU_IRQ_STATE_ENABLE: 5726 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5727 PRIV_INSTR_INT_ENABLE, 5728 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5729 break; 5730 default: 5731 break; 5732 } 5733 5734 return 0; 5735 } 5736 5737 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5738 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5739 CP_ECC_ERROR_INT_ENABLE, 1) 5740 5741 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5742 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5743 CP_ECC_ERROR_INT_ENABLE, 0) 5744 5745 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5746 struct amdgpu_irq_src *source, 5747 unsigned type, 5748 enum amdgpu_interrupt_state state) 5749 { 5750 switch (state) { 5751 case AMDGPU_IRQ_STATE_DISABLE: 5752 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5753 CP_ECC_ERROR_INT_ENABLE, 0); 5754 DISABLE_ECC_ON_ME_PIPE(1, 0); 5755 DISABLE_ECC_ON_ME_PIPE(1, 1); 5756 DISABLE_ECC_ON_ME_PIPE(1, 2); 5757 DISABLE_ECC_ON_ME_PIPE(1, 3); 5758 break; 5759 5760 case AMDGPU_IRQ_STATE_ENABLE: 5761 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5762 CP_ECC_ERROR_INT_ENABLE, 1); 5763 ENABLE_ECC_ON_ME_PIPE(1, 0); 5764 ENABLE_ECC_ON_ME_PIPE(1, 1); 5765 ENABLE_ECC_ON_ME_PIPE(1, 2); 5766 ENABLE_ECC_ON_ME_PIPE(1, 3); 5767 break; 5768 default: 5769 break; 5770 } 5771 5772 return 0; 5773 } 5774 5775 5776 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5777 struct amdgpu_irq_src *src, 5778 unsigned type, 5779 enum amdgpu_interrupt_state state) 5780 { 5781 switch (type) { 5782 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5783 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5784 break; 5785 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5786 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5787 break; 5788 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5789 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5790 break; 5791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5792 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5793 break; 5794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5795 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5796 break; 5797 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5798 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5799 break; 5800 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5801 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5802 break; 5803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5804 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5805 break; 5806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5807 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5808 break; 5809 default: 5810 break; 5811 } 5812 return 0; 5813 } 5814 5815 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5816 struct amdgpu_irq_src *source, 5817 struct amdgpu_iv_entry *entry) 5818 { 5819 int i; 5820 u8 me_id, pipe_id, queue_id; 5821 struct amdgpu_ring *ring; 5822 5823 DRM_DEBUG("IH: CP EOP\n"); 5824 me_id = (entry->ring_id & 0x0c) >> 2; 5825 pipe_id = (entry->ring_id & 0x03) >> 0; 5826 queue_id = (entry->ring_id & 0x70) >> 4; 5827 5828 switch (me_id) { 5829 case 0: 5830 if (adev->gfx.num_gfx_rings && 5831 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { 5832 /* Fence signals are handled on the software rings*/ 5833 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 5834 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); 5835 } 5836 break; 5837 case 1: 5838 case 2: 5839 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5840 ring = &adev->gfx.compute_ring[i]; 5841 /* Per-queue interrupt is supported for MEC starting from VI. 5842 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5843 */ 5844 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5845 amdgpu_fence_process(ring); 5846 } 5847 break; 5848 } 5849 return 0; 5850 } 5851 5852 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5853 struct amdgpu_iv_entry *entry) 5854 { 5855 u8 me_id, pipe_id, queue_id; 5856 struct amdgpu_ring *ring; 5857 int i; 5858 5859 me_id = (entry->ring_id & 0x0c) >> 2; 5860 pipe_id = (entry->ring_id & 0x03) >> 0; 5861 queue_id = (entry->ring_id & 0x70) >> 4; 5862 5863 switch (me_id) { 5864 case 0: 5865 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5866 break; 5867 case 1: 5868 case 2: 5869 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5870 ring = &adev->gfx.compute_ring[i]; 5871 if (ring->me == me_id && ring->pipe == pipe_id && 5872 ring->queue == queue_id) 5873 drm_sched_fault(&ring->sched); 5874 } 5875 break; 5876 } 5877 } 5878 5879 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5880 struct amdgpu_irq_src *source, 5881 struct amdgpu_iv_entry *entry) 5882 { 5883 DRM_ERROR("Illegal register access in command stream\n"); 5884 gfx_v9_0_fault(adev, entry); 5885 return 0; 5886 } 5887 5888 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5889 struct amdgpu_irq_src *source, 5890 struct amdgpu_iv_entry *entry) 5891 { 5892 DRM_ERROR("Illegal instruction in command stream\n"); 5893 gfx_v9_0_fault(adev, entry); 5894 return 0; 5895 } 5896 5897 5898 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5899 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5900 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5901 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5902 }, 5903 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5904 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5905 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5906 }, 5907 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5908 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5909 0, 0 5910 }, 5911 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5912 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5913 0, 0 5914 }, 5915 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5916 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5917 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5918 }, 5919 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5920 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5921 0, 0 5922 }, 5923 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5924 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5925 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5926 }, 5927 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5928 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5929 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5930 }, 5931 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5932 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5933 0, 0 5934 }, 5935 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5936 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5937 0, 0 5938 }, 5939 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5940 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5941 0, 0 5942 }, 5943 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5944 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5945 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5946 }, 5947 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5948 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5949 0, 0 5950 }, 5951 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5952 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5953 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5954 }, 5955 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5956 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5957 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5958 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5959 }, 5960 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5961 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5962 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5963 0, 0 5964 }, 5965 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5966 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5967 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5968 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5969 }, 5970 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5971 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5972 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5973 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5974 }, 5975 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5976 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5977 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5978 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5979 }, 5980 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5981 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5982 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5983 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5984 }, 5985 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5986 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5987 0, 0 5988 }, 5989 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5990 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5991 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5992 }, 5993 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5994 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5995 0, 0 5996 }, 5997 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5998 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5999 0, 0 6000 }, 6001 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6002 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 6003 0, 0 6004 }, 6005 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 6006 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 6007 0, 0 6008 }, 6009 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6010 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 6011 0, 0 6012 }, 6013 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 6014 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 6015 0, 0 6016 }, 6017 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6018 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 6019 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 6020 }, 6021 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6022 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 6023 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 6024 }, 6025 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6026 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 6027 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 6028 }, 6029 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6030 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6031 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6032 }, 6033 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6034 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6035 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6036 }, 6037 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6038 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6039 0, 0 6040 }, 6041 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6042 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6043 0, 0 6044 }, 6045 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6046 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6047 0, 0 6048 }, 6049 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6050 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6051 0, 0 6052 }, 6053 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6054 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6055 0, 0 6056 }, 6057 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6058 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6059 0, 0 6060 }, 6061 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6062 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6063 0, 0 6064 }, 6065 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6066 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6067 0, 0 6068 }, 6069 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6070 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6071 0, 0 6072 }, 6073 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6074 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6075 0, 0 6076 }, 6077 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6078 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6079 0, 0 6080 }, 6081 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6082 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6083 0, 0 6084 }, 6085 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6086 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6087 0, 0 6088 }, 6089 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6090 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6091 0, 0 6092 }, 6093 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6094 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6095 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6096 }, 6097 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6098 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6099 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6100 }, 6101 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6102 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6103 0, 0 6104 }, 6105 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6106 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6107 0, 0 6108 }, 6109 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6110 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6111 0, 0 6112 }, 6113 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6114 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6115 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6116 }, 6117 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6118 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6119 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6120 }, 6121 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6122 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6123 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6124 }, 6125 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6126 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6127 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6128 }, 6129 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6130 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6131 0, 0 6132 }, 6133 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6134 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6135 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6136 }, 6137 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6138 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6139 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6140 }, 6141 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6142 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6143 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6144 }, 6145 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6146 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6147 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6148 }, 6149 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6150 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6151 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6152 }, 6153 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6154 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6155 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6156 }, 6157 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6158 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6159 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6160 }, 6161 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6162 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6163 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6164 }, 6165 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6166 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6167 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6168 }, 6169 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6170 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6171 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6172 }, 6173 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6174 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6175 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6176 }, 6177 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6178 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6179 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6180 }, 6181 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6182 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6183 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6184 }, 6185 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6186 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6187 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6188 }, 6189 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6190 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6191 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6192 }, 6193 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6194 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6195 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6196 }, 6197 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6198 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6199 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6200 }, 6201 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6202 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6203 0, 0 6204 }, 6205 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6206 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6207 0, 0 6208 }, 6209 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6210 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6211 0, 0 6212 }, 6213 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6214 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6215 0, 0 6216 }, 6217 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6218 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6219 0, 0 6220 }, 6221 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6222 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6223 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6224 }, 6225 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6226 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6227 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6228 }, 6229 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6230 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6231 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6232 }, 6233 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6234 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6235 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6236 }, 6237 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6238 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6239 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6240 }, 6241 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6242 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6243 0, 0 6244 }, 6245 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6246 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6247 0, 0 6248 }, 6249 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6250 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6251 0, 0 6252 }, 6253 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6254 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6255 0, 0 6256 }, 6257 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6258 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6259 0, 0 6260 }, 6261 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6262 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6263 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6264 }, 6265 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6266 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6267 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6268 }, 6269 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6270 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6271 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6272 }, 6273 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6274 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6275 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6276 }, 6277 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6278 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6279 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6280 }, 6281 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6282 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6283 0, 0 6284 }, 6285 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6286 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6287 0, 0 6288 }, 6289 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6290 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6291 0, 0 6292 }, 6293 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6294 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6295 0, 0 6296 }, 6297 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6298 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6299 0, 0 6300 }, 6301 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6302 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6303 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6304 }, 6305 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6306 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6307 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6308 }, 6309 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6310 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6311 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6312 }, 6313 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6314 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6315 0, 0 6316 }, 6317 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6318 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6319 0, 0 6320 }, 6321 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6322 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6323 0, 0 6324 }, 6325 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6326 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6327 0, 0 6328 }, 6329 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6330 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6331 0, 0 6332 }, 6333 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6334 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6335 0, 0 6336 } 6337 }; 6338 6339 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6340 void *inject_if) 6341 { 6342 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6343 int ret; 6344 struct ta_ras_trigger_error_input block_info = { 0 }; 6345 6346 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6347 return -EINVAL; 6348 6349 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6350 return -EINVAL; 6351 6352 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6353 return -EPERM; 6354 6355 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6356 info->head.type)) { 6357 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6358 ras_gfx_subblocks[info->head.sub_block_index].name, 6359 info->head.type); 6360 return -EPERM; 6361 } 6362 6363 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6364 info->head.type)) { 6365 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6366 ras_gfx_subblocks[info->head.sub_block_index].name, 6367 info->head.type); 6368 return -EPERM; 6369 } 6370 6371 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6372 block_info.sub_block_index = 6373 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6374 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6375 block_info.address = info->address; 6376 block_info.value = info->value; 6377 6378 mutex_lock(&adev->grbm_idx_mutex); 6379 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6380 mutex_unlock(&adev->grbm_idx_mutex); 6381 6382 return ret; 6383 } 6384 6385 static const char *vml2_mems[] = { 6386 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6387 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6388 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6389 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6390 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6391 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6392 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6393 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6394 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6395 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6396 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6397 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6398 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6399 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6400 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6401 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6402 }; 6403 6404 static const char *vml2_walker_mems[] = { 6405 "UTC_VML2_CACHE_PDE0_MEM0", 6406 "UTC_VML2_CACHE_PDE0_MEM1", 6407 "UTC_VML2_CACHE_PDE1_MEM0", 6408 "UTC_VML2_CACHE_PDE1_MEM1", 6409 "UTC_VML2_CACHE_PDE2_MEM0", 6410 "UTC_VML2_CACHE_PDE2_MEM1", 6411 "UTC_VML2_RDIF_LOG_FIFO", 6412 }; 6413 6414 static const char *atc_l2_cache_2m_mems[] = { 6415 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6416 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6417 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6418 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6419 }; 6420 6421 static const char *atc_l2_cache_4k_mems[] = { 6422 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6423 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6424 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6425 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6426 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6427 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6428 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6429 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6430 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6431 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6432 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6433 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6434 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6435 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6436 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6437 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6438 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6439 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6440 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6441 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6442 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6443 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6444 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6445 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6446 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6447 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6448 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6449 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6450 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6451 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6452 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6453 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6454 }; 6455 6456 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6457 struct ras_err_data *err_data) 6458 { 6459 uint32_t i, data; 6460 uint32_t sec_count, ded_count; 6461 6462 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6463 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6464 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6465 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6466 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6467 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6468 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6469 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6470 6471 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6472 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6473 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6474 6475 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6476 if (sec_count) { 6477 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6478 "SEC %d\n", i, vml2_mems[i], sec_count); 6479 err_data->ce_count += sec_count; 6480 } 6481 6482 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6483 if (ded_count) { 6484 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6485 "DED %d\n", i, vml2_mems[i], ded_count); 6486 err_data->ue_count += ded_count; 6487 } 6488 } 6489 6490 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6491 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6492 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6493 6494 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6495 SEC_COUNT); 6496 if (sec_count) { 6497 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6498 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6499 err_data->ce_count += sec_count; 6500 } 6501 6502 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6503 DED_COUNT); 6504 if (ded_count) { 6505 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6506 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6507 err_data->ue_count += ded_count; 6508 } 6509 } 6510 6511 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6512 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6513 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6514 6515 sec_count = (data & 0x00006000L) >> 0xd; 6516 if (sec_count) { 6517 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6518 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6519 sec_count); 6520 err_data->ce_count += sec_count; 6521 } 6522 } 6523 6524 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6525 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6526 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6527 6528 sec_count = (data & 0x00006000L) >> 0xd; 6529 if (sec_count) { 6530 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6531 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6532 sec_count); 6533 err_data->ce_count += sec_count; 6534 } 6535 6536 ded_count = (data & 0x00018000L) >> 0xf; 6537 if (ded_count) { 6538 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6539 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6540 ded_count); 6541 err_data->ue_count += ded_count; 6542 } 6543 } 6544 6545 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6546 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6547 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6548 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6549 6550 return 0; 6551 } 6552 6553 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6554 const struct soc15_reg_entry *reg, 6555 uint32_t se_id, uint32_t inst_id, uint32_t value, 6556 uint32_t *sec_count, uint32_t *ded_count) 6557 { 6558 uint32_t i; 6559 uint32_t sec_cnt, ded_cnt; 6560 6561 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6562 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6563 gfx_v9_0_ras_fields[i].seg != reg->seg || 6564 gfx_v9_0_ras_fields[i].inst != reg->inst) 6565 continue; 6566 6567 sec_cnt = (value & 6568 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6569 gfx_v9_0_ras_fields[i].sec_count_shift; 6570 if (sec_cnt) { 6571 dev_info(adev->dev, "GFX SubBlock %s, " 6572 "Instance[%d][%d], SEC %d\n", 6573 gfx_v9_0_ras_fields[i].name, 6574 se_id, inst_id, 6575 sec_cnt); 6576 *sec_count += sec_cnt; 6577 } 6578 6579 ded_cnt = (value & 6580 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6581 gfx_v9_0_ras_fields[i].ded_count_shift; 6582 if (ded_cnt) { 6583 dev_info(adev->dev, "GFX SubBlock %s, " 6584 "Instance[%d][%d], DED %d\n", 6585 gfx_v9_0_ras_fields[i].name, 6586 se_id, inst_id, 6587 ded_cnt); 6588 *ded_count += ded_cnt; 6589 } 6590 } 6591 6592 return 0; 6593 } 6594 6595 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6596 { 6597 int i, j, k; 6598 6599 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6600 return; 6601 6602 /* read back registers to clear the counters */ 6603 mutex_lock(&adev->grbm_idx_mutex); 6604 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6605 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6606 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6607 amdgpu_gfx_select_se_sh(adev, j, 0x0, k); 6608 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6609 } 6610 } 6611 } 6612 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6613 mutex_unlock(&adev->grbm_idx_mutex); 6614 6615 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6616 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6617 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6618 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6619 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6620 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6621 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6622 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6623 6624 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6625 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6626 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6627 } 6628 6629 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6630 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6631 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6632 } 6633 6634 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6635 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6636 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6637 } 6638 6639 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6640 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6641 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6642 } 6643 6644 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6645 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6646 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6647 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6648 } 6649 6650 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6651 void *ras_error_status) 6652 { 6653 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6654 uint32_t sec_count = 0, ded_count = 0; 6655 uint32_t i, j, k; 6656 uint32_t reg_value; 6657 6658 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6659 return; 6660 6661 err_data->ue_count = 0; 6662 err_data->ce_count = 0; 6663 6664 mutex_lock(&adev->grbm_idx_mutex); 6665 6666 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6667 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6668 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6669 amdgpu_gfx_select_se_sh(adev, j, 0, k); 6670 reg_value = 6671 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6672 if (reg_value) 6673 gfx_v9_0_ras_error_count(adev, 6674 &gfx_v9_0_edc_counter_regs[i], 6675 j, k, reg_value, 6676 &sec_count, &ded_count); 6677 } 6678 } 6679 } 6680 6681 err_data->ce_count += sec_count; 6682 err_data->ue_count += ded_count; 6683 6684 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6685 mutex_unlock(&adev->grbm_idx_mutex); 6686 6687 gfx_v9_0_query_utc_edc_status(adev, err_data); 6688 } 6689 6690 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6691 { 6692 const unsigned int cp_coher_cntl = 6693 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6694 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6695 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6696 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6697 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6698 6699 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6700 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6701 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6702 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6703 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6704 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6705 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6706 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6707 } 6708 6709 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6710 uint32_t pipe, bool enable) 6711 { 6712 struct amdgpu_device *adev = ring->adev; 6713 uint32_t val; 6714 uint32_t wcl_cs_reg; 6715 6716 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6717 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6718 6719 switch (pipe) { 6720 case 0: 6721 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6722 break; 6723 case 1: 6724 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6725 break; 6726 case 2: 6727 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6728 break; 6729 case 3: 6730 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6731 break; 6732 default: 6733 DRM_DEBUG("invalid pipe %d\n", pipe); 6734 return; 6735 } 6736 6737 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6738 6739 } 6740 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6741 { 6742 struct amdgpu_device *adev = ring->adev; 6743 uint32_t val; 6744 int i; 6745 6746 6747 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6748 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6749 * around 25% of gpu resources. 6750 */ 6751 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6752 amdgpu_ring_emit_wreg(ring, 6753 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6754 val); 6755 6756 /* Restrict waves for normal/low priority compute queues as well 6757 * to get best QoS for high priority compute jobs. 6758 * 6759 * amdgpu controls only 1st ME(0-3 CS pipes). 6760 */ 6761 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6762 if (i != ring->pipe) 6763 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6764 6765 } 6766 } 6767 6768 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6769 .name = "gfx_v9_0", 6770 .early_init = gfx_v9_0_early_init, 6771 .late_init = gfx_v9_0_late_init, 6772 .sw_init = gfx_v9_0_sw_init, 6773 .sw_fini = gfx_v9_0_sw_fini, 6774 .hw_init = gfx_v9_0_hw_init, 6775 .hw_fini = gfx_v9_0_hw_fini, 6776 .suspend = gfx_v9_0_suspend, 6777 .resume = gfx_v9_0_resume, 6778 .is_idle = gfx_v9_0_is_idle, 6779 .wait_for_idle = gfx_v9_0_wait_for_idle, 6780 .soft_reset = gfx_v9_0_soft_reset, 6781 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6782 .set_powergating_state = gfx_v9_0_set_powergating_state, 6783 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6784 }; 6785 6786 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6787 .type = AMDGPU_RING_TYPE_GFX, 6788 .align_mask = 0xff, 6789 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6790 .support_64bit_ptrs = true, 6791 .secure_submission_supported = true, 6792 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6793 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6794 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6795 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6796 5 + /* COND_EXEC */ 6797 7 + /* PIPELINE_SYNC */ 6798 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6799 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6800 2 + /* VM_FLUSH */ 6801 8 + /* FENCE for VM_FLUSH */ 6802 20 + /* GDS switch */ 6803 4 + /* double SWITCH_BUFFER, 6804 the first COND_EXEC jump to the place just 6805 prior to this double SWITCH_BUFFER */ 6806 5 + /* COND_EXEC */ 6807 7 + /* HDP_flush */ 6808 4 + /* VGT_flush */ 6809 14 + /* CE_META */ 6810 31 + /* DE_META */ 6811 3 + /* CNTX_CTRL */ 6812 5 + /* HDP_INVL */ 6813 8 + 8 + /* FENCE x2 */ 6814 2 + /* SWITCH_BUFFER */ 6815 7, /* gfx_v9_0_emit_mem_sync */ 6816 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6817 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6818 .emit_fence = gfx_v9_0_ring_emit_fence, 6819 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6820 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6821 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6822 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6823 .test_ring = gfx_v9_0_ring_test_ring, 6824 .insert_nop = amdgpu_ring_insert_nop, 6825 .pad_ib = amdgpu_ring_generic_pad_ib, 6826 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6827 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6828 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6829 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6830 .preempt_ib = gfx_v9_0_ring_preempt_ib, 6831 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6832 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6833 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6834 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6835 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6836 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6837 }; 6838 6839 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 6840 .type = AMDGPU_RING_TYPE_GFX, 6841 .align_mask = 0xff, 6842 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6843 .support_64bit_ptrs = true, 6844 .secure_submission_supported = true, 6845 .get_rptr = amdgpu_sw_ring_get_rptr_gfx, 6846 .get_wptr = amdgpu_sw_ring_get_wptr_gfx, 6847 .set_wptr = amdgpu_sw_ring_set_wptr_gfx, 6848 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6849 5 + /* COND_EXEC */ 6850 7 + /* PIPELINE_SYNC */ 6851 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6852 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6853 2 + /* VM_FLUSH */ 6854 8 + /* FENCE for VM_FLUSH */ 6855 20 + /* GDS switch */ 6856 4 + /* double SWITCH_BUFFER, 6857 * the first COND_EXEC jump to the place just 6858 * prior to this double SWITCH_BUFFER 6859 */ 6860 5 + /* COND_EXEC */ 6861 7 + /* HDP_flush */ 6862 4 + /* VGT_flush */ 6863 14 + /* CE_META */ 6864 31 + /* DE_META */ 6865 3 + /* CNTX_CTRL */ 6866 5 + /* HDP_INVL */ 6867 8 + 8 + /* FENCE x2 */ 6868 2 + /* SWITCH_BUFFER */ 6869 7, /* gfx_v9_0_emit_mem_sync */ 6870 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6871 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6872 .emit_fence = gfx_v9_0_ring_emit_fence, 6873 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6874 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6875 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6876 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6877 .test_ring = gfx_v9_0_ring_test_ring, 6878 .test_ib = gfx_v9_0_ring_test_ib, 6879 .insert_nop = amdgpu_sw_ring_insert_nop, 6880 .pad_ib = amdgpu_ring_generic_pad_ib, 6881 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6882 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6883 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6884 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6885 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6886 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6887 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6888 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6889 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6890 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6891 }; 6892 6893 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6894 .type = AMDGPU_RING_TYPE_COMPUTE, 6895 .align_mask = 0xff, 6896 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6897 .support_64bit_ptrs = true, 6898 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6899 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6900 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6901 .emit_frame_size = 6902 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6903 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6904 5 + /* hdp invalidate */ 6905 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6906 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6907 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6908 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6909 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6910 7 + /* gfx_v9_0_emit_mem_sync */ 6911 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6912 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6913 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6914 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6915 .emit_fence = gfx_v9_0_ring_emit_fence, 6916 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6917 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6918 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6919 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6920 .test_ring = gfx_v9_0_ring_test_ring, 6921 .test_ib = gfx_v9_0_ring_test_ib, 6922 .insert_nop = amdgpu_ring_insert_nop, 6923 .pad_ib = amdgpu_ring_generic_pad_ib, 6924 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6925 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6926 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6927 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6928 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6929 }; 6930 6931 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6932 .type = AMDGPU_RING_TYPE_KIQ, 6933 .align_mask = 0xff, 6934 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6935 .support_64bit_ptrs = true, 6936 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6937 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6938 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6939 .emit_frame_size = 6940 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6941 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6942 5 + /* hdp invalidate */ 6943 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6944 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6945 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6946 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6947 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6948 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6949 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6950 .test_ring = gfx_v9_0_ring_test_ring, 6951 .insert_nop = amdgpu_ring_insert_nop, 6952 .pad_ib = amdgpu_ring_generic_pad_ib, 6953 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6954 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6955 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6956 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6957 }; 6958 6959 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6960 { 6961 int i; 6962 6963 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6964 6965 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6966 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6967 6968 if (adev->gfx.num_gfx_rings) { 6969 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 6970 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; 6971 } 6972 6973 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6974 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6975 } 6976 6977 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6978 .set = gfx_v9_0_set_eop_interrupt_state, 6979 .process = gfx_v9_0_eop_irq, 6980 }; 6981 6982 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6983 .set = gfx_v9_0_set_priv_reg_fault_state, 6984 .process = gfx_v9_0_priv_reg_irq, 6985 }; 6986 6987 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6988 .set = gfx_v9_0_set_priv_inst_fault_state, 6989 .process = gfx_v9_0_priv_inst_irq, 6990 }; 6991 6992 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6993 .set = gfx_v9_0_set_cp_ecc_error_state, 6994 .process = amdgpu_gfx_cp_ecc_error_irq, 6995 }; 6996 6997 6998 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6999 { 7000 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 7001 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 7002 7003 adev->gfx.priv_reg_irq.num_types = 1; 7004 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 7005 7006 adev->gfx.priv_inst_irq.num_types = 1; 7007 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 7008 7009 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 7010 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 7011 } 7012 7013 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 7014 { 7015 switch (adev->ip_versions[GC_HWIP][0]) { 7016 case IP_VERSION(9, 0, 1): 7017 case IP_VERSION(9, 2, 1): 7018 case IP_VERSION(9, 4, 0): 7019 case IP_VERSION(9, 2, 2): 7020 case IP_VERSION(9, 1, 0): 7021 case IP_VERSION(9, 4, 1): 7022 case IP_VERSION(9, 3, 0): 7023 case IP_VERSION(9, 4, 2): 7024 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 7025 break; 7026 default: 7027 break; 7028 } 7029 } 7030 7031 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 7032 { 7033 /* init asci gds info */ 7034 switch (adev->ip_versions[GC_HWIP][0]) { 7035 case IP_VERSION(9, 0, 1): 7036 case IP_VERSION(9, 2, 1): 7037 case IP_VERSION(9, 4, 0): 7038 adev->gds.gds_size = 0x10000; 7039 break; 7040 case IP_VERSION(9, 2, 2): 7041 case IP_VERSION(9, 1, 0): 7042 case IP_VERSION(9, 4, 1): 7043 adev->gds.gds_size = 0x1000; 7044 break; 7045 case IP_VERSION(9, 4, 2): 7046 /* aldebaran removed all the GDS internal memory, 7047 * only support GWS opcode in kernel, like barrier 7048 * semaphore.etc */ 7049 adev->gds.gds_size = 0; 7050 break; 7051 default: 7052 adev->gds.gds_size = 0x10000; 7053 break; 7054 } 7055 7056 switch (adev->ip_versions[GC_HWIP][0]) { 7057 case IP_VERSION(9, 0, 1): 7058 case IP_VERSION(9, 4, 0): 7059 adev->gds.gds_compute_max_wave_id = 0x7ff; 7060 break; 7061 case IP_VERSION(9, 2, 1): 7062 adev->gds.gds_compute_max_wave_id = 0x27f; 7063 break; 7064 case IP_VERSION(9, 2, 2): 7065 case IP_VERSION(9, 1, 0): 7066 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 7067 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 7068 else 7069 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 7070 break; 7071 case IP_VERSION(9, 4, 1): 7072 adev->gds.gds_compute_max_wave_id = 0xfff; 7073 break; 7074 case IP_VERSION(9, 4, 2): 7075 /* deprecated for Aldebaran, no usage at all */ 7076 adev->gds.gds_compute_max_wave_id = 0; 7077 break; 7078 default: 7079 /* this really depends on the chip */ 7080 adev->gds.gds_compute_max_wave_id = 0x7ff; 7081 break; 7082 } 7083 7084 adev->gds.gws_size = 64; 7085 adev->gds.oa_size = 16; 7086 } 7087 7088 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7089 u32 bitmap) 7090 { 7091 u32 data; 7092 7093 if (!bitmap) 7094 return; 7095 7096 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7097 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7098 7099 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7100 } 7101 7102 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7103 { 7104 u32 data, mask; 7105 7106 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7107 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7108 7109 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7110 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7111 7112 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7113 7114 return (~data) & mask; 7115 } 7116 7117 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7118 struct amdgpu_cu_info *cu_info) 7119 { 7120 int i, j, k, counter, active_cu_number = 0; 7121 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7122 unsigned disable_masks[4 * 4]; 7123 7124 if (!adev || !cu_info) 7125 return -EINVAL; 7126 7127 /* 7128 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7129 */ 7130 if (adev->gfx.config.max_shader_engines * 7131 adev->gfx.config.max_sh_per_se > 16) 7132 return -EINVAL; 7133 7134 amdgpu_gfx_parse_disable_cu(disable_masks, 7135 adev->gfx.config.max_shader_engines, 7136 adev->gfx.config.max_sh_per_se); 7137 7138 mutex_lock(&adev->grbm_idx_mutex); 7139 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7140 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7141 mask = 1; 7142 ao_bitmap = 0; 7143 counter = 0; 7144 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 7145 gfx_v9_0_set_user_cu_inactive_bitmap( 7146 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7147 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7148 7149 /* 7150 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7151 * 4x4 size array, and it's usually suitable for Vega 7152 * ASICs which has 4*2 SE/SH layout. 7153 * But for Arcturus, SE/SH layout is changed to 8*1. 7154 * To mostly reduce the impact, we make it compatible 7155 * with current bitmap array as below: 7156 * SE4,SH0 --> bitmap[0][1] 7157 * SE5,SH0 --> bitmap[1][1] 7158 * SE6,SH0 --> bitmap[2][1] 7159 * SE7,SH0 --> bitmap[3][1] 7160 */ 7161 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 7162 7163 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7164 if (bitmap & mask) { 7165 if (counter < adev->gfx.config.max_cu_per_sh) 7166 ao_bitmap |= mask; 7167 counter ++; 7168 } 7169 mask <<= 1; 7170 } 7171 active_cu_number += counter; 7172 if (i < 2 && j < 2) 7173 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7174 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7175 } 7176 } 7177 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7178 mutex_unlock(&adev->grbm_idx_mutex); 7179 7180 cu_info->number = active_cu_number; 7181 cu_info->ao_cu_mask = ao_cu_mask; 7182 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7183 7184 return 0; 7185 } 7186 7187 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7188 { 7189 .type = AMD_IP_BLOCK_TYPE_GFX, 7190 .major = 9, 7191 .minor = 0, 7192 .rev = 0, 7193 .funcs = &gfx_v9_0_ip_funcs, 7194 }; 7195