1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 42 #include "soc15_common.h" 43 #include "clearstate_gfx9.h" 44 #include "v9_structs.h" 45 46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 47 48 #include "amdgpu_ras.h" 49 50 #include "amdgpu_ring_mux.h" 51 #include "gfx_v9_4.h" 52 #include "gfx_v9_0.h" 53 #include "gfx_v9_4_2.h" 54 55 #include "asic_reg/pwr/pwr_10_0_offset.h" 56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 57 #include "asic_reg/gc/gc_9_0_default.h" 58 59 #define GFX9_NUM_GFX_RINGS 1 60 #define GFX9_NUM_SW_GFX_RINGS 2 61 #define GFX9_MEC_HPD_SIZE 4096 62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 114 115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 120 121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); 122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); 123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); 124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); 125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); 126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); 127 128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); 129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); 130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); 131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); 132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); 133 134 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 136 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 138 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 140 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 142 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 144 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 146 147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir 0x0025 148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX 1 149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 151 152 enum ta_ras_gfx_subblock { 153 /*CPC*/ 154 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 155 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 156 TA_RAS_BLOCK__GFX_CPC_UCODE, 157 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 158 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 159 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 160 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 161 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 162 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 163 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 164 /* CPF*/ 165 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 166 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 167 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 168 TA_RAS_BLOCK__GFX_CPF_TAG, 169 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 170 /* CPG*/ 171 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 172 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 173 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 174 TA_RAS_BLOCK__GFX_CPG_TAG, 175 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 176 /* GDS*/ 177 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 178 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 179 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 180 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 181 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 182 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 183 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 184 /* SPI*/ 185 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 186 /* SQ*/ 187 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 188 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 189 TA_RAS_BLOCK__GFX_SQ_LDS_D, 190 TA_RAS_BLOCK__GFX_SQ_LDS_I, 191 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 192 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 193 /* SQC (3 ranges)*/ 194 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 195 /* SQC range 0*/ 196 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 197 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 198 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 199 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 200 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 201 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 202 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 203 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 204 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 205 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 206 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 207 /* SQC range 1*/ 208 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 210 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 212 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 213 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 217 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 219 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 220 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 221 /* SQC range 2*/ 222 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 223 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 224 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 225 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 226 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 227 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 228 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 229 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 230 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 231 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 232 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 233 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 234 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 235 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 236 /* TA*/ 237 TA_RAS_BLOCK__GFX_TA_INDEX_START, 238 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 239 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 240 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 241 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 242 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 243 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 244 /* TCA*/ 245 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 246 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 247 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 248 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 249 /* TCC (5 sub-ranges)*/ 250 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 251 /* TCC range 0*/ 252 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 253 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 254 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 255 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 256 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 257 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 258 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 259 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 260 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 261 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 262 /* TCC range 1*/ 263 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 264 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 265 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 266 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 267 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 268 /* TCC range 2*/ 269 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 270 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 271 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 272 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 273 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 274 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 275 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 276 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 277 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 278 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 279 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 280 /* TCC range 3*/ 281 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 282 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 283 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 284 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 285 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 286 /* TCC range 4*/ 287 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 288 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 289 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 290 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 291 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 292 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 293 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 294 /* TCI*/ 295 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 296 /* TCP*/ 297 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 298 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 299 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 300 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 301 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 302 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 303 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 304 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 305 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 306 /* TD*/ 307 TA_RAS_BLOCK__GFX_TD_INDEX_START, 308 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 309 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 310 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 311 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 312 /* EA (3 sub-ranges)*/ 313 TA_RAS_BLOCK__GFX_EA_INDEX_START, 314 /* EA range 0*/ 315 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 316 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 317 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 318 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 319 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 320 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 321 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 322 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 323 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 324 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 325 /* EA range 1*/ 326 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 327 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 328 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 329 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 330 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 331 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 332 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 333 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 334 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 335 /* EA range 2*/ 336 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 337 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 338 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 339 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 340 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 341 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 342 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 343 /* UTC VM L2 bank*/ 344 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 345 /* UTC VM walker*/ 346 TA_RAS_BLOCK__UTC_VML2_WALKER, 347 /* UTC ATC L2 2MB cache*/ 348 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 349 /* UTC ATC L2 4KB cache*/ 350 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 351 TA_RAS_BLOCK__GFX_MAX 352 }; 353 354 struct ras_gfx_subblock { 355 unsigned char *name; 356 int ta_subblock; 357 int hw_supported_error_type; 358 int sw_supported_error_type; 359 }; 360 361 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 362 [AMDGPU_RAS_BLOCK__##subblock] = { \ 363 #subblock, \ 364 TA_RAS_BLOCK__##subblock, \ 365 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 366 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 367 } 368 369 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 370 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 371 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 372 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 373 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 375 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 378 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 379 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 380 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 382 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 383 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 384 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 386 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 387 0), 388 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 389 0), 390 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 392 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 394 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 396 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 398 0, 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 400 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 402 0, 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 404 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 406 0, 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 408 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 410 1), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 412 0, 0, 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 414 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 416 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 422 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 424 0, 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 426 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 430 0, 0, 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 432 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 434 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 436 0), 437 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 438 0), 439 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 440 0), 441 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 442 0, 0), 443 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 446 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 448 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 454 1), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 456 1), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 458 1), 459 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 460 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 462 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 464 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 466 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 468 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 475 0), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 478 0), 479 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 480 0, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 482 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 485 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 490 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 492 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 501 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 502 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 503 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 504 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 505 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 506 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 507 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 508 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 509 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 510 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 511 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 512 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 513 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 514 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 515 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 516 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 517 }; 518 519 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 520 { 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 541 }; 542 543 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 544 { 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 563 }; 564 565 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 566 { 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 578 }; 579 580 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 581 { 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 606 }; 607 608 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 609 { 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 617 }; 618 619 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 620 { 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 640 }; 641 642 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 643 { 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 656 }; 657 658 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 659 { 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 663 }; 664 665 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 666 { 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 683 }; 684 685 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 686 { 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 700 }; 701 702 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 703 { 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000) 715 }; 716 717 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 718 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 719 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 720 }; 721 722 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 723 { 724 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 725 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 726 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 727 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 728 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 729 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 730 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 731 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 732 }; 733 734 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 735 { 736 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 737 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 738 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 739 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 740 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 741 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 742 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 743 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 744 }; 745 746 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 747 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 748 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 749 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 750 751 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 752 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 753 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 754 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 755 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 756 struct amdgpu_cu_info *cu_info); 757 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 758 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 759 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 760 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 761 void *ras_error_status); 762 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 763 void *inject_if); 764 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 765 766 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 767 uint64_t queue_mask) 768 { 769 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 770 amdgpu_ring_write(kiq_ring, 771 PACKET3_SET_RESOURCES_VMID_MASK(0) | 772 /* vmid_mask:0* queue_type:0 (KIQ) */ 773 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 774 amdgpu_ring_write(kiq_ring, 775 lower_32_bits(queue_mask)); /* queue mask lo */ 776 amdgpu_ring_write(kiq_ring, 777 upper_32_bits(queue_mask)); /* queue mask hi */ 778 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 779 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 780 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 781 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 782 } 783 784 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 785 struct amdgpu_ring *ring) 786 { 787 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 788 uint64_t wptr_addr = ring->wptr_gpu_addr; 789 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 790 791 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 792 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 793 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 794 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 795 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 796 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 797 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 798 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 799 /*queue_type: normal compute queue */ 800 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 801 /* alloc format: all_on_one_pipe */ 802 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 803 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 804 /* num_queues: must be 1 */ 805 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 806 amdgpu_ring_write(kiq_ring, 807 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 808 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 809 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 810 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 811 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 812 } 813 814 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 815 struct amdgpu_ring *ring, 816 enum amdgpu_unmap_queues_action action, 817 u64 gpu_addr, u64 seq) 818 { 819 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 820 821 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 822 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 823 PACKET3_UNMAP_QUEUES_ACTION(action) | 824 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 825 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 826 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 827 amdgpu_ring_write(kiq_ring, 828 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 829 830 if (action == PREEMPT_QUEUES_NO_UNMAP) { 831 amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask)); 832 amdgpu_ring_write(kiq_ring, 0); 833 amdgpu_ring_write(kiq_ring, 0); 834 835 } else { 836 amdgpu_ring_write(kiq_ring, 0); 837 amdgpu_ring_write(kiq_ring, 0); 838 amdgpu_ring_write(kiq_ring, 0); 839 } 840 } 841 842 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 843 struct amdgpu_ring *ring, 844 u64 addr, 845 u64 seq) 846 { 847 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 848 849 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 850 amdgpu_ring_write(kiq_ring, 851 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 852 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 853 PACKET3_QUERY_STATUS_COMMAND(2)); 854 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 855 amdgpu_ring_write(kiq_ring, 856 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 857 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 858 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 859 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 860 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 861 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 862 } 863 864 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 865 uint16_t pasid, uint32_t flush_type, 866 bool all_hub) 867 { 868 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 869 amdgpu_ring_write(kiq_ring, 870 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 871 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 872 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 873 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 874 } 875 876 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 877 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 878 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 879 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 880 .kiq_query_status = gfx_v9_0_kiq_query_status, 881 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 882 .set_resources_size = 8, 883 .map_queues_size = 7, 884 .unmap_queues_size = 6, 885 .query_status_size = 7, 886 .invalidate_tlbs_size = 2, 887 }; 888 889 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 890 { 891 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 892 } 893 894 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 895 { 896 switch (adev->ip_versions[GC_HWIP][0]) { 897 case IP_VERSION(9, 0, 1): 898 soc15_program_register_sequence(adev, 899 golden_settings_gc_9_0, 900 ARRAY_SIZE(golden_settings_gc_9_0)); 901 soc15_program_register_sequence(adev, 902 golden_settings_gc_9_0_vg10, 903 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 904 break; 905 case IP_VERSION(9, 2, 1): 906 soc15_program_register_sequence(adev, 907 golden_settings_gc_9_2_1, 908 ARRAY_SIZE(golden_settings_gc_9_2_1)); 909 soc15_program_register_sequence(adev, 910 golden_settings_gc_9_2_1_vg12, 911 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 912 break; 913 case IP_VERSION(9, 4, 0): 914 soc15_program_register_sequence(adev, 915 golden_settings_gc_9_0, 916 ARRAY_SIZE(golden_settings_gc_9_0)); 917 soc15_program_register_sequence(adev, 918 golden_settings_gc_9_0_vg20, 919 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 920 break; 921 case IP_VERSION(9, 4, 1): 922 soc15_program_register_sequence(adev, 923 golden_settings_gc_9_4_1_arct, 924 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 925 break; 926 case IP_VERSION(9, 2, 2): 927 case IP_VERSION(9, 1, 0): 928 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 929 ARRAY_SIZE(golden_settings_gc_9_1)); 930 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 931 soc15_program_register_sequence(adev, 932 golden_settings_gc_9_1_rv2, 933 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 934 else 935 soc15_program_register_sequence(adev, 936 golden_settings_gc_9_1_rv1, 937 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 938 break; 939 case IP_VERSION(9, 3, 0): 940 soc15_program_register_sequence(adev, 941 golden_settings_gc_9_1_rn, 942 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 943 return; /* for renoir, don't need common goldensetting */ 944 case IP_VERSION(9, 4, 2): 945 gfx_v9_4_2_init_golden_registers(adev, 946 adev->smuio.funcs->get_die_id(adev)); 947 break; 948 default: 949 break; 950 } 951 952 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 953 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) 954 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 955 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 956 } 957 958 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 959 bool wc, uint32_t reg, uint32_t val) 960 { 961 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 962 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 963 WRITE_DATA_DST_SEL(0) | 964 (wc ? WR_CONFIRM : 0)); 965 amdgpu_ring_write(ring, reg); 966 amdgpu_ring_write(ring, 0); 967 amdgpu_ring_write(ring, val); 968 } 969 970 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 971 int mem_space, int opt, uint32_t addr0, 972 uint32_t addr1, uint32_t ref, uint32_t mask, 973 uint32_t inv) 974 { 975 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 976 amdgpu_ring_write(ring, 977 /* memory (1) or register (0) */ 978 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 979 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 980 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 981 WAIT_REG_MEM_ENGINE(eng_sel))); 982 983 if (mem_space) 984 BUG_ON(addr0 & 0x3); /* Dword align */ 985 amdgpu_ring_write(ring, addr0); 986 amdgpu_ring_write(ring, addr1); 987 amdgpu_ring_write(ring, ref); 988 amdgpu_ring_write(ring, mask); 989 amdgpu_ring_write(ring, inv); /* poll interval */ 990 } 991 992 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 993 { 994 struct amdgpu_device *adev = ring->adev; 995 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 996 uint32_t tmp = 0; 997 unsigned i; 998 int r; 999 1000 WREG32(scratch, 0xCAFEDEAD); 1001 r = amdgpu_ring_alloc(ring, 3); 1002 if (r) 1003 return r; 1004 1005 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1006 amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START); 1007 amdgpu_ring_write(ring, 0xDEADBEEF); 1008 amdgpu_ring_commit(ring); 1009 1010 for (i = 0; i < adev->usec_timeout; i++) { 1011 tmp = RREG32(scratch); 1012 if (tmp == 0xDEADBEEF) 1013 break; 1014 udelay(1); 1015 } 1016 1017 if (i >= adev->usec_timeout) 1018 r = -ETIMEDOUT; 1019 return r; 1020 } 1021 1022 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1023 { 1024 struct amdgpu_device *adev = ring->adev; 1025 struct amdgpu_ib ib; 1026 struct dma_fence *f = NULL; 1027 1028 unsigned index; 1029 uint64_t gpu_addr; 1030 uint32_t tmp; 1031 long r; 1032 1033 r = amdgpu_device_wb_get(adev, &index); 1034 if (r) 1035 return r; 1036 1037 gpu_addr = adev->wb.gpu_addr + (index * 4); 1038 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1039 memset(&ib, 0, sizeof(ib)); 1040 r = amdgpu_ib_get(adev, NULL, 16, 1041 AMDGPU_IB_POOL_DIRECT, &ib); 1042 if (r) 1043 goto err1; 1044 1045 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1046 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1047 ib.ptr[2] = lower_32_bits(gpu_addr); 1048 ib.ptr[3] = upper_32_bits(gpu_addr); 1049 ib.ptr[4] = 0xDEADBEEF; 1050 ib.length_dw = 5; 1051 1052 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1053 if (r) 1054 goto err2; 1055 1056 r = dma_fence_wait_timeout(f, false, timeout); 1057 if (r == 0) { 1058 r = -ETIMEDOUT; 1059 goto err2; 1060 } else if (r < 0) { 1061 goto err2; 1062 } 1063 1064 tmp = adev->wb.wb[index]; 1065 if (tmp == 0xDEADBEEF) 1066 r = 0; 1067 else 1068 r = -EINVAL; 1069 1070 err2: 1071 amdgpu_ib_free(adev, &ib, NULL); 1072 dma_fence_put(f); 1073 err1: 1074 amdgpu_device_wb_free(adev, index); 1075 return r; 1076 } 1077 1078 1079 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1080 { 1081 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1082 amdgpu_ucode_release(&adev->gfx.me_fw); 1083 amdgpu_ucode_release(&adev->gfx.ce_fw); 1084 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1085 amdgpu_ucode_release(&adev->gfx.mec_fw); 1086 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1087 1088 kfree(adev->gfx.rlc.register_list_format); 1089 } 1090 1091 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1092 { 1093 adev->gfx.me_fw_write_wait = false; 1094 adev->gfx.mec_fw_write_wait = false; 1095 1096 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && 1097 ((adev->gfx.mec_fw_version < 0x000001a5) || 1098 (adev->gfx.mec_feature_version < 46) || 1099 (adev->gfx.pfp_fw_version < 0x000000b7) || 1100 (adev->gfx.pfp_feature_version < 46))) 1101 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1102 1103 switch (adev->ip_versions[GC_HWIP][0]) { 1104 case IP_VERSION(9, 0, 1): 1105 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1106 (adev->gfx.me_feature_version >= 42) && 1107 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1108 (adev->gfx.pfp_feature_version >= 42)) 1109 adev->gfx.me_fw_write_wait = true; 1110 1111 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1112 (adev->gfx.mec_feature_version >= 42)) 1113 adev->gfx.mec_fw_write_wait = true; 1114 break; 1115 case IP_VERSION(9, 2, 1): 1116 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1117 (adev->gfx.me_feature_version >= 44) && 1118 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1119 (adev->gfx.pfp_feature_version >= 44)) 1120 adev->gfx.me_fw_write_wait = true; 1121 1122 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1123 (adev->gfx.mec_feature_version >= 44)) 1124 adev->gfx.mec_fw_write_wait = true; 1125 break; 1126 case IP_VERSION(9, 4, 0): 1127 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1128 (adev->gfx.me_feature_version >= 44) && 1129 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1130 (adev->gfx.pfp_feature_version >= 44)) 1131 adev->gfx.me_fw_write_wait = true; 1132 1133 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1134 (adev->gfx.mec_feature_version >= 44)) 1135 adev->gfx.mec_fw_write_wait = true; 1136 break; 1137 case IP_VERSION(9, 1, 0): 1138 case IP_VERSION(9, 2, 2): 1139 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1140 (adev->gfx.me_feature_version >= 42) && 1141 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1142 (adev->gfx.pfp_feature_version >= 42)) 1143 adev->gfx.me_fw_write_wait = true; 1144 1145 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1146 (adev->gfx.mec_feature_version >= 42)) 1147 adev->gfx.mec_fw_write_wait = true; 1148 break; 1149 default: 1150 adev->gfx.me_fw_write_wait = true; 1151 adev->gfx.mec_fw_write_wait = true; 1152 break; 1153 } 1154 } 1155 1156 struct amdgpu_gfxoff_quirk { 1157 u16 chip_vendor; 1158 u16 chip_device; 1159 u16 subsys_vendor; 1160 u16 subsys_device; 1161 u8 revision; 1162 }; 1163 1164 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1165 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1166 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1167 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1168 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1169 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1170 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1171 /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ 1172 { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, 1173 { 0, 0, 0, 0, 0 }, 1174 }; 1175 1176 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1177 { 1178 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1179 1180 while (p && p->chip_device != 0) { 1181 if (pdev->vendor == p->chip_vendor && 1182 pdev->device == p->chip_device && 1183 pdev->subsystem_vendor == p->subsys_vendor && 1184 pdev->subsystem_device == p->subsys_device && 1185 pdev->revision == p->revision) { 1186 return true; 1187 } 1188 ++p; 1189 } 1190 return false; 1191 } 1192 1193 static bool is_raven_kicker(struct amdgpu_device *adev) 1194 { 1195 if (adev->pm.fw_version >= 0x41e2b) 1196 return true; 1197 else 1198 return false; 1199 } 1200 1201 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev) 1202 { 1203 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && 1204 (adev->gfx.me_fw_version >= 0x000000a5) && 1205 (adev->gfx.me_feature_version >= 52)) 1206 return true; 1207 else 1208 return false; 1209 } 1210 1211 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1212 { 1213 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1214 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1215 1216 switch (adev->ip_versions[GC_HWIP][0]) { 1217 case IP_VERSION(9, 0, 1): 1218 case IP_VERSION(9, 2, 1): 1219 case IP_VERSION(9, 4, 0): 1220 break; 1221 case IP_VERSION(9, 2, 2): 1222 case IP_VERSION(9, 1, 0): 1223 if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) || 1224 (adev->apu_flags & AMD_APU_IS_PICASSO)) && 1225 ((!is_raven_kicker(adev) && 1226 adev->gfx.rlc_fw_version < 531) || 1227 (adev->gfx.rlc_feature_version < 1) || 1228 !adev->gfx.rlc.is_rlc_v2_1)) 1229 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1230 1231 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1232 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1233 AMD_PG_SUPPORT_CP | 1234 AMD_PG_SUPPORT_RLC_SMU_HS; 1235 break; 1236 case IP_VERSION(9, 3, 0): 1237 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1238 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1239 AMD_PG_SUPPORT_CP | 1240 AMD_PG_SUPPORT_RLC_SMU_HS; 1241 break; 1242 default: 1243 break; 1244 } 1245 } 1246 1247 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1248 char *chip_name) 1249 { 1250 char fw_name[30]; 1251 int err; 1252 1253 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1254 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 1255 if (err) 1256 goto out; 1257 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 1258 1259 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1260 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 1261 if (err) 1262 goto out; 1263 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 1264 1265 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1266 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 1267 if (err) 1268 goto out; 1269 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 1270 1271 out: 1272 if (err) { 1273 amdgpu_ucode_release(&adev->gfx.pfp_fw); 1274 amdgpu_ucode_release(&adev->gfx.me_fw); 1275 amdgpu_ucode_release(&adev->gfx.ce_fw); 1276 } 1277 return err; 1278 } 1279 1280 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1281 char *chip_name) 1282 { 1283 char fw_name[30]; 1284 int err; 1285 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1286 uint16_t version_major; 1287 uint16_t version_minor; 1288 uint32_t smu_version; 1289 1290 /* 1291 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1292 * instead of picasso_rlc.bin. 1293 * Judgment method: 1294 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1295 * or revision >= 0xD8 && revision <= 0xDF 1296 * otherwise is PCO FP5 1297 */ 1298 if (!strcmp(chip_name, "picasso") && 1299 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1300 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1301 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1302 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1303 (smu_version >= 0x41e2b)) 1304 /** 1305 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1306 */ 1307 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1308 else 1309 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1310 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 1311 if (err) 1312 goto out; 1313 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1314 1315 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1316 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1317 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 1318 out: 1319 if (err) 1320 amdgpu_ucode_release(&adev->gfx.rlc_fw); 1321 1322 return err; 1323 } 1324 1325 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) 1326 { 1327 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || 1328 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1329 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) 1330 return false; 1331 1332 return true; 1333 } 1334 1335 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1336 char *chip_name) 1337 { 1338 char fw_name[30]; 1339 int err; 1340 1341 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1342 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); 1343 else 1344 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1345 1346 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 1347 if (err) 1348 return err; 1349 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 1350 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 1351 1352 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { 1353 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN)) 1354 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); 1355 else 1356 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1357 1358 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 1359 if (!err) { 1360 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 1361 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 1362 } else { 1363 err = 0; 1364 adev->gfx.mec2_fw = NULL; 1365 } 1366 } else { 1367 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 1368 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 1369 } 1370 1371 gfx_v9_0_check_if_need_gfxoff(adev); 1372 gfx_v9_0_check_fw_write_wait(adev); 1373 if (err) { 1374 amdgpu_ucode_release(&adev->gfx.mec_fw); 1375 amdgpu_ucode_release(&adev->gfx.mec2_fw); 1376 } 1377 return err; 1378 } 1379 1380 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1381 { 1382 char ucode_prefix[30]; 1383 int r; 1384 1385 DRM_DEBUG("\n"); 1386 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 1387 1388 /* No CPG in Arcturus */ 1389 if (adev->gfx.num_gfx_rings) { 1390 r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix); 1391 if (r) 1392 return r; 1393 } 1394 1395 r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix); 1396 if (r) 1397 return r; 1398 1399 r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix); 1400 if (r) 1401 return r; 1402 1403 return r; 1404 } 1405 1406 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1407 { 1408 u32 count = 0; 1409 const struct cs_section_def *sect = NULL; 1410 const struct cs_extent_def *ext = NULL; 1411 1412 /* begin clear state */ 1413 count += 2; 1414 /* context control state */ 1415 count += 3; 1416 1417 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1418 for (ext = sect->section; ext->extent != NULL; ++ext) { 1419 if (sect->id == SECT_CONTEXT) 1420 count += 2 + ext->reg_count; 1421 else 1422 return 0; 1423 } 1424 } 1425 1426 /* end clear state */ 1427 count += 2; 1428 /* clear state */ 1429 count += 2; 1430 1431 return count; 1432 } 1433 1434 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1435 volatile u32 *buffer) 1436 { 1437 u32 count = 0, i; 1438 const struct cs_section_def *sect = NULL; 1439 const struct cs_extent_def *ext = NULL; 1440 1441 if (adev->gfx.rlc.cs_data == NULL) 1442 return; 1443 if (buffer == NULL) 1444 return; 1445 1446 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1447 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1448 1449 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1450 buffer[count++] = cpu_to_le32(0x80000000); 1451 buffer[count++] = cpu_to_le32(0x80000000); 1452 1453 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1454 for (ext = sect->section; ext->extent != NULL; ++ext) { 1455 if (sect->id == SECT_CONTEXT) { 1456 buffer[count++] = 1457 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1458 buffer[count++] = cpu_to_le32(ext->reg_index - 1459 PACKET3_SET_CONTEXT_REG_START); 1460 for (i = 0; i < ext->reg_count; i++) 1461 buffer[count++] = cpu_to_le32(ext->extent[i]); 1462 } else { 1463 return; 1464 } 1465 } 1466 } 1467 1468 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1469 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1470 1471 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1472 buffer[count++] = cpu_to_le32(0); 1473 } 1474 1475 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1476 { 1477 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1478 uint32_t pg_always_on_cu_num = 2; 1479 uint32_t always_on_cu_num; 1480 uint32_t i, j, k; 1481 uint32_t mask, cu_bitmap, counter; 1482 1483 if (adev->flags & AMD_IS_APU) 1484 always_on_cu_num = 4; 1485 else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)) 1486 always_on_cu_num = 8; 1487 else 1488 always_on_cu_num = 12; 1489 1490 mutex_lock(&adev->grbm_idx_mutex); 1491 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1492 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1493 mask = 1; 1494 cu_bitmap = 0; 1495 counter = 0; 1496 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 1497 1498 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1499 if (cu_info->bitmap[i][j] & mask) { 1500 if (counter == pg_always_on_cu_num) 1501 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1502 if (counter < always_on_cu_num) 1503 cu_bitmap |= mask; 1504 else 1505 break; 1506 counter++; 1507 } 1508 mask <<= 1; 1509 } 1510 1511 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1512 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1513 } 1514 } 1515 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1516 mutex_unlock(&adev->grbm_idx_mutex); 1517 } 1518 1519 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1520 { 1521 uint32_t data; 1522 1523 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1524 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1525 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1526 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1527 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1528 1529 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1530 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1531 1532 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1533 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1534 1535 mutex_lock(&adev->grbm_idx_mutex); 1536 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1537 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1538 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1539 1540 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1541 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1542 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1543 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1544 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1545 1546 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1547 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1548 data &= 0x0000FFFF; 1549 data |= 0x00C00000; 1550 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1551 1552 /* 1553 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1554 * programmed in gfx_v9_0_init_always_on_cu_mask() 1555 */ 1556 1557 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1558 * but used for RLC_LB_CNTL configuration */ 1559 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1560 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1561 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1562 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1563 mutex_unlock(&adev->grbm_idx_mutex); 1564 1565 gfx_v9_0_init_always_on_cu_mask(adev); 1566 } 1567 1568 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1569 { 1570 uint32_t data; 1571 1572 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1573 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1574 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1575 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1576 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1577 1578 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1579 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1580 1581 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1582 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1583 1584 mutex_lock(&adev->grbm_idx_mutex); 1585 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1586 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1587 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1588 1589 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1590 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1591 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1592 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1593 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1594 1595 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1596 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1597 data &= 0x0000FFFF; 1598 data |= 0x00C00000; 1599 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1600 1601 /* 1602 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1603 * programmed in gfx_v9_0_init_always_on_cu_mask() 1604 */ 1605 1606 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1607 * but used for RLC_LB_CNTL configuration */ 1608 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1609 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1610 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1611 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1612 mutex_unlock(&adev->grbm_idx_mutex); 1613 1614 gfx_v9_0_init_always_on_cu_mask(adev); 1615 } 1616 1617 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1618 { 1619 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1620 } 1621 1622 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1623 { 1624 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) 1625 return 5; 1626 else 1627 return 4; 1628 } 1629 1630 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1631 { 1632 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1633 1634 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 1635 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1636 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 1637 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 1638 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 1639 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 1640 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 1641 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 1642 adev->gfx.rlc.rlcg_reg_access_supported = true; 1643 } 1644 1645 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1646 { 1647 const struct cs_section_def *cs_data; 1648 int r; 1649 1650 adev->gfx.rlc.cs_data = gfx9_cs_data; 1651 1652 cs_data = adev->gfx.rlc.cs_data; 1653 1654 if (cs_data) { 1655 /* init clear state block */ 1656 r = amdgpu_gfx_rlc_init_csb(adev); 1657 if (r) 1658 return r; 1659 } 1660 1661 if (adev->flags & AMD_IS_APU) { 1662 /* TODO: double check the cp_table_size for RV */ 1663 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1664 r = amdgpu_gfx_rlc_init_cpt(adev); 1665 if (r) 1666 return r; 1667 } 1668 1669 switch (adev->ip_versions[GC_HWIP][0]) { 1670 case IP_VERSION(9, 2, 2): 1671 case IP_VERSION(9, 1, 0): 1672 gfx_v9_0_init_lbpw(adev); 1673 break; 1674 case IP_VERSION(9, 4, 0): 1675 gfx_v9_4_init_lbpw(adev); 1676 break; 1677 default: 1678 break; 1679 } 1680 1681 /* init spm vmid with 0xf */ 1682 if (adev->gfx.rlc.funcs->update_spm_vmid) 1683 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1684 1685 return 0; 1686 } 1687 1688 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1689 { 1690 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1691 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1692 } 1693 1694 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1695 { 1696 int r; 1697 u32 *hpd; 1698 const __le32 *fw_data; 1699 unsigned fw_size; 1700 u32 *fw; 1701 size_t mec_hpd_size; 1702 1703 const struct gfx_firmware_header_v1_0 *mec_hdr; 1704 1705 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1706 1707 /* take ownership of the relevant compute queues */ 1708 amdgpu_gfx_compute_queue_acquire(adev); 1709 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1710 if (mec_hpd_size) { 1711 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1712 AMDGPU_GEM_DOMAIN_VRAM | 1713 AMDGPU_GEM_DOMAIN_GTT, 1714 &adev->gfx.mec.hpd_eop_obj, 1715 &adev->gfx.mec.hpd_eop_gpu_addr, 1716 (void **)&hpd); 1717 if (r) { 1718 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1719 gfx_v9_0_mec_fini(adev); 1720 return r; 1721 } 1722 1723 memset(hpd, 0, mec_hpd_size); 1724 1725 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1726 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1727 } 1728 1729 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1730 1731 fw_data = (const __le32 *) 1732 (adev->gfx.mec_fw->data + 1733 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1734 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1735 1736 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1737 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1738 &adev->gfx.mec.mec_fw_obj, 1739 &adev->gfx.mec.mec_fw_gpu_addr, 1740 (void **)&fw); 1741 if (r) { 1742 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1743 gfx_v9_0_mec_fini(adev); 1744 return r; 1745 } 1746 1747 memcpy(fw, fw_data, fw_size); 1748 1749 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1750 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1751 1752 return 0; 1753 } 1754 1755 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1756 { 1757 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1758 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1759 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1760 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1761 (SQ_IND_INDEX__FORCE_READ_MASK)); 1762 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1763 } 1764 1765 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1766 uint32_t wave, uint32_t thread, 1767 uint32_t regno, uint32_t num, uint32_t *out) 1768 { 1769 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 1770 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1771 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1772 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1773 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1774 (SQ_IND_INDEX__FORCE_READ_MASK) | 1775 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1776 while (num--) 1777 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1778 } 1779 1780 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1781 { 1782 /* type 1 wave data */ 1783 dst[(*no_fields)++] = 1; 1784 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1785 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1786 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1787 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1788 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1789 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1790 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1791 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1792 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1793 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1794 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1795 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1796 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1797 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1798 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 1799 } 1800 1801 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1802 uint32_t wave, uint32_t start, 1803 uint32_t size, uint32_t *dst) 1804 { 1805 wave_read_regs( 1806 adev, simd, wave, 0, 1807 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1808 } 1809 1810 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1811 uint32_t wave, uint32_t thread, 1812 uint32_t start, uint32_t size, 1813 uint32_t *dst) 1814 { 1815 wave_read_regs( 1816 adev, simd, wave, thread, 1817 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1818 } 1819 1820 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1821 u32 me, u32 pipe, u32 q, u32 vm) 1822 { 1823 soc15_grbm_select(adev, me, pipe, q, vm); 1824 } 1825 1826 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1827 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1828 .select_se_sh = &gfx_v9_0_select_se_sh, 1829 .read_wave_data = &gfx_v9_0_read_wave_data, 1830 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1831 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1832 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 1833 }; 1834 1835 const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { 1836 .ras_error_inject = &gfx_v9_0_ras_error_inject, 1837 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 1838 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 1839 }; 1840 1841 static struct amdgpu_gfx_ras gfx_v9_0_ras = { 1842 .ras_block = { 1843 .hw_ops = &gfx_v9_0_ras_ops, 1844 }, 1845 }; 1846 1847 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1848 { 1849 u32 gb_addr_config; 1850 int err; 1851 1852 switch (adev->ip_versions[GC_HWIP][0]) { 1853 case IP_VERSION(9, 0, 1): 1854 adev->gfx.config.max_hw_contexts = 8; 1855 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1856 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1857 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1858 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1859 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1860 break; 1861 case IP_VERSION(9, 2, 1): 1862 adev->gfx.config.max_hw_contexts = 8; 1863 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1864 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1865 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1866 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1867 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1868 DRM_INFO("fix gfx.config for vega12\n"); 1869 break; 1870 case IP_VERSION(9, 4, 0): 1871 adev->gfx.ras = &gfx_v9_0_ras; 1872 adev->gfx.config.max_hw_contexts = 8; 1873 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1874 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1875 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1876 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1877 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1878 gb_addr_config &= ~0xf3e777ff; 1879 gb_addr_config |= 0x22014042; 1880 /* check vbios table if gpu info is not available */ 1881 err = amdgpu_atomfirmware_get_gfx_info(adev); 1882 if (err) 1883 return err; 1884 break; 1885 case IP_VERSION(9, 2, 2): 1886 case IP_VERSION(9, 1, 0): 1887 adev->gfx.config.max_hw_contexts = 8; 1888 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1889 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1890 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1891 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1892 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1893 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1894 else 1895 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1896 break; 1897 case IP_VERSION(9, 4, 1): 1898 adev->gfx.ras = &gfx_v9_4_ras; 1899 adev->gfx.config.max_hw_contexts = 8; 1900 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1901 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1902 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1903 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1904 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1905 gb_addr_config &= ~0xf3e777ff; 1906 gb_addr_config |= 0x22014042; 1907 break; 1908 case IP_VERSION(9, 3, 0): 1909 adev->gfx.config.max_hw_contexts = 8; 1910 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1911 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1912 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 1913 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1914 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1915 gb_addr_config &= ~0xf3e777ff; 1916 gb_addr_config |= 0x22010042; 1917 break; 1918 case IP_VERSION(9, 4, 2): 1919 adev->gfx.ras = &gfx_v9_4_2_ras; 1920 adev->gfx.config.max_hw_contexts = 8; 1921 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1922 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1923 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1924 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1925 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1926 gb_addr_config &= ~0xf3e777ff; 1927 gb_addr_config |= 0x22014042; 1928 /* check vbios table if gpu info is not available */ 1929 err = amdgpu_atomfirmware_get_gfx_info(adev); 1930 if (err) 1931 return err; 1932 break; 1933 default: 1934 BUG(); 1935 break; 1936 } 1937 1938 if (adev->gfx.ras) { 1939 err = amdgpu_ras_register_ras_block(adev, &adev->gfx.ras->ras_block); 1940 if (err) { 1941 DRM_ERROR("Failed to register gfx ras block!\n"); 1942 return err; 1943 } 1944 1945 strcpy(adev->gfx.ras->ras_block.ras_comm.name, "gfx"); 1946 adev->gfx.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; 1947 adev->gfx.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1948 adev->gfx.ras_if = &adev->gfx.ras->ras_block.ras_comm; 1949 1950 /* If not define special ras_late_init function, use gfx default ras_late_init */ 1951 if (!adev->gfx.ras->ras_block.ras_late_init) 1952 adev->gfx.ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; 1953 1954 /* If not defined special ras_cb function, use default ras_cb */ 1955 if (!adev->gfx.ras->ras_block.ras_cb) 1956 adev->gfx.ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; 1957 } 1958 1959 adev->gfx.config.gb_addr_config = gb_addr_config; 1960 1961 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1962 REG_GET_FIELD( 1963 adev->gfx.config.gb_addr_config, 1964 GB_ADDR_CONFIG, 1965 NUM_PIPES); 1966 1967 adev->gfx.config.max_tile_pipes = 1968 adev->gfx.config.gb_addr_config_fields.num_pipes; 1969 1970 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1971 REG_GET_FIELD( 1972 adev->gfx.config.gb_addr_config, 1973 GB_ADDR_CONFIG, 1974 NUM_BANKS); 1975 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1976 REG_GET_FIELD( 1977 adev->gfx.config.gb_addr_config, 1978 GB_ADDR_CONFIG, 1979 MAX_COMPRESSED_FRAGS); 1980 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1981 REG_GET_FIELD( 1982 adev->gfx.config.gb_addr_config, 1983 GB_ADDR_CONFIG, 1984 NUM_RB_PER_SE); 1985 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1986 REG_GET_FIELD( 1987 adev->gfx.config.gb_addr_config, 1988 GB_ADDR_CONFIG, 1989 NUM_SHADER_ENGINES); 1990 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1991 REG_GET_FIELD( 1992 adev->gfx.config.gb_addr_config, 1993 GB_ADDR_CONFIG, 1994 PIPE_INTERLEAVE_SIZE)); 1995 1996 return 0; 1997 } 1998 1999 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2000 int mec, int pipe, int queue) 2001 { 2002 unsigned irq_type; 2003 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2004 unsigned int hw_prio; 2005 2006 ring = &adev->gfx.compute_ring[ring_id]; 2007 2008 /* mec0 is me1 */ 2009 ring->me = mec + 1; 2010 ring->pipe = pipe; 2011 ring->queue = queue; 2012 2013 ring->ring_obj = NULL; 2014 ring->use_doorbell = true; 2015 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2016 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2017 + (ring_id * GFX9_MEC_HPD_SIZE); 2018 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2019 2020 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2021 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2022 + ring->pipe; 2023 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2024 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 2025 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2026 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2027 hw_prio, NULL); 2028 } 2029 2030 static int gfx_v9_0_sw_init(void *handle) 2031 { 2032 int i, j, k, r, ring_id; 2033 struct amdgpu_ring *ring; 2034 struct amdgpu_kiq *kiq; 2035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2036 unsigned int hw_prio; 2037 2038 switch (adev->ip_versions[GC_HWIP][0]) { 2039 case IP_VERSION(9, 0, 1): 2040 case IP_VERSION(9, 2, 1): 2041 case IP_VERSION(9, 4, 0): 2042 case IP_VERSION(9, 2, 2): 2043 case IP_VERSION(9, 1, 0): 2044 case IP_VERSION(9, 4, 1): 2045 case IP_VERSION(9, 3, 0): 2046 case IP_VERSION(9, 4, 2): 2047 adev->gfx.mec.num_mec = 2; 2048 break; 2049 default: 2050 adev->gfx.mec.num_mec = 1; 2051 break; 2052 } 2053 2054 adev->gfx.mec.num_pipe_per_mec = 4; 2055 adev->gfx.mec.num_queue_per_pipe = 8; 2056 2057 /* EOP Event */ 2058 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2059 if (r) 2060 return r; 2061 2062 /* Privileged reg */ 2063 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2064 &adev->gfx.priv_reg_irq); 2065 if (r) 2066 return r; 2067 2068 /* Privileged inst */ 2069 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2070 &adev->gfx.priv_inst_irq); 2071 if (r) 2072 return r; 2073 2074 /* ECC error */ 2075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2076 &adev->gfx.cp_ecc_error_irq); 2077 if (r) 2078 return r; 2079 2080 /* FUE error */ 2081 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2082 &adev->gfx.cp_ecc_error_irq); 2083 if (r) 2084 return r; 2085 2086 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2087 2088 if (adev->gfx.rlc.funcs) { 2089 if (adev->gfx.rlc.funcs->init) { 2090 r = adev->gfx.rlc.funcs->init(adev); 2091 if (r) { 2092 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 2093 return r; 2094 } 2095 } 2096 } 2097 2098 r = gfx_v9_0_mec_init(adev); 2099 if (r) { 2100 DRM_ERROR("Failed to init MEC BOs!\n"); 2101 return r; 2102 } 2103 2104 /* set up the gfx ring */ 2105 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2106 ring = &adev->gfx.gfx_ring[i]; 2107 ring->ring_obj = NULL; 2108 if (!i) 2109 sprintf(ring->name, "gfx"); 2110 else 2111 sprintf(ring->name, "gfx_%d", i); 2112 ring->use_doorbell = true; 2113 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2114 2115 /* disable scheduler on the real ring */ 2116 ring->no_scheduler = true; 2117 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2118 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2119 AMDGPU_RING_PRIO_DEFAULT, NULL); 2120 if (r) 2121 return r; 2122 } 2123 2124 /* set up the software rings */ 2125 if (adev->gfx.num_gfx_rings) { 2126 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2127 ring = &adev->gfx.sw_gfx_ring[i]; 2128 ring->ring_obj = NULL; 2129 sprintf(ring->name, amdgpu_sw_ring_name(i)); 2130 ring->use_doorbell = true; 2131 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2132 ring->is_sw_ring = true; 2133 hw_prio = amdgpu_sw_ring_priority(i); 2134 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2135 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio, 2136 NULL); 2137 if (r) 2138 return r; 2139 ring->wptr = 0; 2140 } 2141 2142 /* init the muxer and add software rings */ 2143 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0], 2144 GFX9_NUM_SW_GFX_RINGS); 2145 if (r) { 2146 DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r); 2147 return r; 2148 } 2149 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { 2150 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer, 2151 &adev->gfx.sw_gfx_ring[i]); 2152 if (r) { 2153 DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r); 2154 return r; 2155 } 2156 } 2157 } 2158 2159 /* set up the compute queues - allocate horizontally across pipes */ 2160 ring_id = 0; 2161 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2162 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2163 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2164 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2165 continue; 2166 2167 r = gfx_v9_0_compute_ring_init(adev, 2168 ring_id, 2169 i, k, j); 2170 if (r) 2171 return r; 2172 2173 ring_id++; 2174 } 2175 } 2176 } 2177 2178 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2179 if (r) { 2180 DRM_ERROR("Failed to init KIQ BOs!\n"); 2181 return r; 2182 } 2183 2184 kiq = &adev->gfx.kiq; 2185 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2186 if (r) 2187 return r; 2188 2189 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2190 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2191 if (r) 2192 return r; 2193 2194 adev->gfx.ce_ram_size = 0x8000; 2195 2196 r = gfx_v9_0_gpu_early_init(adev); 2197 if (r) 2198 return r; 2199 2200 return 0; 2201 } 2202 2203 2204 static int gfx_v9_0_sw_fini(void *handle) 2205 { 2206 int i; 2207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2208 2209 if (adev->gfx.num_gfx_rings) { 2210 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 2211 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]); 2212 amdgpu_ring_mux_fini(&adev->gfx.muxer); 2213 } 2214 2215 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2216 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2217 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2218 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2219 2220 amdgpu_gfx_mqd_sw_fini(adev); 2221 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2222 amdgpu_gfx_kiq_fini(adev); 2223 2224 gfx_v9_0_mec_fini(adev); 2225 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 2226 &adev->gfx.rlc.clear_state_gpu_addr, 2227 (void **)&adev->gfx.rlc.cs_ptr); 2228 if (adev->flags & AMD_IS_APU) { 2229 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2230 &adev->gfx.rlc.cp_table_gpu_addr, 2231 (void **)&adev->gfx.rlc.cp_table_ptr); 2232 } 2233 gfx_v9_0_free_microcode(adev); 2234 2235 return 0; 2236 } 2237 2238 2239 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2240 { 2241 /* TODO */ 2242 } 2243 2244 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2245 u32 instance) 2246 { 2247 u32 data; 2248 2249 if (instance == 0xffffffff) 2250 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2251 else 2252 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2253 2254 if (se_num == 0xffffffff) 2255 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2256 else 2257 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2258 2259 if (sh_num == 0xffffffff) 2260 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2261 else 2262 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2263 2264 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2265 } 2266 2267 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2268 { 2269 u32 data, mask; 2270 2271 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2272 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2273 2274 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2275 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2276 2277 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2278 adev->gfx.config.max_sh_per_se); 2279 2280 return (~data) & mask; 2281 } 2282 2283 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2284 { 2285 int i, j; 2286 u32 data; 2287 u32 active_rbs = 0; 2288 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2289 adev->gfx.config.max_sh_per_se; 2290 2291 mutex_lock(&adev->grbm_idx_mutex); 2292 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2293 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2294 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2295 data = gfx_v9_0_get_rb_active_bitmap(adev); 2296 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2297 rb_bitmap_width_per_sh); 2298 } 2299 } 2300 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2301 mutex_unlock(&adev->grbm_idx_mutex); 2302 2303 adev->gfx.config.backend_enable_mask = active_rbs; 2304 adev->gfx.config.num_rbs = hweight32(active_rbs); 2305 } 2306 2307 #define DEFAULT_SH_MEM_BASES (0x6000) 2308 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2309 { 2310 int i; 2311 uint32_t sh_mem_config; 2312 uint32_t sh_mem_bases; 2313 2314 /* 2315 * Configure apertures: 2316 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2317 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2318 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2319 */ 2320 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2321 2322 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2323 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2324 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2325 2326 mutex_lock(&adev->srbm_mutex); 2327 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2328 soc15_grbm_select(adev, 0, 0, 0, i); 2329 /* CP and shaders */ 2330 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2331 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2332 } 2333 soc15_grbm_select(adev, 0, 0, 0, 0); 2334 mutex_unlock(&adev->srbm_mutex); 2335 2336 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2337 access. These should be enabled by FW for target VMIDs. */ 2338 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 2339 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2340 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2341 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2342 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2343 } 2344 } 2345 2346 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2347 { 2348 int vmid; 2349 2350 /* 2351 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2352 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2353 * the driver can enable them for graphics. VMID0 should maintain 2354 * access so that HWS firmware can save/restore entries. 2355 */ 2356 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 2357 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2358 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2359 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2360 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2361 } 2362 } 2363 2364 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2365 { 2366 uint32_t tmp; 2367 2368 switch (adev->ip_versions[GC_HWIP][0]) { 2369 case IP_VERSION(9, 4, 1): 2370 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2371 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2372 DISABLE_BARRIER_WAITCNT, 1); 2373 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2374 break; 2375 default: 2376 break; 2377 } 2378 } 2379 2380 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2381 { 2382 u32 tmp; 2383 int i; 2384 2385 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2386 2387 gfx_v9_0_tiling_mode_table_init(adev); 2388 2389 if (adev->gfx.num_gfx_rings) 2390 gfx_v9_0_setup_rb(adev); 2391 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2392 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2393 2394 /* XXX SH_MEM regs */ 2395 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2396 mutex_lock(&adev->srbm_mutex); 2397 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2398 soc15_grbm_select(adev, 0, 0, 0, i); 2399 /* CP and shaders */ 2400 if (i == 0) { 2401 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2402 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2403 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2404 !!adev->gmc.noretry); 2405 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2406 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2407 } else { 2408 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2409 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2410 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2411 !!adev->gmc.noretry); 2412 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2413 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2414 (adev->gmc.private_aperture_start >> 48)); 2415 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2416 (adev->gmc.shared_aperture_start >> 48)); 2417 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2418 } 2419 } 2420 soc15_grbm_select(adev, 0, 0, 0, 0); 2421 2422 mutex_unlock(&adev->srbm_mutex); 2423 2424 gfx_v9_0_init_compute_vmid(adev); 2425 gfx_v9_0_init_gds_vmid(adev); 2426 gfx_v9_0_init_sq_config(adev); 2427 } 2428 2429 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2430 { 2431 u32 i, j, k; 2432 u32 mask; 2433 2434 mutex_lock(&adev->grbm_idx_mutex); 2435 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2436 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2437 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2438 for (k = 0; k < adev->usec_timeout; k++) { 2439 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2440 break; 2441 udelay(1); 2442 } 2443 if (k == adev->usec_timeout) { 2444 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2445 0xffffffff, 0xffffffff); 2446 mutex_unlock(&adev->grbm_idx_mutex); 2447 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2448 i, j); 2449 return; 2450 } 2451 } 2452 } 2453 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2454 mutex_unlock(&adev->grbm_idx_mutex); 2455 2456 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2457 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2458 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2459 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2460 for (k = 0; k < adev->usec_timeout; k++) { 2461 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2462 break; 2463 udelay(1); 2464 } 2465 } 2466 2467 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2468 bool enable) 2469 { 2470 u32 tmp; 2471 2472 /* These interrupts should be enabled to drive DS clock */ 2473 2474 tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2475 2476 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2477 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2478 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2479 if(adev->gfx.num_gfx_rings) 2480 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2481 2482 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2483 } 2484 2485 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2486 { 2487 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2488 /* csib */ 2489 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2490 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2491 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2492 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2493 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2494 adev->gfx.rlc.clear_state_size); 2495 } 2496 2497 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2498 int indirect_offset, 2499 int list_size, 2500 int *unique_indirect_regs, 2501 int unique_indirect_reg_count, 2502 int *indirect_start_offsets, 2503 int *indirect_start_offsets_count, 2504 int max_start_offsets_count) 2505 { 2506 int idx; 2507 2508 for (; indirect_offset < list_size; indirect_offset++) { 2509 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2510 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2511 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2512 2513 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2514 indirect_offset += 2; 2515 2516 /* look for the matching indice */ 2517 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2518 if (unique_indirect_regs[idx] == 2519 register_list_format[indirect_offset] || 2520 !unique_indirect_regs[idx]) 2521 break; 2522 } 2523 2524 BUG_ON(idx >= unique_indirect_reg_count); 2525 2526 if (!unique_indirect_regs[idx]) 2527 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2528 2529 indirect_offset++; 2530 } 2531 } 2532 } 2533 2534 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2535 { 2536 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2537 int unique_indirect_reg_count = 0; 2538 2539 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2540 int indirect_start_offsets_count = 0; 2541 2542 int list_size = 0; 2543 int i = 0, j = 0; 2544 u32 tmp = 0; 2545 2546 u32 *register_list_format = 2547 kmemdup(adev->gfx.rlc.register_list_format, 2548 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2549 if (!register_list_format) 2550 return -ENOMEM; 2551 2552 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2553 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2554 gfx_v9_1_parse_ind_reg_list(register_list_format, 2555 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2556 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2557 unique_indirect_regs, 2558 unique_indirect_reg_count, 2559 indirect_start_offsets, 2560 &indirect_start_offsets_count, 2561 ARRAY_SIZE(indirect_start_offsets)); 2562 2563 /* enable auto inc in case it is disabled */ 2564 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2565 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2566 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2567 2568 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2569 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2570 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2571 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2572 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2573 adev->gfx.rlc.register_restore[i]); 2574 2575 /* load indirect register */ 2576 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2577 adev->gfx.rlc.reg_list_format_start); 2578 2579 /* direct register portion */ 2580 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2581 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2582 register_list_format[i]); 2583 2584 /* indirect register portion */ 2585 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2586 if (register_list_format[i] == 0xFFFFFFFF) { 2587 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2588 continue; 2589 } 2590 2591 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2592 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2593 2594 for (j = 0; j < unique_indirect_reg_count; j++) { 2595 if (register_list_format[i] == unique_indirect_regs[j]) { 2596 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2597 break; 2598 } 2599 } 2600 2601 BUG_ON(j >= unique_indirect_reg_count); 2602 2603 i++; 2604 } 2605 2606 /* set save/restore list size */ 2607 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2608 list_size = list_size >> 1; 2609 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2610 adev->gfx.rlc.reg_restore_list_size); 2611 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2612 2613 /* write the starting offsets to RLC scratch ram */ 2614 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2615 adev->gfx.rlc.starting_offsets_start); 2616 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2617 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2618 indirect_start_offsets[i]); 2619 2620 /* load unique indirect regs*/ 2621 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2622 if (unique_indirect_regs[i] != 0) { 2623 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2624 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2625 unique_indirect_regs[i] & 0x3FFFF); 2626 2627 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2628 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2629 unique_indirect_regs[i] >> 20); 2630 } 2631 } 2632 2633 kfree(register_list_format); 2634 return 0; 2635 } 2636 2637 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2638 { 2639 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2640 } 2641 2642 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2643 bool enable) 2644 { 2645 uint32_t data = 0; 2646 uint32_t default_data = 0; 2647 2648 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2649 if (enable) { 2650 /* enable GFXIP control over CGPG */ 2651 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2652 if(default_data != data) 2653 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2654 2655 /* update status */ 2656 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2657 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2658 if(default_data != data) 2659 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2660 } else { 2661 /* restore GFXIP control over GCPG */ 2662 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2663 if(default_data != data) 2664 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2665 } 2666 } 2667 2668 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2669 { 2670 uint32_t data = 0; 2671 2672 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2673 AMD_PG_SUPPORT_GFX_SMG | 2674 AMD_PG_SUPPORT_GFX_DMG)) { 2675 /* init IDLE_POLL_COUNT = 60 */ 2676 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2677 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2678 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2679 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2680 2681 /* init RLC PG Delay */ 2682 data = 0; 2683 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2684 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2685 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2686 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2687 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2688 2689 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2690 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2691 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2692 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2693 2694 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2695 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2696 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2697 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2698 2699 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2700 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2701 2702 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2703 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2704 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2705 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) 2706 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2707 } 2708 } 2709 2710 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2711 bool enable) 2712 { 2713 uint32_t data = 0; 2714 uint32_t default_data = 0; 2715 2716 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2717 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2718 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2719 enable ? 1 : 0); 2720 if (default_data != data) 2721 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2722 } 2723 2724 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2725 bool enable) 2726 { 2727 uint32_t data = 0; 2728 uint32_t default_data = 0; 2729 2730 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2731 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2732 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2733 enable ? 1 : 0); 2734 if(default_data != data) 2735 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2736 } 2737 2738 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2739 bool enable) 2740 { 2741 uint32_t data = 0; 2742 uint32_t default_data = 0; 2743 2744 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2745 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2746 CP_PG_DISABLE, 2747 enable ? 0 : 1); 2748 if(default_data != data) 2749 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2750 } 2751 2752 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2753 bool enable) 2754 { 2755 uint32_t data, default_data; 2756 2757 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2758 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2759 GFX_POWER_GATING_ENABLE, 2760 enable ? 1 : 0); 2761 if(default_data != data) 2762 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2763 } 2764 2765 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2766 bool enable) 2767 { 2768 uint32_t data, default_data; 2769 2770 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2771 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2772 GFX_PIPELINE_PG_ENABLE, 2773 enable ? 1 : 0); 2774 if(default_data != data) 2775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2776 2777 if (!enable) 2778 /* read any GFX register to wake up GFX */ 2779 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2780 } 2781 2782 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2783 bool enable) 2784 { 2785 uint32_t data, default_data; 2786 2787 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2788 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2789 STATIC_PER_CU_PG_ENABLE, 2790 enable ? 1 : 0); 2791 if(default_data != data) 2792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2793 } 2794 2795 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2796 bool enable) 2797 { 2798 uint32_t data, default_data; 2799 2800 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2801 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2802 DYN_PER_CU_PG_ENABLE, 2803 enable ? 1 : 0); 2804 if(default_data != data) 2805 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2806 } 2807 2808 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2809 { 2810 gfx_v9_0_init_csb(adev); 2811 2812 /* 2813 * Rlc save restore list is workable since v2_1. 2814 * And it's needed by gfxoff feature. 2815 */ 2816 if (adev->gfx.rlc.is_rlc_v2_1) { 2817 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) || 2818 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 2819 gfx_v9_1_init_rlc_save_restore_list(adev); 2820 gfx_v9_0_enable_save_restore_machine(adev); 2821 } 2822 2823 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2824 AMD_PG_SUPPORT_GFX_SMG | 2825 AMD_PG_SUPPORT_GFX_DMG | 2826 AMD_PG_SUPPORT_CP | 2827 AMD_PG_SUPPORT_GDS | 2828 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2829 WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, 2830 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2831 gfx_v9_0_init_gfx_power_gating(adev); 2832 } 2833 } 2834 2835 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2836 { 2837 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2838 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2839 gfx_v9_0_wait_for_rlc_serdes(adev); 2840 } 2841 2842 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2843 { 2844 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2845 udelay(50); 2846 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2847 udelay(50); 2848 } 2849 2850 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2851 { 2852 #ifdef AMDGPU_RLC_DEBUG_RETRY 2853 u32 rlc_ucode_ver; 2854 #endif 2855 2856 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2857 udelay(50); 2858 2859 /* carrizo do enable cp interrupt after cp inited */ 2860 if (!(adev->flags & AMD_IS_APU)) { 2861 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2862 udelay(50); 2863 } 2864 2865 #ifdef AMDGPU_RLC_DEBUG_RETRY 2866 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2867 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2868 if(rlc_ucode_ver == 0x108) { 2869 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2870 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2871 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2872 * default is 0x9C4 to create a 100us interval */ 2873 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2874 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2875 * to disable the page fault retry interrupts, default is 2876 * 0x100 (256) */ 2877 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2878 } 2879 #endif 2880 } 2881 2882 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2883 { 2884 const struct rlc_firmware_header_v2_0 *hdr; 2885 const __le32 *fw_data; 2886 unsigned i, fw_size; 2887 2888 if (!adev->gfx.rlc_fw) 2889 return -EINVAL; 2890 2891 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2892 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2893 2894 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2895 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2896 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2897 2898 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2899 RLCG_UCODE_LOADING_START_ADDRESS); 2900 for (i = 0; i < fw_size; i++) 2901 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2902 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2903 2904 return 0; 2905 } 2906 2907 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2908 { 2909 int r; 2910 2911 if (amdgpu_sriov_vf(adev)) { 2912 gfx_v9_0_init_csb(adev); 2913 return 0; 2914 } 2915 2916 adev->gfx.rlc.funcs->stop(adev); 2917 2918 /* disable CG */ 2919 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2920 2921 gfx_v9_0_init_pg(adev); 2922 2923 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2924 /* legacy rlc firmware loading */ 2925 r = gfx_v9_0_rlc_load_microcode(adev); 2926 if (r) 2927 return r; 2928 } 2929 2930 switch (adev->ip_versions[GC_HWIP][0]) { 2931 case IP_VERSION(9, 2, 2): 2932 case IP_VERSION(9, 1, 0): 2933 if (amdgpu_lbpw == 0) 2934 gfx_v9_0_enable_lbpw(adev, false); 2935 else 2936 gfx_v9_0_enable_lbpw(adev, true); 2937 break; 2938 case IP_VERSION(9, 4, 0): 2939 if (amdgpu_lbpw > 0) 2940 gfx_v9_0_enable_lbpw(adev, true); 2941 else 2942 gfx_v9_0_enable_lbpw(adev, false); 2943 break; 2944 default: 2945 break; 2946 } 2947 2948 adev->gfx.rlc.funcs->start(adev); 2949 2950 return 0; 2951 } 2952 2953 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2954 { 2955 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2956 2957 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2958 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2959 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2960 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2961 udelay(50); 2962 } 2963 2964 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2965 { 2966 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2967 const struct gfx_firmware_header_v1_0 *ce_hdr; 2968 const struct gfx_firmware_header_v1_0 *me_hdr; 2969 const __le32 *fw_data; 2970 unsigned i, fw_size; 2971 2972 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2973 return -EINVAL; 2974 2975 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2976 adev->gfx.pfp_fw->data; 2977 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2978 adev->gfx.ce_fw->data; 2979 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2980 adev->gfx.me_fw->data; 2981 2982 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2983 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2984 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2985 2986 gfx_v9_0_cp_gfx_enable(adev, false); 2987 2988 /* PFP */ 2989 fw_data = (const __le32 *) 2990 (adev->gfx.pfp_fw->data + 2991 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2992 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2993 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2994 for (i = 0; i < fw_size; i++) 2995 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2996 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2997 2998 /* CE */ 2999 fw_data = (const __le32 *) 3000 (adev->gfx.ce_fw->data + 3001 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3002 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3003 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3004 for (i = 0; i < fw_size; i++) 3005 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3006 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3007 3008 /* ME */ 3009 fw_data = (const __le32 *) 3010 (adev->gfx.me_fw->data + 3011 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3012 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3013 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3014 for (i = 0; i < fw_size; i++) 3015 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3016 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3017 3018 return 0; 3019 } 3020 3021 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3022 { 3023 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3024 const struct cs_section_def *sect = NULL; 3025 const struct cs_extent_def *ext = NULL; 3026 int r, i, tmp; 3027 3028 /* init the CP */ 3029 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3030 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3031 3032 gfx_v9_0_cp_gfx_enable(adev, true); 3033 3034 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3035 if (r) { 3036 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3037 return r; 3038 } 3039 3040 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3041 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3042 3043 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3044 amdgpu_ring_write(ring, 0x80000000); 3045 amdgpu_ring_write(ring, 0x80000000); 3046 3047 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3048 for (ext = sect->section; ext->extent != NULL; ++ext) { 3049 if (sect->id == SECT_CONTEXT) { 3050 amdgpu_ring_write(ring, 3051 PACKET3(PACKET3_SET_CONTEXT_REG, 3052 ext->reg_count)); 3053 amdgpu_ring_write(ring, 3054 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3055 for (i = 0; i < ext->reg_count; i++) 3056 amdgpu_ring_write(ring, ext->extent[i]); 3057 } 3058 } 3059 } 3060 3061 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3062 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3063 3064 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3065 amdgpu_ring_write(ring, 0); 3066 3067 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3068 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3069 amdgpu_ring_write(ring, 0x8000); 3070 amdgpu_ring_write(ring, 0x8000); 3071 3072 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3073 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3074 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3075 amdgpu_ring_write(ring, tmp); 3076 amdgpu_ring_write(ring, 0); 3077 3078 amdgpu_ring_commit(ring); 3079 3080 return 0; 3081 } 3082 3083 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3084 { 3085 struct amdgpu_ring *ring; 3086 u32 tmp; 3087 u32 rb_bufsz; 3088 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3089 3090 /* Set the write pointer delay */ 3091 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3092 3093 /* set the RB to use vmid 0 */ 3094 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3095 3096 /* Set ring buffer size */ 3097 ring = &adev->gfx.gfx_ring[0]; 3098 rb_bufsz = order_base_2(ring->ring_size / 8); 3099 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3100 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3101 #ifdef __BIG_ENDIAN 3102 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3103 #endif 3104 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3105 3106 /* Initialize the ring buffer's write pointers */ 3107 ring->wptr = 0; 3108 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3109 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3110 3111 /* set the wb address wether it's enabled or not */ 3112 rptr_addr = ring->rptr_gpu_addr; 3113 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3114 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3115 3116 wptr_gpu_addr = ring->wptr_gpu_addr; 3117 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3118 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3119 3120 mdelay(1); 3121 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3122 3123 rb_addr = ring->gpu_addr >> 8; 3124 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3125 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3126 3127 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3128 if (ring->use_doorbell) { 3129 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3130 DOORBELL_OFFSET, ring->doorbell_index); 3131 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3132 DOORBELL_EN, 1); 3133 } else { 3134 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3135 } 3136 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3137 3138 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3139 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3140 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3141 3142 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3143 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3144 3145 3146 /* start the ring */ 3147 gfx_v9_0_cp_gfx_start(adev); 3148 ring->sched.ready = true; 3149 3150 return 0; 3151 } 3152 3153 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3154 { 3155 if (enable) { 3156 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3157 } else { 3158 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3159 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3160 adev->gfx.kiq.ring.sched.ready = false; 3161 } 3162 udelay(50); 3163 } 3164 3165 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3166 { 3167 const struct gfx_firmware_header_v1_0 *mec_hdr; 3168 const __le32 *fw_data; 3169 unsigned i; 3170 u32 tmp; 3171 3172 if (!adev->gfx.mec_fw) 3173 return -EINVAL; 3174 3175 gfx_v9_0_cp_compute_enable(adev, false); 3176 3177 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3178 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3179 3180 fw_data = (const __le32 *) 3181 (adev->gfx.mec_fw->data + 3182 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3183 tmp = 0; 3184 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3185 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3186 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3187 3188 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3189 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3190 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3191 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3192 3193 /* MEC1 */ 3194 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3195 mec_hdr->jt_offset); 3196 for (i = 0; i < mec_hdr->jt_size; i++) 3197 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3198 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3199 3200 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3201 adev->gfx.mec_fw_version); 3202 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3203 3204 return 0; 3205 } 3206 3207 /* KIQ functions */ 3208 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3209 { 3210 uint32_t tmp; 3211 struct amdgpu_device *adev = ring->adev; 3212 3213 /* tell RLC which is KIQ queue */ 3214 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3215 tmp &= 0xffffff00; 3216 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3217 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3218 tmp |= 0x80; 3219 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3220 } 3221 3222 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3223 { 3224 struct amdgpu_device *adev = ring->adev; 3225 3226 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3227 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 3228 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3229 mqd->cp_hqd_queue_priority = 3230 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3231 } 3232 } 3233 } 3234 3235 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3236 { 3237 struct amdgpu_device *adev = ring->adev; 3238 struct v9_mqd *mqd = ring->mqd_ptr; 3239 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3240 uint32_t tmp; 3241 3242 mqd->header = 0xC0310800; 3243 mqd->compute_pipelinestat_enable = 0x00000001; 3244 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3245 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3246 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3247 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3248 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3249 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3250 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3251 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3252 mqd->compute_misc_reserved = 0x00000003; 3253 3254 mqd->dynamic_cu_mask_addr_lo = 3255 lower_32_bits(ring->mqd_gpu_addr 3256 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3257 mqd->dynamic_cu_mask_addr_hi = 3258 upper_32_bits(ring->mqd_gpu_addr 3259 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3260 3261 eop_base_addr = ring->eop_gpu_addr >> 8; 3262 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3263 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3264 3265 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3266 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3267 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3268 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3269 3270 mqd->cp_hqd_eop_control = tmp; 3271 3272 /* enable doorbell? */ 3273 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3274 3275 if (ring->use_doorbell) { 3276 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3277 DOORBELL_OFFSET, ring->doorbell_index); 3278 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3279 DOORBELL_EN, 1); 3280 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3281 DOORBELL_SOURCE, 0); 3282 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3283 DOORBELL_HIT, 0); 3284 } else { 3285 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3286 DOORBELL_EN, 0); 3287 } 3288 3289 mqd->cp_hqd_pq_doorbell_control = tmp; 3290 3291 /* disable the queue if it's active */ 3292 ring->wptr = 0; 3293 mqd->cp_hqd_dequeue_request = 0; 3294 mqd->cp_hqd_pq_rptr = 0; 3295 mqd->cp_hqd_pq_wptr_lo = 0; 3296 mqd->cp_hqd_pq_wptr_hi = 0; 3297 3298 /* set the pointer to the MQD */ 3299 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3300 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3301 3302 /* set MQD vmid to 0 */ 3303 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3304 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3305 mqd->cp_mqd_control = tmp; 3306 3307 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3308 hqd_gpu_addr = ring->gpu_addr >> 8; 3309 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3310 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3311 3312 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3313 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3314 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3315 (order_base_2(ring->ring_size / 4) - 1)); 3316 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3317 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 3318 #ifdef __BIG_ENDIAN 3319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3320 #endif 3321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3323 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3324 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3325 mqd->cp_hqd_pq_control = tmp; 3326 3327 /* set the wb address whether it's enabled or not */ 3328 wb_gpu_addr = ring->rptr_gpu_addr; 3329 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3330 mqd->cp_hqd_pq_rptr_report_addr_hi = 3331 upper_32_bits(wb_gpu_addr) & 0xffff; 3332 3333 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3334 wb_gpu_addr = ring->wptr_gpu_addr; 3335 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3336 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3337 3338 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3339 ring->wptr = 0; 3340 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3341 3342 /* set the vmid for the queue */ 3343 mqd->cp_hqd_vmid = 0; 3344 3345 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3346 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3347 mqd->cp_hqd_persistent_state = tmp; 3348 3349 /* set MIN_IB_AVAIL_SIZE */ 3350 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3351 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3352 mqd->cp_hqd_ib_control = tmp; 3353 3354 /* set static priority for a queue/ring */ 3355 gfx_v9_0_mqd_set_priority(ring, mqd); 3356 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); 3357 3358 /* map_queues packet doesn't need activate the queue, 3359 * so only kiq need set this field. 3360 */ 3361 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3362 mqd->cp_hqd_active = 1; 3363 3364 return 0; 3365 } 3366 3367 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3368 { 3369 struct amdgpu_device *adev = ring->adev; 3370 struct v9_mqd *mqd = ring->mqd_ptr; 3371 int j; 3372 3373 /* disable wptr polling */ 3374 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3375 3376 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3377 mqd->cp_hqd_eop_base_addr_lo); 3378 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3379 mqd->cp_hqd_eop_base_addr_hi); 3380 3381 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3382 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3383 mqd->cp_hqd_eop_control); 3384 3385 /* enable doorbell? */ 3386 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3387 mqd->cp_hqd_pq_doorbell_control); 3388 3389 /* disable the queue if it's active */ 3390 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3391 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3392 for (j = 0; j < adev->usec_timeout; j++) { 3393 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3394 break; 3395 udelay(1); 3396 } 3397 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3398 mqd->cp_hqd_dequeue_request); 3399 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3400 mqd->cp_hqd_pq_rptr); 3401 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3402 mqd->cp_hqd_pq_wptr_lo); 3403 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3404 mqd->cp_hqd_pq_wptr_hi); 3405 } 3406 3407 /* set the pointer to the MQD */ 3408 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3409 mqd->cp_mqd_base_addr_lo); 3410 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3411 mqd->cp_mqd_base_addr_hi); 3412 3413 /* set MQD vmid to 0 */ 3414 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3415 mqd->cp_mqd_control); 3416 3417 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3418 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3419 mqd->cp_hqd_pq_base_lo); 3420 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3421 mqd->cp_hqd_pq_base_hi); 3422 3423 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3424 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3425 mqd->cp_hqd_pq_control); 3426 3427 /* set the wb address whether it's enabled or not */ 3428 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3429 mqd->cp_hqd_pq_rptr_report_addr_lo); 3430 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3431 mqd->cp_hqd_pq_rptr_report_addr_hi); 3432 3433 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3434 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3435 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3436 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3437 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3438 3439 /* enable the doorbell if requested */ 3440 if (ring->use_doorbell) { 3441 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3442 (adev->doorbell_index.kiq * 2) << 2); 3443 /* If GC has entered CGPG, ringing doorbell > first page 3444 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to 3445 * workaround this issue. And this change has to align with firmware 3446 * update. 3447 */ 3448 if (check_if_enlarge_doorbell_range(adev)) 3449 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3450 (adev->doorbell.size - 4)); 3451 else 3452 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3453 (adev->doorbell_index.userqueue_end * 2) << 2); 3454 } 3455 3456 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3457 mqd->cp_hqd_pq_doorbell_control); 3458 3459 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3460 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3461 mqd->cp_hqd_pq_wptr_lo); 3462 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3463 mqd->cp_hqd_pq_wptr_hi); 3464 3465 /* set the vmid for the queue */ 3466 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3467 3468 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3469 mqd->cp_hqd_persistent_state); 3470 3471 /* activate the queue */ 3472 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3473 mqd->cp_hqd_active); 3474 3475 if (ring->use_doorbell) 3476 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3477 3478 return 0; 3479 } 3480 3481 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3482 { 3483 struct amdgpu_device *adev = ring->adev; 3484 int j; 3485 3486 /* disable the queue if it's active */ 3487 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3488 3489 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3490 3491 for (j = 0; j < adev->usec_timeout; j++) { 3492 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3493 break; 3494 udelay(1); 3495 } 3496 3497 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3498 DRM_DEBUG("KIQ dequeue request failed.\n"); 3499 3500 /* Manual disable if dequeue request times out */ 3501 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3502 } 3503 3504 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3505 0); 3506 } 3507 3508 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3509 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3510 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3511 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3512 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3513 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3514 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3515 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3516 3517 return 0; 3518 } 3519 3520 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3521 { 3522 struct amdgpu_device *adev = ring->adev; 3523 struct v9_mqd *mqd = ring->mqd_ptr; 3524 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3525 struct v9_mqd *tmp_mqd; 3526 3527 gfx_v9_0_kiq_setting(ring); 3528 3529 /* GPU could be in bad state during probe, driver trigger the reset 3530 * after load the SMU, in this case , the mqd is not be initialized. 3531 * driver need to re-init the mqd. 3532 * check mqd->cp_hqd_pq_control since this value should not be 0 3533 */ 3534 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3535 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ 3536 /* for GPU_RESET case , reset MQD to a clean status */ 3537 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3538 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3539 3540 /* reset ring buffer */ 3541 ring->wptr = 0; 3542 amdgpu_ring_clear_ring(ring); 3543 3544 mutex_lock(&adev->srbm_mutex); 3545 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3546 gfx_v9_0_kiq_init_register(ring); 3547 soc15_grbm_select(adev, 0, 0, 0, 0); 3548 mutex_unlock(&adev->srbm_mutex); 3549 } else { 3550 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3551 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3552 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3553 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 3554 amdgpu_ring_clear_ring(ring); 3555 mutex_lock(&adev->srbm_mutex); 3556 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3557 gfx_v9_0_mqd_init(ring); 3558 gfx_v9_0_kiq_init_register(ring); 3559 soc15_grbm_select(adev, 0, 0, 0, 0); 3560 mutex_unlock(&adev->srbm_mutex); 3561 3562 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3563 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3564 } 3565 3566 return 0; 3567 } 3568 3569 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3570 { 3571 struct amdgpu_device *adev = ring->adev; 3572 struct v9_mqd *mqd = ring->mqd_ptr; 3573 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3574 struct v9_mqd *tmp_mqd; 3575 3576 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 3577 * is not be initialized before 3578 */ 3579 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 3580 3581 if (!tmp_mqd->cp_hqd_pq_control || 3582 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 3583 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3584 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3585 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3586 mutex_lock(&adev->srbm_mutex); 3587 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3588 gfx_v9_0_mqd_init(ring); 3589 soc15_grbm_select(adev, 0, 0, 0, 0); 3590 mutex_unlock(&adev->srbm_mutex); 3591 3592 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3593 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3594 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 3595 /* reset MQD to a clean status */ 3596 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3597 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3598 3599 /* reset ring buffer */ 3600 ring->wptr = 0; 3601 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 3602 amdgpu_ring_clear_ring(ring); 3603 } else { 3604 amdgpu_ring_clear_ring(ring); 3605 } 3606 3607 return 0; 3608 } 3609 3610 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3611 { 3612 struct amdgpu_ring *ring; 3613 int r; 3614 3615 ring = &adev->gfx.kiq.ring; 3616 3617 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3618 if (unlikely(r != 0)) 3619 return r; 3620 3621 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3622 if (unlikely(r != 0)) 3623 return r; 3624 3625 gfx_v9_0_kiq_init_queue(ring); 3626 amdgpu_bo_kunmap(ring->mqd_obj); 3627 ring->mqd_ptr = NULL; 3628 amdgpu_bo_unreserve(ring->mqd_obj); 3629 ring->sched.ready = true; 3630 return 0; 3631 } 3632 3633 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3634 { 3635 struct amdgpu_ring *ring = NULL; 3636 int r = 0, i; 3637 3638 gfx_v9_0_cp_compute_enable(adev, true); 3639 3640 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3641 ring = &adev->gfx.compute_ring[i]; 3642 3643 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3644 if (unlikely(r != 0)) 3645 goto done; 3646 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3647 if (!r) { 3648 r = gfx_v9_0_kcq_init_queue(ring); 3649 amdgpu_bo_kunmap(ring->mqd_obj); 3650 ring->mqd_ptr = NULL; 3651 } 3652 amdgpu_bo_unreserve(ring->mqd_obj); 3653 if (r) 3654 goto done; 3655 } 3656 3657 r = amdgpu_gfx_enable_kcq(adev); 3658 done: 3659 return r; 3660 } 3661 3662 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3663 { 3664 int r, i; 3665 struct amdgpu_ring *ring; 3666 3667 if (!(adev->flags & AMD_IS_APU)) 3668 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3669 3670 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3671 if (adev->gfx.num_gfx_rings) { 3672 /* legacy firmware loading */ 3673 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3674 if (r) 3675 return r; 3676 } 3677 3678 r = gfx_v9_0_cp_compute_load_microcode(adev); 3679 if (r) 3680 return r; 3681 } 3682 3683 r = gfx_v9_0_kiq_resume(adev); 3684 if (r) 3685 return r; 3686 3687 if (adev->gfx.num_gfx_rings) { 3688 r = gfx_v9_0_cp_gfx_resume(adev); 3689 if (r) 3690 return r; 3691 } 3692 3693 r = gfx_v9_0_kcq_resume(adev); 3694 if (r) 3695 return r; 3696 3697 if (adev->gfx.num_gfx_rings) { 3698 ring = &adev->gfx.gfx_ring[0]; 3699 r = amdgpu_ring_test_helper(ring); 3700 if (r) 3701 return r; 3702 } 3703 3704 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3705 ring = &adev->gfx.compute_ring[i]; 3706 amdgpu_ring_test_helper(ring); 3707 } 3708 3709 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3710 3711 return 0; 3712 } 3713 3714 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3715 { 3716 u32 tmp; 3717 3718 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) && 3719 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)) 3720 return; 3721 3722 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3723 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3724 adev->df.hash_status.hash_64k); 3725 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3726 adev->df.hash_status.hash_2m); 3727 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3728 adev->df.hash_status.hash_1g); 3729 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3730 } 3731 3732 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3733 { 3734 if (adev->gfx.num_gfx_rings) 3735 gfx_v9_0_cp_gfx_enable(adev, enable); 3736 gfx_v9_0_cp_compute_enable(adev, enable); 3737 } 3738 3739 static int gfx_v9_0_hw_init(void *handle) 3740 { 3741 int r; 3742 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3743 3744 if (!amdgpu_sriov_vf(adev)) 3745 gfx_v9_0_init_golden_registers(adev); 3746 3747 gfx_v9_0_constants_init(adev); 3748 3749 gfx_v9_0_init_tcp_config(adev); 3750 3751 r = adev->gfx.rlc.funcs->resume(adev); 3752 if (r) 3753 return r; 3754 3755 r = gfx_v9_0_cp_resume(adev); 3756 if (r) 3757 return r; 3758 3759 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 3760 gfx_v9_4_2_set_power_brake_sequence(adev); 3761 3762 return r; 3763 } 3764 3765 static int gfx_v9_0_hw_fini(void *handle) 3766 { 3767 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3768 3769 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3770 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3771 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3772 3773 /* DF freeze and kcq disable will fail */ 3774 if (!amdgpu_ras_intr_triggered()) 3775 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3776 amdgpu_gfx_disable_kcq(adev); 3777 3778 if (amdgpu_sriov_vf(adev)) { 3779 gfx_v9_0_cp_gfx_enable(adev, false); 3780 /* must disable polling for SRIOV when hw finished, otherwise 3781 * CPC engine may still keep fetching WB address which is already 3782 * invalid after sw finished and trigger DMAR reading error in 3783 * hypervisor side. 3784 */ 3785 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3786 return 0; 3787 } 3788 3789 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3790 * otherwise KIQ is hanging when binding back 3791 */ 3792 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 3793 mutex_lock(&adev->srbm_mutex); 3794 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3795 adev->gfx.kiq.ring.pipe, 3796 adev->gfx.kiq.ring.queue, 0); 3797 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3798 soc15_grbm_select(adev, 0, 0, 0, 0); 3799 mutex_unlock(&adev->srbm_mutex); 3800 } 3801 3802 gfx_v9_0_cp_enable(adev, false); 3803 3804 /* Skip stopping RLC with A+A reset or when RLC controls GFX clock */ 3805 if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) || 3806 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) { 3807 dev_dbg(adev->dev, "Skipping RLC halt\n"); 3808 return 0; 3809 } 3810 3811 adev->gfx.rlc.funcs->stop(adev); 3812 return 0; 3813 } 3814 3815 static int gfx_v9_0_suspend(void *handle) 3816 { 3817 return gfx_v9_0_hw_fini(handle); 3818 } 3819 3820 static int gfx_v9_0_resume(void *handle) 3821 { 3822 return gfx_v9_0_hw_init(handle); 3823 } 3824 3825 static bool gfx_v9_0_is_idle(void *handle) 3826 { 3827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3828 3829 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3830 GRBM_STATUS, GUI_ACTIVE)) 3831 return false; 3832 else 3833 return true; 3834 } 3835 3836 static int gfx_v9_0_wait_for_idle(void *handle) 3837 { 3838 unsigned i; 3839 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3840 3841 for (i = 0; i < adev->usec_timeout; i++) { 3842 if (gfx_v9_0_is_idle(handle)) 3843 return 0; 3844 udelay(1); 3845 } 3846 return -ETIMEDOUT; 3847 } 3848 3849 static int gfx_v9_0_soft_reset(void *handle) 3850 { 3851 u32 grbm_soft_reset = 0; 3852 u32 tmp; 3853 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3854 3855 /* GRBM_STATUS */ 3856 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3857 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3858 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3859 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3860 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3861 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3862 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3863 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3864 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3865 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3866 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3867 } 3868 3869 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3870 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3871 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3872 } 3873 3874 /* GRBM_STATUS2 */ 3875 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3876 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3877 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3878 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3879 3880 3881 if (grbm_soft_reset) { 3882 /* stop the rlc */ 3883 adev->gfx.rlc.funcs->stop(adev); 3884 3885 if (adev->gfx.num_gfx_rings) 3886 /* Disable GFX parsing/prefetching */ 3887 gfx_v9_0_cp_gfx_enable(adev, false); 3888 3889 /* Disable MEC parsing/prefetching */ 3890 gfx_v9_0_cp_compute_enable(adev, false); 3891 3892 if (grbm_soft_reset) { 3893 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3894 tmp |= grbm_soft_reset; 3895 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3896 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3897 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3898 3899 udelay(50); 3900 3901 tmp &= ~grbm_soft_reset; 3902 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3903 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3904 } 3905 3906 /* Wait a little for things to settle down */ 3907 udelay(50); 3908 } 3909 return 0; 3910 } 3911 3912 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 3913 { 3914 signed long r, cnt = 0; 3915 unsigned long flags; 3916 uint32_t seq, reg_val_offs = 0; 3917 uint64_t value = 0; 3918 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3919 struct amdgpu_ring *ring = &kiq->ring; 3920 3921 BUG_ON(!ring->funcs->emit_rreg); 3922 3923 spin_lock_irqsave(&kiq->ring_lock, flags); 3924 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 3925 pr_err("critical bug! too many kiq readers\n"); 3926 goto failed_unlock; 3927 } 3928 amdgpu_ring_alloc(ring, 32); 3929 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3930 amdgpu_ring_write(ring, 9 | /* src: register*/ 3931 (5 << 8) | /* dst: memory */ 3932 (1 << 16) | /* count sel */ 3933 (1 << 20)); /* write confirm */ 3934 amdgpu_ring_write(ring, 0); 3935 amdgpu_ring_write(ring, 0); 3936 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3937 reg_val_offs * 4)); 3938 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3939 reg_val_offs * 4)); 3940 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 3941 if (r) 3942 goto failed_undo; 3943 3944 amdgpu_ring_commit(ring); 3945 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3946 3947 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3948 3949 /* don't wait anymore for gpu reset case because this way may 3950 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 3951 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 3952 * never return if we keep waiting in virt_kiq_rreg, which cause 3953 * gpu_recover() hang there. 3954 * 3955 * also don't wait anymore for IRQ context 3956 * */ 3957 if (r < 1 && (amdgpu_in_reset(adev))) 3958 goto failed_kiq_read; 3959 3960 might_sleep(); 3961 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 3962 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 3963 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 3964 } 3965 3966 if (cnt > MAX_KIQ_REG_TRY) 3967 goto failed_kiq_read; 3968 3969 mb(); 3970 value = (uint64_t)adev->wb.wb[reg_val_offs] | 3971 (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; 3972 amdgpu_device_wb_free(adev, reg_val_offs); 3973 return value; 3974 3975 failed_undo: 3976 amdgpu_ring_undo(ring); 3977 failed_unlock: 3978 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3979 failed_kiq_read: 3980 if (reg_val_offs) 3981 amdgpu_device_wb_free(adev, reg_val_offs); 3982 pr_err("failed to read gpu clock\n"); 3983 return ~0; 3984 } 3985 3986 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3987 { 3988 uint64_t clock, clock_lo, clock_hi, hi_check; 3989 3990 switch (adev->ip_versions[GC_HWIP][0]) { 3991 case IP_VERSION(9, 3, 0): 3992 preempt_disable(); 3993 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3994 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 3995 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir); 3996 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 3997 * roughly every 42 seconds. 3998 */ 3999 if (hi_check != clock_hi) { 4000 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir); 4001 clock_hi = hi_check; 4002 } 4003 preempt_enable(); 4004 clock = clock_lo | (clock_hi << 32ULL); 4005 break; 4006 default: 4007 amdgpu_gfx_off_ctrl(adev, false); 4008 mutex_lock(&adev->gfx.gpu_clock_mutex); 4009 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) { 4010 clock = gfx_v9_0_kiq_read_clock(adev); 4011 } else { 4012 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4013 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4014 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4015 } 4016 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4017 amdgpu_gfx_off_ctrl(adev, true); 4018 break; 4019 } 4020 return clock; 4021 } 4022 4023 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4024 uint32_t vmid, 4025 uint32_t gds_base, uint32_t gds_size, 4026 uint32_t gws_base, uint32_t gws_size, 4027 uint32_t oa_base, uint32_t oa_size) 4028 { 4029 struct amdgpu_device *adev = ring->adev; 4030 4031 /* GDS Base */ 4032 gfx_v9_0_write_data_to_reg(ring, 0, false, 4033 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4034 gds_base); 4035 4036 /* GDS Size */ 4037 gfx_v9_0_write_data_to_reg(ring, 0, false, 4038 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4039 gds_size); 4040 4041 /* GWS */ 4042 gfx_v9_0_write_data_to_reg(ring, 0, false, 4043 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4044 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4045 4046 /* OA */ 4047 gfx_v9_0_write_data_to_reg(ring, 0, false, 4048 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4049 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4050 } 4051 4052 static const u32 vgpr_init_compute_shader[] = 4053 { 4054 0xb07c0000, 0xbe8000ff, 4055 0x000000f8, 0xbf110800, 4056 0x7e000280, 0x7e020280, 4057 0x7e040280, 0x7e060280, 4058 0x7e080280, 0x7e0a0280, 4059 0x7e0c0280, 0x7e0e0280, 4060 0x80808800, 0xbe803200, 4061 0xbf84fff5, 0xbf9c0000, 4062 0xd28c0001, 0x0001007f, 4063 0xd28d0001, 0x0002027e, 4064 0x10020288, 0xb8810904, 4065 0xb7814000, 0xd1196a01, 4066 0x00000301, 0xbe800087, 4067 0xbefc00c1, 0xd89c4000, 4068 0x00020201, 0xd89cc080, 4069 0x00040401, 0x320202ff, 4070 0x00000800, 0x80808100, 4071 0xbf84fff8, 0x7e020280, 4072 0xbf810000, 0x00000000, 4073 }; 4074 4075 static const u32 sgpr_init_compute_shader[] = 4076 { 4077 0xb07c0000, 0xbe8000ff, 4078 0x0000005f, 0xbee50080, 4079 0xbe812c65, 0xbe822c65, 4080 0xbe832c65, 0xbe842c65, 4081 0xbe852c65, 0xb77c0005, 4082 0x80808500, 0xbf84fff8, 4083 0xbe800080, 0xbf810000, 4084 }; 4085 4086 static const u32 vgpr_init_compute_shader_arcturus[] = { 4087 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4088 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4089 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4090 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4091 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4092 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4093 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4094 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4095 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4096 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4097 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4098 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4099 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4100 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4101 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4102 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4103 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4104 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4105 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4106 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4107 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4108 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4109 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4110 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4111 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4112 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4113 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4114 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4115 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4116 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4117 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4118 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4119 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4120 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4121 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4122 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4123 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4124 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4125 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4126 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4127 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4128 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4129 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4130 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4131 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4132 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4133 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4134 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4135 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4136 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4137 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4138 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4139 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4140 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4141 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4142 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4143 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4144 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4145 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4146 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4147 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4148 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4149 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4150 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4151 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4152 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4153 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4154 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4155 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4156 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4157 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4158 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4159 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4160 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4161 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4162 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4163 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4164 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4165 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4166 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4167 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4168 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4169 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4170 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4171 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4172 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4173 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4174 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4175 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4176 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4177 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4178 0xbf84fff8, 0xbf810000, 4179 }; 4180 4181 /* When below register arrays changed, please update gpr_reg_size, 4182 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4183 to cover all gfx9 ASICs */ 4184 static const struct soc15_reg_entry vgpr_init_regs[] = { 4185 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4186 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4187 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4188 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4189 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4190 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4191 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4192 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4193 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4194 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4195 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4196 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4197 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4198 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4199 }; 4200 4201 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4202 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4203 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4204 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4205 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4206 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4207 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4208 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4209 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4210 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4211 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4212 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4213 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4214 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4215 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4216 }; 4217 4218 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4219 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4220 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4221 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4222 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4223 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4224 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4225 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4226 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4227 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4228 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4229 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4230 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4231 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4232 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4233 }; 4234 4235 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4236 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4237 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4238 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4239 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4240 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4241 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4242 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4243 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4244 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4245 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4246 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4247 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4248 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4249 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4250 }; 4251 4252 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4253 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4254 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4255 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4256 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4257 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4258 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4259 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4260 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4261 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4262 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4263 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4264 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4265 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4266 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4267 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4268 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4269 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4270 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4271 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4272 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4273 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4274 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4275 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4276 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4277 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4278 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4279 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4280 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4281 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4282 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4283 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4284 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4285 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4286 }; 4287 4288 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4289 { 4290 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4291 int i, r; 4292 4293 /* only support when RAS is enabled */ 4294 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4295 return 0; 4296 4297 r = amdgpu_ring_alloc(ring, 7); 4298 if (r) { 4299 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4300 ring->name, r); 4301 return r; 4302 } 4303 4304 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4305 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4306 4307 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4308 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4309 PACKET3_DMA_DATA_DST_SEL(1) | 4310 PACKET3_DMA_DATA_SRC_SEL(2) | 4311 PACKET3_DMA_DATA_ENGINE(0))); 4312 amdgpu_ring_write(ring, 0); 4313 amdgpu_ring_write(ring, 0); 4314 amdgpu_ring_write(ring, 0); 4315 amdgpu_ring_write(ring, 0); 4316 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4317 adev->gds.gds_size); 4318 4319 amdgpu_ring_commit(ring); 4320 4321 for (i = 0; i < adev->usec_timeout; i++) { 4322 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4323 break; 4324 udelay(1); 4325 } 4326 4327 if (i >= adev->usec_timeout) 4328 r = -ETIMEDOUT; 4329 4330 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4331 4332 return r; 4333 } 4334 4335 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4336 { 4337 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4338 struct amdgpu_ib ib; 4339 struct dma_fence *f = NULL; 4340 int r, i; 4341 unsigned total_size, vgpr_offset, sgpr_offset; 4342 u64 gpu_addr; 4343 4344 int compute_dim_x = adev->gfx.config.max_shader_engines * 4345 adev->gfx.config.max_cu_per_sh * 4346 adev->gfx.config.max_sh_per_se; 4347 int sgpr_work_group_size = 5; 4348 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4349 int vgpr_init_shader_size; 4350 const u32 *vgpr_init_shader_ptr; 4351 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4352 4353 /* only support when RAS is enabled */ 4354 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4355 return 0; 4356 4357 /* bail if the compute ring is not ready */ 4358 if (!ring->sched.ready) 4359 return 0; 4360 4361 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 4362 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4363 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4364 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4365 } else { 4366 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4367 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4368 vgpr_init_regs_ptr = vgpr_init_regs; 4369 } 4370 4371 total_size = 4372 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4373 total_size += 4374 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4375 total_size += 4376 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4377 total_size = ALIGN(total_size, 256); 4378 vgpr_offset = total_size; 4379 total_size += ALIGN(vgpr_init_shader_size, 256); 4380 sgpr_offset = total_size; 4381 total_size += sizeof(sgpr_init_compute_shader); 4382 4383 /* allocate an indirect buffer to put the commands in */ 4384 memset(&ib, 0, sizeof(ib)); 4385 r = amdgpu_ib_get(adev, NULL, total_size, 4386 AMDGPU_IB_POOL_DIRECT, &ib); 4387 if (r) { 4388 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4389 return r; 4390 } 4391 4392 /* load the compute shaders */ 4393 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4394 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4395 4396 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4397 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4398 4399 /* init the ib length to 0 */ 4400 ib.length_dw = 0; 4401 4402 /* VGPR */ 4403 /* write the register state for the compute dispatch */ 4404 for (i = 0; i < gpr_reg_size; i++) { 4405 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4406 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4407 - PACKET3_SET_SH_REG_START; 4408 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4409 } 4410 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4411 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4412 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4413 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4414 - PACKET3_SET_SH_REG_START; 4415 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4416 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4417 4418 /* write dispatch packet */ 4419 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4420 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4421 ib.ptr[ib.length_dw++] = 1; /* y */ 4422 ib.ptr[ib.length_dw++] = 1; /* z */ 4423 ib.ptr[ib.length_dw++] = 4424 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4425 4426 /* write CS partial flush packet */ 4427 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4428 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4429 4430 /* SGPR1 */ 4431 /* write the register state for the compute dispatch */ 4432 for (i = 0; i < gpr_reg_size; i++) { 4433 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4434 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4435 - PACKET3_SET_SH_REG_START; 4436 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4437 } 4438 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4439 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4440 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4441 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4442 - PACKET3_SET_SH_REG_START; 4443 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4444 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4445 4446 /* write dispatch packet */ 4447 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4448 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4449 ib.ptr[ib.length_dw++] = 1; /* y */ 4450 ib.ptr[ib.length_dw++] = 1; /* z */ 4451 ib.ptr[ib.length_dw++] = 4452 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4453 4454 /* write CS partial flush packet */ 4455 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4456 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4457 4458 /* SGPR2 */ 4459 /* write the register state for the compute dispatch */ 4460 for (i = 0; i < gpr_reg_size; i++) { 4461 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4462 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4463 - PACKET3_SET_SH_REG_START; 4464 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4465 } 4466 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4467 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4468 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4469 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4470 - PACKET3_SET_SH_REG_START; 4471 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4472 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4473 4474 /* write dispatch packet */ 4475 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4476 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4477 ib.ptr[ib.length_dw++] = 1; /* y */ 4478 ib.ptr[ib.length_dw++] = 1; /* z */ 4479 ib.ptr[ib.length_dw++] = 4480 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4481 4482 /* write CS partial flush packet */ 4483 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4484 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4485 4486 /* shedule the ib on the ring */ 4487 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4488 if (r) { 4489 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4490 goto fail; 4491 } 4492 4493 /* wait for the GPU to finish processing the IB */ 4494 r = dma_fence_wait(f, false); 4495 if (r) { 4496 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4497 goto fail; 4498 } 4499 4500 fail: 4501 amdgpu_ib_free(adev, &ib, NULL); 4502 dma_fence_put(f); 4503 4504 return r; 4505 } 4506 4507 static int gfx_v9_0_early_init(void *handle) 4508 { 4509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4510 4511 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 4512 4513 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 4514 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4515 adev->gfx.num_gfx_rings = 0; 4516 else 4517 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4518 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4519 AMDGPU_MAX_COMPUTE_RINGS); 4520 gfx_v9_0_set_kiq_pm4_funcs(adev); 4521 gfx_v9_0_set_ring_funcs(adev); 4522 gfx_v9_0_set_irq_funcs(adev); 4523 gfx_v9_0_set_gds_init(adev); 4524 gfx_v9_0_set_rlc_funcs(adev); 4525 4526 /* init rlcg reg access ctrl */ 4527 gfx_v9_0_init_rlcg_reg_access_ctrl(adev); 4528 4529 return gfx_v9_0_init_microcode(adev); 4530 } 4531 4532 static int gfx_v9_0_ecc_late_init(void *handle) 4533 { 4534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4535 int r; 4536 4537 /* 4538 * Temp workaround to fix the issue that CP firmware fails to 4539 * update read pointer when CPDMA is writing clearing operation 4540 * to GDS in suspend/resume sequence on several cards. So just 4541 * limit this operation in cold boot sequence. 4542 */ 4543 if ((!adev->in_suspend) && 4544 (adev->gds.gds_size)) { 4545 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4546 if (r) 4547 return r; 4548 } 4549 4550 /* requires IBs so do in late init after IB pool is initialized */ 4551 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 4552 r = gfx_v9_4_2_do_edc_gpr_workarounds(adev); 4553 else 4554 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4555 4556 if (r) 4557 return r; 4558 4559 if (adev->gfx.ras && 4560 adev->gfx.ras->enable_watchdog_timer) 4561 adev->gfx.ras->enable_watchdog_timer(adev); 4562 4563 return 0; 4564 } 4565 4566 static int gfx_v9_0_late_init(void *handle) 4567 { 4568 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4569 int r; 4570 4571 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4572 if (r) 4573 return r; 4574 4575 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4576 if (r) 4577 return r; 4578 4579 r = gfx_v9_0_ecc_late_init(handle); 4580 if (r) 4581 return r; 4582 4583 return 0; 4584 } 4585 4586 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4587 { 4588 uint32_t rlc_setting; 4589 4590 /* if RLC is not enabled, do nothing */ 4591 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4592 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4593 return false; 4594 4595 return true; 4596 } 4597 4598 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4599 { 4600 uint32_t data; 4601 unsigned i; 4602 4603 data = RLC_SAFE_MODE__CMD_MASK; 4604 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4605 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4606 4607 /* wait for RLC_SAFE_MODE */ 4608 for (i = 0; i < adev->usec_timeout; i++) { 4609 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4610 break; 4611 udelay(1); 4612 } 4613 } 4614 4615 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4616 { 4617 uint32_t data; 4618 4619 data = RLC_SAFE_MODE__CMD_MASK; 4620 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4621 } 4622 4623 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4624 bool enable) 4625 { 4626 amdgpu_gfx_rlc_enter_safe_mode(adev); 4627 4628 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4629 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4630 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4631 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4632 } else { 4633 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4634 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4635 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4636 } 4637 4638 amdgpu_gfx_rlc_exit_safe_mode(adev); 4639 } 4640 4641 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4642 bool enable) 4643 { 4644 /* TODO: double check if we need to perform under safe mode */ 4645 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4646 4647 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4648 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4649 else 4650 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4651 4652 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4653 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4654 else 4655 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4656 4657 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4658 } 4659 4660 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4661 bool enable) 4662 { 4663 uint32_t data, def; 4664 4665 amdgpu_gfx_rlc_enter_safe_mode(adev); 4666 4667 /* It is disabled by HW by default */ 4668 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4669 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4670 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4671 4672 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4673 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4674 4675 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4676 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4677 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4678 4679 /* only for Vega10 & Raven1 */ 4680 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4681 4682 if (def != data) 4683 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4684 4685 /* MGLS is a global flag to control all MGLS in GFX */ 4686 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4687 /* 2 - RLC memory Light sleep */ 4688 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4689 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4690 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4691 if (def != data) 4692 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4693 } 4694 /* 3 - CP memory Light sleep */ 4695 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4696 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4697 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4698 if (def != data) 4699 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4700 } 4701 } 4702 } else { 4703 /* 1 - MGCG_OVERRIDE */ 4704 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4705 4706 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1)) 4707 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4708 4709 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4710 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4711 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4712 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4713 4714 if (def != data) 4715 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4716 4717 /* 2 - disable MGLS in RLC */ 4718 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4719 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4720 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4721 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4722 } 4723 4724 /* 3 - disable MGLS in CP */ 4725 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4726 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4727 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4728 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4729 } 4730 } 4731 4732 amdgpu_gfx_rlc_exit_safe_mode(adev); 4733 } 4734 4735 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4736 bool enable) 4737 { 4738 uint32_t data, def; 4739 4740 if (!adev->gfx.num_gfx_rings) 4741 return; 4742 4743 amdgpu_gfx_rlc_enter_safe_mode(adev); 4744 4745 /* Enable 3D CGCG/CGLS */ 4746 if (enable) { 4747 /* write cmd to clear cgcg/cgls ov */ 4748 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4749 /* unset CGCG override */ 4750 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4751 /* update CGCG and CGLS override bits */ 4752 if (def != data) 4753 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4754 4755 /* enable 3Dcgcg FSM(0x0000363f) */ 4756 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4757 4758 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 4759 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4760 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4761 else 4762 data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; 4763 4764 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4765 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4766 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4767 if (def != data) 4768 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4769 4770 /* set IDLE_POLL_COUNT(0x00900100) */ 4771 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4772 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4773 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4774 if (def != data) 4775 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4776 } else { 4777 /* Disable CGCG/CGLS */ 4778 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4779 /* disable cgcg, cgls should be disabled */ 4780 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4781 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4782 /* disable cgcg and cgls in FSM */ 4783 if (def != data) 4784 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4785 } 4786 4787 amdgpu_gfx_rlc_exit_safe_mode(adev); 4788 } 4789 4790 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4791 bool enable) 4792 { 4793 uint32_t def, data; 4794 4795 amdgpu_gfx_rlc_enter_safe_mode(adev); 4796 4797 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4798 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4799 /* unset CGCG override */ 4800 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4801 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4802 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4803 else 4804 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4805 /* update CGCG and CGLS override bits */ 4806 if (def != data) 4807 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4808 4809 /* enable cgcg FSM(0x0000363F) */ 4810 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4811 4812 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) 4813 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4814 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4815 else 4816 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4817 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4818 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4819 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4820 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4821 if (def != data) 4822 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4823 4824 /* set IDLE_POLL_COUNT(0x00900100) */ 4825 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4826 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4827 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4828 if (def != data) 4829 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4830 } else { 4831 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4832 /* reset CGCG/CGLS bits */ 4833 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4834 /* disable cgcg and cgls in FSM */ 4835 if (def != data) 4836 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4837 } 4838 4839 amdgpu_gfx_rlc_exit_safe_mode(adev); 4840 } 4841 4842 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4843 bool enable) 4844 { 4845 if (enable) { 4846 /* CGCG/CGLS should be enabled after MGCG/MGLS 4847 * === MGCG + MGLS === 4848 */ 4849 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4850 /* === CGCG /CGLS for GFX 3D Only === */ 4851 gfx_v9_0_update_3d_clock_gating(adev, enable); 4852 /* === CGCG + CGLS === */ 4853 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4854 } else { 4855 /* CGCG/CGLS should be disabled before MGCG/MGLS 4856 * === CGCG + CGLS === 4857 */ 4858 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4859 /* === CGCG /CGLS for GFX 3D Only === */ 4860 gfx_v9_0_update_3d_clock_gating(adev, enable); 4861 /* === MGCG + MGLS === */ 4862 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4863 } 4864 return 0; 4865 } 4866 4867 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4868 { 4869 u32 reg, data; 4870 4871 amdgpu_gfx_off_ctrl(adev, false); 4872 4873 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 4874 if (amdgpu_sriov_is_pp_one_vf(adev)) 4875 data = RREG32_NO_KIQ(reg); 4876 else 4877 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4878 4879 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4880 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4881 4882 if (amdgpu_sriov_is_pp_one_vf(adev)) 4883 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 4884 else 4885 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4886 4887 amdgpu_gfx_off_ctrl(adev, true); 4888 } 4889 4890 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4891 uint32_t offset, 4892 struct soc15_reg_rlcg *entries, int arr_size) 4893 { 4894 int i; 4895 uint32_t reg; 4896 4897 if (!entries) 4898 return false; 4899 4900 for (i = 0; i < arr_size; i++) { 4901 const struct soc15_reg_rlcg *entry; 4902 4903 entry = &entries[i]; 4904 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4905 if (offset == reg) 4906 return true; 4907 } 4908 4909 return false; 4910 } 4911 4912 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4913 { 4914 return gfx_v9_0_check_rlcg_range(adev, offset, 4915 (void *)rlcg_access_gc_9_0, 4916 ARRAY_SIZE(rlcg_access_gc_9_0)); 4917 } 4918 4919 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 4920 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 4921 .set_safe_mode = gfx_v9_0_set_safe_mode, 4922 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 4923 .init = gfx_v9_0_rlc_init, 4924 .get_csb_size = gfx_v9_0_get_csb_size, 4925 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 4926 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 4927 .resume = gfx_v9_0_rlc_resume, 4928 .stop = gfx_v9_0_rlc_stop, 4929 .reset = gfx_v9_0_rlc_reset, 4930 .start = gfx_v9_0_rlc_start, 4931 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 4932 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 4933 }; 4934 4935 static int gfx_v9_0_set_powergating_state(void *handle, 4936 enum amd_powergating_state state) 4937 { 4938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4939 bool enable = (state == AMD_PG_STATE_GATE); 4940 4941 switch (adev->ip_versions[GC_HWIP][0]) { 4942 case IP_VERSION(9, 2, 2): 4943 case IP_VERSION(9, 1, 0): 4944 case IP_VERSION(9, 3, 0): 4945 if (!enable) 4946 amdgpu_gfx_off_ctrl(adev, false); 4947 4948 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 4949 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 4950 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 4951 } else { 4952 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 4953 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 4954 } 4955 4956 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 4957 gfx_v9_0_enable_cp_power_gating(adev, true); 4958 else 4959 gfx_v9_0_enable_cp_power_gating(adev, false); 4960 4961 /* update gfx cgpg state */ 4962 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 4963 4964 /* update mgcg state */ 4965 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 4966 4967 if (enable) 4968 amdgpu_gfx_off_ctrl(adev, true); 4969 break; 4970 case IP_VERSION(9, 2, 1): 4971 amdgpu_gfx_off_ctrl(adev, enable); 4972 break; 4973 default: 4974 break; 4975 } 4976 4977 return 0; 4978 } 4979 4980 static int gfx_v9_0_set_clockgating_state(void *handle, 4981 enum amd_clockgating_state state) 4982 { 4983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4984 4985 if (amdgpu_sriov_vf(adev)) 4986 return 0; 4987 4988 switch (adev->ip_versions[GC_HWIP][0]) { 4989 case IP_VERSION(9, 0, 1): 4990 case IP_VERSION(9, 2, 1): 4991 case IP_VERSION(9, 4, 0): 4992 case IP_VERSION(9, 2, 2): 4993 case IP_VERSION(9, 1, 0): 4994 case IP_VERSION(9, 4, 1): 4995 case IP_VERSION(9, 3, 0): 4996 case IP_VERSION(9, 4, 2): 4997 gfx_v9_0_update_gfx_clock_gating(adev, 4998 state == AMD_CG_STATE_GATE); 4999 break; 5000 default: 5001 break; 5002 } 5003 return 0; 5004 } 5005 5006 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags) 5007 { 5008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5009 int data; 5010 5011 if (amdgpu_sriov_vf(adev)) 5012 *flags = 0; 5013 5014 /* AMD_CG_SUPPORT_GFX_MGCG */ 5015 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5016 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5017 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5018 5019 /* AMD_CG_SUPPORT_GFX_CGCG */ 5020 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5021 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5022 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5023 5024 /* AMD_CG_SUPPORT_GFX_CGLS */ 5025 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5026 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5027 5028 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5029 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5030 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5031 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5032 5033 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5034 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5035 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5036 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5037 5038 if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) { 5039 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5040 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5041 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5042 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5043 5044 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5045 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5046 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5047 } 5048 } 5049 5050 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5051 { 5052 return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/ 5053 } 5054 5055 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5056 { 5057 struct amdgpu_device *adev = ring->adev; 5058 u64 wptr; 5059 5060 /* XXX check if swapping is necessary on BE */ 5061 if (ring->use_doorbell) { 5062 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5063 } else { 5064 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5065 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5066 } 5067 5068 return wptr; 5069 } 5070 5071 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5072 { 5073 struct amdgpu_device *adev = ring->adev; 5074 5075 if (ring->use_doorbell) { 5076 /* XXX check if swapping is necessary on BE */ 5077 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5078 WDOORBELL64(ring->doorbell_index, ring->wptr); 5079 } else { 5080 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5081 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5082 } 5083 } 5084 5085 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5086 { 5087 struct amdgpu_device *adev = ring->adev; 5088 u32 ref_and_mask, reg_mem_engine; 5089 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5090 5091 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5092 switch (ring->me) { 5093 case 1: 5094 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5095 break; 5096 case 2: 5097 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5098 break; 5099 default: 5100 return; 5101 } 5102 reg_mem_engine = 0; 5103 } else { 5104 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5105 reg_mem_engine = 1; /* pfp */ 5106 } 5107 5108 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5109 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5110 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5111 ref_and_mask, ref_and_mask, 0x20); 5112 } 5113 5114 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5115 struct amdgpu_job *job, 5116 struct amdgpu_ib *ib, 5117 uint32_t flags) 5118 { 5119 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5120 u32 header, control = 0; 5121 5122 if (ib->flags & AMDGPU_IB_FLAG_CE) 5123 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5124 else 5125 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5126 5127 control |= ib->length_dw | (vmid << 24); 5128 5129 if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) { 5130 control |= INDIRECT_BUFFER_PRE_ENB(1); 5131 5132 if (flags & AMDGPU_IB_PREEMPTED) 5133 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5134 5135 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5136 gfx_v9_0_ring_emit_de_meta(ring, 5137 (!amdgpu_sriov_vf(ring->adev) && 5138 flags & AMDGPU_IB_PREEMPTED) ? 5139 true : false); 5140 } 5141 5142 amdgpu_ring_write(ring, header); 5143 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5144 amdgpu_ring_write(ring, 5145 #ifdef __BIG_ENDIAN 5146 (2 << 0) | 5147 #endif 5148 lower_32_bits(ib->gpu_addr)); 5149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5150 amdgpu_ring_write(ring, control); 5151 } 5152 5153 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5154 struct amdgpu_job *job, 5155 struct amdgpu_ib *ib, 5156 uint32_t flags) 5157 { 5158 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5159 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5160 5161 /* Currently, there is a high possibility to get wave ID mismatch 5162 * between ME and GDS, leading to a hw deadlock, because ME generates 5163 * different wave IDs than the GDS expects. This situation happens 5164 * randomly when at least 5 compute pipes use GDS ordered append. 5165 * The wave IDs generated by ME are also wrong after suspend/resume. 5166 * Those are probably bugs somewhere else in the kernel driver. 5167 * 5168 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5169 * GDS to 0 for this ring (me/pipe). 5170 */ 5171 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5172 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5173 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5174 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5175 } 5176 5177 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5178 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5179 amdgpu_ring_write(ring, 5180 #ifdef __BIG_ENDIAN 5181 (2 << 0) | 5182 #endif 5183 lower_32_bits(ib->gpu_addr)); 5184 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5185 amdgpu_ring_write(ring, control); 5186 } 5187 5188 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5189 u64 seq, unsigned flags) 5190 { 5191 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5192 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5193 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5194 bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; 5195 uint32_t dw2 = 0; 5196 5197 /* RELEASE_MEM - flush caches, send int */ 5198 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5199 5200 if (writeback) { 5201 dw2 = EOP_TC_NC_ACTION_EN; 5202 } else { 5203 dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | 5204 EOP_TC_MD_ACTION_EN; 5205 } 5206 dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5207 EVENT_INDEX(5); 5208 if (exec) 5209 dw2 |= EOP_EXEC; 5210 5211 amdgpu_ring_write(ring, dw2); 5212 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5213 5214 /* 5215 * the address should be Qword aligned if 64bit write, Dword 5216 * aligned if only send 32bit data low (discard data high) 5217 */ 5218 if (write64bit) 5219 BUG_ON(addr & 0x7); 5220 else 5221 BUG_ON(addr & 0x3); 5222 amdgpu_ring_write(ring, lower_32_bits(addr)); 5223 amdgpu_ring_write(ring, upper_32_bits(addr)); 5224 amdgpu_ring_write(ring, lower_32_bits(seq)); 5225 amdgpu_ring_write(ring, upper_32_bits(seq)); 5226 amdgpu_ring_write(ring, 0); 5227 } 5228 5229 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5230 { 5231 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5232 uint32_t seq = ring->fence_drv.sync_seq; 5233 uint64_t addr = ring->fence_drv.gpu_addr; 5234 5235 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5236 lower_32_bits(addr), upper_32_bits(addr), 5237 seq, 0xffffffff, 4); 5238 } 5239 5240 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5241 unsigned vmid, uint64_t pd_addr) 5242 { 5243 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5244 5245 /* compute doesn't have PFP */ 5246 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5247 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5248 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5249 amdgpu_ring_write(ring, 0x0); 5250 } 5251 } 5252 5253 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5254 { 5255 return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */ 5256 } 5257 5258 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5259 { 5260 u64 wptr; 5261 5262 /* XXX check if swapping is necessary on BE */ 5263 if (ring->use_doorbell) 5264 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 5265 else 5266 BUG(); 5267 return wptr; 5268 } 5269 5270 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5271 { 5272 struct amdgpu_device *adev = ring->adev; 5273 5274 /* XXX check if swapping is necessary on BE */ 5275 if (ring->use_doorbell) { 5276 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr); 5277 WDOORBELL64(ring->doorbell_index, ring->wptr); 5278 } else{ 5279 BUG(); /* only DOORBELL method supported on gfx9 now */ 5280 } 5281 } 5282 5283 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5284 u64 seq, unsigned int flags) 5285 { 5286 struct amdgpu_device *adev = ring->adev; 5287 5288 /* we only allocate 32bit for each seq wb address */ 5289 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5290 5291 /* write fence seq to the "addr" */ 5292 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5293 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5294 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5295 amdgpu_ring_write(ring, lower_32_bits(addr)); 5296 amdgpu_ring_write(ring, upper_32_bits(addr)); 5297 amdgpu_ring_write(ring, lower_32_bits(seq)); 5298 5299 if (flags & AMDGPU_FENCE_FLAG_INT) { 5300 /* set register to trigger INT */ 5301 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5302 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5303 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5304 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5305 amdgpu_ring_write(ring, 0); 5306 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5307 } 5308 } 5309 5310 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5311 { 5312 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5313 amdgpu_ring_write(ring, 0); 5314 } 5315 5316 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 5317 { 5318 struct amdgpu_device *adev = ring->adev; 5319 struct v9_ce_ib_state ce_payload = {0}; 5320 uint64_t offset, ce_payload_gpu_addr; 5321 void *ce_payload_cpu_addr; 5322 int cnt; 5323 5324 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5325 5326 if (ring->is_mes_queue) { 5327 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5328 gfx[0].gfx_meta_data) + 5329 offsetof(struct v9_gfx_meta_data, ce_payload); 5330 ce_payload_gpu_addr = 5331 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5332 ce_payload_cpu_addr = 5333 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5334 } else { 5335 offset = offsetof(struct v9_gfx_meta_data, ce_payload); 5336 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5337 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5338 } 5339 5340 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5341 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5342 WRITE_DATA_DST_SEL(8) | 5343 WR_CONFIRM) | 5344 WRITE_DATA_CACHE_POLICY(0)); 5345 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 5346 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 5347 5348 if (resume) 5349 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 5350 sizeof(ce_payload) >> 2); 5351 else 5352 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 5353 sizeof(ce_payload) >> 2); 5354 } 5355 5356 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) 5357 { 5358 int i, r = 0; 5359 struct amdgpu_device *adev = ring->adev; 5360 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5361 struct amdgpu_ring *kiq_ring = &kiq->ring; 5362 unsigned long flags; 5363 5364 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 5365 return -EINVAL; 5366 5367 spin_lock_irqsave(&kiq->ring_lock, flags); 5368 5369 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 5370 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5371 return -ENOMEM; 5372 } 5373 5374 /* assert preemption condition */ 5375 amdgpu_ring_set_preempt_cond_exec(ring, false); 5376 5377 ring->trail_seq += 1; 5378 amdgpu_ring_alloc(ring, 13); 5379 gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 5380 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT); 5381 /*reset the CP_VMID_PREEMPT after trailing fence*/ 5382 amdgpu_ring_emit_wreg(ring, 5383 SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT), 5384 0x0); 5385 5386 /* assert IB preemption, emit the trailing fence */ 5387 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 5388 ring->trail_fence_gpu_addr, 5389 ring->trail_seq); 5390 5391 amdgpu_ring_commit(kiq_ring); 5392 spin_unlock_irqrestore(&kiq->ring_lock, flags); 5393 5394 /* poll the trailing fence */ 5395 for (i = 0; i < adev->usec_timeout; i++) { 5396 if (ring->trail_seq == 5397 le32_to_cpu(*ring->trail_fence_cpu_addr)) 5398 break; 5399 udelay(1); 5400 } 5401 5402 if (i >= adev->usec_timeout) { 5403 r = -EINVAL; 5404 DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); 5405 } 5406 5407 amdgpu_ring_commit(ring); 5408 5409 /* deassert preemption condition */ 5410 amdgpu_ring_set_preempt_cond_exec(ring, true); 5411 return r; 5412 } 5413 5414 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 5415 { 5416 struct amdgpu_device *adev = ring->adev; 5417 struct v9_de_ib_state de_payload = {0}; 5418 uint64_t offset, gds_addr, de_payload_gpu_addr; 5419 void *de_payload_cpu_addr; 5420 int cnt; 5421 5422 if (ring->is_mes_queue) { 5423 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5424 gfx[0].gfx_meta_data) + 5425 offsetof(struct v9_gfx_meta_data, de_payload); 5426 de_payload_gpu_addr = 5427 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5428 de_payload_cpu_addr = 5429 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 5430 5431 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 5432 gfx[0].gds_backup) + 5433 offsetof(struct v9_gfx_meta_data, de_payload); 5434 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 5435 } else { 5436 offset = offsetof(struct v9_gfx_meta_data, de_payload); 5437 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 5438 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 5439 5440 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 5441 AMDGPU_CSA_SIZE - adev->gds.gds_size, 5442 PAGE_SIZE); 5443 } 5444 5445 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5446 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5447 5448 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5449 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5450 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5451 WRITE_DATA_DST_SEL(8) | 5452 WR_CONFIRM) | 5453 WRITE_DATA_CACHE_POLICY(0)); 5454 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 5455 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 5456 5457 if (resume) 5458 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 5459 sizeof(de_payload) >> 2); 5460 else 5461 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 5462 sizeof(de_payload) >> 2); 5463 } 5464 5465 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 5466 bool secure) 5467 { 5468 uint32_t v = secure ? FRAME_TMZ : 0; 5469 5470 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5471 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 5472 } 5473 5474 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5475 { 5476 uint32_t dw2 = 0; 5477 5478 gfx_v9_0_ring_emit_ce_meta(ring, 5479 (!amdgpu_sriov_vf(ring->adev) && 5480 flags & AMDGPU_IB_PREEMPTED) ? true : false); 5481 5482 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5483 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5484 /* set load_global_config & load_global_uconfig */ 5485 dw2 |= 0x8001; 5486 /* set load_cs_sh_regs */ 5487 dw2 |= 0x01000000; 5488 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5489 dw2 |= 0x10002; 5490 5491 /* set load_ce_ram if preamble presented */ 5492 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5493 dw2 |= 0x10000000; 5494 } else { 5495 /* still load_ce_ram if this is the first time preamble presented 5496 * although there is no context switch happens. 5497 */ 5498 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5499 dw2 |= 0x10000000; 5500 } 5501 5502 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5503 amdgpu_ring_write(ring, dw2); 5504 amdgpu_ring_write(ring, 0); 5505 } 5506 5507 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5508 { 5509 unsigned ret; 5510 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5511 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5512 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5513 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5514 ret = ring->wptr & ring->buf_mask; 5515 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5516 return ret; 5517 } 5518 5519 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5520 { 5521 unsigned cur; 5522 BUG_ON(offset > ring->buf_mask); 5523 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5524 5525 cur = (ring->wptr - 1) & ring->buf_mask; 5526 if (likely(cur > offset)) 5527 ring->ring[offset] = cur - offset; 5528 else 5529 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5530 } 5531 5532 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 5533 uint32_t reg_val_offs) 5534 { 5535 struct amdgpu_device *adev = ring->adev; 5536 5537 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5538 amdgpu_ring_write(ring, 0 | /* src: register*/ 5539 (5 << 8) | /* dst: memory */ 5540 (1 << 20)); /* write confirm */ 5541 amdgpu_ring_write(ring, reg); 5542 amdgpu_ring_write(ring, 0); 5543 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5544 reg_val_offs * 4)); 5545 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5546 reg_val_offs * 4)); 5547 } 5548 5549 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5550 uint32_t val) 5551 { 5552 uint32_t cmd = 0; 5553 5554 switch (ring->funcs->type) { 5555 case AMDGPU_RING_TYPE_GFX: 5556 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5557 break; 5558 case AMDGPU_RING_TYPE_KIQ: 5559 cmd = (1 << 16); /* no inc addr */ 5560 break; 5561 default: 5562 cmd = WR_CONFIRM; 5563 break; 5564 } 5565 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5566 amdgpu_ring_write(ring, cmd); 5567 amdgpu_ring_write(ring, reg); 5568 amdgpu_ring_write(ring, 0); 5569 amdgpu_ring_write(ring, val); 5570 } 5571 5572 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5573 uint32_t val, uint32_t mask) 5574 { 5575 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5576 } 5577 5578 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5579 uint32_t reg0, uint32_t reg1, 5580 uint32_t ref, uint32_t mask) 5581 { 5582 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5583 struct amdgpu_device *adev = ring->adev; 5584 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5585 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5586 5587 if (fw_version_ok) 5588 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5589 ref, mask, 0x20); 5590 else 5591 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5592 ref, mask); 5593 } 5594 5595 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5596 { 5597 struct amdgpu_device *adev = ring->adev; 5598 uint32_t value = 0; 5599 5600 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5601 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5602 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5603 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5604 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5605 } 5606 5607 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5608 enum amdgpu_interrupt_state state) 5609 { 5610 switch (state) { 5611 case AMDGPU_IRQ_STATE_DISABLE: 5612 case AMDGPU_IRQ_STATE_ENABLE: 5613 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5614 TIME_STAMP_INT_ENABLE, 5615 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5616 break; 5617 default: 5618 break; 5619 } 5620 } 5621 5622 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5623 int me, int pipe, 5624 enum amdgpu_interrupt_state state) 5625 { 5626 u32 mec_int_cntl, mec_int_cntl_reg; 5627 5628 /* 5629 * amdgpu controls only the first MEC. That's why this function only 5630 * handles the setting of interrupts for this specific MEC. All other 5631 * pipes' interrupts are set by amdkfd. 5632 */ 5633 5634 if (me == 1) { 5635 switch (pipe) { 5636 case 0: 5637 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5638 break; 5639 case 1: 5640 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5641 break; 5642 case 2: 5643 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5644 break; 5645 case 3: 5646 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5647 break; 5648 default: 5649 DRM_DEBUG("invalid pipe %d\n", pipe); 5650 return; 5651 } 5652 } else { 5653 DRM_DEBUG("invalid me %d\n", me); 5654 return; 5655 } 5656 5657 switch (state) { 5658 case AMDGPU_IRQ_STATE_DISABLE: 5659 mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg); 5660 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5661 TIME_STAMP_INT_ENABLE, 0); 5662 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5663 break; 5664 case AMDGPU_IRQ_STATE_ENABLE: 5665 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 5666 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5667 TIME_STAMP_INT_ENABLE, 1); 5668 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 5669 break; 5670 default: 5671 break; 5672 } 5673 } 5674 5675 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5676 struct amdgpu_irq_src *source, 5677 unsigned type, 5678 enum amdgpu_interrupt_state state) 5679 { 5680 switch (state) { 5681 case AMDGPU_IRQ_STATE_DISABLE: 5682 case AMDGPU_IRQ_STATE_ENABLE: 5683 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5684 PRIV_REG_INT_ENABLE, 5685 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5686 break; 5687 default: 5688 break; 5689 } 5690 5691 return 0; 5692 } 5693 5694 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5695 struct amdgpu_irq_src *source, 5696 unsigned type, 5697 enum amdgpu_interrupt_state state) 5698 { 5699 switch (state) { 5700 case AMDGPU_IRQ_STATE_DISABLE: 5701 case AMDGPU_IRQ_STATE_ENABLE: 5702 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5703 PRIV_INSTR_INT_ENABLE, 5704 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5705 break; 5706 default: 5707 break; 5708 } 5709 5710 return 0; 5711 } 5712 5713 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5714 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5715 CP_ECC_ERROR_INT_ENABLE, 1) 5716 5717 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5718 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5719 CP_ECC_ERROR_INT_ENABLE, 0) 5720 5721 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5722 struct amdgpu_irq_src *source, 5723 unsigned type, 5724 enum amdgpu_interrupt_state state) 5725 { 5726 switch (state) { 5727 case AMDGPU_IRQ_STATE_DISABLE: 5728 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5729 CP_ECC_ERROR_INT_ENABLE, 0); 5730 DISABLE_ECC_ON_ME_PIPE(1, 0); 5731 DISABLE_ECC_ON_ME_PIPE(1, 1); 5732 DISABLE_ECC_ON_ME_PIPE(1, 2); 5733 DISABLE_ECC_ON_ME_PIPE(1, 3); 5734 break; 5735 5736 case AMDGPU_IRQ_STATE_ENABLE: 5737 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5738 CP_ECC_ERROR_INT_ENABLE, 1); 5739 ENABLE_ECC_ON_ME_PIPE(1, 0); 5740 ENABLE_ECC_ON_ME_PIPE(1, 1); 5741 ENABLE_ECC_ON_ME_PIPE(1, 2); 5742 ENABLE_ECC_ON_ME_PIPE(1, 3); 5743 break; 5744 default: 5745 break; 5746 } 5747 5748 return 0; 5749 } 5750 5751 5752 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5753 struct amdgpu_irq_src *src, 5754 unsigned type, 5755 enum amdgpu_interrupt_state state) 5756 { 5757 switch (type) { 5758 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5759 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5760 break; 5761 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5762 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5763 break; 5764 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5765 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5766 break; 5767 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5768 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5769 break; 5770 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5771 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5772 break; 5773 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5774 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5775 break; 5776 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5777 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5778 break; 5779 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5780 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5781 break; 5782 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5783 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5784 break; 5785 default: 5786 break; 5787 } 5788 return 0; 5789 } 5790 5791 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5792 struct amdgpu_irq_src *source, 5793 struct amdgpu_iv_entry *entry) 5794 { 5795 int i; 5796 u8 me_id, pipe_id, queue_id; 5797 struct amdgpu_ring *ring; 5798 5799 DRM_DEBUG("IH: CP EOP\n"); 5800 me_id = (entry->ring_id & 0x0c) >> 2; 5801 pipe_id = (entry->ring_id & 0x03) >> 0; 5802 queue_id = (entry->ring_id & 0x70) >> 4; 5803 5804 switch (me_id) { 5805 case 0: 5806 if (adev->gfx.num_gfx_rings && 5807 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) { 5808 /* Fence signals are handled on the software rings*/ 5809 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 5810 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]); 5811 } 5812 break; 5813 case 1: 5814 case 2: 5815 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5816 ring = &adev->gfx.compute_ring[i]; 5817 /* Per-queue interrupt is supported for MEC starting from VI. 5818 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5819 */ 5820 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5821 amdgpu_fence_process(ring); 5822 } 5823 break; 5824 } 5825 return 0; 5826 } 5827 5828 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5829 struct amdgpu_iv_entry *entry) 5830 { 5831 u8 me_id, pipe_id, queue_id; 5832 struct amdgpu_ring *ring; 5833 int i; 5834 5835 me_id = (entry->ring_id & 0x0c) >> 2; 5836 pipe_id = (entry->ring_id & 0x03) >> 0; 5837 queue_id = (entry->ring_id & 0x70) >> 4; 5838 5839 switch (me_id) { 5840 case 0: 5841 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5842 break; 5843 case 1: 5844 case 2: 5845 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5846 ring = &adev->gfx.compute_ring[i]; 5847 if (ring->me == me_id && ring->pipe == pipe_id && 5848 ring->queue == queue_id) 5849 drm_sched_fault(&ring->sched); 5850 } 5851 break; 5852 } 5853 } 5854 5855 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5856 struct amdgpu_irq_src *source, 5857 struct amdgpu_iv_entry *entry) 5858 { 5859 DRM_ERROR("Illegal register access in command stream\n"); 5860 gfx_v9_0_fault(adev, entry); 5861 return 0; 5862 } 5863 5864 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5865 struct amdgpu_irq_src *source, 5866 struct amdgpu_iv_entry *entry) 5867 { 5868 DRM_ERROR("Illegal instruction in command stream\n"); 5869 gfx_v9_0_fault(adev, entry); 5870 return 0; 5871 } 5872 5873 5874 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5875 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5876 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5877 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5878 }, 5879 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5880 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5881 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5882 }, 5883 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5884 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5885 0, 0 5886 }, 5887 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5888 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5889 0, 0 5890 }, 5891 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5892 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5893 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5894 }, 5895 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5896 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5897 0, 0 5898 }, 5899 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5900 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5901 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5902 }, 5903 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5904 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5905 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5906 }, 5907 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5908 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5909 0, 0 5910 }, 5911 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5912 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5913 0, 0 5914 }, 5915 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5916 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5917 0, 0 5918 }, 5919 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5920 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5921 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5922 }, 5923 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5924 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5925 0, 0 5926 }, 5927 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5928 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5929 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5930 }, 5931 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5932 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5933 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5934 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5935 }, 5936 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5937 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5938 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5939 0, 0 5940 }, 5941 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5942 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5943 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5944 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5945 }, 5946 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5947 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5948 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5949 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5950 }, 5951 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5952 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5953 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5954 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5955 }, 5956 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5957 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5958 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5959 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5960 }, 5961 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5962 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5963 0, 0 5964 }, 5965 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5966 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5967 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5968 }, 5969 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5970 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5971 0, 0 5972 }, 5973 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5974 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5975 0, 0 5976 }, 5977 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5978 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 5979 0, 0 5980 }, 5981 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5982 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 5983 0, 0 5984 }, 5985 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5986 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 5987 0, 0 5988 }, 5989 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5990 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 5991 0, 0 5992 }, 5993 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5994 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 5995 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 5996 }, 5997 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5998 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 5999 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 6000 }, 6001 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6002 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 6003 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 6004 }, 6005 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6006 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 6007 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 6008 }, 6009 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6010 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 6011 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 6012 }, 6013 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6014 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 6015 0, 0 6016 }, 6017 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6018 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 6019 0, 0 6020 }, 6021 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6022 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 6023 0, 0 6024 }, 6025 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6026 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 6027 0, 0 6028 }, 6029 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6030 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 6031 0, 0 6032 }, 6033 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6034 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6035 0, 0 6036 }, 6037 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6038 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6039 0, 0 6040 }, 6041 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6042 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6043 0, 0 6044 }, 6045 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6046 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6047 0, 0 6048 }, 6049 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6050 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6051 0, 0 6052 }, 6053 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6054 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6055 0, 0 6056 }, 6057 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6058 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6059 0, 0 6060 }, 6061 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6062 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6063 0, 0 6064 }, 6065 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6066 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6067 0, 0 6068 }, 6069 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6070 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6071 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6072 }, 6073 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6074 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6075 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6076 }, 6077 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6078 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6079 0, 0 6080 }, 6081 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6082 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6083 0, 0 6084 }, 6085 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6086 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6087 0, 0 6088 }, 6089 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6090 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6091 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6092 }, 6093 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6094 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6095 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6096 }, 6097 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6098 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6099 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6100 }, 6101 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6102 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6103 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6104 }, 6105 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6106 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6107 0, 0 6108 }, 6109 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6110 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6111 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6112 }, 6113 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6114 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6115 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6116 }, 6117 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6118 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6119 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6120 }, 6121 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6122 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6123 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6124 }, 6125 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6126 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6127 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6128 }, 6129 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6130 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6131 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6132 }, 6133 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6134 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6135 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6136 }, 6137 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6138 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6139 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6140 }, 6141 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6142 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6143 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6144 }, 6145 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6146 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6147 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6148 }, 6149 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6150 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6151 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6152 }, 6153 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6154 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6155 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6156 }, 6157 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6158 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6159 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6160 }, 6161 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6162 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6163 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6164 }, 6165 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6166 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6167 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6168 }, 6169 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6170 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6171 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6172 }, 6173 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6174 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6175 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6176 }, 6177 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6178 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6179 0, 0 6180 }, 6181 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6182 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6183 0, 0 6184 }, 6185 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6186 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6187 0, 0 6188 }, 6189 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6190 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6191 0, 0 6192 }, 6193 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6194 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6195 0, 0 6196 }, 6197 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6198 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6199 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6200 }, 6201 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6202 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6203 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6204 }, 6205 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6206 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6207 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6208 }, 6209 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6210 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6211 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6212 }, 6213 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6214 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6215 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6216 }, 6217 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6218 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6219 0, 0 6220 }, 6221 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6222 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6223 0, 0 6224 }, 6225 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6226 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6227 0, 0 6228 }, 6229 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6230 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6231 0, 0 6232 }, 6233 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6234 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6235 0, 0 6236 }, 6237 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6238 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6239 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6240 }, 6241 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6242 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6243 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6244 }, 6245 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6246 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6247 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6248 }, 6249 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6250 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6251 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6252 }, 6253 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6254 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6255 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6256 }, 6257 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6258 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6259 0, 0 6260 }, 6261 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6262 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6263 0, 0 6264 }, 6265 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6266 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6267 0, 0 6268 }, 6269 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6270 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6271 0, 0 6272 }, 6273 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6274 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6275 0, 0 6276 }, 6277 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6278 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6279 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6280 }, 6281 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6282 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6283 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6284 }, 6285 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6286 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6287 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6288 }, 6289 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6290 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6291 0, 0 6292 }, 6293 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6294 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6295 0, 0 6296 }, 6297 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6298 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6299 0, 0 6300 }, 6301 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6302 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6303 0, 0 6304 }, 6305 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6306 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6307 0, 0 6308 }, 6309 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6310 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6311 0, 0 6312 } 6313 }; 6314 6315 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6316 void *inject_if) 6317 { 6318 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6319 int ret; 6320 struct ta_ras_trigger_error_input block_info = { 0 }; 6321 6322 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6323 return -EINVAL; 6324 6325 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6326 return -EINVAL; 6327 6328 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6329 return -EPERM; 6330 6331 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6332 info->head.type)) { 6333 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6334 ras_gfx_subblocks[info->head.sub_block_index].name, 6335 info->head.type); 6336 return -EPERM; 6337 } 6338 6339 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6340 info->head.type)) { 6341 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6342 ras_gfx_subblocks[info->head.sub_block_index].name, 6343 info->head.type); 6344 return -EPERM; 6345 } 6346 6347 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6348 block_info.sub_block_index = 6349 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6350 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6351 block_info.address = info->address; 6352 block_info.value = info->value; 6353 6354 mutex_lock(&adev->grbm_idx_mutex); 6355 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6356 mutex_unlock(&adev->grbm_idx_mutex); 6357 6358 return ret; 6359 } 6360 6361 static const char *vml2_mems[] = { 6362 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6363 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6364 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6365 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6366 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6367 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6368 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6369 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6370 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6371 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6372 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6373 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6374 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6375 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6376 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6377 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6378 }; 6379 6380 static const char *vml2_walker_mems[] = { 6381 "UTC_VML2_CACHE_PDE0_MEM0", 6382 "UTC_VML2_CACHE_PDE0_MEM1", 6383 "UTC_VML2_CACHE_PDE1_MEM0", 6384 "UTC_VML2_CACHE_PDE1_MEM1", 6385 "UTC_VML2_CACHE_PDE2_MEM0", 6386 "UTC_VML2_CACHE_PDE2_MEM1", 6387 "UTC_VML2_RDIF_LOG_FIFO", 6388 }; 6389 6390 static const char *atc_l2_cache_2m_mems[] = { 6391 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6392 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6393 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6394 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6395 }; 6396 6397 static const char *atc_l2_cache_4k_mems[] = { 6398 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6399 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6400 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6401 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6402 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6403 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6404 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6405 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6406 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6407 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6408 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6409 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6410 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6411 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6412 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6413 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6414 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6415 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6416 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6417 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6418 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6419 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6420 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6421 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6422 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6423 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6424 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6425 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6426 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6427 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6428 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6429 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6430 }; 6431 6432 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6433 struct ras_err_data *err_data) 6434 { 6435 uint32_t i, data; 6436 uint32_t sec_count, ded_count; 6437 6438 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6439 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6440 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6441 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6442 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6443 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6444 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6445 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6446 6447 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6448 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6449 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6450 6451 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6452 if (sec_count) { 6453 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6454 "SEC %d\n", i, vml2_mems[i], sec_count); 6455 err_data->ce_count += sec_count; 6456 } 6457 6458 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6459 if (ded_count) { 6460 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6461 "DED %d\n", i, vml2_mems[i], ded_count); 6462 err_data->ue_count += ded_count; 6463 } 6464 } 6465 6466 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6467 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6468 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6469 6470 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6471 SEC_COUNT); 6472 if (sec_count) { 6473 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6474 "SEC %d\n", i, vml2_walker_mems[i], sec_count); 6475 err_data->ce_count += sec_count; 6476 } 6477 6478 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6479 DED_COUNT); 6480 if (ded_count) { 6481 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6482 "DED %d\n", i, vml2_walker_mems[i], ded_count); 6483 err_data->ue_count += ded_count; 6484 } 6485 } 6486 6487 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6488 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6489 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6490 6491 sec_count = (data & 0x00006000L) >> 0xd; 6492 if (sec_count) { 6493 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6494 "SEC %d\n", i, atc_l2_cache_2m_mems[i], 6495 sec_count); 6496 err_data->ce_count += sec_count; 6497 } 6498 } 6499 6500 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6501 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6502 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6503 6504 sec_count = (data & 0x00006000L) >> 0xd; 6505 if (sec_count) { 6506 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6507 "SEC %d\n", i, atc_l2_cache_4k_mems[i], 6508 sec_count); 6509 err_data->ce_count += sec_count; 6510 } 6511 6512 ded_count = (data & 0x00018000L) >> 0xf; 6513 if (ded_count) { 6514 dev_info(adev->dev, "Instance[%d]: SubBlock %s, " 6515 "DED %d\n", i, atc_l2_cache_4k_mems[i], 6516 ded_count); 6517 err_data->ue_count += ded_count; 6518 } 6519 } 6520 6521 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6522 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6523 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6524 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6525 6526 return 0; 6527 } 6528 6529 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev, 6530 const struct soc15_reg_entry *reg, 6531 uint32_t se_id, uint32_t inst_id, uint32_t value, 6532 uint32_t *sec_count, uint32_t *ded_count) 6533 { 6534 uint32_t i; 6535 uint32_t sec_cnt, ded_cnt; 6536 6537 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6538 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6539 gfx_v9_0_ras_fields[i].seg != reg->seg || 6540 gfx_v9_0_ras_fields[i].inst != reg->inst) 6541 continue; 6542 6543 sec_cnt = (value & 6544 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6545 gfx_v9_0_ras_fields[i].sec_count_shift; 6546 if (sec_cnt) { 6547 dev_info(adev->dev, "GFX SubBlock %s, " 6548 "Instance[%d][%d], SEC %d\n", 6549 gfx_v9_0_ras_fields[i].name, 6550 se_id, inst_id, 6551 sec_cnt); 6552 *sec_count += sec_cnt; 6553 } 6554 6555 ded_cnt = (value & 6556 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6557 gfx_v9_0_ras_fields[i].ded_count_shift; 6558 if (ded_cnt) { 6559 dev_info(adev->dev, "GFX SubBlock %s, " 6560 "Instance[%d][%d], DED %d\n", 6561 gfx_v9_0_ras_fields[i].name, 6562 se_id, inst_id, 6563 ded_cnt); 6564 *ded_count += ded_cnt; 6565 } 6566 } 6567 6568 return 0; 6569 } 6570 6571 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6572 { 6573 int i, j, k; 6574 6575 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6576 return; 6577 6578 /* read back registers to clear the counters */ 6579 mutex_lock(&adev->grbm_idx_mutex); 6580 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6581 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6582 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6583 amdgpu_gfx_select_se_sh(adev, j, 0x0, k); 6584 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6585 } 6586 } 6587 } 6588 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6589 mutex_unlock(&adev->grbm_idx_mutex); 6590 6591 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6592 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6593 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6594 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6595 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6596 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6597 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6598 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6599 6600 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6601 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6602 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6603 } 6604 6605 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6606 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6607 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6608 } 6609 6610 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6611 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6612 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6613 } 6614 6615 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6616 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6617 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6618 } 6619 6620 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6621 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6622 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6623 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6624 } 6625 6626 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6627 void *ras_error_status) 6628 { 6629 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6630 uint32_t sec_count = 0, ded_count = 0; 6631 uint32_t i, j, k; 6632 uint32_t reg_value; 6633 6634 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6635 return; 6636 6637 err_data->ue_count = 0; 6638 err_data->ce_count = 0; 6639 6640 mutex_lock(&adev->grbm_idx_mutex); 6641 6642 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6643 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6644 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6645 amdgpu_gfx_select_se_sh(adev, j, 0, k); 6646 reg_value = 6647 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6648 if (reg_value) 6649 gfx_v9_0_ras_error_count(adev, 6650 &gfx_v9_0_edc_counter_regs[i], 6651 j, k, reg_value, 6652 &sec_count, &ded_count); 6653 } 6654 } 6655 } 6656 6657 err_data->ce_count += sec_count; 6658 err_data->ue_count += ded_count; 6659 6660 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6661 mutex_unlock(&adev->grbm_idx_mutex); 6662 6663 gfx_v9_0_query_utc_edc_status(adev, err_data); 6664 } 6665 6666 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) 6667 { 6668 const unsigned int cp_coher_cntl = 6669 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 6670 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 6671 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 6672 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 6673 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 6674 6675 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 6676 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 6677 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 6678 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 6679 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 6680 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 6681 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 6682 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 6683 } 6684 6685 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, 6686 uint32_t pipe, bool enable) 6687 { 6688 struct amdgpu_device *adev = ring->adev; 6689 uint32_t val; 6690 uint32_t wcl_cs_reg; 6691 6692 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 6693 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT; 6694 6695 switch (pipe) { 6696 case 0: 6697 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); 6698 break; 6699 case 1: 6700 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); 6701 break; 6702 case 2: 6703 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); 6704 break; 6705 case 3: 6706 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); 6707 break; 6708 default: 6709 DRM_DEBUG("invalid pipe %d\n", pipe); 6710 return; 6711 } 6712 6713 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 6714 6715 } 6716 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 6717 { 6718 struct amdgpu_device *adev = ring->adev; 6719 uint32_t val; 6720 int i; 6721 6722 6723 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 6724 * number of gfx waves. Setting 5 bit will make sure gfx only gets 6725 * around 25% of gpu resources. 6726 */ 6727 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT; 6728 amdgpu_ring_emit_wreg(ring, 6729 SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX), 6730 val); 6731 6732 /* Restrict waves for normal/low priority compute queues as well 6733 * to get best QoS for high priority compute jobs. 6734 * 6735 * amdgpu controls only 1st ME(0-3 CS pipes). 6736 */ 6737 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 6738 if (i != ring->pipe) 6739 gfx_v9_0_emit_wave_limit_cs(ring, i, enable); 6740 6741 } 6742 } 6743 6744 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6745 .name = "gfx_v9_0", 6746 .early_init = gfx_v9_0_early_init, 6747 .late_init = gfx_v9_0_late_init, 6748 .sw_init = gfx_v9_0_sw_init, 6749 .sw_fini = gfx_v9_0_sw_fini, 6750 .hw_init = gfx_v9_0_hw_init, 6751 .hw_fini = gfx_v9_0_hw_fini, 6752 .suspend = gfx_v9_0_suspend, 6753 .resume = gfx_v9_0_resume, 6754 .is_idle = gfx_v9_0_is_idle, 6755 .wait_for_idle = gfx_v9_0_wait_for_idle, 6756 .soft_reset = gfx_v9_0_soft_reset, 6757 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6758 .set_powergating_state = gfx_v9_0_set_powergating_state, 6759 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6760 }; 6761 6762 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6763 .type = AMDGPU_RING_TYPE_GFX, 6764 .align_mask = 0xff, 6765 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6766 .support_64bit_ptrs = true, 6767 .secure_submission_supported = true, 6768 .vmhub = AMDGPU_GFXHUB_0, 6769 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6770 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6771 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6772 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6773 5 + /* COND_EXEC */ 6774 7 + /* PIPELINE_SYNC */ 6775 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6776 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6777 2 + /* VM_FLUSH */ 6778 8 + /* FENCE for VM_FLUSH */ 6779 20 + /* GDS switch */ 6780 4 + /* double SWITCH_BUFFER, 6781 the first COND_EXEC jump to the place just 6782 prior to this double SWITCH_BUFFER */ 6783 5 + /* COND_EXEC */ 6784 7 + /* HDP_flush */ 6785 4 + /* VGT_flush */ 6786 14 + /* CE_META */ 6787 31 + /* DE_META */ 6788 3 + /* CNTX_CTRL */ 6789 5 + /* HDP_INVL */ 6790 8 + 8 + /* FENCE x2 */ 6791 2 + /* SWITCH_BUFFER */ 6792 7, /* gfx_v9_0_emit_mem_sync */ 6793 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6794 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6795 .emit_fence = gfx_v9_0_ring_emit_fence, 6796 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6797 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6798 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6799 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6800 .test_ring = gfx_v9_0_ring_test_ring, 6801 .test_ib = gfx_v9_0_ring_test_ib, 6802 .insert_nop = amdgpu_ring_insert_nop, 6803 .pad_ib = amdgpu_ring_generic_pad_ib, 6804 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6805 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6806 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6807 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6808 .preempt_ib = gfx_v9_0_ring_preempt_ib, 6809 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6810 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6811 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6812 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6813 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6814 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6815 }; 6816 6817 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 6818 .type = AMDGPU_RING_TYPE_GFX, 6819 .align_mask = 0xff, 6820 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6821 .support_64bit_ptrs = true, 6822 .secure_submission_supported = true, 6823 .vmhub = AMDGPU_GFXHUB_0, 6824 .get_rptr = amdgpu_sw_ring_get_rptr_gfx, 6825 .get_wptr = amdgpu_sw_ring_get_wptr_gfx, 6826 .set_wptr = amdgpu_sw_ring_set_wptr_gfx, 6827 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6828 5 + /* COND_EXEC */ 6829 7 + /* PIPELINE_SYNC */ 6830 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6831 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6832 2 + /* VM_FLUSH */ 6833 8 + /* FENCE for VM_FLUSH */ 6834 20 + /* GDS switch */ 6835 4 + /* double SWITCH_BUFFER, 6836 * the first COND_EXEC jump to the place just 6837 * prior to this double SWITCH_BUFFER 6838 */ 6839 5 + /* COND_EXEC */ 6840 7 + /* HDP_flush */ 6841 4 + /* VGT_flush */ 6842 14 + /* CE_META */ 6843 31 + /* DE_META */ 6844 3 + /* CNTX_CTRL */ 6845 5 + /* HDP_INVL */ 6846 8 + 8 + /* FENCE x2 */ 6847 2 + /* SWITCH_BUFFER */ 6848 7, /* gfx_v9_0_emit_mem_sync */ 6849 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6850 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6851 .emit_fence = gfx_v9_0_ring_emit_fence, 6852 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6853 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6854 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6855 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6856 .test_ring = gfx_v9_0_ring_test_ring, 6857 .test_ib = gfx_v9_0_ring_test_ib, 6858 .insert_nop = amdgpu_sw_ring_insert_nop, 6859 .pad_ib = amdgpu_ring_generic_pad_ib, 6860 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6861 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6862 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6863 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6864 .emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl, 6865 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6866 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6867 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6868 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6869 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6870 }; 6871 6872 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6873 .type = AMDGPU_RING_TYPE_COMPUTE, 6874 .align_mask = 0xff, 6875 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6876 .support_64bit_ptrs = true, 6877 .vmhub = AMDGPU_GFXHUB_0, 6878 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6879 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6880 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6881 .emit_frame_size = 6882 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6883 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6884 5 + /* hdp invalidate */ 6885 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6886 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6887 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6888 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6889 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6890 7 + /* gfx_v9_0_emit_mem_sync */ 6891 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ 6892 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ 6893 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6894 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6895 .emit_fence = gfx_v9_0_ring_emit_fence, 6896 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6897 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6898 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6899 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6900 .test_ring = gfx_v9_0_ring_test_ring, 6901 .test_ib = gfx_v9_0_ring_test_ib, 6902 .insert_nop = amdgpu_ring_insert_nop, 6903 .pad_ib = amdgpu_ring_generic_pad_ib, 6904 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6905 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6906 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6907 .emit_mem_sync = gfx_v9_0_emit_mem_sync, 6908 .emit_wave_limit = gfx_v9_0_emit_wave_limit, 6909 }; 6910 6911 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6912 .type = AMDGPU_RING_TYPE_KIQ, 6913 .align_mask = 0xff, 6914 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6915 .support_64bit_ptrs = true, 6916 .vmhub = AMDGPU_GFXHUB_0, 6917 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6918 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6919 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6920 .emit_frame_size = 6921 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6922 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6923 5 + /* hdp invalidate */ 6924 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6925 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6926 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6927 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6928 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6929 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6930 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6931 .test_ring = gfx_v9_0_ring_test_ring, 6932 .insert_nop = amdgpu_ring_insert_nop, 6933 .pad_ib = amdgpu_ring_generic_pad_ib, 6934 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6935 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6936 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6937 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6938 }; 6939 6940 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6941 { 6942 int i; 6943 6944 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6945 6946 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6947 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6948 6949 if (adev->gfx.num_gfx_rings) { 6950 for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) 6951 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx; 6952 } 6953 6954 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6955 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6956 } 6957 6958 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6959 .set = gfx_v9_0_set_eop_interrupt_state, 6960 .process = gfx_v9_0_eop_irq, 6961 }; 6962 6963 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6964 .set = gfx_v9_0_set_priv_reg_fault_state, 6965 .process = gfx_v9_0_priv_reg_irq, 6966 }; 6967 6968 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6969 .set = gfx_v9_0_set_priv_inst_fault_state, 6970 .process = gfx_v9_0_priv_inst_irq, 6971 }; 6972 6973 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6974 .set = gfx_v9_0_set_cp_ecc_error_state, 6975 .process = amdgpu_gfx_cp_ecc_error_irq, 6976 }; 6977 6978 6979 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6980 { 6981 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6982 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 6983 6984 adev->gfx.priv_reg_irq.num_types = 1; 6985 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 6986 6987 adev->gfx.priv_inst_irq.num_types = 1; 6988 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 6989 6990 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 6991 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 6992 } 6993 6994 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 6995 { 6996 switch (adev->ip_versions[GC_HWIP][0]) { 6997 case IP_VERSION(9, 0, 1): 6998 case IP_VERSION(9, 2, 1): 6999 case IP_VERSION(9, 4, 0): 7000 case IP_VERSION(9, 2, 2): 7001 case IP_VERSION(9, 1, 0): 7002 case IP_VERSION(9, 4, 1): 7003 case IP_VERSION(9, 3, 0): 7004 case IP_VERSION(9, 4, 2): 7005 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 7006 break; 7007 default: 7008 break; 7009 } 7010 } 7011 7012 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 7013 { 7014 /* init asci gds info */ 7015 switch (adev->ip_versions[GC_HWIP][0]) { 7016 case IP_VERSION(9, 0, 1): 7017 case IP_VERSION(9, 2, 1): 7018 case IP_VERSION(9, 4, 0): 7019 adev->gds.gds_size = 0x10000; 7020 break; 7021 case IP_VERSION(9, 2, 2): 7022 case IP_VERSION(9, 1, 0): 7023 case IP_VERSION(9, 4, 1): 7024 adev->gds.gds_size = 0x1000; 7025 break; 7026 case IP_VERSION(9, 4, 2): 7027 /* aldebaran removed all the GDS internal memory, 7028 * only support GWS opcode in kernel, like barrier 7029 * semaphore.etc */ 7030 adev->gds.gds_size = 0; 7031 break; 7032 default: 7033 adev->gds.gds_size = 0x10000; 7034 break; 7035 } 7036 7037 switch (adev->ip_versions[GC_HWIP][0]) { 7038 case IP_VERSION(9, 0, 1): 7039 case IP_VERSION(9, 4, 0): 7040 adev->gds.gds_compute_max_wave_id = 0x7ff; 7041 break; 7042 case IP_VERSION(9, 2, 1): 7043 adev->gds.gds_compute_max_wave_id = 0x27f; 7044 break; 7045 case IP_VERSION(9, 2, 2): 7046 case IP_VERSION(9, 1, 0): 7047 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 7048 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 7049 else 7050 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 7051 break; 7052 case IP_VERSION(9, 4, 1): 7053 adev->gds.gds_compute_max_wave_id = 0xfff; 7054 break; 7055 case IP_VERSION(9, 4, 2): 7056 /* deprecated for Aldebaran, no usage at all */ 7057 adev->gds.gds_compute_max_wave_id = 0; 7058 break; 7059 default: 7060 /* this really depends on the chip */ 7061 adev->gds.gds_compute_max_wave_id = 0x7ff; 7062 break; 7063 } 7064 7065 adev->gds.gws_size = 64; 7066 adev->gds.oa_size = 16; 7067 } 7068 7069 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 7070 u32 bitmap) 7071 { 7072 u32 data; 7073 7074 if (!bitmap) 7075 return; 7076 7077 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7078 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7079 7080 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 7081 } 7082 7083 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 7084 { 7085 u32 data, mask; 7086 7087 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 7088 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 7089 7090 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 7091 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 7092 7093 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7094 7095 return (~data) & mask; 7096 } 7097 7098 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 7099 struct amdgpu_cu_info *cu_info) 7100 { 7101 int i, j, k, counter, active_cu_number = 0; 7102 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7103 unsigned disable_masks[4 * 4]; 7104 7105 if (!adev || !cu_info) 7106 return -EINVAL; 7107 7108 /* 7109 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 7110 */ 7111 if (adev->gfx.config.max_shader_engines * 7112 adev->gfx.config.max_sh_per_se > 16) 7113 return -EINVAL; 7114 7115 amdgpu_gfx_parse_disable_cu(disable_masks, 7116 adev->gfx.config.max_shader_engines, 7117 adev->gfx.config.max_sh_per_se); 7118 7119 mutex_lock(&adev->grbm_idx_mutex); 7120 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7121 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7122 mask = 1; 7123 ao_bitmap = 0; 7124 counter = 0; 7125 amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 7126 gfx_v9_0_set_user_cu_inactive_bitmap( 7127 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7128 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 7129 7130 /* 7131 * The bitmap(and ao_cu_bitmap) in cu_info structure is 7132 * 4x4 size array, and it's usually suitable for Vega 7133 * ASICs which has 4*2 SE/SH layout. 7134 * But for Arcturus, SE/SH layout is changed to 8*1. 7135 * To mostly reduce the impact, we make it compatible 7136 * with current bitmap array as below: 7137 * SE4,SH0 --> bitmap[0][1] 7138 * SE5,SH0 --> bitmap[1][1] 7139 * SE6,SH0 --> bitmap[2][1] 7140 * SE7,SH0 --> bitmap[3][1] 7141 */ 7142 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 7143 7144 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7145 if (bitmap & mask) { 7146 if (counter < adev->gfx.config.max_cu_per_sh) 7147 ao_bitmap |= mask; 7148 counter ++; 7149 } 7150 mask <<= 1; 7151 } 7152 active_cu_number += counter; 7153 if (i < 2 && j < 2) 7154 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7155 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7156 } 7157 } 7158 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7159 mutex_unlock(&adev->grbm_idx_mutex); 7160 7161 cu_info->number = active_cu_number; 7162 cu_info->ao_cu_mask = ao_cu_mask; 7163 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 7164 7165 return 0; 7166 } 7167 7168 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 7169 { 7170 .type = AMD_IP_BLOCK_TYPE_GFX, 7171 .major = 9, 7172 .minor = 0, 7173 .rev = 0, 7174 .funcs = &gfx_v9_0_ip_funcs, 7175 }; 7176