1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_atomfirmware.h" 31 32 #include "gc/gc_9_0_offset.h" 33 #include "gc/gc_9_0_sh_mask.h" 34 #include "vega10_enum.h" 35 #include "hdp/hdp_4_0_offset.h" 36 37 #include "soc15_common.h" 38 #include "clearstate_gfx9.h" 39 #include "v9_structs.h" 40 41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 42 43 #include "amdgpu_ras.h" 44 45 #define GFX9_NUM_GFX_RINGS 1 46 #define GFX9_MEC_HPD_SIZE 4096 47 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 48 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 49 50 #define mmPWR_MISC_CNTL_STATUS 0x0183 51 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 54 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 55 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 56 57 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 59 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 60 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 61 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 62 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 63 64 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 66 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 67 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 68 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 69 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 70 71 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 72 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 73 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 74 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 75 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 76 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 77 78 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 81 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 88 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 91 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 92 93 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 94 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 95 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 96 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 97 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 98 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 99 100 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 101 { 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 122 }; 123 124 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 125 { 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 144 }; 145 146 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 147 { 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 159 }; 160 161 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 162 { 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 187 }; 188 189 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 190 { 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 198 }; 199 200 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 201 { 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 221 }; 222 223 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 224 { 225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 228 }; 229 230 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 231 { 232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 248 }; 249 250 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 251 { 252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800), 263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800), 264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000) 265 }; 266 267 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 268 { 269 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 270 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 271 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 272 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 273 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 274 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 275 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 276 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 277 }; 278 279 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 280 { 281 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 282 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 283 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 284 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 285 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 286 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 287 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 288 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 289 }; 290 291 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 292 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 293 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 294 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 295 296 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 297 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 298 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 299 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 300 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 301 struct amdgpu_cu_info *cu_info); 302 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 303 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 304 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 305 306 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 307 { 308 switch (adev->asic_type) { 309 case CHIP_VEGA10: 310 soc15_program_register_sequence(adev, 311 golden_settings_gc_9_0, 312 ARRAY_SIZE(golden_settings_gc_9_0)); 313 soc15_program_register_sequence(adev, 314 golden_settings_gc_9_0_vg10, 315 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 316 break; 317 case CHIP_VEGA12: 318 soc15_program_register_sequence(adev, 319 golden_settings_gc_9_2_1, 320 ARRAY_SIZE(golden_settings_gc_9_2_1)); 321 soc15_program_register_sequence(adev, 322 golden_settings_gc_9_2_1_vg12, 323 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 324 break; 325 case CHIP_VEGA20: 326 soc15_program_register_sequence(adev, 327 golden_settings_gc_9_0, 328 ARRAY_SIZE(golden_settings_gc_9_0)); 329 soc15_program_register_sequence(adev, 330 golden_settings_gc_9_0_vg20, 331 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 332 break; 333 case CHIP_RAVEN: 334 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 335 ARRAY_SIZE(golden_settings_gc_9_1)); 336 if (adev->rev_id >= 8) 337 soc15_program_register_sequence(adev, 338 golden_settings_gc_9_1_rv2, 339 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 340 else 341 soc15_program_register_sequence(adev, 342 golden_settings_gc_9_1_rv1, 343 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 344 break; 345 default: 346 break; 347 } 348 349 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 350 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 351 } 352 353 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 354 { 355 adev->gfx.scratch.num_reg = 8; 356 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 357 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 358 } 359 360 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 361 bool wc, uint32_t reg, uint32_t val) 362 { 363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 364 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 365 WRITE_DATA_DST_SEL(0) | 366 (wc ? WR_CONFIRM : 0)); 367 amdgpu_ring_write(ring, reg); 368 amdgpu_ring_write(ring, 0); 369 amdgpu_ring_write(ring, val); 370 } 371 372 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 373 int mem_space, int opt, uint32_t addr0, 374 uint32_t addr1, uint32_t ref, uint32_t mask, 375 uint32_t inv) 376 { 377 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 378 amdgpu_ring_write(ring, 379 /* memory (1) or register (0) */ 380 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 381 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 382 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 383 WAIT_REG_MEM_ENGINE(eng_sel))); 384 385 if (mem_space) 386 BUG_ON(addr0 & 0x3); /* Dword align */ 387 amdgpu_ring_write(ring, addr0); 388 amdgpu_ring_write(ring, addr1); 389 amdgpu_ring_write(ring, ref); 390 amdgpu_ring_write(ring, mask); 391 amdgpu_ring_write(ring, inv); /* poll interval */ 392 } 393 394 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 395 { 396 struct amdgpu_device *adev = ring->adev; 397 uint32_t scratch; 398 uint32_t tmp = 0; 399 unsigned i; 400 int r; 401 402 r = amdgpu_gfx_scratch_get(adev, &scratch); 403 if (r) 404 return r; 405 406 WREG32(scratch, 0xCAFEDEAD); 407 r = amdgpu_ring_alloc(ring, 3); 408 if (r) 409 goto error_free_scratch; 410 411 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 412 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 413 amdgpu_ring_write(ring, 0xDEADBEEF); 414 amdgpu_ring_commit(ring); 415 416 for (i = 0; i < adev->usec_timeout; i++) { 417 tmp = RREG32(scratch); 418 if (tmp == 0xDEADBEEF) 419 break; 420 DRM_UDELAY(1); 421 } 422 423 if (i >= adev->usec_timeout) 424 r = -ETIMEDOUT; 425 426 error_free_scratch: 427 amdgpu_gfx_scratch_free(adev, scratch); 428 return r; 429 } 430 431 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 432 { 433 struct amdgpu_device *adev = ring->adev; 434 struct amdgpu_ib ib; 435 struct dma_fence *f = NULL; 436 437 unsigned index; 438 uint64_t gpu_addr; 439 uint32_t tmp; 440 long r; 441 442 r = amdgpu_device_wb_get(adev, &index); 443 if (r) 444 return r; 445 446 gpu_addr = adev->wb.gpu_addr + (index * 4); 447 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 448 memset(&ib, 0, sizeof(ib)); 449 r = amdgpu_ib_get(adev, NULL, 16, &ib); 450 if (r) 451 goto err1; 452 453 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 454 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 455 ib.ptr[2] = lower_32_bits(gpu_addr); 456 ib.ptr[3] = upper_32_bits(gpu_addr); 457 ib.ptr[4] = 0xDEADBEEF; 458 ib.length_dw = 5; 459 460 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 461 if (r) 462 goto err2; 463 464 r = dma_fence_wait_timeout(f, false, timeout); 465 if (r == 0) { 466 r = -ETIMEDOUT; 467 goto err2; 468 } else if (r < 0) { 469 goto err2; 470 } 471 472 tmp = adev->wb.wb[index]; 473 if (tmp == 0xDEADBEEF) 474 r = 0; 475 else 476 r = -EINVAL; 477 478 err2: 479 amdgpu_ib_free(adev, &ib, NULL); 480 dma_fence_put(f); 481 err1: 482 amdgpu_device_wb_free(adev, index); 483 return r; 484 } 485 486 487 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 488 { 489 release_firmware(adev->gfx.pfp_fw); 490 adev->gfx.pfp_fw = NULL; 491 release_firmware(adev->gfx.me_fw); 492 adev->gfx.me_fw = NULL; 493 release_firmware(adev->gfx.ce_fw); 494 adev->gfx.ce_fw = NULL; 495 release_firmware(adev->gfx.rlc_fw); 496 adev->gfx.rlc_fw = NULL; 497 release_firmware(adev->gfx.mec_fw); 498 adev->gfx.mec_fw = NULL; 499 release_firmware(adev->gfx.mec2_fw); 500 adev->gfx.mec2_fw = NULL; 501 502 kfree(adev->gfx.rlc.register_list_format); 503 } 504 505 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 506 { 507 const struct rlc_firmware_header_v2_1 *rlc_hdr; 508 509 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 510 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 511 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 512 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 513 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 514 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 515 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 516 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 517 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 518 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 519 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 520 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 521 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 522 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 523 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 524 } 525 526 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 527 { 528 adev->gfx.me_fw_write_wait = false; 529 adev->gfx.mec_fw_write_wait = false; 530 531 switch (adev->asic_type) { 532 case CHIP_VEGA10: 533 if ((adev->gfx.me_fw_version >= 0x0000009c) && 534 (adev->gfx.me_feature_version >= 42) && 535 (adev->gfx.pfp_fw_version >= 0x000000b1) && 536 (adev->gfx.pfp_feature_version >= 42)) 537 adev->gfx.me_fw_write_wait = true; 538 539 if ((adev->gfx.mec_fw_version >= 0x00000193) && 540 (adev->gfx.mec_feature_version >= 42)) 541 adev->gfx.mec_fw_write_wait = true; 542 break; 543 case CHIP_VEGA12: 544 if ((adev->gfx.me_fw_version >= 0x0000009c) && 545 (adev->gfx.me_feature_version >= 44) && 546 (adev->gfx.pfp_fw_version >= 0x000000b2) && 547 (adev->gfx.pfp_feature_version >= 44)) 548 adev->gfx.me_fw_write_wait = true; 549 550 if ((adev->gfx.mec_fw_version >= 0x00000196) && 551 (adev->gfx.mec_feature_version >= 44)) 552 adev->gfx.mec_fw_write_wait = true; 553 break; 554 case CHIP_VEGA20: 555 if ((adev->gfx.me_fw_version >= 0x0000009c) && 556 (adev->gfx.me_feature_version >= 44) && 557 (adev->gfx.pfp_fw_version >= 0x000000b2) && 558 (adev->gfx.pfp_feature_version >= 44)) 559 adev->gfx.me_fw_write_wait = true; 560 561 if ((adev->gfx.mec_fw_version >= 0x00000197) && 562 (adev->gfx.mec_feature_version >= 44)) 563 adev->gfx.mec_fw_write_wait = true; 564 break; 565 case CHIP_RAVEN: 566 if ((adev->gfx.me_fw_version >= 0x0000009c) && 567 (adev->gfx.me_feature_version >= 42) && 568 (adev->gfx.pfp_fw_version >= 0x000000b1) && 569 (adev->gfx.pfp_feature_version >= 42)) 570 adev->gfx.me_fw_write_wait = true; 571 572 if ((adev->gfx.mec_fw_version >= 0x00000192) && 573 (adev->gfx.mec_feature_version >= 42)) 574 adev->gfx.mec_fw_write_wait = true; 575 break; 576 default: 577 break; 578 } 579 } 580 581 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 582 { 583 switch (adev->asic_type) { 584 case CHIP_VEGA10: 585 case CHIP_VEGA12: 586 case CHIP_VEGA20: 587 break; 588 case CHIP_RAVEN: 589 if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) 590 break; 591 if ((adev->gfx.rlc_fw_version < 531) || 592 (adev->gfx.rlc_fw_version == 53815) || 593 (adev->gfx.rlc_feature_version < 1) || 594 !adev->gfx.rlc.is_rlc_v2_1) 595 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 596 break; 597 default: 598 break; 599 } 600 } 601 602 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 603 { 604 const char *chip_name; 605 char fw_name[30]; 606 int err; 607 struct amdgpu_firmware_info *info = NULL; 608 const struct common_firmware_header *header = NULL; 609 const struct gfx_firmware_header_v1_0 *cp_hdr; 610 const struct rlc_firmware_header_v2_0 *rlc_hdr; 611 unsigned int *tmp = NULL; 612 unsigned int i = 0; 613 uint16_t version_major; 614 uint16_t version_minor; 615 616 DRM_DEBUG("\n"); 617 618 switch (adev->asic_type) { 619 case CHIP_VEGA10: 620 chip_name = "vega10"; 621 break; 622 case CHIP_VEGA12: 623 chip_name = "vega12"; 624 break; 625 case CHIP_VEGA20: 626 chip_name = "vega20"; 627 break; 628 case CHIP_RAVEN: 629 if (adev->rev_id >= 8) 630 chip_name = "raven2"; 631 else if (adev->pdev->device == 0x15d8) 632 chip_name = "picasso"; 633 else 634 chip_name = "raven"; 635 break; 636 default: 637 BUG(); 638 } 639 640 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 641 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 642 if (err) 643 goto out; 644 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 645 if (err) 646 goto out; 647 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 648 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 649 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 650 651 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 652 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 653 if (err) 654 goto out; 655 err = amdgpu_ucode_validate(adev->gfx.me_fw); 656 if (err) 657 goto out; 658 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 659 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 660 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 661 662 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 663 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 664 if (err) 665 goto out; 666 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 667 if (err) 668 goto out; 669 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 670 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 671 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 672 673 /* 674 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 675 * instead of picasso_rlc.bin. 676 * Judgment method: 677 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 678 * or revision >= 0xD8 && revision <= 0xDF 679 * otherwise is PCO FP5 680 */ 681 if (!strcmp(chip_name, "picasso") && 682 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 683 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 684 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 685 else 686 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 687 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 688 if (err) 689 goto out; 690 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 691 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 692 693 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 694 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 695 if (version_major == 2 && version_minor == 1) 696 adev->gfx.rlc.is_rlc_v2_1 = true; 697 698 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 699 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 700 adev->gfx.rlc.save_and_restore_offset = 701 le32_to_cpu(rlc_hdr->save_and_restore_offset); 702 adev->gfx.rlc.clear_state_descriptor_offset = 703 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 704 adev->gfx.rlc.avail_scratch_ram_locations = 705 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 706 adev->gfx.rlc.reg_restore_list_size = 707 le32_to_cpu(rlc_hdr->reg_restore_list_size); 708 adev->gfx.rlc.reg_list_format_start = 709 le32_to_cpu(rlc_hdr->reg_list_format_start); 710 adev->gfx.rlc.reg_list_format_separate_start = 711 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 712 adev->gfx.rlc.starting_offsets_start = 713 le32_to_cpu(rlc_hdr->starting_offsets_start); 714 adev->gfx.rlc.reg_list_format_size_bytes = 715 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 716 adev->gfx.rlc.reg_list_size_bytes = 717 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 718 adev->gfx.rlc.register_list_format = 719 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 720 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 721 if (!adev->gfx.rlc.register_list_format) { 722 err = -ENOMEM; 723 goto out; 724 } 725 726 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 727 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 728 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 729 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 730 731 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 732 733 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 734 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 735 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 736 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 737 738 if (adev->gfx.rlc.is_rlc_v2_1) 739 gfx_v9_0_init_rlc_ext_microcode(adev); 740 741 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 742 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 743 if (err) 744 goto out; 745 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 746 if (err) 747 goto out; 748 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 749 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 750 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 751 752 753 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 754 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 755 if (!err) { 756 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 757 if (err) 758 goto out; 759 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 760 adev->gfx.mec2_fw->data; 761 adev->gfx.mec2_fw_version = 762 le32_to_cpu(cp_hdr->header.ucode_version); 763 adev->gfx.mec2_feature_version = 764 le32_to_cpu(cp_hdr->ucode_feature_version); 765 } else { 766 err = 0; 767 adev->gfx.mec2_fw = NULL; 768 } 769 770 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 771 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 772 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 773 info->fw = adev->gfx.pfp_fw; 774 header = (const struct common_firmware_header *)info->fw->data; 775 adev->firmware.fw_size += 776 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 777 778 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 779 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 780 info->fw = adev->gfx.me_fw; 781 header = (const struct common_firmware_header *)info->fw->data; 782 adev->firmware.fw_size += 783 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 784 785 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 786 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 787 info->fw = adev->gfx.ce_fw; 788 header = (const struct common_firmware_header *)info->fw->data; 789 adev->firmware.fw_size += 790 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 791 792 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 793 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 794 info->fw = adev->gfx.rlc_fw; 795 header = (const struct common_firmware_header *)info->fw->data; 796 adev->firmware.fw_size += 797 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 798 799 if (adev->gfx.rlc.is_rlc_v2_1 && 800 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 801 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 802 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 803 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 804 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 805 info->fw = adev->gfx.rlc_fw; 806 adev->firmware.fw_size += 807 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 808 809 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 810 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 811 info->fw = adev->gfx.rlc_fw; 812 adev->firmware.fw_size += 813 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 814 815 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 816 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 817 info->fw = adev->gfx.rlc_fw; 818 adev->firmware.fw_size += 819 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 820 } 821 822 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 823 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 824 info->fw = adev->gfx.mec_fw; 825 header = (const struct common_firmware_header *)info->fw->data; 826 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 827 adev->firmware.fw_size += 828 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 829 830 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 831 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 832 info->fw = adev->gfx.mec_fw; 833 adev->firmware.fw_size += 834 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 835 836 if (adev->gfx.mec2_fw) { 837 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 838 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 839 info->fw = adev->gfx.mec2_fw; 840 header = (const struct common_firmware_header *)info->fw->data; 841 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 842 adev->firmware.fw_size += 843 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 844 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 845 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 846 info->fw = adev->gfx.mec2_fw; 847 adev->firmware.fw_size += 848 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 849 } 850 851 } 852 853 out: 854 gfx_v9_0_check_if_need_gfxoff(adev); 855 gfx_v9_0_check_fw_write_wait(adev); 856 if (err) { 857 dev_err(adev->dev, 858 "gfx9: Failed to load firmware \"%s\"\n", 859 fw_name); 860 release_firmware(adev->gfx.pfp_fw); 861 adev->gfx.pfp_fw = NULL; 862 release_firmware(adev->gfx.me_fw); 863 adev->gfx.me_fw = NULL; 864 release_firmware(adev->gfx.ce_fw); 865 adev->gfx.ce_fw = NULL; 866 release_firmware(adev->gfx.rlc_fw); 867 adev->gfx.rlc_fw = NULL; 868 release_firmware(adev->gfx.mec_fw); 869 adev->gfx.mec_fw = NULL; 870 release_firmware(adev->gfx.mec2_fw); 871 adev->gfx.mec2_fw = NULL; 872 } 873 return err; 874 } 875 876 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 877 { 878 u32 count = 0; 879 const struct cs_section_def *sect = NULL; 880 const struct cs_extent_def *ext = NULL; 881 882 /* begin clear state */ 883 count += 2; 884 /* context control state */ 885 count += 3; 886 887 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 888 for (ext = sect->section; ext->extent != NULL; ++ext) { 889 if (sect->id == SECT_CONTEXT) 890 count += 2 + ext->reg_count; 891 else 892 return 0; 893 } 894 } 895 896 /* end clear state */ 897 count += 2; 898 /* clear state */ 899 count += 2; 900 901 return count; 902 } 903 904 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 905 volatile u32 *buffer) 906 { 907 u32 count = 0, i; 908 const struct cs_section_def *sect = NULL; 909 const struct cs_extent_def *ext = NULL; 910 911 if (adev->gfx.rlc.cs_data == NULL) 912 return; 913 if (buffer == NULL) 914 return; 915 916 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 917 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 918 919 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 920 buffer[count++] = cpu_to_le32(0x80000000); 921 buffer[count++] = cpu_to_le32(0x80000000); 922 923 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 924 for (ext = sect->section; ext->extent != NULL; ++ext) { 925 if (sect->id == SECT_CONTEXT) { 926 buffer[count++] = 927 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 928 buffer[count++] = cpu_to_le32(ext->reg_index - 929 PACKET3_SET_CONTEXT_REG_START); 930 for (i = 0; i < ext->reg_count; i++) 931 buffer[count++] = cpu_to_le32(ext->extent[i]); 932 } else { 933 return; 934 } 935 } 936 } 937 938 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 939 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 940 941 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 942 buffer[count++] = cpu_to_le32(0); 943 } 944 945 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 946 { 947 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 948 uint32_t pg_always_on_cu_num = 2; 949 uint32_t always_on_cu_num; 950 uint32_t i, j, k; 951 uint32_t mask, cu_bitmap, counter; 952 953 if (adev->flags & AMD_IS_APU) 954 always_on_cu_num = 4; 955 else if (adev->asic_type == CHIP_VEGA12) 956 always_on_cu_num = 8; 957 else 958 always_on_cu_num = 12; 959 960 mutex_lock(&adev->grbm_idx_mutex); 961 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 962 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 963 mask = 1; 964 cu_bitmap = 0; 965 counter = 0; 966 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 967 968 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 969 if (cu_info->bitmap[i][j] & mask) { 970 if (counter == pg_always_on_cu_num) 971 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 972 if (counter < always_on_cu_num) 973 cu_bitmap |= mask; 974 else 975 break; 976 counter++; 977 } 978 mask <<= 1; 979 } 980 981 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 982 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 983 } 984 } 985 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 986 mutex_unlock(&adev->grbm_idx_mutex); 987 } 988 989 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 990 { 991 uint32_t data; 992 993 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 994 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 995 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 996 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 997 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 998 999 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1000 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1001 1002 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1003 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1004 1005 mutex_lock(&adev->grbm_idx_mutex); 1006 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1007 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1008 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1009 1010 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1011 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1012 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1013 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1014 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1015 1016 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1017 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1018 data &= 0x0000FFFF; 1019 data |= 0x00C00000; 1020 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1021 1022 /* 1023 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1024 * programmed in gfx_v9_0_init_always_on_cu_mask() 1025 */ 1026 1027 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1028 * but used for RLC_LB_CNTL configuration */ 1029 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1030 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1031 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1032 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1033 mutex_unlock(&adev->grbm_idx_mutex); 1034 1035 gfx_v9_0_init_always_on_cu_mask(adev); 1036 } 1037 1038 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1039 { 1040 uint32_t data; 1041 1042 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1043 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1044 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1045 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1046 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1047 1048 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1049 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1050 1051 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1052 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1053 1054 mutex_lock(&adev->grbm_idx_mutex); 1055 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1056 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1057 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1058 1059 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1060 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1061 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1062 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1063 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1064 1065 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1066 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1067 data &= 0x0000FFFF; 1068 data |= 0x00C00000; 1069 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1070 1071 /* 1072 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1073 * programmed in gfx_v9_0_init_always_on_cu_mask() 1074 */ 1075 1076 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1077 * but used for RLC_LB_CNTL configuration */ 1078 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1079 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1080 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1081 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1082 mutex_unlock(&adev->grbm_idx_mutex); 1083 1084 gfx_v9_0_init_always_on_cu_mask(adev); 1085 } 1086 1087 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1088 { 1089 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1090 } 1091 1092 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1093 { 1094 return 5; 1095 } 1096 1097 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1098 { 1099 const struct cs_section_def *cs_data; 1100 int r; 1101 1102 adev->gfx.rlc.cs_data = gfx9_cs_data; 1103 1104 cs_data = adev->gfx.rlc.cs_data; 1105 1106 if (cs_data) { 1107 /* init clear state block */ 1108 r = amdgpu_gfx_rlc_init_csb(adev); 1109 if (r) 1110 return r; 1111 } 1112 1113 if (adev->asic_type == CHIP_RAVEN) { 1114 /* TODO: double check the cp_table_size for RV */ 1115 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1116 r = amdgpu_gfx_rlc_init_cpt(adev); 1117 if (r) 1118 return r; 1119 } 1120 1121 switch (adev->asic_type) { 1122 case CHIP_RAVEN: 1123 gfx_v9_0_init_lbpw(adev); 1124 break; 1125 case CHIP_VEGA20: 1126 gfx_v9_4_init_lbpw(adev); 1127 break; 1128 default: 1129 break; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev) 1136 { 1137 int r; 1138 1139 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1140 if (unlikely(r != 0)) 1141 return r; 1142 1143 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 1144 AMDGPU_GEM_DOMAIN_VRAM); 1145 if (!r) 1146 adev->gfx.rlc.clear_state_gpu_addr = 1147 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 1148 1149 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1150 1151 return r; 1152 } 1153 1154 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev) 1155 { 1156 int r; 1157 1158 if (!adev->gfx.rlc.clear_state_obj) 1159 return; 1160 1161 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 1162 if (likely(r == 0)) { 1163 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 1164 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1165 } 1166 } 1167 1168 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1169 { 1170 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1171 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1172 } 1173 1174 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1175 { 1176 int r; 1177 u32 *hpd; 1178 const __le32 *fw_data; 1179 unsigned fw_size; 1180 u32 *fw; 1181 size_t mec_hpd_size; 1182 1183 const struct gfx_firmware_header_v1_0 *mec_hdr; 1184 1185 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1186 1187 /* take ownership of the relevant compute queues */ 1188 amdgpu_gfx_compute_queue_acquire(adev); 1189 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1190 1191 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1192 AMDGPU_GEM_DOMAIN_VRAM, 1193 &adev->gfx.mec.hpd_eop_obj, 1194 &adev->gfx.mec.hpd_eop_gpu_addr, 1195 (void **)&hpd); 1196 if (r) { 1197 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1198 gfx_v9_0_mec_fini(adev); 1199 return r; 1200 } 1201 1202 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1203 1204 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1205 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1206 1207 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1208 1209 fw_data = (const __le32 *) 1210 (adev->gfx.mec_fw->data + 1211 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1212 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 1213 1214 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1215 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1216 &adev->gfx.mec.mec_fw_obj, 1217 &adev->gfx.mec.mec_fw_gpu_addr, 1218 (void **)&fw); 1219 if (r) { 1220 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1221 gfx_v9_0_mec_fini(adev); 1222 return r; 1223 } 1224 1225 memcpy(fw, fw_data, fw_size); 1226 1227 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1228 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1229 1230 return 0; 1231 } 1232 1233 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1234 { 1235 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1236 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1237 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1238 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1239 (SQ_IND_INDEX__FORCE_READ_MASK)); 1240 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1241 } 1242 1243 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1244 uint32_t wave, uint32_t thread, 1245 uint32_t regno, uint32_t num, uint32_t *out) 1246 { 1247 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1248 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1249 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1250 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1251 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1252 (SQ_IND_INDEX__FORCE_READ_MASK) | 1253 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1254 while (num--) 1255 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1256 } 1257 1258 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1259 { 1260 /* type 1 wave data */ 1261 dst[(*no_fields)++] = 1; 1262 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1263 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1267 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1270 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1271 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1272 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1273 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1274 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1276 } 1277 1278 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1279 uint32_t wave, uint32_t start, 1280 uint32_t size, uint32_t *dst) 1281 { 1282 wave_read_regs( 1283 adev, simd, wave, 0, 1284 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1285 } 1286 1287 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1288 uint32_t wave, uint32_t thread, 1289 uint32_t start, uint32_t size, 1290 uint32_t *dst) 1291 { 1292 wave_read_regs( 1293 adev, simd, wave, thread, 1294 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1295 } 1296 1297 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1298 u32 me, u32 pipe, u32 q) 1299 { 1300 soc15_grbm_select(adev, me, pipe, q, 0); 1301 } 1302 1303 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1304 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1305 .select_se_sh = &gfx_v9_0_select_se_sh, 1306 .read_wave_data = &gfx_v9_0_read_wave_data, 1307 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1308 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1309 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q 1310 }; 1311 1312 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1313 { 1314 u32 gb_addr_config; 1315 int err; 1316 1317 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1318 1319 switch (adev->asic_type) { 1320 case CHIP_VEGA10: 1321 adev->gfx.config.max_hw_contexts = 8; 1322 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1323 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1324 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1325 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1326 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1327 break; 1328 case CHIP_VEGA12: 1329 adev->gfx.config.max_hw_contexts = 8; 1330 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1331 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1332 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1333 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1334 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1335 DRM_INFO("fix gfx.config for vega12\n"); 1336 break; 1337 case CHIP_VEGA20: 1338 adev->gfx.config.max_hw_contexts = 8; 1339 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1340 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1341 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1342 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1343 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1344 gb_addr_config &= ~0xf3e777ff; 1345 gb_addr_config |= 0x22014042; 1346 /* check vbios table if gpu info is not available */ 1347 err = amdgpu_atomfirmware_get_gfx_info(adev); 1348 if (err) 1349 return err; 1350 break; 1351 case CHIP_RAVEN: 1352 adev->gfx.config.max_hw_contexts = 8; 1353 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1354 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1355 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1356 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1357 if (adev->rev_id >= 8) 1358 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 1359 else 1360 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1361 break; 1362 default: 1363 BUG(); 1364 break; 1365 } 1366 1367 adev->gfx.config.gb_addr_config = gb_addr_config; 1368 1369 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1370 REG_GET_FIELD( 1371 adev->gfx.config.gb_addr_config, 1372 GB_ADDR_CONFIG, 1373 NUM_PIPES); 1374 1375 adev->gfx.config.max_tile_pipes = 1376 adev->gfx.config.gb_addr_config_fields.num_pipes; 1377 1378 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1379 REG_GET_FIELD( 1380 adev->gfx.config.gb_addr_config, 1381 GB_ADDR_CONFIG, 1382 NUM_BANKS); 1383 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1384 REG_GET_FIELD( 1385 adev->gfx.config.gb_addr_config, 1386 GB_ADDR_CONFIG, 1387 MAX_COMPRESSED_FRAGS); 1388 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1389 REG_GET_FIELD( 1390 adev->gfx.config.gb_addr_config, 1391 GB_ADDR_CONFIG, 1392 NUM_RB_PER_SE); 1393 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1394 REG_GET_FIELD( 1395 adev->gfx.config.gb_addr_config, 1396 GB_ADDR_CONFIG, 1397 NUM_SHADER_ENGINES); 1398 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1399 REG_GET_FIELD( 1400 adev->gfx.config.gb_addr_config, 1401 GB_ADDR_CONFIG, 1402 PIPE_INTERLEAVE_SIZE)); 1403 1404 return 0; 1405 } 1406 1407 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1408 struct amdgpu_ngg_buf *ngg_buf, 1409 int size_se, 1410 int default_size_se) 1411 { 1412 int r; 1413 1414 if (size_se < 0) { 1415 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1416 return -EINVAL; 1417 } 1418 size_se = size_se ? size_se : default_size_se; 1419 1420 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1421 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1422 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1423 &ngg_buf->bo, 1424 &ngg_buf->gpu_addr, 1425 NULL); 1426 if (r) { 1427 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1428 return r; 1429 } 1430 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1431 1432 return r; 1433 } 1434 1435 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1436 { 1437 int i; 1438 1439 for (i = 0; i < NGG_BUF_MAX; i++) 1440 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1441 &adev->gfx.ngg.buf[i].gpu_addr, 1442 NULL); 1443 1444 memset(&adev->gfx.ngg.buf[0], 0, 1445 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1446 1447 adev->gfx.ngg.init = false; 1448 1449 return 0; 1450 } 1451 1452 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1453 { 1454 int r; 1455 1456 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1457 return 0; 1458 1459 /* GDS reserve memory: 64 bytes alignment */ 1460 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1461 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1462 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1463 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); 1464 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 1465 1466 /* Primitive Buffer */ 1467 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1468 amdgpu_prim_buf_per_se, 1469 64 * 1024); 1470 if (r) { 1471 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1472 goto err; 1473 } 1474 1475 /* Position Buffer */ 1476 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1477 amdgpu_pos_buf_per_se, 1478 256 * 1024); 1479 if (r) { 1480 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1481 goto err; 1482 } 1483 1484 /* Control Sideband */ 1485 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1486 amdgpu_cntl_sb_buf_per_se, 1487 256); 1488 if (r) { 1489 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1490 goto err; 1491 } 1492 1493 /* Parameter Cache, not created by default */ 1494 if (amdgpu_param_buf_per_se <= 0) 1495 goto out; 1496 1497 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1498 amdgpu_param_buf_per_se, 1499 512 * 1024); 1500 if (r) { 1501 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1502 goto err; 1503 } 1504 1505 out: 1506 adev->gfx.ngg.init = true; 1507 return 0; 1508 err: 1509 gfx_v9_0_ngg_fini(adev); 1510 return r; 1511 } 1512 1513 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1514 { 1515 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1516 int r; 1517 u32 data, base; 1518 1519 if (!amdgpu_ngg) 1520 return 0; 1521 1522 /* Program buffer size */ 1523 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, 1524 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); 1525 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, 1526 adev->gfx.ngg.buf[NGG_POS].size >> 8); 1527 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1528 1529 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, 1530 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); 1531 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, 1532 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); 1533 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1534 1535 /* Program buffer base address */ 1536 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1537 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1538 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1539 1540 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1541 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1542 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1543 1544 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1545 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1546 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1547 1548 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1549 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1550 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1551 1552 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1553 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1554 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1555 1556 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1557 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1558 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1559 1560 /* Clear GDS reserved memory */ 1561 r = amdgpu_ring_alloc(ring, 17); 1562 if (r) { 1563 DRM_ERROR("amdgpu: NGG failed to lock ring %s (%d).\n", 1564 ring->name, r); 1565 return r; 1566 } 1567 1568 gfx_v9_0_write_data_to_reg(ring, 0, false, 1569 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 1570 (adev->gds.mem.total_size + 1571 adev->gfx.ngg.gds_reserve_size)); 1572 1573 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1574 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1575 PACKET3_DMA_DATA_DST_SEL(1) | 1576 PACKET3_DMA_DATA_SRC_SEL(2))); 1577 amdgpu_ring_write(ring, 0); 1578 amdgpu_ring_write(ring, 0); 1579 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1580 amdgpu_ring_write(ring, 0); 1581 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 1582 adev->gfx.ngg.gds_reserve_size); 1583 1584 gfx_v9_0_write_data_to_reg(ring, 0, false, 1585 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); 1586 1587 amdgpu_ring_commit(ring); 1588 1589 return 0; 1590 } 1591 1592 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1593 int mec, int pipe, int queue) 1594 { 1595 int r; 1596 unsigned irq_type; 1597 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1598 1599 ring = &adev->gfx.compute_ring[ring_id]; 1600 1601 /* mec0 is me1 */ 1602 ring->me = mec + 1; 1603 ring->pipe = pipe; 1604 ring->queue = queue; 1605 1606 ring->ring_obj = NULL; 1607 ring->use_doorbell = true; 1608 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1609 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1610 + (ring_id * GFX9_MEC_HPD_SIZE); 1611 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1612 1613 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1614 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1615 + ring->pipe; 1616 1617 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1618 r = amdgpu_ring_init(adev, ring, 1024, 1619 &adev->gfx.eop_irq, irq_type); 1620 if (r) 1621 return r; 1622 1623 1624 return 0; 1625 } 1626 1627 static int gfx_v9_0_sw_init(void *handle) 1628 { 1629 int i, j, k, r, ring_id; 1630 struct amdgpu_ring *ring; 1631 struct amdgpu_kiq *kiq; 1632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1633 1634 switch (adev->asic_type) { 1635 case CHIP_VEGA10: 1636 case CHIP_VEGA12: 1637 case CHIP_VEGA20: 1638 case CHIP_RAVEN: 1639 adev->gfx.mec.num_mec = 2; 1640 break; 1641 default: 1642 adev->gfx.mec.num_mec = 1; 1643 break; 1644 } 1645 1646 adev->gfx.mec.num_pipe_per_mec = 4; 1647 adev->gfx.mec.num_queue_per_pipe = 8; 1648 1649 /* EOP Event */ 1650 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1651 if (r) 1652 return r; 1653 1654 /* Privileged reg */ 1655 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1656 &adev->gfx.priv_reg_irq); 1657 if (r) 1658 return r; 1659 1660 /* Privileged inst */ 1661 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1662 &adev->gfx.priv_inst_irq); 1663 if (r) 1664 return r; 1665 1666 /* ECC error */ 1667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 1668 &adev->gfx.cp_ecc_error_irq); 1669 if (r) 1670 return r; 1671 1672 /* FUE error */ 1673 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 1674 &adev->gfx.cp_ecc_error_irq); 1675 if (r) 1676 return r; 1677 1678 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1679 1680 gfx_v9_0_scratch_init(adev); 1681 1682 r = gfx_v9_0_init_microcode(adev); 1683 if (r) { 1684 DRM_ERROR("Failed to load gfx firmware!\n"); 1685 return r; 1686 } 1687 1688 r = adev->gfx.rlc.funcs->init(adev); 1689 if (r) { 1690 DRM_ERROR("Failed to init rlc BOs!\n"); 1691 return r; 1692 } 1693 1694 r = gfx_v9_0_mec_init(adev); 1695 if (r) { 1696 DRM_ERROR("Failed to init MEC BOs!\n"); 1697 return r; 1698 } 1699 1700 /* set up the gfx ring */ 1701 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1702 ring = &adev->gfx.gfx_ring[i]; 1703 ring->ring_obj = NULL; 1704 if (!i) 1705 sprintf(ring->name, "gfx"); 1706 else 1707 sprintf(ring->name, "gfx_%d", i); 1708 ring->use_doorbell = true; 1709 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1710 r = amdgpu_ring_init(adev, ring, 1024, 1711 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1712 if (r) 1713 return r; 1714 } 1715 1716 /* set up the compute queues - allocate horizontally across pipes */ 1717 ring_id = 0; 1718 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1719 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1720 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1721 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 1722 continue; 1723 1724 r = gfx_v9_0_compute_ring_init(adev, 1725 ring_id, 1726 i, k, j); 1727 if (r) 1728 return r; 1729 1730 ring_id++; 1731 } 1732 } 1733 } 1734 1735 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 1736 if (r) { 1737 DRM_ERROR("Failed to init KIQ BOs!\n"); 1738 return r; 1739 } 1740 1741 kiq = &adev->gfx.kiq; 1742 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1743 if (r) 1744 return r; 1745 1746 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1747 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 1748 if (r) 1749 return r; 1750 1751 adev->gfx.ce_ram_size = 0x8000; 1752 1753 r = gfx_v9_0_gpu_early_init(adev); 1754 if (r) 1755 return r; 1756 1757 r = gfx_v9_0_ngg_init(adev); 1758 if (r) 1759 return r; 1760 1761 return 0; 1762 } 1763 1764 1765 static int gfx_v9_0_sw_fini(void *handle) 1766 { 1767 int i; 1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1769 1770 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) && 1771 adev->gfx.ras_if) { 1772 struct ras_common_if *ras_if = adev->gfx.ras_if; 1773 struct ras_ih_if ih_info = { 1774 .head = *ras_if, 1775 }; 1776 1777 amdgpu_ras_debugfs_remove(adev, ras_if); 1778 amdgpu_ras_sysfs_remove(adev, ras_if); 1779 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1780 amdgpu_ras_feature_enable(adev, ras_if, 0); 1781 kfree(ras_if); 1782 } 1783 1784 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1785 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1786 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1787 1788 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1789 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1790 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1791 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1792 1793 amdgpu_gfx_compute_mqd_sw_fini(adev); 1794 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1795 amdgpu_gfx_kiq_fini(adev); 1796 1797 gfx_v9_0_mec_fini(adev); 1798 gfx_v9_0_ngg_fini(adev); 1799 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1800 &adev->gfx.rlc.clear_state_gpu_addr, 1801 (void **)&adev->gfx.rlc.cs_ptr); 1802 if (adev->asic_type == CHIP_RAVEN) { 1803 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1804 &adev->gfx.rlc.cp_table_gpu_addr, 1805 (void **)&adev->gfx.rlc.cp_table_ptr); 1806 } 1807 gfx_v9_0_free_microcode(adev); 1808 1809 return 0; 1810 } 1811 1812 1813 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1814 { 1815 /* TODO */ 1816 } 1817 1818 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1819 { 1820 u32 data; 1821 1822 if (instance == 0xffffffff) 1823 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1824 else 1825 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1826 1827 if (se_num == 0xffffffff) 1828 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1829 else 1830 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1831 1832 if (sh_num == 0xffffffff) 1833 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1834 else 1835 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1836 1837 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1838 } 1839 1840 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1841 { 1842 u32 data, mask; 1843 1844 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1845 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1846 1847 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1848 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1849 1850 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1851 adev->gfx.config.max_sh_per_se); 1852 1853 return (~data) & mask; 1854 } 1855 1856 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1857 { 1858 int i, j; 1859 u32 data; 1860 u32 active_rbs = 0; 1861 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1862 adev->gfx.config.max_sh_per_se; 1863 1864 mutex_lock(&adev->grbm_idx_mutex); 1865 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1866 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1867 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1868 data = gfx_v9_0_get_rb_active_bitmap(adev); 1869 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1870 rb_bitmap_width_per_sh); 1871 } 1872 } 1873 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1874 mutex_unlock(&adev->grbm_idx_mutex); 1875 1876 adev->gfx.config.backend_enable_mask = active_rbs; 1877 adev->gfx.config.num_rbs = hweight32(active_rbs); 1878 } 1879 1880 #define DEFAULT_SH_MEM_BASES (0x6000) 1881 #define FIRST_COMPUTE_VMID (8) 1882 #define LAST_COMPUTE_VMID (16) 1883 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1884 { 1885 int i; 1886 uint32_t sh_mem_config; 1887 uint32_t sh_mem_bases; 1888 1889 /* 1890 * Configure apertures: 1891 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1892 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1893 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1894 */ 1895 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1896 1897 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1898 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1899 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1900 1901 mutex_lock(&adev->srbm_mutex); 1902 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1903 soc15_grbm_select(adev, 0, 0, 0, i); 1904 /* CP and shaders */ 1905 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1906 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1907 } 1908 soc15_grbm_select(adev, 0, 0, 0, 0); 1909 mutex_unlock(&adev->srbm_mutex); 1910 } 1911 1912 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 1913 { 1914 u32 tmp; 1915 int i; 1916 1917 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1918 1919 gfx_v9_0_tiling_mode_table_init(adev); 1920 1921 gfx_v9_0_setup_rb(adev); 1922 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1923 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 1924 1925 /* XXX SH_MEM regs */ 1926 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1927 mutex_lock(&adev->srbm_mutex); 1928 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { 1929 soc15_grbm_select(adev, 0, 0, 0, i); 1930 /* CP and shaders */ 1931 if (i == 0) { 1932 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1933 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1934 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1935 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1936 } else { 1937 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1938 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1939 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1940 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1941 (adev->gmc.private_aperture_start >> 48)); 1942 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1943 (adev->gmc.shared_aperture_start >> 48)); 1944 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1945 } 1946 } 1947 soc15_grbm_select(adev, 0, 0, 0, 0); 1948 1949 mutex_unlock(&adev->srbm_mutex); 1950 1951 gfx_v9_0_init_compute_vmid(adev); 1952 1953 mutex_lock(&adev->grbm_idx_mutex); 1954 /* 1955 * making sure that the following register writes will be broadcasted 1956 * to all the shaders 1957 */ 1958 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1959 1960 WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, 1961 (adev->gfx.config.sc_prim_fifo_size_frontend << 1962 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1963 (adev->gfx.config.sc_prim_fifo_size_backend << 1964 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1965 (adev->gfx.config.sc_hiz_tile_fifo_size << 1966 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1967 (adev->gfx.config.sc_earlyz_tile_fifo_size << 1968 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 1969 mutex_unlock(&adev->grbm_idx_mutex); 1970 1971 } 1972 1973 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1974 { 1975 u32 i, j, k; 1976 u32 mask; 1977 1978 mutex_lock(&adev->grbm_idx_mutex); 1979 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1980 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1981 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1982 for (k = 0; k < adev->usec_timeout; k++) { 1983 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1984 break; 1985 udelay(1); 1986 } 1987 if (k == adev->usec_timeout) { 1988 gfx_v9_0_select_se_sh(adev, 0xffffffff, 1989 0xffffffff, 0xffffffff); 1990 mutex_unlock(&adev->grbm_idx_mutex); 1991 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1992 i, j); 1993 return; 1994 } 1995 } 1996 } 1997 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1998 mutex_unlock(&adev->grbm_idx_mutex); 1999 2000 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2001 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2002 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2003 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2004 for (k = 0; k < adev->usec_timeout; k++) { 2005 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2006 break; 2007 udelay(1); 2008 } 2009 } 2010 2011 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2012 bool enable) 2013 { 2014 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2015 2016 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2017 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2019 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2020 2021 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2022 } 2023 2024 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2025 { 2026 /* csib */ 2027 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2028 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2029 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2030 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2031 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2032 adev->gfx.rlc.clear_state_size); 2033 } 2034 2035 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2036 int indirect_offset, 2037 int list_size, 2038 int *unique_indirect_regs, 2039 int unique_indirect_reg_count, 2040 int *indirect_start_offsets, 2041 int *indirect_start_offsets_count, 2042 int max_start_offsets_count) 2043 { 2044 int idx; 2045 2046 for (; indirect_offset < list_size; indirect_offset++) { 2047 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2048 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2049 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2050 2051 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2052 indirect_offset += 2; 2053 2054 /* look for the matching indice */ 2055 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2056 if (unique_indirect_regs[idx] == 2057 register_list_format[indirect_offset] || 2058 !unique_indirect_regs[idx]) 2059 break; 2060 } 2061 2062 BUG_ON(idx >= unique_indirect_reg_count); 2063 2064 if (!unique_indirect_regs[idx]) 2065 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2066 2067 indirect_offset++; 2068 } 2069 } 2070 } 2071 2072 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2073 { 2074 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2075 int unique_indirect_reg_count = 0; 2076 2077 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2078 int indirect_start_offsets_count = 0; 2079 2080 int list_size = 0; 2081 int i = 0, j = 0; 2082 u32 tmp = 0; 2083 2084 u32 *register_list_format = 2085 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2086 if (!register_list_format) 2087 return -ENOMEM; 2088 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 2089 adev->gfx.rlc.reg_list_format_size_bytes); 2090 2091 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2092 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2093 gfx_v9_1_parse_ind_reg_list(register_list_format, 2094 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2095 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2096 unique_indirect_regs, 2097 unique_indirect_reg_count, 2098 indirect_start_offsets, 2099 &indirect_start_offsets_count, 2100 ARRAY_SIZE(indirect_start_offsets)); 2101 2102 /* enable auto inc in case it is disabled */ 2103 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2104 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2105 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2106 2107 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2108 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2109 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2110 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2111 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2112 adev->gfx.rlc.register_restore[i]); 2113 2114 /* load indirect register */ 2115 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2116 adev->gfx.rlc.reg_list_format_start); 2117 2118 /* direct register portion */ 2119 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2120 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2121 register_list_format[i]); 2122 2123 /* indirect register portion */ 2124 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2125 if (register_list_format[i] == 0xFFFFFFFF) { 2126 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2127 continue; 2128 } 2129 2130 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2131 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2132 2133 for (j = 0; j < unique_indirect_reg_count; j++) { 2134 if (register_list_format[i] == unique_indirect_regs[j]) { 2135 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2136 break; 2137 } 2138 } 2139 2140 BUG_ON(j >= unique_indirect_reg_count); 2141 2142 i++; 2143 } 2144 2145 /* set save/restore list size */ 2146 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2147 list_size = list_size >> 1; 2148 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2149 adev->gfx.rlc.reg_restore_list_size); 2150 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2151 2152 /* write the starting offsets to RLC scratch ram */ 2153 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2154 adev->gfx.rlc.starting_offsets_start); 2155 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2156 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2157 indirect_start_offsets[i]); 2158 2159 /* load unique indirect regs*/ 2160 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2161 if (unique_indirect_regs[i] != 0) { 2162 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2163 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2164 unique_indirect_regs[i] & 0x3FFFF); 2165 2166 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2167 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2168 unique_indirect_regs[i] >> 20); 2169 } 2170 } 2171 2172 kfree(register_list_format); 2173 return 0; 2174 } 2175 2176 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2177 { 2178 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2179 } 2180 2181 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2182 bool enable) 2183 { 2184 uint32_t data = 0; 2185 uint32_t default_data = 0; 2186 2187 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2188 if (enable == true) { 2189 /* enable GFXIP control over CGPG */ 2190 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2191 if(default_data != data) 2192 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2193 2194 /* update status */ 2195 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2196 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2197 if(default_data != data) 2198 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2199 } else { 2200 /* restore GFXIP control over GCPG */ 2201 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2202 if(default_data != data) 2203 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2204 } 2205 } 2206 2207 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2208 { 2209 uint32_t data = 0; 2210 2211 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2212 AMD_PG_SUPPORT_GFX_SMG | 2213 AMD_PG_SUPPORT_GFX_DMG)) { 2214 /* init IDLE_POLL_COUNT = 60 */ 2215 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2216 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2217 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2218 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2219 2220 /* init RLC PG Delay */ 2221 data = 0; 2222 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2223 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2224 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2225 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2226 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2227 2228 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2229 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2230 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2231 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2232 2233 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2234 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2235 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2236 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2237 2238 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2239 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2240 2241 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2242 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2243 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2244 2245 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2246 } 2247 } 2248 2249 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2250 bool enable) 2251 { 2252 uint32_t data = 0; 2253 uint32_t default_data = 0; 2254 2255 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2256 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2257 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2258 enable ? 1 : 0); 2259 if (default_data != data) 2260 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2261 } 2262 2263 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2264 bool enable) 2265 { 2266 uint32_t data = 0; 2267 uint32_t default_data = 0; 2268 2269 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2270 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2271 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2272 enable ? 1 : 0); 2273 if(default_data != data) 2274 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2275 } 2276 2277 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2278 bool enable) 2279 { 2280 uint32_t data = 0; 2281 uint32_t default_data = 0; 2282 2283 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2284 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2285 CP_PG_DISABLE, 2286 enable ? 0 : 1); 2287 if(default_data != data) 2288 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2289 } 2290 2291 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2292 bool enable) 2293 { 2294 uint32_t data, default_data; 2295 2296 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2297 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2298 GFX_POWER_GATING_ENABLE, 2299 enable ? 1 : 0); 2300 if(default_data != data) 2301 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2302 } 2303 2304 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2305 bool enable) 2306 { 2307 uint32_t data, default_data; 2308 2309 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2310 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2311 GFX_PIPELINE_PG_ENABLE, 2312 enable ? 1 : 0); 2313 if(default_data != data) 2314 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2315 2316 if (!enable) 2317 /* read any GFX register to wake up GFX */ 2318 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2319 } 2320 2321 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2322 bool enable) 2323 { 2324 uint32_t data, default_data; 2325 2326 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2327 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2328 STATIC_PER_CU_PG_ENABLE, 2329 enable ? 1 : 0); 2330 if(default_data != data) 2331 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2332 } 2333 2334 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2335 bool enable) 2336 { 2337 uint32_t data, default_data; 2338 2339 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2340 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2341 DYN_PER_CU_PG_ENABLE, 2342 enable ? 1 : 0); 2343 if(default_data != data) 2344 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2345 } 2346 2347 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2348 { 2349 gfx_v9_0_init_csb(adev); 2350 2351 /* 2352 * Rlc save restore list is workable since v2_1. 2353 * And it's needed by gfxoff feature. 2354 */ 2355 if (adev->gfx.rlc.is_rlc_v2_1) { 2356 gfx_v9_1_init_rlc_save_restore_list(adev); 2357 gfx_v9_0_enable_save_restore_machine(adev); 2358 } 2359 2360 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2361 AMD_PG_SUPPORT_GFX_SMG | 2362 AMD_PG_SUPPORT_GFX_DMG | 2363 AMD_PG_SUPPORT_CP | 2364 AMD_PG_SUPPORT_GDS | 2365 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2366 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2367 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2368 gfx_v9_0_init_gfx_power_gating(adev); 2369 } 2370 } 2371 2372 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2373 { 2374 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2375 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2376 gfx_v9_0_wait_for_rlc_serdes(adev); 2377 } 2378 2379 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2380 { 2381 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2382 udelay(50); 2383 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2384 udelay(50); 2385 } 2386 2387 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2388 { 2389 #ifdef AMDGPU_RLC_DEBUG_RETRY 2390 u32 rlc_ucode_ver; 2391 #endif 2392 2393 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2394 udelay(50); 2395 2396 /* carrizo do enable cp interrupt after cp inited */ 2397 if (!(adev->flags & AMD_IS_APU)) { 2398 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2399 udelay(50); 2400 } 2401 2402 #ifdef AMDGPU_RLC_DEBUG_RETRY 2403 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2404 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2405 if(rlc_ucode_ver == 0x108) { 2406 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2407 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2408 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2409 * default is 0x9C4 to create a 100us interval */ 2410 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2411 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2412 * to disable the page fault retry interrupts, default is 2413 * 0x100 (256) */ 2414 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2415 } 2416 #endif 2417 } 2418 2419 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2420 { 2421 const struct rlc_firmware_header_v2_0 *hdr; 2422 const __le32 *fw_data; 2423 unsigned i, fw_size; 2424 2425 if (!adev->gfx.rlc_fw) 2426 return -EINVAL; 2427 2428 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2429 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2430 2431 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2432 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2433 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2434 2435 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2436 RLCG_UCODE_LOADING_START_ADDRESS); 2437 for (i = 0; i < fw_size; i++) 2438 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2439 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2440 2441 return 0; 2442 } 2443 2444 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2445 { 2446 int r; 2447 2448 if (amdgpu_sriov_vf(adev)) { 2449 gfx_v9_0_init_csb(adev); 2450 return 0; 2451 } 2452 2453 adev->gfx.rlc.funcs->stop(adev); 2454 2455 /* disable CG */ 2456 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2457 2458 gfx_v9_0_init_pg(adev); 2459 2460 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2461 /* legacy rlc firmware loading */ 2462 r = gfx_v9_0_rlc_load_microcode(adev); 2463 if (r) 2464 return r; 2465 } 2466 2467 switch (adev->asic_type) { 2468 case CHIP_RAVEN: 2469 if (amdgpu_lbpw == 0) 2470 gfx_v9_0_enable_lbpw(adev, false); 2471 else 2472 gfx_v9_0_enable_lbpw(adev, true); 2473 break; 2474 case CHIP_VEGA20: 2475 if (amdgpu_lbpw > 0) 2476 gfx_v9_0_enable_lbpw(adev, true); 2477 else 2478 gfx_v9_0_enable_lbpw(adev, false); 2479 break; 2480 default: 2481 break; 2482 } 2483 2484 adev->gfx.rlc.funcs->start(adev); 2485 2486 return 0; 2487 } 2488 2489 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2490 { 2491 int i; 2492 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2493 2494 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2495 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2496 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2497 if (!enable) { 2498 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2499 adev->gfx.gfx_ring[i].sched.ready = false; 2500 } 2501 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2502 udelay(50); 2503 } 2504 2505 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2506 { 2507 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2508 const struct gfx_firmware_header_v1_0 *ce_hdr; 2509 const struct gfx_firmware_header_v1_0 *me_hdr; 2510 const __le32 *fw_data; 2511 unsigned i, fw_size; 2512 2513 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2514 return -EINVAL; 2515 2516 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2517 adev->gfx.pfp_fw->data; 2518 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2519 adev->gfx.ce_fw->data; 2520 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2521 adev->gfx.me_fw->data; 2522 2523 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2524 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2525 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2526 2527 gfx_v9_0_cp_gfx_enable(adev, false); 2528 2529 /* PFP */ 2530 fw_data = (const __le32 *) 2531 (adev->gfx.pfp_fw->data + 2532 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2533 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2534 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2535 for (i = 0; i < fw_size; i++) 2536 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2537 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2538 2539 /* CE */ 2540 fw_data = (const __le32 *) 2541 (adev->gfx.ce_fw->data + 2542 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2543 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2544 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2545 for (i = 0; i < fw_size; i++) 2546 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2547 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2548 2549 /* ME */ 2550 fw_data = (const __le32 *) 2551 (adev->gfx.me_fw->data + 2552 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2553 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2554 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2555 for (i = 0; i < fw_size; i++) 2556 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2557 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2558 2559 return 0; 2560 } 2561 2562 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2563 { 2564 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2565 const struct cs_section_def *sect = NULL; 2566 const struct cs_extent_def *ext = NULL; 2567 int r, i, tmp; 2568 2569 /* init the CP */ 2570 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2571 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2572 2573 gfx_v9_0_cp_gfx_enable(adev, true); 2574 2575 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 2576 if (r) { 2577 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2578 return r; 2579 } 2580 2581 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2582 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2583 2584 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2585 amdgpu_ring_write(ring, 0x80000000); 2586 amdgpu_ring_write(ring, 0x80000000); 2587 2588 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2589 for (ext = sect->section; ext->extent != NULL; ++ext) { 2590 if (sect->id == SECT_CONTEXT) { 2591 amdgpu_ring_write(ring, 2592 PACKET3(PACKET3_SET_CONTEXT_REG, 2593 ext->reg_count)); 2594 amdgpu_ring_write(ring, 2595 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2596 for (i = 0; i < ext->reg_count; i++) 2597 amdgpu_ring_write(ring, ext->extent[i]); 2598 } 2599 } 2600 } 2601 2602 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2603 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2604 2605 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2606 amdgpu_ring_write(ring, 0); 2607 2608 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2609 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2610 amdgpu_ring_write(ring, 0x8000); 2611 amdgpu_ring_write(ring, 0x8000); 2612 2613 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 2614 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 2615 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 2616 amdgpu_ring_write(ring, tmp); 2617 amdgpu_ring_write(ring, 0); 2618 2619 amdgpu_ring_commit(ring); 2620 2621 return 0; 2622 } 2623 2624 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2625 { 2626 struct amdgpu_ring *ring; 2627 u32 tmp; 2628 u32 rb_bufsz; 2629 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2630 2631 /* Set the write pointer delay */ 2632 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2633 2634 /* set the RB to use vmid 0 */ 2635 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2636 2637 /* Set ring buffer size */ 2638 ring = &adev->gfx.gfx_ring[0]; 2639 rb_bufsz = order_base_2(ring->ring_size / 8); 2640 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2641 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2642 #ifdef __BIG_ENDIAN 2643 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2644 #endif 2645 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2646 2647 /* Initialize the ring buffer's write pointers */ 2648 ring->wptr = 0; 2649 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2650 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2651 2652 /* set the wb address wether it's enabled or not */ 2653 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2654 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2655 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2656 2657 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2658 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2659 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2660 2661 mdelay(1); 2662 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2663 2664 rb_addr = ring->gpu_addr >> 8; 2665 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2666 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2667 2668 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2669 if (ring->use_doorbell) { 2670 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2671 DOORBELL_OFFSET, ring->doorbell_index); 2672 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2673 DOORBELL_EN, 1); 2674 } else { 2675 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2676 } 2677 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2678 2679 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2680 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2681 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2682 2683 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2684 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2685 2686 2687 /* start the ring */ 2688 gfx_v9_0_cp_gfx_start(adev); 2689 ring->sched.ready = true; 2690 2691 return 0; 2692 } 2693 2694 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2695 { 2696 int i; 2697 2698 if (enable) { 2699 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2700 } else { 2701 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2702 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2703 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2704 adev->gfx.compute_ring[i].sched.ready = false; 2705 adev->gfx.kiq.ring.sched.ready = false; 2706 } 2707 udelay(50); 2708 } 2709 2710 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2711 { 2712 const struct gfx_firmware_header_v1_0 *mec_hdr; 2713 const __le32 *fw_data; 2714 unsigned i; 2715 u32 tmp; 2716 2717 if (!adev->gfx.mec_fw) 2718 return -EINVAL; 2719 2720 gfx_v9_0_cp_compute_enable(adev, false); 2721 2722 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2723 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2724 2725 fw_data = (const __le32 *) 2726 (adev->gfx.mec_fw->data + 2727 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2728 tmp = 0; 2729 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2730 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2731 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2732 2733 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2734 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2735 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2736 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2737 2738 /* MEC1 */ 2739 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2740 mec_hdr->jt_offset); 2741 for (i = 0; i < mec_hdr->jt_size; i++) 2742 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2743 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2744 2745 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2746 adev->gfx.mec_fw_version); 2747 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2748 2749 return 0; 2750 } 2751 2752 /* KIQ functions */ 2753 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2754 { 2755 uint32_t tmp; 2756 struct amdgpu_device *adev = ring->adev; 2757 2758 /* tell RLC which is KIQ queue */ 2759 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2760 tmp &= 0xffffff00; 2761 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2762 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2763 tmp |= 0x80; 2764 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2765 } 2766 2767 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) 2768 { 2769 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 2770 uint64_t queue_mask = 0; 2771 int r, i; 2772 2773 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 2774 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 2775 continue; 2776 2777 /* This situation may be hit in the future if a new HW 2778 * generation exposes more than 64 queues. If so, the 2779 * definition of queue_mask needs updating */ 2780 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 2781 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 2782 break; 2783 } 2784 2785 queue_mask |= (1ull << i); 2786 } 2787 2788 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8); 2789 if (r) { 2790 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2791 return r; 2792 } 2793 2794 /* set resources */ 2795 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2796 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2797 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2798 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 2799 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 2800 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 2801 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 2802 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 2803 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 2804 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2805 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2806 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2807 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2808 2809 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2810 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2811 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2812 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2813 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2814 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2815 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2816 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2817 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2818 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 2819 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2820 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2821 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2822 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2823 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2824 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2825 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2826 } 2827 2828 r = amdgpu_ring_test_helper(kiq_ring); 2829 if (r) 2830 DRM_ERROR("KCQ enable failed\n"); 2831 2832 return r; 2833 } 2834 2835 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2836 { 2837 struct amdgpu_device *adev = ring->adev; 2838 struct v9_mqd *mqd = ring->mqd_ptr; 2839 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2840 uint32_t tmp; 2841 2842 mqd->header = 0xC0310800; 2843 mqd->compute_pipelinestat_enable = 0x00000001; 2844 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2845 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2846 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2847 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2848 mqd->compute_misc_reserved = 0x00000003; 2849 2850 mqd->dynamic_cu_mask_addr_lo = 2851 lower_32_bits(ring->mqd_gpu_addr 2852 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2853 mqd->dynamic_cu_mask_addr_hi = 2854 upper_32_bits(ring->mqd_gpu_addr 2855 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2856 2857 eop_base_addr = ring->eop_gpu_addr >> 8; 2858 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2859 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2860 2861 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2862 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2863 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2864 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2865 2866 mqd->cp_hqd_eop_control = tmp; 2867 2868 /* enable doorbell? */ 2869 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2870 2871 if (ring->use_doorbell) { 2872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2873 DOORBELL_OFFSET, ring->doorbell_index); 2874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2875 DOORBELL_EN, 1); 2876 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2877 DOORBELL_SOURCE, 0); 2878 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2879 DOORBELL_HIT, 0); 2880 } else { 2881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2882 DOORBELL_EN, 0); 2883 } 2884 2885 mqd->cp_hqd_pq_doorbell_control = tmp; 2886 2887 /* disable the queue if it's active */ 2888 ring->wptr = 0; 2889 mqd->cp_hqd_dequeue_request = 0; 2890 mqd->cp_hqd_pq_rptr = 0; 2891 mqd->cp_hqd_pq_wptr_lo = 0; 2892 mqd->cp_hqd_pq_wptr_hi = 0; 2893 2894 /* set the pointer to the MQD */ 2895 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2896 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2897 2898 /* set MQD vmid to 0 */ 2899 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2900 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2901 mqd->cp_mqd_control = tmp; 2902 2903 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2904 hqd_gpu_addr = ring->gpu_addr >> 8; 2905 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2906 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2907 2908 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2909 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2910 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2911 (order_base_2(ring->ring_size / 4) - 1)); 2912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2913 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2914 #ifdef __BIG_ENDIAN 2915 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2916 #endif 2917 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2918 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2919 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2920 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2921 mqd->cp_hqd_pq_control = tmp; 2922 2923 /* set the wb address whether it's enabled or not */ 2924 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2925 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2926 mqd->cp_hqd_pq_rptr_report_addr_hi = 2927 upper_32_bits(wb_gpu_addr) & 0xffff; 2928 2929 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2930 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2931 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2932 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2933 2934 tmp = 0; 2935 /* enable the doorbell if requested */ 2936 if (ring->use_doorbell) { 2937 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2938 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2939 DOORBELL_OFFSET, ring->doorbell_index); 2940 2941 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2942 DOORBELL_EN, 1); 2943 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2944 DOORBELL_SOURCE, 0); 2945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2946 DOORBELL_HIT, 0); 2947 } 2948 2949 mqd->cp_hqd_pq_doorbell_control = tmp; 2950 2951 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2952 ring->wptr = 0; 2953 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2954 2955 /* set the vmid for the queue */ 2956 mqd->cp_hqd_vmid = 0; 2957 2958 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2959 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2960 mqd->cp_hqd_persistent_state = tmp; 2961 2962 /* set MIN_IB_AVAIL_SIZE */ 2963 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2964 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2965 mqd->cp_hqd_ib_control = tmp; 2966 2967 /* activate the queue */ 2968 mqd->cp_hqd_active = 1; 2969 2970 return 0; 2971 } 2972 2973 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2974 { 2975 struct amdgpu_device *adev = ring->adev; 2976 struct v9_mqd *mqd = ring->mqd_ptr; 2977 int j; 2978 2979 /* disable wptr polling */ 2980 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2981 2982 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2983 mqd->cp_hqd_eop_base_addr_lo); 2984 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2985 mqd->cp_hqd_eop_base_addr_hi); 2986 2987 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2988 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2989 mqd->cp_hqd_eop_control); 2990 2991 /* enable doorbell? */ 2992 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2993 mqd->cp_hqd_pq_doorbell_control); 2994 2995 /* disable the queue if it's active */ 2996 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2997 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2998 for (j = 0; j < adev->usec_timeout; j++) { 2999 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3000 break; 3001 udelay(1); 3002 } 3003 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3004 mqd->cp_hqd_dequeue_request); 3005 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3006 mqd->cp_hqd_pq_rptr); 3007 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3008 mqd->cp_hqd_pq_wptr_lo); 3009 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3010 mqd->cp_hqd_pq_wptr_hi); 3011 } 3012 3013 /* set the pointer to the MQD */ 3014 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3015 mqd->cp_mqd_base_addr_lo); 3016 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3017 mqd->cp_mqd_base_addr_hi); 3018 3019 /* set MQD vmid to 0 */ 3020 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3021 mqd->cp_mqd_control); 3022 3023 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3024 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3025 mqd->cp_hqd_pq_base_lo); 3026 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3027 mqd->cp_hqd_pq_base_hi); 3028 3029 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3030 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3031 mqd->cp_hqd_pq_control); 3032 3033 /* set the wb address whether it's enabled or not */ 3034 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3035 mqd->cp_hqd_pq_rptr_report_addr_lo); 3036 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3037 mqd->cp_hqd_pq_rptr_report_addr_hi); 3038 3039 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3040 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3041 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3042 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3043 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3044 3045 /* enable the doorbell if requested */ 3046 if (ring->use_doorbell) { 3047 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3048 (adev->doorbell_index.kiq * 2) << 2); 3049 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3050 (adev->doorbell_index.userqueue_end * 2) << 2); 3051 } 3052 3053 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3054 mqd->cp_hqd_pq_doorbell_control); 3055 3056 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3057 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3058 mqd->cp_hqd_pq_wptr_lo); 3059 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3060 mqd->cp_hqd_pq_wptr_hi); 3061 3062 /* set the vmid for the queue */ 3063 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3064 3065 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3066 mqd->cp_hqd_persistent_state); 3067 3068 /* activate the queue */ 3069 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3070 mqd->cp_hqd_active); 3071 3072 if (ring->use_doorbell) 3073 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3074 3075 return 0; 3076 } 3077 3078 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3079 { 3080 struct amdgpu_device *adev = ring->adev; 3081 int j; 3082 3083 /* disable the queue if it's active */ 3084 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3085 3086 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3087 3088 for (j = 0; j < adev->usec_timeout; j++) { 3089 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3090 break; 3091 udelay(1); 3092 } 3093 3094 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3095 DRM_DEBUG("KIQ dequeue request failed.\n"); 3096 3097 /* Manual disable if dequeue request times out */ 3098 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 3099 } 3100 3101 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3102 0); 3103 } 3104 3105 WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3106 WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3107 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3108 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3109 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3110 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3111 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3112 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3113 3114 return 0; 3115 } 3116 3117 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3118 { 3119 struct amdgpu_device *adev = ring->adev; 3120 struct v9_mqd *mqd = ring->mqd_ptr; 3121 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3122 3123 gfx_v9_0_kiq_setting(ring); 3124 3125 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3126 /* reset MQD to a clean status */ 3127 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3128 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3129 3130 /* reset ring buffer */ 3131 ring->wptr = 0; 3132 amdgpu_ring_clear_ring(ring); 3133 3134 mutex_lock(&adev->srbm_mutex); 3135 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3136 gfx_v9_0_kiq_init_register(ring); 3137 soc15_grbm_select(adev, 0, 0, 0, 0); 3138 mutex_unlock(&adev->srbm_mutex); 3139 } else { 3140 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3141 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3142 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3143 mutex_lock(&adev->srbm_mutex); 3144 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3145 gfx_v9_0_mqd_init(ring); 3146 gfx_v9_0_kiq_init_register(ring); 3147 soc15_grbm_select(adev, 0, 0, 0, 0); 3148 mutex_unlock(&adev->srbm_mutex); 3149 3150 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3151 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3152 } 3153 3154 return 0; 3155 } 3156 3157 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3158 { 3159 struct amdgpu_device *adev = ring->adev; 3160 struct v9_mqd *mqd = ring->mqd_ptr; 3161 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3162 3163 if (!adev->in_gpu_reset && !adev->in_suspend) { 3164 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3165 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3166 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3167 mutex_lock(&adev->srbm_mutex); 3168 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3169 gfx_v9_0_mqd_init(ring); 3170 soc15_grbm_select(adev, 0, 0, 0, 0); 3171 mutex_unlock(&adev->srbm_mutex); 3172 3173 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3174 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3175 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3176 /* reset MQD to a clean status */ 3177 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3178 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3179 3180 /* reset ring buffer */ 3181 ring->wptr = 0; 3182 amdgpu_ring_clear_ring(ring); 3183 } else { 3184 amdgpu_ring_clear_ring(ring); 3185 } 3186 3187 return 0; 3188 } 3189 3190 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3191 { 3192 struct amdgpu_ring *ring; 3193 int r; 3194 3195 ring = &adev->gfx.kiq.ring; 3196 3197 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3198 if (unlikely(r != 0)) 3199 return r; 3200 3201 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3202 if (unlikely(r != 0)) 3203 return r; 3204 3205 gfx_v9_0_kiq_init_queue(ring); 3206 amdgpu_bo_kunmap(ring->mqd_obj); 3207 ring->mqd_ptr = NULL; 3208 amdgpu_bo_unreserve(ring->mqd_obj); 3209 ring->sched.ready = true; 3210 return 0; 3211 } 3212 3213 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3214 { 3215 struct amdgpu_ring *ring = NULL; 3216 int r = 0, i; 3217 3218 gfx_v9_0_cp_compute_enable(adev, true); 3219 3220 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3221 ring = &adev->gfx.compute_ring[i]; 3222 3223 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3224 if (unlikely(r != 0)) 3225 goto done; 3226 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3227 if (!r) { 3228 r = gfx_v9_0_kcq_init_queue(ring); 3229 amdgpu_bo_kunmap(ring->mqd_obj); 3230 ring->mqd_ptr = NULL; 3231 } 3232 amdgpu_bo_unreserve(ring->mqd_obj); 3233 if (r) 3234 goto done; 3235 } 3236 3237 r = gfx_v9_0_kiq_kcq_enable(adev); 3238 done: 3239 return r; 3240 } 3241 3242 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3243 { 3244 int r, i; 3245 struct amdgpu_ring *ring; 3246 3247 if (!(adev->flags & AMD_IS_APU)) 3248 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3249 3250 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3251 /* legacy firmware loading */ 3252 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3253 if (r) 3254 return r; 3255 3256 r = gfx_v9_0_cp_compute_load_microcode(adev); 3257 if (r) 3258 return r; 3259 } 3260 3261 r = gfx_v9_0_kiq_resume(adev); 3262 if (r) 3263 return r; 3264 3265 r = gfx_v9_0_cp_gfx_resume(adev); 3266 if (r) 3267 return r; 3268 3269 r = gfx_v9_0_kcq_resume(adev); 3270 if (r) 3271 return r; 3272 3273 ring = &adev->gfx.gfx_ring[0]; 3274 r = amdgpu_ring_test_helper(ring); 3275 if (r) 3276 return r; 3277 3278 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3279 ring = &adev->gfx.compute_ring[i]; 3280 amdgpu_ring_test_helper(ring); 3281 } 3282 3283 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3284 3285 return 0; 3286 } 3287 3288 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3289 { 3290 gfx_v9_0_cp_gfx_enable(adev, enable); 3291 gfx_v9_0_cp_compute_enable(adev, enable); 3292 } 3293 3294 static int gfx_v9_0_hw_init(void *handle) 3295 { 3296 int r; 3297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3298 3299 gfx_v9_0_init_golden_registers(adev); 3300 3301 gfx_v9_0_constants_init(adev); 3302 3303 r = gfx_v9_0_csb_vram_pin(adev); 3304 if (r) 3305 return r; 3306 3307 r = adev->gfx.rlc.funcs->resume(adev); 3308 if (r) 3309 return r; 3310 3311 r = gfx_v9_0_cp_resume(adev); 3312 if (r) 3313 return r; 3314 3315 r = gfx_v9_0_ngg_en(adev); 3316 if (r) 3317 return r; 3318 3319 return r; 3320 } 3321 3322 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev) 3323 { 3324 int r, i; 3325 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3326 3327 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); 3328 if (r) 3329 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3330 3331 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3332 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3333 3334 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3335 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3336 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 3337 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3338 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 3339 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3340 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3341 amdgpu_ring_write(kiq_ring, 0); 3342 amdgpu_ring_write(kiq_ring, 0); 3343 amdgpu_ring_write(kiq_ring, 0); 3344 } 3345 r = amdgpu_ring_test_helper(kiq_ring); 3346 if (r) 3347 DRM_ERROR("KCQ disable failed\n"); 3348 3349 return r; 3350 } 3351 3352 static int gfx_v9_0_hw_fini(void *handle) 3353 { 3354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3355 3356 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3357 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3358 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3359 3360 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3361 gfx_v9_0_kcq_disable(adev); 3362 3363 if (amdgpu_sriov_vf(adev)) { 3364 gfx_v9_0_cp_gfx_enable(adev, false); 3365 /* must disable polling for SRIOV when hw finished, otherwise 3366 * CPC engine may still keep fetching WB address which is already 3367 * invalid after sw finished and trigger DMAR reading error in 3368 * hypervisor side. 3369 */ 3370 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3371 return 0; 3372 } 3373 3374 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3375 * otherwise KIQ is hanging when binding back 3376 */ 3377 if (!adev->in_gpu_reset && !adev->in_suspend) { 3378 mutex_lock(&adev->srbm_mutex); 3379 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3380 adev->gfx.kiq.ring.pipe, 3381 adev->gfx.kiq.ring.queue, 0); 3382 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3383 soc15_grbm_select(adev, 0, 0, 0, 0); 3384 mutex_unlock(&adev->srbm_mutex); 3385 } 3386 3387 gfx_v9_0_cp_enable(adev, false); 3388 adev->gfx.rlc.funcs->stop(adev); 3389 3390 gfx_v9_0_csb_vram_unpin(adev); 3391 3392 return 0; 3393 } 3394 3395 static int gfx_v9_0_suspend(void *handle) 3396 { 3397 return gfx_v9_0_hw_fini(handle); 3398 } 3399 3400 static int gfx_v9_0_resume(void *handle) 3401 { 3402 return gfx_v9_0_hw_init(handle); 3403 } 3404 3405 static bool gfx_v9_0_is_idle(void *handle) 3406 { 3407 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3408 3409 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3410 GRBM_STATUS, GUI_ACTIVE)) 3411 return false; 3412 else 3413 return true; 3414 } 3415 3416 static int gfx_v9_0_wait_for_idle(void *handle) 3417 { 3418 unsigned i; 3419 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3420 3421 for (i = 0; i < adev->usec_timeout; i++) { 3422 if (gfx_v9_0_is_idle(handle)) 3423 return 0; 3424 udelay(1); 3425 } 3426 return -ETIMEDOUT; 3427 } 3428 3429 static int gfx_v9_0_soft_reset(void *handle) 3430 { 3431 u32 grbm_soft_reset = 0; 3432 u32 tmp; 3433 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3434 3435 /* GRBM_STATUS */ 3436 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3437 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3438 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3439 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3440 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3441 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3442 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3443 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3444 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3445 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3446 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3447 } 3448 3449 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3450 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3451 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3452 } 3453 3454 /* GRBM_STATUS2 */ 3455 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3456 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3457 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3458 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3459 3460 3461 if (grbm_soft_reset) { 3462 /* stop the rlc */ 3463 adev->gfx.rlc.funcs->stop(adev); 3464 3465 /* Disable GFX parsing/prefetching */ 3466 gfx_v9_0_cp_gfx_enable(adev, false); 3467 3468 /* Disable MEC parsing/prefetching */ 3469 gfx_v9_0_cp_compute_enable(adev, false); 3470 3471 if (grbm_soft_reset) { 3472 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3473 tmp |= grbm_soft_reset; 3474 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3475 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3476 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3477 3478 udelay(50); 3479 3480 tmp &= ~grbm_soft_reset; 3481 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3482 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3483 } 3484 3485 /* Wait a little for things to settle down */ 3486 udelay(50); 3487 } 3488 return 0; 3489 } 3490 3491 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3492 { 3493 uint64_t clock; 3494 3495 mutex_lock(&adev->gfx.gpu_clock_mutex); 3496 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3497 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3498 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3499 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3500 return clock; 3501 } 3502 3503 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3504 uint32_t vmid, 3505 uint32_t gds_base, uint32_t gds_size, 3506 uint32_t gws_base, uint32_t gws_size, 3507 uint32_t oa_base, uint32_t oa_size) 3508 { 3509 struct amdgpu_device *adev = ring->adev; 3510 3511 /* GDS Base */ 3512 gfx_v9_0_write_data_to_reg(ring, 0, false, 3513 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3514 gds_base); 3515 3516 /* GDS Size */ 3517 gfx_v9_0_write_data_to_reg(ring, 0, false, 3518 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3519 gds_size); 3520 3521 /* GWS */ 3522 gfx_v9_0_write_data_to_reg(ring, 0, false, 3523 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3524 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3525 3526 /* OA */ 3527 gfx_v9_0_write_data_to_reg(ring, 0, false, 3528 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3529 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3530 } 3531 3532 static int gfx_v9_0_early_init(void *handle) 3533 { 3534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3535 3536 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3537 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3538 gfx_v9_0_set_ring_funcs(adev); 3539 gfx_v9_0_set_irq_funcs(adev); 3540 gfx_v9_0_set_gds_init(adev); 3541 gfx_v9_0_set_rlc_funcs(adev); 3542 3543 return 0; 3544 } 3545 3546 static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 3547 struct amdgpu_iv_entry *entry); 3548 3549 static int gfx_v9_0_ecc_late_init(void *handle) 3550 { 3551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3552 struct ras_common_if **ras_if = &adev->gfx.ras_if; 3553 struct ras_ih_if ih_info = { 3554 .cb = gfx_v9_0_process_ras_data_cb, 3555 }; 3556 struct ras_fs_if fs_info = { 3557 .sysfs_name = "gfx_err_count", 3558 .debugfs_name = "gfx_err_inject", 3559 }; 3560 struct ras_common_if ras_block = { 3561 .block = AMDGPU_RAS_BLOCK__GFX, 3562 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3563 .sub_block_index = 0, 3564 .name = "gfx", 3565 }; 3566 int r; 3567 3568 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { 3569 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 3570 return 0; 3571 } 3572 3573 if (*ras_if) 3574 goto resume; 3575 3576 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 3577 if (!*ras_if) 3578 return -ENOMEM; 3579 3580 **ras_if = ras_block; 3581 3582 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 3583 if (r) 3584 goto feature; 3585 3586 ih_info.head = **ras_if; 3587 fs_info.head = **ras_if; 3588 3589 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 3590 if (r) 3591 goto interrupt; 3592 3593 r = amdgpu_ras_debugfs_create(adev, &fs_info); 3594 if (r) 3595 goto debugfs; 3596 3597 r = amdgpu_ras_sysfs_create(adev, &fs_info); 3598 if (r) 3599 goto sysfs; 3600 resume: 3601 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 3602 if (r) 3603 goto irq; 3604 3605 return 0; 3606 irq: 3607 amdgpu_ras_sysfs_remove(adev, *ras_if); 3608 sysfs: 3609 amdgpu_ras_debugfs_remove(adev, *ras_if); 3610 debugfs: 3611 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 3612 interrupt: 3613 amdgpu_ras_feature_enable(adev, *ras_if, 0); 3614 feature: 3615 kfree(*ras_if); 3616 *ras_if = NULL; 3617 return -EINVAL; 3618 } 3619 3620 static int gfx_v9_0_late_init(void *handle) 3621 { 3622 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3623 int r; 3624 3625 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3626 if (r) 3627 return r; 3628 3629 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3630 if (r) 3631 return r; 3632 3633 r = gfx_v9_0_ecc_late_init(handle); 3634 if (r) 3635 return r; 3636 3637 return 0; 3638 } 3639 3640 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 3641 { 3642 uint32_t rlc_setting; 3643 3644 /* if RLC is not enabled, do nothing */ 3645 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3646 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3647 return false; 3648 3649 return true; 3650 } 3651 3652 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 3653 { 3654 uint32_t data; 3655 unsigned i; 3656 3657 data = RLC_SAFE_MODE__CMD_MASK; 3658 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3659 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3660 3661 /* wait for RLC_SAFE_MODE */ 3662 for (i = 0; i < adev->usec_timeout; i++) { 3663 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3664 break; 3665 udelay(1); 3666 } 3667 } 3668 3669 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 3670 { 3671 uint32_t data; 3672 3673 data = RLC_SAFE_MODE__CMD_MASK; 3674 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3675 } 3676 3677 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3678 bool enable) 3679 { 3680 amdgpu_gfx_rlc_enter_safe_mode(adev); 3681 3682 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3683 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3684 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3685 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3686 } else { 3687 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3688 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3689 } 3690 3691 amdgpu_gfx_rlc_exit_safe_mode(adev); 3692 } 3693 3694 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3695 bool enable) 3696 { 3697 /* TODO: double check if we need to perform under safe mode */ 3698 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3699 3700 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3701 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3702 else 3703 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3704 3705 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3706 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3707 else 3708 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3709 3710 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3711 } 3712 3713 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3714 bool enable) 3715 { 3716 uint32_t data, def; 3717 3718 amdgpu_gfx_rlc_enter_safe_mode(adev); 3719 3720 /* It is disabled by HW by default */ 3721 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3722 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3723 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3724 3725 if (adev->asic_type != CHIP_VEGA12) 3726 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3727 3728 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3729 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3730 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3731 3732 /* only for Vega10 & Raven1 */ 3733 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3734 3735 if (def != data) 3736 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3737 3738 /* MGLS is a global flag to control all MGLS in GFX */ 3739 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3740 /* 2 - RLC memory Light sleep */ 3741 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3742 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3743 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3744 if (def != data) 3745 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3746 } 3747 /* 3 - CP memory Light sleep */ 3748 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3749 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3750 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3751 if (def != data) 3752 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3753 } 3754 } 3755 } else { 3756 /* 1 - MGCG_OVERRIDE */ 3757 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3758 3759 if (adev->asic_type != CHIP_VEGA12) 3760 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3761 3762 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3763 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3764 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3765 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3766 3767 if (def != data) 3768 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3769 3770 /* 2 - disable MGLS in RLC */ 3771 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3772 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3773 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3774 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3775 } 3776 3777 /* 3 - disable MGLS in CP */ 3778 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3779 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3780 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3781 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3782 } 3783 } 3784 3785 amdgpu_gfx_rlc_exit_safe_mode(adev); 3786 } 3787 3788 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3789 bool enable) 3790 { 3791 uint32_t data, def; 3792 3793 amdgpu_gfx_rlc_enter_safe_mode(adev); 3794 3795 /* Enable 3D CGCG/CGLS */ 3796 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3797 /* write cmd to clear cgcg/cgls ov */ 3798 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3799 /* unset CGCG override */ 3800 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3801 /* update CGCG and CGLS override bits */ 3802 if (def != data) 3803 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3804 3805 /* enable 3Dcgcg FSM(0x0000363f) */ 3806 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3807 3808 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3809 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3810 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3811 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3812 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3813 if (def != data) 3814 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3815 3816 /* set IDLE_POLL_COUNT(0x00900100) */ 3817 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3818 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3819 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3820 if (def != data) 3821 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3822 } else { 3823 /* Disable CGCG/CGLS */ 3824 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3825 /* disable cgcg, cgls should be disabled */ 3826 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3827 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3828 /* disable cgcg and cgls in FSM */ 3829 if (def != data) 3830 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3831 } 3832 3833 amdgpu_gfx_rlc_exit_safe_mode(adev); 3834 } 3835 3836 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3837 bool enable) 3838 { 3839 uint32_t def, data; 3840 3841 amdgpu_gfx_rlc_enter_safe_mode(adev); 3842 3843 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3844 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3845 /* unset CGCG override */ 3846 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3847 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3848 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3849 else 3850 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3851 /* update CGCG and CGLS override bits */ 3852 if (def != data) 3853 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3854 3855 /* enable cgcg FSM(0x0000363F) */ 3856 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3857 3858 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3859 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3861 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3862 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3863 if (def != data) 3864 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3865 3866 /* set IDLE_POLL_COUNT(0x00900100) */ 3867 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3868 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3869 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3870 if (def != data) 3871 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3872 } else { 3873 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3874 /* reset CGCG/CGLS bits */ 3875 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3876 /* disable cgcg and cgls in FSM */ 3877 if (def != data) 3878 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3879 } 3880 3881 amdgpu_gfx_rlc_exit_safe_mode(adev); 3882 } 3883 3884 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3885 bool enable) 3886 { 3887 if (enable) { 3888 /* CGCG/CGLS should be enabled after MGCG/MGLS 3889 * === MGCG + MGLS === 3890 */ 3891 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3892 /* === CGCG /CGLS for GFX 3D Only === */ 3893 gfx_v9_0_update_3d_clock_gating(adev, enable); 3894 /* === CGCG + CGLS === */ 3895 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3896 } else { 3897 /* CGCG/CGLS should be disabled before MGCG/MGLS 3898 * === CGCG + CGLS === 3899 */ 3900 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3901 /* === CGCG /CGLS for GFX 3D Only === */ 3902 gfx_v9_0_update_3d_clock_gating(adev, enable); 3903 /* === MGCG + MGLS === */ 3904 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3905 } 3906 return 0; 3907 } 3908 3909 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3910 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 3911 .set_safe_mode = gfx_v9_0_set_safe_mode, 3912 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 3913 .init = gfx_v9_0_rlc_init, 3914 .get_csb_size = gfx_v9_0_get_csb_size, 3915 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 3916 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 3917 .resume = gfx_v9_0_rlc_resume, 3918 .stop = gfx_v9_0_rlc_stop, 3919 .reset = gfx_v9_0_rlc_reset, 3920 .start = gfx_v9_0_rlc_start 3921 }; 3922 3923 static int gfx_v9_0_set_powergating_state(void *handle, 3924 enum amd_powergating_state state) 3925 { 3926 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3927 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3928 3929 switch (adev->asic_type) { 3930 case CHIP_RAVEN: 3931 if (!enable) { 3932 amdgpu_gfx_off_ctrl(adev, false); 3933 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 3934 } 3935 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3936 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3937 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3938 } else { 3939 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3940 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3941 } 3942 3943 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3944 gfx_v9_0_enable_cp_power_gating(adev, true); 3945 else 3946 gfx_v9_0_enable_cp_power_gating(adev, false); 3947 3948 /* update gfx cgpg state */ 3949 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3950 3951 /* update mgcg state */ 3952 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3953 3954 if (enable) 3955 amdgpu_gfx_off_ctrl(adev, true); 3956 break; 3957 case CHIP_VEGA12: 3958 if (!enable) { 3959 amdgpu_gfx_off_ctrl(adev, false); 3960 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 3961 } else { 3962 amdgpu_gfx_off_ctrl(adev, true); 3963 } 3964 break; 3965 default: 3966 break; 3967 } 3968 3969 return 0; 3970 } 3971 3972 static int gfx_v9_0_set_clockgating_state(void *handle, 3973 enum amd_clockgating_state state) 3974 { 3975 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3976 3977 if (amdgpu_sriov_vf(adev)) 3978 return 0; 3979 3980 switch (adev->asic_type) { 3981 case CHIP_VEGA10: 3982 case CHIP_VEGA12: 3983 case CHIP_VEGA20: 3984 case CHIP_RAVEN: 3985 gfx_v9_0_update_gfx_clock_gating(adev, 3986 state == AMD_CG_STATE_GATE ? true : false); 3987 break; 3988 default: 3989 break; 3990 } 3991 return 0; 3992 } 3993 3994 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3995 { 3996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3997 int data; 3998 3999 if (amdgpu_sriov_vf(adev)) 4000 *flags = 0; 4001 4002 /* AMD_CG_SUPPORT_GFX_MGCG */ 4003 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4004 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4005 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4006 4007 /* AMD_CG_SUPPORT_GFX_CGCG */ 4008 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4009 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4010 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4011 4012 /* AMD_CG_SUPPORT_GFX_CGLS */ 4013 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4014 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4015 4016 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4017 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4018 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4019 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4020 4021 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4022 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4023 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4024 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4025 4026 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4027 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4028 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4029 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4030 4031 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4032 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4033 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4034 } 4035 4036 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4037 { 4038 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 4039 } 4040 4041 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4042 { 4043 struct amdgpu_device *adev = ring->adev; 4044 u64 wptr; 4045 4046 /* XXX check if swapping is necessary on BE */ 4047 if (ring->use_doorbell) { 4048 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4049 } else { 4050 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4051 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4052 } 4053 4054 return wptr; 4055 } 4056 4057 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4058 { 4059 struct amdgpu_device *adev = ring->adev; 4060 4061 if (ring->use_doorbell) { 4062 /* XXX check if swapping is necessary on BE */ 4063 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4064 WDOORBELL64(ring->doorbell_index, ring->wptr); 4065 } else { 4066 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4067 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4068 } 4069 } 4070 4071 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4072 { 4073 struct amdgpu_device *adev = ring->adev; 4074 u32 ref_and_mask, reg_mem_engine; 4075 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 4076 4077 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4078 switch (ring->me) { 4079 case 1: 4080 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4081 break; 4082 case 2: 4083 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4084 break; 4085 default: 4086 return; 4087 } 4088 reg_mem_engine = 0; 4089 } else { 4090 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4091 reg_mem_engine = 1; /* pfp */ 4092 } 4093 4094 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4095 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 4096 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 4097 ref_and_mask, ref_and_mask, 0x20); 4098 } 4099 4100 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4101 struct amdgpu_job *job, 4102 struct amdgpu_ib *ib, 4103 uint32_t flags) 4104 { 4105 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4106 u32 header, control = 0; 4107 4108 if (ib->flags & AMDGPU_IB_FLAG_CE) 4109 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 4110 else 4111 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4112 4113 control |= ib->length_dw | (vmid << 24); 4114 4115 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4116 control |= INDIRECT_BUFFER_PRE_ENB(1); 4117 4118 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4119 gfx_v9_0_ring_emit_de_meta(ring); 4120 } 4121 4122 amdgpu_ring_write(ring, header); 4123 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4124 amdgpu_ring_write(ring, 4125 #ifdef __BIG_ENDIAN 4126 (2 << 0) | 4127 #endif 4128 lower_32_bits(ib->gpu_addr)); 4129 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4130 amdgpu_ring_write(ring, control); 4131 } 4132 4133 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4134 struct amdgpu_job *job, 4135 struct amdgpu_ib *ib, 4136 uint32_t flags) 4137 { 4138 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4139 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4140 4141 /* Currently, there is a high possibility to get wave ID mismatch 4142 * between ME and GDS, leading to a hw deadlock, because ME generates 4143 * different wave IDs than the GDS expects. This situation happens 4144 * randomly when at least 5 compute pipes use GDS ordered append. 4145 * The wave IDs generated by ME are also wrong after suspend/resume. 4146 * Those are probably bugs somewhere else in the kernel driver. 4147 * 4148 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4149 * GDS to 0 for this ring (me/pipe). 4150 */ 4151 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4152 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4153 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4154 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4155 } 4156 4157 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4158 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4159 amdgpu_ring_write(ring, 4160 #ifdef __BIG_ENDIAN 4161 (2 << 0) | 4162 #endif 4163 lower_32_bits(ib->gpu_addr)); 4164 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4165 amdgpu_ring_write(ring, control); 4166 } 4167 4168 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4169 u64 seq, unsigned flags) 4170 { 4171 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4172 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4173 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 4174 4175 /* RELEASE_MEM - flush caches, send int */ 4176 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4177 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 4178 EOP_TC_NC_ACTION_EN) : 4179 (EOP_TCL1_ACTION_EN | 4180 EOP_TC_ACTION_EN | 4181 EOP_TC_WB_ACTION_EN | 4182 EOP_TC_MD_ACTION_EN)) | 4183 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4184 EVENT_INDEX(5))); 4185 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 4186 4187 /* 4188 * the address should be Qword aligned if 64bit write, Dword 4189 * aligned if only send 32bit data low (discard data high) 4190 */ 4191 if (write64bit) 4192 BUG_ON(addr & 0x7); 4193 else 4194 BUG_ON(addr & 0x3); 4195 amdgpu_ring_write(ring, lower_32_bits(addr)); 4196 amdgpu_ring_write(ring, upper_32_bits(addr)); 4197 amdgpu_ring_write(ring, lower_32_bits(seq)); 4198 amdgpu_ring_write(ring, upper_32_bits(seq)); 4199 amdgpu_ring_write(ring, 0); 4200 } 4201 4202 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4203 { 4204 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4205 uint32_t seq = ring->fence_drv.sync_seq; 4206 uint64_t addr = ring->fence_drv.gpu_addr; 4207 4208 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 4209 lower_32_bits(addr), upper_32_bits(addr), 4210 seq, 0xffffffff, 4); 4211 } 4212 4213 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4214 unsigned vmid, uint64_t pd_addr) 4215 { 4216 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4217 4218 /* compute doesn't have PFP */ 4219 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4220 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4221 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4222 amdgpu_ring_write(ring, 0x0); 4223 } 4224 } 4225 4226 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4227 { 4228 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 4229 } 4230 4231 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4232 { 4233 u64 wptr; 4234 4235 /* XXX check if swapping is necessary on BE */ 4236 if (ring->use_doorbell) 4237 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4238 else 4239 BUG(); 4240 return wptr; 4241 } 4242 4243 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring, 4244 bool acquire) 4245 { 4246 struct amdgpu_device *adev = ring->adev; 4247 int pipe_num, tmp, reg; 4248 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1; 4249 4250 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; 4251 4252 /* first me only has 2 entries, GFX and HP3D */ 4253 if (ring->me > 0) 4254 pipe_num -= 2; 4255 4256 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; 4257 tmp = RREG32(reg); 4258 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent); 4259 WREG32(reg, tmp); 4260 } 4261 4262 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev, 4263 struct amdgpu_ring *ring, 4264 bool acquire) 4265 { 4266 int i, pipe; 4267 bool reserve; 4268 struct amdgpu_ring *iring; 4269 4270 mutex_lock(&adev->gfx.pipe_reserve_mutex); 4271 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0); 4272 if (acquire) 4273 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4274 else 4275 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4276 4277 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { 4278 /* Clear all reservations - everyone reacquires all resources */ 4279 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) 4280 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], 4281 true); 4282 4283 for (i = 0; i < adev->gfx.num_compute_rings; ++i) 4284 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], 4285 true); 4286 } else { 4287 /* Lower all pipes without a current reservation */ 4288 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 4289 iring = &adev->gfx.gfx_ring[i]; 4290 pipe = amdgpu_gfx_queue_to_bit(adev, 4291 iring->me, 4292 iring->pipe, 4293 0); 4294 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4295 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4296 } 4297 4298 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 4299 iring = &adev->gfx.compute_ring[i]; 4300 pipe = amdgpu_gfx_queue_to_bit(adev, 4301 iring->me, 4302 iring->pipe, 4303 0); 4304 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4305 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4306 } 4307 } 4308 4309 mutex_unlock(&adev->gfx.pipe_reserve_mutex); 4310 } 4311 4312 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev, 4313 struct amdgpu_ring *ring, 4314 bool acquire) 4315 { 4316 uint32_t pipe_priority = acquire ? 0x2 : 0x0; 4317 uint32_t queue_priority = acquire ? 0xf : 0x0; 4318 4319 mutex_lock(&adev->srbm_mutex); 4320 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4321 4322 WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); 4323 WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); 4324 4325 soc15_grbm_select(adev, 0, 0, 0, 0); 4326 mutex_unlock(&adev->srbm_mutex); 4327 } 4328 4329 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring, 4330 enum drm_sched_priority priority) 4331 { 4332 struct amdgpu_device *adev = ring->adev; 4333 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; 4334 4335 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) 4336 return; 4337 4338 gfx_v9_0_hqd_set_priority(adev, ring, acquire); 4339 gfx_v9_0_pipe_reserve_resources(adev, ring, acquire); 4340 } 4341 4342 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4343 { 4344 struct amdgpu_device *adev = ring->adev; 4345 4346 /* XXX check if swapping is necessary on BE */ 4347 if (ring->use_doorbell) { 4348 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4349 WDOORBELL64(ring->doorbell_index, ring->wptr); 4350 } else{ 4351 BUG(); /* only DOORBELL method supported on gfx9 now */ 4352 } 4353 } 4354 4355 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4356 u64 seq, unsigned int flags) 4357 { 4358 struct amdgpu_device *adev = ring->adev; 4359 4360 /* we only allocate 32bit for each seq wb address */ 4361 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4362 4363 /* write fence seq to the "addr" */ 4364 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4365 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4366 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4367 amdgpu_ring_write(ring, lower_32_bits(addr)); 4368 amdgpu_ring_write(ring, upper_32_bits(addr)); 4369 amdgpu_ring_write(ring, lower_32_bits(seq)); 4370 4371 if (flags & AMDGPU_FENCE_FLAG_INT) { 4372 /* set register to trigger INT */ 4373 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4374 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4375 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4376 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4377 amdgpu_ring_write(ring, 0); 4378 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4379 } 4380 } 4381 4382 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 4383 { 4384 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4385 amdgpu_ring_write(ring, 0); 4386 } 4387 4388 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 4389 { 4390 struct v9_ce_ib_state ce_payload = {0}; 4391 uint64_t csa_addr; 4392 int cnt; 4393 4394 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4395 csa_addr = amdgpu_csa_vaddr(ring->adev); 4396 4397 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4398 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4399 WRITE_DATA_DST_SEL(8) | 4400 WR_CONFIRM) | 4401 WRITE_DATA_CACHE_POLICY(0)); 4402 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4403 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4404 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 4405 } 4406 4407 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 4408 { 4409 struct v9_de_ib_state de_payload = {0}; 4410 uint64_t csa_addr, gds_addr; 4411 int cnt; 4412 4413 csa_addr = amdgpu_csa_vaddr(ring->adev); 4414 gds_addr = csa_addr + 4096; 4415 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4416 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4417 4418 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4419 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4420 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4421 WRITE_DATA_DST_SEL(8) | 4422 WR_CONFIRM) | 4423 WRITE_DATA_CACHE_POLICY(0)); 4424 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4425 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4426 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 4427 } 4428 4429 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4430 { 4431 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4432 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4433 } 4434 4435 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4436 { 4437 uint32_t dw2 = 0; 4438 4439 if (amdgpu_sriov_vf(ring->adev)) 4440 gfx_v9_0_ring_emit_ce_meta(ring); 4441 4442 gfx_v9_0_ring_emit_tmz(ring, true); 4443 4444 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4445 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4446 /* set load_global_config & load_global_uconfig */ 4447 dw2 |= 0x8001; 4448 /* set load_cs_sh_regs */ 4449 dw2 |= 0x01000000; 4450 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4451 dw2 |= 0x10002; 4452 4453 /* set load_ce_ram if preamble presented */ 4454 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4455 dw2 |= 0x10000000; 4456 } else { 4457 /* still load_ce_ram if this is the first time preamble presented 4458 * although there is no context switch happens. 4459 */ 4460 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4461 dw2 |= 0x10000000; 4462 } 4463 4464 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4465 amdgpu_ring_write(ring, dw2); 4466 amdgpu_ring_write(ring, 0); 4467 } 4468 4469 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4470 { 4471 unsigned ret; 4472 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4473 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4474 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4475 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4476 ret = ring->wptr & ring->buf_mask; 4477 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4478 return ret; 4479 } 4480 4481 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4482 { 4483 unsigned cur; 4484 BUG_ON(offset > ring->buf_mask); 4485 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4486 4487 cur = (ring->wptr & ring->buf_mask) - 1; 4488 if (likely(cur > offset)) 4489 ring->ring[offset] = cur - offset; 4490 else 4491 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 4492 } 4493 4494 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4495 { 4496 struct amdgpu_device *adev = ring->adev; 4497 4498 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4499 amdgpu_ring_write(ring, 0 | /* src: register*/ 4500 (5 << 8) | /* dst: memory */ 4501 (1 << 20)); /* write confirm */ 4502 amdgpu_ring_write(ring, reg); 4503 amdgpu_ring_write(ring, 0); 4504 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4505 adev->virt.reg_val_offs * 4)); 4506 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4507 adev->virt.reg_val_offs * 4)); 4508 } 4509 4510 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4511 uint32_t val) 4512 { 4513 uint32_t cmd = 0; 4514 4515 switch (ring->funcs->type) { 4516 case AMDGPU_RING_TYPE_GFX: 4517 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4518 break; 4519 case AMDGPU_RING_TYPE_KIQ: 4520 cmd = (1 << 16); /* no inc addr */ 4521 break; 4522 default: 4523 cmd = WR_CONFIRM; 4524 break; 4525 } 4526 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4527 amdgpu_ring_write(ring, cmd); 4528 amdgpu_ring_write(ring, reg); 4529 amdgpu_ring_write(ring, 0); 4530 amdgpu_ring_write(ring, val); 4531 } 4532 4533 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4534 uint32_t val, uint32_t mask) 4535 { 4536 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4537 } 4538 4539 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4540 uint32_t reg0, uint32_t reg1, 4541 uint32_t ref, uint32_t mask) 4542 { 4543 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4544 struct amdgpu_device *adev = ring->adev; 4545 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 4546 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 4547 4548 if (fw_version_ok) 4549 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4550 ref, mask, 0x20); 4551 else 4552 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4553 ref, mask); 4554 } 4555 4556 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4557 { 4558 struct amdgpu_device *adev = ring->adev; 4559 uint32_t value = 0; 4560 4561 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4562 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4563 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4564 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4565 WREG32(mmSQ_CMD, value); 4566 } 4567 4568 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4569 enum amdgpu_interrupt_state state) 4570 { 4571 switch (state) { 4572 case AMDGPU_IRQ_STATE_DISABLE: 4573 case AMDGPU_IRQ_STATE_ENABLE: 4574 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4575 TIME_STAMP_INT_ENABLE, 4576 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4577 break; 4578 default: 4579 break; 4580 } 4581 } 4582 4583 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4584 int me, int pipe, 4585 enum amdgpu_interrupt_state state) 4586 { 4587 u32 mec_int_cntl, mec_int_cntl_reg; 4588 4589 /* 4590 * amdgpu controls only the first MEC. That's why this function only 4591 * handles the setting of interrupts for this specific MEC. All other 4592 * pipes' interrupts are set by amdkfd. 4593 */ 4594 4595 if (me == 1) { 4596 switch (pipe) { 4597 case 0: 4598 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4599 break; 4600 case 1: 4601 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4602 break; 4603 case 2: 4604 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4605 break; 4606 case 3: 4607 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4608 break; 4609 default: 4610 DRM_DEBUG("invalid pipe %d\n", pipe); 4611 return; 4612 } 4613 } else { 4614 DRM_DEBUG("invalid me %d\n", me); 4615 return; 4616 } 4617 4618 switch (state) { 4619 case AMDGPU_IRQ_STATE_DISABLE: 4620 mec_int_cntl = RREG32(mec_int_cntl_reg); 4621 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4622 TIME_STAMP_INT_ENABLE, 0); 4623 WREG32(mec_int_cntl_reg, mec_int_cntl); 4624 break; 4625 case AMDGPU_IRQ_STATE_ENABLE: 4626 mec_int_cntl = RREG32(mec_int_cntl_reg); 4627 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4628 TIME_STAMP_INT_ENABLE, 1); 4629 WREG32(mec_int_cntl_reg, mec_int_cntl); 4630 break; 4631 default: 4632 break; 4633 } 4634 } 4635 4636 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4637 struct amdgpu_irq_src *source, 4638 unsigned type, 4639 enum amdgpu_interrupt_state state) 4640 { 4641 switch (state) { 4642 case AMDGPU_IRQ_STATE_DISABLE: 4643 case AMDGPU_IRQ_STATE_ENABLE: 4644 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4645 PRIV_REG_INT_ENABLE, 4646 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4647 break; 4648 default: 4649 break; 4650 } 4651 4652 return 0; 4653 } 4654 4655 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4656 struct amdgpu_irq_src *source, 4657 unsigned type, 4658 enum amdgpu_interrupt_state state) 4659 { 4660 switch (state) { 4661 case AMDGPU_IRQ_STATE_DISABLE: 4662 case AMDGPU_IRQ_STATE_ENABLE: 4663 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4664 PRIV_INSTR_INT_ENABLE, 4665 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4666 default: 4667 break; 4668 } 4669 4670 return 0; 4671 } 4672 4673 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 4674 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 4675 CP_ECC_ERROR_INT_ENABLE, 1) 4676 4677 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 4678 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 4679 CP_ECC_ERROR_INT_ENABLE, 0) 4680 4681 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 4682 struct amdgpu_irq_src *source, 4683 unsigned type, 4684 enum amdgpu_interrupt_state state) 4685 { 4686 switch (state) { 4687 case AMDGPU_IRQ_STATE_DISABLE: 4688 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4689 CP_ECC_ERROR_INT_ENABLE, 0); 4690 DISABLE_ECC_ON_ME_PIPE(1, 0); 4691 DISABLE_ECC_ON_ME_PIPE(1, 1); 4692 DISABLE_ECC_ON_ME_PIPE(1, 2); 4693 DISABLE_ECC_ON_ME_PIPE(1, 3); 4694 break; 4695 4696 case AMDGPU_IRQ_STATE_ENABLE: 4697 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4698 CP_ECC_ERROR_INT_ENABLE, 1); 4699 ENABLE_ECC_ON_ME_PIPE(1, 0); 4700 ENABLE_ECC_ON_ME_PIPE(1, 1); 4701 ENABLE_ECC_ON_ME_PIPE(1, 2); 4702 ENABLE_ECC_ON_ME_PIPE(1, 3); 4703 break; 4704 default: 4705 break; 4706 } 4707 4708 return 0; 4709 } 4710 4711 4712 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4713 struct amdgpu_irq_src *src, 4714 unsigned type, 4715 enum amdgpu_interrupt_state state) 4716 { 4717 switch (type) { 4718 case AMDGPU_CP_IRQ_GFX_EOP: 4719 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4720 break; 4721 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4722 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4723 break; 4724 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4725 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4726 break; 4727 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4728 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4729 break; 4730 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4731 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4732 break; 4733 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4734 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4735 break; 4736 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4737 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4738 break; 4739 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4740 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4741 break; 4742 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4743 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4744 break; 4745 default: 4746 break; 4747 } 4748 return 0; 4749 } 4750 4751 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4752 struct amdgpu_irq_src *source, 4753 struct amdgpu_iv_entry *entry) 4754 { 4755 int i; 4756 u8 me_id, pipe_id, queue_id; 4757 struct amdgpu_ring *ring; 4758 4759 DRM_DEBUG("IH: CP EOP\n"); 4760 me_id = (entry->ring_id & 0x0c) >> 2; 4761 pipe_id = (entry->ring_id & 0x03) >> 0; 4762 queue_id = (entry->ring_id & 0x70) >> 4; 4763 4764 switch (me_id) { 4765 case 0: 4766 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4767 break; 4768 case 1: 4769 case 2: 4770 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4771 ring = &adev->gfx.compute_ring[i]; 4772 /* Per-queue interrupt is supported for MEC starting from VI. 4773 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4774 */ 4775 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4776 amdgpu_fence_process(ring); 4777 } 4778 break; 4779 } 4780 return 0; 4781 } 4782 4783 static void gfx_v9_0_fault(struct amdgpu_device *adev, 4784 struct amdgpu_iv_entry *entry) 4785 { 4786 u8 me_id, pipe_id, queue_id; 4787 struct amdgpu_ring *ring; 4788 int i; 4789 4790 me_id = (entry->ring_id & 0x0c) >> 2; 4791 pipe_id = (entry->ring_id & 0x03) >> 0; 4792 queue_id = (entry->ring_id & 0x70) >> 4; 4793 4794 switch (me_id) { 4795 case 0: 4796 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4797 break; 4798 case 1: 4799 case 2: 4800 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4801 ring = &adev->gfx.compute_ring[i]; 4802 if (ring->me == me_id && ring->pipe == pipe_id && 4803 ring->queue == queue_id) 4804 drm_sched_fault(&ring->sched); 4805 } 4806 break; 4807 } 4808 } 4809 4810 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4811 struct amdgpu_irq_src *source, 4812 struct amdgpu_iv_entry *entry) 4813 { 4814 DRM_ERROR("Illegal register access in command stream\n"); 4815 gfx_v9_0_fault(adev, entry); 4816 return 0; 4817 } 4818 4819 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4820 struct amdgpu_irq_src *source, 4821 struct amdgpu_iv_entry *entry) 4822 { 4823 DRM_ERROR("Illegal instruction in command stream\n"); 4824 gfx_v9_0_fault(adev, entry); 4825 return 0; 4826 } 4827 4828 static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 4829 struct amdgpu_iv_entry *entry) 4830 { 4831 /* TODO ue will trigger an interrupt. */ 4832 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 4833 amdgpu_ras_reset_gpu(adev, 0); 4834 return AMDGPU_RAS_UE; 4835 } 4836 4837 static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev, 4838 struct amdgpu_irq_src *source, 4839 struct amdgpu_iv_entry *entry) 4840 { 4841 struct ras_common_if *ras_if = adev->gfx.ras_if; 4842 struct ras_dispatch_if ih_data = { 4843 .entry = entry, 4844 }; 4845 4846 if (!ras_if) 4847 return 0; 4848 4849 ih_data.head = *ras_if; 4850 4851 DRM_ERROR("CP ECC ERROR IRQ\n"); 4852 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 4853 return 0; 4854 } 4855 4856 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4857 .name = "gfx_v9_0", 4858 .early_init = gfx_v9_0_early_init, 4859 .late_init = gfx_v9_0_late_init, 4860 .sw_init = gfx_v9_0_sw_init, 4861 .sw_fini = gfx_v9_0_sw_fini, 4862 .hw_init = gfx_v9_0_hw_init, 4863 .hw_fini = gfx_v9_0_hw_fini, 4864 .suspend = gfx_v9_0_suspend, 4865 .resume = gfx_v9_0_resume, 4866 .is_idle = gfx_v9_0_is_idle, 4867 .wait_for_idle = gfx_v9_0_wait_for_idle, 4868 .soft_reset = gfx_v9_0_soft_reset, 4869 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4870 .set_powergating_state = gfx_v9_0_set_powergating_state, 4871 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4872 }; 4873 4874 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4875 .type = AMDGPU_RING_TYPE_GFX, 4876 .align_mask = 0xff, 4877 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4878 .support_64bit_ptrs = true, 4879 .vmhub = AMDGPU_GFXHUB, 4880 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4881 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4882 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4883 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4884 5 + /* COND_EXEC */ 4885 7 + /* PIPELINE_SYNC */ 4886 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4887 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4888 2 + /* VM_FLUSH */ 4889 8 + /* FENCE for VM_FLUSH */ 4890 20 + /* GDS switch */ 4891 4 + /* double SWITCH_BUFFER, 4892 the first COND_EXEC jump to the place just 4893 prior to this double SWITCH_BUFFER */ 4894 5 + /* COND_EXEC */ 4895 7 + /* HDP_flush */ 4896 4 + /* VGT_flush */ 4897 14 + /* CE_META */ 4898 31 + /* DE_META */ 4899 3 + /* CNTX_CTRL */ 4900 5 + /* HDP_INVL */ 4901 8 + 8 + /* FENCE x2 */ 4902 2, /* SWITCH_BUFFER */ 4903 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4904 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4905 .emit_fence = gfx_v9_0_ring_emit_fence, 4906 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4907 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4908 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4909 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4910 .test_ring = gfx_v9_0_ring_test_ring, 4911 .test_ib = gfx_v9_0_ring_test_ib, 4912 .insert_nop = amdgpu_ring_insert_nop, 4913 .pad_ib = amdgpu_ring_generic_pad_ib, 4914 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4915 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4916 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4917 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4918 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4919 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4920 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4921 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4922 .soft_recovery = gfx_v9_0_ring_soft_recovery, 4923 }; 4924 4925 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4926 .type = AMDGPU_RING_TYPE_COMPUTE, 4927 .align_mask = 0xff, 4928 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4929 .support_64bit_ptrs = true, 4930 .vmhub = AMDGPU_GFXHUB, 4931 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4932 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4933 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4934 .emit_frame_size = 4935 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4936 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4937 5 + /* hdp invalidate */ 4938 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4939 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4940 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4941 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4942 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4943 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 4944 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4945 .emit_fence = gfx_v9_0_ring_emit_fence, 4946 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4947 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4948 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4949 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4950 .test_ring = gfx_v9_0_ring_test_ring, 4951 .test_ib = gfx_v9_0_ring_test_ib, 4952 .insert_nop = amdgpu_ring_insert_nop, 4953 .pad_ib = amdgpu_ring_generic_pad_ib, 4954 .set_priority = gfx_v9_0_ring_set_priority_compute, 4955 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4956 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4957 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4958 }; 4959 4960 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4961 .type = AMDGPU_RING_TYPE_KIQ, 4962 .align_mask = 0xff, 4963 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4964 .support_64bit_ptrs = true, 4965 .vmhub = AMDGPU_GFXHUB, 4966 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4967 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4968 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4969 .emit_frame_size = 4970 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4971 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4972 5 + /* hdp invalidate */ 4973 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4974 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4975 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4976 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4977 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4978 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 4979 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4980 .test_ring = gfx_v9_0_ring_test_ring, 4981 .insert_nop = amdgpu_ring_insert_nop, 4982 .pad_ib = amdgpu_ring_generic_pad_ib, 4983 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4984 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4985 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4986 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4987 }; 4988 4989 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4990 { 4991 int i; 4992 4993 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4994 4995 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4996 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4997 4998 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4999 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 5000 } 5001 5002 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 5003 .set = gfx_v9_0_set_eop_interrupt_state, 5004 .process = gfx_v9_0_eop_irq, 5005 }; 5006 5007 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 5008 .set = gfx_v9_0_set_priv_reg_fault_state, 5009 .process = gfx_v9_0_priv_reg_irq, 5010 }; 5011 5012 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 5013 .set = gfx_v9_0_set_priv_inst_fault_state, 5014 .process = gfx_v9_0_priv_inst_irq, 5015 }; 5016 5017 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 5018 .set = gfx_v9_0_set_cp_ecc_error_state, 5019 .process = gfx_v9_0_cp_ecc_error_irq, 5020 }; 5021 5022 5023 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 5024 { 5025 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5026 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 5027 5028 adev->gfx.priv_reg_irq.num_types = 1; 5029 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 5030 5031 adev->gfx.priv_inst_irq.num_types = 1; 5032 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 5033 5034 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 5035 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 5036 } 5037 5038 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 5039 { 5040 switch (adev->asic_type) { 5041 case CHIP_VEGA10: 5042 case CHIP_VEGA12: 5043 case CHIP_VEGA20: 5044 case CHIP_RAVEN: 5045 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 5046 break; 5047 default: 5048 break; 5049 } 5050 } 5051 5052 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 5053 { 5054 /* init asci gds info */ 5055 switch (adev->asic_type) { 5056 case CHIP_VEGA10: 5057 case CHIP_VEGA12: 5058 case CHIP_VEGA20: 5059 adev->gds.mem.total_size = 0x10000; 5060 break; 5061 case CHIP_RAVEN: 5062 adev->gds.mem.total_size = 0x1000; 5063 break; 5064 default: 5065 adev->gds.mem.total_size = 0x10000; 5066 break; 5067 } 5068 5069 switch (adev->asic_type) { 5070 case CHIP_VEGA10: 5071 case CHIP_VEGA20: 5072 adev->gds.gds_compute_max_wave_id = 0x7ff; 5073 break; 5074 case CHIP_VEGA12: 5075 adev->gds.gds_compute_max_wave_id = 0x27f; 5076 break; 5077 case CHIP_RAVEN: 5078 if (adev->rev_id >= 0x8) 5079 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 5080 else 5081 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 5082 break; 5083 default: 5084 /* this really depends on the chip */ 5085 adev->gds.gds_compute_max_wave_id = 0x7ff; 5086 break; 5087 } 5088 5089 adev->gds.gws.total_size = 64; 5090 adev->gds.oa.total_size = 16; 5091 5092 if (adev->gds.mem.total_size == 64 * 1024) { 5093 adev->gds.mem.gfx_partition_size = 4096; 5094 adev->gds.mem.cs_partition_size = 4096; 5095 5096 adev->gds.gws.gfx_partition_size = 4; 5097 adev->gds.gws.cs_partition_size = 4; 5098 5099 adev->gds.oa.gfx_partition_size = 4; 5100 adev->gds.oa.cs_partition_size = 1; 5101 } else { 5102 adev->gds.mem.gfx_partition_size = 1024; 5103 adev->gds.mem.cs_partition_size = 1024; 5104 5105 adev->gds.gws.gfx_partition_size = 16; 5106 adev->gds.gws.cs_partition_size = 16; 5107 5108 adev->gds.oa.gfx_partition_size = 4; 5109 adev->gds.oa.cs_partition_size = 4; 5110 } 5111 } 5112 5113 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 5114 u32 bitmap) 5115 { 5116 u32 data; 5117 5118 if (!bitmap) 5119 return; 5120 5121 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 5122 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 5123 5124 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5125 } 5126 5127 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 5128 { 5129 u32 data, mask; 5130 5131 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5132 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5133 5134 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 5135 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 5136 5137 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 5138 5139 return (~data) & mask; 5140 } 5141 5142 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 5143 struct amdgpu_cu_info *cu_info) 5144 { 5145 int i, j, k, counter, active_cu_number = 0; 5146 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5147 unsigned disable_masks[4 * 2]; 5148 5149 if (!adev || !cu_info) 5150 return -EINVAL; 5151 5152 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5153 5154 mutex_lock(&adev->grbm_idx_mutex); 5155 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5156 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5157 mask = 1; 5158 ao_bitmap = 0; 5159 counter = 0; 5160 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 5161 if (i < 4 && j < 2) 5162 gfx_v9_0_set_user_cu_inactive_bitmap( 5163 adev, disable_masks[i * 2 + j]); 5164 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 5165 cu_info->bitmap[i][j] = bitmap; 5166 5167 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5168 if (bitmap & mask) { 5169 if (counter < adev->gfx.config.max_cu_per_sh) 5170 ao_bitmap |= mask; 5171 counter ++; 5172 } 5173 mask <<= 1; 5174 } 5175 active_cu_number += counter; 5176 if (i < 2 && j < 2) 5177 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5178 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5179 } 5180 } 5181 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5182 mutex_unlock(&adev->grbm_idx_mutex); 5183 5184 cu_info->number = active_cu_number; 5185 cu_info->ao_cu_mask = ao_cu_mask; 5186 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5187 5188 return 0; 5189 } 5190 5191 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 5192 { 5193 .type = AMD_IP_BLOCK_TYPE_GFX, 5194 .major = 9, 5195 .minor = 0, 5196 .rev = 0, 5197 .funcs = &gfx_v9_0_ip_funcs, 5198 }; 5199