xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c (revision 2a598d0b)
1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 
30 #include "amdgpu.h"
31 #include "amdgpu_gfx.h"
32 #include "soc15.h"
33 #include "soc15d.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_pm.h"
36 
37 #include "gc/gc_9_0_offset.h"
38 #include "gc/gc_9_0_sh_mask.h"
39 
40 #include "vega10_enum.h"
41 
42 #include "soc15_common.h"
43 #include "clearstate_gfx9.h"
44 #include "v9_structs.h"
45 
46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
47 
48 #include "amdgpu_ras.h"
49 
50 #include "amdgpu_ring_mux.h"
51 #include "gfx_v9_4.h"
52 #include "gfx_v9_0.h"
53 #include "gfx_v9_4_2.h"
54 
55 #include "asic_reg/pwr/pwr_10_0_offset.h"
56 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
57 #include "asic_reg/gc/gc_9_0_default.h"
58 
59 #define GFX9_NUM_GFX_RINGS     1
60 #define GFX9_NUM_SW_GFX_RINGS  2
61 #define GFX9_MEC_HPD_SIZE 4096
62 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
63 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
64 
65 #define mmGCEA_PROBE_MAP                        0x070c
66 #define mmGCEA_PROBE_MAP_BASE_IDX               0
67 
68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
70 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
74 
75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
77 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
81 
82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
84 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
88 
89 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
91 MODULE_FIRMWARE("amdgpu/raven_me.bin");
92 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
95 
96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
98 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin");
103 
104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
106 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
111 
112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
113 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
114 
115 MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
116 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
117 MODULE_FIRMWARE("amdgpu/renoir_me.bin");
118 MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
119 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
120 
121 MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
122 MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
123 MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
124 MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
125 MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
126 MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
127 
128 MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin");
129 MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin");
130 MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin");
131 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin");
132 MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
133 
134 #define mmTCP_CHAN_STEER_0_ARCT								0x0b03
135 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX							0
136 #define mmTCP_CHAN_STEER_1_ARCT								0x0b04
137 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX							0
138 #define mmTCP_CHAN_STEER_2_ARCT								0x0b09
139 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX							0
140 #define mmTCP_CHAN_STEER_3_ARCT								0x0b0a
141 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX							0
142 #define mmTCP_CHAN_STEER_4_ARCT								0x0b0b
143 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX							0
144 #define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
145 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
146 
147 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir                0x0025
148 #define mmGOLDEN_TSC_COUNT_UPPER_Renoir_BASE_IDX       1
149 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir                0x0026
150 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX       1
151 
152 enum ta_ras_gfx_subblock {
153 	/*CPC*/
154 	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
155 	TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
156 	TA_RAS_BLOCK__GFX_CPC_UCODE,
157 	TA_RAS_BLOCK__GFX_DC_STATE_ME1,
158 	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
159 	TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
160 	TA_RAS_BLOCK__GFX_DC_STATE_ME2,
161 	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
162 	TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
163 	TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
164 	/* CPF*/
165 	TA_RAS_BLOCK__GFX_CPF_INDEX_START,
166 	TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
167 	TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
168 	TA_RAS_BLOCK__GFX_CPF_TAG,
169 	TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
170 	/* CPG*/
171 	TA_RAS_BLOCK__GFX_CPG_INDEX_START,
172 	TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
173 	TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
174 	TA_RAS_BLOCK__GFX_CPG_TAG,
175 	TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
176 	/* GDS*/
177 	TA_RAS_BLOCK__GFX_GDS_INDEX_START,
178 	TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
179 	TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
180 	TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
181 	TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
182 	TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
183 	TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
184 	/* SPI*/
185 	TA_RAS_BLOCK__GFX_SPI_SR_MEM,
186 	/* SQ*/
187 	TA_RAS_BLOCK__GFX_SQ_INDEX_START,
188 	TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
189 	TA_RAS_BLOCK__GFX_SQ_LDS_D,
190 	TA_RAS_BLOCK__GFX_SQ_LDS_I,
191 	TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
192 	TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
193 	/* SQC (3 ranges)*/
194 	TA_RAS_BLOCK__GFX_SQC_INDEX_START,
195 	/* SQC range 0*/
196 	TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
197 	TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
198 		TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
199 	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
200 	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
201 	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
202 	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
203 	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
204 	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
205 	TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
206 		TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
207 	/* SQC range 1*/
208 	TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
209 	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
210 		TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
211 	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
212 	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
213 	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
214 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
215 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
216 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
217 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
218 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
219 	TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
220 		TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
221 	/* SQC range 2*/
222 	TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
223 	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
224 		TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
225 	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
226 	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
227 	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
228 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
229 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
230 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
231 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
232 	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
233 	TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
234 		TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
235 	TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
236 	/* TA*/
237 	TA_RAS_BLOCK__GFX_TA_INDEX_START,
238 	TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
239 	TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
240 	TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
241 	TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
242 	TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
243 	TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
244 	/* TCA*/
245 	TA_RAS_BLOCK__GFX_TCA_INDEX_START,
246 	TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
247 	TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
248 	TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
249 	/* TCC (5 sub-ranges)*/
250 	TA_RAS_BLOCK__GFX_TCC_INDEX_START,
251 	/* TCC range 0*/
252 	TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
253 	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
254 	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
255 	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
256 	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
257 	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
258 	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
259 	TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
260 	TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
261 	TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
262 	/* TCC range 1*/
263 	TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
264 	TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
265 	TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
266 	TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
267 		TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
268 	/* TCC range 2*/
269 	TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
270 	TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
271 	TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
272 	TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
273 	TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
274 	TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
275 	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
276 	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
277 	TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
278 	TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
279 		TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
280 	/* TCC range 3*/
281 	TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
282 	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
283 	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
284 	TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
285 		TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
286 	/* TCC range 4*/
287 	TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
288 	TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
289 		TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
290 	TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
291 	TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
292 		TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
293 	TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
294 	/* TCI*/
295 	TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
296 	/* TCP*/
297 	TA_RAS_BLOCK__GFX_TCP_INDEX_START,
298 	TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
299 	TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
300 	TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
301 	TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
302 	TA_RAS_BLOCK__GFX_TCP_DB_RAM,
303 	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
304 	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
305 	TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
306 	/* TD*/
307 	TA_RAS_BLOCK__GFX_TD_INDEX_START,
308 	TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
309 	TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
310 	TA_RAS_BLOCK__GFX_TD_CS_FIFO,
311 	TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
312 	/* EA (3 sub-ranges)*/
313 	TA_RAS_BLOCK__GFX_EA_INDEX_START,
314 	/* EA range 0*/
315 	TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
316 	TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
317 	TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
318 	TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
319 	TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
320 	TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
321 	TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
322 	TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
323 	TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
324 	TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
325 	/* EA range 1*/
326 	TA_RAS_BLOCK__GFX_EA_INDEX1_START,
327 	TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
328 	TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
329 	TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
330 	TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
331 	TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
332 	TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
333 	TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
334 	TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
335 	/* EA range 2*/
336 	TA_RAS_BLOCK__GFX_EA_INDEX2_START,
337 	TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
338 	TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
339 	TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
340 	TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
341 	TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
342 	TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
343 	/* UTC VM L2 bank*/
344 	TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
345 	/* UTC VM walker*/
346 	TA_RAS_BLOCK__UTC_VML2_WALKER,
347 	/* UTC ATC L2 2MB cache*/
348 	TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
349 	/* UTC ATC L2 4KB cache*/
350 	TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
351 	TA_RAS_BLOCK__GFX_MAX
352 };
353 
354 struct ras_gfx_subblock {
355 	unsigned char *name;
356 	int ta_subblock;
357 	int hw_supported_error_type;
358 	int sw_supported_error_type;
359 };
360 
361 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
362 	[AMDGPU_RAS_BLOCK__##subblock] = {                                     \
363 		#subblock,                                                     \
364 		TA_RAS_BLOCK__##subblock,                                      \
365 		((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
366 		(((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
367 	}
368 
369 static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
370 	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
371 	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
372 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
373 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
374 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
375 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
376 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
377 	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
378 	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
379 	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
380 	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
381 	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
382 	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
383 	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
384 	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
385 	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
386 	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
387 			     0),
388 	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
389 			     0),
390 	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
391 	AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
392 	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
393 	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
394 	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
395 	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
396 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
397 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
398 			     0, 0),
399 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
400 			     0),
401 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
402 			     0, 0),
403 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
404 			     0),
405 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
406 			     0, 0),
407 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
408 			     0),
409 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
410 			     1),
411 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
412 			     0, 0, 0),
413 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
414 			     0),
415 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
416 			     0),
417 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
418 			     0),
419 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
420 			     0),
421 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
422 			     0),
423 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
424 			     0, 0),
425 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
426 			     0),
427 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
428 			     0),
429 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
430 			     0, 0, 0),
431 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
432 			     0),
433 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
434 			     0),
435 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
436 			     0),
437 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
438 			     0),
439 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
440 			     0),
441 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
442 			     0, 0),
443 	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
444 			     0),
445 	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
446 	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
447 	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
448 	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
449 	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
450 	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
451 	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
452 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
453 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
454 			     1),
455 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
456 			     1),
457 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
458 			     1),
459 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
460 			     0),
461 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
462 			     0),
463 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
464 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
465 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
466 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
467 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
468 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
469 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
470 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
471 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
472 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
473 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
474 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
475 			     0),
476 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
477 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
478 			     0),
479 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
480 			     0, 0),
481 	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
482 			     0),
483 	AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
484 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
485 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
486 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
487 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
488 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
489 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
490 	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
491 	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
492 	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
493 	AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
494 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
495 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
496 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
497 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
498 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
499 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
500 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
501 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
502 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
503 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
504 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
505 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
506 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
507 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
508 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
509 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
510 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
511 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
512 	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
513 	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
514 	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
515 	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
516 	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
517 };
518 
519 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
520 {
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x00ffff87),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x00ffff8f),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
541 };
542 
543 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
544 {
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
563 };
564 
565 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
566 {
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
578 };
579 
580 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
581 {
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
606 };
607 
608 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
609 {
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
617 };
618 
619 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
620 {
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
640 };
641 
642 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
643 {
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
656 };
657 
658 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
659 {
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
663 };
664 
665 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
666 {
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
683 };
684 
685 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
686 {
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000)
700 };
701 
702 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
703 {
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
715 };
716 
717 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
718 	{SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
719 	{SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
720 };
721 
722 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
723 {
724 	mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
725 	mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
726 	mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
727 	mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
728 	mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
729 	mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
730 	mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
731 	mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
732 };
733 
734 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
735 {
736 	mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
737 	mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
738 	mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
739 	mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
740 	mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
741 	mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
742 	mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
743 	mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
744 };
745 
746 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
747 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
748 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
749 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
750 
751 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
752 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
753 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
754 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
755 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
756 				struct amdgpu_cu_info *cu_info);
757 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
758 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds);
759 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
760 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
761 					  void *ras_error_status);
762 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
763 				     void *inject_if, uint32_t instance_mask);
764 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev);
765 
766 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
767 				uint64_t queue_mask)
768 {
769 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
770 	amdgpu_ring_write(kiq_ring,
771 		PACKET3_SET_RESOURCES_VMID_MASK(0) |
772 		/* vmid_mask:0* queue_type:0 (KIQ) */
773 		PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
774 	amdgpu_ring_write(kiq_ring,
775 			lower_32_bits(queue_mask));	/* queue mask lo */
776 	amdgpu_ring_write(kiq_ring,
777 			upper_32_bits(queue_mask));	/* queue mask hi */
778 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
779 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
780 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
781 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
782 }
783 
784 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
785 				 struct amdgpu_ring *ring)
786 {
787 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
788 	uint64_t wptr_addr = ring->wptr_gpu_addr;
789 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
790 
791 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
792 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
793 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
794 			 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
795 			 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
796 			 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
797 			 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
798 			 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
799 			 /*queue_type: normal compute queue */
800 			 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
801 			 /* alloc format: all_on_one_pipe */
802 			 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
803 			 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
804 			 /* num_queues: must be 1 */
805 			 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
806 	amdgpu_ring_write(kiq_ring,
807 			PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
808 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
809 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
810 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
811 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
812 }
813 
814 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
815 				   struct amdgpu_ring *ring,
816 				   enum amdgpu_unmap_queues_action action,
817 				   u64 gpu_addr, u64 seq)
818 {
819 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
820 
821 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
822 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
823 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
824 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
825 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
826 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
827 	amdgpu_ring_write(kiq_ring,
828 			PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
829 
830 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
831 		amdgpu_ring_write(kiq_ring, lower_32_bits(ring->wptr & ring->buf_mask));
832 		amdgpu_ring_write(kiq_ring, 0);
833 		amdgpu_ring_write(kiq_ring, 0);
834 
835 	} else {
836 		amdgpu_ring_write(kiq_ring, 0);
837 		amdgpu_ring_write(kiq_ring, 0);
838 		amdgpu_ring_write(kiq_ring, 0);
839 	}
840 }
841 
842 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
843 				   struct amdgpu_ring *ring,
844 				   u64 addr,
845 				   u64 seq)
846 {
847 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
848 
849 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
850 	amdgpu_ring_write(kiq_ring,
851 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
852 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
853 			  PACKET3_QUERY_STATUS_COMMAND(2));
854 	/* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
855 	amdgpu_ring_write(kiq_ring,
856 			PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
857 			PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
858 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
859 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
860 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
861 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
862 }
863 
864 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
865 				uint16_t pasid, uint32_t flush_type,
866 				bool all_hub)
867 {
868 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
869 	amdgpu_ring_write(kiq_ring,
870 			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
871 			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
872 			PACKET3_INVALIDATE_TLBS_PASID(pasid) |
873 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
874 }
875 
876 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = {
877 	.kiq_set_resources = gfx_v9_0_kiq_set_resources,
878 	.kiq_map_queues = gfx_v9_0_kiq_map_queues,
879 	.kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues,
880 	.kiq_query_status = gfx_v9_0_kiq_query_status,
881 	.kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs,
882 	.set_resources_size = 8,
883 	.map_queues_size = 7,
884 	.unmap_queues_size = 6,
885 	.query_status_size = 7,
886 	.invalidate_tlbs_size = 2,
887 };
888 
889 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
890 {
891 	adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs;
892 }
893 
894 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
895 {
896 	switch (adev->ip_versions[GC_HWIP][0]) {
897 	case IP_VERSION(9, 0, 1):
898 		soc15_program_register_sequence(adev,
899 						golden_settings_gc_9_0,
900 						ARRAY_SIZE(golden_settings_gc_9_0));
901 		soc15_program_register_sequence(adev,
902 						golden_settings_gc_9_0_vg10,
903 						ARRAY_SIZE(golden_settings_gc_9_0_vg10));
904 		break;
905 	case IP_VERSION(9, 2, 1):
906 		soc15_program_register_sequence(adev,
907 						golden_settings_gc_9_2_1,
908 						ARRAY_SIZE(golden_settings_gc_9_2_1));
909 		soc15_program_register_sequence(adev,
910 						golden_settings_gc_9_2_1_vg12,
911 						ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
912 		break;
913 	case IP_VERSION(9, 4, 0):
914 		soc15_program_register_sequence(adev,
915 						golden_settings_gc_9_0,
916 						ARRAY_SIZE(golden_settings_gc_9_0));
917 		soc15_program_register_sequence(adev,
918 						golden_settings_gc_9_0_vg20,
919 						ARRAY_SIZE(golden_settings_gc_9_0_vg20));
920 		break;
921 	case IP_VERSION(9, 4, 1):
922 		soc15_program_register_sequence(adev,
923 						golden_settings_gc_9_4_1_arct,
924 						ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
925 		break;
926 	case IP_VERSION(9, 2, 2):
927 	case IP_VERSION(9, 1, 0):
928 		soc15_program_register_sequence(adev, golden_settings_gc_9_1,
929 						ARRAY_SIZE(golden_settings_gc_9_1));
930 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
931 			soc15_program_register_sequence(adev,
932 							golden_settings_gc_9_1_rv2,
933 							ARRAY_SIZE(golden_settings_gc_9_1_rv2));
934 		else
935 			soc15_program_register_sequence(adev,
936 							golden_settings_gc_9_1_rv1,
937 							ARRAY_SIZE(golden_settings_gc_9_1_rv1));
938 		break;
939 	 case IP_VERSION(9, 3, 0):
940 		soc15_program_register_sequence(adev,
941 						golden_settings_gc_9_1_rn,
942 						ARRAY_SIZE(golden_settings_gc_9_1_rn));
943 		return; /* for renoir, don't need common goldensetting */
944 	case IP_VERSION(9, 4, 2):
945 		gfx_v9_4_2_init_golden_registers(adev,
946 						 adev->smuio.funcs->get_die_id(adev));
947 		break;
948 	default:
949 		break;
950 	}
951 
952 	if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
953 	    (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2)))
954 		soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
955 						(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
956 }
957 
958 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
959 				       bool wc, uint32_t reg, uint32_t val)
960 {
961 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
962 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
963 				WRITE_DATA_DST_SEL(0) |
964 				(wc ? WR_CONFIRM : 0));
965 	amdgpu_ring_write(ring, reg);
966 	amdgpu_ring_write(ring, 0);
967 	amdgpu_ring_write(ring, val);
968 }
969 
970 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
971 				  int mem_space, int opt, uint32_t addr0,
972 				  uint32_t addr1, uint32_t ref, uint32_t mask,
973 				  uint32_t inv)
974 {
975 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
976 	amdgpu_ring_write(ring,
977 				 /* memory (1) or register (0) */
978 				 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
979 				 WAIT_REG_MEM_OPERATION(opt) | /* wait */
980 				 WAIT_REG_MEM_FUNCTION(3) |  /* equal */
981 				 WAIT_REG_MEM_ENGINE(eng_sel)));
982 
983 	if (mem_space)
984 		BUG_ON(addr0 & 0x3); /* Dword align */
985 	amdgpu_ring_write(ring, addr0);
986 	amdgpu_ring_write(ring, addr1);
987 	amdgpu_ring_write(ring, ref);
988 	amdgpu_ring_write(ring, mask);
989 	amdgpu_ring_write(ring, inv); /* poll interval */
990 }
991 
992 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
993 {
994 	struct amdgpu_device *adev = ring->adev;
995 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
996 	uint32_t tmp = 0;
997 	unsigned i;
998 	int r;
999 
1000 	WREG32(scratch, 0xCAFEDEAD);
1001 	r = amdgpu_ring_alloc(ring, 3);
1002 	if (r)
1003 		return r;
1004 
1005 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1006 	amdgpu_ring_write(ring, scratch - PACKET3_SET_UCONFIG_REG_START);
1007 	amdgpu_ring_write(ring, 0xDEADBEEF);
1008 	amdgpu_ring_commit(ring);
1009 
1010 	for (i = 0; i < adev->usec_timeout; i++) {
1011 		tmp = RREG32(scratch);
1012 		if (tmp == 0xDEADBEEF)
1013 			break;
1014 		udelay(1);
1015 	}
1016 
1017 	if (i >= adev->usec_timeout)
1018 		r = -ETIMEDOUT;
1019 	return r;
1020 }
1021 
1022 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1023 {
1024 	struct amdgpu_device *adev = ring->adev;
1025 	struct amdgpu_ib ib;
1026 	struct dma_fence *f = NULL;
1027 
1028 	unsigned index;
1029 	uint64_t gpu_addr;
1030 	uint32_t tmp;
1031 	long r;
1032 
1033 	r = amdgpu_device_wb_get(adev, &index);
1034 	if (r)
1035 		return r;
1036 
1037 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1038 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
1039 	memset(&ib, 0, sizeof(ib));
1040 	r = amdgpu_ib_get(adev, NULL, 16,
1041 					AMDGPU_IB_POOL_DIRECT, &ib);
1042 	if (r)
1043 		goto err1;
1044 
1045 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
1046 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
1047 	ib.ptr[2] = lower_32_bits(gpu_addr);
1048 	ib.ptr[3] = upper_32_bits(gpu_addr);
1049 	ib.ptr[4] = 0xDEADBEEF;
1050 	ib.length_dw = 5;
1051 
1052 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1053 	if (r)
1054 		goto err2;
1055 
1056 	r = dma_fence_wait_timeout(f, false, timeout);
1057 	if (r == 0) {
1058 		r = -ETIMEDOUT;
1059 		goto err2;
1060 	} else if (r < 0) {
1061 		goto err2;
1062 	}
1063 
1064 	tmp = adev->wb.wb[index];
1065 	if (tmp == 0xDEADBEEF)
1066 		r = 0;
1067 	else
1068 		r = -EINVAL;
1069 
1070 err2:
1071 	amdgpu_ib_free(adev, &ib, NULL);
1072 	dma_fence_put(f);
1073 err1:
1074 	amdgpu_device_wb_free(adev, index);
1075 	return r;
1076 }
1077 
1078 
1079 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
1080 {
1081 	amdgpu_ucode_release(&adev->gfx.pfp_fw);
1082 	amdgpu_ucode_release(&adev->gfx.me_fw);
1083 	amdgpu_ucode_release(&adev->gfx.ce_fw);
1084 	amdgpu_ucode_release(&adev->gfx.rlc_fw);
1085 	amdgpu_ucode_release(&adev->gfx.mec_fw);
1086 	amdgpu_ucode_release(&adev->gfx.mec2_fw);
1087 
1088 	kfree(adev->gfx.rlc.register_list_format);
1089 }
1090 
1091 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
1092 {
1093 	adev->gfx.me_fw_write_wait = false;
1094 	adev->gfx.mec_fw_write_wait = false;
1095 
1096 	if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) &&
1097 	    ((adev->gfx.mec_fw_version < 0x000001a5) ||
1098 	    (adev->gfx.mec_feature_version < 46) ||
1099 	    (adev->gfx.pfp_fw_version < 0x000000b7) ||
1100 	    (adev->gfx.pfp_feature_version < 46)))
1101 		DRM_WARN_ONCE("CP firmware version too old, please update!");
1102 
1103 	switch (adev->ip_versions[GC_HWIP][0]) {
1104 	case IP_VERSION(9, 0, 1):
1105 		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1106 		    (adev->gfx.me_feature_version >= 42) &&
1107 		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
1108 		    (adev->gfx.pfp_feature_version >= 42))
1109 			adev->gfx.me_fw_write_wait = true;
1110 
1111 		if ((adev->gfx.mec_fw_version >=  0x00000193) &&
1112 		    (adev->gfx.mec_feature_version >= 42))
1113 			adev->gfx.mec_fw_write_wait = true;
1114 		break;
1115 	case IP_VERSION(9, 2, 1):
1116 		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1117 		    (adev->gfx.me_feature_version >= 44) &&
1118 		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
1119 		    (adev->gfx.pfp_feature_version >= 44))
1120 			adev->gfx.me_fw_write_wait = true;
1121 
1122 		if ((adev->gfx.mec_fw_version >=  0x00000196) &&
1123 		    (adev->gfx.mec_feature_version >= 44))
1124 			adev->gfx.mec_fw_write_wait = true;
1125 		break;
1126 	case IP_VERSION(9, 4, 0):
1127 		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1128 		    (adev->gfx.me_feature_version >= 44) &&
1129 		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
1130 		    (adev->gfx.pfp_feature_version >= 44))
1131 			adev->gfx.me_fw_write_wait = true;
1132 
1133 		if ((adev->gfx.mec_fw_version >=  0x00000197) &&
1134 		    (adev->gfx.mec_feature_version >= 44))
1135 			adev->gfx.mec_fw_write_wait = true;
1136 		break;
1137 	case IP_VERSION(9, 1, 0):
1138 	case IP_VERSION(9, 2, 2):
1139 		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1140 		    (adev->gfx.me_feature_version >= 42) &&
1141 		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
1142 		    (adev->gfx.pfp_feature_version >= 42))
1143 			adev->gfx.me_fw_write_wait = true;
1144 
1145 		if ((adev->gfx.mec_fw_version >=  0x00000192) &&
1146 		    (adev->gfx.mec_feature_version >= 42))
1147 			adev->gfx.mec_fw_write_wait = true;
1148 		break;
1149 	default:
1150 		adev->gfx.me_fw_write_wait = true;
1151 		adev->gfx.mec_fw_write_wait = true;
1152 		break;
1153 	}
1154 }
1155 
1156 struct amdgpu_gfxoff_quirk {
1157 	u16 chip_vendor;
1158 	u16 chip_device;
1159 	u16 subsys_vendor;
1160 	u16 subsys_device;
1161 	u8 revision;
1162 };
1163 
1164 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
1165 	/* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */
1166 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1167 	/* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */
1168 	{ 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
1169 	/* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
1170 	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
1171 	/* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */
1172 	{ 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },
1173 	{ 0, 0, 0, 0, 0 },
1174 };
1175 
1176 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev)
1177 {
1178 	const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list;
1179 
1180 	while (p && p->chip_device != 0) {
1181 		if (pdev->vendor == p->chip_vendor &&
1182 		    pdev->device == p->chip_device &&
1183 		    pdev->subsystem_vendor == p->subsys_vendor &&
1184 		    pdev->subsystem_device == p->subsys_device &&
1185 		    pdev->revision == p->revision) {
1186 			return true;
1187 		}
1188 		++p;
1189 	}
1190 	return false;
1191 }
1192 
1193 static bool is_raven_kicker(struct amdgpu_device *adev)
1194 {
1195 	if (adev->pm.fw_version >= 0x41e2b)
1196 		return true;
1197 	else
1198 		return false;
1199 }
1200 
1201 static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
1202 {
1203 	if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) &&
1204 	    (adev->gfx.me_fw_version >= 0x000000a5) &&
1205 	    (adev->gfx.me_feature_version >= 52))
1206 		return true;
1207 	else
1208 		return false;
1209 }
1210 
1211 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
1212 {
1213 	if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
1214 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1215 
1216 	switch (adev->ip_versions[GC_HWIP][0]) {
1217 	case IP_VERSION(9, 0, 1):
1218 	case IP_VERSION(9, 2, 1):
1219 	case IP_VERSION(9, 4, 0):
1220 		break;
1221 	case IP_VERSION(9, 2, 2):
1222 	case IP_VERSION(9, 1, 0):
1223 		if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1224 		      (adev->apu_flags & AMD_APU_IS_PICASSO)) &&
1225 		    ((!is_raven_kicker(adev) &&
1226 		      adev->gfx.rlc_fw_version < 531) ||
1227 		     (adev->gfx.rlc_feature_version < 1) ||
1228 		     !adev->gfx.rlc.is_rlc_v2_1))
1229 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1230 
1231 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1232 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1233 				AMD_PG_SUPPORT_CP |
1234 				AMD_PG_SUPPORT_RLC_SMU_HS;
1235 		break;
1236 	case IP_VERSION(9, 3, 0):
1237 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
1238 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1239 				AMD_PG_SUPPORT_CP |
1240 				AMD_PG_SUPPORT_RLC_SMU_HS;
1241 		break;
1242 	default:
1243 		break;
1244 	}
1245 }
1246 
1247 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
1248 					  char *chip_name)
1249 {
1250 	char fw_name[30];
1251 	int err;
1252 
1253 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1254 	err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
1255 	if (err)
1256 		goto out;
1257 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
1258 
1259 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1260 	err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1261 	if (err)
1262 		goto out;
1263 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
1264 
1265 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1266 	err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1267 	if (err)
1268 		goto out;
1269 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
1270 
1271 out:
1272 	if (err) {
1273 		amdgpu_ucode_release(&adev->gfx.pfp_fw);
1274 		amdgpu_ucode_release(&adev->gfx.me_fw);
1275 		amdgpu_ucode_release(&adev->gfx.ce_fw);
1276 	}
1277 	return err;
1278 }
1279 
1280 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
1281 				       char *chip_name)
1282 {
1283 	char fw_name[30];
1284 	int err;
1285 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
1286 	uint16_t version_major;
1287 	uint16_t version_minor;
1288 	uint32_t smu_version;
1289 
1290 	/*
1291 	 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
1292 	 * instead of picasso_rlc.bin.
1293 	 * Judgment method:
1294 	 * PCO AM4: revision >= 0xC8 && revision <= 0xCF
1295 	 *          or revision >= 0xD8 && revision <= 0xDF
1296 	 * otherwise is PCO FP5
1297 	 */
1298 	if (!strcmp(chip_name, "picasso") &&
1299 		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
1300 		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
1301 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
1302 	else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) &&
1303 		(smu_version >= 0x41e2b))
1304 		/**
1305 		*SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
1306 		*/
1307 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
1308 	else
1309 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1310 	err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
1311 	if (err)
1312 		goto out;
1313 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1314 
1315 	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1316 	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1317 	err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
1318 out:
1319 	if (err)
1320 		amdgpu_ucode_release(&adev->gfx.rlc_fw);
1321 
1322 	return err;
1323 }
1324 
1325 static bool gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev)
1326 {
1327 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ||
1328 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
1329 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0))
1330 		return false;
1331 
1332 	return true;
1333 }
1334 
1335 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
1336 					      char *chip_name)
1337 {
1338 	char fw_name[30];
1339 	int err;
1340 
1341 	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
1342 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name);
1343 	else
1344 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1345 
1346 	err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1347 	if (err)
1348 		goto out;
1349 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
1350 	amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
1351 
1352 	if (gfx_v9_0_load_mec2_fw_bin_support(adev)) {
1353 		if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_ALDEBARAN))
1354 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name);
1355 		else
1356 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1357 
1358 		/* ignore failures to load */
1359 		err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1360 		if (!err) {
1361 			amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
1362 			amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
1363 		} else {
1364 			err = 0;
1365 			amdgpu_ucode_release(&adev->gfx.mec2_fw);
1366 		}
1367 	} else {
1368 		adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
1369 		adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
1370 	}
1371 
1372 	gfx_v9_0_check_if_need_gfxoff(adev);
1373 	gfx_v9_0_check_fw_write_wait(adev);
1374 
1375 out:
1376 	if (err)
1377 		amdgpu_ucode_release(&adev->gfx.mec_fw);
1378 	return err;
1379 }
1380 
1381 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
1382 {
1383 	char ucode_prefix[30];
1384 	int r;
1385 
1386 	DRM_DEBUG("\n");
1387 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
1388 
1389 	/* No CPG in Arcturus */
1390 	if (adev->gfx.num_gfx_rings) {
1391 		r = gfx_v9_0_init_cp_gfx_microcode(adev, ucode_prefix);
1392 		if (r)
1393 			return r;
1394 	}
1395 
1396 	r = gfx_v9_0_init_rlc_microcode(adev, ucode_prefix);
1397 	if (r)
1398 		return r;
1399 
1400 	r = gfx_v9_0_init_cp_compute_microcode(adev, ucode_prefix);
1401 	if (r)
1402 		return r;
1403 
1404 	return r;
1405 }
1406 
1407 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
1408 {
1409 	u32 count = 0;
1410 	const struct cs_section_def *sect = NULL;
1411 	const struct cs_extent_def *ext = NULL;
1412 
1413 	/* begin clear state */
1414 	count += 2;
1415 	/* context control state */
1416 	count += 3;
1417 
1418 	for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
1419 		for (ext = sect->section; ext->extent != NULL; ++ext) {
1420 			if (sect->id == SECT_CONTEXT)
1421 				count += 2 + ext->reg_count;
1422 			else
1423 				return 0;
1424 		}
1425 	}
1426 
1427 	/* end clear state */
1428 	count += 2;
1429 	/* clear state */
1430 	count += 2;
1431 
1432 	return count;
1433 }
1434 
1435 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
1436 				    volatile u32 *buffer)
1437 {
1438 	u32 count = 0, i;
1439 	const struct cs_section_def *sect = NULL;
1440 	const struct cs_extent_def *ext = NULL;
1441 
1442 	if (adev->gfx.rlc.cs_data == NULL)
1443 		return;
1444 	if (buffer == NULL)
1445 		return;
1446 
1447 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1448 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1449 
1450 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1451 	buffer[count++] = cpu_to_le32(0x80000000);
1452 	buffer[count++] = cpu_to_le32(0x80000000);
1453 
1454 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1455 		for (ext = sect->section; ext->extent != NULL; ++ext) {
1456 			if (sect->id == SECT_CONTEXT) {
1457 				buffer[count++] =
1458 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1459 				buffer[count++] = cpu_to_le32(ext->reg_index -
1460 						PACKET3_SET_CONTEXT_REG_START);
1461 				for (i = 0; i < ext->reg_count; i++)
1462 					buffer[count++] = cpu_to_le32(ext->extent[i]);
1463 			} else {
1464 				return;
1465 			}
1466 		}
1467 	}
1468 
1469 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1470 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1471 
1472 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1473 	buffer[count++] = cpu_to_le32(0);
1474 }
1475 
1476 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev)
1477 {
1478 	struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1479 	uint32_t pg_always_on_cu_num = 2;
1480 	uint32_t always_on_cu_num;
1481 	uint32_t i, j, k;
1482 	uint32_t mask, cu_bitmap, counter;
1483 
1484 	if (adev->flags & AMD_IS_APU)
1485 		always_on_cu_num = 4;
1486 	else if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1))
1487 		always_on_cu_num = 8;
1488 	else
1489 		always_on_cu_num = 12;
1490 
1491 	mutex_lock(&adev->grbm_idx_mutex);
1492 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1493 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1494 			mask = 1;
1495 			cu_bitmap = 0;
1496 			counter = 0;
1497 			amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0);
1498 
1499 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1500 				if (cu_info->bitmap[i][j] & mask) {
1501 					if (counter == pg_always_on_cu_num)
1502 						WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap);
1503 					if (counter < always_on_cu_num)
1504 						cu_bitmap |= mask;
1505 					else
1506 						break;
1507 					counter++;
1508 				}
1509 				mask <<= 1;
1510 			}
1511 
1512 			WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap);
1513 			cu_info->ao_cu_bitmap[i][j] = cu_bitmap;
1514 		}
1515 	}
1516 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1517 	mutex_unlock(&adev->grbm_idx_mutex);
1518 }
1519 
1520 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
1521 {
1522 	uint32_t data;
1523 
1524 	/* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1525 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1526 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
1527 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1528 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
1529 
1530 	/* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1531 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1532 
1533 	/* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1534 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
1535 
1536 	mutex_lock(&adev->grbm_idx_mutex);
1537 	/* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1538 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1539 	WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1540 
1541 	/* set mmRLC_LB_PARAMS = 0x003F_1006 */
1542 	data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1543 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1544 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1545 	WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1546 
1547 	/* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1548 	data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1549 	data &= 0x0000FFFF;
1550 	data |= 0x00C00000;
1551 	WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1552 
1553 	/*
1554 	 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven),
1555 	 * programmed in gfx_v9_0_init_always_on_cu_mask()
1556 	 */
1557 
1558 	/* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1559 	 * but used for RLC_LB_CNTL configuration */
1560 	data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1561 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1562 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1563 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1564 	mutex_unlock(&adev->grbm_idx_mutex);
1565 
1566 	gfx_v9_0_init_always_on_cu_mask(adev);
1567 }
1568 
1569 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev)
1570 {
1571 	uint32_t data;
1572 
1573 	/* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
1574 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
1575 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8);
1576 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
1577 	WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16));
1578 
1579 	/* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
1580 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
1581 
1582 	/* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1583 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
1584 
1585 	mutex_lock(&adev->grbm_idx_mutex);
1586 	/* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
1587 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1588 	WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
1589 
1590 	/* set mmRLC_LB_PARAMS = 0x003F_1006 */
1591 	data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
1592 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
1593 	data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
1594 	WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
1595 
1596 	/* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
1597 	data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
1598 	data &= 0x0000FFFF;
1599 	data |= 0x00C00000;
1600 	WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
1601 
1602 	/*
1603 	 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON),
1604 	 * programmed in gfx_v9_0_init_always_on_cu_mask()
1605 	 */
1606 
1607 	/* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1608 	 * but used for RLC_LB_CNTL configuration */
1609 	data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
1610 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1611 	data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1612 	WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1613 	mutex_unlock(&adev->grbm_idx_mutex);
1614 
1615 	gfx_v9_0_init_always_on_cu_mask(adev);
1616 }
1617 
1618 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
1619 {
1620 	WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
1621 }
1622 
1623 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev)
1624 {
1625 	if (gfx_v9_0_load_mec2_fw_bin_support(adev))
1626 		return 5;
1627 	else
1628 		return 4;
1629 }
1630 
1631 static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1632 {
1633 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1634 
1635 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
1636 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
1637 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
1638 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
1639 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
1640 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
1641 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
1642 	reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
1643 	adev->gfx.rlc.rlcg_reg_access_supported = true;
1644 }
1645 
1646 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1647 {
1648 	const struct cs_section_def *cs_data;
1649 	int r;
1650 
1651 	adev->gfx.rlc.cs_data = gfx9_cs_data;
1652 
1653 	cs_data = adev->gfx.rlc.cs_data;
1654 
1655 	if (cs_data) {
1656 		/* init clear state block */
1657 		r = amdgpu_gfx_rlc_init_csb(adev);
1658 		if (r)
1659 			return r;
1660 	}
1661 
1662 	if (adev->flags & AMD_IS_APU) {
1663 		/* TODO: double check the cp_table_size for RV */
1664 		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1665 		r = amdgpu_gfx_rlc_init_cpt(adev);
1666 		if (r)
1667 			return r;
1668 	}
1669 
1670 	switch (adev->ip_versions[GC_HWIP][0]) {
1671 	case IP_VERSION(9, 2, 2):
1672 	case IP_VERSION(9, 1, 0):
1673 		gfx_v9_0_init_lbpw(adev);
1674 		break;
1675 	case IP_VERSION(9, 4, 0):
1676 		gfx_v9_4_init_lbpw(adev);
1677 		break;
1678 	default:
1679 		break;
1680 	}
1681 
1682 	/* init spm vmid with 0xf */
1683 	if (adev->gfx.rlc.funcs->update_spm_vmid)
1684 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1685 
1686 	return 0;
1687 }
1688 
1689 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1690 {
1691 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1692 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1693 }
1694 
1695 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1696 {
1697 	int r;
1698 	u32 *hpd;
1699 	const __le32 *fw_data;
1700 	unsigned fw_size;
1701 	u32 *fw;
1702 	size_t mec_hpd_size;
1703 
1704 	const struct gfx_firmware_header_v1_0 *mec_hdr;
1705 
1706 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1707 
1708 	/* take ownership of the relevant compute queues */
1709 	amdgpu_gfx_compute_queue_acquire(adev);
1710 	mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1711 	if (mec_hpd_size) {
1712 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1713 					      AMDGPU_GEM_DOMAIN_VRAM |
1714 					      AMDGPU_GEM_DOMAIN_GTT,
1715 					      &adev->gfx.mec.hpd_eop_obj,
1716 					      &adev->gfx.mec.hpd_eop_gpu_addr,
1717 					      (void **)&hpd);
1718 		if (r) {
1719 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1720 			gfx_v9_0_mec_fini(adev);
1721 			return r;
1722 		}
1723 
1724 		memset(hpd, 0, mec_hpd_size);
1725 
1726 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1727 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1728 	}
1729 
1730 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1731 
1732 	fw_data = (const __le32 *)
1733 		(adev->gfx.mec_fw->data +
1734 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1735 	fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1736 
1737 	r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1738 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1739 				      &adev->gfx.mec.mec_fw_obj,
1740 				      &adev->gfx.mec.mec_fw_gpu_addr,
1741 				      (void **)&fw);
1742 	if (r) {
1743 		dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1744 		gfx_v9_0_mec_fini(adev);
1745 		return r;
1746 	}
1747 
1748 	memcpy(fw, fw_data, fw_size);
1749 
1750 	amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1751 	amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1752 
1753 	return 0;
1754 }
1755 
1756 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1757 {
1758 	WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
1759 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1760 		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1761 		(address << SQ_IND_INDEX__INDEX__SHIFT) |
1762 		(SQ_IND_INDEX__FORCE_READ_MASK));
1763 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1764 }
1765 
1766 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1767 			   uint32_t wave, uint32_t thread,
1768 			   uint32_t regno, uint32_t num, uint32_t *out)
1769 {
1770 	WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX,
1771 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1772 		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1773 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
1774 		(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1775 		(SQ_IND_INDEX__FORCE_READ_MASK) |
1776 		(SQ_IND_INDEX__AUTO_INCR_MASK));
1777 	while (num--)
1778 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1779 }
1780 
1781 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1782 {
1783 	/* type 1 wave data */
1784 	dst[(*no_fields)++] = 1;
1785 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1786 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1787 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1788 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1789 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1790 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1791 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1792 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1793 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1794 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1795 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1796 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1797 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1798 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1799 	dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
1800 }
1801 
1802 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
1803 				     uint32_t wave, uint32_t start,
1804 				     uint32_t size, uint32_t *dst)
1805 {
1806 	wave_read_regs(
1807 		adev, simd, wave, 0,
1808 		start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1809 }
1810 
1811 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
1812 				     uint32_t wave, uint32_t thread,
1813 				     uint32_t start, uint32_t size,
1814 				     uint32_t *dst)
1815 {
1816 	wave_read_regs(
1817 		adev, simd, wave, thread,
1818 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1819 }
1820 
1821 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1822 				  u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
1823 {
1824 	soc15_grbm_select(adev, me, pipe, q, vm, 0);
1825 }
1826 
1827 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1828         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1829         .select_se_sh = &gfx_v9_0_select_se_sh,
1830         .read_wave_data = &gfx_v9_0_read_wave_data,
1831         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1832         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1833         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
1834 };
1835 
1836 const struct amdgpu_ras_block_hw_ops  gfx_v9_0_ras_ops = {
1837 		.ras_error_inject = &gfx_v9_0_ras_error_inject,
1838 		.query_ras_error_count = &gfx_v9_0_query_ras_error_count,
1839 		.reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,
1840 };
1841 
1842 static struct amdgpu_gfx_ras gfx_v9_0_ras = {
1843 	.ras_block = {
1844 		.hw_ops = &gfx_v9_0_ras_ops,
1845 	},
1846 };
1847 
1848 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1849 {
1850 	u32 gb_addr_config;
1851 	int err;
1852 
1853 	switch (adev->ip_versions[GC_HWIP][0]) {
1854 	case IP_VERSION(9, 0, 1):
1855 		adev->gfx.config.max_hw_contexts = 8;
1856 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1857 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1858 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1859 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1860 		gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1861 		break;
1862 	case IP_VERSION(9, 2, 1):
1863 		adev->gfx.config.max_hw_contexts = 8;
1864 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1865 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1866 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1867 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1868 		gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1869 		DRM_INFO("fix gfx.config for vega12\n");
1870 		break;
1871 	case IP_VERSION(9, 4, 0):
1872 		adev->gfx.ras = &gfx_v9_0_ras;
1873 		adev->gfx.config.max_hw_contexts = 8;
1874 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1875 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1876 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1877 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1878 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1879 		gb_addr_config &= ~0xf3e777ff;
1880 		gb_addr_config |= 0x22014042;
1881 		/* check vbios table if gpu info is not available */
1882 		err = amdgpu_atomfirmware_get_gfx_info(adev);
1883 		if (err)
1884 			return err;
1885 		break;
1886 	case IP_VERSION(9, 2, 2):
1887 	case IP_VERSION(9, 1, 0):
1888 		adev->gfx.config.max_hw_contexts = 8;
1889 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1890 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1891 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1892 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1893 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1894 			gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1895 		else
1896 			gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1897 		break;
1898 	case IP_VERSION(9, 4, 1):
1899 		adev->gfx.ras = &gfx_v9_4_ras;
1900 		adev->gfx.config.max_hw_contexts = 8;
1901 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1902 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1903 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1904 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1905 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1906 		gb_addr_config &= ~0xf3e777ff;
1907 		gb_addr_config |= 0x22014042;
1908 		break;
1909 	case IP_VERSION(9, 3, 0):
1910 		adev->gfx.config.max_hw_contexts = 8;
1911 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1912 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1913 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
1914 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1915 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1916 		gb_addr_config &= ~0xf3e777ff;
1917 		gb_addr_config |= 0x22010042;
1918 		break;
1919 	case IP_VERSION(9, 4, 2):
1920 		adev->gfx.ras = &gfx_v9_4_2_ras;
1921 		adev->gfx.config.max_hw_contexts = 8;
1922 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1923 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1924 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1925 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1926 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1927 		gb_addr_config &= ~0xf3e777ff;
1928 		gb_addr_config |= 0x22014042;
1929 		/* check vbios table if gpu info is not available */
1930 		err = amdgpu_atomfirmware_get_gfx_info(adev);
1931 		if (err)
1932 			return err;
1933 		break;
1934 	default:
1935 		BUG();
1936 		break;
1937 	}
1938 
1939 	adev->gfx.config.gb_addr_config = gb_addr_config;
1940 
1941 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1942 			REG_GET_FIELD(
1943 					adev->gfx.config.gb_addr_config,
1944 					GB_ADDR_CONFIG,
1945 					NUM_PIPES);
1946 
1947 	adev->gfx.config.max_tile_pipes =
1948 		adev->gfx.config.gb_addr_config_fields.num_pipes;
1949 
1950 	adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1951 			REG_GET_FIELD(
1952 					adev->gfx.config.gb_addr_config,
1953 					GB_ADDR_CONFIG,
1954 					NUM_BANKS);
1955 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1956 			REG_GET_FIELD(
1957 					adev->gfx.config.gb_addr_config,
1958 					GB_ADDR_CONFIG,
1959 					MAX_COMPRESSED_FRAGS);
1960 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1961 			REG_GET_FIELD(
1962 					adev->gfx.config.gb_addr_config,
1963 					GB_ADDR_CONFIG,
1964 					NUM_RB_PER_SE);
1965 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1966 			REG_GET_FIELD(
1967 					adev->gfx.config.gb_addr_config,
1968 					GB_ADDR_CONFIG,
1969 					NUM_SHADER_ENGINES);
1970 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1971 			REG_GET_FIELD(
1972 					adev->gfx.config.gb_addr_config,
1973 					GB_ADDR_CONFIG,
1974 					PIPE_INTERLEAVE_SIZE));
1975 
1976 	return 0;
1977 }
1978 
1979 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1980 				      int mec, int pipe, int queue)
1981 {
1982 	unsigned irq_type;
1983 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1984 	unsigned int hw_prio;
1985 
1986 	ring = &adev->gfx.compute_ring[ring_id];
1987 
1988 	/* mec0 is me1 */
1989 	ring->me = mec + 1;
1990 	ring->pipe = pipe;
1991 	ring->queue = queue;
1992 
1993 	ring->ring_obj = NULL;
1994 	ring->use_doorbell = true;
1995 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1996 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1997 				+ (ring_id * GFX9_MEC_HPD_SIZE);
1998 	ring->vm_hub = AMDGPU_GFXHUB(0);
1999 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
2000 
2001 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
2002 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
2003 		+ ring->pipe;
2004 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
2005 			AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
2006 	/* type-2 packets are deprecated on MEC, use type-3 instead */
2007 	return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
2008 				hw_prio, NULL);
2009 }
2010 
2011 static int gfx_v9_0_sw_init(void *handle)
2012 {
2013 	int i, j, k, r, ring_id;
2014 	struct amdgpu_ring *ring;
2015 	struct amdgpu_kiq *kiq;
2016 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2017 	unsigned int hw_prio;
2018 
2019 	switch (adev->ip_versions[GC_HWIP][0]) {
2020 	case IP_VERSION(9, 0, 1):
2021 	case IP_VERSION(9, 2, 1):
2022 	case IP_VERSION(9, 4, 0):
2023 	case IP_VERSION(9, 2, 2):
2024 	case IP_VERSION(9, 1, 0):
2025 	case IP_VERSION(9, 4, 1):
2026 	case IP_VERSION(9, 3, 0):
2027 	case IP_VERSION(9, 4, 2):
2028 		adev->gfx.mec.num_mec = 2;
2029 		break;
2030 	default:
2031 		adev->gfx.mec.num_mec = 1;
2032 		break;
2033 	}
2034 
2035 	adev->gfx.mec.num_pipe_per_mec = 4;
2036 	adev->gfx.mec.num_queue_per_pipe = 8;
2037 
2038 	/* EOP Event */
2039 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
2040 	if (r)
2041 		return r;
2042 
2043 	/* Privileged reg */
2044 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
2045 			      &adev->gfx.priv_reg_irq);
2046 	if (r)
2047 		return r;
2048 
2049 	/* Privileged inst */
2050 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
2051 			      &adev->gfx.priv_inst_irq);
2052 	if (r)
2053 		return r;
2054 
2055 	/* ECC error */
2056 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR,
2057 			      &adev->gfx.cp_ecc_error_irq);
2058 	if (r)
2059 		return r;
2060 
2061 	/* FUE error */
2062 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR,
2063 			      &adev->gfx.cp_ecc_error_irq);
2064 	if (r)
2065 		return r;
2066 
2067 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2068 
2069 	if (adev->gfx.rlc.funcs) {
2070 		if (adev->gfx.rlc.funcs->init) {
2071 			r = adev->gfx.rlc.funcs->init(adev);
2072 			if (r) {
2073 				dev_err(adev->dev, "Failed to init rlc BOs!\n");
2074 				return r;
2075 			}
2076 		}
2077 	}
2078 
2079 	r = gfx_v9_0_mec_init(adev);
2080 	if (r) {
2081 		DRM_ERROR("Failed to init MEC BOs!\n");
2082 		return r;
2083 	}
2084 
2085 	/* set up the gfx ring */
2086 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2087 		ring = &adev->gfx.gfx_ring[i];
2088 		ring->ring_obj = NULL;
2089 		if (!i)
2090 			sprintf(ring->name, "gfx");
2091 		else
2092 			sprintf(ring->name, "gfx_%d", i);
2093 		ring->use_doorbell = true;
2094 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
2095 
2096 		/* disable scheduler on the real ring */
2097 		ring->no_scheduler = true;
2098 		ring->vm_hub = AMDGPU_GFXHUB(0);
2099 		r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2100 				     AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2101 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
2102 		if (r)
2103 			return r;
2104 	}
2105 
2106 	/* set up the software rings */
2107 	if (adev->gfx.num_gfx_rings) {
2108 		for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) {
2109 			ring = &adev->gfx.sw_gfx_ring[i];
2110 			ring->ring_obj = NULL;
2111 			sprintf(ring->name, amdgpu_sw_ring_name(i));
2112 			ring->use_doorbell = true;
2113 			ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
2114 			ring->is_sw_ring = true;
2115 			hw_prio = amdgpu_sw_ring_priority(i);
2116 			ring->vm_hub = AMDGPU_GFXHUB(0);
2117 			r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2118 					     AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, hw_prio,
2119 					     NULL);
2120 			if (r)
2121 				return r;
2122 			ring->wptr = 0;
2123 		}
2124 
2125 		/* init the muxer and add software rings */
2126 		r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0],
2127 					 GFX9_NUM_SW_GFX_RINGS);
2128 		if (r) {
2129 			DRM_ERROR("amdgpu_ring_mux_init failed(%d)\n", r);
2130 			return r;
2131 		}
2132 		for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) {
2133 			r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer,
2134 							&adev->gfx.sw_gfx_ring[i]);
2135 			if (r) {
2136 				DRM_ERROR("amdgpu_ring_mux_add_sw_ring failed(%d)\n", r);
2137 				return r;
2138 			}
2139 		}
2140 	}
2141 
2142 	/* set up the compute queues - allocate horizontally across pipes */
2143 	ring_id = 0;
2144 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2145 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2146 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2147 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
2148 								     k, j))
2149 					continue;
2150 
2151 				r = gfx_v9_0_compute_ring_init(adev,
2152 							       ring_id,
2153 							       i, k, j);
2154 				if (r)
2155 					return r;
2156 
2157 				ring_id++;
2158 			}
2159 		}
2160 	}
2161 
2162 	r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0);
2163 	if (r) {
2164 		DRM_ERROR("Failed to init KIQ BOs!\n");
2165 		return r;
2166 	}
2167 
2168 	kiq = &adev->gfx.kiq[0];
2169 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
2170 	if (r)
2171 		return r;
2172 
2173 	/* create MQD for all compute queues as wel as KIQ for SRIOV case */
2174 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation), 0);
2175 	if (r)
2176 		return r;
2177 
2178 	adev->gfx.ce_ram_size = 0x8000;
2179 
2180 	r = gfx_v9_0_gpu_early_init(adev);
2181 	if (r)
2182 		return r;
2183 
2184 	if (amdgpu_gfx_ras_sw_init(adev)) {
2185 		dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
2186 		return -EINVAL;
2187 	}
2188 
2189 	return 0;
2190 }
2191 
2192 
2193 static int gfx_v9_0_sw_fini(void *handle)
2194 {
2195 	int i;
2196 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2197 
2198 	if (adev->gfx.num_gfx_rings) {
2199 		for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++)
2200 			amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]);
2201 		amdgpu_ring_mux_fini(&adev->gfx.muxer);
2202 	}
2203 
2204 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2205 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2206 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
2207 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2208 
2209 	amdgpu_gfx_mqd_sw_fini(adev, 0);
2210 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
2211 	amdgpu_gfx_kiq_fini(adev, 0);
2212 
2213 	gfx_v9_0_mec_fini(adev);
2214 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2215 				&adev->gfx.rlc.clear_state_gpu_addr,
2216 				(void **)&adev->gfx.rlc.cs_ptr);
2217 	if (adev->flags & AMD_IS_APU) {
2218 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2219 				&adev->gfx.rlc.cp_table_gpu_addr,
2220 				(void **)&adev->gfx.rlc.cp_table_ptr);
2221 	}
2222 	gfx_v9_0_free_microcode(adev);
2223 
2224 	return 0;
2225 }
2226 
2227 
2228 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
2229 {
2230 	/* TODO */
2231 }
2232 
2233 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
2234 			   u32 instance, int xcc_id)
2235 {
2236 	u32 data;
2237 
2238 	if (instance == 0xffffffff)
2239 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2240 	else
2241 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
2242 
2243 	if (se_num == 0xffffffff)
2244 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2245 	else
2246 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2247 
2248 	if (sh_num == 0xffffffff)
2249 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2250 	else
2251 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2252 
2253 	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
2254 }
2255 
2256 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
2257 {
2258 	u32 data, mask;
2259 
2260 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
2261 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
2262 
2263 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2264 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2265 
2266 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2267 					 adev->gfx.config.max_sh_per_se);
2268 
2269 	return (~data) & mask;
2270 }
2271 
2272 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
2273 {
2274 	int i, j;
2275 	u32 data;
2276 	u32 active_rbs = 0;
2277 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2278 					adev->gfx.config.max_sh_per_se;
2279 
2280 	mutex_lock(&adev->grbm_idx_mutex);
2281 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2282 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2283 			amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0);
2284 			data = gfx_v9_0_get_rb_active_bitmap(adev);
2285 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2286 					       rb_bitmap_width_per_sh);
2287 		}
2288 	}
2289 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
2290 	mutex_unlock(&adev->grbm_idx_mutex);
2291 
2292 	adev->gfx.config.backend_enable_mask = active_rbs;
2293 	adev->gfx.config.num_rbs = hweight32(active_rbs);
2294 }
2295 
2296 static void gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev,
2297 				uint32_t first_vmid,
2298 				uint32_t last_vmid)
2299 {
2300 	uint32_t data;
2301 	uint32_t trap_config_vmid_mask = 0;
2302 	int i;
2303 
2304 	/* Calculate trap config vmid mask */
2305 	for (i = first_vmid; i < last_vmid; i++)
2306 		trap_config_vmid_mask |= (1 << i);
2307 
2308 	data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
2309 			VMID_SEL, trap_config_vmid_mask);
2310 	data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
2311 			TRAP_EN, 1);
2312 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
2313 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
2314 
2315 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
2316 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
2317 }
2318 
2319 #define DEFAULT_SH_MEM_BASES	(0x6000)
2320 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
2321 {
2322 	int i;
2323 	uint32_t sh_mem_config;
2324 	uint32_t sh_mem_bases;
2325 
2326 	/*
2327 	 * Configure apertures:
2328 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2329 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2330 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2331 	 */
2332 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2333 
2334 	sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
2335 			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2336 			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
2337 
2338 	mutex_lock(&adev->srbm_mutex);
2339 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
2340 		soc15_grbm_select(adev, 0, 0, 0, i, 0);
2341 		/* CP and shaders */
2342 		WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
2343 		WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2344 	}
2345 	soc15_grbm_select(adev, 0, 0, 0, 0, 0);
2346 	mutex_unlock(&adev->srbm_mutex);
2347 
2348 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
2349 	   access. These should be enabled by FW for target VMIDs. */
2350 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
2351 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
2352 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
2353 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
2354 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
2355 	}
2356 }
2357 
2358 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
2359 {
2360 	int vmid;
2361 
2362 	/*
2363 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2364 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
2365 	 * the driver can enable them for graphics. VMID0 should maintain
2366 	 * access so that HWS firmware can save/restore entries.
2367 	 */
2368 	for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
2369 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
2370 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
2371 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
2372 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
2373 	}
2374 }
2375 
2376 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev)
2377 {
2378 	uint32_t tmp;
2379 
2380 	switch (adev->ip_versions[GC_HWIP][0]) {
2381 	case IP_VERSION(9, 4, 1):
2382 		tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG);
2383 		tmp = REG_SET_FIELD(tmp, SQ_CONFIG, DISABLE_BARRIER_WAITCNT,
2384 				!READ_ONCE(adev->barrier_has_auto_waitcnt));
2385 		WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp);
2386 		break;
2387 	default:
2388 		break;
2389 	}
2390 }
2391 
2392 static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
2393 {
2394 	u32 tmp;
2395 	int i;
2396 
2397 	WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
2398 
2399 	gfx_v9_0_tiling_mode_table_init(adev);
2400 
2401 	if (adev->gfx.num_gfx_rings)
2402 		gfx_v9_0_setup_rb(adev);
2403 	gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
2404 	adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
2405 
2406 	/* XXX SH_MEM regs */
2407 	/* where to put LDS, scratch, GPUVM in FSA64 space */
2408 	mutex_lock(&adev->srbm_mutex);
2409 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
2410 		soc15_grbm_select(adev, 0, 0, 0, i, 0);
2411 		/* CP and shaders */
2412 		if (i == 0) {
2413 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2414 					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2415 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2416 					    !!adev->gmc.noretry);
2417 			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2418 			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0);
2419 		} else {
2420 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2421 					    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2422 			tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
2423 					    !!adev->gmc.noretry);
2424 			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp);
2425 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2426 				(adev->gmc.private_aperture_start >> 48));
2427 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
2428 				(adev->gmc.shared_aperture_start >> 48));
2429 			WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp);
2430 		}
2431 	}
2432 	soc15_grbm_select(adev, 0, 0, 0, 0, 0);
2433 
2434 	mutex_unlock(&adev->srbm_mutex);
2435 
2436 	gfx_v9_0_init_compute_vmid(adev);
2437 	gfx_v9_0_init_gds_vmid(adev);
2438 	gfx_v9_0_init_sq_config(adev);
2439 }
2440 
2441 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2442 {
2443 	u32 i, j, k;
2444 	u32 mask;
2445 
2446 	mutex_lock(&adev->grbm_idx_mutex);
2447 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2448 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2449 			amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0);
2450 			for (k = 0; k < adev->usec_timeout; k++) {
2451 				if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2452 					break;
2453 				udelay(1);
2454 			}
2455 			if (k == adev->usec_timeout) {
2456 				amdgpu_gfx_select_se_sh(adev, 0xffffffff,
2457 						      0xffffffff, 0xffffffff, 0);
2458 				mutex_unlock(&adev->grbm_idx_mutex);
2459 				DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
2460 					 i, j);
2461 				return;
2462 			}
2463 		}
2464 	}
2465 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
2466 	mutex_unlock(&adev->grbm_idx_mutex);
2467 
2468 	mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2469 		RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2470 		RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2471 		RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2472 	for (k = 0; k < adev->usec_timeout; k++) {
2473 		if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2474 			break;
2475 		udelay(1);
2476 	}
2477 }
2478 
2479 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2480 					       bool enable)
2481 {
2482 	u32 tmp;
2483 
2484 	/* These interrupts should be enabled to drive DS clock */
2485 
2486 	tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
2487 
2488 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
2489 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
2490 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
2491 	if(adev->gfx.num_gfx_rings)
2492 		tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
2493 
2494 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
2495 }
2496 
2497 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
2498 {
2499 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2500 	/* csib */
2501 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
2502 			adev->gfx.rlc.clear_state_gpu_addr >> 32);
2503 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
2504 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2505 	WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
2506 			adev->gfx.rlc.clear_state_size);
2507 }
2508 
2509 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
2510 				int indirect_offset,
2511 				int list_size,
2512 				int *unique_indirect_regs,
2513 				int unique_indirect_reg_count,
2514 				int *indirect_start_offsets,
2515 				int *indirect_start_offsets_count,
2516 				int max_start_offsets_count)
2517 {
2518 	int idx;
2519 
2520 	for (; indirect_offset < list_size; indirect_offset++) {
2521 		WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
2522 		indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
2523 		*indirect_start_offsets_count = *indirect_start_offsets_count + 1;
2524 
2525 		while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
2526 			indirect_offset += 2;
2527 
2528 			/* look for the matching indice */
2529 			for (idx = 0; idx < unique_indirect_reg_count; idx++) {
2530 				if (unique_indirect_regs[idx] ==
2531 					register_list_format[indirect_offset] ||
2532 					!unique_indirect_regs[idx])
2533 					break;
2534 			}
2535 
2536 			BUG_ON(idx >= unique_indirect_reg_count);
2537 
2538 			if (!unique_indirect_regs[idx])
2539 				unique_indirect_regs[idx] = register_list_format[indirect_offset];
2540 
2541 			indirect_offset++;
2542 		}
2543 	}
2544 }
2545 
2546 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2547 {
2548 	int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2549 	int unique_indirect_reg_count = 0;
2550 
2551 	int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2552 	int indirect_start_offsets_count = 0;
2553 
2554 	int list_size = 0;
2555 	int i = 0, j = 0;
2556 	u32 tmp = 0;
2557 
2558 	u32 *register_list_format =
2559 		kmemdup(adev->gfx.rlc.register_list_format,
2560 			adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2561 	if (!register_list_format)
2562 		return -ENOMEM;
2563 
2564 	/* setup unique_indirect_regs array and indirect_start_offsets array */
2565 	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2566 	gfx_v9_1_parse_ind_reg_list(register_list_format,
2567 				    adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2568 				    adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2569 				    unique_indirect_regs,
2570 				    unique_indirect_reg_count,
2571 				    indirect_start_offsets,
2572 				    &indirect_start_offsets_count,
2573 				    ARRAY_SIZE(indirect_start_offsets));
2574 
2575 	/* enable auto inc in case it is disabled */
2576 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2577 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2578 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2579 
2580 	/* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2581 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2582 		RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2583 	for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2584 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2585 			adev->gfx.rlc.register_restore[i]);
2586 
2587 	/* load indirect register */
2588 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2589 		adev->gfx.rlc.reg_list_format_start);
2590 
2591 	/* direct register portion */
2592 	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2593 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2594 			register_list_format[i]);
2595 
2596 	/* indirect register portion */
2597 	while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2598 		if (register_list_format[i] == 0xFFFFFFFF) {
2599 			WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2600 			continue;
2601 		}
2602 
2603 		WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2604 		WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2605 
2606 		for (j = 0; j < unique_indirect_reg_count; j++) {
2607 			if (register_list_format[i] == unique_indirect_regs[j]) {
2608 				WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2609 				break;
2610 			}
2611 		}
2612 
2613 		BUG_ON(j >= unique_indirect_reg_count);
2614 
2615 		i++;
2616 	}
2617 
2618 	/* set save/restore list size */
2619 	list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2620 	list_size = list_size >> 1;
2621 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2622 		adev->gfx.rlc.reg_restore_list_size);
2623 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2624 
2625 	/* write the starting offsets to RLC scratch ram */
2626 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2627 		adev->gfx.rlc.starting_offsets_start);
2628 	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2629 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2630 		       indirect_start_offsets[i]);
2631 
2632 	/* load unique indirect regs*/
2633 	for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2634 		if (unique_indirect_regs[i] != 0) {
2635 			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2636 			       + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2637 			       unique_indirect_regs[i] & 0x3FFFF);
2638 
2639 			WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2640 			       + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2641 			       unique_indirect_regs[i] >> 20);
2642 		}
2643 	}
2644 
2645 	kfree(register_list_format);
2646 	return 0;
2647 }
2648 
2649 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2650 {
2651 	WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2652 }
2653 
2654 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2655 					     bool enable)
2656 {
2657 	uint32_t data = 0;
2658 	uint32_t default_data = 0;
2659 
2660 	default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2661 	if (enable) {
2662 		/* enable GFXIP control over CGPG */
2663 		data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2664 		if(default_data != data)
2665 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2666 
2667 		/* update status */
2668 		data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2669 		data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2670 		if(default_data != data)
2671 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2672 	} else {
2673 		/* restore GFXIP control over GCPG */
2674 		data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2675 		if(default_data != data)
2676 			WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2677 	}
2678 }
2679 
2680 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2681 {
2682 	uint32_t data = 0;
2683 
2684 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2685 			      AMD_PG_SUPPORT_GFX_SMG |
2686 			      AMD_PG_SUPPORT_GFX_DMG)) {
2687 		/* init IDLE_POLL_COUNT = 60 */
2688 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2689 		data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2690 		data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2691 		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2692 
2693 		/* init RLC PG Delay */
2694 		data = 0;
2695 		data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2696 		data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2697 		data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2698 		data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2699 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2700 
2701 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2702 		data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2703 		data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2704 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2705 
2706 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2707 		data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2708 		data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2709 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2710 
2711 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2712 		data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2713 
2714 		/* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2715 		data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2716 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2717 		if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0))
2718 			pwr_10_0_gfxip_control_over_cgpg(adev, true);
2719 	}
2720 }
2721 
2722 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2723 						bool enable)
2724 {
2725 	uint32_t data = 0;
2726 	uint32_t default_data = 0;
2727 
2728 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2729 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2730 			     SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2731 			     enable ? 1 : 0);
2732 	if (default_data != data)
2733 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2734 }
2735 
2736 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2737 						bool enable)
2738 {
2739 	uint32_t data = 0;
2740 	uint32_t default_data = 0;
2741 
2742 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2743 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2744 			     SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2745 			     enable ? 1 : 0);
2746 	if(default_data != data)
2747 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2748 }
2749 
2750 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2751 					bool enable)
2752 {
2753 	uint32_t data = 0;
2754 	uint32_t default_data = 0;
2755 
2756 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2757 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2758 			     CP_PG_DISABLE,
2759 			     enable ? 0 : 1);
2760 	if(default_data != data)
2761 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2762 }
2763 
2764 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2765 						bool enable)
2766 {
2767 	uint32_t data, default_data;
2768 
2769 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2770 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2771 			     GFX_POWER_GATING_ENABLE,
2772 			     enable ? 1 : 0);
2773 	if(default_data != data)
2774 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2775 }
2776 
2777 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2778 						bool enable)
2779 {
2780 	uint32_t data, default_data;
2781 
2782 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2783 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2784 			     GFX_PIPELINE_PG_ENABLE,
2785 			     enable ? 1 : 0);
2786 	if(default_data != data)
2787 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2788 
2789 	if (!enable)
2790 		/* read any GFX register to wake up GFX */
2791 		data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2792 }
2793 
2794 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2795 						       bool enable)
2796 {
2797 	uint32_t data, default_data;
2798 
2799 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2800 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2801 			     STATIC_PER_CU_PG_ENABLE,
2802 			     enable ? 1 : 0);
2803 	if(default_data != data)
2804 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2805 }
2806 
2807 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2808 						bool enable)
2809 {
2810 	uint32_t data, default_data;
2811 
2812 	default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2813 	data = REG_SET_FIELD(data, RLC_PG_CNTL,
2814 			     DYN_PER_CU_PG_ENABLE,
2815 			     enable ? 1 : 0);
2816 	if(default_data != data)
2817 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2818 }
2819 
2820 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2821 {
2822 	gfx_v9_0_init_csb(adev);
2823 
2824 	/*
2825 	 * Rlc save restore list is workable since v2_1.
2826 	 * And it's needed by gfxoff feature.
2827 	 */
2828 	if (adev->gfx.rlc.is_rlc_v2_1) {
2829 		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1) ||
2830 		    (adev->apu_flags & AMD_APU_IS_RAVEN2))
2831 			gfx_v9_1_init_rlc_save_restore_list(adev);
2832 		gfx_v9_0_enable_save_restore_machine(adev);
2833 	}
2834 
2835 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2836 			      AMD_PG_SUPPORT_GFX_SMG |
2837 			      AMD_PG_SUPPORT_GFX_DMG |
2838 			      AMD_PG_SUPPORT_CP |
2839 			      AMD_PG_SUPPORT_GDS |
2840 			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
2841 		WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE,
2842 			     adev->gfx.rlc.cp_table_gpu_addr >> 8);
2843 		gfx_v9_0_init_gfx_power_gating(adev);
2844 	}
2845 }
2846 
2847 static void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2848 {
2849 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2850 	gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2851 	gfx_v9_0_wait_for_rlc_serdes(adev);
2852 }
2853 
2854 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2855 {
2856 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2857 	udelay(50);
2858 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2859 	udelay(50);
2860 }
2861 
2862 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2863 {
2864 #ifdef AMDGPU_RLC_DEBUG_RETRY
2865 	u32 rlc_ucode_ver;
2866 #endif
2867 
2868 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2869 	udelay(50);
2870 
2871 	/* carrizo do enable cp interrupt after cp inited */
2872 	if (!(adev->flags & AMD_IS_APU)) {
2873 		gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2874 		udelay(50);
2875 	}
2876 
2877 #ifdef AMDGPU_RLC_DEBUG_RETRY
2878 	/* RLC_GPM_GENERAL_6 : RLC Ucode version */
2879 	rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2880 	if(rlc_ucode_ver == 0x108) {
2881 		DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2882 				rlc_ucode_ver, adev->gfx.rlc_fw_version);
2883 		/* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2884 		 * default is 0x9C4 to create a 100us interval */
2885 		WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2886 		/* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2887 		 * to disable the page fault retry interrupts, default is
2888 		 * 0x100 (256) */
2889 		WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2890 	}
2891 #endif
2892 }
2893 
2894 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2895 {
2896 	const struct rlc_firmware_header_v2_0 *hdr;
2897 	const __le32 *fw_data;
2898 	unsigned i, fw_size;
2899 
2900 	if (!adev->gfx.rlc_fw)
2901 		return -EINVAL;
2902 
2903 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2904 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
2905 
2906 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2907 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2908 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2909 
2910 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2911 			RLCG_UCODE_LOADING_START_ADDRESS);
2912 	for (i = 0; i < fw_size; i++)
2913 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2914 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2915 
2916 	return 0;
2917 }
2918 
2919 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2920 {
2921 	int r;
2922 
2923 	if (amdgpu_sriov_vf(adev)) {
2924 		gfx_v9_0_init_csb(adev);
2925 		return 0;
2926 	}
2927 
2928 	adev->gfx.rlc.funcs->stop(adev);
2929 
2930 	/* disable CG */
2931 	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2932 
2933 	gfx_v9_0_init_pg(adev);
2934 
2935 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2936 		/* legacy rlc firmware loading */
2937 		r = gfx_v9_0_rlc_load_microcode(adev);
2938 		if (r)
2939 			return r;
2940 	}
2941 
2942 	switch (adev->ip_versions[GC_HWIP][0]) {
2943 	case IP_VERSION(9, 2, 2):
2944 	case IP_VERSION(9, 1, 0):
2945 		if (amdgpu_lbpw == 0)
2946 			gfx_v9_0_enable_lbpw(adev, false);
2947 		else
2948 			gfx_v9_0_enable_lbpw(adev, true);
2949 		break;
2950 	case IP_VERSION(9, 4, 0):
2951 		if (amdgpu_lbpw > 0)
2952 			gfx_v9_0_enable_lbpw(adev, true);
2953 		else
2954 			gfx_v9_0_enable_lbpw(adev, false);
2955 		break;
2956 	default:
2957 		break;
2958 	}
2959 
2960 	adev->gfx.rlc.funcs->start(adev);
2961 
2962 	return 0;
2963 }
2964 
2965 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2966 {
2967 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2968 
2969 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2970 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2971 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2972 	WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
2973 	udelay(50);
2974 }
2975 
2976 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2977 {
2978 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
2979 	const struct gfx_firmware_header_v1_0 *ce_hdr;
2980 	const struct gfx_firmware_header_v1_0 *me_hdr;
2981 	const __le32 *fw_data;
2982 	unsigned i, fw_size;
2983 
2984 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2985 		return -EINVAL;
2986 
2987 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2988 		adev->gfx.pfp_fw->data;
2989 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2990 		adev->gfx.ce_fw->data;
2991 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
2992 		adev->gfx.me_fw->data;
2993 
2994 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2995 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2996 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2997 
2998 	gfx_v9_0_cp_gfx_enable(adev, false);
2999 
3000 	/* PFP */
3001 	fw_data = (const __le32 *)
3002 		(adev->gfx.pfp_fw->data +
3003 		 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3004 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3005 	WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
3006 	for (i = 0; i < fw_size; i++)
3007 		WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3008 	WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3009 
3010 	/* CE */
3011 	fw_data = (const __le32 *)
3012 		(adev->gfx.ce_fw->data +
3013 		 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3014 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3015 	WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
3016 	for (i = 0; i < fw_size; i++)
3017 		WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3018 	WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3019 
3020 	/* ME */
3021 	fw_data = (const __le32 *)
3022 		(adev->gfx.me_fw->data +
3023 		 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3024 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3025 	WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
3026 	for (i = 0; i < fw_size; i++)
3027 		WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3028 	WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3029 
3030 	return 0;
3031 }
3032 
3033 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
3034 {
3035 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3036 	const struct cs_section_def *sect = NULL;
3037 	const struct cs_extent_def *ext = NULL;
3038 	int r, i, tmp;
3039 
3040 	/* init the CP */
3041 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3042 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
3043 
3044 	gfx_v9_0_cp_gfx_enable(adev, true);
3045 
3046 	r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
3047 	if (r) {
3048 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3049 		return r;
3050 	}
3051 
3052 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3053 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3054 
3055 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3056 	amdgpu_ring_write(ring, 0x80000000);
3057 	amdgpu_ring_write(ring, 0x80000000);
3058 
3059 	for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
3060 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3061 			if (sect->id == SECT_CONTEXT) {
3062 				amdgpu_ring_write(ring,
3063 				       PACKET3(PACKET3_SET_CONTEXT_REG,
3064 					       ext->reg_count));
3065 				amdgpu_ring_write(ring,
3066 				       ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3067 				for (i = 0; i < ext->reg_count; i++)
3068 					amdgpu_ring_write(ring, ext->extent[i]);
3069 			}
3070 		}
3071 	}
3072 
3073 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3074 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3075 
3076 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3077 	amdgpu_ring_write(ring, 0);
3078 
3079 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3080 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3081 	amdgpu_ring_write(ring, 0x8000);
3082 	amdgpu_ring_write(ring, 0x8000);
3083 
3084 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
3085 	tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
3086 		(SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
3087 	amdgpu_ring_write(ring, tmp);
3088 	amdgpu_ring_write(ring, 0);
3089 
3090 	amdgpu_ring_commit(ring);
3091 
3092 	return 0;
3093 }
3094 
3095 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
3096 {
3097 	struct amdgpu_ring *ring;
3098 	u32 tmp;
3099 	u32 rb_bufsz;
3100 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
3101 
3102 	/* Set the write pointer delay */
3103 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
3104 
3105 	/* set the RB to use vmid 0 */
3106 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
3107 
3108 	/* Set ring buffer size */
3109 	ring = &adev->gfx.gfx_ring[0];
3110 	rb_bufsz = order_base_2(ring->ring_size / 8);
3111 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3112 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3113 #ifdef __BIG_ENDIAN
3114 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3115 #endif
3116 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3117 
3118 	/* Initialize the ring buffer's write pointers */
3119 	ring->wptr = 0;
3120 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3121 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3122 
3123 	/* set the wb address wether it's enabled or not */
3124 	rptr_addr = ring->rptr_gpu_addr;
3125 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3126 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3127 
3128 	wptr_gpu_addr = ring->wptr_gpu_addr;
3129 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
3130 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
3131 
3132 	mdelay(1);
3133 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3134 
3135 	rb_addr = ring->gpu_addr >> 8;
3136 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
3137 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3138 
3139 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3140 	if (ring->use_doorbell) {
3141 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3142 				    DOORBELL_OFFSET, ring->doorbell_index);
3143 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3144 				    DOORBELL_EN, 1);
3145 	} else {
3146 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
3147 	}
3148 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
3149 
3150 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3151 			DOORBELL_RANGE_LOWER, ring->doorbell_index);
3152 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3153 
3154 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
3155 		       CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3156 
3157 
3158 	/* start the ring */
3159 	gfx_v9_0_cp_gfx_start(adev);
3160 
3161 	return 0;
3162 }
3163 
3164 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3165 {
3166 	if (enable) {
3167 		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0);
3168 	} else {
3169 		WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL,
3170 			(CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3171 		adev->gfx.kiq[0].ring.sched.ready = false;
3172 	}
3173 	udelay(50);
3174 }
3175 
3176 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3177 {
3178 	const struct gfx_firmware_header_v1_0 *mec_hdr;
3179 	const __le32 *fw_data;
3180 	unsigned i;
3181 	u32 tmp;
3182 
3183 	if (!adev->gfx.mec_fw)
3184 		return -EINVAL;
3185 
3186 	gfx_v9_0_cp_compute_enable(adev, false);
3187 
3188 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3189 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3190 
3191 	fw_data = (const __le32 *)
3192 		(adev->gfx.mec_fw->data +
3193 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3194 	tmp = 0;
3195 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3196 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3197 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
3198 
3199 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
3200 		adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
3201 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
3202 		upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3203 
3204 	/* MEC1 */
3205 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3206 			 mec_hdr->jt_offset);
3207 	for (i = 0; i < mec_hdr->jt_size; i++)
3208 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
3209 			le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3210 
3211 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3212 			adev->gfx.mec_fw_version);
3213 	/* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3214 
3215 	return 0;
3216 }
3217 
3218 /* KIQ functions */
3219 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
3220 {
3221 	uint32_t tmp;
3222 	struct amdgpu_device *adev = ring->adev;
3223 
3224 	/* tell RLC which is KIQ queue */
3225 	tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
3226 	tmp &= 0xffffff00;
3227 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3228 	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3229 	tmp |= 0x80;
3230 	WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
3231 }
3232 
3233 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
3234 {
3235 	struct amdgpu_device *adev = ring->adev;
3236 
3237 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3238 		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
3239 			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
3240 			mqd->cp_hqd_queue_priority =
3241 				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
3242 		}
3243 	}
3244 }
3245 
3246 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
3247 {
3248 	struct amdgpu_device *adev = ring->adev;
3249 	struct v9_mqd *mqd = ring->mqd_ptr;
3250 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3251 	uint32_t tmp;
3252 
3253 	mqd->header = 0xC0310800;
3254 	mqd->compute_pipelinestat_enable = 0x00000001;
3255 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3256 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3257 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3258 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3259 	mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
3260 	mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
3261 	mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
3262 	mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
3263 	mqd->compute_misc_reserved = 0x00000003;
3264 
3265 	mqd->dynamic_cu_mask_addr_lo =
3266 		lower_32_bits(ring->mqd_gpu_addr
3267 			      + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3268 	mqd->dynamic_cu_mask_addr_hi =
3269 		upper_32_bits(ring->mqd_gpu_addr
3270 			      + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
3271 
3272 	eop_base_addr = ring->eop_gpu_addr >> 8;
3273 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3274 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3275 
3276 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3277 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3278 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3279 			(order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
3280 
3281 	mqd->cp_hqd_eop_control = tmp;
3282 
3283 	/* enable doorbell? */
3284 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3285 
3286 	if (ring->use_doorbell) {
3287 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3288 				    DOORBELL_OFFSET, ring->doorbell_index);
3289 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3290 				    DOORBELL_EN, 1);
3291 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3292 				    DOORBELL_SOURCE, 0);
3293 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3294 				    DOORBELL_HIT, 0);
3295 	} else {
3296 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3297 					 DOORBELL_EN, 0);
3298 	}
3299 
3300 	mqd->cp_hqd_pq_doorbell_control = tmp;
3301 
3302 	/* disable the queue if it's active */
3303 	ring->wptr = 0;
3304 	mqd->cp_hqd_dequeue_request = 0;
3305 	mqd->cp_hqd_pq_rptr = 0;
3306 	mqd->cp_hqd_pq_wptr_lo = 0;
3307 	mqd->cp_hqd_pq_wptr_hi = 0;
3308 
3309 	/* set the pointer to the MQD */
3310 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3311 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3312 
3313 	/* set MQD vmid to 0 */
3314 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3315 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3316 	mqd->cp_mqd_control = tmp;
3317 
3318 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3319 	hqd_gpu_addr = ring->gpu_addr >> 8;
3320 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3321 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3322 
3323 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3324 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3325 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3326 			    (order_base_2(ring->ring_size / 4) - 1));
3327 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3328 			(order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3329 #ifdef __BIG_ENDIAN
3330 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3331 #endif
3332 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3333 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3334 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3335 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3336 	mqd->cp_hqd_pq_control = tmp;
3337 
3338 	/* set the wb address whether it's enabled or not */
3339 	wb_gpu_addr = ring->rptr_gpu_addr;
3340 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3341 	mqd->cp_hqd_pq_rptr_report_addr_hi =
3342 		upper_32_bits(wb_gpu_addr) & 0xffff;
3343 
3344 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3345 	wb_gpu_addr = ring->wptr_gpu_addr;
3346 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3347 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3348 
3349 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3350 	ring->wptr = 0;
3351 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3352 
3353 	/* set the vmid for the queue */
3354 	mqd->cp_hqd_vmid = 0;
3355 
3356 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3357 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3358 	mqd->cp_hqd_persistent_state = tmp;
3359 
3360 	/* set MIN_IB_AVAIL_SIZE */
3361 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3362 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3363 	mqd->cp_hqd_ib_control = tmp;
3364 
3365 	/* set static priority for a queue/ring */
3366 	gfx_v9_0_mqd_set_priority(ring, mqd);
3367 	mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);
3368 
3369 	/* map_queues packet doesn't need activate the queue,
3370 	 * so only kiq need set this field.
3371 	 */
3372 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3373 		mqd->cp_hqd_active = 1;
3374 
3375 	return 0;
3376 }
3377 
3378 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
3379 {
3380 	struct amdgpu_device *adev = ring->adev;
3381 	struct v9_mqd *mqd = ring->mqd_ptr;
3382 	int j;
3383 
3384 	/* disable wptr polling */
3385 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3386 
3387 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3388 	       mqd->cp_hqd_eop_base_addr_lo);
3389 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3390 	       mqd->cp_hqd_eop_base_addr_hi);
3391 
3392 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3393 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL,
3394 	       mqd->cp_hqd_eop_control);
3395 
3396 	/* enable doorbell? */
3397 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3398 	       mqd->cp_hqd_pq_doorbell_control);
3399 
3400 	/* disable the queue if it's active */
3401 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3402 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3403 		for (j = 0; j < adev->usec_timeout; j++) {
3404 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3405 				break;
3406 			udelay(1);
3407 		}
3408 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3409 		       mqd->cp_hqd_dequeue_request);
3410 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR,
3411 		       mqd->cp_hqd_pq_rptr);
3412 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3413 		       mqd->cp_hqd_pq_wptr_lo);
3414 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3415 		       mqd->cp_hqd_pq_wptr_hi);
3416 	}
3417 
3418 	/* set the pointer to the MQD */
3419 	WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR,
3420 	       mqd->cp_mqd_base_addr_lo);
3421 	WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3422 	       mqd->cp_mqd_base_addr_hi);
3423 
3424 	/* set MQD vmid to 0 */
3425 	WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL,
3426 	       mqd->cp_mqd_control);
3427 
3428 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3429 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE,
3430 	       mqd->cp_hqd_pq_base_lo);
3431 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI,
3432 	       mqd->cp_hqd_pq_base_hi);
3433 
3434 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3435 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL,
3436 	       mqd->cp_hqd_pq_control);
3437 
3438 	/* set the wb address whether it's enabled or not */
3439 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3440 				mqd->cp_hqd_pq_rptr_report_addr_lo);
3441 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3442 				mqd->cp_hqd_pq_rptr_report_addr_hi);
3443 
3444 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3445 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3446 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
3447 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3448 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
3449 
3450 	/* enable the doorbell if requested */
3451 	if (ring->use_doorbell) {
3452 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3453 					(adev->doorbell_index.kiq * 2) << 2);
3454 		/* If GC has entered CGPG, ringing doorbell > first page
3455 		 * doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
3456 		 * workaround this issue. And this change has to align with firmware
3457 		 * update.
3458 		 */
3459 		if (check_if_enlarge_doorbell_range(adev))
3460 			WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3461 					(adev->doorbell.size - 4));
3462 		else
3463 			WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3464 					(adev->doorbell_index.userqueue_end * 2) << 2);
3465 	}
3466 
3467 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3468 	       mqd->cp_hqd_pq_doorbell_control);
3469 
3470 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3471 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3472 	       mqd->cp_hqd_pq_wptr_lo);
3473 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3474 	       mqd->cp_hqd_pq_wptr_hi);
3475 
3476 	/* set the vmid for the queue */
3477 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3478 
3479 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3480 	       mqd->cp_hqd_persistent_state);
3481 
3482 	/* activate the queue */
3483 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE,
3484 	       mqd->cp_hqd_active);
3485 
3486 	if (ring->use_doorbell)
3487 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3488 
3489 	return 0;
3490 }
3491 
3492 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3493 {
3494 	struct amdgpu_device *adev = ring->adev;
3495 	int j;
3496 
3497 	/* disable the queue if it's active */
3498 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3499 
3500 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3501 
3502 		for (j = 0; j < adev->usec_timeout; j++) {
3503 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3504 				break;
3505 			udelay(1);
3506 		}
3507 
3508 		if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3509 			DRM_DEBUG("KIQ dequeue request failed.\n");
3510 
3511 			/* Manual disable if dequeue request times out */
3512 			WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0);
3513 		}
3514 
3515 		WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3516 		      0);
3517 	}
3518 
3519 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3520 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3521 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3522 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3523 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3524 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3525 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3526 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3527 
3528 	return 0;
3529 }
3530 
3531 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3532 {
3533 	struct amdgpu_device *adev = ring->adev;
3534 	struct v9_mqd *mqd = ring->mqd_ptr;
3535 	struct v9_mqd *tmp_mqd;
3536 
3537 	gfx_v9_0_kiq_setting(ring);
3538 
3539 	/* GPU could be in bad state during probe, driver trigger the reset
3540 	 * after load the SMU, in this case , the mqd is not be initialized.
3541 	 * driver need to re-init the mqd.
3542 	 * check mqd->cp_hqd_pq_control since this value should not be 0
3543 	 */
3544 	tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup;
3545 	if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){
3546 		/* for GPU_RESET case , reset MQD to a clean status */
3547 		if (adev->gfx.kiq[0].mqd_backup)
3548 			memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation));
3549 
3550 		/* reset ring buffer */
3551 		ring->wptr = 0;
3552 		amdgpu_ring_clear_ring(ring);
3553 
3554 		mutex_lock(&adev->srbm_mutex);
3555 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);
3556 		gfx_v9_0_kiq_init_register(ring);
3557 		soc15_grbm_select(adev, 0, 0, 0, 0, 0);
3558 		mutex_unlock(&adev->srbm_mutex);
3559 	} else {
3560 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3561 		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3562 		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3563 		if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3564 			amdgpu_ring_clear_ring(ring);
3565 		mutex_lock(&adev->srbm_mutex);
3566 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);
3567 		gfx_v9_0_mqd_init(ring);
3568 		gfx_v9_0_kiq_init_register(ring);
3569 		soc15_grbm_select(adev, 0, 0, 0, 0, 0);
3570 		mutex_unlock(&adev->srbm_mutex);
3571 
3572 		if (adev->gfx.kiq[0].mqd_backup)
3573 			memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
3574 	}
3575 
3576 	return 0;
3577 }
3578 
3579 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3580 {
3581 	struct amdgpu_device *adev = ring->adev;
3582 	struct v9_mqd *mqd = ring->mqd_ptr;
3583 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
3584 	struct v9_mqd *tmp_mqd;
3585 
3586 	/* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
3587 	 * is not be initialized before
3588 	 */
3589 	tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
3590 
3591 	if (!tmp_mqd->cp_hqd_pq_control ||
3592 	    (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
3593 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3594 		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3595 		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3596 		mutex_lock(&adev->srbm_mutex);
3597 		soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0);
3598 		gfx_v9_0_mqd_init(ring);
3599 		soc15_grbm_select(adev, 0, 0, 0, 0, 0);
3600 		mutex_unlock(&adev->srbm_mutex);
3601 
3602 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3603 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3604 	} else {
3605 		/* restore MQD to a clean status */
3606 		if (adev->gfx.mec.mqd_backup[mqd_idx])
3607 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3608 		/* reset ring buffer */
3609 		ring->wptr = 0;
3610 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3611 		amdgpu_ring_clear_ring(ring);
3612 	}
3613 
3614 	return 0;
3615 }
3616 
3617 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3618 {
3619 	struct amdgpu_ring *ring;
3620 	int r;
3621 
3622 	ring = &adev->gfx.kiq[0].ring;
3623 
3624 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
3625 	if (unlikely(r != 0))
3626 		return r;
3627 
3628 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3629 	if (unlikely(r != 0)) {
3630 		amdgpu_bo_unreserve(ring->mqd_obj);
3631 		return r;
3632 	}
3633 
3634 	gfx_v9_0_kiq_init_queue(ring);
3635 	amdgpu_bo_kunmap(ring->mqd_obj);
3636 	ring->mqd_ptr = NULL;
3637 	amdgpu_bo_unreserve(ring->mqd_obj);
3638 	return 0;
3639 }
3640 
3641 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3642 {
3643 	struct amdgpu_ring *ring = NULL;
3644 	int r = 0, i;
3645 
3646 	gfx_v9_0_cp_compute_enable(adev, true);
3647 
3648 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3649 		ring = &adev->gfx.compute_ring[i];
3650 
3651 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3652 		if (unlikely(r != 0))
3653 			goto done;
3654 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3655 		if (!r) {
3656 			r = gfx_v9_0_kcq_init_queue(ring);
3657 			amdgpu_bo_kunmap(ring->mqd_obj);
3658 			ring->mqd_ptr = NULL;
3659 		}
3660 		amdgpu_bo_unreserve(ring->mqd_obj);
3661 		if (r)
3662 			goto done;
3663 	}
3664 
3665 	r = amdgpu_gfx_enable_kcq(adev, 0);
3666 done:
3667 	return r;
3668 }
3669 
3670 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3671 {
3672 	int r, i;
3673 	struct amdgpu_ring *ring;
3674 
3675 	if (!(adev->flags & AMD_IS_APU))
3676 		gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3677 
3678 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3679 		if (adev->gfx.num_gfx_rings) {
3680 			/* legacy firmware loading */
3681 			r = gfx_v9_0_cp_gfx_load_microcode(adev);
3682 			if (r)
3683 				return r;
3684 		}
3685 
3686 		r = gfx_v9_0_cp_compute_load_microcode(adev);
3687 		if (r)
3688 			return r;
3689 	}
3690 
3691 	r = gfx_v9_0_kiq_resume(adev);
3692 	if (r)
3693 		return r;
3694 
3695 	if (adev->gfx.num_gfx_rings) {
3696 		r = gfx_v9_0_cp_gfx_resume(adev);
3697 		if (r)
3698 			return r;
3699 	}
3700 
3701 	r = gfx_v9_0_kcq_resume(adev);
3702 	if (r)
3703 		return r;
3704 
3705 	if (adev->gfx.num_gfx_rings) {
3706 		ring = &adev->gfx.gfx_ring[0];
3707 		r = amdgpu_ring_test_helper(ring);
3708 		if (r)
3709 			return r;
3710 	}
3711 
3712 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3713 		ring = &adev->gfx.compute_ring[i];
3714 		amdgpu_ring_test_helper(ring);
3715 	}
3716 
3717 	gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3718 
3719 	return 0;
3720 }
3721 
3722 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev)
3723 {
3724 	u32 tmp;
3725 
3726 	if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1) &&
3727 	    adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))
3728 		return;
3729 
3730 	tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG);
3731 	tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH,
3732 				adev->df.hash_status.hash_64k);
3733 	tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH,
3734 				adev->df.hash_status.hash_2m);
3735 	tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH,
3736 				adev->df.hash_status.hash_1g);
3737 	WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp);
3738 }
3739 
3740 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3741 {
3742 	if (adev->gfx.num_gfx_rings)
3743 		gfx_v9_0_cp_gfx_enable(adev, enable);
3744 	gfx_v9_0_cp_compute_enable(adev, enable);
3745 }
3746 
3747 static int gfx_v9_0_hw_init(void *handle)
3748 {
3749 	int r;
3750 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3751 
3752 	if (!amdgpu_sriov_vf(adev))
3753 		gfx_v9_0_init_golden_registers(adev);
3754 
3755 	gfx_v9_0_constants_init(adev);
3756 
3757 	gfx_v9_0_init_tcp_config(adev);
3758 
3759 	r = adev->gfx.rlc.funcs->resume(adev);
3760 	if (r)
3761 		return r;
3762 
3763 	r = gfx_v9_0_cp_resume(adev);
3764 	if (r)
3765 		return r;
3766 
3767 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
3768 		gfx_v9_4_2_set_power_brake_sequence(adev);
3769 
3770 	return r;
3771 }
3772 
3773 static int gfx_v9_0_hw_fini(void *handle)
3774 {
3775 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3776 
3777 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
3778 		amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3779 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3780 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3781 
3782 	/* DF freeze and kcq disable will fail */
3783 	if (!amdgpu_ras_intr_triggered())
3784 		/* disable KCQ to avoid CPC touch memory not valid anymore */
3785 		amdgpu_gfx_disable_kcq(adev, 0);
3786 
3787 	if (amdgpu_sriov_vf(adev)) {
3788 		gfx_v9_0_cp_gfx_enable(adev, false);
3789 		/* must disable polling for SRIOV when hw finished, otherwise
3790 		 * CPC engine may still keep fetching WB address which is already
3791 		 * invalid after sw finished and trigger DMAR reading error in
3792 		 * hypervisor side.
3793 		 */
3794 		WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3795 		return 0;
3796 	}
3797 
3798 	/* Use deinitialize sequence from CAIL when unbinding device from driver,
3799 	 * otherwise KIQ is hanging when binding back
3800 	 */
3801 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3802 		mutex_lock(&adev->srbm_mutex);
3803 		soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me,
3804 				adev->gfx.kiq[0].ring.pipe,
3805 				adev->gfx.kiq[0].ring.queue, 0, 0);
3806 		gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring);
3807 		soc15_grbm_select(adev, 0, 0, 0, 0, 0);
3808 		mutex_unlock(&adev->srbm_mutex);
3809 	}
3810 
3811 	gfx_v9_0_cp_enable(adev, false);
3812 
3813 	/* Skip stopping RLC with A+A reset or when RLC controls GFX clock */
3814 	if ((adev->gmc.xgmi.connected_to_cpu && amdgpu_in_reset(adev)) ||
3815 	    (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2))) {
3816 		dev_dbg(adev->dev, "Skipping RLC halt\n");
3817 		return 0;
3818 	}
3819 
3820 	adev->gfx.rlc.funcs->stop(adev);
3821 	return 0;
3822 }
3823 
3824 static int gfx_v9_0_suspend(void *handle)
3825 {
3826 	return gfx_v9_0_hw_fini(handle);
3827 }
3828 
3829 static int gfx_v9_0_resume(void *handle)
3830 {
3831 	return gfx_v9_0_hw_init(handle);
3832 }
3833 
3834 static bool gfx_v9_0_is_idle(void *handle)
3835 {
3836 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3837 
3838 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3839 				GRBM_STATUS, GUI_ACTIVE))
3840 		return false;
3841 	else
3842 		return true;
3843 }
3844 
3845 static int gfx_v9_0_wait_for_idle(void *handle)
3846 {
3847 	unsigned i;
3848 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3849 
3850 	for (i = 0; i < adev->usec_timeout; i++) {
3851 		if (gfx_v9_0_is_idle(handle))
3852 			return 0;
3853 		udelay(1);
3854 	}
3855 	return -ETIMEDOUT;
3856 }
3857 
3858 static int gfx_v9_0_soft_reset(void *handle)
3859 {
3860 	u32 grbm_soft_reset = 0;
3861 	u32 tmp;
3862 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3863 
3864 	/* GRBM_STATUS */
3865 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3866 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3867 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3868 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3869 		   GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3870 		   GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3871 		   GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3872 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3873 						GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3874 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3875 						GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3876 	}
3877 
3878 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3879 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3880 						GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3881 	}
3882 
3883 	/* GRBM_STATUS2 */
3884 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3885 	if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3886 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3887 						GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3888 
3889 
3890 	if (grbm_soft_reset) {
3891 		/* stop the rlc */
3892 		adev->gfx.rlc.funcs->stop(adev);
3893 
3894 		if (adev->gfx.num_gfx_rings)
3895 			/* Disable GFX parsing/prefetching */
3896 			gfx_v9_0_cp_gfx_enable(adev, false);
3897 
3898 		/* Disable MEC parsing/prefetching */
3899 		gfx_v9_0_cp_compute_enable(adev, false);
3900 
3901 		if (grbm_soft_reset) {
3902 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3903 			tmp |= grbm_soft_reset;
3904 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3905 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3906 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3907 
3908 			udelay(50);
3909 
3910 			tmp &= ~grbm_soft_reset;
3911 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3912 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3913 		}
3914 
3915 		/* Wait a little for things to settle down */
3916 		udelay(50);
3917 	}
3918 	return 0;
3919 }
3920 
3921 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev)
3922 {
3923 	signed long r, cnt = 0;
3924 	unsigned long flags;
3925 	uint32_t seq, reg_val_offs = 0;
3926 	uint64_t value = 0;
3927 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
3928 	struct amdgpu_ring *ring = &kiq->ring;
3929 
3930 	BUG_ON(!ring->funcs->emit_rreg);
3931 
3932 	spin_lock_irqsave(&kiq->ring_lock, flags);
3933 	if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
3934 		pr_err("critical bug! too many kiq readers\n");
3935 		goto failed_unlock;
3936 	}
3937 	amdgpu_ring_alloc(ring, 32);
3938 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
3939 	amdgpu_ring_write(ring, 9 |	/* src: register*/
3940 				(5 << 8) |	/* dst: memory */
3941 				(1 << 16) |	/* count sel */
3942 				(1 << 20));	/* write confirm */
3943 	amdgpu_ring_write(ring, 0);
3944 	amdgpu_ring_write(ring, 0);
3945 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
3946 				reg_val_offs * 4));
3947 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
3948 				reg_val_offs * 4));
3949 	r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
3950 	if (r)
3951 		goto failed_undo;
3952 
3953 	amdgpu_ring_commit(ring);
3954 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
3955 
3956 	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
3957 
3958 	/* don't wait anymore for gpu reset case because this way may
3959 	 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
3960 	 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
3961 	 * never return if we keep waiting in virt_kiq_rreg, which cause
3962 	 * gpu_recover() hang there.
3963 	 *
3964 	 * also don't wait anymore for IRQ context
3965 	 * */
3966 	if (r < 1 && (amdgpu_in_reset(adev)))
3967 		goto failed_kiq_read;
3968 
3969 	might_sleep();
3970 	while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
3971 		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
3972 		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
3973 	}
3974 
3975 	if (cnt > MAX_KIQ_REG_TRY)
3976 		goto failed_kiq_read;
3977 
3978 	mb();
3979 	value = (uint64_t)adev->wb.wb[reg_val_offs] |
3980 		(uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL;
3981 	amdgpu_device_wb_free(adev, reg_val_offs);
3982 	return value;
3983 
3984 failed_undo:
3985 	amdgpu_ring_undo(ring);
3986 failed_unlock:
3987 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
3988 failed_kiq_read:
3989 	if (reg_val_offs)
3990 		amdgpu_device_wb_free(adev, reg_val_offs);
3991 	pr_err("failed to read gpu clock\n");
3992 	return ~0;
3993 }
3994 
3995 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3996 {
3997 	uint64_t clock, clock_lo, clock_hi, hi_check;
3998 
3999 	switch (adev->ip_versions[GC_HWIP][0]) {
4000 	case IP_VERSION(9, 3, 0):
4001 		preempt_disable();
4002 		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
4003 		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
4004 		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Renoir);
4005 		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
4006 		 * roughly every 42 seconds.
4007 		 */
4008 		if (hi_check != clock_hi) {
4009 			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Renoir);
4010 			clock_hi = hi_check;
4011 		}
4012 		preempt_enable();
4013 		clock = clock_lo | (clock_hi << 32ULL);
4014 		break;
4015 	default:
4016 		amdgpu_gfx_off_ctrl(adev, false);
4017 		mutex_lock(&adev->gfx.gpu_clock_mutex);
4018 		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1) && amdgpu_sriov_runtime(adev)) {
4019 			clock = gfx_v9_0_kiq_read_clock(adev);
4020 		} else {
4021 			WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4022 			clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
4023 				((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4024 		}
4025 		mutex_unlock(&adev->gfx.gpu_clock_mutex);
4026 		amdgpu_gfx_off_ctrl(adev, true);
4027 		break;
4028 	}
4029 	return clock;
4030 }
4031 
4032 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4033 					  uint32_t vmid,
4034 					  uint32_t gds_base, uint32_t gds_size,
4035 					  uint32_t gws_base, uint32_t gws_size,
4036 					  uint32_t oa_base, uint32_t oa_size)
4037 {
4038 	struct amdgpu_device *adev = ring->adev;
4039 
4040 	/* GDS Base */
4041 	gfx_v9_0_write_data_to_reg(ring, 0, false,
4042 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
4043 				   gds_base);
4044 
4045 	/* GDS Size */
4046 	gfx_v9_0_write_data_to_reg(ring, 0, false,
4047 				   SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
4048 				   gds_size);
4049 
4050 	/* GWS */
4051 	gfx_v9_0_write_data_to_reg(ring, 0, false,
4052 				   SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
4053 				   gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4054 
4055 	/* OA */
4056 	gfx_v9_0_write_data_to_reg(ring, 0, false,
4057 				   SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
4058 				   (1 << (oa_size + oa_base)) - (1 << oa_base));
4059 }
4060 
4061 static const u32 vgpr_init_compute_shader[] =
4062 {
4063 	0xb07c0000, 0xbe8000ff,
4064 	0x000000f8, 0xbf110800,
4065 	0x7e000280, 0x7e020280,
4066 	0x7e040280, 0x7e060280,
4067 	0x7e080280, 0x7e0a0280,
4068 	0x7e0c0280, 0x7e0e0280,
4069 	0x80808800, 0xbe803200,
4070 	0xbf84fff5, 0xbf9c0000,
4071 	0xd28c0001, 0x0001007f,
4072 	0xd28d0001, 0x0002027e,
4073 	0x10020288, 0xb8810904,
4074 	0xb7814000, 0xd1196a01,
4075 	0x00000301, 0xbe800087,
4076 	0xbefc00c1, 0xd89c4000,
4077 	0x00020201, 0xd89cc080,
4078 	0x00040401, 0x320202ff,
4079 	0x00000800, 0x80808100,
4080 	0xbf84fff8, 0x7e020280,
4081 	0xbf810000, 0x00000000,
4082 };
4083 
4084 static const u32 sgpr_init_compute_shader[] =
4085 {
4086 	0xb07c0000, 0xbe8000ff,
4087 	0x0000005f, 0xbee50080,
4088 	0xbe812c65, 0xbe822c65,
4089 	0xbe832c65, 0xbe842c65,
4090 	0xbe852c65, 0xb77c0005,
4091 	0x80808500, 0xbf84fff8,
4092 	0xbe800080, 0xbf810000,
4093 };
4094 
4095 static const u32 vgpr_init_compute_shader_arcturus[] = {
4096 	0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080,
4097 	0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080,
4098 	0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080,
4099 	0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080,
4100 	0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080,
4101 	0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080,
4102 	0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080,
4103 	0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080,
4104 	0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080,
4105 	0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080,
4106 	0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080,
4107 	0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080,
4108 	0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080,
4109 	0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080,
4110 	0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080,
4111 	0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080,
4112 	0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080,
4113 	0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080,
4114 	0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080,
4115 	0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080,
4116 	0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080,
4117 	0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080,
4118 	0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080,
4119 	0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080,
4120 	0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080,
4121 	0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080,
4122 	0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080,
4123 	0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080,
4124 	0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080,
4125 	0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080,
4126 	0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080,
4127 	0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080,
4128 	0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080,
4129 	0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080,
4130 	0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080,
4131 	0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080,
4132 	0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080,
4133 	0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080,
4134 	0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080,
4135 	0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080,
4136 	0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080,
4137 	0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080,
4138 	0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080,
4139 	0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080,
4140 	0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080,
4141 	0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080,
4142 	0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080,
4143 	0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080,
4144 	0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080,
4145 	0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080,
4146 	0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080,
4147 	0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080,
4148 	0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080,
4149 	0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080,
4150 	0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080,
4151 	0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080,
4152 	0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080,
4153 	0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080,
4154 	0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080,
4155 	0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080,
4156 	0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080,
4157 	0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080,
4158 	0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080,
4159 	0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080,
4160 	0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080,
4161 	0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080,
4162 	0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080,
4163 	0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080,
4164 	0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080,
4165 	0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080,
4166 	0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080,
4167 	0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080,
4168 	0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080,
4169 	0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080,
4170 	0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080,
4171 	0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080,
4172 	0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080,
4173 	0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080,
4174 	0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080,
4175 	0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080,
4176 	0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080,
4177 	0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080,
4178 	0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080,
4179 	0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080,
4180 	0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080,
4181 	0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a,
4182 	0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280,
4183 	0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000,
4184 	0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904,
4185 	0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000,
4186 	0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a,
4187 	0xbf84fff8, 0xbf810000,
4188 };
4189 
4190 /* When below register arrays changed, please update gpr_reg_size,
4191   and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds,
4192   to cover all gfx9 ASICs */
4193 static const struct soc15_reg_entry vgpr_init_regs[] = {
4194    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4195    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4196    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4197    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4198    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
4199    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 },  /* 64KB LDS */
4200    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4201    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4202    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4203    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4204    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4205    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4206    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4207    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4208 };
4209 
4210 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = {
4211    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4212    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4213    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 },
4214    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4215    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf },
4216    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 },  /* 64KB LDS */
4217    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
4218    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
4219    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
4220    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
4221    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
4222    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
4223    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
4224    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
4225 };
4226 
4227 static const struct soc15_reg_entry sgpr1_init_regs[] = {
4228    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4229    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4230    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4231    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4232    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4233    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4234    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff },
4235    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff },
4236    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff },
4237    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff },
4238    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff },
4239    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff },
4240    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff },
4241    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff },
4242 };
4243 
4244 static const struct soc15_reg_entry sgpr2_init_regs[] = {
4245    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
4246    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 },
4247    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 },
4248    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 },
4249    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4250    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 },
4251    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 },
4252    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 },
4253    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 },
4254    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 },
4255    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 },
4256    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 },
4257    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 },
4258    { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 },
4259 };
4260 
4261 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = {
4262    { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1},
4263    { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1},
4264    { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1},
4265    { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1},
4266    { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1},
4267    { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1},
4268    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1},
4269    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1},
4270    { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1},
4271    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1},
4272    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1},
4273    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1},
4274    { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1},
4275    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6},
4276    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16},
4277    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16},
4278    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
4279    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16},
4280    { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16},
4281    { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16},
4282    { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16},
4283    { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16},
4284    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6},
4285    { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16},
4286    { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16},
4287    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1},
4288    { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1},
4289    { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32},
4290    { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32},
4291    { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72},
4292    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
4293    { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
4294    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
4295 };
4296 
4297 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
4298 {
4299 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4300 	int i, r;
4301 
4302 	/* only support when RAS is enabled */
4303 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4304 		return 0;
4305 
4306 	r = amdgpu_ring_alloc(ring, 7);
4307 	if (r) {
4308 		DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n",
4309 			ring->name, r);
4310 		return r;
4311 	}
4312 
4313 	WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000);
4314 	WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size);
4315 
4316 	amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
4317 	amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
4318 				PACKET3_DMA_DATA_DST_SEL(1) |
4319 				PACKET3_DMA_DATA_SRC_SEL(2) |
4320 				PACKET3_DMA_DATA_ENGINE(0)));
4321 	amdgpu_ring_write(ring, 0);
4322 	amdgpu_ring_write(ring, 0);
4323 	amdgpu_ring_write(ring, 0);
4324 	amdgpu_ring_write(ring, 0);
4325 	amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
4326 				adev->gds.gds_size);
4327 
4328 	amdgpu_ring_commit(ring);
4329 
4330 	for (i = 0; i < adev->usec_timeout; i++) {
4331 		if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring))
4332 			break;
4333 		udelay(1);
4334 	}
4335 
4336 	if (i >= adev->usec_timeout)
4337 		r = -ETIMEDOUT;
4338 
4339 	WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000);
4340 
4341 	return r;
4342 }
4343 
4344 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
4345 {
4346 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4347 	struct amdgpu_ib ib;
4348 	struct dma_fence *f = NULL;
4349 	int r, i;
4350 	unsigned total_size, vgpr_offset, sgpr_offset;
4351 	u64 gpu_addr;
4352 
4353 	int compute_dim_x = adev->gfx.config.max_shader_engines *
4354 						adev->gfx.config.max_cu_per_sh *
4355 						adev->gfx.config.max_sh_per_se;
4356 	int sgpr_work_group_size = 5;
4357 	int gpr_reg_size = adev->gfx.config.max_shader_engines + 6;
4358 	int vgpr_init_shader_size;
4359 	const u32 *vgpr_init_shader_ptr;
4360 	const struct soc15_reg_entry *vgpr_init_regs_ptr;
4361 
4362 	/* only support when RAS is enabled */
4363 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
4364 		return 0;
4365 
4366 	/* bail if the compute ring is not ready */
4367 	if (!ring->sched.ready)
4368 		return 0;
4369 
4370 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
4371 		vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus;
4372 		vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus);
4373 		vgpr_init_regs_ptr = vgpr_init_regs_arcturus;
4374 	} else {
4375 		vgpr_init_shader_ptr = vgpr_init_compute_shader;
4376 		vgpr_init_shader_size = sizeof(vgpr_init_compute_shader);
4377 		vgpr_init_regs_ptr = vgpr_init_regs;
4378 	}
4379 
4380 	total_size =
4381 		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */
4382 	total_size +=
4383 		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */
4384 	total_size +=
4385 		(gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */
4386 	total_size = ALIGN(total_size, 256);
4387 	vgpr_offset = total_size;
4388 	total_size += ALIGN(vgpr_init_shader_size, 256);
4389 	sgpr_offset = total_size;
4390 	total_size += sizeof(sgpr_init_compute_shader);
4391 
4392 	/* allocate an indirect buffer to put the commands in */
4393 	memset(&ib, 0, sizeof(ib));
4394 	r = amdgpu_ib_get(adev, NULL, total_size,
4395 					AMDGPU_IB_POOL_DIRECT, &ib);
4396 	if (r) {
4397 		DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
4398 		return r;
4399 	}
4400 
4401 	/* load the compute shaders */
4402 	for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)
4403 		ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i];
4404 
4405 	for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
4406 		ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
4407 
4408 	/* init the ib length to 0 */
4409 	ib.length_dw = 0;
4410 
4411 	/* VGPR */
4412 	/* write the register state for the compute dispatch */
4413 	for (i = 0; i < gpr_reg_size; i++) {
4414 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4415 		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])
4416 								- PACKET3_SET_SH_REG_START;
4417 		ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;
4418 	}
4419 	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4420 	gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
4421 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4422 	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4423 							- PACKET3_SET_SH_REG_START;
4424 	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4425 	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4426 
4427 	/* write dispatch packet */
4428 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4429 	ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */
4430 	ib.ptr[ib.length_dw++] = 1; /* y */
4431 	ib.ptr[ib.length_dw++] = 1; /* z */
4432 	ib.ptr[ib.length_dw++] =
4433 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4434 
4435 	/* write CS partial flush packet */
4436 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4437 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4438 
4439 	/* SGPR1 */
4440 	/* write the register state for the compute dispatch */
4441 	for (i = 0; i < gpr_reg_size; i++) {
4442 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4443 		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
4444 								- PACKET3_SET_SH_REG_START;
4445 		ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4446 	}
4447 	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4448 	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4449 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4450 	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4451 							- PACKET3_SET_SH_REG_START;
4452 	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4453 	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4454 
4455 	/* write dispatch packet */
4456 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4457 	ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4458 	ib.ptr[ib.length_dw++] = 1; /* y */
4459 	ib.ptr[ib.length_dw++] = 1; /* z */
4460 	ib.ptr[ib.length_dw++] =
4461 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4462 
4463 	/* write CS partial flush packet */
4464 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4465 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4466 
4467 	/* SGPR2 */
4468 	/* write the register state for the compute dispatch */
4469 	for (i = 0; i < gpr_reg_size; i++) {
4470 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
4471 		ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
4472 								- PACKET3_SET_SH_REG_START;
4473 		ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
4474 	}
4475 	/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
4476 	gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
4477 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
4478 	ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
4479 							- PACKET3_SET_SH_REG_START;
4480 	ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
4481 	ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
4482 
4483 	/* write dispatch packet */
4484 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
4485 	ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
4486 	ib.ptr[ib.length_dw++] = 1; /* y */
4487 	ib.ptr[ib.length_dw++] = 1; /* z */
4488 	ib.ptr[ib.length_dw++] =
4489 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
4490 
4491 	/* write CS partial flush packet */
4492 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
4493 	ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
4494 
4495 	/* shedule the ib on the ring */
4496 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4497 	if (r) {
4498 		DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
4499 		goto fail;
4500 	}
4501 
4502 	/* wait for the GPU to finish processing the IB */
4503 	r = dma_fence_wait(f, false);
4504 	if (r) {
4505 		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
4506 		goto fail;
4507 	}
4508 
4509 fail:
4510 	amdgpu_ib_free(adev, &ib, NULL);
4511 	dma_fence_put(f);
4512 
4513 	return r;
4514 }
4515 
4516 static int gfx_v9_0_early_init(void *handle)
4517 {
4518 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4519 
4520 	adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
4521 
4522 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) ||
4523 	    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
4524 		adev->gfx.num_gfx_rings = 0;
4525 	else
4526 		adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
4527 	adev->gfx.xcc_mask = 1;
4528 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4529 					  AMDGPU_MAX_COMPUTE_RINGS);
4530 	gfx_v9_0_set_kiq_pm4_funcs(adev);
4531 	gfx_v9_0_set_ring_funcs(adev);
4532 	gfx_v9_0_set_irq_funcs(adev);
4533 	gfx_v9_0_set_gds_init(adev);
4534 	gfx_v9_0_set_rlc_funcs(adev);
4535 
4536 	/* init rlcg reg access ctrl */
4537 	gfx_v9_0_init_rlcg_reg_access_ctrl(adev);
4538 
4539 	return gfx_v9_0_init_microcode(adev);
4540 }
4541 
4542 static int gfx_v9_0_ecc_late_init(void *handle)
4543 {
4544 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4545 	int r;
4546 
4547 	/*
4548 	 * Temp workaround to fix the issue that CP firmware fails to
4549 	 * update read pointer when CPDMA is writing clearing operation
4550 	 * to GDS in suspend/resume sequence on several cards. So just
4551 	 * limit this operation in cold boot sequence.
4552 	 */
4553 	if ((!adev->in_suspend) &&
4554 	    (adev->gds.gds_size)) {
4555 		r = gfx_v9_0_do_edc_gds_workarounds(adev);
4556 		if (r)
4557 			return r;
4558 	}
4559 
4560 	/* requires IBs so do in late init after IB pool is initialized */
4561 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
4562 		r = gfx_v9_4_2_do_edc_gpr_workarounds(adev);
4563 	else
4564 		r = gfx_v9_0_do_edc_gpr_workarounds(adev);
4565 
4566 	if (r)
4567 		return r;
4568 
4569 	if (adev->gfx.ras &&
4570 	    adev->gfx.ras->enable_watchdog_timer)
4571 		adev->gfx.ras->enable_watchdog_timer(adev);
4572 
4573 	return 0;
4574 }
4575 
4576 static int gfx_v9_0_late_init(void *handle)
4577 {
4578 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4579 	int r;
4580 
4581 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4582 	if (r)
4583 		return r;
4584 
4585 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4586 	if (r)
4587 		return r;
4588 
4589 	r = gfx_v9_0_ecc_late_init(handle);
4590 	if (r)
4591 		return r;
4592 
4593 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
4594 		gfx_v9_4_2_debug_trap_config_init(adev,
4595 			adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID);
4596 	else
4597 		gfx_v9_0_debug_trap_config_init(adev,
4598 			adev->vm_manager.first_kfd_vmid, AMDGPU_NUM_VMID);
4599 
4600 	return 0;
4601 }
4602 
4603 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev)
4604 {
4605 	uint32_t rlc_setting;
4606 
4607 	/* if RLC is not enabled, do nothing */
4608 	rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4609 	if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
4610 		return false;
4611 
4612 	return true;
4613 }
4614 
4615 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
4616 {
4617 	uint32_t data;
4618 	unsigned i;
4619 
4620 	data = RLC_SAFE_MODE__CMD_MASK;
4621 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4622 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4623 
4624 	/* wait for RLC_SAFE_MODE */
4625 	for (i = 0; i < adev->usec_timeout; i++) {
4626 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4627 			break;
4628 		udelay(1);
4629 	}
4630 }
4631 
4632 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
4633 {
4634 	uint32_t data;
4635 
4636 	data = RLC_SAFE_MODE__CMD_MASK;
4637 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4638 }
4639 
4640 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
4641 						bool enable)
4642 {
4643 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4644 
4645 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
4646 		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
4647 		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4648 			gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
4649 	} else {
4650 		gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
4651 		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
4652 			gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
4653 	}
4654 
4655 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4656 }
4657 
4658 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
4659 						bool enable)
4660 {
4661 	/* TODO: double check if we need to perform under safe mode */
4662 	/* gfx_v9_0_enter_rlc_safe_mode(adev); */
4663 
4664 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
4665 		gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
4666 	else
4667 		gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
4668 
4669 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
4670 		gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
4671 	else
4672 		gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
4673 
4674 	/* gfx_v9_0_exit_rlc_safe_mode(adev); */
4675 }
4676 
4677 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4678 						      bool enable)
4679 {
4680 	uint32_t data, def;
4681 
4682 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4683 
4684 	/* It is disabled by HW by default */
4685 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4686 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
4687 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4688 
4689 		if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
4690 			data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4691 
4692 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4693 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4694 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4695 
4696 		/* only for Vega10 & Raven1 */
4697 		data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4698 
4699 		if (def != data)
4700 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4701 
4702 		/* MGLS is a global flag to control all MGLS in GFX */
4703 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4704 			/* 2 - RLC memory Light sleep */
4705 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4706 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4707 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4708 				if (def != data)
4709 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4710 			}
4711 			/* 3 - CP memory Light sleep */
4712 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4713 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4714 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4715 				if (def != data)
4716 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4717 			}
4718 		}
4719 	} else {
4720 		/* 1 - MGCG_OVERRIDE */
4721 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4722 
4723 		if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 1))
4724 			data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
4725 
4726 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4727 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4728 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4729 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4730 
4731 		if (def != data)
4732 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4733 
4734 		/* 2 - disable MGLS in RLC */
4735 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4736 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4737 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4738 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4739 		}
4740 
4741 		/* 3 - disable MGLS in CP */
4742 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4743 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4744 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4745 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4746 		}
4747 	}
4748 
4749 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4750 }
4751 
4752 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
4753 					   bool enable)
4754 {
4755 	uint32_t data, def;
4756 
4757 	if (!adev->gfx.num_gfx_rings)
4758 		return;
4759 
4760 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4761 
4762 	/* Enable 3D CGCG/CGLS */
4763 	if (enable) {
4764 		/* write cmd to clear cgcg/cgls ov */
4765 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4766 		/* unset CGCG override */
4767 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4768 		/* update CGCG and CGLS override bits */
4769 		if (def != data)
4770 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4771 
4772 		/* enable 3Dcgcg FSM(0x0000363f) */
4773 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4774 
4775 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4776 			data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4777 				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4778 		else
4779 			data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
4780 
4781 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4782 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4783 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4784 		if (def != data)
4785 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4786 
4787 		/* set IDLE_POLL_COUNT(0x00900100) */
4788 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4789 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4790 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4791 		if (def != data)
4792 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4793 	} else {
4794 		/* Disable CGCG/CGLS */
4795 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4796 		/* disable cgcg, cgls should be disabled */
4797 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4798 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4799 		/* disable cgcg and cgls in FSM */
4800 		if (def != data)
4801 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4802 	}
4803 
4804 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4805 }
4806 
4807 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4808 						      bool enable)
4809 {
4810 	uint32_t def, data;
4811 
4812 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4813 
4814 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4815 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4816 		/* unset CGCG override */
4817 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4818 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4819 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4820 		else
4821 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4822 		/* update CGCG and CGLS override bits */
4823 		if (def != data)
4824 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4825 
4826 		/* enable cgcg FSM(0x0000363F) */
4827 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4828 
4829 		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1))
4830 			data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4831 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4832 		else
4833 			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4834 				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4835 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4836 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4837 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4838 		if (def != data)
4839 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4840 
4841 		/* set IDLE_POLL_COUNT(0x00900100) */
4842 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4843 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4844 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4845 		if (def != data)
4846 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4847 	} else {
4848 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4849 		/* reset CGCG/CGLS bits */
4850 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4851 		/* disable cgcg and cgls in FSM */
4852 		if (def != data)
4853 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4854 	}
4855 
4856 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4857 }
4858 
4859 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4860 					    bool enable)
4861 {
4862 	if (enable) {
4863 		/* CGCG/CGLS should be enabled after MGCG/MGLS
4864 		 * ===  MGCG + MGLS ===
4865 		 */
4866 		gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
4867 		/* ===  CGCG /CGLS for GFX 3D Only === */
4868 		gfx_v9_0_update_3d_clock_gating(adev, enable);
4869 		/* ===  CGCG + CGLS === */
4870 		gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
4871 	} else {
4872 		/* CGCG/CGLS should be disabled before MGCG/MGLS
4873 		 * ===  CGCG + CGLS ===
4874 		 */
4875 		gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
4876 		/* ===  CGCG /CGLS for GFX 3D Only === */
4877 		gfx_v9_0_update_3d_clock_gating(adev, enable);
4878 		/* ===  MGCG + MGLS === */
4879 		gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
4880 	}
4881 	return 0;
4882 }
4883 
4884 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4885 {
4886 	u32 reg, data;
4887 
4888 	amdgpu_gfx_off_ctrl(adev, false);
4889 
4890 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
4891 	if (amdgpu_sriov_is_pp_one_vf(adev))
4892 		data = RREG32_NO_KIQ(reg);
4893 	else
4894 		data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
4895 
4896 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4897 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4898 
4899 	if (amdgpu_sriov_is_pp_one_vf(adev))
4900 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
4901 	else
4902 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
4903 
4904 	amdgpu_gfx_off_ctrl(adev, true);
4905 }
4906 
4907 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,
4908 					uint32_t offset,
4909 					struct soc15_reg_rlcg *entries, int arr_size)
4910 {
4911 	int i;
4912 	uint32_t reg;
4913 
4914 	if (!entries)
4915 		return false;
4916 
4917 	for (i = 0; i < arr_size; i++) {
4918 		const struct soc15_reg_rlcg *entry;
4919 
4920 		entry = &entries[i];
4921 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
4922 		if (offset == reg)
4923 			return true;
4924 	}
4925 
4926 	return false;
4927 }
4928 
4929 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
4930 {
4931 	return gfx_v9_0_check_rlcg_range(adev, offset,
4932 					(void *)rlcg_access_gc_9_0,
4933 					ARRAY_SIZE(rlcg_access_gc_9_0));
4934 }
4935 
4936 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
4937 	.is_rlc_enabled = gfx_v9_0_is_rlc_enabled,
4938 	.set_safe_mode = gfx_v9_0_set_safe_mode,
4939 	.unset_safe_mode = gfx_v9_0_unset_safe_mode,
4940 	.init = gfx_v9_0_rlc_init,
4941 	.get_csb_size = gfx_v9_0_get_csb_size,
4942 	.get_csb_buffer = gfx_v9_0_get_csb_buffer,
4943 	.get_cp_table_num = gfx_v9_0_cp_jump_table_num,
4944 	.resume = gfx_v9_0_rlc_resume,
4945 	.stop = gfx_v9_0_rlc_stop,
4946 	.reset = gfx_v9_0_rlc_reset,
4947 	.start = gfx_v9_0_rlc_start,
4948 	.update_spm_vmid = gfx_v9_0_update_spm_vmid,
4949 	.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
4950 };
4951 
4952 static int gfx_v9_0_set_powergating_state(void *handle,
4953 					  enum amd_powergating_state state)
4954 {
4955 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4956 	bool enable = (state == AMD_PG_STATE_GATE);
4957 
4958 	switch (adev->ip_versions[GC_HWIP][0]) {
4959 	case IP_VERSION(9, 2, 2):
4960 	case IP_VERSION(9, 1, 0):
4961 	case IP_VERSION(9, 3, 0):
4962 		if (!enable)
4963 			amdgpu_gfx_off_ctrl(adev, false);
4964 
4965 		if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
4966 			gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
4967 			gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
4968 		} else {
4969 			gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
4970 			gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
4971 		}
4972 
4973 		if (adev->pg_flags & AMD_PG_SUPPORT_CP)
4974 			gfx_v9_0_enable_cp_power_gating(adev, true);
4975 		else
4976 			gfx_v9_0_enable_cp_power_gating(adev, false);
4977 
4978 		/* update gfx cgpg state */
4979 		gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
4980 
4981 		/* update mgcg state */
4982 		gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
4983 
4984 		if (enable)
4985 			amdgpu_gfx_off_ctrl(adev, true);
4986 		break;
4987 	case IP_VERSION(9, 2, 1):
4988 		amdgpu_gfx_off_ctrl(adev, enable);
4989 		break;
4990 	default:
4991 		break;
4992 	}
4993 
4994 	return 0;
4995 }
4996 
4997 static int gfx_v9_0_set_clockgating_state(void *handle,
4998 					  enum amd_clockgating_state state)
4999 {
5000 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5001 
5002 	if (amdgpu_sriov_vf(adev))
5003 		return 0;
5004 
5005 	switch (adev->ip_versions[GC_HWIP][0]) {
5006 	case IP_VERSION(9, 0, 1):
5007 	case IP_VERSION(9, 2, 1):
5008 	case IP_VERSION(9, 4, 0):
5009 	case IP_VERSION(9, 2, 2):
5010 	case IP_VERSION(9, 1, 0):
5011 	case IP_VERSION(9, 4, 1):
5012 	case IP_VERSION(9, 3, 0):
5013 	case IP_VERSION(9, 4, 2):
5014 		gfx_v9_0_update_gfx_clock_gating(adev,
5015 						 state == AMD_CG_STATE_GATE);
5016 		break;
5017 	default:
5018 		break;
5019 	}
5020 	return 0;
5021 }
5022 
5023 static void gfx_v9_0_get_clockgating_state(void *handle, u64 *flags)
5024 {
5025 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5026 	int data;
5027 
5028 	if (amdgpu_sriov_vf(adev))
5029 		*flags = 0;
5030 
5031 	/* AMD_CG_SUPPORT_GFX_MGCG */
5032 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
5033 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5034 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
5035 
5036 	/* AMD_CG_SUPPORT_GFX_CGCG */
5037 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
5038 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5039 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
5040 
5041 	/* AMD_CG_SUPPORT_GFX_CGLS */
5042 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5043 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
5044 
5045 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
5046 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
5047 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5048 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5049 
5050 	/* AMD_CG_SUPPORT_GFX_CP_LS */
5051 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
5052 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5053 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5054 
5055 	if (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) {
5056 		/* AMD_CG_SUPPORT_GFX_3D_CGCG */
5057 		data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
5058 		if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5059 			*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5060 
5061 		/* AMD_CG_SUPPORT_GFX_3D_CGLS */
5062 		if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5063 			*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5064 	}
5065 }
5066 
5067 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5068 {
5069 	return *ring->rptr_cpu_addr; /* gfx9 is 32bit rptr*/
5070 }
5071 
5072 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5073 {
5074 	struct amdgpu_device *adev = ring->adev;
5075 	u64 wptr;
5076 
5077 	/* XXX check if swapping is necessary on BE */
5078 	if (ring->use_doorbell) {
5079 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5080 	} else {
5081 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
5082 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
5083 	}
5084 
5085 	return wptr;
5086 }
5087 
5088 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5089 {
5090 	struct amdgpu_device *adev = ring->adev;
5091 
5092 	if (ring->use_doorbell) {
5093 		/* XXX check if swapping is necessary on BE */
5094 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
5095 		WDOORBELL64(ring->doorbell_index, ring->wptr);
5096 	} else {
5097 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5098 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5099 	}
5100 }
5101 
5102 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5103 {
5104 	struct amdgpu_device *adev = ring->adev;
5105 	u32 ref_and_mask, reg_mem_engine;
5106 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5107 
5108 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5109 		switch (ring->me) {
5110 		case 1:
5111 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5112 			break;
5113 		case 2:
5114 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5115 			break;
5116 		default:
5117 			return;
5118 		}
5119 		reg_mem_engine = 0;
5120 	} else {
5121 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5122 		reg_mem_engine = 1; /* pfp */
5123 	}
5124 
5125 	gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5126 			      adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5127 			      adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5128 			      ref_and_mask, ref_and_mask, 0x20);
5129 }
5130 
5131 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5132 					struct amdgpu_job *job,
5133 					struct amdgpu_ib *ib,
5134 					uint32_t flags)
5135 {
5136 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5137 	u32 header, control = 0;
5138 
5139 	if (ib->flags & AMDGPU_IB_FLAG_CE)
5140 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
5141 	else
5142 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5143 
5144 	control |= ib->length_dw | (vmid << 24);
5145 
5146 	if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
5147 		control |= INDIRECT_BUFFER_PRE_ENB(1);
5148 
5149 		if (flags & AMDGPU_IB_PREEMPTED)
5150 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
5151 
5152 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
5153 			gfx_v9_0_ring_emit_de_meta(ring,
5154 						   (!amdgpu_sriov_vf(ring->adev) &&
5155 						   flags & AMDGPU_IB_PREEMPTED) ?
5156 						   true : false,
5157 						   job->gds_size > 0 && job->gds_base != 0);
5158 	}
5159 
5160 	amdgpu_ring_write(ring, header);
5161 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5162 	amdgpu_ring_write(ring,
5163 #ifdef __BIG_ENDIAN
5164 		(2 << 0) |
5165 #endif
5166 		lower_32_bits(ib->gpu_addr));
5167 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5168 	amdgpu_ring_ib_on_emit_cntl(ring);
5169 	amdgpu_ring_write(ring, control);
5170 }
5171 
5172 static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring,
5173 				     unsigned offset)
5174 {
5175 	u32 control = ring->ring[offset];
5176 
5177 	control |= INDIRECT_BUFFER_PRE_RESUME(1);
5178 	ring->ring[offset] = control;
5179 }
5180 
5181 static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring,
5182 					unsigned offset)
5183 {
5184 	struct amdgpu_device *adev = ring->adev;
5185 	void *ce_payload_cpu_addr;
5186 	uint64_t payload_offset, payload_size;
5187 
5188 	payload_size = sizeof(struct v9_ce_ib_state);
5189 
5190 	if (ring->is_mes_queue) {
5191 		payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5192 					  gfx[0].gfx_meta_data) +
5193 			offsetof(struct v9_gfx_meta_data, ce_payload);
5194 		ce_payload_cpu_addr =
5195 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
5196 	} else {
5197 		payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);
5198 		ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
5199 	}
5200 
5201 	if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
5202 		memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size);
5203 	} else {
5204 		memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr,
5205 		       (ring->buf_mask + 1 - offset) << 2);
5206 		payload_size -= (ring->buf_mask + 1 - offset) << 2;
5207 		memcpy((void *)&ring->ring[0],
5208 		       ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
5209 		       payload_size);
5210 	}
5211 }
5212 
5213 static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring,
5214 					unsigned offset)
5215 {
5216 	struct amdgpu_device *adev = ring->adev;
5217 	void *de_payload_cpu_addr;
5218 	uint64_t payload_offset, payload_size;
5219 
5220 	payload_size = sizeof(struct v9_de_ib_state);
5221 
5222 	if (ring->is_mes_queue) {
5223 		payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5224 					  gfx[0].gfx_meta_data) +
5225 			offsetof(struct v9_gfx_meta_data, de_payload);
5226 		de_payload_cpu_addr =
5227 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
5228 	} else {
5229 		payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);
5230 		de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
5231 	}
5232 
5233 	if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
5234 		memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size);
5235 	} else {
5236 		memcpy((void *)&ring->ring[offset], de_payload_cpu_addr,
5237 		       (ring->buf_mask + 1 - offset) << 2);
5238 		payload_size -= (ring->buf_mask + 1 - offset) << 2;
5239 		memcpy((void *)&ring->ring[0],
5240 		       de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
5241 		       payload_size);
5242 	}
5243 }
5244 
5245 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5246 					  struct amdgpu_job *job,
5247 					  struct amdgpu_ib *ib,
5248 					  uint32_t flags)
5249 {
5250 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5251 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5252 
5253 	/* Currently, there is a high possibility to get wave ID mismatch
5254 	 * between ME and GDS, leading to a hw deadlock, because ME generates
5255 	 * different wave IDs than the GDS expects. This situation happens
5256 	 * randomly when at least 5 compute pipes use GDS ordered append.
5257 	 * The wave IDs generated by ME are also wrong after suspend/resume.
5258 	 * Those are probably bugs somewhere else in the kernel driver.
5259 	 *
5260 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5261 	 * GDS to 0 for this ring (me/pipe).
5262 	 */
5263 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5264 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5265 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
5266 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5267 	}
5268 
5269 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5270 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5271 	amdgpu_ring_write(ring,
5272 #ifdef __BIG_ENDIAN
5273 				(2 << 0) |
5274 #endif
5275 				lower_32_bits(ib->gpu_addr));
5276 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5277 	amdgpu_ring_write(ring, control);
5278 }
5279 
5280 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5281 				     u64 seq, unsigned flags)
5282 {
5283 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5284 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5285 	bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
5286 	bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
5287 	uint32_t dw2 = 0;
5288 
5289 	/* RELEASE_MEM - flush caches, send int */
5290 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5291 
5292 	if (writeback) {
5293 		dw2 = EOP_TC_NC_ACTION_EN;
5294 	} else {
5295 		dw2 = EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN |
5296 				EOP_TC_MD_ACTION_EN;
5297 	}
5298 	dw2 |= EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5299 				EVENT_INDEX(5);
5300 	if (exec)
5301 		dw2 |= EOP_EXEC;
5302 
5303 	amdgpu_ring_write(ring, dw2);
5304 	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
5305 
5306 	/*
5307 	 * the address should be Qword aligned if 64bit write, Dword
5308 	 * aligned if only send 32bit data low (discard data high)
5309 	 */
5310 	if (write64bit)
5311 		BUG_ON(addr & 0x7);
5312 	else
5313 		BUG_ON(addr & 0x3);
5314 	amdgpu_ring_write(ring, lower_32_bits(addr));
5315 	amdgpu_ring_write(ring, upper_32_bits(addr));
5316 	amdgpu_ring_write(ring, lower_32_bits(seq));
5317 	amdgpu_ring_write(ring, upper_32_bits(seq));
5318 	amdgpu_ring_write(ring, 0);
5319 }
5320 
5321 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5322 {
5323 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5324 	uint32_t seq = ring->fence_drv.sync_seq;
5325 	uint64_t addr = ring->fence_drv.gpu_addr;
5326 
5327 	gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
5328 			      lower_32_bits(addr), upper_32_bits(addr),
5329 			      seq, 0xffffffff, 4);
5330 }
5331 
5332 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5333 					unsigned vmid, uint64_t pd_addr)
5334 {
5335 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5336 
5337 	/* compute doesn't have PFP */
5338 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5339 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
5340 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5341 		amdgpu_ring_write(ring, 0x0);
5342 	}
5343 }
5344 
5345 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5346 {
5347 	return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */
5348 }
5349 
5350 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5351 {
5352 	u64 wptr;
5353 
5354 	/* XXX check if swapping is necessary on BE */
5355 	if (ring->use_doorbell)
5356 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5357 	else
5358 		BUG();
5359 	return wptr;
5360 }
5361 
5362 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5363 {
5364 	struct amdgpu_device *adev = ring->adev;
5365 
5366 	/* XXX check if swapping is necessary on BE */
5367 	if (ring->use_doorbell) {
5368 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
5369 		WDOORBELL64(ring->doorbell_index, ring->wptr);
5370 	} else{
5371 		BUG(); /* only DOORBELL method supported on gfx9 now */
5372 	}
5373 }
5374 
5375 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5376 					 u64 seq, unsigned int flags)
5377 {
5378 	struct amdgpu_device *adev = ring->adev;
5379 
5380 	/* we only allocate 32bit for each seq wb address */
5381 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5382 
5383 	/* write fence seq to the "addr" */
5384 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5385 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5386 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5387 	amdgpu_ring_write(ring, lower_32_bits(addr));
5388 	amdgpu_ring_write(ring, upper_32_bits(addr));
5389 	amdgpu_ring_write(ring, lower_32_bits(seq));
5390 
5391 	if (flags & AMDGPU_FENCE_FLAG_INT) {
5392 		/* set register to trigger INT */
5393 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5394 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5395 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5396 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
5397 		amdgpu_ring_write(ring, 0);
5398 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5399 	}
5400 }
5401 
5402 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
5403 {
5404 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
5405 	amdgpu_ring_write(ring, 0);
5406 }
5407 
5408 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
5409 {
5410 	struct amdgpu_device *adev = ring->adev;
5411 	struct v9_ce_ib_state ce_payload = {0};
5412 	uint64_t offset, ce_payload_gpu_addr;
5413 	void *ce_payload_cpu_addr;
5414 	int cnt;
5415 
5416 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
5417 
5418 	if (ring->is_mes_queue) {
5419 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5420 				  gfx[0].gfx_meta_data) +
5421 			offsetof(struct v9_gfx_meta_data, ce_payload);
5422 		ce_payload_gpu_addr =
5423 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5424 		ce_payload_cpu_addr =
5425 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5426 	} else {
5427 		offset = offsetof(struct v9_gfx_meta_data, ce_payload);
5428 		ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5429 		ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5430 	}
5431 
5432 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5433 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
5434 				 WRITE_DATA_DST_SEL(8) |
5435 				 WR_CONFIRM) |
5436 				 WRITE_DATA_CACHE_POLICY(0));
5437 	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
5438 	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
5439 
5440 	amdgpu_ring_ib_on_emit_ce(ring);
5441 
5442 	if (resume)
5443 		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
5444 					   sizeof(ce_payload) >> 2);
5445 	else
5446 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
5447 					   sizeof(ce_payload) >> 2);
5448 }
5449 
5450 static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)
5451 {
5452 	int i, r = 0;
5453 	struct amdgpu_device *adev = ring->adev;
5454 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5455 	struct amdgpu_ring *kiq_ring = &kiq->ring;
5456 	unsigned long flags;
5457 
5458 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5459 		return -EINVAL;
5460 
5461 	spin_lock_irqsave(&kiq->ring_lock, flags);
5462 
5463 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5464 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
5465 		return -ENOMEM;
5466 	}
5467 
5468 	/* assert preemption condition */
5469 	amdgpu_ring_set_preempt_cond_exec(ring, false);
5470 
5471 	ring->trail_seq += 1;
5472 	amdgpu_ring_alloc(ring, 13);
5473 	gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
5474 				 ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT);
5475 
5476 	/* assert IB preemption, emit the trailing fence */
5477 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5478 				   ring->trail_fence_gpu_addr,
5479 				   ring->trail_seq);
5480 
5481 	amdgpu_ring_commit(kiq_ring);
5482 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
5483 
5484 	/* poll the trailing fence */
5485 	for (i = 0; i < adev->usec_timeout; i++) {
5486 		if (ring->trail_seq ==
5487 			le32_to_cpu(*ring->trail_fence_cpu_addr))
5488 			break;
5489 		udelay(1);
5490 	}
5491 
5492 	if (i >= adev->usec_timeout) {
5493 		r = -EINVAL;
5494 		DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);
5495 	}
5496 
5497 	/*reset the CP_VMID_PREEMPT after trailing fence*/
5498 	amdgpu_ring_emit_wreg(ring,
5499 			      SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
5500 			      0x0);
5501 	amdgpu_ring_commit(ring);
5502 
5503 	/* deassert preemption condition */
5504 	amdgpu_ring_set_preempt_cond_exec(ring, true);
5505 	return r;
5506 }
5507 
5508 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds)
5509 {
5510 	struct amdgpu_device *adev = ring->adev;
5511 	struct v9_de_ib_state de_payload = {0};
5512 	uint64_t offset, gds_addr, de_payload_gpu_addr;
5513 	void *de_payload_cpu_addr;
5514 	int cnt;
5515 
5516 	if (ring->is_mes_queue) {
5517 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5518 				  gfx[0].gfx_meta_data) +
5519 			offsetof(struct v9_gfx_meta_data, de_payload);
5520 		de_payload_gpu_addr =
5521 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5522 		de_payload_cpu_addr =
5523 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5524 
5525 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5526 				  gfx[0].gds_backup) +
5527 			offsetof(struct v9_gfx_meta_data, de_payload);
5528 		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5529 	} else {
5530 		offset = offsetof(struct v9_gfx_meta_data, de_payload);
5531 		de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5532 		de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5533 
5534 		gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5535 				 AMDGPU_CSA_SIZE - adev->gds.gds_size,
5536 				 PAGE_SIZE);
5537 	}
5538 
5539 	if (usegds) {
5540 		de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5541 		de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5542 	}
5543 
5544 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5545 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5546 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5547 				 WRITE_DATA_DST_SEL(8) |
5548 				 WR_CONFIRM) |
5549 				 WRITE_DATA_CACHE_POLICY(0));
5550 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5551 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5552 
5553 	amdgpu_ring_ib_on_emit_de(ring);
5554 	if (resume)
5555 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5556 					   sizeof(de_payload) >> 2);
5557 	else
5558 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5559 					   sizeof(de_payload) >> 2);
5560 }
5561 
5562 static void gfx_v9_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5563 				   bool secure)
5564 {
5565 	uint32_t v = secure ? FRAME_TMZ : 0;
5566 
5567 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5568 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5569 }
5570 
5571 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
5572 {
5573 	uint32_t dw2 = 0;
5574 
5575 	gfx_v9_0_ring_emit_ce_meta(ring,
5576 				   (!amdgpu_sriov_vf(ring->adev) &&
5577 				   flags & AMDGPU_IB_PREEMPTED) ? true : false);
5578 
5579 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5580 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5581 		/* set load_global_config & load_global_uconfig */
5582 		dw2 |= 0x8001;
5583 		/* set load_cs_sh_regs */
5584 		dw2 |= 0x01000000;
5585 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
5586 		dw2 |= 0x10002;
5587 
5588 		/* set load_ce_ram if preamble presented */
5589 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
5590 			dw2 |= 0x10000000;
5591 	} else {
5592 		/* still load_ce_ram if this is the first time preamble presented
5593 		 * although there is no context switch happens.
5594 		 */
5595 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
5596 			dw2 |= 0x10000000;
5597 	}
5598 
5599 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5600 	amdgpu_ring_write(ring, dw2);
5601 	amdgpu_ring_write(ring, 0);
5602 }
5603 
5604 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5605 {
5606 	unsigned ret;
5607 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5608 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5609 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5610 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5611 	ret = ring->wptr & ring->buf_mask;
5612 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5613 	return ret;
5614 }
5615 
5616 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5617 {
5618 	unsigned cur;
5619 	BUG_ON(offset > ring->buf_mask);
5620 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
5621 
5622 	cur = (ring->wptr - 1) & ring->buf_mask;
5623 	if (likely(cur > offset))
5624 		ring->ring[offset] = cur - offset;
5625 	else
5626 		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
5627 }
5628 
5629 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5630 				    uint32_t reg_val_offs)
5631 {
5632 	struct amdgpu_device *adev = ring->adev;
5633 
5634 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5635 	amdgpu_ring_write(ring, 0 |	/* src: register*/
5636 				(5 << 8) |	/* dst: memory */
5637 				(1 << 20));	/* write confirm */
5638 	amdgpu_ring_write(ring, reg);
5639 	amdgpu_ring_write(ring, 0);
5640 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5641 				reg_val_offs * 4));
5642 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5643 				reg_val_offs * 4));
5644 }
5645 
5646 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5647 				    uint32_t val)
5648 {
5649 	uint32_t cmd = 0;
5650 
5651 	switch (ring->funcs->type) {
5652 	case AMDGPU_RING_TYPE_GFX:
5653 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5654 		break;
5655 	case AMDGPU_RING_TYPE_KIQ:
5656 		cmd = (1 << 16); /* no inc addr */
5657 		break;
5658 	default:
5659 		cmd = WR_CONFIRM;
5660 		break;
5661 	}
5662 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5663 	amdgpu_ring_write(ring, cmd);
5664 	amdgpu_ring_write(ring, reg);
5665 	amdgpu_ring_write(ring, 0);
5666 	amdgpu_ring_write(ring, val);
5667 }
5668 
5669 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5670 					uint32_t val, uint32_t mask)
5671 {
5672 	gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5673 }
5674 
5675 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5676 						  uint32_t reg0, uint32_t reg1,
5677 						  uint32_t ref, uint32_t mask)
5678 {
5679 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5680 	struct amdgpu_device *adev = ring->adev;
5681 	bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
5682 		adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
5683 
5684 	if (fw_version_ok)
5685 		gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5686 				      ref, mask, 0x20);
5687 	else
5688 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
5689 							   ref, mask);
5690 }
5691 
5692 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
5693 {
5694 	struct amdgpu_device *adev = ring->adev;
5695 	uint32_t value = 0;
5696 
5697 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5698 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5699 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5700 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5701 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
5702 }
5703 
5704 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5705 						 enum amdgpu_interrupt_state state)
5706 {
5707 	switch (state) {
5708 	case AMDGPU_IRQ_STATE_DISABLE:
5709 	case AMDGPU_IRQ_STATE_ENABLE:
5710 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5711 			       TIME_STAMP_INT_ENABLE,
5712 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5713 		break;
5714 	default:
5715 		break;
5716 	}
5717 }
5718 
5719 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5720 						     int me, int pipe,
5721 						     enum amdgpu_interrupt_state state)
5722 {
5723 	u32 mec_int_cntl, mec_int_cntl_reg;
5724 
5725 	/*
5726 	 * amdgpu controls only the first MEC. That's why this function only
5727 	 * handles the setting of interrupts for this specific MEC. All other
5728 	 * pipes' interrupts are set by amdkfd.
5729 	 */
5730 
5731 	if (me == 1) {
5732 		switch (pipe) {
5733 		case 0:
5734 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5735 			break;
5736 		case 1:
5737 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5738 			break;
5739 		case 2:
5740 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5741 			break;
5742 		case 3:
5743 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5744 			break;
5745 		default:
5746 			DRM_DEBUG("invalid pipe %d\n", pipe);
5747 			return;
5748 		}
5749 	} else {
5750 		DRM_DEBUG("invalid me %d\n", me);
5751 		return;
5752 	}
5753 
5754 	switch (state) {
5755 	case AMDGPU_IRQ_STATE_DISABLE:
5756 		mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg);
5757 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5758 					     TIME_STAMP_INT_ENABLE, 0);
5759 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5760 		break;
5761 	case AMDGPU_IRQ_STATE_ENABLE:
5762 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5763 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5764 					     TIME_STAMP_INT_ENABLE, 1);
5765 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5766 		break;
5767 	default:
5768 		break;
5769 	}
5770 }
5771 
5772 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5773 					     struct amdgpu_irq_src *source,
5774 					     unsigned type,
5775 					     enum amdgpu_interrupt_state state)
5776 {
5777 	switch (state) {
5778 	case AMDGPU_IRQ_STATE_DISABLE:
5779 	case AMDGPU_IRQ_STATE_ENABLE:
5780 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5781 			       PRIV_REG_INT_ENABLE,
5782 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5783 		break;
5784 	default:
5785 		break;
5786 	}
5787 
5788 	return 0;
5789 }
5790 
5791 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5792 					      struct amdgpu_irq_src *source,
5793 					      unsigned type,
5794 					      enum amdgpu_interrupt_state state)
5795 {
5796 	switch (state) {
5797 	case AMDGPU_IRQ_STATE_DISABLE:
5798 	case AMDGPU_IRQ_STATE_ENABLE:
5799 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5800 			       PRIV_INSTR_INT_ENABLE,
5801 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5802 		break;
5803 	default:
5804 		break;
5805 	}
5806 
5807 	return 0;
5808 }
5809 
5810 #define ENABLE_ECC_ON_ME_PIPE(me, pipe)				\
5811 	WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5812 			CP_ECC_ERROR_INT_ENABLE, 1)
5813 
5814 #define DISABLE_ECC_ON_ME_PIPE(me, pipe)			\
5815 	WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\
5816 			CP_ECC_ERROR_INT_ENABLE, 0)
5817 
5818 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
5819 					      struct amdgpu_irq_src *source,
5820 					      unsigned type,
5821 					      enum amdgpu_interrupt_state state)
5822 {
5823 	switch (state) {
5824 	case AMDGPU_IRQ_STATE_DISABLE:
5825 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5826 				CP_ECC_ERROR_INT_ENABLE, 0);
5827 		DISABLE_ECC_ON_ME_PIPE(1, 0);
5828 		DISABLE_ECC_ON_ME_PIPE(1, 1);
5829 		DISABLE_ECC_ON_ME_PIPE(1, 2);
5830 		DISABLE_ECC_ON_ME_PIPE(1, 3);
5831 		break;
5832 
5833 	case AMDGPU_IRQ_STATE_ENABLE:
5834 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5835 				CP_ECC_ERROR_INT_ENABLE, 1);
5836 		ENABLE_ECC_ON_ME_PIPE(1, 0);
5837 		ENABLE_ECC_ON_ME_PIPE(1, 1);
5838 		ENABLE_ECC_ON_ME_PIPE(1, 2);
5839 		ENABLE_ECC_ON_ME_PIPE(1, 3);
5840 		break;
5841 	default:
5842 		break;
5843 	}
5844 
5845 	return 0;
5846 }
5847 
5848 
5849 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5850 					    struct amdgpu_irq_src *src,
5851 					    unsigned type,
5852 					    enum amdgpu_interrupt_state state)
5853 {
5854 	switch (type) {
5855 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5856 		gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
5857 		break;
5858 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5859 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5860 		break;
5861 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5862 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5863 		break;
5864 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5865 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5866 		break;
5867 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5868 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5869 		break;
5870 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5871 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5872 		break;
5873 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5874 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5875 		break;
5876 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5877 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5878 		break;
5879 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5880 		gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5881 		break;
5882 	default:
5883 		break;
5884 	}
5885 	return 0;
5886 }
5887 
5888 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
5889 			    struct amdgpu_irq_src *source,
5890 			    struct amdgpu_iv_entry *entry)
5891 {
5892 	int i;
5893 	u8 me_id, pipe_id, queue_id;
5894 	struct amdgpu_ring *ring;
5895 
5896 	DRM_DEBUG("IH: CP EOP\n");
5897 	me_id = (entry->ring_id & 0x0c) >> 2;
5898 	pipe_id = (entry->ring_id & 0x03) >> 0;
5899 	queue_id = (entry->ring_id & 0x70) >> 4;
5900 
5901 	switch (me_id) {
5902 	case 0:
5903 		if (adev->gfx.num_gfx_rings &&
5904 		    !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) {
5905 			/* Fence signals are handled on the software rings*/
5906 			for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++)
5907 				amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]);
5908 		}
5909 		break;
5910 	case 1:
5911 	case 2:
5912 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5913 			ring = &adev->gfx.compute_ring[i];
5914 			/* Per-queue interrupt is supported for MEC starting from VI.
5915 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
5916 			  */
5917 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
5918 				amdgpu_fence_process(ring);
5919 		}
5920 		break;
5921 	}
5922 	return 0;
5923 }
5924 
5925 static void gfx_v9_0_fault(struct amdgpu_device *adev,
5926 			   struct amdgpu_iv_entry *entry)
5927 {
5928 	u8 me_id, pipe_id, queue_id;
5929 	struct amdgpu_ring *ring;
5930 	int i;
5931 
5932 	me_id = (entry->ring_id & 0x0c) >> 2;
5933 	pipe_id = (entry->ring_id & 0x03) >> 0;
5934 	queue_id = (entry->ring_id & 0x70) >> 4;
5935 
5936 	switch (me_id) {
5937 	case 0:
5938 		drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
5939 		break;
5940 	case 1:
5941 	case 2:
5942 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5943 			ring = &adev->gfx.compute_ring[i];
5944 			if (ring->me == me_id && ring->pipe == pipe_id &&
5945 			    ring->queue == queue_id)
5946 				drm_sched_fault(&ring->sched);
5947 		}
5948 		break;
5949 	}
5950 }
5951 
5952 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
5953 				 struct amdgpu_irq_src *source,
5954 				 struct amdgpu_iv_entry *entry)
5955 {
5956 	DRM_ERROR("Illegal register access in command stream\n");
5957 	gfx_v9_0_fault(adev, entry);
5958 	return 0;
5959 }
5960 
5961 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
5962 				  struct amdgpu_irq_src *source,
5963 				  struct amdgpu_iv_entry *entry)
5964 {
5965 	DRM_ERROR("Illegal instruction in command stream\n");
5966 	gfx_v9_0_fault(adev, entry);
5967 	return 0;
5968 }
5969 
5970 
5971 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = {
5972 	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
5973 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
5974 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT)
5975 	},
5976 	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
5977 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
5978 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT)
5979 	},
5980 	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5981 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1),
5982 	  0, 0
5983 	},
5984 	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
5985 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2),
5986 	  0, 0
5987 	},
5988 	{ "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
5989 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
5990 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT)
5991 	},
5992 	{ "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5993 	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT),
5994 	  0, 0
5995 	},
5996 	{ "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT),
5997 	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
5998 	  SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT)
5999 	},
6000 	{ "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT),
6001 	  SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT),
6002 	  SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT)
6003 	},
6004 	{ "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
6005 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1),
6006 	  0, 0
6007 	},
6008 	{ "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
6009 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1),
6010 	  0, 0
6011 	},
6012 	{ "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
6013 	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1),
6014 	  0, 0
6015 	},
6016 	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
6017 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
6018 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED)
6019 	},
6020 	{ "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
6021 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED),
6022 	  0, 0
6023 	},
6024 	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6025 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
6026 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED)
6027 	},
6028 	{ "GDS_OA_PHY_PHY_CMD_RAM_MEM",
6029 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6030 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
6031 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED)
6032 	},
6033 	{ "GDS_OA_PHY_PHY_DATA_RAM_MEM",
6034 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6035 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED),
6036 	  0, 0
6037 	},
6038 	{ "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
6039 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6040 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
6041 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED)
6042 	},
6043 	{ "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
6044 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6045 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
6046 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED)
6047 	},
6048 	{ "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
6049 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6050 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
6051 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED)
6052 	},
6053 	{ "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
6054 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6055 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
6056 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED)
6057 	},
6058 	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
6059 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT),
6060 	  0, 0
6061 	},
6062 	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6063 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
6064 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT)
6065 	},
6066 	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6067 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT),
6068 	  0, 0
6069 	},
6070 	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6071 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT),
6072 	  0, 0
6073 	},
6074 	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6075 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT),
6076 	  0, 0
6077 	},
6078 	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
6079 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT),
6080 	  0, 0
6081 	},
6082 	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
6083 	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT),
6084 	  0, 0
6085 	},
6086 	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
6087 	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT),
6088 	  0, 0
6089 	},
6090 	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6091 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
6092 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT)
6093 	},
6094 	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6095 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
6096 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT)
6097 	},
6098 	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6099 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
6100 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT)
6101 	},
6102 	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6103 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
6104 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT)
6105 	},
6106 	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6107 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
6108 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT)
6109 	},
6110 	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6111 	  SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT),
6112 	  0, 0
6113 	},
6114 	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6115 	  SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT),
6116 	  0, 0
6117 	},
6118 	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6119 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT),
6120 	  0, 0
6121 	},
6122 	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6123 	  SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT),
6124 	  0, 0
6125 	},
6126 	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6127 	  SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT),
6128 	  0, 0
6129 	},
6130 	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
6131 	  SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT),
6132 	  0, 0
6133 	},
6134 	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6135 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT),
6136 	  0, 0
6137 	},
6138 	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6139 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT),
6140 	  0, 0
6141 	},
6142 	{ "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6143 	  SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT),
6144 	  0, 0
6145 	},
6146 	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6147 	  SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
6148 	  0, 0
6149 	},
6150 	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6151 	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT),
6152 	  0, 0
6153 	},
6154 	{ "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6155 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
6156 	  0, 0
6157 	},
6158 	{ "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
6159 	  SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT),
6160 	  0, 0
6161 	},
6162 	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
6163 	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT),
6164 	  0, 0
6165 	},
6166 	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6167 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
6168 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT)
6169 	},
6170 	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6171 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
6172 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT)
6173 	},
6174 	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6175 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT),
6176 	  0, 0
6177 	},
6178 	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6179 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
6180 	  0, 0
6181 	},
6182 	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6183 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT),
6184 	  0, 0
6185 	},
6186 	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6187 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
6188 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT)
6189 	},
6190 	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
6191 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
6192 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT)
6193 	},
6194 	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6195 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
6196 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT)
6197 	},
6198 	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6199 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
6200 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT)
6201 	},
6202 	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
6203 	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT),
6204 	  0, 0
6205 	},
6206 	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6207 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
6208 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT)
6209 	},
6210 	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6211 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
6212 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT)
6213 	},
6214 	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6215 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
6216 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT)
6217 	},
6218 	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6219 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
6220 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT)
6221 	},
6222 	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6223 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
6224 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT)
6225 	},
6226 	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6227 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
6228 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT)
6229 	},
6230 	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6231 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
6232 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT)
6233 	},
6234 	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6235 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
6236 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT)
6237 	},
6238 	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6239 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
6240 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT)
6241 	},
6242 	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6243 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
6244 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT)
6245 	},
6246 	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6247 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
6248 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT)
6249 	},
6250 	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6251 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
6252 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT)
6253 	},
6254 	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
6255 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
6256 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT)
6257 	},
6258 	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6259 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
6260 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT)
6261 	},
6262 	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6263 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
6264 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT)
6265 	},
6266 	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6267 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
6268 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT)
6269 	},
6270 	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6271 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
6272 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT)
6273 	},
6274 	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6275 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
6276 	  0, 0
6277 	},
6278 	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6279 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT),
6280 	  0, 0
6281 	},
6282 	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6283 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT),
6284 	  0, 0
6285 	},
6286 	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6287 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT),
6288 	  0, 0
6289 	},
6290 	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6291 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT),
6292 	  0, 0
6293 	},
6294 	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
6295 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
6296 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT)
6297 	},
6298 	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6299 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
6300 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT)
6301 	},
6302 	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6303 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
6304 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT)
6305 	},
6306 	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6307 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
6308 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT)
6309 	},
6310 	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6311 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
6312 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT)
6313 	},
6314 	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6315 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
6316 	  0, 0
6317 	},
6318 	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6319 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT),
6320 	  0, 0
6321 	},
6322 	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6323 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT),
6324 	  0, 0
6325 	},
6326 	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6327 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT),
6328 	  0, 0
6329 	},
6330 	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
6331 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT),
6332 	  0, 0
6333 	},
6334 	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6335 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
6336 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT)
6337 	},
6338 	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6339 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
6340 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT)
6341 	},
6342 	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6343 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
6344 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT)
6345 	},
6346 	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6347 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
6348 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT)
6349 	},
6350 	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6351 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
6352 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT)
6353 	},
6354 	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6355 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
6356 	  0, 0
6357 	},
6358 	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6359 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
6360 	  0, 0
6361 	},
6362 	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6363 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT),
6364 	  0, 0
6365 	},
6366 	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6367 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
6368 	  0, 0
6369 	},
6370 	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
6371 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
6372 	  0, 0
6373 	},
6374 	{ "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6375 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
6376 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT)
6377 	},
6378 	{ "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6379 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
6380 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT)
6381 	},
6382 	{ "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6383 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
6384 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT)
6385 	},
6386 	{ "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6387 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
6388 	  0, 0
6389 	},
6390 	{ "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6391 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
6392 	  0, 0
6393 	},
6394 	{ "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6395 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
6396 	  0, 0
6397 	},
6398 	{ "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6399 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
6400 	  0, 0
6401 	},
6402 	{ "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6403 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
6404 	  0, 0
6405 	},
6406 	{ "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
6407 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
6408 	  0, 0
6409 	}
6410 };
6411 
6412 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
6413 				     void *inject_if, uint32_t instance_mask)
6414 {
6415 	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
6416 	int ret;
6417 	struct ta_ras_trigger_error_input block_info = { 0 };
6418 
6419 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6420 		return -EINVAL;
6421 
6422 	if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
6423 		return -EINVAL;
6424 
6425 	if (!ras_gfx_subblocks[info->head.sub_block_index].name)
6426 		return -EPERM;
6427 
6428 	if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
6429 	      info->head.type)) {
6430 		DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
6431 			ras_gfx_subblocks[info->head.sub_block_index].name,
6432 			info->head.type);
6433 		return -EPERM;
6434 	}
6435 
6436 	if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
6437 	      info->head.type)) {
6438 		DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
6439 			ras_gfx_subblocks[info->head.sub_block_index].name,
6440 			info->head.type);
6441 		return -EPERM;
6442 	}
6443 
6444 	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
6445 	block_info.sub_block_index =
6446 		ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
6447 	block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
6448 	block_info.address = info->address;
6449 	block_info.value = info->value;
6450 
6451 	mutex_lock(&adev->grbm_idx_mutex);
6452 	ret = psp_ras_trigger_error(&adev->psp, &block_info, instance_mask);
6453 	mutex_unlock(&adev->grbm_idx_mutex);
6454 
6455 	return ret;
6456 }
6457 
6458 static const char *vml2_mems[] = {
6459 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
6460 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
6461 	"UTC_VML2_BANK_CACHE_0_4K_MEM0",
6462 	"UTC_VML2_BANK_CACHE_0_4K_MEM1",
6463 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
6464 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
6465 	"UTC_VML2_BANK_CACHE_1_4K_MEM0",
6466 	"UTC_VML2_BANK_CACHE_1_4K_MEM1",
6467 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
6468 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
6469 	"UTC_VML2_BANK_CACHE_2_4K_MEM0",
6470 	"UTC_VML2_BANK_CACHE_2_4K_MEM1",
6471 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
6472 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
6473 	"UTC_VML2_BANK_CACHE_3_4K_MEM0",
6474 	"UTC_VML2_BANK_CACHE_3_4K_MEM1",
6475 };
6476 
6477 static const char *vml2_walker_mems[] = {
6478 	"UTC_VML2_CACHE_PDE0_MEM0",
6479 	"UTC_VML2_CACHE_PDE0_MEM1",
6480 	"UTC_VML2_CACHE_PDE1_MEM0",
6481 	"UTC_VML2_CACHE_PDE1_MEM1",
6482 	"UTC_VML2_CACHE_PDE2_MEM0",
6483 	"UTC_VML2_CACHE_PDE2_MEM1",
6484 	"UTC_VML2_RDIF_LOG_FIFO",
6485 };
6486 
6487 static const char *atc_l2_cache_2m_mems[] = {
6488 	"UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
6489 	"UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
6490 	"UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
6491 	"UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
6492 };
6493 
6494 static const char *atc_l2_cache_4k_mems[] = {
6495 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
6496 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
6497 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
6498 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
6499 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
6500 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
6501 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
6502 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
6503 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
6504 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
6505 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
6506 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
6507 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
6508 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
6509 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
6510 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
6511 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
6512 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
6513 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
6514 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
6515 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
6516 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
6517 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
6518 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
6519 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
6520 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
6521 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
6522 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
6523 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
6524 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
6525 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
6526 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
6527 };
6528 
6529 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
6530 					 struct ras_err_data *err_data)
6531 {
6532 	uint32_t i, data;
6533 	uint32_t sec_count, ded_count;
6534 
6535 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6536 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6537 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6538 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6539 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6540 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6541 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6542 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6543 
6544 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6545 		WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6546 		data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6547 
6548 		sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
6549 		if (sec_count) {
6550 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6551 				"SEC %d\n", i, vml2_mems[i], sec_count);
6552 			err_data->ce_count += sec_count;
6553 		}
6554 
6555 		ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
6556 		if (ded_count) {
6557 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6558 				"DED %d\n", i, vml2_mems[i], ded_count);
6559 			err_data->ue_count += ded_count;
6560 		}
6561 	}
6562 
6563 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6564 		WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6565 		data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6566 
6567 		sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6568 						SEC_COUNT);
6569 		if (sec_count) {
6570 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6571 				"SEC %d\n", i, vml2_walker_mems[i], sec_count);
6572 			err_data->ce_count += sec_count;
6573 		}
6574 
6575 		ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT,
6576 						DED_COUNT);
6577 		if (ded_count) {
6578 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6579 				"DED %d\n", i, vml2_walker_mems[i], ded_count);
6580 			err_data->ue_count += ded_count;
6581 		}
6582 	}
6583 
6584 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6585 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6586 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6587 
6588 		sec_count = (data & 0x00006000L) >> 0xd;
6589 		if (sec_count) {
6590 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6591 				"SEC %d\n", i, atc_l2_cache_2m_mems[i],
6592 				sec_count);
6593 			err_data->ce_count += sec_count;
6594 		}
6595 	}
6596 
6597 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6598 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6599 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6600 
6601 		sec_count = (data & 0x00006000L) >> 0xd;
6602 		if (sec_count) {
6603 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6604 				"SEC %d\n", i, atc_l2_cache_4k_mems[i],
6605 				sec_count);
6606 			err_data->ce_count += sec_count;
6607 		}
6608 
6609 		ded_count = (data & 0x00018000L) >> 0xf;
6610 		if (ded_count) {
6611 			dev_info(adev->dev, "Instance[%d]: SubBlock %s, "
6612 				"DED %d\n", i, atc_l2_cache_4k_mems[i],
6613 				ded_count);
6614 			err_data->ue_count += ded_count;
6615 		}
6616 	}
6617 
6618 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6619 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6620 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6621 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6622 
6623 	return 0;
6624 }
6625 
6626 static int gfx_v9_0_ras_error_count(struct amdgpu_device *adev,
6627 	const struct soc15_reg_entry *reg,
6628 	uint32_t se_id, uint32_t inst_id, uint32_t value,
6629 	uint32_t *sec_count, uint32_t *ded_count)
6630 {
6631 	uint32_t i;
6632 	uint32_t sec_cnt, ded_cnt;
6633 
6634 	for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) {
6635 		if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset ||
6636 			gfx_v9_0_ras_fields[i].seg != reg->seg ||
6637 			gfx_v9_0_ras_fields[i].inst != reg->inst)
6638 			continue;
6639 
6640 		sec_cnt = (value &
6641 				gfx_v9_0_ras_fields[i].sec_count_mask) >>
6642 				gfx_v9_0_ras_fields[i].sec_count_shift;
6643 		if (sec_cnt) {
6644 			dev_info(adev->dev, "GFX SubBlock %s, "
6645 				"Instance[%d][%d], SEC %d\n",
6646 				gfx_v9_0_ras_fields[i].name,
6647 				se_id, inst_id,
6648 				sec_cnt);
6649 			*sec_count += sec_cnt;
6650 		}
6651 
6652 		ded_cnt = (value &
6653 				gfx_v9_0_ras_fields[i].ded_count_mask) >>
6654 				gfx_v9_0_ras_fields[i].ded_count_shift;
6655 		if (ded_cnt) {
6656 			dev_info(adev->dev, "GFX SubBlock %s, "
6657 				"Instance[%d][%d], DED %d\n",
6658 				gfx_v9_0_ras_fields[i].name,
6659 				se_id, inst_id,
6660 				ded_cnt);
6661 			*ded_count += ded_cnt;
6662 		}
6663 	}
6664 
6665 	return 0;
6666 }
6667 
6668 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev)
6669 {
6670 	int i, j, k;
6671 
6672 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6673 		return;
6674 
6675 	/* read back registers to clear the counters */
6676 	mutex_lock(&adev->grbm_idx_mutex);
6677 	for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6678 		for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6679 			for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6680 				amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0);
6681 				RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6682 			}
6683 		}
6684 	}
6685 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
6686 	mutex_unlock(&adev->grbm_idx_mutex);
6687 
6688 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6689 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
6690 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6691 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
6692 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6693 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
6694 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6695 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
6696 
6697 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
6698 		WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
6699 		RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
6700 	}
6701 
6702 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
6703 		WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i);
6704 		RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT);
6705 	}
6706 
6707 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
6708 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i);
6709 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT);
6710 	}
6711 
6712 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
6713 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i);
6714 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT);
6715 	}
6716 
6717 	WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
6718 	WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
6719 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
6720 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
6721 }
6722 
6723 static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
6724 					  void *ras_error_status)
6725 {
6726 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
6727 	uint32_t sec_count = 0, ded_count = 0;
6728 	uint32_t i, j, k;
6729 	uint32_t reg_value;
6730 
6731 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6732 		return;
6733 
6734 	err_data->ue_count = 0;
6735 	err_data->ce_count = 0;
6736 
6737 	mutex_lock(&adev->grbm_idx_mutex);
6738 
6739 	for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) {
6740 		for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) {
6741 			for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) {
6742 				amdgpu_gfx_select_se_sh(adev, j, 0, k, 0);
6743 				reg_value =
6744 					RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i]));
6745 				if (reg_value)
6746 					gfx_v9_0_ras_error_count(adev,
6747 						&gfx_v9_0_edc_counter_regs[i],
6748 						j, k, reg_value,
6749 						&sec_count, &ded_count);
6750 			}
6751 		}
6752 	}
6753 
6754 	err_data->ce_count += sec_count;
6755 	err_data->ue_count += ded_count;
6756 
6757 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6758 	mutex_unlock(&adev->grbm_idx_mutex);
6759 
6760 	gfx_v9_0_query_utc_edc_status(adev, err_data);
6761 }
6762 
6763 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
6764 {
6765 	const unsigned int cp_coher_cntl =
6766 			PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
6767 			PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
6768 			PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
6769 			PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
6770 			PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
6771 
6772 	/* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
6773 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6774 	amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
6775 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6776 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6777 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6778 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6779 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6780 }
6781 
6782 static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
6783 					uint32_t pipe, bool enable)
6784 {
6785 	struct amdgpu_device *adev = ring->adev;
6786 	uint32_t val;
6787 	uint32_t wcl_cs_reg;
6788 
6789 	/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6790 	val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT;
6791 
6792 	switch (pipe) {
6793 	case 0:
6794 		wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0);
6795 		break;
6796 	case 1:
6797 		wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1);
6798 		break;
6799 	case 2:
6800 		wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2);
6801 		break;
6802 	case 3:
6803 		wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3);
6804 		break;
6805 	default:
6806 		DRM_DEBUG("invalid pipe %d\n", pipe);
6807 		return;
6808 	}
6809 
6810 	amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
6811 
6812 }
6813 static void gfx_v9_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
6814 {
6815 	struct amdgpu_device *adev = ring->adev;
6816 	uint32_t val;
6817 	int i;
6818 
6819 
6820 	/* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
6821 	 * number of gfx waves. Setting 5 bit will make sure gfx only gets
6822 	 * around 25% of gpu resources.
6823 	 */
6824 	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
6825 	amdgpu_ring_emit_wreg(ring,
6826 			      SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX),
6827 			      val);
6828 
6829 	/* Restrict waves for normal/low priority compute queues as well
6830 	 * to get best QoS for high priority compute jobs.
6831 	 *
6832 	 * amdgpu controls only 1st ME(0-3 CS pipes).
6833 	 */
6834 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
6835 		if (i != ring->pipe)
6836 			gfx_v9_0_emit_wave_limit_cs(ring, i, enable);
6837 
6838 	}
6839 }
6840 
6841 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
6842 	.name = "gfx_v9_0",
6843 	.early_init = gfx_v9_0_early_init,
6844 	.late_init = gfx_v9_0_late_init,
6845 	.sw_init = gfx_v9_0_sw_init,
6846 	.sw_fini = gfx_v9_0_sw_fini,
6847 	.hw_init = gfx_v9_0_hw_init,
6848 	.hw_fini = gfx_v9_0_hw_fini,
6849 	.suspend = gfx_v9_0_suspend,
6850 	.resume = gfx_v9_0_resume,
6851 	.is_idle = gfx_v9_0_is_idle,
6852 	.wait_for_idle = gfx_v9_0_wait_for_idle,
6853 	.soft_reset = gfx_v9_0_soft_reset,
6854 	.set_clockgating_state = gfx_v9_0_set_clockgating_state,
6855 	.set_powergating_state = gfx_v9_0_set_powergating_state,
6856 	.get_clockgating_state = gfx_v9_0_get_clockgating_state,
6857 };
6858 
6859 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
6860 	.type = AMDGPU_RING_TYPE_GFX,
6861 	.align_mask = 0xff,
6862 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6863 	.support_64bit_ptrs = true,
6864 	.secure_submission_supported = true,
6865 	.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
6866 	.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
6867 	.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
6868 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
6869 		5 +  /* COND_EXEC */
6870 		7 +  /* PIPELINE_SYNC */
6871 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6872 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6873 		2 + /* VM_FLUSH */
6874 		8 +  /* FENCE for VM_FLUSH */
6875 		20 + /* GDS switch */
6876 		4 + /* double SWITCH_BUFFER,
6877 		       the first COND_EXEC jump to the place just
6878 			   prior to this double SWITCH_BUFFER  */
6879 		5 + /* COND_EXEC */
6880 		7 +	 /*	HDP_flush */
6881 		4 +	 /*	VGT_flush */
6882 		14 + /*	CE_META */
6883 		31 + /*	DE_META */
6884 		3 + /* CNTX_CTRL */
6885 		5 + /* HDP_INVL */
6886 		8 + 8 + /* FENCE x2 */
6887 		2 + /* SWITCH_BUFFER */
6888 		7, /* gfx_v9_0_emit_mem_sync */
6889 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_gfx */
6890 	.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
6891 	.emit_fence = gfx_v9_0_ring_emit_fence,
6892 	.emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6893 	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6894 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6895 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6896 	.test_ring = gfx_v9_0_ring_test_ring,
6897 	.insert_nop = amdgpu_ring_insert_nop,
6898 	.pad_ib = amdgpu_ring_generic_pad_ib,
6899 	.emit_switch_buffer = gfx_v9_ring_emit_sb,
6900 	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
6901 	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
6902 	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
6903 	.preempt_ib = gfx_v9_0_ring_preempt_ib,
6904 	.emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
6905 	.emit_wreg = gfx_v9_0_ring_emit_wreg,
6906 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6907 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6908 	.soft_recovery = gfx_v9_0_ring_soft_recovery,
6909 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
6910 };
6911 
6912 static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {
6913 	.type = AMDGPU_RING_TYPE_GFX,
6914 	.align_mask = 0xff,
6915 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6916 	.support_64bit_ptrs = true,
6917 	.secure_submission_supported = true,
6918 	.get_rptr = amdgpu_sw_ring_get_rptr_gfx,
6919 	.get_wptr = amdgpu_sw_ring_get_wptr_gfx,
6920 	.set_wptr = amdgpu_sw_ring_set_wptr_gfx,
6921 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
6922 		5 +  /* COND_EXEC */
6923 		7 +  /* PIPELINE_SYNC */
6924 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6925 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6926 		2 + /* VM_FLUSH */
6927 		8 +  /* FENCE for VM_FLUSH */
6928 		20 + /* GDS switch */
6929 		4 + /* double SWITCH_BUFFER,
6930 		     * the first COND_EXEC jump to the place just
6931 		     * prior to this double SWITCH_BUFFER
6932 		     */
6933 		5 + /* COND_EXEC */
6934 		7 +	 /*	HDP_flush */
6935 		4 +	 /*	VGT_flush */
6936 		14 + /*	CE_META */
6937 		31 + /*	DE_META */
6938 		3 + /* CNTX_CTRL */
6939 		5 + /* HDP_INVL */
6940 		8 + 8 + /* FENCE x2 */
6941 		2 + /* SWITCH_BUFFER */
6942 		7, /* gfx_v9_0_emit_mem_sync */
6943 	.emit_ib_size =	4, /* gfx_v9_0_ring_emit_ib_gfx */
6944 	.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
6945 	.emit_fence = gfx_v9_0_ring_emit_fence,
6946 	.emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6947 	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6948 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6949 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6950 	.test_ring = gfx_v9_0_ring_test_ring,
6951 	.test_ib = gfx_v9_0_ring_test_ib,
6952 	.insert_nop = amdgpu_sw_ring_insert_nop,
6953 	.pad_ib = amdgpu_ring_generic_pad_ib,
6954 	.emit_switch_buffer = gfx_v9_ring_emit_sb,
6955 	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
6956 	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
6957 	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
6958 	.emit_frame_cntl = gfx_v9_0_ring_emit_frame_cntl,
6959 	.emit_wreg = gfx_v9_0_ring_emit_wreg,
6960 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
6961 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
6962 	.soft_recovery = gfx_v9_0_ring_soft_recovery,
6963 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
6964 	.patch_cntl = gfx_v9_0_ring_patch_cntl,
6965 	.patch_de = gfx_v9_0_ring_patch_de_meta,
6966 	.patch_ce = gfx_v9_0_ring_patch_ce_meta,
6967 };
6968 
6969 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
6970 	.type = AMDGPU_RING_TYPE_COMPUTE,
6971 	.align_mask = 0xff,
6972 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6973 	.support_64bit_ptrs = true,
6974 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
6975 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
6976 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
6977 	.emit_frame_size =
6978 		20 + /* gfx_v9_0_ring_emit_gds_switch */
6979 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
6980 		5 + /* hdp invalidate */
6981 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
6982 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6983 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6984 		2 + /* gfx_v9_0_ring_emit_vm_flush */
6985 		8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
6986 		7 + /* gfx_v9_0_emit_mem_sync */
6987 		5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
6988 		15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
6989 	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */
6990 	.emit_ib = gfx_v9_0_ring_emit_ib_compute,
6991 	.emit_fence = gfx_v9_0_ring_emit_fence,
6992 	.emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
6993 	.emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
6994 	.emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
6995 	.emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
6996 	.test_ring = gfx_v9_0_ring_test_ring,
6997 	.test_ib = gfx_v9_0_ring_test_ib,
6998 	.insert_nop = amdgpu_ring_insert_nop,
6999 	.pad_ib = amdgpu_ring_generic_pad_ib,
7000 	.emit_wreg = gfx_v9_0_ring_emit_wreg,
7001 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
7002 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
7003 	.emit_mem_sync = gfx_v9_0_emit_mem_sync,
7004 	.emit_wave_limit = gfx_v9_0_emit_wave_limit,
7005 };
7006 
7007 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
7008 	.type = AMDGPU_RING_TYPE_KIQ,
7009 	.align_mask = 0xff,
7010 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7011 	.support_64bit_ptrs = true,
7012 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
7013 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
7014 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
7015 	.emit_frame_size =
7016 		20 + /* gfx_v9_0_ring_emit_gds_switch */
7017 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
7018 		5 + /* hdp invalidate */
7019 		7 + /* gfx_v9_0_ring_emit_pipeline_sync */
7020 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
7021 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
7022 		2 + /* gfx_v9_0_ring_emit_vm_flush */
7023 		8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
7024 	.emit_ib_size =	7, /* gfx_v9_0_ring_emit_ib_compute */
7025 	.emit_fence = gfx_v9_0_ring_emit_fence_kiq,
7026 	.test_ring = gfx_v9_0_ring_test_ring,
7027 	.insert_nop = amdgpu_ring_insert_nop,
7028 	.pad_ib = amdgpu_ring_generic_pad_ib,
7029 	.emit_rreg = gfx_v9_0_ring_emit_rreg,
7030 	.emit_wreg = gfx_v9_0_ring_emit_wreg,
7031 	.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
7032 	.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
7033 };
7034 
7035 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
7036 {
7037 	int i;
7038 
7039 	adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq;
7040 
7041 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7042 		adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
7043 
7044 	if (adev->gfx.num_gfx_rings) {
7045 		for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++)
7046 			adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx;
7047 	}
7048 
7049 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
7050 		adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
7051 }
7052 
7053 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
7054 	.set = gfx_v9_0_set_eop_interrupt_state,
7055 	.process = gfx_v9_0_eop_irq,
7056 };
7057 
7058 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
7059 	.set = gfx_v9_0_set_priv_reg_fault_state,
7060 	.process = gfx_v9_0_priv_reg_irq,
7061 };
7062 
7063 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
7064 	.set = gfx_v9_0_set_priv_inst_fault_state,
7065 	.process = gfx_v9_0_priv_inst_irq,
7066 };
7067 
7068 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = {
7069 	.set = gfx_v9_0_set_cp_ecc_error_state,
7070 	.process = amdgpu_gfx_cp_ecc_error_irq,
7071 };
7072 
7073 
7074 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
7075 {
7076 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7077 	adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
7078 
7079 	adev->gfx.priv_reg_irq.num_types = 1;
7080 	adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
7081 
7082 	adev->gfx.priv_inst_irq.num_types = 1;
7083 	adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
7084 
7085 	adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
7086 	adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
7087 }
7088 
7089 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
7090 {
7091 	switch (adev->ip_versions[GC_HWIP][0]) {
7092 	case IP_VERSION(9, 0, 1):
7093 	case IP_VERSION(9, 2, 1):
7094 	case IP_VERSION(9, 4, 0):
7095 	case IP_VERSION(9, 2, 2):
7096 	case IP_VERSION(9, 1, 0):
7097 	case IP_VERSION(9, 4, 1):
7098 	case IP_VERSION(9, 3, 0):
7099 	case IP_VERSION(9, 4, 2):
7100 		adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
7101 		break;
7102 	default:
7103 		break;
7104 	}
7105 }
7106 
7107 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
7108 {
7109 	/* init asci gds info */
7110 	switch (adev->ip_versions[GC_HWIP][0]) {
7111 	case IP_VERSION(9, 0, 1):
7112 	case IP_VERSION(9, 2, 1):
7113 	case IP_VERSION(9, 4, 0):
7114 		adev->gds.gds_size = 0x10000;
7115 		break;
7116 	case IP_VERSION(9, 2, 2):
7117 	case IP_VERSION(9, 1, 0):
7118 	case IP_VERSION(9, 4, 1):
7119 		adev->gds.gds_size = 0x1000;
7120 		break;
7121 	case IP_VERSION(9, 4, 2):
7122 		/* aldebaran removed all the GDS internal memory,
7123 		 * only support GWS opcode in kernel, like barrier
7124 		 * semaphore.etc */
7125 		adev->gds.gds_size = 0;
7126 		break;
7127 	default:
7128 		adev->gds.gds_size = 0x10000;
7129 		break;
7130 	}
7131 
7132 	switch (adev->ip_versions[GC_HWIP][0]) {
7133 	case IP_VERSION(9, 0, 1):
7134 	case IP_VERSION(9, 4, 0):
7135 		adev->gds.gds_compute_max_wave_id = 0x7ff;
7136 		break;
7137 	case IP_VERSION(9, 2, 1):
7138 		adev->gds.gds_compute_max_wave_id = 0x27f;
7139 		break;
7140 	case IP_VERSION(9, 2, 2):
7141 	case IP_VERSION(9, 1, 0):
7142 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
7143 			adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
7144 		else
7145 			adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
7146 		break;
7147 	case IP_VERSION(9, 4, 1):
7148 		adev->gds.gds_compute_max_wave_id = 0xfff;
7149 		break;
7150 	case IP_VERSION(9, 4, 2):
7151 		/* deprecated for Aldebaran, no usage at all */
7152 		adev->gds.gds_compute_max_wave_id = 0;
7153 		break;
7154 	default:
7155 		/* this really depends on the chip */
7156 		adev->gds.gds_compute_max_wave_id = 0x7ff;
7157 		break;
7158 	}
7159 
7160 	adev->gds.gws_size = 64;
7161 	adev->gds.oa_size = 16;
7162 }
7163 
7164 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7165 						 u32 bitmap)
7166 {
7167 	u32 data;
7168 
7169 	if (!bitmap)
7170 		return;
7171 
7172 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7173 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7174 
7175 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
7176 }
7177 
7178 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7179 {
7180 	u32 data, mask;
7181 
7182 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
7183 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
7184 
7185 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7186 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7187 
7188 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7189 
7190 	return (~data) & mask;
7191 }
7192 
7193 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
7194 				 struct amdgpu_cu_info *cu_info)
7195 {
7196 	int i, j, k, counter, active_cu_number = 0;
7197 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7198 	unsigned disable_masks[4 * 4];
7199 
7200 	if (!adev || !cu_info)
7201 		return -EINVAL;
7202 
7203 	/*
7204 	 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
7205 	 */
7206 	if (adev->gfx.config.max_shader_engines *
7207 		adev->gfx.config.max_sh_per_se > 16)
7208 		return -EINVAL;
7209 
7210 	amdgpu_gfx_parse_disable_cu(disable_masks,
7211 				    adev->gfx.config.max_shader_engines,
7212 				    adev->gfx.config.max_sh_per_se);
7213 
7214 	mutex_lock(&adev->grbm_idx_mutex);
7215 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7216 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7217 			mask = 1;
7218 			ao_bitmap = 0;
7219 			counter = 0;
7220 			amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0);
7221 			gfx_v9_0_set_user_cu_inactive_bitmap(
7222 				adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
7223 			bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
7224 
7225 			/*
7226 			 * The bitmap(and ao_cu_bitmap) in cu_info structure is
7227 			 * 4x4 size array, and it's usually suitable for Vega
7228 			 * ASICs which has 4*2 SE/SH layout.
7229 			 * But for Arcturus, SE/SH layout is changed to 8*1.
7230 			 * To mostly reduce the impact, we make it compatible
7231 			 * with current bitmap array as below:
7232 			 *    SE4,SH0 --> bitmap[0][1]
7233 			 *    SE5,SH0 --> bitmap[1][1]
7234 			 *    SE6,SH0 --> bitmap[2][1]
7235 			 *    SE7,SH0 --> bitmap[3][1]
7236 			 */
7237 			cu_info->bitmap[i % 4][j + i / 4] = bitmap;
7238 
7239 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7240 				if (bitmap & mask) {
7241 					if (counter < adev->gfx.config.max_cu_per_sh)
7242 						ao_bitmap |= mask;
7243 					counter ++;
7244 				}
7245 				mask <<= 1;
7246 			}
7247 			active_cu_number += counter;
7248 			if (i < 2 && j < 2)
7249 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7250 			cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
7251 		}
7252 	}
7253 	amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
7254 	mutex_unlock(&adev->grbm_idx_mutex);
7255 
7256 	cu_info->number = active_cu_number;
7257 	cu_info->ao_cu_mask = ao_cu_mask;
7258 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7259 
7260 	return 0;
7261 }
7262 
7263 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
7264 {
7265 	.type = AMD_IP_BLOCK_TYPE_GFX,
7266 	.major = 9,
7267 	.minor = 0,
7268 	.rev = 0,
7269 	.funcs = &gfx_v9_0_ip_funcs,
7270 };
7271