1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "vi.h" 28 #include "vi_structs.h" 29 #include "vid.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_atombios.h" 32 #include "atombios_i2c.h" 33 #include "clearstate_vi.h" 34 35 #include "gmc/gmc_8_2_d.h" 36 #include "gmc/gmc_8_2_sh_mask.h" 37 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 41 #include "bif/bif_5_0_d.h" 42 #include "bif/bif_5_0_sh_mask.h" 43 #include "gca/gfx_8_0_d.h" 44 #include "gca/gfx_8_0_enum.h" 45 #include "gca/gfx_8_0_sh_mask.h" 46 #include "gca/gfx_8_0_enum.h" 47 48 #include "dce/dce_10_0_d.h" 49 #include "dce/dce_10_0_sh_mask.h" 50 51 #include "smu/smu_7_1_3_d.h" 52 53 #define GFX8_NUM_GFX_RINGS 1 54 #define GFX8_MEC_HPD_SIZE 2048 55 56 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 57 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 58 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 59 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 60 61 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 62 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 63 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 64 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) 65 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 66 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) 67 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) 68 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) 69 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) 70 71 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L 72 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L 73 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L 74 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L 75 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L 76 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L 77 78 /* BPM SERDES CMD */ 79 #define SET_BPM_SERDES_CMD 1 80 #define CLE_BPM_SERDES_CMD 0 81 82 /* BPM Register Address*/ 83 enum { 84 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */ 85 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */ 86 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */ 87 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */ 88 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */ 89 BPM_REG_FGCG_MAX 90 }; 91 92 #define RLC_FormatDirectRegListLength 14 93 94 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); 95 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); 96 MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); 97 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); 98 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); 99 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); 100 101 MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); 102 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); 103 MODULE_FIRMWARE("amdgpu/stoney_me.bin"); 104 MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); 105 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); 106 107 MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); 108 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); 109 MODULE_FIRMWARE("amdgpu/tonga_me.bin"); 110 MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); 111 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); 112 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); 113 114 MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); 115 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); 116 MODULE_FIRMWARE("amdgpu/topaz_me.bin"); 117 MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); 118 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); 119 120 MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); 121 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); 122 MODULE_FIRMWARE("amdgpu/fiji_me.bin"); 123 MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); 124 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); 125 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); 126 127 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); 128 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin"); 129 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); 130 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin"); 131 MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); 132 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin"); 133 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); 134 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin"); 135 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); 136 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin"); 137 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); 138 139 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); 140 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin"); 141 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); 142 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin"); 143 MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); 144 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin"); 145 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); 146 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin"); 147 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); 148 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin"); 149 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); 150 151 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin"); 152 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin"); 153 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin"); 154 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin"); 155 MODULE_FIRMWARE("amdgpu/polaris12_me.bin"); 156 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin"); 157 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin"); 158 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin"); 159 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin"); 160 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin"); 161 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin"); 162 163 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 164 { 165 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 166 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 167 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 168 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 169 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 170 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 171 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 172 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 173 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 174 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 175 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 176 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 177 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 178 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 179 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 180 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 181 }; 182 183 static const u32 golden_settings_tonga_a11[] = 184 { 185 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, 186 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 187 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 188 mmGB_GPU_ID, 0x0000000f, 0x00000000, 189 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 190 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 191 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 192 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 193 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 194 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 195 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 196 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 197 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, 198 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 199 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 200 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 201 }; 202 203 static const u32 tonga_golden_common_all[] = 204 { 205 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 206 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 207 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 208 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 209 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 210 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 211 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 212 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 213 }; 214 215 static const u32 tonga_mgcg_cgcg_init[] = 216 { 217 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 218 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 219 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 220 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 221 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 222 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 223 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 224 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 225 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 226 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 227 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 228 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 229 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 230 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 231 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 232 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 233 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 234 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 235 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 236 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 237 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 238 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 239 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 240 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 241 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 242 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 243 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 244 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 245 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 246 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 247 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 248 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 249 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 250 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 251 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 252 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 253 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 254 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 255 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 256 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 257 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 258 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 259 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 260 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 261 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 262 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 263 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 264 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 265 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 266 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 267 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 268 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 269 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 270 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 271 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 272 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 273 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 274 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 275 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 276 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 277 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 278 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 279 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 280 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 281 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 282 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 283 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 284 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 285 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 286 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 287 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 288 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 289 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 290 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 291 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 292 }; 293 294 static const u32 golden_settings_polaris11_a11[] = 295 { 296 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208, 297 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000, 298 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 299 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 300 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 301 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 302 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, 303 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 304 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 305 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, 306 mmSQ_CONFIG, 0x07f80000, 0x01180000, 307 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 308 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 309 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 310 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 311 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 312 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 313 }; 314 315 static const u32 polaris11_golden_common_all[] = 316 { 317 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 318 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002, 319 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 320 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 321 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 322 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 323 }; 324 325 static const u32 golden_settings_polaris10_a11[] = 326 { 327 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, 328 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208, 329 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000, 330 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 331 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 332 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 333 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 334 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012, 335 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a, 336 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 337 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c, 338 mmSQ_CONFIG, 0x07f80000, 0x07180000, 339 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 340 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 341 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 342 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 343 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 344 }; 345 346 static const u32 polaris10_golden_common_all[] = 347 { 348 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 349 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 350 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 351 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 352 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 353 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 354 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 355 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 356 }; 357 358 static const u32 fiji_golden_common_all[] = 359 { 360 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 361 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, 362 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, 363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 368 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 369 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, 370 }; 371 372 static const u32 golden_settings_fiji_a10[] = 373 { 374 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, 375 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 376 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 377 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 378 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 379 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 380 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 381 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 382 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 383 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, 384 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 385 }; 386 387 static const u32 fiji_mgcg_cgcg_init[] = 388 { 389 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 390 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 391 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 392 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 393 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 394 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 395 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 396 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 397 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 398 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 399 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 400 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 401 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 402 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 403 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 404 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 405 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 406 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 407 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 408 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 409 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 410 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 411 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 412 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 413 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 414 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 415 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 416 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 417 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 418 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 419 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 420 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 421 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 422 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 423 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 424 }; 425 426 static const u32 golden_settings_iceland_a11[] = 427 { 428 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 429 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 430 mmDB_DEBUG3, 0xc0000000, 0xc0000000, 431 mmGB_GPU_ID, 0x0000000f, 0x00000000, 432 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 433 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 434 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, 435 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 436 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 437 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 438 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 439 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 440 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 441 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 442 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 443 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, 444 }; 445 446 static const u32 iceland_golden_common_all[] = 447 { 448 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 449 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 450 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 451 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 452 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 453 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 454 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 455 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 456 }; 457 458 static const u32 iceland_mgcg_cgcg_init[] = 459 { 460 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 461 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 462 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 463 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 464 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, 465 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, 466 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, 467 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 468 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 469 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 470 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 471 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 472 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 473 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 474 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 475 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 476 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 477 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 478 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 479 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 480 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 481 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 482 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, 483 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 484 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 485 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 486 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 487 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 488 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 489 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 490 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 491 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 492 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 493 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 494 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 495 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 496 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 497 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 498 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 499 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 500 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 501 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 502 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 503 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 504 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 505 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 506 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 507 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 508 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 509 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 510 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 511 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 512 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 513 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 514 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 515 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 516 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 517 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 518 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 519 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 520 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 521 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 522 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 523 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 524 }; 525 526 static const u32 cz_golden_settings_a11[] = 527 { 528 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 529 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 530 mmGB_GPU_ID, 0x0000000f, 0x00000000, 531 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, 532 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 533 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c, 534 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 535 mmTA_CNTL_AUX, 0x000f000f, 0x00010000, 536 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 537 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 538 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, 539 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 540 }; 541 542 static const u32 cz_golden_common_all[] = 543 { 544 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 545 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 546 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 547 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 548 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 549 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 550 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 551 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF 552 }; 553 554 static const u32 cz_mgcg_cgcg_init[] = 555 { 556 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 557 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 558 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 559 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 560 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 561 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 562 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, 563 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 564 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 565 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 566 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 567 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 568 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 569 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 570 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 571 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 572 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 573 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 574 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 575 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 576 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 577 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 578 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 579 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 580 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 581 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 582 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 583 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 584 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 585 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 586 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 587 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 588 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 589 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 590 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 591 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 592 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 593 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 594 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 595 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 596 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 597 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 598 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 599 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 600 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 601 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 602 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 603 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 604 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 605 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 606 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 607 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 608 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 609 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 610 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 611 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 612 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 613 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 614 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 615 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 616 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 617 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 618 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 619 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 620 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 621 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 622 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 623 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 624 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 625 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 626 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 627 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 628 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 629 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 630 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 631 }; 632 633 static const u32 stoney_golden_settings_a11[] = 634 { 635 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 636 mmGB_GPU_ID, 0x0000000f, 0x00000000, 637 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 638 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 639 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, 640 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 641 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 642 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 643 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, 644 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, 645 }; 646 647 static const u32 stoney_golden_common_all[] = 648 { 649 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 650 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, 651 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 652 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, 653 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 654 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 655 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF, 656 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF, 657 }; 658 659 static const u32 stoney_mgcg_cgcg_init[] = 660 { 661 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 662 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 663 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 664 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, 665 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 666 }; 667 668 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); 669 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); 670 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); 671 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); 672 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); 673 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); 674 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring); 675 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring); 676 677 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) 678 { 679 switch (adev->asic_type) { 680 case CHIP_TOPAZ: 681 amdgpu_program_register_sequence(adev, 682 iceland_mgcg_cgcg_init, 683 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 684 amdgpu_program_register_sequence(adev, 685 golden_settings_iceland_a11, 686 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 687 amdgpu_program_register_sequence(adev, 688 iceland_golden_common_all, 689 (const u32)ARRAY_SIZE(iceland_golden_common_all)); 690 break; 691 case CHIP_FIJI: 692 amdgpu_program_register_sequence(adev, 693 fiji_mgcg_cgcg_init, 694 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 695 amdgpu_program_register_sequence(adev, 696 golden_settings_fiji_a10, 697 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 698 amdgpu_program_register_sequence(adev, 699 fiji_golden_common_all, 700 (const u32)ARRAY_SIZE(fiji_golden_common_all)); 701 break; 702 703 case CHIP_TONGA: 704 amdgpu_program_register_sequence(adev, 705 tonga_mgcg_cgcg_init, 706 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 707 amdgpu_program_register_sequence(adev, 708 golden_settings_tonga_a11, 709 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 710 amdgpu_program_register_sequence(adev, 711 tonga_golden_common_all, 712 (const u32)ARRAY_SIZE(tonga_golden_common_all)); 713 break; 714 case CHIP_POLARIS11: 715 case CHIP_POLARIS12: 716 amdgpu_program_register_sequence(adev, 717 golden_settings_polaris11_a11, 718 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 719 amdgpu_program_register_sequence(adev, 720 polaris11_golden_common_all, 721 (const u32)ARRAY_SIZE(polaris11_golden_common_all)); 722 break; 723 case CHIP_POLARIS10: 724 amdgpu_program_register_sequence(adev, 725 golden_settings_polaris10_a11, 726 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 727 amdgpu_program_register_sequence(adev, 728 polaris10_golden_common_all, 729 (const u32)ARRAY_SIZE(polaris10_golden_common_all)); 730 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); 731 if (adev->pdev->revision == 0xc7 && 732 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || 733 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || 734 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) { 735 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); 736 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); 737 } 738 break; 739 case CHIP_CARRIZO: 740 amdgpu_program_register_sequence(adev, 741 cz_mgcg_cgcg_init, 742 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 743 amdgpu_program_register_sequence(adev, 744 cz_golden_settings_a11, 745 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 746 amdgpu_program_register_sequence(adev, 747 cz_golden_common_all, 748 (const u32)ARRAY_SIZE(cz_golden_common_all)); 749 break; 750 case CHIP_STONEY: 751 amdgpu_program_register_sequence(adev, 752 stoney_mgcg_cgcg_init, 753 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 754 amdgpu_program_register_sequence(adev, 755 stoney_golden_settings_a11, 756 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 757 amdgpu_program_register_sequence(adev, 758 stoney_golden_common_all, 759 (const u32)ARRAY_SIZE(stoney_golden_common_all)); 760 break; 761 default: 762 break; 763 } 764 } 765 766 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) 767 { 768 adev->gfx.scratch.num_reg = 8; 769 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 770 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 771 } 772 773 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) 774 { 775 struct amdgpu_device *adev = ring->adev; 776 uint32_t scratch; 777 uint32_t tmp = 0; 778 unsigned i; 779 int r; 780 781 r = amdgpu_gfx_scratch_get(adev, &scratch); 782 if (r) { 783 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 784 return r; 785 } 786 WREG32(scratch, 0xCAFEDEAD); 787 r = amdgpu_ring_alloc(ring, 3); 788 if (r) { 789 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 790 ring->idx, r); 791 amdgpu_gfx_scratch_free(adev, scratch); 792 return r; 793 } 794 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 795 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 796 amdgpu_ring_write(ring, 0xDEADBEEF); 797 amdgpu_ring_commit(ring); 798 799 for (i = 0; i < adev->usec_timeout; i++) { 800 tmp = RREG32(scratch); 801 if (tmp == 0xDEADBEEF) 802 break; 803 DRM_UDELAY(1); 804 } 805 if (i < adev->usec_timeout) { 806 DRM_INFO("ring test on %d succeeded in %d usecs\n", 807 ring->idx, i); 808 } else { 809 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 810 ring->idx, scratch, tmp); 811 r = -EINVAL; 812 } 813 amdgpu_gfx_scratch_free(adev, scratch); 814 return r; 815 } 816 817 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 818 { 819 struct amdgpu_device *adev = ring->adev; 820 struct amdgpu_ib ib; 821 struct dma_fence *f = NULL; 822 uint32_t scratch; 823 uint32_t tmp = 0; 824 long r; 825 826 r = amdgpu_gfx_scratch_get(adev, &scratch); 827 if (r) { 828 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 829 return r; 830 } 831 WREG32(scratch, 0xCAFEDEAD); 832 memset(&ib, 0, sizeof(ib)); 833 r = amdgpu_ib_get(adev, NULL, 256, &ib); 834 if (r) { 835 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 836 goto err1; 837 } 838 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 839 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 840 ib.ptr[2] = 0xDEADBEEF; 841 ib.length_dw = 3; 842 843 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 844 if (r) 845 goto err2; 846 847 r = dma_fence_wait_timeout(f, false, timeout); 848 if (r == 0) { 849 DRM_ERROR("amdgpu: IB test timed out.\n"); 850 r = -ETIMEDOUT; 851 goto err2; 852 } else if (r < 0) { 853 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 854 goto err2; 855 } 856 tmp = RREG32(scratch); 857 if (tmp == 0xDEADBEEF) { 858 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 859 r = 0; 860 } else { 861 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 862 scratch, tmp); 863 r = -EINVAL; 864 } 865 err2: 866 amdgpu_ib_free(adev, &ib, NULL); 867 dma_fence_put(f); 868 err1: 869 amdgpu_gfx_scratch_free(adev, scratch); 870 return r; 871 } 872 873 874 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) 875 { 876 release_firmware(adev->gfx.pfp_fw); 877 adev->gfx.pfp_fw = NULL; 878 release_firmware(adev->gfx.me_fw); 879 adev->gfx.me_fw = NULL; 880 release_firmware(adev->gfx.ce_fw); 881 adev->gfx.ce_fw = NULL; 882 release_firmware(adev->gfx.rlc_fw); 883 adev->gfx.rlc_fw = NULL; 884 release_firmware(adev->gfx.mec_fw); 885 adev->gfx.mec_fw = NULL; 886 if ((adev->asic_type != CHIP_STONEY) && 887 (adev->asic_type != CHIP_TOPAZ)) 888 release_firmware(adev->gfx.mec2_fw); 889 adev->gfx.mec2_fw = NULL; 890 891 kfree(adev->gfx.rlc.register_list_format); 892 } 893 894 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 895 { 896 const char *chip_name; 897 char fw_name[30]; 898 int err; 899 struct amdgpu_firmware_info *info = NULL; 900 const struct common_firmware_header *header = NULL; 901 const struct gfx_firmware_header_v1_0 *cp_hdr; 902 const struct rlc_firmware_header_v2_0 *rlc_hdr; 903 unsigned int *tmp = NULL, i; 904 905 DRM_DEBUG("\n"); 906 907 switch (adev->asic_type) { 908 case CHIP_TOPAZ: 909 chip_name = "topaz"; 910 break; 911 case CHIP_TONGA: 912 chip_name = "tonga"; 913 break; 914 case CHIP_CARRIZO: 915 chip_name = "carrizo"; 916 break; 917 case CHIP_FIJI: 918 chip_name = "fiji"; 919 break; 920 case CHIP_POLARIS11: 921 chip_name = "polaris11"; 922 break; 923 case CHIP_POLARIS10: 924 chip_name = "polaris10"; 925 break; 926 case CHIP_POLARIS12: 927 chip_name = "polaris12"; 928 break; 929 case CHIP_STONEY: 930 chip_name = "stoney"; 931 break; 932 default: 933 BUG(); 934 } 935 936 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name); 938 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 939 if (err == -ENOENT) { 940 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 941 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 942 } 943 } else { 944 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 945 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 946 } 947 if (err) 948 goto out; 949 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 950 if (err) 951 goto out; 952 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 953 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 954 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 955 956 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 957 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name); 958 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 959 if (err == -ENOENT) { 960 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 961 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 962 } 963 } else { 964 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 965 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 966 } 967 if (err) 968 goto out; 969 err = amdgpu_ucode_validate(adev->gfx.me_fw); 970 if (err) 971 goto out; 972 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 973 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 974 975 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 976 977 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 978 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name); 979 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 980 if (err == -ENOENT) { 981 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 982 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 983 } 984 } else { 985 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 986 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 987 } 988 if (err) 989 goto out; 990 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 991 if (err) 992 goto out; 993 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 994 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 995 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 996 997 /* 998 * Support for MCBP/Virtualization in combination with chained IBs is 999 * formal released on feature version #46 1000 */ 1001 if (adev->gfx.ce_feature_version >= 46 && 1002 adev->gfx.pfp_feature_version >= 46) { 1003 adev->virt.chained_ib_support = true; 1004 DRM_INFO("Chained IB support enabled!\n"); 1005 } else 1006 adev->virt.chained_ib_support = false; 1007 1008 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1009 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1010 if (err) 1011 goto out; 1012 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1013 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1014 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 1015 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 1016 1017 adev->gfx.rlc.save_and_restore_offset = 1018 le32_to_cpu(rlc_hdr->save_and_restore_offset); 1019 adev->gfx.rlc.clear_state_descriptor_offset = 1020 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 1021 adev->gfx.rlc.avail_scratch_ram_locations = 1022 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 1023 adev->gfx.rlc.reg_restore_list_size = 1024 le32_to_cpu(rlc_hdr->reg_restore_list_size); 1025 adev->gfx.rlc.reg_list_format_start = 1026 le32_to_cpu(rlc_hdr->reg_list_format_start); 1027 adev->gfx.rlc.reg_list_format_separate_start = 1028 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 1029 adev->gfx.rlc.starting_offsets_start = 1030 le32_to_cpu(rlc_hdr->starting_offsets_start); 1031 adev->gfx.rlc.reg_list_format_size_bytes = 1032 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 1033 adev->gfx.rlc.reg_list_size_bytes = 1034 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 1035 1036 adev->gfx.rlc.register_list_format = 1037 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 1038 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 1039 1040 if (!adev->gfx.rlc.register_list_format) { 1041 err = -ENOMEM; 1042 goto out; 1043 } 1044 1045 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1046 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 1047 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 1048 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 1049 1050 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 1051 1052 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1053 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 1054 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 1055 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 1056 1057 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1058 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name); 1059 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1060 if (err == -ENOENT) { 1061 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1062 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1063 } 1064 } else { 1065 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1066 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1067 } 1068 if (err) 1069 goto out; 1070 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1071 if (err) 1072 goto out; 1073 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1074 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1075 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1076 1077 if ((adev->asic_type != CHIP_STONEY) && 1078 (adev->asic_type != CHIP_TOPAZ)) { 1079 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { 1080 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name); 1081 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1082 if (err == -ENOENT) { 1083 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1084 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1085 } 1086 } else { 1087 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1088 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1089 } 1090 if (!err) { 1091 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1092 if (err) 1093 goto out; 1094 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1095 adev->gfx.mec2_fw->data; 1096 adev->gfx.mec2_fw_version = 1097 le32_to_cpu(cp_hdr->header.ucode_version); 1098 adev->gfx.mec2_feature_version = 1099 le32_to_cpu(cp_hdr->ucode_feature_version); 1100 } else { 1101 err = 0; 1102 adev->gfx.mec2_fw = NULL; 1103 } 1104 } 1105 1106 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 1107 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 1108 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 1109 info->fw = adev->gfx.pfp_fw; 1110 header = (const struct common_firmware_header *)info->fw->data; 1111 adev->firmware.fw_size += 1112 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1113 1114 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 1115 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 1116 info->fw = adev->gfx.me_fw; 1117 header = (const struct common_firmware_header *)info->fw->data; 1118 adev->firmware.fw_size += 1119 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1120 1121 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 1122 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 1123 info->fw = adev->gfx.ce_fw; 1124 header = (const struct common_firmware_header *)info->fw->data; 1125 adev->firmware.fw_size += 1126 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1127 1128 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 1129 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 1130 info->fw = adev->gfx.rlc_fw; 1131 header = (const struct common_firmware_header *)info->fw->data; 1132 adev->firmware.fw_size += 1133 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1134 1135 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 1136 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 1137 info->fw = adev->gfx.mec_fw; 1138 header = (const struct common_firmware_header *)info->fw->data; 1139 adev->firmware.fw_size += 1140 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1141 1142 /* we need account JT in */ 1143 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1144 adev->firmware.fw_size += 1145 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 1146 1147 if (amdgpu_sriov_vf(adev)) { 1148 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE]; 1149 info->ucode_id = AMDGPU_UCODE_ID_STORAGE; 1150 info->fw = adev->gfx.mec_fw; 1151 adev->firmware.fw_size += 1152 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE); 1153 } 1154 1155 if (adev->gfx.mec2_fw) { 1156 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 1157 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 1158 info->fw = adev->gfx.mec2_fw; 1159 header = (const struct common_firmware_header *)info->fw->data; 1160 adev->firmware.fw_size += 1161 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1162 } 1163 1164 } 1165 1166 out: 1167 if (err) { 1168 dev_err(adev->dev, 1169 "gfx8: Failed to load firmware \"%s\"\n", 1170 fw_name); 1171 release_firmware(adev->gfx.pfp_fw); 1172 adev->gfx.pfp_fw = NULL; 1173 release_firmware(adev->gfx.me_fw); 1174 adev->gfx.me_fw = NULL; 1175 release_firmware(adev->gfx.ce_fw); 1176 adev->gfx.ce_fw = NULL; 1177 release_firmware(adev->gfx.rlc_fw); 1178 adev->gfx.rlc_fw = NULL; 1179 release_firmware(adev->gfx.mec_fw); 1180 adev->gfx.mec_fw = NULL; 1181 release_firmware(adev->gfx.mec2_fw); 1182 adev->gfx.mec2_fw = NULL; 1183 } 1184 return err; 1185 } 1186 1187 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, 1188 volatile u32 *buffer) 1189 { 1190 u32 count = 0, i; 1191 const struct cs_section_def *sect = NULL; 1192 const struct cs_extent_def *ext = NULL; 1193 1194 if (adev->gfx.rlc.cs_data == NULL) 1195 return; 1196 if (buffer == NULL) 1197 return; 1198 1199 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1200 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1201 1202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1203 buffer[count++] = cpu_to_le32(0x80000000); 1204 buffer[count++] = cpu_to_le32(0x80000000); 1205 1206 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1207 for (ext = sect->section; ext->extent != NULL; ++ext) { 1208 if (sect->id == SECT_CONTEXT) { 1209 buffer[count++] = 1210 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1211 buffer[count++] = cpu_to_le32(ext->reg_index - 1212 PACKET3_SET_CONTEXT_REG_START); 1213 for (i = 0; i < ext->reg_count; i++) 1214 buffer[count++] = cpu_to_le32(ext->extent[i]); 1215 } else { 1216 return; 1217 } 1218 } 1219 } 1220 1221 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1222 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - 1223 PACKET3_SET_CONTEXT_REG_START); 1224 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 1225 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); 1226 1227 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1228 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1229 1230 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1231 buffer[count++] = cpu_to_le32(0); 1232 } 1233 1234 static void cz_init_cp_jump_table(struct amdgpu_device *adev) 1235 { 1236 const __le32 *fw_data; 1237 volatile u32 *dst_ptr; 1238 int me, i, max_me = 4; 1239 u32 bo_offset = 0; 1240 u32 table_offset, table_size; 1241 1242 if (adev->asic_type == CHIP_CARRIZO) 1243 max_me = 5; 1244 1245 /* write the cp table buffer */ 1246 dst_ptr = adev->gfx.rlc.cp_table_ptr; 1247 for (me = 0; me < max_me; me++) { 1248 if (me == 0) { 1249 const struct gfx_firmware_header_v1_0 *hdr = 1250 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1251 fw_data = (const __le32 *) 1252 (adev->gfx.ce_fw->data + 1253 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1254 table_offset = le32_to_cpu(hdr->jt_offset); 1255 table_size = le32_to_cpu(hdr->jt_size); 1256 } else if (me == 1) { 1257 const struct gfx_firmware_header_v1_0 *hdr = 1258 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1259 fw_data = (const __le32 *) 1260 (adev->gfx.pfp_fw->data + 1261 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1262 table_offset = le32_to_cpu(hdr->jt_offset); 1263 table_size = le32_to_cpu(hdr->jt_size); 1264 } else if (me == 2) { 1265 const struct gfx_firmware_header_v1_0 *hdr = 1266 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1267 fw_data = (const __le32 *) 1268 (adev->gfx.me_fw->data + 1269 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1270 table_offset = le32_to_cpu(hdr->jt_offset); 1271 table_size = le32_to_cpu(hdr->jt_size); 1272 } else if (me == 3) { 1273 const struct gfx_firmware_header_v1_0 *hdr = 1274 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1275 fw_data = (const __le32 *) 1276 (adev->gfx.mec_fw->data + 1277 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1278 table_offset = le32_to_cpu(hdr->jt_offset); 1279 table_size = le32_to_cpu(hdr->jt_size); 1280 } else if (me == 4) { 1281 const struct gfx_firmware_header_v1_0 *hdr = 1282 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 1283 fw_data = (const __le32 *) 1284 (adev->gfx.mec2_fw->data + 1285 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1286 table_offset = le32_to_cpu(hdr->jt_offset); 1287 table_size = le32_to_cpu(hdr->jt_size); 1288 } 1289 1290 for (i = 0; i < table_size; i ++) { 1291 dst_ptr[bo_offset + i] = 1292 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 1293 } 1294 1295 bo_offset += table_size; 1296 } 1297 } 1298 1299 static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev) 1300 { 1301 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); 1302 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); 1303 } 1304 1305 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) 1306 { 1307 volatile u32 *dst_ptr; 1308 u32 dws; 1309 const struct cs_section_def *cs_data; 1310 int r; 1311 1312 adev->gfx.rlc.cs_data = vi_cs_data; 1313 1314 cs_data = adev->gfx.rlc.cs_data; 1315 1316 if (cs_data) { 1317 /* clear state block */ 1318 adev->gfx.rlc.clear_state_size = dws = gfx_v8_0_get_csb_size(adev); 1319 1320 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 1321 AMDGPU_GEM_DOMAIN_VRAM, 1322 &adev->gfx.rlc.clear_state_obj, 1323 &adev->gfx.rlc.clear_state_gpu_addr, 1324 (void **)&adev->gfx.rlc.cs_ptr); 1325 if (r) { 1326 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 1327 gfx_v8_0_rlc_fini(adev); 1328 return r; 1329 } 1330 1331 /* set up the cs buffer */ 1332 dst_ptr = adev->gfx.rlc.cs_ptr; 1333 gfx_v8_0_get_csb_buffer(adev, dst_ptr); 1334 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 1335 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1336 } 1337 1338 if ((adev->asic_type == CHIP_CARRIZO) || 1339 (adev->asic_type == CHIP_STONEY)) { 1340 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1341 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, 1342 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1343 &adev->gfx.rlc.cp_table_obj, 1344 &adev->gfx.rlc.cp_table_gpu_addr, 1345 (void **)&adev->gfx.rlc.cp_table_ptr); 1346 if (r) { 1347 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 1348 return r; 1349 } 1350 1351 cz_init_cp_jump_table(adev); 1352 1353 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 1354 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 1355 } 1356 1357 return 0; 1358 } 1359 1360 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) 1361 { 1362 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1363 } 1364 1365 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 1366 { 1367 int r; 1368 u32 *hpd; 1369 size_t mec_hpd_size; 1370 1371 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1372 1373 /* take ownership of the relevant compute queues */ 1374 amdgpu_gfx_compute_queue_acquire(adev); 1375 1376 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; 1377 1378 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1379 AMDGPU_GEM_DOMAIN_GTT, 1380 &adev->gfx.mec.hpd_eop_obj, 1381 &adev->gfx.mec.hpd_eop_gpu_addr, 1382 (void **)&hpd); 1383 if (r) { 1384 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1385 return r; 1386 } 1387 1388 memset(hpd, 0, mec_hpd_size); 1389 1390 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1391 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1392 1393 return 0; 1394 } 1395 1396 static const u32 vgpr_init_compute_shader[] = 1397 { 1398 0x7e000209, 0x7e020208, 1399 0x7e040207, 0x7e060206, 1400 0x7e080205, 0x7e0a0204, 1401 0x7e0c0203, 0x7e0e0202, 1402 0x7e100201, 0x7e120200, 1403 0x7e140209, 0x7e160208, 1404 0x7e180207, 0x7e1a0206, 1405 0x7e1c0205, 0x7e1e0204, 1406 0x7e200203, 0x7e220202, 1407 0x7e240201, 0x7e260200, 1408 0x7e280209, 0x7e2a0208, 1409 0x7e2c0207, 0x7e2e0206, 1410 0x7e300205, 0x7e320204, 1411 0x7e340203, 0x7e360202, 1412 0x7e380201, 0x7e3a0200, 1413 0x7e3c0209, 0x7e3e0208, 1414 0x7e400207, 0x7e420206, 1415 0x7e440205, 0x7e460204, 1416 0x7e480203, 0x7e4a0202, 1417 0x7e4c0201, 0x7e4e0200, 1418 0x7e500209, 0x7e520208, 1419 0x7e540207, 0x7e560206, 1420 0x7e580205, 0x7e5a0204, 1421 0x7e5c0203, 0x7e5e0202, 1422 0x7e600201, 0x7e620200, 1423 0x7e640209, 0x7e660208, 1424 0x7e680207, 0x7e6a0206, 1425 0x7e6c0205, 0x7e6e0204, 1426 0x7e700203, 0x7e720202, 1427 0x7e740201, 0x7e760200, 1428 0x7e780209, 0x7e7a0208, 1429 0x7e7c0207, 0x7e7e0206, 1430 0xbf8a0000, 0xbf810000, 1431 }; 1432 1433 static const u32 sgpr_init_compute_shader[] = 1434 { 1435 0xbe8a0100, 0xbe8c0102, 1436 0xbe8e0104, 0xbe900106, 1437 0xbe920108, 0xbe940100, 1438 0xbe960102, 0xbe980104, 1439 0xbe9a0106, 0xbe9c0108, 1440 0xbe9e0100, 0xbea00102, 1441 0xbea20104, 0xbea40106, 1442 0xbea60108, 0xbea80100, 1443 0xbeaa0102, 0xbeac0104, 1444 0xbeae0106, 0xbeb00108, 1445 0xbeb20100, 0xbeb40102, 1446 0xbeb60104, 0xbeb80106, 1447 0xbeba0108, 0xbebc0100, 1448 0xbebe0102, 0xbec00104, 1449 0xbec20106, 0xbec40108, 1450 0xbec60100, 0xbec80102, 1451 0xbee60004, 0xbee70005, 1452 0xbeea0006, 0xbeeb0007, 1453 0xbee80008, 0xbee90009, 1454 0xbefc0000, 0xbf8a0000, 1455 0xbf810000, 0x00000000, 1456 }; 1457 1458 static const u32 vgpr_init_regs[] = 1459 { 1460 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, 1461 mmCOMPUTE_RESOURCE_LIMITS, 0, 1462 mmCOMPUTE_NUM_THREAD_X, 256*4, 1463 mmCOMPUTE_NUM_THREAD_Y, 1, 1464 mmCOMPUTE_NUM_THREAD_Z, 1, 1465 mmCOMPUTE_PGM_RSRC2, 20, 1466 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1467 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1468 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1469 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1470 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1471 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1472 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1473 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1474 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1475 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1476 }; 1477 1478 static const u32 sgpr1_init_regs[] = 1479 { 1480 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, 1481 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, 1482 mmCOMPUTE_NUM_THREAD_X, 256*5, 1483 mmCOMPUTE_NUM_THREAD_Y, 1, 1484 mmCOMPUTE_NUM_THREAD_Z, 1, 1485 mmCOMPUTE_PGM_RSRC2, 20, 1486 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1487 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1488 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1489 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1490 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1491 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1492 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1493 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1494 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1495 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1496 }; 1497 1498 static const u32 sgpr2_init_regs[] = 1499 { 1500 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0, 1501 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, 1502 mmCOMPUTE_NUM_THREAD_X, 256*5, 1503 mmCOMPUTE_NUM_THREAD_Y, 1, 1504 mmCOMPUTE_NUM_THREAD_Z, 1, 1505 mmCOMPUTE_PGM_RSRC2, 20, 1506 mmCOMPUTE_USER_DATA_0, 0xedcedc00, 1507 mmCOMPUTE_USER_DATA_1, 0xedcedc01, 1508 mmCOMPUTE_USER_DATA_2, 0xedcedc02, 1509 mmCOMPUTE_USER_DATA_3, 0xedcedc03, 1510 mmCOMPUTE_USER_DATA_4, 0xedcedc04, 1511 mmCOMPUTE_USER_DATA_5, 0xedcedc05, 1512 mmCOMPUTE_USER_DATA_6, 0xedcedc06, 1513 mmCOMPUTE_USER_DATA_7, 0xedcedc07, 1514 mmCOMPUTE_USER_DATA_8, 0xedcedc08, 1515 mmCOMPUTE_USER_DATA_9, 0xedcedc09, 1516 }; 1517 1518 static const u32 sec_ded_counter_registers[] = 1519 { 1520 mmCPC_EDC_ATC_CNT, 1521 mmCPC_EDC_SCRATCH_CNT, 1522 mmCPC_EDC_UCODE_CNT, 1523 mmCPF_EDC_ATC_CNT, 1524 mmCPF_EDC_ROQ_CNT, 1525 mmCPF_EDC_TAG_CNT, 1526 mmCPG_EDC_ATC_CNT, 1527 mmCPG_EDC_DMA_CNT, 1528 mmCPG_EDC_TAG_CNT, 1529 mmDC_EDC_CSINVOC_CNT, 1530 mmDC_EDC_RESTORE_CNT, 1531 mmDC_EDC_STATE_CNT, 1532 mmGDS_EDC_CNT, 1533 mmGDS_EDC_GRBM_CNT, 1534 mmGDS_EDC_OA_DED, 1535 mmSPI_EDC_CNT, 1536 mmSQC_ATC_EDC_GATCL1_CNT, 1537 mmSQC_EDC_CNT, 1538 mmSQ_EDC_DED_CNT, 1539 mmSQ_EDC_INFO, 1540 mmSQ_EDC_SEC_CNT, 1541 mmTCC_EDC_CNT, 1542 mmTCP_ATC_EDC_GATCL1_CNT, 1543 mmTCP_EDC_CNT, 1544 mmTD_EDC_CNT 1545 }; 1546 1547 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 1548 { 1549 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 1550 struct amdgpu_ib ib; 1551 struct dma_fence *f = NULL; 1552 int r, i; 1553 u32 tmp; 1554 unsigned total_size, vgpr_offset, sgpr_offset; 1555 u64 gpu_addr; 1556 1557 /* only supported on CZ */ 1558 if (adev->asic_type != CHIP_CARRIZO) 1559 return 0; 1560 1561 /* bail if the compute ring is not ready */ 1562 if (!ring->ready) 1563 return 0; 1564 1565 tmp = RREG32(mmGB_EDC_MODE); 1566 WREG32(mmGB_EDC_MODE, 0); 1567 1568 total_size = 1569 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1570 total_size += 1571 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1572 total_size += 1573 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4; 1574 total_size = ALIGN(total_size, 256); 1575 vgpr_offset = total_size; 1576 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256); 1577 sgpr_offset = total_size; 1578 total_size += sizeof(sgpr_init_compute_shader); 1579 1580 /* allocate an indirect buffer to put the commands in */ 1581 memset(&ib, 0, sizeof(ib)); 1582 r = amdgpu_ib_get(adev, NULL, total_size, &ib); 1583 if (r) { 1584 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 1585 return r; 1586 } 1587 1588 /* load the compute shaders */ 1589 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++) 1590 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; 1591 1592 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 1593 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 1594 1595 /* init the ib length to 0 */ 1596 ib.length_dw = 0; 1597 1598 /* VGPR */ 1599 /* write the register state for the compute dispatch */ 1600 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) { 1601 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1602 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START; 1603 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1]; 1604 } 1605 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1606 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 1607 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1608 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1609 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1610 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1611 1612 /* write dispatch packet */ 1613 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1614 ib.ptr[ib.length_dw++] = 8; /* x */ 1615 ib.ptr[ib.length_dw++] = 1; /* y */ 1616 ib.ptr[ib.length_dw++] = 1; /* z */ 1617 ib.ptr[ib.length_dw++] = 1618 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1619 1620 /* write CS partial flush packet */ 1621 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1622 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1623 1624 /* SGPR1 */ 1625 /* write the register state for the compute dispatch */ 1626 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) { 1627 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1628 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START; 1629 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1]; 1630 } 1631 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1632 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 1633 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1634 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1635 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1636 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1637 1638 /* write dispatch packet */ 1639 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1640 ib.ptr[ib.length_dw++] = 8; /* x */ 1641 ib.ptr[ib.length_dw++] = 1; /* y */ 1642 ib.ptr[ib.length_dw++] = 1; /* z */ 1643 ib.ptr[ib.length_dw++] = 1644 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1645 1646 /* write CS partial flush packet */ 1647 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1648 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1649 1650 /* SGPR2 */ 1651 /* write the register state for the compute dispatch */ 1652 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) { 1653 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 1654 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START; 1655 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1]; 1656 } 1657 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 1658 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 1659 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 1660 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; 1661 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 1662 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 1663 1664 /* write dispatch packet */ 1665 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 1666 ib.ptr[ib.length_dw++] = 8; /* x */ 1667 ib.ptr[ib.length_dw++] = 1; /* y */ 1668 ib.ptr[ib.length_dw++] = 1; /* z */ 1669 ib.ptr[ib.length_dw++] = 1670 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 1671 1672 /* write CS partial flush packet */ 1673 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 1674 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 1675 1676 /* shedule the ib on the ring */ 1677 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1678 if (r) { 1679 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 1680 goto fail; 1681 } 1682 1683 /* wait for the GPU to finish processing the IB */ 1684 r = dma_fence_wait(f, false); 1685 if (r) { 1686 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 1687 goto fail; 1688 } 1689 1690 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2); 1691 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1); 1692 WREG32(mmGB_EDC_MODE, tmp); 1693 1694 tmp = RREG32(mmCC_GC_EDC_CONFIG); 1695 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1; 1696 WREG32(mmCC_GC_EDC_CONFIG, tmp); 1697 1698 1699 /* read back registers to clear the counters */ 1700 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++) 1701 RREG32(sec_ded_counter_registers[i]); 1702 1703 fail: 1704 amdgpu_ib_free(adev, &ib, NULL); 1705 dma_fence_put(f); 1706 1707 return r; 1708 } 1709 1710 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) 1711 { 1712 u32 gb_addr_config; 1713 u32 mc_shared_chmap, mc_arb_ramcfg; 1714 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 1715 u32 tmp; 1716 int ret; 1717 1718 switch (adev->asic_type) { 1719 case CHIP_TOPAZ: 1720 adev->gfx.config.max_shader_engines = 1; 1721 adev->gfx.config.max_tile_pipes = 2; 1722 adev->gfx.config.max_cu_per_sh = 6; 1723 adev->gfx.config.max_sh_per_se = 1; 1724 adev->gfx.config.max_backends_per_se = 2; 1725 adev->gfx.config.max_texture_channel_caches = 2; 1726 adev->gfx.config.max_gprs = 256; 1727 adev->gfx.config.max_gs_threads = 32; 1728 adev->gfx.config.max_hw_contexts = 8; 1729 1730 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1731 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1732 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1733 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1734 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; 1735 break; 1736 case CHIP_FIJI: 1737 adev->gfx.config.max_shader_engines = 4; 1738 adev->gfx.config.max_tile_pipes = 16; 1739 adev->gfx.config.max_cu_per_sh = 16; 1740 adev->gfx.config.max_sh_per_se = 1; 1741 adev->gfx.config.max_backends_per_se = 4; 1742 adev->gfx.config.max_texture_channel_caches = 16; 1743 adev->gfx.config.max_gprs = 256; 1744 adev->gfx.config.max_gs_threads = 32; 1745 adev->gfx.config.max_hw_contexts = 8; 1746 1747 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1748 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1749 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1750 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1751 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1752 break; 1753 case CHIP_POLARIS11: 1754 case CHIP_POLARIS12: 1755 ret = amdgpu_atombios_get_gfx_info(adev); 1756 if (ret) 1757 return ret; 1758 adev->gfx.config.max_gprs = 256; 1759 adev->gfx.config.max_gs_threads = 32; 1760 adev->gfx.config.max_hw_contexts = 8; 1761 1762 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1763 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1764 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1765 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1766 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; 1767 break; 1768 case CHIP_POLARIS10: 1769 ret = amdgpu_atombios_get_gfx_info(adev); 1770 if (ret) 1771 return ret; 1772 adev->gfx.config.max_gprs = 256; 1773 adev->gfx.config.max_gs_threads = 32; 1774 adev->gfx.config.max_hw_contexts = 8; 1775 1776 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1777 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1778 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1779 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1780 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1781 break; 1782 case CHIP_TONGA: 1783 adev->gfx.config.max_shader_engines = 4; 1784 adev->gfx.config.max_tile_pipes = 8; 1785 adev->gfx.config.max_cu_per_sh = 8; 1786 adev->gfx.config.max_sh_per_se = 1; 1787 adev->gfx.config.max_backends_per_se = 2; 1788 adev->gfx.config.max_texture_channel_caches = 8; 1789 adev->gfx.config.max_gprs = 256; 1790 adev->gfx.config.max_gs_threads = 32; 1791 adev->gfx.config.max_hw_contexts = 8; 1792 1793 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1794 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1795 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1796 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1797 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1798 break; 1799 case CHIP_CARRIZO: 1800 adev->gfx.config.max_shader_engines = 1; 1801 adev->gfx.config.max_tile_pipes = 2; 1802 adev->gfx.config.max_sh_per_se = 1; 1803 adev->gfx.config.max_backends_per_se = 2; 1804 adev->gfx.config.max_cu_per_sh = 8; 1805 adev->gfx.config.max_texture_channel_caches = 2; 1806 adev->gfx.config.max_gprs = 256; 1807 adev->gfx.config.max_gs_threads = 32; 1808 adev->gfx.config.max_hw_contexts = 8; 1809 1810 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1811 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1812 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1813 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1814 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1815 break; 1816 case CHIP_STONEY: 1817 adev->gfx.config.max_shader_engines = 1; 1818 adev->gfx.config.max_tile_pipes = 2; 1819 adev->gfx.config.max_sh_per_se = 1; 1820 adev->gfx.config.max_backends_per_se = 1; 1821 adev->gfx.config.max_cu_per_sh = 3; 1822 adev->gfx.config.max_texture_channel_caches = 2; 1823 adev->gfx.config.max_gprs = 256; 1824 adev->gfx.config.max_gs_threads = 16; 1825 adev->gfx.config.max_hw_contexts = 8; 1826 1827 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1828 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1829 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1830 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1831 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 1832 break; 1833 default: 1834 adev->gfx.config.max_shader_engines = 2; 1835 adev->gfx.config.max_tile_pipes = 4; 1836 adev->gfx.config.max_cu_per_sh = 2; 1837 adev->gfx.config.max_sh_per_se = 1; 1838 adev->gfx.config.max_backends_per_se = 2; 1839 adev->gfx.config.max_texture_channel_caches = 4; 1840 adev->gfx.config.max_gprs = 256; 1841 adev->gfx.config.max_gs_threads = 32; 1842 adev->gfx.config.max_hw_contexts = 8; 1843 1844 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1845 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1846 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1847 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1848 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1849 break; 1850 } 1851 1852 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1853 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1854 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1855 1856 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1857 adev->gfx.config.mem_max_burst_length_bytes = 256; 1858 if (adev->flags & AMD_IS_APU) { 1859 /* Get memory bank mapping mode. */ 1860 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 1861 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1862 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1863 1864 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 1865 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 1866 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 1867 1868 /* Validate settings in case only one DIMM installed. */ 1869 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 1870 dimm00_addr_map = 0; 1871 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 1872 dimm01_addr_map = 0; 1873 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 1874 dimm10_addr_map = 0; 1875 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 1876 dimm11_addr_map = 0; 1877 1878 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 1879 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 1880 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 1881 adev->gfx.config.mem_row_size_in_kb = 2; 1882 else 1883 adev->gfx.config.mem_row_size_in_kb = 1; 1884 } else { 1885 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); 1886 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1887 if (adev->gfx.config.mem_row_size_in_kb > 4) 1888 adev->gfx.config.mem_row_size_in_kb = 4; 1889 } 1890 1891 adev->gfx.config.shader_engine_tile_size = 32; 1892 adev->gfx.config.num_gpus = 1; 1893 adev->gfx.config.multi_gpu_tile_size = 64; 1894 1895 /* fix up row size */ 1896 switch (adev->gfx.config.mem_row_size_in_kb) { 1897 case 1: 1898 default: 1899 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); 1900 break; 1901 case 2: 1902 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); 1903 break; 1904 case 4: 1905 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); 1906 break; 1907 } 1908 adev->gfx.config.gb_addr_config = gb_addr_config; 1909 1910 return 0; 1911 } 1912 1913 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1914 int mec, int pipe, int queue) 1915 { 1916 int r; 1917 unsigned irq_type; 1918 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1919 1920 ring = &adev->gfx.compute_ring[ring_id]; 1921 1922 /* mec0 is me1 */ 1923 ring->me = mec + 1; 1924 ring->pipe = pipe; 1925 ring->queue = queue; 1926 1927 ring->ring_obj = NULL; 1928 ring->use_doorbell = true; 1929 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; 1930 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1931 + (ring_id * GFX8_MEC_HPD_SIZE); 1932 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1933 1934 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1935 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1936 + ring->pipe; 1937 1938 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1939 r = amdgpu_ring_init(adev, ring, 1024, 1940 &adev->gfx.eop_irq, irq_type); 1941 if (r) 1942 return r; 1943 1944 1945 return 0; 1946 } 1947 1948 static int gfx_v8_0_sw_init(void *handle) 1949 { 1950 int i, j, k, r, ring_id; 1951 struct amdgpu_ring *ring; 1952 struct amdgpu_kiq *kiq; 1953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1954 1955 switch (adev->asic_type) { 1956 case CHIP_FIJI: 1957 case CHIP_TONGA: 1958 case CHIP_POLARIS11: 1959 case CHIP_POLARIS12: 1960 case CHIP_POLARIS10: 1961 case CHIP_CARRIZO: 1962 adev->gfx.mec.num_mec = 2; 1963 break; 1964 case CHIP_TOPAZ: 1965 case CHIP_STONEY: 1966 default: 1967 adev->gfx.mec.num_mec = 1; 1968 break; 1969 } 1970 1971 adev->gfx.mec.num_pipe_per_mec = 4; 1972 adev->gfx.mec.num_queue_per_pipe = 8; 1973 1974 /* KIQ event */ 1975 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq); 1976 if (r) 1977 return r; 1978 1979 /* EOP Event */ 1980 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 1981 if (r) 1982 return r; 1983 1984 /* Privileged reg */ 1985 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, 1986 &adev->gfx.priv_reg_irq); 1987 if (r) 1988 return r; 1989 1990 /* Privileged inst */ 1991 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, 1992 &adev->gfx.priv_inst_irq); 1993 if (r) 1994 return r; 1995 1996 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1997 1998 gfx_v8_0_scratch_init(adev); 1999 2000 r = gfx_v8_0_init_microcode(adev); 2001 if (r) { 2002 DRM_ERROR("Failed to load gfx firmware!\n"); 2003 return r; 2004 } 2005 2006 r = gfx_v8_0_rlc_init(adev); 2007 if (r) { 2008 DRM_ERROR("Failed to init rlc BOs!\n"); 2009 return r; 2010 } 2011 2012 r = gfx_v8_0_mec_init(adev); 2013 if (r) { 2014 DRM_ERROR("Failed to init MEC BOs!\n"); 2015 return r; 2016 } 2017 2018 /* set up the gfx ring */ 2019 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2020 ring = &adev->gfx.gfx_ring[i]; 2021 ring->ring_obj = NULL; 2022 sprintf(ring->name, "gfx"); 2023 /* no gfx doorbells on iceland */ 2024 if (adev->asic_type != CHIP_TOPAZ) { 2025 ring->use_doorbell = true; 2026 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; 2027 } 2028 2029 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2030 AMDGPU_CP_IRQ_GFX_EOP); 2031 if (r) 2032 return r; 2033 } 2034 2035 2036 /* set up the compute queues - allocate horizontally across pipes */ 2037 ring_id = 0; 2038 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2039 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2040 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2041 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2042 continue; 2043 2044 r = gfx_v8_0_compute_ring_init(adev, 2045 ring_id, 2046 i, k, j); 2047 if (r) 2048 return r; 2049 2050 ring_id++; 2051 } 2052 } 2053 } 2054 2055 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE); 2056 if (r) { 2057 DRM_ERROR("Failed to init KIQ BOs!\n"); 2058 return r; 2059 } 2060 2061 kiq = &adev->gfx.kiq; 2062 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2063 if (r) 2064 return r; 2065 2066 /* create MQD for all compute queues as well as KIQ for SRIOV case */ 2067 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation)); 2068 if (r) 2069 return r; 2070 2071 /* reserve GDS, GWS and OA resource for gfx */ 2072 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 2073 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 2074 &adev->gds.gds_gfx_bo, NULL, NULL); 2075 if (r) 2076 return r; 2077 2078 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 2079 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 2080 &adev->gds.gws_gfx_bo, NULL, NULL); 2081 if (r) 2082 return r; 2083 2084 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 2085 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 2086 &adev->gds.oa_gfx_bo, NULL, NULL); 2087 if (r) 2088 return r; 2089 2090 adev->gfx.ce_ram_size = 0x8000; 2091 2092 r = gfx_v8_0_gpu_early_init(adev); 2093 if (r) 2094 return r; 2095 2096 return 0; 2097 } 2098 2099 static int gfx_v8_0_sw_fini(void *handle) 2100 { 2101 int i; 2102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2103 2104 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 2105 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 2106 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 2107 2108 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2109 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2110 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2111 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2112 2113 amdgpu_gfx_compute_mqd_sw_fini(adev); 2114 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 2115 amdgpu_gfx_kiq_fini(adev); 2116 amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); 2117 2118 gfx_v8_0_mec_fini(adev); 2119 gfx_v8_0_rlc_fini(adev); 2120 gfx_v8_0_free_microcode(adev); 2121 2122 return 0; 2123 } 2124 2125 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) 2126 { 2127 uint32_t *modearray, *mod2array; 2128 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 2129 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 2130 u32 reg_offset; 2131 2132 modearray = adev->gfx.config.tile_mode_array; 2133 mod2array = adev->gfx.config.macrotile_mode_array; 2134 2135 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2136 modearray[reg_offset] = 0; 2137 2138 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2139 mod2array[reg_offset] = 0; 2140 2141 switch (adev->asic_type) { 2142 case CHIP_TOPAZ: 2143 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2144 PIPE_CONFIG(ADDR_SURF_P2) | 2145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2146 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2147 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2148 PIPE_CONFIG(ADDR_SURF_P2) | 2149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2150 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2151 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2152 PIPE_CONFIG(ADDR_SURF_P2) | 2153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2154 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2155 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2156 PIPE_CONFIG(ADDR_SURF_P2) | 2157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2159 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2160 PIPE_CONFIG(ADDR_SURF_P2) | 2161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2163 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2164 PIPE_CONFIG(ADDR_SURF_P2) | 2165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2167 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2168 PIPE_CONFIG(ADDR_SURF_P2) | 2169 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2171 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2172 PIPE_CONFIG(ADDR_SURF_P2)); 2173 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2174 PIPE_CONFIG(ADDR_SURF_P2) | 2175 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2176 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2177 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2178 PIPE_CONFIG(ADDR_SURF_P2) | 2179 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2181 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2182 PIPE_CONFIG(ADDR_SURF_P2) | 2183 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2185 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2186 PIPE_CONFIG(ADDR_SURF_P2) | 2187 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2189 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2190 PIPE_CONFIG(ADDR_SURF_P2) | 2191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2193 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2194 PIPE_CONFIG(ADDR_SURF_P2) | 2195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2197 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2198 PIPE_CONFIG(ADDR_SURF_P2) | 2199 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2201 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2202 PIPE_CONFIG(ADDR_SURF_P2) | 2203 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2205 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2206 PIPE_CONFIG(ADDR_SURF_P2) | 2207 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2209 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2210 PIPE_CONFIG(ADDR_SURF_P2) | 2211 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2213 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2214 PIPE_CONFIG(ADDR_SURF_P2) | 2215 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2217 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2218 PIPE_CONFIG(ADDR_SURF_P2) | 2219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2221 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2222 PIPE_CONFIG(ADDR_SURF_P2) | 2223 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2225 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2226 PIPE_CONFIG(ADDR_SURF_P2) | 2227 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2229 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2230 PIPE_CONFIG(ADDR_SURF_P2) | 2231 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2233 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2234 PIPE_CONFIG(ADDR_SURF_P2) | 2235 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2237 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2238 PIPE_CONFIG(ADDR_SURF_P2) | 2239 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2240 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2241 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2242 PIPE_CONFIG(ADDR_SURF_P2) | 2243 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2245 2246 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2249 NUM_BANKS(ADDR_SURF_8_BANK)); 2250 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2253 NUM_BANKS(ADDR_SURF_8_BANK)); 2254 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2257 NUM_BANKS(ADDR_SURF_8_BANK)); 2258 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2261 NUM_BANKS(ADDR_SURF_8_BANK)); 2262 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2265 NUM_BANKS(ADDR_SURF_8_BANK)); 2266 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2269 NUM_BANKS(ADDR_SURF_8_BANK)); 2270 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2273 NUM_BANKS(ADDR_SURF_8_BANK)); 2274 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2277 NUM_BANKS(ADDR_SURF_16_BANK)); 2278 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 2279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2281 NUM_BANKS(ADDR_SURF_16_BANK)); 2282 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2285 NUM_BANKS(ADDR_SURF_16_BANK)); 2286 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2289 NUM_BANKS(ADDR_SURF_16_BANK)); 2290 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2293 NUM_BANKS(ADDR_SURF_16_BANK)); 2294 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2297 NUM_BANKS(ADDR_SURF_16_BANK)); 2298 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2301 NUM_BANKS(ADDR_SURF_8_BANK)); 2302 2303 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2304 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 2305 reg_offset != 23) 2306 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2307 2308 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2309 if (reg_offset != 7) 2310 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2311 2312 break; 2313 case CHIP_FIJI: 2314 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2317 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2318 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2322 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2325 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2326 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2330 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2334 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2335 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2338 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2340 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2341 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2342 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2343 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2345 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2346 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2347 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 2348 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2349 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2350 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2352 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2353 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2354 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2356 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2358 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2360 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2361 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2362 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2364 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2366 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2368 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2372 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2373 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2376 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2380 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2381 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2384 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2388 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2392 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2396 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2397 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2400 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2404 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2405 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2408 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2409 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2412 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2414 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2416 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2418 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2420 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2422 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2424 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2425 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2426 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2428 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2429 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 2430 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2431 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2432 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2433 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2434 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2436 2437 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2440 NUM_BANKS(ADDR_SURF_8_BANK)); 2441 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2444 NUM_BANKS(ADDR_SURF_8_BANK)); 2445 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2448 NUM_BANKS(ADDR_SURF_8_BANK)); 2449 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2452 NUM_BANKS(ADDR_SURF_8_BANK)); 2453 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2456 NUM_BANKS(ADDR_SURF_8_BANK)); 2457 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2460 NUM_BANKS(ADDR_SURF_8_BANK)); 2461 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2464 NUM_BANKS(ADDR_SURF_8_BANK)); 2465 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2468 NUM_BANKS(ADDR_SURF_8_BANK)); 2469 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2472 NUM_BANKS(ADDR_SURF_8_BANK)); 2473 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2476 NUM_BANKS(ADDR_SURF_8_BANK)); 2477 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2480 NUM_BANKS(ADDR_SURF_8_BANK)); 2481 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2484 NUM_BANKS(ADDR_SURF_8_BANK)); 2485 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2488 NUM_BANKS(ADDR_SURF_8_BANK)); 2489 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2492 NUM_BANKS(ADDR_SURF_4_BANK)); 2493 2494 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2495 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2496 2497 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2498 if (reg_offset != 7) 2499 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2500 2501 break; 2502 case CHIP_TONGA: 2503 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2506 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2507 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2511 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2515 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2519 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2523 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2527 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2529 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2530 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2531 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2532 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2535 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2536 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 2537 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2539 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2540 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2541 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2542 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2543 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2545 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2547 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2549 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2550 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2551 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2553 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2555 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2557 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2561 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2562 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2565 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2569 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2570 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2573 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2577 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2581 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2585 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2586 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2589 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2593 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2594 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2597 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2601 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2603 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2605 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2606 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2607 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2609 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2611 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2613 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2614 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2615 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2617 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2618 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2619 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2620 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2621 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2622 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2623 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2624 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2625 2626 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2629 NUM_BANKS(ADDR_SURF_16_BANK)); 2630 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2633 NUM_BANKS(ADDR_SURF_16_BANK)); 2634 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2637 NUM_BANKS(ADDR_SURF_16_BANK)); 2638 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2641 NUM_BANKS(ADDR_SURF_16_BANK)); 2642 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2645 NUM_BANKS(ADDR_SURF_16_BANK)); 2646 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2649 NUM_BANKS(ADDR_SURF_16_BANK)); 2650 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2653 NUM_BANKS(ADDR_SURF_16_BANK)); 2654 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2657 NUM_BANKS(ADDR_SURF_16_BANK)); 2658 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2661 NUM_BANKS(ADDR_SURF_16_BANK)); 2662 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2665 NUM_BANKS(ADDR_SURF_16_BANK)); 2666 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2669 NUM_BANKS(ADDR_SURF_16_BANK)); 2670 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2673 NUM_BANKS(ADDR_SURF_8_BANK)); 2674 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2677 NUM_BANKS(ADDR_SURF_4_BANK)); 2678 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2681 NUM_BANKS(ADDR_SURF_4_BANK)); 2682 2683 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2684 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2685 2686 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2687 if (reg_offset != 7) 2688 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2689 2690 break; 2691 case CHIP_POLARIS11: 2692 case CHIP_POLARIS12: 2693 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2696 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2697 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2699 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2700 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2701 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2704 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2705 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2708 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2709 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2712 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2713 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2716 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2717 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2718 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2720 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2721 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2722 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2724 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2725 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2726 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 2727 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2728 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2729 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2731 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2732 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2733 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2734 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2735 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2736 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2737 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2738 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2739 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2740 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2741 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2743 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2744 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2745 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2747 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2748 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2749 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2751 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2752 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2753 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2755 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2756 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2757 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2759 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2760 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2761 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2762 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2763 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2764 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2765 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2767 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2768 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2769 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2771 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2772 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2773 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2774 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2775 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2776 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2777 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2779 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2780 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2781 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2783 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2784 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2785 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2787 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2788 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2789 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2791 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2792 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2793 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2794 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2795 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2796 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2797 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2798 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2799 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2800 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2801 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2803 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2805 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2807 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2808 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2809 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2810 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2811 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2812 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2813 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 2814 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2815 2816 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2819 NUM_BANKS(ADDR_SURF_16_BANK)); 2820 2821 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2824 NUM_BANKS(ADDR_SURF_16_BANK)); 2825 2826 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2827 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2828 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2829 NUM_BANKS(ADDR_SURF_16_BANK)); 2830 2831 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2834 NUM_BANKS(ADDR_SURF_16_BANK)); 2835 2836 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2837 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2838 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2839 NUM_BANKS(ADDR_SURF_16_BANK)); 2840 2841 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2844 NUM_BANKS(ADDR_SURF_16_BANK)); 2845 2846 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2847 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2848 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2849 NUM_BANKS(ADDR_SURF_16_BANK)); 2850 2851 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2852 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 2853 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2854 NUM_BANKS(ADDR_SURF_16_BANK)); 2855 2856 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 2857 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2858 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2859 NUM_BANKS(ADDR_SURF_16_BANK)); 2860 2861 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 2863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2864 NUM_BANKS(ADDR_SURF_16_BANK)); 2865 2866 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2867 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 2868 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 2869 NUM_BANKS(ADDR_SURF_16_BANK)); 2870 2871 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2872 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2873 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2874 NUM_BANKS(ADDR_SURF_16_BANK)); 2875 2876 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2877 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2878 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 2879 NUM_BANKS(ADDR_SURF_8_BANK)); 2880 2881 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 2882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 2883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 2884 NUM_BANKS(ADDR_SURF_4_BANK)); 2885 2886 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2887 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 2888 2889 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 2890 if (reg_offset != 7) 2891 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 2892 2893 break; 2894 case CHIP_POLARIS10: 2895 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 2898 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2899 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2900 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 2902 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2903 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2905 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 2906 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2907 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2908 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 2910 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2911 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2914 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2915 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2916 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2918 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2919 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2922 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2923 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2924 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2925 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 2926 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 2927 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 2928 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 2929 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2930 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2931 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2932 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2933 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2934 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2935 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2936 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2937 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2938 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2939 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2940 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2941 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2942 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2943 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 2944 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2945 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 2946 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2947 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2948 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2949 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 2950 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2951 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2952 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2953 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 2954 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2955 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 2957 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2959 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2961 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 2962 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2963 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2964 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 2965 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2966 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2968 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2969 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 2970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2973 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2974 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2975 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2976 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2977 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 2978 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2979 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2980 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2981 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2983 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2985 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 2986 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 2987 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2988 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2989 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 2990 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2991 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2993 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 2994 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2995 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 2997 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 2998 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 2999 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3000 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3001 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3002 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 3003 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3005 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3006 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 3007 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3009 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3010 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 3011 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3012 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3013 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3014 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 3015 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3017 3018 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3021 NUM_BANKS(ADDR_SURF_16_BANK)); 3022 3023 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3024 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3025 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3026 NUM_BANKS(ADDR_SURF_16_BANK)); 3027 3028 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3031 NUM_BANKS(ADDR_SURF_16_BANK)); 3032 3033 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3036 NUM_BANKS(ADDR_SURF_16_BANK)); 3037 3038 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3039 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3040 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3041 NUM_BANKS(ADDR_SURF_16_BANK)); 3042 3043 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3044 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3045 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3046 NUM_BANKS(ADDR_SURF_16_BANK)); 3047 3048 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3049 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3050 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3051 NUM_BANKS(ADDR_SURF_16_BANK)); 3052 3053 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3054 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3055 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3056 NUM_BANKS(ADDR_SURF_16_BANK)); 3057 3058 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3059 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3060 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3061 NUM_BANKS(ADDR_SURF_16_BANK)); 3062 3063 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3066 NUM_BANKS(ADDR_SURF_16_BANK)); 3067 3068 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3069 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3070 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3071 NUM_BANKS(ADDR_SURF_16_BANK)); 3072 3073 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3074 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3075 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3076 NUM_BANKS(ADDR_SURF_8_BANK)); 3077 3078 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3081 NUM_BANKS(ADDR_SURF_4_BANK)); 3082 3083 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3084 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3085 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 3086 NUM_BANKS(ADDR_SURF_4_BANK)); 3087 3088 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3089 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3090 3091 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3092 if (reg_offset != 7) 3093 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3094 3095 break; 3096 case CHIP_STONEY: 3097 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3098 PIPE_CONFIG(ADDR_SURF_P2) | 3099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 3100 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3101 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3102 PIPE_CONFIG(ADDR_SURF_P2) | 3103 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 3104 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3105 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3106 PIPE_CONFIG(ADDR_SURF_P2) | 3107 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 3108 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3109 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3110 PIPE_CONFIG(ADDR_SURF_P2) | 3111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 3112 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3113 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3114 PIPE_CONFIG(ADDR_SURF_P2) | 3115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3116 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3117 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3118 PIPE_CONFIG(ADDR_SURF_P2) | 3119 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3120 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3121 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3122 PIPE_CONFIG(ADDR_SURF_P2) | 3123 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3124 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3125 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 3126 PIPE_CONFIG(ADDR_SURF_P2)); 3127 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3128 PIPE_CONFIG(ADDR_SURF_P2) | 3129 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3131 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3132 PIPE_CONFIG(ADDR_SURF_P2) | 3133 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3135 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3136 PIPE_CONFIG(ADDR_SURF_P2) | 3137 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3139 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3140 PIPE_CONFIG(ADDR_SURF_P2) | 3141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3143 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3144 PIPE_CONFIG(ADDR_SURF_P2) | 3145 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3147 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 3148 PIPE_CONFIG(ADDR_SURF_P2) | 3149 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3151 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3152 PIPE_CONFIG(ADDR_SURF_P2) | 3153 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3155 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3156 PIPE_CONFIG(ADDR_SURF_P2) | 3157 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3158 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3159 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3160 PIPE_CONFIG(ADDR_SURF_P2) | 3161 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3163 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3164 PIPE_CONFIG(ADDR_SURF_P2) | 3165 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3167 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 3168 PIPE_CONFIG(ADDR_SURF_P2) | 3169 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3170 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3171 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 3172 PIPE_CONFIG(ADDR_SURF_P2) | 3173 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3175 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3176 PIPE_CONFIG(ADDR_SURF_P2) | 3177 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3179 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 3180 PIPE_CONFIG(ADDR_SURF_P2) | 3181 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3182 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3183 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 3184 PIPE_CONFIG(ADDR_SURF_P2) | 3185 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3186 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3187 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3188 PIPE_CONFIG(ADDR_SURF_P2) | 3189 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3191 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3192 PIPE_CONFIG(ADDR_SURF_P2) | 3193 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3194 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3195 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3196 PIPE_CONFIG(ADDR_SURF_P2) | 3197 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3198 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3199 3200 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3203 NUM_BANKS(ADDR_SURF_8_BANK)); 3204 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3207 NUM_BANKS(ADDR_SURF_8_BANK)); 3208 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3211 NUM_BANKS(ADDR_SURF_8_BANK)); 3212 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3215 NUM_BANKS(ADDR_SURF_8_BANK)); 3216 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3219 NUM_BANKS(ADDR_SURF_8_BANK)); 3220 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3223 NUM_BANKS(ADDR_SURF_8_BANK)); 3224 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3227 NUM_BANKS(ADDR_SURF_8_BANK)); 3228 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3231 NUM_BANKS(ADDR_SURF_16_BANK)); 3232 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3235 NUM_BANKS(ADDR_SURF_16_BANK)); 3236 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3239 NUM_BANKS(ADDR_SURF_16_BANK)); 3240 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3243 NUM_BANKS(ADDR_SURF_16_BANK)); 3244 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3247 NUM_BANKS(ADDR_SURF_16_BANK)); 3248 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3249 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3251 NUM_BANKS(ADDR_SURF_16_BANK)); 3252 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3255 NUM_BANKS(ADDR_SURF_8_BANK)); 3256 3257 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3258 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 3259 reg_offset != 23) 3260 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3261 3262 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3263 if (reg_offset != 7) 3264 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3265 3266 break; 3267 default: 3268 dev_warn(adev->dev, 3269 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n", 3270 adev->asic_type); 3271 3272 case CHIP_CARRIZO: 3273 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3274 PIPE_CONFIG(ADDR_SURF_P2) | 3275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 3276 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3277 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3278 PIPE_CONFIG(ADDR_SURF_P2) | 3279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 3280 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3281 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3282 PIPE_CONFIG(ADDR_SURF_P2) | 3283 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 3284 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3285 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3286 PIPE_CONFIG(ADDR_SURF_P2) | 3287 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 3288 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3289 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3290 PIPE_CONFIG(ADDR_SURF_P2) | 3291 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3292 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3293 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3294 PIPE_CONFIG(ADDR_SURF_P2) | 3295 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3296 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3297 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3298 PIPE_CONFIG(ADDR_SURF_P2) | 3299 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 3300 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 3301 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 3302 PIPE_CONFIG(ADDR_SURF_P2)); 3303 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3304 PIPE_CONFIG(ADDR_SURF_P2) | 3305 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3307 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3308 PIPE_CONFIG(ADDR_SURF_P2) | 3309 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3311 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3312 PIPE_CONFIG(ADDR_SURF_P2) | 3313 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 3314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3315 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3316 PIPE_CONFIG(ADDR_SURF_P2) | 3317 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3319 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3320 PIPE_CONFIG(ADDR_SURF_P2) | 3321 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3323 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 3324 PIPE_CONFIG(ADDR_SURF_P2) | 3325 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3326 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3327 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3328 PIPE_CONFIG(ADDR_SURF_P2) | 3329 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3331 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3332 PIPE_CONFIG(ADDR_SURF_P2) | 3333 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3334 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3335 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 3336 PIPE_CONFIG(ADDR_SURF_P2) | 3337 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3338 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3339 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3340 PIPE_CONFIG(ADDR_SURF_P2) | 3341 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3342 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3343 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 3344 PIPE_CONFIG(ADDR_SURF_P2) | 3345 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3346 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3347 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 3348 PIPE_CONFIG(ADDR_SURF_P2) | 3349 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3350 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3351 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 3352 PIPE_CONFIG(ADDR_SURF_P2) | 3353 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 3354 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3355 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 3356 PIPE_CONFIG(ADDR_SURF_P2) | 3357 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3358 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3359 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 3360 PIPE_CONFIG(ADDR_SURF_P2) | 3361 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 3362 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 3363 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 3364 PIPE_CONFIG(ADDR_SURF_P2) | 3365 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3366 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3367 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 3368 PIPE_CONFIG(ADDR_SURF_P2) | 3369 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3370 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 3371 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 3372 PIPE_CONFIG(ADDR_SURF_P2) | 3373 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 3374 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 3375 3376 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3379 NUM_BANKS(ADDR_SURF_8_BANK)); 3380 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3381 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3382 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3383 NUM_BANKS(ADDR_SURF_8_BANK)); 3384 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3385 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3386 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3387 NUM_BANKS(ADDR_SURF_8_BANK)); 3388 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3389 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3390 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3391 NUM_BANKS(ADDR_SURF_8_BANK)); 3392 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3393 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3394 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3395 NUM_BANKS(ADDR_SURF_8_BANK)); 3396 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3397 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3398 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3399 NUM_BANKS(ADDR_SURF_8_BANK)); 3400 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3401 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3402 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3403 NUM_BANKS(ADDR_SURF_8_BANK)); 3404 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3405 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 3406 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3407 NUM_BANKS(ADDR_SURF_16_BANK)); 3408 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 3409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3411 NUM_BANKS(ADDR_SURF_16_BANK)); 3412 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3413 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 3414 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3415 NUM_BANKS(ADDR_SURF_16_BANK)); 3416 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 3417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3419 NUM_BANKS(ADDR_SURF_16_BANK)); 3420 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 3422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3423 NUM_BANKS(ADDR_SURF_16_BANK)); 3424 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3425 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3426 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 3427 NUM_BANKS(ADDR_SURF_16_BANK)); 3428 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 3429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 3430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 3431 NUM_BANKS(ADDR_SURF_8_BANK)); 3432 3433 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3434 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && 3435 reg_offset != 23) 3436 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); 3437 3438 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 3439 if (reg_offset != 7) 3440 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); 3441 3442 break; 3443 } 3444 } 3445 3446 static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, 3447 u32 se_num, u32 sh_num, u32 instance) 3448 { 3449 u32 data; 3450 3451 if (instance == 0xffffffff) 3452 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 3453 else 3454 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 3455 3456 if (se_num == 0xffffffff) 3457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 3458 else 3459 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 3460 3461 if (sh_num == 0xffffffff) 3462 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 3463 else 3464 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 3465 3466 WREG32(mmGRBM_GFX_INDEX, data); 3467 } 3468 3469 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) 3470 { 3471 u32 data, mask; 3472 3473 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 3474 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 3475 3476 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 3477 3478 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 3479 adev->gfx.config.max_sh_per_se); 3480 3481 return (~data) & mask; 3482 } 3483 3484 static void 3485 gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 3486 { 3487 switch (adev->asic_type) { 3488 case CHIP_FIJI: 3489 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 3490 RB_XSEL2(1) | PKR_MAP(2) | 3491 PKR_XSEL(1) | PKR_YSEL(1) | 3492 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3); 3493 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 3494 SE_PAIR_YSEL(2); 3495 break; 3496 case CHIP_TONGA: 3497 case CHIP_POLARIS10: 3498 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 3499 SE_XSEL(1) | SE_YSEL(1); 3500 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) | 3501 SE_PAIR_YSEL(2); 3502 break; 3503 case CHIP_TOPAZ: 3504 case CHIP_CARRIZO: 3505 *rconf |= RB_MAP_PKR0(2); 3506 *rconf1 |= 0x0; 3507 break; 3508 case CHIP_POLARIS11: 3509 case CHIP_POLARIS12: 3510 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 3511 SE_XSEL(1) | SE_YSEL(1); 3512 *rconf1 |= 0x0; 3513 break; 3514 case CHIP_STONEY: 3515 *rconf |= 0x0; 3516 *rconf1 |= 0x0; 3517 break; 3518 default: 3519 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 3520 break; 3521 } 3522 } 3523 3524 static void 3525 gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev, 3526 u32 raster_config, u32 raster_config_1, 3527 unsigned rb_mask, unsigned num_rb) 3528 { 3529 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 3530 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 3531 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 3532 unsigned rb_per_se = num_rb / num_se; 3533 unsigned se_mask[4]; 3534 unsigned se; 3535 3536 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 3537 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 3538 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 3539 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 3540 3541 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 3542 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 3543 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 3544 3545 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 3546 (!se_mask[2] && !se_mask[3]))) { 3547 raster_config_1 &= ~SE_PAIR_MAP_MASK; 3548 3549 if (!se_mask[0] && !se_mask[1]) { 3550 raster_config_1 |= 3551 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 3552 } else { 3553 raster_config_1 |= 3554 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 3555 } 3556 } 3557 3558 for (se = 0; se < num_se; se++) { 3559 unsigned raster_config_se = raster_config; 3560 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 3561 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 3562 int idx = (se / 2) * 2; 3563 3564 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 3565 raster_config_se &= ~SE_MAP_MASK; 3566 3567 if (!se_mask[idx]) { 3568 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 3569 } else { 3570 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 3571 } 3572 } 3573 3574 pkr0_mask &= rb_mask; 3575 pkr1_mask &= rb_mask; 3576 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 3577 raster_config_se &= ~PKR_MAP_MASK; 3578 3579 if (!pkr0_mask) { 3580 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 3581 } else { 3582 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 3583 } 3584 } 3585 3586 if (rb_per_se >= 2) { 3587 unsigned rb0_mask = 1 << (se * rb_per_se); 3588 unsigned rb1_mask = rb0_mask << 1; 3589 3590 rb0_mask &= rb_mask; 3591 rb1_mask &= rb_mask; 3592 if (!rb0_mask || !rb1_mask) { 3593 raster_config_se &= ~RB_MAP_PKR0_MASK; 3594 3595 if (!rb0_mask) { 3596 raster_config_se |= 3597 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 3598 } else { 3599 raster_config_se |= 3600 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 3601 } 3602 } 3603 3604 if (rb_per_se > 2) { 3605 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 3606 rb1_mask = rb0_mask << 1; 3607 rb0_mask &= rb_mask; 3608 rb1_mask &= rb_mask; 3609 if (!rb0_mask || !rb1_mask) { 3610 raster_config_se &= ~RB_MAP_PKR1_MASK; 3611 3612 if (!rb0_mask) { 3613 raster_config_se |= 3614 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 3615 } else { 3616 raster_config_se |= 3617 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 3618 } 3619 } 3620 } 3621 } 3622 3623 /* GRBM_GFX_INDEX has a different offset on VI */ 3624 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 3625 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 3626 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 3627 } 3628 3629 /* GRBM_GFX_INDEX has a different offset on VI */ 3630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3631 } 3632 3633 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) 3634 { 3635 int i, j; 3636 u32 data; 3637 u32 raster_config = 0, raster_config_1 = 0; 3638 u32 active_rbs = 0; 3639 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 3640 adev->gfx.config.max_sh_per_se; 3641 unsigned num_rb_pipes; 3642 3643 mutex_lock(&adev->grbm_idx_mutex); 3644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3646 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3647 data = gfx_v8_0_get_rb_active_bitmap(adev); 3648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 3649 rb_bitmap_width_per_sh); 3650 } 3651 } 3652 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3653 3654 adev->gfx.config.backend_enable_mask = active_rbs; 3655 adev->gfx.config.num_rbs = hweight32(active_rbs); 3656 3657 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 3658 adev->gfx.config.max_shader_engines, 16); 3659 3660 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1); 3661 3662 if (!adev->gfx.config.backend_enable_mask || 3663 adev->gfx.config.num_rbs >= num_rb_pipes) { 3664 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 3665 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 3666 } else { 3667 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 3668 adev->gfx.config.backend_enable_mask, 3669 num_rb_pipes); 3670 } 3671 3672 /* cache the values for userspace */ 3673 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3674 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3675 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3676 adev->gfx.config.rb_config[i][j].rb_backend_disable = 3677 RREG32(mmCC_RB_BACKEND_DISABLE); 3678 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 3679 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 3680 adev->gfx.config.rb_config[i][j].raster_config = 3681 RREG32(mmPA_SC_RASTER_CONFIG); 3682 adev->gfx.config.rb_config[i][j].raster_config_1 = 3683 RREG32(mmPA_SC_RASTER_CONFIG_1); 3684 } 3685 } 3686 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3687 mutex_unlock(&adev->grbm_idx_mutex); 3688 } 3689 3690 /** 3691 * gfx_v8_0_init_compute_vmid - gart enable 3692 * 3693 * @adev: amdgpu_device pointer 3694 * 3695 * Initialize compute vmid sh_mem registers 3696 * 3697 */ 3698 #define DEFAULT_SH_MEM_BASES (0x6000) 3699 #define FIRST_COMPUTE_VMID (8) 3700 #define LAST_COMPUTE_VMID (16) 3701 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) 3702 { 3703 int i; 3704 uint32_t sh_mem_config; 3705 uint32_t sh_mem_bases; 3706 3707 /* 3708 * Configure apertures: 3709 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 3710 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 3711 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 3712 */ 3713 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 3714 3715 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << 3716 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | 3717 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 3718 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | 3719 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | 3720 SH_MEM_CONFIG__PRIVATE_ATC_MASK; 3721 3722 mutex_lock(&adev->srbm_mutex); 3723 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 3724 vi_srbm_select(adev, 0, 0, 0, i); 3725 /* CP and shaders */ 3726 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 3727 WREG32(mmSH_MEM_APE1_BASE, 1); 3728 WREG32(mmSH_MEM_APE1_LIMIT, 0); 3729 WREG32(mmSH_MEM_BASES, sh_mem_bases); 3730 } 3731 vi_srbm_select(adev, 0, 0, 0, 0); 3732 mutex_unlock(&adev->srbm_mutex); 3733 } 3734 3735 static void gfx_v8_0_config_init(struct amdgpu_device *adev) 3736 { 3737 switch (adev->asic_type) { 3738 default: 3739 adev->gfx.config.double_offchip_lds_buf = 1; 3740 break; 3741 case CHIP_CARRIZO: 3742 case CHIP_STONEY: 3743 adev->gfx.config.double_offchip_lds_buf = 0; 3744 break; 3745 } 3746 } 3747 3748 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 3749 { 3750 u32 tmp, sh_static_mem_cfg; 3751 int i; 3752 3753 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); 3754 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 3755 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 3756 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 3757 3758 gfx_v8_0_tiling_mode_table_init(adev); 3759 gfx_v8_0_setup_rb(adev); 3760 gfx_v8_0_get_cu_info(adev); 3761 gfx_v8_0_config_init(adev); 3762 3763 /* XXX SH_MEM regs */ 3764 /* where to put LDS, scratch, GPUVM in FSA64 space */ 3765 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 3766 SWIZZLE_ENABLE, 1); 3767 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 3768 ELEMENT_SIZE, 1); 3769 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 3770 INDEX_STRIDE, 3); 3771 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 3772 3773 mutex_lock(&adev->srbm_mutex); 3774 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 3775 vi_srbm_select(adev, 0, 0, 0, i); 3776 /* CP and shaders */ 3777 if (i == 0) { 3778 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); 3779 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 3780 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 3781 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 3782 WREG32(mmSH_MEM_CONFIG, tmp); 3783 WREG32(mmSH_MEM_BASES, 0); 3784 } else { 3785 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); 3786 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 3787 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 3788 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 3789 WREG32(mmSH_MEM_CONFIG, tmp); 3790 tmp = adev->mc.shared_aperture_start >> 48; 3791 WREG32(mmSH_MEM_BASES, tmp); 3792 } 3793 3794 WREG32(mmSH_MEM_APE1_BASE, 1); 3795 WREG32(mmSH_MEM_APE1_LIMIT, 0); 3796 } 3797 vi_srbm_select(adev, 0, 0, 0, 0); 3798 mutex_unlock(&adev->srbm_mutex); 3799 3800 gfx_v8_0_init_compute_vmid(adev); 3801 3802 mutex_lock(&adev->grbm_idx_mutex); 3803 /* 3804 * making sure that the following register writes will be broadcasted 3805 * to all the shaders 3806 */ 3807 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3808 3809 WREG32(mmPA_SC_FIFO_SIZE, 3810 (adev->gfx.config.sc_prim_fifo_size_frontend << 3811 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 3812 (adev->gfx.config.sc_prim_fifo_size_backend << 3813 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 3814 (adev->gfx.config.sc_hiz_tile_fifo_size << 3815 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 3816 (adev->gfx.config.sc_earlyz_tile_fifo_size << 3817 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 3818 3819 tmp = RREG32(mmSPI_ARB_PRIORITY); 3820 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 3821 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 3822 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 3823 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 3824 WREG32(mmSPI_ARB_PRIORITY, tmp); 3825 3826 mutex_unlock(&adev->grbm_idx_mutex); 3827 3828 } 3829 3830 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3831 { 3832 u32 i, j, k; 3833 u32 mask; 3834 3835 mutex_lock(&adev->grbm_idx_mutex); 3836 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3837 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3838 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3839 for (k = 0; k < adev->usec_timeout; k++) { 3840 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3841 break; 3842 udelay(1); 3843 } 3844 } 3845 } 3846 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3847 mutex_unlock(&adev->grbm_idx_mutex); 3848 3849 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3850 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3851 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3852 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3853 for (k = 0; k < adev->usec_timeout; k++) { 3854 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3855 break; 3856 udelay(1); 3857 } 3858 } 3859 3860 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3861 bool enable) 3862 { 3863 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3864 3865 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 3866 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 3867 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 3868 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 3869 3870 WREG32(mmCP_INT_CNTL_RING0, tmp); 3871 } 3872 3873 static void gfx_v8_0_init_csb(struct amdgpu_device *adev) 3874 { 3875 /* csib */ 3876 WREG32(mmRLC_CSIB_ADDR_HI, 3877 adev->gfx.rlc.clear_state_gpu_addr >> 32); 3878 WREG32(mmRLC_CSIB_ADDR_LO, 3879 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 3880 WREG32(mmRLC_CSIB_LENGTH, 3881 adev->gfx.rlc.clear_state_size); 3882 } 3883 3884 static void gfx_v8_0_parse_ind_reg_list(int *register_list_format, 3885 int ind_offset, 3886 int list_size, 3887 int *unique_indices, 3888 int *indices_count, 3889 int max_indices, 3890 int *ind_start_offsets, 3891 int *offset_count, 3892 int max_offset) 3893 { 3894 int indices; 3895 bool new_entry = true; 3896 3897 for (; ind_offset < list_size; ind_offset++) { 3898 3899 if (new_entry) { 3900 new_entry = false; 3901 ind_start_offsets[*offset_count] = ind_offset; 3902 *offset_count = *offset_count + 1; 3903 BUG_ON(*offset_count >= max_offset); 3904 } 3905 3906 if (register_list_format[ind_offset] == 0xFFFFFFFF) { 3907 new_entry = true; 3908 continue; 3909 } 3910 3911 ind_offset += 2; 3912 3913 /* look for the matching indice */ 3914 for (indices = 0; 3915 indices < *indices_count; 3916 indices++) { 3917 if (unique_indices[indices] == 3918 register_list_format[ind_offset]) 3919 break; 3920 } 3921 3922 if (indices >= *indices_count) { 3923 unique_indices[*indices_count] = 3924 register_list_format[ind_offset]; 3925 indices = *indices_count; 3926 *indices_count = *indices_count + 1; 3927 BUG_ON(*indices_count >= max_indices); 3928 } 3929 3930 register_list_format[ind_offset] = indices; 3931 } 3932 } 3933 3934 static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) 3935 { 3936 int i, temp, data; 3937 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; 3938 int indices_count = 0; 3939 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 3940 int offset_count = 0; 3941 3942 int list_size; 3943 unsigned int *register_list_format = 3944 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 3945 if (!register_list_format) 3946 return -ENOMEM; 3947 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 3948 adev->gfx.rlc.reg_list_format_size_bytes); 3949 3950 gfx_v8_0_parse_ind_reg_list(register_list_format, 3951 RLC_FormatDirectRegListLength, 3952 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 3953 unique_indices, 3954 &indices_count, 3955 sizeof(unique_indices) / sizeof(int), 3956 indirect_start_offsets, 3957 &offset_count, 3958 sizeof(indirect_start_offsets)/sizeof(int)); 3959 3960 /* save and restore list */ 3961 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); 3962 3963 WREG32(mmRLC_SRM_ARAM_ADDR, 0); 3964 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 3965 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]); 3966 3967 /* indirect list */ 3968 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start); 3969 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) 3970 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]); 3971 3972 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 3973 list_size = list_size >> 1; 3974 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size); 3975 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size); 3976 3977 /* starting offsets starts */ 3978 WREG32(mmRLC_GPM_SCRATCH_ADDR, 3979 adev->gfx.rlc.starting_offsets_start); 3980 for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++) 3981 WREG32(mmRLC_GPM_SCRATCH_DATA, 3982 indirect_start_offsets[i]); 3983 3984 /* unique indices */ 3985 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; 3986 data = mmRLC_SRM_INDEX_CNTL_DATA_0; 3987 for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) { 3988 if (unique_indices[i] != 0) { 3989 WREG32(temp + i, unique_indices[i] & 0x3FFFF); 3990 WREG32(data + i, unique_indices[i] >> 20); 3991 } 3992 } 3993 kfree(register_list_format); 3994 3995 return 0; 3996 } 3997 3998 static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) 3999 { 4000 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); 4001 } 4002 4003 static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) 4004 { 4005 uint32_t data; 4006 4007 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60); 4008 4009 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10); 4010 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10); 4011 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10); 4012 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10); 4013 WREG32(mmRLC_PG_DELAY, data); 4014 4015 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3); 4016 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0); 4017 4018 } 4019 4020 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 4021 bool enable) 4022 { 4023 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); 4024 } 4025 4026 static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 4027 bool enable) 4028 { 4029 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); 4030 } 4031 4032 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) 4033 { 4034 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); 4035 } 4036 4037 static void gfx_v8_0_init_pg(struct amdgpu_device *adev) 4038 { 4039 if ((adev->asic_type == CHIP_CARRIZO) || 4040 (adev->asic_type == CHIP_STONEY)) { 4041 gfx_v8_0_init_csb(adev); 4042 gfx_v8_0_init_save_restore_list(adev); 4043 gfx_v8_0_enable_save_restore_machine(adev); 4044 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4045 gfx_v8_0_init_power_gating(adev); 4046 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4047 } else if ((adev->asic_type == CHIP_POLARIS11) || 4048 (adev->asic_type == CHIP_POLARIS12)) { 4049 gfx_v8_0_init_csb(adev); 4050 gfx_v8_0_init_save_restore_list(adev); 4051 gfx_v8_0_enable_save_restore_machine(adev); 4052 gfx_v8_0_init_power_gating(adev); 4053 } 4054 4055 } 4056 4057 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) 4058 { 4059 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); 4060 4061 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 4062 gfx_v8_0_wait_for_rlc_serdes(adev); 4063 } 4064 4065 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) 4066 { 4067 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4068 udelay(50); 4069 4070 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 4071 udelay(50); 4072 } 4073 4074 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) 4075 { 4076 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); 4077 4078 /* carrizo do enable cp interrupt after cp inited */ 4079 if (!(adev->flags & AMD_IS_APU)) 4080 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 4081 4082 udelay(50); 4083 } 4084 4085 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) 4086 { 4087 const struct rlc_firmware_header_v2_0 *hdr; 4088 const __le32 *fw_data; 4089 unsigned i, fw_size; 4090 4091 if (!adev->gfx.rlc_fw) 4092 return -EINVAL; 4093 4094 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4095 amdgpu_ucode_print_rlc_hdr(&hdr->header); 4096 4097 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 4098 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 4099 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 4100 4101 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 4102 for (i = 0; i < fw_size; i++) 4103 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 4104 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 4105 4106 return 0; 4107 } 4108 4109 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 4110 { 4111 int r; 4112 u32 tmp; 4113 4114 gfx_v8_0_rlc_stop(adev); 4115 4116 /* disable CG */ 4117 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL); 4118 tmp &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | 4119 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4120 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 4121 if (adev->asic_type == CHIP_POLARIS11 || 4122 adev->asic_type == CHIP_POLARIS10 || 4123 adev->asic_type == CHIP_POLARIS12) { 4124 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL_3D); 4125 tmp &= ~0x3; 4126 WREG32(mmRLC_CGCG_CGLS_CTRL_3D, tmp); 4127 } 4128 4129 /* disable PG */ 4130 WREG32(mmRLC_PG_CNTL, 0); 4131 4132 gfx_v8_0_rlc_reset(adev); 4133 gfx_v8_0_init_pg(adev); 4134 4135 if (!adev->pp_enabled) { 4136 if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { 4137 /* legacy rlc firmware loading */ 4138 r = gfx_v8_0_rlc_load_microcode(adev); 4139 if (r) 4140 return r; 4141 } else { 4142 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4143 AMDGPU_UCODE_ID_RLC_G); 4144 if (r) 4145 return -EINVAL; 4146 } 4147 } 4148 4149 gfx_v8_0_rlc_start(adev); 4150 4151 return 0; 4152 } 4153 4154 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 4155 { 4156 int i; 4157 u32 tmp = RREG32(mmCP_ME_CNTL); 4158 4159 if (enable) { 4160 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); 4161 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); 4162 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); 4163 } else { 4164 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); 4165 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); 4166 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); 4167 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4168 adev->gfx.gfx_ring[i].ready = false; 4169 } 4170 WREG32(mmCP_ME_CNTL, tmp); 4171 udelay(50); 4172 } 4173 4174 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 4175 { 4176 const struct gfx_firmware_header_v1_0 *pfp_hdr; 4177 const struct gfx_firmware_header_v1_0 *ce_hdr; 4178 const struct gfx_firmware_header_v1_0 *me_hdr; 4179 const __le32 *fw_data; 4180 unsigned i, fw_size; 4181 4182 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 4183 return -EINVAL; 4184 4185 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 4186 adev->gfx.pfp_fw->data; 4187 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 4188 adev->gfx.ce_fw->data; 4189 me_hdr = (const struct gfx_firmware_header_v1_0 *) 4190 adev->gfx.me_fw->data; 4191 4192 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 4193 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 4194 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 4195 4196 gfx_v8_0_cp_gfx_enable(adev, false); 4197 4198 /* PFP */ 4199 fw_data = (const __le32 *) 4200 (adev->gfx.pfp_fw->data + 4201 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 4202 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 4203 WREG32(mmCP_PFP_UCODE_ADDR, 0); 4204 for (i = 0; i < fw_size; i++) 4205 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 4206 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 4207 4208 /* CE */ 4209 fw_data = (const __le32 *) 4210 (adev->gfx.ce_fw->data + 4211 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 4212 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 4213 WREG32(mmCP_CE_UCODE_ADDR, 0); 4214 for (i = 0; i < fw_size; i++) 4215 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 4216 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 4217 4218 /* ME */ 4219 fw_data = (const __le32 *) 4220 (adev->gfx.me_fw->data + 4221 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 4222 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 4223 WREG32(mmCP_ME_RAM_WADDR, 0); 4224 for (i = 0; i < fw_size; i++) 4225 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 4226 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 4227 4228 return 0; 4229 } 4230 4231 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) 4232 { 4233 u32 count = 0; 4234 const struct cs_section_def *sect = NULL; 4235 const struct cs_extent_def *ext = NULL; 4236 4237 /* begin clear state */ 4238 count += 2; 4239 /* context control state */ 4240 count += 3; 4241 4242 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 4243 for (ext = sect->section; ext->extent != NULL; ++ext) { 4244 if (sect->id == SECT_CONTEXT) 4245 count += 2 + ext->reg_count; 4246 else 4247 return 0; 4248 } 4249 } 4250 /* pa_sc_raster_config/pa_sc_raster_config1 */ 4251 count += 4; 4252 /* end clear state */ 4253 count += 2; 4254 /* clear state */ 4255 count += 2; 4256 4257 return count; 4258 } 4259 4260 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) 4261 { 4262 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 4263 const struct cs_section_def *sect = NULL; 4264 const struct cs_extent_def *ext = NULL; 4265 int r, i; 4266 4267 /* init the CP */ 4268 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 4269 WREG32(mmCP_ENDIAN_SWAP, 0); 4270 WREG32(mmCP_DEVICE_ID, 1); 4271 4272 gfx_v8_0_cp_gfx_enable(adev, true); 4273 4274 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4); 4275 if (r) { 4276 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 4277 return r; 4278 } 4279 4280 /* clear state buffer */ 4281 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4282 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4283 4284 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4285 amdgpu_ring_write(ring, 0x80000000); 4286 amdgpu_ring_write(ring, 0x80000000); 4287 4288 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 4289 for (ext = sect->section; ext->extent != NULL; ++ext) { 4290 if (sect->id == SECT_CONTEXT) { 4291 amdgpu_ring_write(ring, 4292 PACKET3(PACKET3_SET_CONTEXT_REG, 4293 ext->reg_count)); 4294 amdgpu_ring_write(ring, 4295 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4296 for (i = 0; i < ext->reg_count; i++) 4297 amdgpu_ring_write(ring, ext->extent[i]); 4298 } 4299 } 4300 } 4301 4302 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4303 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4304 switch (adev->asic_type) { 4305 case CHIP_TONGA: 4306 case CHIP_POLARIS10: 4307 amdgpu_ring_write(ring, 0x16000012); 4308 amdgpu_ring_write(ring, 0x0000002A); 4309 break; 4310 case CHIP_POLARIS11: 4311 case CHIP_POLARIS12: 4312 amdgpu_ring_write(ring, 0x16000012); 4313 amdgpu_ring_write(ring, 0x00000000); 4314 break; 4315 case CHIP_FIJI: 4316 amdgpu_ring_write(ring, 0x3a00161a); 4317 amdgpu_ring_write(ring, 0x0000002e); 4318 break; 4319 case CHIP_CARRIZO: 4320 amdgpu_ring_write(ring, 0x00000002); 4321 amdgpu_ring_write(ring, 0x00000000); 4322 break; 4323 case CHIP_TOPAZ: 4324 amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ? 4325 0x00000000 : 0x00000002); 4326 amdgpu_ring_write(ring, 0x00000000); 4327 break; 4328 case CHIP_STONEY: 4329 amdgpu_ring_write(ring, 0x00000000); 4330 amdgpu_ring_write(ring, 0x00000000); 4331 break; 4332 default: 4333 BUG(); 4334 } 4335 4336 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4337 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 4338 4339 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 4340 amdgpu_ring_write(ring, 0); 4341 4342 /* init the CE partitions */ 4343 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 4344 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 4345 amdgpu_ring_write(ring, 0x8000); 4346 amdgpu_ring_write(ring, 0x8000); 4347 4348 amdgpu_ring_commit(ring); 4349 4350 return 0; 4351 } 4352 static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring) 4353 { 4354 u32 tmp; 4355 /* no gfx doorbells on iceland */ 4356 if (adev->asic_type == CHIP_TOPAZ) 4357 return; 4358 4359 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); 4360 4361 if (ring->use_doorbell) { 4362 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4363 DOORBELL_OFFSET, ring->doorbell_index); 4364 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4365 DOORBELL_HIT, 0); 4366 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 4367 DOORBELL_EN, 1); 4368 } else { 4369 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 4370 } 4371 4372 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); 4373 4374 if (adev->flags & AMD_IS_APU) 4375 return; 4376 4377 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 4378 DOORBELL_RANGE_LOWER, 4379 AMDGPU_DOORBELL_GFX_RING0); 4380 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 4381 4382 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, 4383 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 4384 } 4385 4386 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) 4387 { 4388 struct amdgpu_ring *ring; 4389 u32 tmp; 4390 u32 rb_bufsz; 4391 u64 rb_addr, rptr_addr, wptr_gpu_addr; 4392 int r; 4393 4394 /* Set the write pointer delay */ 4395 WREG32(mmCP_RB_WPTR_DELAY, 0); 4396 4397 /* set the RB to use vmid 0 */ 4398 WREG32(mmCP_RB_VMID, 0); 4399 4400 /* Set ring buffer size */ 4401 ring = &adev->gfx.gfx_ring[0]; 4402 rb_bufsz = order_base_2(ring->ring_size / 8); 4403 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 4404 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 4405 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); 4406 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); 4407 #ifdef __BIG_ENDIAN 4408 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 4409 #endif 4410 WREG32(mmCP_RB0_CNTL, tmp); 4411 4412 /* Initialize the ring buffer's read and write pointers */ 4413 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 4414 ring->wptr = 0; 4415 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4416 4417 /* set the wb address wether it's enabled or not */ 4418 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 4419 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 4420 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 4421 4422 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4423 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 4424 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 4425 mdelay(1); 4426 WREG32(mmCP_RB0_CNTL, tmp); 4427 4428 rb_addr = ring->gpu_addr >> 8; 4429 WREG32(mmCP_RB0_BASE, rb_addr); 4430 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 4431 4432 gfx_v8_0_set_cpg_door_bell(adev, ring); 4433 /* start the ring */ 4434 amdgpu_ring_clear_ring(ring); 4435 gfx_v8_0_cp_gfx_start(adev); 4436 ring->ready = true; 4437 r = amdgpu_ring_test_ring(ring); 4438 if (r) 4439 ring->ready = false; 4440 4441 return r; 4442 } 4443 4444 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 4445 { 4446 int i; 4447 4448 if (enable) { 4449 WREG32(mmCP_MEC_CNTL, 0); 4450 } else { 4451 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 4452 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4453 adev->gfx.compute_ring[i].ready = false; 4454 adev->gfx.kiq.ring.ready = false; 4455 } 4456 udelay(50); 4457 } 4458 4459 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) 4460 { 4461 const struct gfx_firmware_header_v1_0 *mec_hdr; 4462 const __le32 *fw_data; 4463 unsigned i, fw_size; 4464 4465 if (!adev->gfx.mec_fw) 4466 return -EINVAL; 4467 4468 gfx_v8_0_cp_compute_enable(adev, false); 4469 4470 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4471 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 4472 4473 fw_data = (const __le32 *) 4474 (adev->gfx.mec_fw->data + 4475 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4476 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 4477 4478 /* MEC1 */ 4479 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 4480 for (i = 0; i < fw_size; i++) 4481 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); 4482 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 4483 4484 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 4485 if (adev->gfx.mec2_fw) { 4486 const struct gfx_firmware_header_v1_0 *mec2_hdr; 4487 4488 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 4489 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 4490 4491 fw_data = (const __le32 *) 4492 (adev->gfx.mec2_fw->data + 4493 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 4494 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 4495 4496 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 4497 for (i = 0; i < fw_size; i++) 4498 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i)); 4499 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); 4500 } 4501 4502 return 0; 4503 } 4504 4505 /* KIQ functions */ 4506 static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring) 4507 { 4508 uint32_t tmp; 4509 struct amdgpu_device *adev = ring->adev; 4510 4511 /* tell RLC which is KIQ queue */ 4512 tmp = RREG32(mmRLC_CP_SCHEDULERS); 4513 tmp &= 0xffffff00; 4514 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 4515 WREG32(mmRLC_CP_SCHEDULERS, tmp); 4516 tmp |= 0x80; 4517 WREG32(mmRLC_CP_SCHEDULERS, tmp); 4518 } 4519 4520 static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) 4521 { 4522 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 4523 uint32_t scratch, tmp = 0; 4524 uint64_t queue_mask = 0; 4525 int r, i; 4526 4527 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 4528 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 4529 continue; 4530 4531 /* This situation may be hit in the future if a new HW 4532 * generation exposes more than 64 queues. If so, the 4533 * definition of queue_mask needs updating */ 4534 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 4535 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 4536 break; 4537 } 4538 4539 queue_mask |= (1ull << i); 4540 } 4541 4542 r = amdgpu_gfx_scratch_get(adev, &scratch); 4543 if (r) { 4544 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 4545 return r; 4546 } 4547 WREG32(scratch, 0xCAFEDEAD); 4548 4549 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11); 4550 if (r) { 4551 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 4552 amdgpu_gfx_scratch_free(adev, scratch); 4553 return r; 4554 } 4555 /* set resources */ 4556 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 4557 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ 4558 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 4559 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 4560 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 4561 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 4562 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 4563 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 4564 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4565 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 4566 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 4567 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4568 4569 /* map queues */ 4570 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 4571 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 4572 amdgpu_ring_write(kiq_ring, 4573 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 4574 amdgpu_ring_write(kiq_ring, 4575 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) | 4576 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 4577 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 4578 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */ 4579 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 4580 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 4581 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 4582 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 4583 } 4584 /* write to scratch for completion */ 4585 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 4586 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 4587 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 4588 amdgpu_ring_commit(kiq_ring); 4589 4590 for (i = 0; i < adev->usec_timeout; i++) { 4591 tmp = RREG32(scratch); 4592 if (tmp == 0xDEADBEEF) 4593 break; 4594 DRM_UDELAY(1); 4595 } 4596 if (i >= adev->usec_timeout) { 4597 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", 4598 scratch, tmp); 4599 r = -EINVAL; 4600 } 4601 amdgpu_gfx_scratch_free(adev, scratch); 4602 4603 return r; 4604 } 4605 4606 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) 4607 { 4608 int i, r = 0; 4609 4610 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { 4611 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req); 4612 for (i = 0; i < adev->usec_timeout; i++) { 4613 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) 4614 break; 4615 udelay(1); 4616 } 4617 if (i == adev->usec_timeout) 4618 r = -ETIMEDOUT; 4619 } 4620 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 4621 WREG32(mmCP_HQD_PQ_RPTR, 0); 4622 WREG32(mmCP_HQD_PQ_WPTR, 0); 4623 4624 return r; 4625 } 4626 4627 static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) 4628 { 4629 struct amdgpu_device *adev = ring->adev; 4630 struct vi_mqd *mqd = ring->mqd_ptr; 4631 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 4632 uint32_t tmp; 4633 4634 mqd->header = 0xC0310800; 4635 mqd->compute_pipelinestat_enable = 0x00000001; 4636 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 4637 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 4638 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 4639 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 4640 mqd->compute_misc_reserved = 0x00000003; 4641 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr 4642 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); 4643 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr 4644 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); 4645 eop_base_addr = ring->eop_gpu_addr >> 8; 4646 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 4647 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 4648 4649 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 4650 tmp = RREG32(mmCP_HQD_EOP_CONTROL); 4651 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 4652 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1)); 4653 4654 mqd->cp_hqd_eop_control = tmp; 4655 4656 /* enable doorbell? */ 4657 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL), 4658 CP_HQD_PQ_DOORBELL_CONTROL, 4659 DOORBELL_EN, 4660 ring->use_doorbell ? 1 : 0); 4661 4662 mqd->cp_hqd_pq_doorbell_control = tmp; 4663 4664 /* set the pointer to the MQD */ 4665 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 4666 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 4667 4668 /* set MQD vmid to 0 */ 4669 tmp = RREG32(mmCP_MQD_CONTROL); 4670 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 4671 mqd->cp_mqd_control = tmp; 4672 4673 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 4674 hqd_gpu_addr = ring->gpu_addr >> 8; 4675 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 4676 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 4677 4678 /* set up the HQD, this is similar to CP_RB0_CNTL */ 4679 tmp = RREG32(mmCP_HQD_PQ_CONTROL); 4680 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 4681 (order_base_2(ring->ring_size / 4) - 1)); 4682 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 4683 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 4684 #ifdef __BIG_ENDIAN 4685 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 4686 #endif 4687 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 4688 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 4689 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 4690 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 4691 mqd->cp_hqd_pq_control = tmp; 4692 4693 /* set the wb address whether it's enabled or not */ 4694 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 4695 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 4696 mqd->cp_hqd_pq_rptr_report_addr_hi = 4697 upper_32_bits(wb_gpu_addr) & 0xffff; 4698 4699 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4700 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4701 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 4702 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4703 4704 tmp = 0; 4705 /* enable the doorbell if requested */ 4706 if (ring->use_doorbell) { 4707 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 4708 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4709 DOORBELL_OFFSET, ring->doorbell_index); 4710 4711 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4712 DOORBELL_EN, 1); 4713 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4714 DOORBELL_SOURCE, 0); 4715 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 4716 DOORBELL_HIT, 0); 4717 } 4718 4719 mqd->cp_hqd_pq_doorbell_control = tmp; 4720 4721 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 4722 ring->wptr = 0; 4723 mqd->cp_hqd_pq_wptr = ring->wptr; 4724 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 4725 4726 /* set the vmid for the queue */ 4727 mqd->cp_hqd_vmid = 0; 4728 4729 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); 4730 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 4731 mqd->cp_hqd_persistent_state = tmp; 4732 4733 /* set MTYPE */ 4734 tmp = RREG32(mmCP_HQD_IB_CONTROL); 4735 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 4736 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3); 4737 mqd->cp_hqd_ib_control = tmp; 4738 4739 tmp = RREG32(mmCP_HQD_IQ_TIMER); 4740 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3); 4741 mqd->cp_hqd_iq_timer = tmp; 4742 4743 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL); 4744 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3); 4745 mqd->cp_hqd_ctx_save_control = tmp; 4746 4747 /* defaults */ 4748 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR); 4749 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR); 4750 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 4751 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 4752 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 4753 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO); 4754 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI); 4755 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET); 4756 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE); 4757 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET); 4758 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE); 4759 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS); 4760 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR); 4761 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM); 4762 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES); 4763 4764 /* activate the queue */ 4765 mqd->cp_hqd_active = 1; 4766 4767 return 0; 4768 } 4769 4770 int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, 4771 struct vi_mqd *mqd) 4772 { 4773 uint32_t mqd_reg; 4774 uint32_t *mqd_data; 4775 4776 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */ 4777 mqd_data = &mqd->cp_mqd_base_addr_lo; 4778 4779 /* disable wptr polling */ 4780 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); 4781 4782 /* program all HQD registers */ 4783 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++) 4784 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4785 4786 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 4787 * This is safe since EOP RPTR==WPTR for any inactive HQD 4788 * on ASICs that do not support context-save. 4789 * EOP writes/reads can start anywhere in the ring. 4790 */ 4791 if (adev->asic_type != CHIP_TONGA) { 4792 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr); 4793 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr); 4794 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem); 4795 } 4796 4797 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++) 4798 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4799 4800 /* activate the HQD */ 4801 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 4802 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 4803 4804 return 0; 4805 } 4806 4807 static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) 4808 { 4809 struct amdgpu_device *adev = ring->adev; 4810 struct vi_mqd *mqd = ring->mqd_ptr; 4811 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 4812 4813 gfx_v8_0_kiq_setting(ring); 4814 4815 if (adev->in_sriov_reset) { /* for GPU_RESET case */ 4816 /* reset MQD to a clean status */ 4817 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4818 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); 4819 4820 /* reset ring buffer */ 4821 ring->wptr = 0; 4822 amdgpu_ring_clear_ring(ring); 4823 mutex_lock(&adev->srbm_mutex); 4824 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4825 gfx_v8_0_mqd_commit(adev, mqd); 4826 vi_srbm_select(adev, 0, 0, 0, 0); 4827 mutex_unlock(&adev->srbm_mutex); 4828 } else { 4829 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4830 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 4831 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 4832 mutex_lock(&adev->srbm_mutex); 4833 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4834 gfx_v8_0_mqd_init(ring); 4835 gfx_v8_0_mqd_commit(adev, mqd); 4836 vi_srbm_select(adev, 0, 0, 0, 0); 4837 mutex_unlock(&adev->srbm_mutex); 4838 4839 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4840 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); 4841 } 4842 4843 return 0; 4844 } 4845 4846 static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) 4847 { 4848 struct amdgpu_device *adev = ring->adev; 4849 struct vi_mqd *mqd = ring->mqd_ptr; 4850 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 4851 4852 if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { 4853 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); 4854 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 4855 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 4856 mutex_lock(&adev->srbm_mutex); 4857 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4858 gfx_v8_0_mqd_init(ring); 4859 vi_srbm_select(adev, 0, 0, 0, 0); 4860 mutex_unlock(&adev->srbm_mutex); 4861 4862 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4863 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); 4864 } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ 4865 /* reset MQD to a clean status */ 4866 if (adev->gfx.mec.mqd_backup[mqd_idx]) 4867 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); 4868 /* reset ring buffer */ 4869 ring->wptr = 0; 4870 amdgpu_ring_clear_ring(ring); 4871 } else { 4872 amdgpu_ring_clear_ring(ring); 4873 } 4874 return 0; 4875 } 4876 4877 static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev) 4878 { 4879 if (adev->asic_type > CHIP_TONGA) { 4880 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); 4881 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2); 4882 } 4883 /* enable doorbells */ 4884 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); 4885 } 4886 4887 static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) 4888 { 4889 struct amdgpu_ring *ring = NULL; 4890 int r = 0, i; 4891 4892 gfx_v8_0_cp_compute_enable(adev, true); 4893 4894 ring = &adev->gfx.kiq.ring; 4895 4896 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4897 if (unlikely(r != 0)) 4898 goto done; 4899 4900 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4901 if (!r) { 4902 r = gfx_v8_0_kiq_init_queue(ring); 4903 amdgpu_bo_kunmap(ring->mqd_obj); 4904 ring->mqd_ptr = NULL; 4905 } 4906 amdgpu_bo_unreserve(ring->mqd_obj); 4907 if (r) 4908 goto done; 4909 4910 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4911 ring = &adev->gfx.compute_ring[i]; 4912 4913 r = amdgpu_bo_reserve(ring->mqd_obj, false); 4914 if (unlikely(r != 0)) 4915 goto done; 4916 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); 4917 if (!r) { 4918 r = gfx_v8_0_kcq_init_queue(ring); 4919 amdgpu_bo_kunmap(ring->mqd_obj); 4920 ring->mqd_ptr = NULL; 4921 } 4922 amdgpu_bo_unreserve(ring->mqd_obj); 4923 if (r) 4924 goto done; 4925 } 4926 4927 gfx_v8_0_set_mec_doorbell_range(adev); 4928 4929 r = gfx_v8_0_kiq_kcq_enable(adev); 4930 if (r) 4931 goto done; 4932 4933 /* Test KIQ */ 4934 ring = &adev->gfx.kiq.ring; 4935 ring->ready = true; 4936 r = amdgpu_ring_test_ring(ring); 4937 if (r) { 4938 ring->ready = false; 4939 goto done; 4940 } 4941 4942 /* Test KCQs */ 4943 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4944 ring = &adev->gfx.compute_ring[i]; 4945 ring->ready = true; 4946 r = amdgpu_ring_test_ring(ring); 4947 if (r) 4948 ring->ready = false; 4949 } 4950 4951 done: 4952 return r; 4953 } 4954 4955 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) 4956 { 4957 int r; 4958 4959 if (!(adev->flags & AMD_IS_APU)) 4960 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 4961 4962 if (!adev->pp_enabled) { 4963 if (adev->firmware.load_type != AMDGPU_FW_LOAD_SMU) { 4964 /* legacy firmware loading */ 4965 r = gfx_v8_0_cp_gfx_load_microcode(adev); 4966 if (r) 4967 return r; 4968 4969 r = gfx_v8_0_cp_compute_load_microcode(adev); 4970 if (r) 4971 return r; 4972 } else { 4973 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4974 AMDGPU_UCODE_ID_CP_CE); 4975 if (r) 4976 return -EINVAL; 4977 4978 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4979 AMDGPU_UCODE_ID_CP_PFP); 4980 if (r) 4981 return -EINVAL; 4982 4983 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4984 AMDGPU_UCODE_ID_CP_ME); 4985 if (r) 4986 return -EINVAL; 4987 4988 if (adev->asic_type == CHIP_TOPAZ) { 4989 r = gfx_v8_0_cp_compute_load_microcode(adev); 4990 if (r) 4991 return r; 4992 } else { 4993 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 4994 AMDGPU_UCODE_ID_CP_MEC1); 4995 if (r) 4996 return -EINVAL; 4997 } 4998 } 4999 } 5000 5001 r = gfx_v8_0_cp_gfx_resume(adev); 5002 if (r) 5003 return r; 5004 5005 r = gfx_v8_0_kiq_resume(adev); 5006 if (r) 5007 return r; 5008 5009 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 5010 5011 return 0; 5012 } 5013 5014 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) 5015 { 5016 gfx_v8_0_cp_gfx_enable(adev, enable); 5017 gfx_v8_0_cp_compute_enable(adev, enable); 5018 } 5019 5020 static int gfx_v8_0_hw_init(void *handle) 5021 { 5022 int r; 5023 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5024 5025 gfx_v8_0_init_golden_registers(adev); 5026 gfx_v8_0_gpu_init(adev); 5027 5028 r = gfx_v8_0_rlc_resume(adev); 5029 if (r) 5030 return r; 5031 5032 r = gfx_v8_0_cp_resume(adev); 5033 5034 return r; 5035 } 5036 5037 static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) 5038 { 5039 struct amdgpu_device *adev = kiq_ring->adev; 5040 uint32_t scratch, tmp = 0; 5041 int r, i; 5042 5043 r = amdgpu_gfx_scratch_get(adev, &scratch); 5044 if (r) { 5045 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 5046 return r; 5047 } 5048 WREG32(scratch, 0xCAFEDEAD); 5049 5050 r = amdgpu_ring_alloc(kiq_ring, 10); 5051 if (r) { 5052 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 5053 amdgpu_gfx_scratch_free(adev, scratch); 5054 return r; 5055 } 5056 5057 /* unmap queues */ 5058 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 5059 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 5060 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 5061 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 5062 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 5063 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 5064 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 5065 amdgpu_ring_write(kiq_ring, 0); 5066 amdgpu_ring_write(kiq_ring, 0); 5067 amdgpu_ring_write(kiq_ring, 0); 5068 /* write to scratch for completion */ 5069 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 5070 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 5071 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 5072 amdgpu_ring_commit(kiq_ring); 5073 5074 for (i = 0; i < adev->usec_timeout; i++) { 5075 tmp = RREG32(scratch); 5076 if (tmp == 0xDEADBEEF) 5077 break; 5078 DRM_UDELAY(1); 5079 } 5080 if (i >= adev->usec_timeout) { 5081 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); 5082 r = -EINVAL; 5083 } 5084 amdgpu_gfx_scratch_free(adev, scratch); 5085 return r; 5086 } 5087 5088 static int gfx_v8_0_hw_fini(void *handle) 5089 { 5090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5091 int i; 5092 5093 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 5094 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 5095 5096 /* disable KCQ to avoid CPC touch memory not valid anymore */ 5097 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5098 gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); 5099 5100 if (amdgpu_sriov_vf(adev)) { 5101 pr_debug("For SRIOV client, shouldn't do anything.\n"); 5102 return 0; 5103 } 5104 gfx_v8_0_cp_enable(adev, false); 5105 gfx_v8_0_rlc_stop(adev); 5106 5107 amdgpu_set_powergating_state(adev, 5108 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); 5109 5110 return 0; 5111 } 5112 5113 static int gfx_v8_0_suspend(void *handle) 5114 { 5115 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5116 adev->gfx.in_suspend = true; 5117 return gfx_v8_0_hw_fini(adev); 5118 } 5119 5120 static int gfx_v8_0_resume(void *handle) 5121 { 5122 int r; 5123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5124 5125 r = gfx_v8_0_hw_init(adev); 5126 adev->gfx.in_suspend = false; 5127 return r; 5128 } 5129 5130 static bool gfx_v8_0_is_idle(void *handle) 5131 { 5132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5133 5134 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 5135 return false; 5136 else 5137 return true; 5138 } 5139 5140 static int gfx_v8_0_wait_for_idle(void *handle) 5141 { 5142 unsigned i; 5143 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5144 5145 for (i = 0; i < adev->usec_timeout; i++) { 5146 if (gfx_v8_0_is_idle(handle)) 5147 return 0; 5148 5149 udelay(1); 5150 } 5151 return -ETIMEDOUT; 5152 } 5153 5154 static bool gfx_v8_0_check_soft_reset(void *handle) 5155 { 5156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5157 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5158 u32 tmp; 5159 5160 /* GRBM_STATUS */ 5161 tmp = RREG32(mmGRBM_STATUS); 5162 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 5163 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 5164 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 5165 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 5166 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 5167 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK | 5168 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 5169 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 5170 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 5171 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 5172 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 5173 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 5174 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 5175 } 5176 5177 /* GRBM_STATUS2 */ 5178 tmp = RREG32(mmGRBM_STATUS2); 5179 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 5180 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 5181 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5182 5183 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) || 5184 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) || 5185 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) { 5186 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5187 SOFT_RESET_CPF, 1); 5188 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5189 SOFT_RESET_CPC, 1); 5190 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, 5191 SOFT_RESET_CPG, 1); 5192 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 5193 SOFT_RESET_GRBM, 1); 5194 } 5195 5196 /* SRBM_STATUS */ 5197 tmp = RREG32(mmSRBM_STATUS); 5198 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) 5199 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 5200 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 5201 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY)) 5202 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 5203 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1); 5204 5205 if (grbm_soft_reset || srbm_soft_reset) { 5206 adev->gfx.grbm_soft_reset = grbm_soft_reset; 5207 adev->gfx.srbm_soft_reset = srbm_soft_reset; 5208 return true; 5209 } else { 5210 adev->gfx.grbm_soft_reset = 0; 5211 adev->gfx.srbm_soft_reset = 0; 5212 return false; 5213 } 5214 } 5215 5216 static int gfx_v8_0_pre_soft_reset(void *handle) 5217 { 5218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5219 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5220 5221 if ((!adev->gfx.grbm_soft_reset) && 5222 (!adev->gfx.srbm_soft_reset)) 5223 return 0; 5224 5225 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5226 srbm_soft_reset = adev->gfx.srbm_soft_reset; 5227 5228 /* stop the rlc */ 5229 gfx_v8_0_rlc_stop(adev); 5230 5231 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5232 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) 5233 /* Disable GFX parsing/prefetching */ 5234 gfx_v8_0_cp_gfx_enable(adev, false); 5235 5236 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5237 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || 5238 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || 5239 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { 5240 int i; 5241 5242 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5243 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 5244 5245 mutex_lock(&adev->srbm_mutex); 5246 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5247 gfx_v8_0_deactivate_hqd(adev, 2); 5248 vi_srbm_select(adev, 0, 0, 0, 0); 5249 mutex_unlock(&adev->srbm_mutex); 5250 } 5251 /* Disable MEC parsing/prefetching */ 5252 gfx_v8_0_cp_compute_enable(adev, false); 5253 } 5254 5255 return 0; 5256 } 5257 5258 static int gfx_v8_0_soft_reset(void *handle) 5259 { 5260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5261 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5262 u32 tmp; 5263 5264 if ((!adev->gfx.grbm_soft_reset) && 5265 (!adev->gfx.srbm_soft_reset)) 5266 return 0; 5267 5268 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5269 srbm_soft_reset = adev->gfx.srbm_soft_reset; 5270 5271 if (grbm_soft_reset || srbm_soft_reset) { 5272 tmp = RREG32(mmGMCON_DEBUG); 5273 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1); 5274 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1); 5275 WREG32(mmGMCON_DEBUG, tmp); 5276 udelay(50); 5277 } 5278 5279 if (grbm_soft_reset) { 5280 tmp = RREG32(mmGRBM_SOFT_RESET); 5281 tmp |= grbm_soft_reset; 5282 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 5283 WREG32(mmGRBM_SOFT_RESET, tmp); 5284 tmp = RREG32(mmGRBM_SOFT_RESET); 5285 5286 udelay(50); 5287 5288 tmp &= ~grbm_soft_reset; 5289 WREG32(mmGRBM_SOFT_RESET, tmp); 5290 tmp = RREG32(mmGRBM_SOFT_RESET); 5291 } 5292 5293 if (srbm_soft_reset) { 5294 tmp = RREG32(mmSRBM_SOFT_RESET); 5295 tmp |= srbm_soft_reset; 5296 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 5297 WREG32(mmSRBM_SOFT_RESET, tmp); 5298 tmp = RREG32(mmSRBM_SOFT_RESET); 5299 5300 udelay(50); 5301 5302 tmp &= ~srbm_soft_reset; 5303 WREG32(mmSRBM_SOFT_RESET, tmp); 5304 tmp = RREG32(mmSRBM_SOFT_RESET); 5305 } 5306 5307 if (grbm_soft_reset || srbm_soft_reset) { 5308 tmp = RREG32(mmGMCON_DEBUG); 5309 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0); 5310 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0); 5311 WREG32(mmGMCON_DEBUG, tmp); 5312 } 5313 5314 /* Wait a little for things to settle down */ 5315 udelay(50); 5316 5317 return 0; 5318 } 5319 5320 static int gfx_v8_0_post_soft_reset(void *handle) 5321 { 5322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5323 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 5324 5325 if ((!adev->gfx.grbm_soft_reset) && 5326 (!adev->gfx.srbm_soft_reset)) 5327 return 0; 5328 5329 grbm_soft_reset = adev->gfx.grbm_soft_reset; 5330 srbm_soft_reset = adev->gfx.srbm_soft_reset; 5331 5332 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5333 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)) 5334 gfx_v8_0_cp_gfx_resume(adev); 5335 5336 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) || 5337 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) || 5338 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) || 5339 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) { 5340 int i; 5341 5342 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5343 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 5344 5345 mutex_lock(&adev->srbm_mutex); 5346 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 5347 gfx_v8_0_deactivate_hqd(adev, 2); 5348 vi_srbm_select(adev, 0, 0, 0, 0); 5349 mutex_unlock(&adev->srbm_mutex); 5350 } 5351 gfx_v8_0_kiq_resume(adev); 5352 } 5353 gfx_v8_0_rlc_start(adev); 5354 5355 return 0; 5356 } 5357 5358 /** 5359 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot 5360 * 5361 * @adev: amdgpu_device pointer 5362 * 5363 * Fetches a GPU clock counter snapshot. 5364 * Returns the 64 bit clock counter snapshot. 5365 */ 5366 static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) 5367 { 5368 uint64_t clock; 5369 5370 mutex_lock(&adev->gfx.gpu_clock_mutex); 5371 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 5372 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 5373 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 5374 mutex_unlock(&adev->gfx.gpu_clock_mutex); 5375 return clock; 5376 } 5377 5378 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 5379 uint32_t vmid, 5380 uint32_t gds_base, uint32_t gds_size, 5381 uint32_t gws_base, uint32_t gws_size, 5382 uint32_t oa_base, uint32_t oa_size) 5383 { 5384 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 5385 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 5386 5387 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 5388 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 5389 5390 oa_base = oa_base >> AMDGPU_OA_SHIFT; 5391 oa_size = oa_size >> AMDGPU_OA_SHIFT; 5392 5393 /* GDS Base */ 5394 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5395 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5396 WRITE_DATA_DST_SEL(0))); 5397 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 5398 amdgpu_ring_write(ring, 0); 5399 amdgpu_ring_write(ring, gds_base); 5400 5401 /* GDS Size */ 5402 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5403 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5404 WRITE_DATA_DST_SEL(0))); 5405 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 5406 amdgpu_ring_write(ring, 0); 5407 amdgpu_ring_write(ring, gds_size); 5408 5409 /* GWS */ 5410 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5411 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5412 WRITE_DATA_DST_SEL(0))); 5413 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 5414 amdgpu_ring_write(ring, 0); 5415 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 5416 5417 /* OA */ 5418 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5419 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5420 WRITE_DATA_DST_SEL(0))); 5421 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 5422 amdgpu_ring_write(ring, 0); 5423 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 5424 } 5425 5426 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 5427 { 5428 WREG32(mmSQ_IND_INDEX, 5429 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5430 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5431 (address << SQ_IND_INDEX__INDEX__SHIFT) | 5432 (SQ_IND_INDEX__FORCE_READ_MASK)); 5433 return RREG32(mmSQ_IND_DATA); 5434 } 5435 5436 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 5437 uint32_t wave, uint32_t thread, 5438 uint32_t regno, uint32_t num, uint32_t *out) 5439 { 5440 WREG32(mmSQ_IND_INDEX, 5441 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5442 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5443 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 5444 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 5445 (SQ_IND_INDEX__FORCE_READ_MASK) | 5446 (SQ_IND_INDEX__AUTO_INCR_MASK)); 5447 while (num--) 5448 *(out++) = RREG32(mmSQ_IND_DATA); 5449 } 5450 5451 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 5452 { 5453 /* type 0 wave data */ 5454 dst[(*no_fields)++] = 0; 5455 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 5456 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 5457 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 5458 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 5459 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 5460 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 5461 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 5462 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 5463 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 5464 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 5465 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 5466 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 5467 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 5468 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 5469 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 5470 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 5471 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 5472 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 5473 } 5474 5475 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 5476 uint32_t wave, uint32_t start, 5477 uint32_t size, uint32_t *dst) 5478 { 5479 wave_read_regs( 5480 adev, simd, wave, 0, 5481 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 5482 } 5483 5484 5485 static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { 5486 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, 5487 .select_se_sh = &gfx_v8_0_select_se_sh, 5488 .read_wave_data = &gfx_v8_0_read_wave_data, 5489 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs, 5490 }; 5491 5492 static int gfx_v8_0_early_init(void *handle) 5493 { 5494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5495 5496 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; 5497 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 5498 adev->gfx.funcs = &gfx_v8_0_gfx_funcs; 5499 gfx_v8_0_set_ring_funcs(adev); 5500 gfx_v8_0_set_irq_funcs(adev); 5501 gfx_v8_0_set_gds_init(adev); 5502 gfx_v8_0_set_rlc_funcs(adev); 5503 5504 return 0; 5505 } 5506 5507 static int gfx_v8_0_late_init(void *handle) 5508 { 5509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5510 int r; 5511 5512 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 5513 if (r) 5514 return r; 5515 5516 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 5517 if (r) 5518 return r; 5519 5520 /* requires IBs so do in late init after IB pool is initialized */ 5521 r = gfx_v8_0_do_edc_gpr_workarounds(adev); 5522 if (r) 5523 return r; 5524 5525 amdgpu_set_powergating_state(adev, 5526 AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); 5527 5528 return 0; 5529 } 5530 5531 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 5532 bool enable) 5533 { 5534 if ((adev->asic_type == CHIP_POLARIS11) || 5535 (adev->asic_type == CHIP_POLARIS12)) 5536 /* Send msg to SMU via Powerplay */ 5537 amdgpu_set_powergating_state(adev, 5538 AMD_IP_BLOCK_TYPE_SMC, 5539 enable ? 5540 AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); 5541 5542 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); 5543 } 5544 5545 static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 5546 bool enable) 5547 { 5548 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); 5549 } 5550 5551 static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, 5552 bool enable) 5553 { 5554 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); 5555 } 5556 5557 static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 5558 bool enable) 5559 { 5560 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); 5561 } 5562 5563 static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev, 5564 bool enable) 5565 { 5566 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); 5567 5568 /* Read any GFX register to wake up GFX. */ 5569 if (!enable) 5570 RREG32(mmDB_RENDER_CONTROL); 5571 } 5572 5573 static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev, 5574 bool enable) 5575 { 5576 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 5577 cz_enable_gfx_cg_power_gating(adev, true); 5578 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 5579 cz_enable_gfx_pipeline_power_gating(adev, true); 5580 } else { 5581 cz_enable_gfx_cg_power_gating(adev, false); 5582 cz_enable_gfx_pipeline_power_gating(adev, false); 5583 } 5584 } 5585 5586 static int gfx_v8_0_set_powergating_state(void *handle, 5587 enum amd_powergating_state state) 5588 { 5589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5590 bool enable = (state == AMD_PG_STATE_GATE); 5591 5592 if (amdgpu_sriov_vf(adev)) 5593 return 0; 5594 5595 switch (adev->asic_type) { 5596 case CHIP_CARRIZO: 5597 case CHIP_STONEY: 5598 5599 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5600 cz_enable_sck_slow_down_on_power_up(adev, true); 5601 cz_enable_sck_slow_down_on_power_down(adev, true); 5602 } else { 5603 cz_enable_sck_slow_down_on_power_up(adev, false); 5604 cz_enable_sck_slow_down_on_power_down(adev, false); 5605 } 5606 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5607 cz_enable_cp_power_gating(adev, true); 5608 else 5609 cz_enable_cp_power_gating(adev, false); 5610 5611 cz_update_gfx_cg_power_gating(adev, enable); 5612 5613 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5614 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); 5615 else 5616 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false); 5617 5618 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 5619 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true); 5620 else 5621 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false); 5622 break; 5623 case CHIP_POLARIS11: 5624 case CHIP_POLARIS12: 5625 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 5626 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true); 5627 else 5628 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false); 5629 5630 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 5631 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true); 5632 else 5633 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false); 5634 5635 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable) 5636 polaris11_enable_gfx_quick_mg_power_gating(adev, true); 5637 else 5638 polaris11_enable_gfx_quick_mg_power_gating(adev, false); 5639 break; 5640 default: 5641 break; 5642 } 5643 5644 return 0; 5645 } 5646 5647 static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags) 5648 { 5649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5650 int data; 5651 5652 if (amdgpu_sriov_vf(adev)) 5653 *flags = 0; 5654 5655 /* AMD_CG_SUPPORT_GFX_MGCG */ 5656 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5657 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK)) 5658 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5659 5660 /* AMD_CG_SUPPORT_GFX_CGLG */ 5661 data = RREG32(mmRLC_CGCG_CGLS_CTRL); 5662 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5663 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5664 5665 /* AMD_CG_SUPPORT_GFX_CGLS */ 5666 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5667 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5668 5669 /* AMD_CG_SUPPORT_GFX_CGTS */ 5670 data = RREG32(mmCGTS_SM_CTRL_REG); 5671 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK)) 5672 *flags |= AMD_CG_SUPPORT_GFX_CGTS; 5673 5674 /* AMD_CG_SUPPORT_GFX_CGTS_LS */ 5675 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK)) 5676 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS; 5677 5678 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5679 data = RREG32(mmRLC_MEM_SLP_CNTL); 5680 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5681 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5682 5683 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5684 data = RREG32(mmCP_MEM_SLP_CNTL); 5685 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5686 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5687 } 5688 5689 static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev, 5690 uint32_t reg_addr, uint32_t cmd) 5691 { 5692 uint32_t data; 5693 5694 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5695 5696 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 5697 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 5698 5699 data = RREG32(mmRLC_SERDES_WR_CTRL); 5700 if (adev->asic_type == CHIP_STONEY) 5701 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | 5702 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | 5703 RLC_SERDES_WR_CTRL__P1_SELECT_MASK | 5704 RLC_SERDES_WR_CTRL__P2_SELECT_MASK | 5705 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | 5706 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | 5707 RLC_SERDES_WR_CTRL__POWER_UP_MASK | 5708 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | 5709 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); 5710 else 5711 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | 5712 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | 5713 RLC_SERDES_WR_CTRL__P1_SELECT_MASK | 5714 RLC_SERDES_WR_CTRL__P2_SELECT_MASK | 5715 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | 5716 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | 5717 RLC_SERDES_WR_CTRL__POWER_UP_MASK | 5718 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | 5719 RLC_SERDES_WR_CTRL__BPM_DATA_MASK | 5720 RLC_SERDES_WR_CTRL__REG_ADDR_MASK | 5721 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); 5722 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK | 5723 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) | 5724 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) | 5725 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT)); 5726 5727 WREG32(mmRLC_SERDES_WR_CTRL, data); 5728 } 5729 5730 #define MSG_ENTER_RLC_SAFE_MODE 1 5731 #define MSG_EXIT_RLC_SAFE_MODE 0 5732 #define RLC_GPR_REG2__REQ_MASK 0x00000001 5733 #define RLC_GPR_REG2__REQ__SHIFT 0 5734 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001 5735 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e 5736 5737 static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev) 5738 { 5739 u32 data; 5740 unsigned i; 5741 5742 data = RREG32(mmRLC_CNTL); 5743 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) 5744 return; 5745 5746 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 5747 data |= RLC_SAFE_MODE__CMD_MASK; 5748 data &= ~RLC_SAFE_MODE__MESSAGE_MASK; 5749 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 5750 WREG32(mmRLC_SAFE_MODE, data); 5751 5752 for (i = 0; i < adev->usec_timeout; i++) { 5753 if ((RREG32(mmRLC_GPM_STAT) & 5754 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | 5755 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) == 5756 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK | 5757 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) 5758 break; 5759 udelay(1); 5760 } 5761 5762 for (i = 0; i < adev->usec_timeout; i++) { 5763 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 5764 break; 5765 udelay(1); 5766 } 5767 adev->gfx.rlc.in_safe_mode = true; 5768 } 5769 } 5770 5771 static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev) 5772 { 5773 u32 data = 0; 5774 unsigned i; 5775 5776 data = RREG32(mmRLC_CNTL); 5777 if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK)) 5778 return; 5779 5780 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 5781 if (adev->gfx.rlc.in_safe_mode) { 5782 data |= RLC_SAFE_MODE__CMD_MASK; 5783 data &= ~RLC_SAFE_MODE__MESSAGE_MASK; 5784 WREG32(mmRLC_SAFE_MODE, data); 5785 adev->gfx.rlc.in_safe_mode = false; 5786 } 5787 } 5788 5789 for (i = 0; i < adev->usec_timeout; i++) { 5790 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 5791 break; 5792 udelay(1); 5793 } 5794 } 5795 5796 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = { 5797 .enter_safe_mode = iceland_enter_rlc_safe_mode, 5798 .exit_safe_mode = iceland_exit_rlc_safe_mode 5799 }; 5800 5801 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 5802 bool enable) 5803 { 5804 uint32_t temp, data; 5805 5806 adev->gfx.rlc.funcs->enter_safe_mode(adev); 5807 5808 /* It is disabled by HW by default */ 5809 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 5810 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 5811 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) 5812 /* 1 - RLC memory Light sleep */ 5813 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1); 5814 5815 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) 5816 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1); 5817 } 5818 5819 /* 3 - RLC_CGTT_MGCG_OVERRIDE */ 5820 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5821 if (adev->flags & AMD_IS_APU) 5822 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5823 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5824 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK); 5825 else 5826 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5827 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5828 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | 5829 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); 5830 5831 if (temp != data) 5832 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 5833 5834 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5835 gfx_v8_0_wait_for_rlc_serdes(adev); 5836 5837 /* 5 - clear mgcg override */ 5838 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD); 5839 5840 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 5841 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */ 5842 temp = data = RREG32(mmCGTS_SM_CTRL_REG); 5843 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK); 5844 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 5845 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 5846 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 5847 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 5848 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 5849 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 5850 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 5851 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 5852 if (temp != data) 5853 WREG32(mmCGTS_SM_CTRL_REG, data); 5854 } 5855 udelay(50); 5856 5857 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5858 gfx_v8_0_wait_for_rlc_serdes(adev); 5859 } else { 5860 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */ 5861 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5862 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK | 5863 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK | 5864 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK | 5865 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK); 5866 if (temp != data) 5867 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 5868 5869 /* 2 - disable MGLS in RLC */ 5870 data = RREG32(mmRLC_MEM_SLP_CNTL); 5871 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 5872 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 5873 WREG32(mmRLC_MEM_SLP_CNTL, data); 5874 } 5875 5876 /* 3 - disable MGLS in CP */ 5877 data = RREG32(mmCP_MEM_SLP_CNTL); 5878 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 5879 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 5880 WREG32(mmCP_MEM_SLP_CNTL, data); 5881 } 5882 5883 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */ 5884 temp = data = RREG32(mmCGTS_SM_CTRL_REG); 5885 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK | 5886 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK); 5887 if (temp != data) 5888 WREG32(mmCGTS_SM_CTRL_REG, data); 5889 5890 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5891 gfx_v8_0_wait_for_rlc_serdes(adev); 5892 5893 /* 6 - set mgcg override */ 5894 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD); 5895 5896 udelay(50); 5897 5898 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5899 gfx_v8_0_wait_for_rlc_serdes(adev); 5900 } 5901 5902 adev->gfx.rlc.funcs->exit_safe_mode(adev); 5903 } 5904 5905 static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 5906 bool enable) 5907 { 5908 uint32_t temp, temp1, data, data1; 5909 5910 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 5911 5912 adev->gfx.rlc.funcs->enter_safe_mode(adev); 5913 5914 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 5915 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5916 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK; 5917 if (temp1 != data1) 5918 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5919 5920 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5921 gfx_v8_0_wait_for_rlc_serdes(adev); 5922 5923 /* 2 - clear cgcg override */ 5924 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); 5925 5926 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5927 gfx_v8_0_wait_for_rlc_serdes(adev); 5928 5929 /* 3 - write cmd to set CGLS */ 5930 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); 5931 5932 /* 4 - enable cgcg */ 5933 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5934 5935 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5936 /* enable cgls*/ 5937 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5938 5939 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5940 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK; 5941 5942 if (temp1 != data1) 5943 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5944 } else { 5945 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 5946 } 5947 5948 if (temp != data) 5949 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 5950 5951 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/ 5952 * Cmp_busy/GFX_Idle interrupts 5953 */ 5954 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 5955 } else { 5956 /* disable cntx_empty_int_enable & GFX Idle interrupt */ 5957 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 5958 5959 /* TEST CGCG */ 5960 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5961 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK | 5962 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK); 5963 if (temp1 != data1) 5964 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5965 5966 /* read gfx register to wake up cgcg */ 5967 RREG32(mmCB_CGTT_SCLK_CTRL); 5968 RREG32(mmCB_CGTT_SCLK_CTRL); 5969 RREG32(mmCB_CGTT_SCLK_CTRL); 5970 RREG32(mmCB_CGTT_SCLK_CTRL); 5971 5972 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5973 gfx_v8_0_wait_for_rlc_serdes(adev); 5974 5975 /* write cmd to Set CGCG Overrride */ 5976 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD); 5977 5978 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5979 gfx_v8_0_wait_for_rlc_serdes(adev); 5980 5981 /* write cmd to Clear CGLS */ 5982 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD); 5983 5984 /* disable cgcg, cgls should be disabled too. */ 5985 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | 5986 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 5987 if (temp != data) 5988 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 5989 /* enable interrupts again for PG */ 5990 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 5991 } 5992 5993 gfx_v8_0_wait_for_rlc_serdes(adev); 5994 5995 adev->gfx.rlc.funcs->exit_safe_mode(adev); 5996 } 5997 static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev, 5998 bool enable) 5999 { 6000 if (enable) { 6001 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS) 6002 * === MGCG + MGLS + TS(CG/LS) === 6003 */ 6004 gfx_v8_0_update_medium_grain_clock_gating(adev, enable); 6005 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); 6006 } else { 6007 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS) 6008 * === CGCG + CGLS === 6009 */ 6010 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable); 6011 gfx_v8_0_update_medium_grain_clock_gating(adev, enable); 6012 } 6013 return 0; 6014 } 6015 6016 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 6017 enum amd_clockgating_state state) 6018 { 6019 uint32_t msg_id, pp_state = 0; 6020 uint32_t pp_support_state = 0; 6021 void *pp_handle = adev->powerplay.pp_handle; 6022 6023 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 6024 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 6025 pp_support_state = PP_STATE_SUPPORT_LS; 6026 pp_state = PP_STATE_LS; 6027 } 6028 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 6029 pp_support_state |= PP_STATE_SUPPORT_CG; 6030 pp_state |= PP_STATE_CG; 6031 } 6032 if (state == AMD_CG_STATE_UNGATE) 6033 pp_state = 0; 6034 6035 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6036 PP_BLOCK_GFX_CG, 6037 pp_support_state, 6038 pp_state); 6039 amd_set_clockgating_by_smu(pp_handle, msg_id); 6040 } 6041 6042 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 6043 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 6044 pp_support_state = PP_STATE_SUPPORT_LS; 6045 pp_state = PP_STATE_LS; 6046 } 6047 6048 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 6049 pp_support_state |= PP_STATE_SUPPORT_CG; 6050 pp_state |= PP_STATE_CG; 6051 } 6052 6053 if (state == AMD_CG_STATE_UNGATE) 6054 pp_state = 0; 6055 6056 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6057 PP_BLOCK_GFX_MG, 6058 pp_support_state, 6059 pp_state); 6060 amd_set_clockgating_by_smu(pp_handle, msg_id); 6061 } 6062 6063 return 0; 6064 } 6065 6066 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 6067 enum amd_clockgating_state state) 6068 { 6069 6070 uint32_t msg_id, pp_state = 0; 6071 uint32_t pp_support_state = 0; 6072 void *pp_handle = adev->powerplay.pp_handle; 6073 6074 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) { 6075 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 6076 pp_support_state = PP_STATE_SUPPORT_LS; 6077 pp_state = PP_STATE_LS; 6078 } 6079 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 6080 pp_support_state |= PP_STATE_SUPPORT_CG; 6081 pp_state |= PP_STATE_CG; 6082 } 6083 if (state == AMD_CG_STATE_UNGATE) 6084 pp_state = 0; 6085 6086 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6087 PP_BLOCK_GFX_CG, 6088 pp_support_state, 6089 pp_state); 6090 amd_set_clockgating_by_smu(pp_handle, msg_id); 6091 } 6092 6093 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) { 6094 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) { 6095 pp_support_state = PP_STATE_SUPPORT_LS; 6096 pp_state = PP_STATE_LS; 6097 } 6098 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) { 6099 pp_support_state |= PP_STATE_SUPPORT_CG; 6100 pp_state |= PP_STATE_CG; 6101 } 6102 if (state == AMD_CG_STATE_UNGATE) 6103 pp_state = 0; 6104 6105 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6106 PP_BLOCK_GFX_3D, 6107 pp_support_state, 6108 pp_state); 6109 amd_set_clockgating_by_smu(pp_handle, msg_id); 6110 } 6111 6112 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) { 6113 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 6114 pp_support_state = PP_STATE_SUPPORT_LS; 6115 pp_state = PP_STATE_LS; 6116 } 6117 6118 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { 6119 pp_support_state |= PP_STATE_SUPPORT_CG; 6120 pp_state |= PP_STATE_CG; 6121 } 6122 6123 if (state == AMD_CG_STATE_UNGATE) 6124 pp_state = 0; 6125 6126 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6127 PP_BLOCK_GFX_MG, 6128 pp_support_state, 6129 pp_state); 6130 amd_set_clockgating_by_smu(pp_handle, msg_id); 6131 } 6132 6133 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 6134 pp_support_state = PP_STATE_SUPPORT_LS; 6135 6136 if (state == AMD_CG_STATE_UNGATE) 6137 pp_state = 0; 6138 else 6139 pp_state = PP_STATE_LS; 6140 6141 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6142 PP_BLOCK_GFX_RLC, 6143 pp_support_state, 6144 pp_state); 6145 amd_set_clockgating_by_smu(pp_handle, msg_id); 6146 } 6147 6148 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 6149 pp_support_state = PP_STATE_SUPPORT_LS; 6150 6151 if (state == AMD_CG_STATE_UNGATE) 6152 pp_state = 0; 6153 else 6154 pp_state = PP_STATE_LS; 6155 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6156 PP_BLOCK_GFX_CP, 6157 pp_support_state, 6158 pp_state); 6159 amd_set_clockgating_by_smu(pp_handle, msg_id); 6160 } 6161 6162 return 0; 6163 } 6164 6165 static int gfx_v8_0_set_clockgating_state(void *handle, 6166 enum amd_clockgating_state state) 6167 { 6168 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6169 6170 if (amdgpu_sriov_vf(adev)) 6171 return 0; 6172 6173 switch (adev->asic_type) { 6174 case CHIP_FIJI: 6175 case CHIP_CARRIZO: 6176 case CHIP_STONEY: 6177 gfx_v8_0_update_gfx_clock_gating(adev, 6178 state == AMD_CG_STATE_GATE); 6179 break; 6180 case CHIP_TONGA: 6181 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state); 6182 break; 6183 case CHIP_POLARIS10: 6184 case CHIP_POLARIS11: 6185 case CHIP_POLARIS12: 6186 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state); 6187 break; 6188 default: 6189 break; 6190 } 6191 return 0; 6192 } 6193 6194 static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring) 6195 { 6196 return ring->adev->wb.wb[ring->rptr_offs]; 6197 } 6198 6199 static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 6200 { 6201 struct amdgpu_device *adev = ring->adev; 6202 6203 if (ring->use_doorbell) 6204 /* XXX check if swapping is necessary on BE */ 6205 return ring->adev->wb.wb[ring->wptr_offs]; 6206 else 6207 return RREG32(mmCP_RB0_WPTR); 6208 } 6209 6210 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 6211 { 6212 struct amdgpu_device *adev = ring->adev; 6213 6214 if (ring->use_doorbell) { 6215 /* XXX check if swapping is necessary on BE */ 6216 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 6217 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 6218 } else { 6219 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6220 (void)RREG32(mmCP_RB0_WPTR); 6221 } 6222 } 6223 6224 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 6225 { 6226 u32 ref_and_mask, reg_mem_engine; 6227 6228 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || 6229 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { 6230 switch (ring->me) { 6231 case 1: 6232 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 6233 break; 6234 case 2: 6235 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 6236 break; 6237 default: 6238 return; 6239 } 6240 reg_mem_engine = 0; 6241 } else { 6242 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 6243 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ 6244 } 6245 6246 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6247 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 6248 WAIT_REG_MEM_FUNCTION(3) | /* == */ 6249 reg_mem_engine)); 6250 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 6251 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 6252 amdgpu_ring_write(ring, ref_and_mask); 6253 amdgpu_ring_write(ring, ref_and_mask); 6254 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6255 } 6256 6257 static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 6258 { 6259 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 6260 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 6261 EVENT_INDEX(4)); 6262 6263 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 6264 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 6265 EVENT_INDEX(0)); 6266 } 6267 6268 6269 static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 6270 { 6271 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6272 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6273 WRITE_DATA_DST_SEL(0) | 6274 WR_CONFIRM)); 6275 amdgpu_ring_write(ring, mmHDP_DEBUG0); 6276 amdgpu_ring_write(ring, 0); 6277 amdgpu_ring_write(ring, 1); 6278 6279 } 6280 6281 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 6282 struct amdgpu_ib *ib, 6283 unsigned vm_id, bool ctx_switch) 6284 { 6285 u32 header, control = 0; 6286 6287 if (ib->flags & AMDGPU_IB_FLAG_CE) 6288 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 6289 else 6290 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 6291 6292 control |= ib->length_dw | (vm_id << 24); 6293 6294 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 6295 control |= INDIRECT_BUFFER_PRE_ENB(1); 6296 6297 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 6298 gfx_v8_0_ring_emit_de_meta(ring); 6299 } 6300 6301 amdgpu_ring_write(ring, header); 6302 amdgpu_ring_write(ring, 6303 #ifdef __BIG_ENDIAN 6304 (2 << 0) | 6305 #endif 6306 (ib->gpu_addr & 0xFFFFFFFC)); 6307 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 6308 amdgpu_ring_write(ring, control); 6309 } 6310 6311 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 6312 struct amdgpu_ib *ib, 6313 unsigned vm_id, bool ctx_switch) 6314 { 6315 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 6316 6317 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 6318 amdgpu_ring_write(ring, 6319 #ifdef __BIG_ENDIAN 6320 (2 << 0) | 6321 #endif 6322 (ib->gpu_addr & 0xFFFFFFFC)); 6323 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 6324 amdgpu_ring_write(ring, control); 6325 } 6326 6327 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 6328 u64 seq, unsigned flags) 6329 { 6330 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 6331 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 6332 6333 /* EVENT_WRITE_EOP - flush caches, send int */ 6334 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 6335 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 6336 EOP_TC_ACTION_EN | 6337 EOP_TC_WB_ACTION_EN | 6338 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6339 EVENT_INDEX(5))); 6340 amdgpu_ring_write(ring, addr & 0xfffffffc); 6341 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 6342 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 6343 amdgpu_ring_write(ring, lower_32_bits(seq)); 6344 amdgpu_ring_write(ring, upper_32_bits(seq)); 6345 6346 } 6347 6348 static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 6349 { 6350 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6351 uint32_t seq = ring->fence_drv.sync_seq; 6352 uint64_t addr = ring->fence_drv.gpu_addr; 6353 6354 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6355 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 6356 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 6357 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 6358 amdgpu_ring_write(ring, addr & 0xfffffffc); 6359 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 6360 amdgpu_ring_write(ring, seq); 6361 amdgpu_ring_write(ring, 0xffffffff); 6362 amdgpu_ring_write(ring, 4); /* poll interval */ 6363 } 6364 6365 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 6366 unsigned vm_id, uint64_t pd_addr) 6367 { 6368 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 6369 6370 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6371 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 6372 WRITE_DATA_DST_SEL(0)) | 6373 WR_CONFIRM); 6374 if (vm_id < 8) { 6375 amdgpu_ring_write(ring, 6376 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 6377 } else { 6378 amdgpu_ring_write(ring, 6379 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 6380 } 6381 amdgpu_ring_write(ring, 0); 6382 amdgpu_ring_write(ring, pd_addr >> 12); 6383 6384 /* bits 0-15 are the VM contexts0-15 */ 6385 /* invalidate the cache */ 6386 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6387 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6388 WRITE_DATA_DST_SEL(0))); 6389 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 6390 amdgpu_ring_write(ring, 0); 6391 amdgpu_ring_write(ring, 1 << vm_id); 6392 6393 /* wait for the invalidate to complete */ 6394 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 6395 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 6396 WAIT_REG_MEM_FUNCTION(0) | /* always */ 6397 WAIT_REG_MEM_ENGINE(0))); /* me */ 6398 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 6399 amdgpu_ring_write(ring, 0); 6400 amdgpu_ring_write(ring, 0); /* ref */ 6401 amdgpu_ring_write(ring, 0); /* mask */ 6402 amdgpu_ring_write(ring, 0x20); /* poll interval */ 6403 6404 /* compute doesn't have PFP */ 6405 if (usepfp) { 6406 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 6407 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 6408 amdgpu_ring_write(ring, 0x0); 6409 } 6410 } 6411 6412 static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 6413 { 6414 return ring->adev->wb.wb[ring->wptr_offs]; 6415 } 6416 6417 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 6418 { 6419 struct amdgpu_device *adev = ring->adev; 6420 6421 /* XXX check if swapping is necessary on BE */ 6422 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 6423 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 6424 } 6425 6426 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 6427 u64 addr, u64 seq, 6428 unsigned flags) 6429 { 6430 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 6431 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 6432 6433 /* RELEASE_MEM - flush caches, send int */ 6434 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 6435 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 6436 EOP_TC_ACTION_EN | 6437 EOP_TC_WB_ACTION_EN | 6438 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 6439 EVENT_INDEX(5))); 6440 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 6441 amdgpu_ring_write(ring, addr & 0xfffffffc); 6442 amdgpu_ring_write(ring, upper_32_bits(addr)); 6443 amdgpu_ring_write(ring, lower_32_bits(seq)); 6444 amdgpu_ring_write(ring, upper_32_bits(seq)); 6445 } 6446 6447 static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 6448 u64 seq, unsigned int flags) 6449 { 6450 /* we only allocate 32bit for each seq wb address */ 6451 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 6452 6453 /* write fence seq to the "addr" */ 6454 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6455 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6456 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 6457 amdgpu_ring_write(ring, lower_32_bits(addr)); 6458 amdgpu_ring_write(ring, upper_32_bits(addr)); 6459 amdgpu_ring_write(ring, lower_32_bits(seq)); 6460 6461 if (flags & AMDGPU_FENCE_FLAG_INT) { 6462 /* set register to trigger INT */ 6463 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6464 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 6465 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 6466 amdgpu_ring_write(ring, mmCPC_INT_STATUS); 6467 amdgpu_ring_write(ring, 0); 6468 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 6469 } 6470 } 6471 6472 static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring) 6473 { 6474 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 6475 amdgpu_ring_write(ring, 0); 6476 } 6477 6478 static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 6479 { 6480 uint32_t dw2 = 0; 6481 6482 if (amdgpu_sriov_vf(ring->adev)) 6483 gfx_v8_0_ring_emit_ce_meta(ring); 6484 6485 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 6486 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 6487 gfx_v8_0_ring_emit_vgt_flush(ring); 6488 /* set load_global_config & load_global_uconfig */ 6489 dw2 |= 0x8001; 6490 /* set load_cs_sh_regs */ 6491 dw2 |= 0x01000000; 6492 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 6493 dw2 |= 0x10002; 6494 6495 /* set load_ce_ram if preamble presented */ 6496 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 6497 dw2 |= 0x10000000; 6498 } else { 6499 /* still load_ce_ram if this is the first time preamble presented 6500 * although there is no context switch happens. 6501 */ 6502 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 6503 dw2 |= 0x10000000; 6504 } 6505 6506 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6507 amdgpu_ring_write(ring, dw2); 6508 amdgpu_ring_write(ring, 0); 6509 } 6510 6511 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 6512 { 6513 unsigned ret; 6514 6515 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 6516 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 6517 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 6518 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 6519 ret = ring->wptr & ring->buf_mask; 6520 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 6521 return ret; 6522 } 6523 6524 static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 6525 { 6526 unsigned cur; 6527 6528 BUG_ON(offset > ring->buf_mask); 6529 BUG_ON(ring->ring[offset] != 0x55aa55aa); 6530 6531 cur = (ring->wptr & ring->buf_mask) - 1; 6532 if (likely(cur > offset)) 6533 ring->ring[offset] = cur - offset; 6534 else 6535 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur; 6536 } 6537 6538 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 6539 { 6540 struct amdgpu_device *adev = ring->adev; 6541 6542 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 6543 amdgpu_ring_write(ring, 0 | /* src: register*/ 6544 (5 << 8) | /* dst: memory */ 6545 (1 << 20)); /* write confirm */ 6546 amdgpu_ring_write(ring, reg); 6547 amdgpu_ring_write(ring, 0); 6548 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 6549 adev->virt.reg_val_offs * 4)); 6550 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 6551 adev->virt.reg_val_offs * 4)); 6552 } 6553 6554 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 6555 uint32_t val) 6556 { 6557 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 6558 amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */ 6559 amdgpu_ring_write(ring, reg); 6560 amdgpu_ring_write(ring, 0); 6561 amdgpu_ring_write(ring, val); 6562 } 6563 6564 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 6565 enum amdgpu_interrupt_state state) 6566 { 6567 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, 6568 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6569 } 6570 6571 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 6572 int me, int pipe, 6573 enum amdgpu_interrupt_state state) 6574 { 6575 u32 mec_int_cntl, mec_int_cntl_reg; 6576 6577 /* 6578 * amdgpu controls only the first MEC. That's why this function only 6579 * handles the setting of interrupts for this specific MEC. All other 6580 * pipes' interrupts are set by amdkfd. 6581 */ 6582 6583 if (me == 1) { 6584 switch (pipe) { 6585 case 0: 6586 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 6587 break; 6588 case 1: 6589 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 6590 break; 6591 case 2: 6592 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 6593 break; 6594 case 3: 6595 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 6596 break; 6597 default: 6598 DRM_DEBUG("invalid pipe %d\n", pipe); 6599 return; 6600 } 6601 } else { 6602 DRM_DEBUG("invalid me %d\n", me); 6603 return; 6604 } 6605 6606 switch (state) { 6607 case AMDGPU_IRQ_STATE_DISABLE: 6608 mec_int_cntl = RREG32(mec_int_cntl_reg); 6609 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6610 WREG32(mec_int_cntl_reg, mec_int_cntl); 6611 break; 6612 case AMDGPU_IRQ_STATE_ENABLE: 6613 mec_int_cntl = RREG32(mec_int_cntl_reg); 6614 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 6615 WREG32(mec_int_cntl_reg, mec_int_cntl); 6616 break; 6617 default: 6618 break; 6619 } 6620 } 6621 6622 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 6623 struct amdgpu_irq_src *source, 6624 unsigned type, 6625 enum amdgpu_interrupt_state state) 6626 { 6627 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, 6628 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6629 6630 return 0; 6631 } 6632 6633 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 6634 struct amdgpu_irq_src *source, 6635 unsigned type, 6636 enum amdgpu_interrupt_state state) 6637 { 6638 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, 6639 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6640 6641 return 0; 6642 } 6643 6644 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, 6645 struct amdgpu_irq_src *src, 6646 unsigned type, 6647 enum amdgpu_interrupt_state state) 6648 { 6649 switch (type) { 6650 case AMDGPU_CP_IRQ_GFX_EOP: 6651 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); 6652 break; 6653 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 6654 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 6655 break; 6656 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 6657 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 6658 break; 6659 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 6660 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 6661 break; 6662 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 6663 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 6664 break; 6665 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 6666 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 6667 break; 6668 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 6669 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 6670 break; 6671 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 6672 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 6673 break; 6674 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 6675 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 6676 break; 6677 default: 6678 break; 6679 } 6680 return 0; 6681 } 6682 6683 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, 6684 struct amdgpu_irq_src *source, 6685 struct amdgpu_iv_entry *entry) 6686 { 6687 int i; 6688 u8 me_id, pipe_id, queue_id; 6689 struct amdgpu_ring *ring; 6690 6691 DRM_DEBUG("IH: CP EOP\n"); 6692 me_id = (entry->ring_id & 0x0c) >> 2; 6693 pipe_id = (entry->ring_id & 0x03) >> 0; 6694 queue_id = (entry->ring_id & 0x70) >> 4; 6695 6696 switch (me_id) { 6697 case 0: 6698 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 6699 break; 6700 case 1: 6701 case 2: 6702 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6703 ring = &adev->gfx.compute_ring[i]; 6704 /* Per-queue interrupt is supported for MEC starting from VI. 6705 * The interrupt can only be enabled/disabled per pipe instead of per queue. 6706 */ 6707 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 6708 amdgpu_fence_process(ring); 6709 } 6710 break; 6711 } 6712 return 0; 6713 } 6714 6715 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, 6716 struct amdgpu_irq_src *source, 6717 struct amdgpu_iv_entry *entry) 6718 { 6719 DRM_ERROR("Illegal register access in command stream\n"); 6720 schedule_work(&adev->reset_work); 6721 return 0; 6722 } 6723 6724 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, 6725 struct amdgpu_irq_src *source, 6726 struct amdgpu_iv_entry *entry) 6727 { 6728 DRM_ERROR("Illegal instruction in command stream\n"); 6729 schedule_work(&adev->reset_work); 6730 return 0; 6731 } 6732 6733 static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 6734 struct amdgpu_irq_src *src, 6735 unsigned int type, 6736 enum amdgpu_interrupt_state state) 6737 { 6738 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6739 6740 switch (type) { 6741 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 6742 WREG32_FIELD(CPC_INT_CNTL, GENERIC2_INT_ENABLE, 6743 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6744 if (ring->me == 1) 6745 WREG32_FIELD_OFFSET(CP_ME1_PIPE0_INT_CNTL, 6746 ring->pipe, 6747 GENERIC2_INT_ENABLE, 6748 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6749 else 6750 WREG32_FIELD_OFFSET(CP_ME2_PIPE0_INT_CNTL, 6751 ring->pipe, 6752 GENERIC2_INT_ENABLE, 6753 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); 6754 break; 6755 default: 6756 BUG(); /* kiq only support GENERIC2_INT now */ 6757 break; 6758 } 6759 return 0; 6760 } 6761 6762 static int gfx_v8_0_kiq_irq(struct amdgpu_device *adev, 6763 struct amdgpu_irq_src *source, 6764 struct amdgpu_iv_entry *entry) 6765 { 6766 u8 me_id, pipe_id, queue_id; 6767 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 6768 6769 me_id = (entry->ring_id & 0x0c) >> 2; 6770 pipe_id = (entry->ring_id & 0x03) >> 0; 6771 queue_id = (entry->ring_id & 0x70) >> 4; 6772 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 6773 me_id, pipe_id, queue_id); 6774 6775 amdgpu_fence_process(ring); 6776 return 0; 6777 } 6778 6779 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { 6780 .name = "gfx_v8_0", 6781 .early_init = gfx_v8_0_early_init, 6782 .late_init = gfx_v8_0_late_init, 6783 .sw_init = gfx_v8_0_sw_init, 6784 .sw_fini = gfx_v8_0_sw_fini, 6785 .hw_init = gfx_v8_0_hw_init, 6786 .hw_fini = gfx_v8_0_hw_fini, 6787 .suspend = gfx_v8_0_suspend, 6788 .resume = gfx_v8_0_resume, 6789 .is_idle = gfx_v8_0_is_idle, 6790 .wait_for_idle = gfx_v8_0_wait_for_idle, 6791 .check_soft_reset = gfx_v8_0_check_soft_reset, 6792 .pre_soft_reset = gfx_v8_0_pre_soft_reset, 6793 .soft_reset = gfx_v8_0_soft_reset, 6794 .post_soft_reset = gfx_v8_0_post_soft_reset, 6795 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 6796 .set_powergating_state = gfx_v8_0_set_powergating_state, 6797 .get_clockgating_state = gfx_v8_0_get_clockgating_state, 6798 }; 6799 6800 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 6801 .type = AMDGPU_RING_TYPE_GFX, 6802 .align_mask = 0xff, 6803 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6804 .support_64bit_ptrs = false, 6805 .get_rptr = gfx_v8_0_ring_get_rptr, 6806 .get_wptr = gfx_v8_0_ring_get_wptr_gfx, 6807 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 6808 .emit_frame_size = /* maximum 215dw if count 16 IBs in */ 6809 5 + /* COND_EXEC */ 6810 7 + /* PIPELINE_SYNC */ 6811 19 + /* VM_FLUSH */ 6812 8 + /* FENCE for VM_FLUSH */ 6813 20 + /* GDS switch */ 6814 4 + /* double SWITCH_BUFFER, 6815 the first COND_EXEC jump to the place just 6816 prior to this double SWITCH_BUFFER */ 6817 5 + /* COND_EXEC */ 6818 7 + /* HDP_flush */ 6819 4 + /* VGT_flush */ 6820 14 + /* CE_META */ 6821 31 + /* DE_META */ 6822 3 + /* CNTX_CTRL */ 6823 5 + /* HDP_INVL */ 6824 8 + 8 + /* FENCE x2 */ 6825 2, /* SWITCH_BUFFER */ 6826 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ 6827 .emit_ib = gfx_v8_0_ring_emit_ib_gfx, 6828 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 6829 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, 6830 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 6831 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 6832 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 6833 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, 6834 .test_ring = gfx_v8_0_ring_test_ring, 6835 .test_ib = gfx_v8_0_ring_test_ib, 6836 .insert_nop = amdgpu_ring_insert_nop, 6837 .pad_ib = amdgpu_ring_generic_pad_ib, 6838 .emit_switch_buffer = gfx_v8_ring_emit_sb, 6839 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, 6840 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec, 6841 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec, 6842 }; 6843 6844 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 6845 .type = AMDGPU_RING_TYPE_COMPUTE, 6846 .align_mask = 0xff, 6847 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6848 .support_64bit_ptrs = false, 6849 .get_rptr = gfx_v8_0_ring_get_rptr, 6850 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 6851 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 6852 .emit_frame_size = 6853 20 + /* gfx_v8_0_ring_emit_gds_switch */ 6854 7 + /* gfx_v8_0_ring_emit_hdp_flush */ 6855 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ 6856 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 6857 17 + /* gfx_v8_0_ring_emit_vm_flush */ 6858 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ 6859 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */ 6860 .emit_ib = gfx_v8_0_ring_emit_ib_compute, 6861 .emit_fence = gfx_v8_0_ring_emit_fence_compute, 6862 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, 6863 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 6864 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 6865 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 6866 .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, 6867 .test_ring = gfx_v8_0_ring_test_ring, 6868 .test_ib = gfx_v8_0_ring_test_ib, 6869 .insert_nop = amdgpu_ring_insert_nop, 6870 .pad_ib = amdgpu_ring_generic_pad_ib, 6871 }; 6872 6873 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { 6874 .type = AMDGPU_RING_TYPE_KIQ, 6875 .align_mask = 0xff, 6876 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6877 .support_64bit_ptrs = false, 6878 .get_rptr = gfx_v8_0_ring_get_rptr, 6879 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 6880 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 6881 .emit_frame_size = 6882 20 + /* gfx_v8_0_ring_emit_gds_switch */ 6883 7 + /* gfx_v8_0_ring_emit_hdp_flush */ 6884 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ 6885 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ 6886 17 + /* gfx_v8_0_ring_emit_vm_flush */ 6887 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6888 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */ 6889 .emit_ib = gfx_v8_0_ring_emit_ib_compute, 6890 .emit_fence = gfx_v8_0_ring_emit_fence_kiq, 6891 .test_ring = gfx_v8_0_ring_test_ring, 6892 .test_ib = gfx_v8_0_ring_test_ib, 6893 .insert_nop = amdgpu_ring_insert_nop, 6894 .pad_ib = amdgpu_ring_generic_pad_ib, 6895 .emit_rreg = gfx_v8_0_ring_emit_rreg, 6896 .emit_wreg = gfx_v8_0_ring_emit_wreg, 6897 }; 6898 6899 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) 6900 { 6901 int i; 6902 6903 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq; 6904 6905 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6906 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; 6907 6908 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6909 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; 6910 } 6911 6912 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { 6913 .set = gfx_v8_0_set_eop_interrupt_state, 6914 .process = gfx_v8_0_eop_irq, 6915 }; 6916 6917 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { 6918 .set = gfx_v8_0_set_priv_reg_fault_state, 6919 .process = gfx_v8_0_priv_reg_irq, 6920 }; 6921 6922 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { 6923 .set = gfx_v8_0_set_priv_inst_fault_state, 6924 .process = gfx_v8_0_priv_inst_irq, 6925 }; 6926 6927 static const struct amdgpu_irq_src_funcs gfx_v8_0_kiq_irq_funcs = { 6928 .set = gfx_v8_0_kiq_set_interrupt_state, 6929 .process = gfx_v8_0_kiq_irq, 6930 }; 6931 6932 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) 6933 { 6934 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6935 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; 6936 6937 adev->gfx.priv_reg_irq.num_types = 1; 6938 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; 6939 6940 adev->gfx.priv_inst_irq.num_types = 1; 6941 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; 6942 6943 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 6944 adev->gfx.kiq.irq.funcs = &gfx_v8_0_kiq_irq_funcs; 6945 } 6946 6947 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev) 6948 { 6949 adev->gfx.rlc.funcs = &iceland_rlc_funcs; 6950 } 6951 6952 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) 6953 { 6954 /* init asci gds info */ 6955 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 6956 adev->gds.gws.total_size = 64; 6957 adev->gds.oa.total_size = 16; 6958 6959 if (adev->gds.mem.total_size == 64 * 1024) { 6960 adev->gds.mem.gfx_partition_size = 4096; 6961 adev->gds.mem.cs_partition_size = 4096; 6962 6963 adev->gds.gws.gfx_partition_size = 4; 6964 adev->gds.gws.cs_partition_size = 4; 6965 6966 adev->gds.oa.gfx_partition_size = 4; 6967 adev->gds.oa.cs_partition_size = 1; 6968 } else { 6969 adev->gds.mem.gfx_partition_size = 1024; 6970 adev->gds.mem.cs_partition_size = 1024; 6971 6972 adev->gds.gws.gfx_partition_size = 16; 6973 adev->gds.gws.cs_partition_size = 16; 6974 6975 adev->gds.oa.gfx_partition_size = 4; 6976 adev->gds.oa.cs_partition_size = 4; 6977 } 6978 } 6979 6980 static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 6981 u32 bitmap) 6982 { 6983 u32 data; 6984 6985 if (!bitmap) 6986 return; 6987 6988 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6989 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6990 6991 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 6992 } 6993 6994 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) 6995 { 6996 u32 data, mask; 6997 6998 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 6999 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 7000 7001 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 7002 7003 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 7004 } 7005 7006 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) 7007 { 7008 int i, j, k, counter, active_cu_number = 0; 7009 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 7010 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 7011 unsigned disable_masks[4 * 2]; 7012 u32 ao_cu_num; 7013 7014 memset(cu_info, 0, sizeof(*cu_info)); 7015 7016 if (adev->flags & AMD_IS_APU) 7017 ao_cu_num = 2; 7018 else 7019 ao_cu_num = adev->gfx.config.max_cu_per_sh; 7020 7021 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 7022 7023 mutex_lock(&adev->grbm_idx_mutex); 7024 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 7025 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 7026 mask = 1; 7027 ao_bitmap = 0; 7028 counter = 0; 7029 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 7030 if (i < 4 && j < 2) 7031 gfx_v8_0_set_user_cu_inactive_bitmap( 7032 adev, disable_masks[i * 2 + j]); 7033 bitmap = gfx_v8_0_get_cu_active_bitmap(adev); 7034 cu_info->bitmap[i][j] = bitmap; 7035 7036 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 7037 if (bitmap & mask) { 7038 if (counter < ao_cu_num) 7039 ao_bitmap |= mask; 7040 counter ++; 7041 } 7042 mask <<= 1; 7043 } 7044 active_cu_number += counter; 7045 if (i < 2 && j < 2) 7046 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 7047 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 7048 } 7049 } 7050 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7051 mutex_unlock(&adev->grbm_idx_mutex); 7052 7053 cu_info->number = active_cu_number; 7054 cu_info->ao_cu_mask = ao_cu_mask; 7055 } 7056 7057 const struct amdgpu_ip_block_version gfx_v8_0_ip_block = 7058 { 7059 .type = AMD_IP_BLOCK_TYPE_GFX, 7060 .major = 8, 7061 .minor = 0, 7062 .rev = 0, 7063 .funcs = &gfx_v8_0_ip_funcs, 7064 }; 7065 7066 const struct amdgpu_ip_block_version gfx_v8_1_ip_block = 7067 { 7068 .type = AMD_IP_BLOCK_TYPE_GFX, 7069 .major = 8, 7070 .minor = 1, 7071 .rev = 0, 7072 .funcs = &gfx_v8_0_ip_funcs, 7073 }; 7074 7075 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 7076 { 7077 uint64_t ce_payload_addr; 7078 int cnt_ce; 7079 static union { 7080 struct vi_ce_ib_state regular; 7081 struct vi_ce_ib_state_chained_ib chained; 7082 } ce_payload = {}; 7083 7084 if (ring->adev->virt.chained_ib_support) { 7085 ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 + 7086 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload); 7087 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2; 7088 } else { 7089 ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 + 7090 offsetof(struct vi_gfx_meta_data, ce_payload); 7091 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2; 7092 } 7093 7094 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce)); 7095 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 7096 WRITE_DATA_DST_SEL(8) | 7097 WR_CONFIRM) | 7098 WRITE_DATA_CACHE_POLICY(0)); 7099 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr)); 7100 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr)); 7101 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2); 7102 } 7103 7104 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring) 7105 { 7106 uint64_t de_payload_addr, gds_addr, csa_addr; 7107 int cnt_de; 7108 static union { 7109 struct vi_de_ib_state regular; 7110 struct vi_de_ib_state_chained_ib chained; 7111 } de_payload = {}; 7112 7113 csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096; 7114 gds_addr = csa_addr + 4096; 7115 if (ring->adev->virt.chained_ib_support) { 7116 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr); 7117 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr); 7118 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload); 7119 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2; 7120 } else { 7121 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr); 7122 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr); 7123 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload); 7124 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2; 7125 } 7126 7127 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de)); 7128 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 7129 WRITE_DATA_DST_SEL(8) | 7130 WR_CONFIRM) | 7131 WRITE_DATA_CACHE_POLICY(0)); 7132 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr)); 7133 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr)); 7134 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2); 7135 } 7136