1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "vi.h" 28 #include "vid.h" 29 #include "amdgpu_ucode.h" 30 #include "clearstate_vi.h" 31 32 #include "gmc/gmc_8_2_d.h" 33 #include "gmc/gmc_8_2_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 #include "gca/gfx_8_0_enum.h" 45 46 #include "uvd/uvd_5_0_d.h" 47 #include "uvd/uvd_5_0_sh_mask.h" 48 49 #include "dce/dce_10_0_d.h" 50 #include "dce/dce_10_0_sh_mask.h" 51 52 #define GFX8_NUM_GFX_RINGS 1 53 #define GFX8_NUM_COMPUTE_RINGS 8 54 55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 58 59 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 60 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 62 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT) 63 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 64 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT) 65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT) 66 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT) 67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) 68 69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); 72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); 73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); 74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); 75 76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/tonga_me.bin"); 79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); 81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/topaz_me.bin"); 86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin"); 88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); 89 90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 91 { 92 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 93 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 94 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 95 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 96 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 97 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 98 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 99 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 100 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 101 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 102 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 103 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 104 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 105 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 106 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 107 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 108 }; 109 110 static const u32 golden_settings_tonga_a11[] = 111 { 112 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208, 113 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 114 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 115 mmGB_GPU_ID, 0x0000000f, 0x00000000, 116 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 117 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 118 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 119 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 120 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 121 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 122 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 123 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb, 124 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 125 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 126 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, 127 }; 128 129 static const u32 tonga_golden_common_all[] = 130 { 131 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 132 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, 133 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A, 134 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, 135 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 136 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 137 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 138 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 139 }; 140 141 static const u32 tonga_mgcg_cgcg_init[] = 142 { 143 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 145 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 146 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 147 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 148 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 149 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 150 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 151 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 152 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 153 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 154 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 155 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 156 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 157 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 158 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 159 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 160 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 161 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 162 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 163 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 164 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 165 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 166 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 167 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 168 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 169 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 170 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 171 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 172 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 173 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 174 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 175 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 176 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 177 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 178 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 179 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 180 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 181 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 182 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 183 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 184 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 185 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 186 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 187 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 188 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 189 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 190 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 191 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 192 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 193 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 194 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 195 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 196 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 197 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 198 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 199 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 200 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 201 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 202 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 203 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 204 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 205 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 206 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 207 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 208 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 209 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 210 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 211 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 212 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 213 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 214 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 215 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 216 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 217 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 218 }; 219 220 static const u32 golden_settings_iceland_a11[] = 221 { 222 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 223 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 224 mmDB_DEBUG3, 0xc0000000, 0xc0000000, 225 mmGB_GPU_ID, 0x0000000f, 0x00000000, 226 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 227 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 228 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002, 229 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000, 230 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 231 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 232 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 233 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 234 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 235 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 236 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010, 237 }; 238 239 static const u32 iceland_golden_common_all[] = 240 { 241 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 242 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 243 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 244 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 245 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 246 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 247 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 248 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 249 }; 250 251 static const u32 iceland_mgcg_cgcg_init[] = 252 { 253 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 254 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 255 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 256 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 257 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100, 258 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100, 259 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100, 260 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 261 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 262 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 263 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 264 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 265 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 266 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 267 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 268 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 269 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 270 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 271 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 272 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 273 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 274 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 275 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100, 276 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 277 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 278 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 279 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 280 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 281 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 282 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 283 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 284 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 285 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 286 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 287 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 288 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 289 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 290 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 291 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 292 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 293 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 294 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 295 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 296 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 297 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 298 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 299 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 300 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 301 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 302 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 303 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 304 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 305 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 306 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87, 307 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 308 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 309 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 310 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 311 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 312 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 313 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 314 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 315 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 316 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 317 }; 318 319 static const u32 cz_golden_settings_a11[] = 320 { 321 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040, 322 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 323 mmGB_GPU_ID, 0x0000000f, 0x00000000, 324 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001, 325 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 326 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 327 mmTA_CNTL_AUX, 0x000f000f, 0x00010000, 328 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, 329 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3, 330 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302 331 }; 332 333 static const u32 cz_golden_common_all[] = 334 { 335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 336 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002, 337 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, 338 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001, 339 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, 340 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, 341 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, 342 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF 343 }; 344 345 static const u32 cz_mgcg_cgcg_init[] = 346 { 347 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, 348 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 349 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 350 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 351 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 352 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 353 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100, 354 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 355 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 356 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 357 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100, 358 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 359 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 360 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 361 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 362 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 363 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 364 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 365 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 366 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 367 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 368 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100, 369 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 370 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 371 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 372 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 373 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 374 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 375 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 376 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 377 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 378 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000, 379 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 380 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 381 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005, 382 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 383 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000, 384 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 385 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007, 386 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005, 387 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 388 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000, 389 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 390 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007, 391 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005, 392 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 393 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000, 394 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 395 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007, 396 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005, 397 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 398 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000, 399 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 400 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007, 401 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005, 402 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 403 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000, 404 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 405 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007, 406 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005, 407 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 408 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000, 409 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 410 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007, 411 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005, 412 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 413 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000, 414 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002, 415 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007, 416 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005, 417 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008, 418 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 419 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 420 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 421 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 422 }; 423 424 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); 425 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); 426 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); 427 428 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) 429 { 430 switch (adev->asic_type) { 431 case CHIP_TOPAZ: 432 amdgpu_program_register_sequence(adev, 433 iceland_mgcg_cgcg_init, 434 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 435 amdgpu_program_register_sequence(adev, 436 golden_settings_iceland_a11, 437 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 438 amdgpu_program_register_sequence(adev, 439 iceland_golden_common_all, 440 (const u32)ARRAY_SIZE(iceland_golden_common_all)); 441 break; 442 case CHIP_TONGA: 443 amdgpu_program_register_sequence(adev, 444 tonga_mgcg_cgcg_init, 445 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 446 amdgpu_program_register_sequence(adev, 447 golden_settings_tonga_a11, 448 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 449 amdgpu_program_register_sequence(adev, 450 tonga_golden_common_all, 451 (const u32)ARRAY_SIZE(tonga_golden_common_all)); 452 break; 453 case CHIP_CARRIZO: 454 amdgpu_program_register_sequence(adev, 455 cz_mgcg_cgcg_init, 456 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 457 amdgpu_program_register_sequence(adev, 458 cz_golden_settings_a11, 459 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 460 amdgpu_program_register_sequence(adev, 461 cz_golden_common_all, 462 (const u32)ARRAY_SIZE(cz_golden_common_all)); 463 break; 464 default: 465 break; 466 } 467 } 468 469 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) 470 { 471 int i; 472 473 adev->gfx.scratch.num_reg = 7; 474 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 475 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 476 adev->gfx.scratch.free[i] = true; 477 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 478 } 479 } 480 481 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) 482 { 483 struct amdgpu_device *adev = ring->adev; 484 uint32_t scratch; 485 uint32_t tmp = 0; 486 unsigned i; 487 int r; 488 489 r = amdgpu_gfx_scratch_get(adev, &scratch); 490 if (r) { 491 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 492 return r; 493 } 494 WREG32(scratch, 0xCAFEDEAD); 495 r = amdgpu_ring_lock(ring, 3); 496 if (r) { 497 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 498 ring->idx, r); 499 amdgpu_gfx_scratch_free(adev, scratch); 500 return r; 501 } 502 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 503 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 504 amdgpu_ring_write(ring, 0xDEADBEEF); 505 amdgpu_ring_unlock_commit(ring); 506 507 for (i = 0; i < adev->usec_timeout; i++) { 508 tmp = RREG32(scratch); 509 if (tmp == 0xDEADBEEF) 510 break; 511 DRM_UDELAY(1); 512 } 513 if (i < adev->usec_timeout) { 514 DRM_INFO("ring test on %d succeeded in %d usecs\n", 515 ring->idx, i); 516 } else { 517 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 518 ring->idx, scratch, tmp); 519 r = -EINVAL; 520 } 521 amdgpu_gfx_scratch_free(adev, scratch); 522 return r; 523 } 524 525 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring) 526 { 527 struct amdgpu_device *adev = ring->adev; 528 struct amdgpu_ib ib; 529 uint32_t scratch; 530 uint32_t tmp = 0; 531 unsigned i; 532 int r; 533 534 r = amdgpu_gfx_scratch_get(adev, &scratch); 535 if (r) { 536 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); 537 return r; 538 } 539 WREG32(scratch, 0xCAFEDEAD); 540 r = amdgpu_ib_get(ring, NULL, 256, &ib); 541 if (r) { 542 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 543 amdgpu_gfx_scratch_free(adev, scratch); 544 return r; 545 } 546 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 547 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 548 ib.ptr[2] = 0xDEADBEEF; 549 ib.length_dw = 3; 550 r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED); 551 if (r) { 552 amdgpu_gfx_scratch_free(adev, scratch); 553 amdgpu_ib_free(adev, &ib); 554 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r); 555 return r; 556 } 557 r = amdgpu_fence_wait(ib.fence, false); 558 if (r) { 559 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 560 amdgpu_gfx_scratch_free(adev, scratch); 561 amdgpu_ib_free(adev, &ib); 562 return r; 563 } 564 for (i = 0; i < adev->usec_timeout; i++) { 565 tmp = RREG32(scratch); 566 if (tmp == 0xDEADBEEF) 567 break; 568 DRM_UDELAY(1); 569 } 570 if (i < adev->usec_timeout) { 571 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 572 ib.fence->ring->idx, i); 573 } else { 574 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 575 scratch, tmp); 576 r = -EINVAL; 577 } 578 amdgpu_gfx_scratch_free(adev, scratch); 579 amdgpu_ib_free(adev, &ib); 580 return r; 581 } 582 583 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) 584 { 585 const char *chip_name; 586 char fw_name[30]; 587 int err; 588 struct amdgpu_firmware_info *info = NULL; 589 const struct common_firmware_header *header = NULL; 590 591 DRM_DEBUG("\n"); 592 593 switch (adev->asic_type) { 594 case CHIP_TOPAZ: 595 chip_name = "topaz"; 596 break; 597 case CHIP_TONGA: 598 chip_name = "tonga"; 599 break; 600 case CHIP_CARRIZO: 601 chip_name = "carrizo"; 602 break; 603 default: 604 BUG(); 605 } 606 607 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 608 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 609 if (err) 610 goto out; 611 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 612 if (err) 613 goto out; 614 615 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 616 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 617 if (err) 618 goto out; 619 err = amdgpu_ucode_validate(adev->gfx.me_fw); 620 if (err) 621 goto out; 622 623 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 624 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 625 if (err) 626 goto out; 627 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 628 if (err) 629 goto out; 630 631 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 632 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 633 if (err) 634 goto out; 635 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 636 637 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 638 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 639 if (err) 640 goto out; 641 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 642 if (err) 643 goto out; 644 645 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 646 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 647 if (!err) { 648 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 649 if (err) 650 goto out; 651 } else { 652 err = 0; 653 adev->gfx.mec2_fw = NULL; 654 } 655 656 if (adev->firmware.smu_load) { 657 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 658 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 659 info->fw = adev->gfx.pfp_fw; 660 header = (const struct common_firmware_header *)info->fw->data; 661 adev->firmware.fw_size += 662 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 663 664 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 665 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 666 info->fw = adev->gfx.me_fw; 667 header = (const struct common_firmware_header *)info->fw->data; 668 adev->firmware.fw_size += 669 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 670 671 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 672 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 673 info->fw = adev->gfx.ce_fw; 674 header = (const struct common_firmware_header *)info->fw->data; 675 adev->firmware.fw_size += 676 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 677 678 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 679 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 680 info->fw = adev->gfx.rlc_fw; 681 header = (const struct common_firmware_header *)info->fw->data; 682 adev->firmware.fw_size += 683 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 684 685 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 686 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 687 info->fw = adev->gfx.mec_fw; 688 header = (const struct common_firmware_header *)info->fw->data; 689 adev->firmware.fw_size += 690 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 691 692 if (adev->gfx.mec2_fw) { 693 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 694 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 695 info->fw = adev->gfx.mec2_fw; 696 header = (const struct common_firmware_header *)info->fw->data; 697 adev->firmware.fw_size += 698 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 699 } 700 701 } 702 703 out: 704 if (err) { 705 dev_err(adev->dev, 706 "gfx8: Failed to load firmware \"%s\"\n", 707 fw_name); 708 release_firmware(adev->gfx.pfp_fw); 709 adev->gfx.pfp_fw = NULL; 710 release_firmware(adev->gfx.me_fw); 711 adev->gfx.me_fw = NULL; 712 release_firmware(adev->gfx.ce_fw); 713 adev->gfx.ce_fw = NULL; 714 release_firmware(adev->gfx.rlc_fw); 715 adev->gfx.rlc_fw = NULL; 716 release_firmware(adev->gfx.mec_fw); 717 adev->gfx.mec_fw = NULL; 718 release_firmware(adev->gfx.mec2_fw); 719 adev->gfx.mec2_fw = NULL; 720 } 721 return err; 722 } 723 724 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) 725 { 726 int r; 727 728 if (adev->gfx.mec.hpd_eop_obj) { 729 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 730 if (unlikely(r != 0)) 731 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 732 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 733 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 734 735 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 736 adev->gfx.mec.hpd_eop_obj = NULL; 737 } 738 } 739 740 #define MEC_HPD_SIZE 2048 741 742 static int gfx_v8_0_mec_init(struct amdgpu_device *adev) 743 { 744 int r; 745 u32 *hpd; 746 747 /* 748 * we assign only 1 pipe because all other pipes will 749 * be handled by KFD 750 */ 751 adev->gfx.mec.num_mec = 1; 752 adev->gfx.mec.num_pipe = 1; 753 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 754 755 if (adev->gfx.mec.hpd_eop_obj == NULL) { 756 r = amdgpu_bo_create(adev, 757 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 758 PAGE_SIZE, true, 759 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, 760 &adev->gfx.mec.hpd_eop_obj); 761 if (r) { 762 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 763 return r; 764 } 765 } 766 767 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 768 if (unlikely(r != 0)) { 769 gfx_v8_0_mec_fini(adev); 770 return r; 771 } 772 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 773 &adev->gfx.mec.hpd_eop_gpu_addr); 774 if (r) { 775 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 776 gfx_v8_0_mec_fini(adev); 777 return r; 778 } 779 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 780 if (r) { 781 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 782 gfx_v8_0_mec_fini(adev); 783 return r; 784 } 785 786 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 787 788 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 789 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 790 791 return 0; 792 } 793 794 static int gfx_v8_0_sw_init(void *handle) 795 { 796 int i, r; 797 struct amdgpu_ring *ring; 798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 799 800 /* EOP Event */ 801 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 802 if (r) 803 return r; 804 805 /* Privileged reg */ 806 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 807 if (r) 808 return r; 809 810 /* Privileged inst */ 811 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 812 if (r) 813 return r; 814 815 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 816 817 gfx_v8_0_scratch_init(adev); 818 819 r = gfx_v8_0_init_microcode(adev); 820 if (r) { 821 DRM_ERROR("Failed to load gfx firmware!\n"); 822 return r; 823 } 824 825 r = gfx_v8_0_mec_init(adev); 826 if (r) { 827 DRM_ERROR("Failed to init MEC BOs!\n"); 828 return r; 829 } 830 831 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs); 832 if (r) { 833 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r); 834 return r; 835 } 836 837 /* set up the gfx ring */ 838 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 839 ring = &adev->gfx.gfx_ring[i]; 840 ring->ring_obj = NULL; 841 sprintf(ring->name, "gfx"); 842 /* no gfx doorbells on iceland */ 843 if (adev->asic_type != CHIP_TOPAZ) { 844 ring->use_doorbell = true; 845 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; 846 } 847 848 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 849 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 850 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, 851 AMDGPU_RING_TYPE_GFX); 852 if (r) 853 return r; 854 } 855 856 /* set up the compute queues */ 857 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 858 unsigned irq_type; 859 860 /* max 32 queues per MEC */ 861 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 862 DRM_ERROR("Too many (%d) compute rings!\n", i); 863 break; 864 } 865 ring = &adev->gfx.compute_ring[i]; 866 ring->ring_obj = NULL; 867 ring->use_doorbell = true; 868 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; 869 ring->me = 1; /* first MEC */ 870 ring->pipe = i / 8; 871 ring->queue = i % 8; 872 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 873 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 874 /* type-2 packets are deprecated on MEC, use type-3 instead */ 875 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 876 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 877 &adev->gfx.eop_irq, irq_type, 878 AMDGPU_RING_TYPE_COMPUTE); 879 if (r) 880 return r; 881 } 882 883 /* reserve GDS, GWS and OA resource for gfx */ 884 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, 885 PAGE_SIZE, true, 886 AMDGPU_GEM_DOMAIN_GDS, 0, 887 NULL, &adev->gds.gds_gfx_bo); 888 if (r) 889 return r; 890 891 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, 892 PAGE_SIZE, true, 893 AMDGPU_GEM_DOMAIN_GWS, 0, 894 NULL, &adev->gds.gws_gfx_bo); 895 if (r) 896 return r; 897 898 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, 899 PAGE_SIZE, true, 900 AMDGPU_GEM_DOMAIN_OA, 0, 901 NULL, &adev->gds.oa_gfx_bo); 902 if (r) 903 return r; 904 905 adev->gfx.ce_ram_size = 0x8000; 906 907 return 0; 908 } 909 910 static int gfx_v8_0_sw_fini(void *handle) 911 { 912 int i; 913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 914 915 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 916 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 917 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); 918 919 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 920 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 921 for (i = 0; i < adev->gfx.num_compute_rings; i++) 922 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 923 924 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs); 925 926 gfx_v8_0_mec_fini(adev); 927 928 return 0; 929 } 930 931 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) 932 { 933 const u32 num_tile_mode_states = 32; 934 const u32 num_secondary_tile_mode_states = 16; 935 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 936 937 switch (adev->gfx.config.mem_row_size_in_kb) { 938 case 1: 939 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 940 break; 941 case 2: 942 default: 943 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 944 break; 945 case 4: 946 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 947 break; 948 } 949 950 switch (adev->asic_type) { 951 case CHIP_TOPAZ: 952 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 953 switch (reg_offset) { 954 case 0: 955 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 956 PIPE_CONFIG(ADDR_SURF_P2) | 957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 958 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 959 break; 960 case 1: 961 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 962 PIPE_CONFIG(ADDR_SURF_P2) | 963 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 964 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 965 break; 966 case 2: 967 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 968 PIPE_CONFIG(ADDR_SURF_P2) | 969 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 970 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 971 break; 972 case 3: 973 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 974 PIPE_CONFIG(ADDR_SURF_P2) | 975 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 976 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 977 break; 978 case 4: 979 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 980 PIPE_CONFIG(ADDR_SURF_P2) | 981 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 982 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 983 break; 984 case 5: 985 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 986 PIPE_CONFIG(ADDR_SURF_P2) | 987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 988 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 989 break; 990 case 6: 991 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 992 PIPE_CONFIG(ADDR_SURF_P2) | 993 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 994 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 995 break; 996 case 8: 997 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 998 PIPE_CONFIG(ADDR_SURF_P2)); 999 break; 1000 case 9: 1001 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1002 PIPE_CONFIG(ADDR_SURF_P2) | 1003 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1005 break; 1006 case 10: 1007 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1008 PIPE_CONFIG(ADDR_SURF_P2) | 1009 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1010 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1011 break; 1012 case 11: 1013 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1014 PIPE_CONFIG(ADDR_SURF_P2) | 1015 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1016 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1017 break; 1018 case 13: 1019 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1020 PIPE_CONFIG(ADDR_SURF_P2) | 1021 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1022 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1023 break; 1024 case 14: 1025 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1026 PIPE_CONFIG(ADDR_SURF_P2) | 1027 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1028 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1029 break; 1030 case 15: 1031 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1032 PIPE_CONFIG(ADDR_SURF_P2) | 1033 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1034 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1035 break; 1036 case 16: 1037 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1038 PIPE_CONFIG(ADDR_SURF_P2) | 1039 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1040 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1041 break; 1042 case 18: 1043 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1044 PIPE_CONFIG(ADDR_SURF_P2) | 1045 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1046 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1047 break; 1048 case 19: 1049 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1050 PIPE_CONFIG(ADDR_SURF_P2) | 1051 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1052 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1053 break; 1054 case 20: 1055 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1056 PIPE_CONFIG(ADDR_SURF_P2) | 1057 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1058 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1059 break; 1060 case 21: 1061 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1062 PIPE_CONFIG(ADDR_SURF_P2) | 1063 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1064 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1065 break; 1066 case 22: 1067 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1068 PIPE_CONFIG(ADDR_SURF_P2) | 1069 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1070 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1071 break; 1072 case 24: 1073 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1074 PIPE_CONFIG(ADDR_SURF_P2) | 1075 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1076 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1077 break; 1078 case 25: 1079 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1080 PIPE_CONFIG(ADDR_SURF_P2) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1083 break; 1084 case 26: 1085 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1086 PIPE_CONFIG(ADDR_SURF_P2) | 1087 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1089 break; 1090 case 27: 1091 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1092 PIPE_CONFIG(ADDR_SURF_P2) | 1093 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1095 break; 1096 case 28: 1097 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1098 PIPE_CONFIG(ADDR_SURF_P2) | 1099 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1101 break; 1102 case 29: 1103 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1104 PIPE_CONFIG(ADDR_SURF_P2) | 1105 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1107 break; 1108 case 7: 1109 case 12: 1110 case 17: 1111 case 23: 1112 /* unused idx */ 1113 continue; 1114 default: 1115 gb_tile_moden = 0; 1116 break; 1117 }; 1118 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1119 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1120 } 1121 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1122 switch (reg_offset) { 1123 case 0: 1124 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1127 NUM_BANKS(ADDR_SURF_8_BANK)); 1128 break; 1129 case 1: 1130 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1131 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1132 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1133 NUM_BANKS(ADDR_SURF_8_BANK)); 1134 break; 1135 case 2: 1136 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1139 NUM_BANKS(ADDR_SURF_8_BANK)); 1140 break; 1141 case 3: 1142 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1145 NUM_BANKS(ADDR_SURF_8_BANK)); 1146 break; 1147 case 4: 1148 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1151 NUM_BANKS(ADDR_SURF_8_BANK)); 1152 break; 1153 case 5: 1154 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1157 NUM_BANKS(ADDR_SURF_8_BANK)); 1158 break; 1159 case 6: 1160 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1163 NUM_BANKS(ADDR_SURF_8_BANK)); 1164 break; 1165 case 8: 1166 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1169 NUM_BANKS(ADDR_SURF_16_BANK)); 1170 break; 1171 case 9: 1172 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1175 NUM_BANKS(ADDR_SURF_16_BANK)); 1176 break; 1177 case 10: 1178 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1181 NUM_BANKS(ADDR_SURF_16_BANK)); 1182 break; 1183 case 11: 1184 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1187 NUM_BANKS(ADDR_SURF_16_BANK)); 1188 break; 1189 case 12: 1190 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1193 NUM_BANKS(ADDR_SURF_16_BANK)); 1194 break; 1195 case 13: 1196 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1199 NUM_BANKS(ADDR_SURF_16_BANK)); 1200 break; 1201 case 14: 1202 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1205 NUM_BANKS(ADDR_SURF_8_BANK)); 1206 break; 1207 case 7: 1208 /* unused idx */ 1209 continue; 1210 default: 1211 gb_tile_moden = 0; 1212 break; 1213 }; 1214 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1215 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1216 } 1217 case CHIP_TONGA: 1218 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1219 switch (reg_offset) { 1220 case 0: 1221 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1222 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1223 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1225 break; 1226 case 1: 1227 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1231 break; 1232 case 2: 1233 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1234 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1237 break; 1238 case 3: 1239 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1240 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1241 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1243 break; 1244 case 4: 1245 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1246 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1249 break; 1250 case 5: 1251 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1252 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1253 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1254 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1255 break; 1256 case 6: 1257 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1258 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1260 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1261 break; 1262 case 7: 1263 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1264 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1265 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1267 break; 1268 case 8: 1269 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1270 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)); 1271 break; 1272 case 9: 1273 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1274 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1275 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1277 break; 1278 case 10: 1279 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1280 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1283 break; 1284 case 11: 1285 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1286 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1287 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1289 break; 1290 case 12: 1291 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1293 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1295 break; 1296 case 13: 1297 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1298 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1299 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1301 break; 1302 case 14: 1303 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1304 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1307 break; 1308 case 15: 1309 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1310 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1313 break; 1314 case 16: 1315 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1316 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1319 break; 1320 case 17: 1321 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1322 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1323 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1325 break; 1326 case 18: 1327 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1328 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1329 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1331 break; 1332 case 19: 1333 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1334 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1335 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1337 break; 1338 case 20: 1339 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1340 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1341 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1342 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1343 break; 1344 case 21: 1345 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1346 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1347 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1348 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1349 break; 1350 case 22: 1351 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1352 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1353 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1354 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1355 break; 1356 case 23: 1357 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1358 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1359 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1360 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1361 break; 1362 case 24: 1363 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1364 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1365 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1366 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1367 break; 1368 case 25: 1369 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1370 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1371 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1372 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1373 break; 1374 case 26: 1375 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1376 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1377 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1378 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1379 break; 1380 case 27: 1381 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1382 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1383 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1384 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1385 break; 1386 case 28: 1387 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1388 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1389 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1390 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1391 break; 1392 case 29: 1393 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1394 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | 1395 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1397 break; 1398 case 30: 1399 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1400 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1401 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1402 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1403 break; 1404 default: 1405 gb_tile_moden = 0; 1406 break; 1407 }; 1408 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1409 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1410 } 1411 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1412 switch (reg_offset) { 1413 case 0: 1414 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1415 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1416 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1417 NUM_BANKS(ADDR_SURF_16_BANK)); 1418 break; 1419 case 1: 1420 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1423 NUM_BANKS(ADDR_SURF_16_BANK)); 1424 break; 1425 case 2: 1426 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1429 NUM_BANKS(ADDR_SURF_16_BANK)); 1430 break; 1431 case 3: 1432 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1435 NUM_BANKS(ADDR_SURF_16_BANK)); 1436 break; 1437 case 4: 1438 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1439 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1440 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1441 NUM_BANKS(ADDR_SURF_16_BANK)); 1442 break; 1443 case 5: 1444 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1447 NUM_BANKS(ADDR_SURF_16_BANK)); 1448 break; 1449 case 6: 1450 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1453 NUM_BANKS(ADDR_SURF_16_BANK)); 1454 break; 1455 case 8: 1456 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1459 NUM_BANKS(ADDR_SURF_16_BANK)); 1460 break; 1461 case 9: 1462 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1465 NUM_BANKS(ADDR_SURF_16_BANK)); 1466 break; 1467 case 10: 1468 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1469 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1470 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1471 NUM_BANKS(ADDR_SURF_16_BANK)); 1472 break; 1473 case 11: 1474 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1477 NUM_BANKS(ADDR_SURF_16_BANK)); 1478 break; 1479 case 12: 1480 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1483 NUM_BANKS(ADDR_SURF_8_BANK)); 1484 break; 1485 case 13: 1486 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1489 NUM_BANKS(ADDR_SURF_4_BANK)); 1490 break; 1491 case 14: 1492 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1495 NUM_BANKS(ADDR_SURF_4_BANK)); 1496 break; 1497 case 7: 1498 /* unused idx */ 1499 continue; 1500 default: 1501 gb_tile_moden = 0; 1502 break; 1503 }; 1504 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1505 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1506 } 1507 break; 1508 case CHIP_CARRIZO: 1509 default: 1510 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1511 switch (reg_offset) { 1512 case 0: 1513 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1514 PIPE_CONFIG(ADDR_SURF_P2) | 1515 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1516 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1517 break; 1518 case 1: 1519 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1520 PIPE_CONFIG(ADDR_SURF_P2) | 1521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1523 break; 1524 case 2: 1525 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1526 PIPE_CONFIG(ADDR_SURF_P2) | 1527 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1528 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1529 break; 1530 case 3: 1531 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1532 PIPE_CONFIG(ADDR_SURF_P2) | 1533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1534 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1535 break; 1536 case 4: 1537 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1538 PIPE_CONFIG(ADDR_SURF_P2) | 1539 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1540 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1541 break; 1542 case 5: 1543 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1544 PIPE_CONFIG(ADDR_SURF_P2) | 1545 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1546 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1547 break; 1548 case 6: 1549 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1550 PIPE_CONFIG(ADDR_SURF_P2) | 1551 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1552 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1553 break; 1554 case 8: 1555 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1556 PIPE_CONFIG(ADDR_SURF_P2)); 1557 break; 1558 case 9: 1559 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1560 PIPE_CONFIG(ADDR_SURF_P2) | 1561 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1563 break; 1564 case 10: 1565 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1566 PIPE_CONFIG(ADDR_SURF_P2) | 1567 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1569 break; 1570 case 11: 1571 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1572 PIPE_CONFIG(ADDR_SURF_P2) | 1573 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1574 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1575 break; 1576 case 13: 1577 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1578 PIPE_CONFIG(ADDR_SURF_P2) | 1579 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1581 break; 1582 case 14: 1583 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1584 PIPE_CONFIG(ADDR_SURF_P2) | 1585 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1586 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1587 break; 1588 case 15: 1589 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1590 PIPE_CONFIG(ADDR_SURF_P2) | 1591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1593 break; 1594 case 16: 1595 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1596 PIPE_CONFIG(ADDR_SURF_P2) | 1597 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1598 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1599 break; 1600 case 18: 1601 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1602 PIPE_CONFIG(ADDR_SURF_P2) | 1603 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1605 break; 1606 case 19: 1607 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1608 PIPE_CONFIG(ADDR_SURF_P2) | 1609 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1610 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1611 break; 1612 case 20: 1613 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1614 PIPE_CONFIG(ADDR_SURF_P2) | 1615 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1617 break; 1618 case 21: 1619 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1620 PIPE_CONFIG(ADDR_SURF_P2) | 1621 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1622 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1623 break; 1624 case 22: 1625 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1626 PIPE_CONFIG(ADDR_SURF_P2) | 1627 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1628 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1629 break; 1630 case 24: 1631 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1632 PIPE_CONFIG(ADDR_SURF_P2) | 1633 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1634 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1635 break; 1636 case 25: 1637 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1638 PIPE_CONFIG(ADDR_SURF_P2) | 1639 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1640 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1641 break; 1642 case 26: 1643 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1644 PIPE_CONFIG(ADDR_SURF_P2) | 1645 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1646 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1647 break; 1648 case 27: 1649 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1650 PIPE_CONFIG(ADDR_SURF_P2) | 1651 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1652 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1653 break; 1654 case 28: 1655 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1656 PIPE_CONFIG(ADDR_SURF_P2) | 1657 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1658 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1659 break; 1660 case 29: 1661 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1662 PIPE_CONFIG(ADDR_SURF_P2) | 1663 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1664 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1665 break; 1666 case 7: 1667 case 12: 1668 case 17: 1669 case 23: 1670 /* unused idx */ 1671 continue; 1672 default: 1673 gb_tile_moden = 0; 1674 break; 1675 }; 1676 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1677 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1678 } 1679 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1680 switch (reg_offset) { 1681 case 0: 1682 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1685 NUM_BANKS(ADDR_SURF_8_BANK)); 1686 break; 1687 case 1: 1688 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1689 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1690 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1691 NUM_BANKS(ADDR_SURF_8_BANK)); 1692 break; 1693 case 2: 1694 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1697 NUM_BANKS(ADDR_SURF_8_BANK)); 1698 break; 1699 case 3: 1700 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1701 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1702 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1703 NUM_BANKS(ADDR_SURF_8_BANK)); 1704 break; 1705 case 4: 1706 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1707 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1708 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1709 NUM_BANKS(ADDR_SURF_8_BANK)); 1710 break; 1711 case 5: 1712 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1713 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1714 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1715 NUM_BANKS(ADDR_SURF_8_BANK)); 1716 break; 1717 case 6: 1718 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1721 NUM_BANKS(ADDR_SURF_8_BANK)); 1722 break; 1723 case 8: 1724 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1725 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1726 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1727 NUM_BANKS(ADDR_SURF_16_BANK)); 1728 break; 1729 case 9: 1730 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1733 NUM_BANKS(ADDR_SURF_16_BANK)); 1734 break; 1735 case 10: 1736 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1737 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1738 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1739 NUM_BANKS(ADDR_SURF_16_BANK)); 1740 break; 1741 case 11: 1742 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1745 NUM_BANKS(ADDR_SURF_16_BANK)); 1746 break; 1747 case 12: 1748 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1749 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1750 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1751 NUM_BANKS(ADDR_SURF_16_BANK)); 1752 break; 1753 case 13: 1754 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1757 NUM_BANKS(ADDR_SURF_16_BANK)); 1758 break; 1759 case 14: 1760 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1761 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1762 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1763 NUM_BANKS(ADDR_SURF_8_BANK)); 1764 break; 1765 case 7: 1766 /* unused idx */ 1767 continue; 1768 default: 1769 gb_tile_moden = 0; 1770 break; 1771 }; 1772 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1773 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1774 } 1775 } 1776 } 1777 1778 static u32 gfx_v8_0_create_bitmask(u32 bit_width) 1779 { 1780 u32 i, mask = 0; 1781 1782 for (i = 0; i < bit_width; i++) { 1783 mask <<= 1; 1784 mask |= 1; 1785 } 1786 return mask; 1787 } 1788 1789 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) 1790 { 1791 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1792 1793 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) { 1794 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1795 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1796 } else if (se_num == 0xffffffff) { 1797 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1798 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1799 } else if (sh_num == 0xffffffff) { 1800 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1801 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1802 } else { 1803 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1804 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1805 } 1806 WREG32(mmGRBM_GFX_INDEX, data); 1807 } 1808 1809 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev, 1810 u32 max_rb_num_per_se, 1811 u32 sh_per_se) 1812 { 1813 u32 data, mask; 1814 1815 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1816 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1817 1818 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1819 1820 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1821 1822 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se); 1823 1824 return data & mask; 1825 } 1826 1827 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev, 1828 u32 se_num, u32 sh_per_se, 1829 u32 max_rb_num_per_se) 1830 { 1831 int i, j; 1832 u32 data, mask; 1833 u32 disabled_rbs = 0; 1834 u32 enabled_rbs = 0; 1835 1836 mutex_lock(&adev->grbm_idx_mutex); 1837 for (i = 0; i < se_num; i++) { 1838 for (j = 0; j < sh_per_se; j++) { 1839 gfx_v8_0_select_se_sh(adev, i, j); 1840 data = gfx_v8_0_get_rb_disabled(adev, 1841 max_rb_num_per_se, sh_per_se); 1842 disabled_rbs |= data << ((i * sh_per_se + j) * 1843 RB_BITMAP_WIDTH_PER_SH); 1844 } 1845 } 1846 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1847 mutex_unlock(&adev->grbm_idx_mutex); 1848 1849 mask = 1; 1850 for (i = 0; i < max_rb_num_per_se * se_num; i++) { 1851 if (!(disabled_rbs & mask)) 1852 enabled_rbs |= mask; 1853 mask <<= 1; 1854 } 1855 1856 adev->gfx.config.backend_enable_mask = enabled_rbs; 1857 1858 mutex_lock(&adev->grbm_idx_mutex); 1859 for (i = 0; i < se_num; i++) { 1860 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); 1861 data = 0; 1862 for (j = 0; j < sh_per_se; j++) { 1863 switch (enabled_rbs & 3) { 1864 case 0: 1865 if (j == 0) 1866 data |= (RASTER_CONFIG_RB_MAP_3 << 1867 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); 1868 else 1869 data |= (RASTER_CONFIG_RB_MAP_0 << 1870 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT); 1871 break; 1872 case 1: 1873 data |= (RASTER_CONFIG_RB_MAP_0 << 1874 (i * sh_per_se + j) * 2); 1875 break; 1876 case 2: 1877 data |= (RASTER_CONFIG_RB_MAP_3 << 1878 (i * sh_per_se + j) * 2); 1879 break; 1880 case 3: 1881 default: 1882 data |= (RASTER_CONFIG_RB_MAP_2 << 1883 (i * sh_per_se + j) * 2); 1884 break; 1885 } 1886 enabled_rbs >>= 2; 1887 } 1888 WREG32(mmPA_SC_RASTER_CONFIG, data); 1889 } 1890 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1891 mutex_unlock(&adev->grbm_idx_mutex); 1892 } 1893 1894 /** 1895 * gmc_v8_0_init_compute_vmid - gart enable 1896 * 1897 * @rdev: amdgpu_device pointer 1898 * 1899 * Initialize compute vmid sh_mem registers 1900 * 1901 */ 1902 #define DEFAULT_SH_MEM_BASES (0x6000) 1903 #define FIRST_COMPUTE_VMID (8) 1904 #define LAST_COMPUTE_VMID (16) 1905 static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev) 1906 { 1907 int i; 1908 uint32_t sh_mem_config; 1909 uint32_t sh_mem_bases; 1910 1911 /* 1912 * Configure apertures: 1913 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1914 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1915 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1916 */ 1917 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1918 1919 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << 1920 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT | 1921 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1922 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | 1923 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | 1924 SH_MEM_CONFIG__PRIVATE_ATC_MASK; 1925 1926 mutex_lock(&adev->srbm_mutex); 1927 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1928 vi_srbm_select(adev, 0, 0, 0, i); 1929 /* CP and shaders */ 1930 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1931 WREG32(mmSH_MEM_APE1_BASE, 1); 1932 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1933 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1934 } 1935 vi_srbm_select(adev, 0, 0, 0, 0); 1936 mutex_unlock(&adev->srbm_mutex); 1937 } 1938 1939 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) 1940 { 1941 u32 gb_addr_config; 1942 u32 mc_shared_chmap, mc_arb_ramcfg; 1943 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 1944 u32 tmp; 1945 int i; 1946 1947 switch (adev->asic_type) { 1948 case CHIP_TOPAZ: 1949 adev->gfx.config.max_shader_engines = 1; 1950 adev->gfx.config.max_tile_pipes = 2; 1951 adev->gfx.config.max_cu_per_sh = 6; 1952 adev->gfx.config.max_sh_per_se = 1; 1953 adev->gfx.config.max_backends_per_se = 2; 1954 adev->gfx.config.max_texture_channel_caches = 2; 1955 adev->gfx.config.max_gprs = 256; 1956 adev->gfx.config.max_gs_threads = 32; 1957 adev->gfx.config.max_hw_contexts = 8; 1958 1959 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1960 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1961 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1962 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1963 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; 1964 break; 1965 case CHIP_TONGA: 1966 adev->gfx.config.max_shader_engines = 4; 1967 adev->gfx.config.max_tile_pipes = 8; 1968 adev->gfx.config.max_cu_per_sh = 8; 1969 adev->gfx.config.max_sh_per_se = 1; 1970 adev->gfx.config.max_backends_per_se = 2; 1971 adev->gfx.config.max_texture_channel_caches = 8; 1972 adev->gfx.config.max_gprs = 256; 1973 adev->gfx.config.max_gs_threads = 32; 1974 adev->gfx.config.max_hw_contexts = 8; 1975 1976 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1977 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1978 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1979 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1980 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 1981 break; 1982 case CHIP_CARRIZO: 1983 adev->gfx.config.max_shader_engines = 1; 1984 adev->gfx.config.max_tile_pipes = 2; 1985 adev->gfx.config.max_sh_per_se = 1; 1986 1987 switch (adev->pdev->revision) { 1988 case 0xc4: 1989 case 0x84: 1990 case 0xc8: 1991 case 0xcc: 1992 /* B10 */ 1993 adev->gfx.config.max_cu_per_sh = 8; 1994 adev->gfx.config.max_backends_per_se = 2; 1995 break; 1996 case 0xc5: 1997 case 0x81: 1998 case 0x85: 1999 case 0xc9: 2000 case 0xcd: 2001 /* B8 */ 2002 adev->gfx.config.max_cu_per_sh = 6; 2003 adev->gfx.config.max_backends_per_se = 2; 2004 break; 2005 case 0xc6: 2006 case 0xca: 2007 case 0xce: 2008 /* B6 */ 2009 adev->gfx.config.max_cu_per_sh = 6; 2010 adev->gfx.config.max_backends_per_se = 2; 2011 break; 2012 case 0xc7: 2013 case 0x87: 2014 case 0xcb: 2015 default: 2016 /* B4 */ 2017 adev->gfx.config.max_cu_per_sh = 4; 2018 adev->gfx.config.max_backends_per_se = 1; 2019 break; 2020 } 2021 2022 adev->gfx.config.max_texture_channel_caches = 2; 2023 adev->gfx.config.max_gprs = 256; 2024 adev->gfx.config.max_gs_threads = 32; 2025 adev->gfx.config.max_hw_contexts = 8; 2026 2027 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2028 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2029 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2030 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 2031 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; 2032 break; 2033 default: 2034 adev->gfx.config.max_shader_engines = 2; 2035 adev->gfx.config.max_tile_pipes = 4; 2036 adev->gfx.config.max_cu_per_sh = 2; 2037 adev->gfx.config.max_sh_per_se = 1; 2038 adev->gfx.config.max_backends_per_se = 2; 2039 adev->gfx.config.max_texture_channel_caches = 4; 2040 adev->gfx.config.max_gprs = 256; 2041 adev->gfx.config.max_gs_threads = 32; 2042 adev->gfx.config.max_hw_contexts = 8; 2043 2044 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2045 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2046 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2047 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 2048 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; 2049 break; 2050 } 2051 2052 tmp = RREG32(mmGRBM_CNTL); 2053 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); 2054 WREG32(mmGRBM_CNTL, tmp); 2055 2056 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 2057 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 2058 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 2059 2060 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 2061 adev->gfx.config.mem_max_burst_length_bytes = 256; 2062 if (adev->flags & AMDGPU_IS_APU) { 2063 /* Get memory bank mapping mode. */ 2064 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 2065 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 2066 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 2067 2068 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 2069 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 2070 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 2071 2072 /* Validate settings in case only one DIMM installed. */ 2073 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 2074 dimm00_addr_map = 0; 2075 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 2076 dimm01_addr_map = 0; 2077 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 2078 dimm10_addr_map = 0; 2079 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 2080 dimm11_addr_map = 0; 2081 2082 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 2083 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 2084 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 2085 adev->gfx.config.mem_row_size_in_kb = 2; 2086 else 2087 adev->gfx.config.mem_row_size_in_kb = 1; 2088 } else { 2089 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); 2090 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 2091 if (adev->gfx.config.mem_row_size_in_kb > 4) 2092 adev->gfx.config.mem_row_size_in_kb = 4; 2093 } 2094 2095 adev->gfx.config.shader_engine_tile_size = 32; 2096 adev->gfx.config.num_gpus = 1; 2097 adev->gfx.config.multi_gpu_tile_size = 64; 2098 2099 /* fix up row size */ 2100 switch (adev->gfx.config.mem_row_size_in_kb) { 2101 case 1: 2102 default: 2103 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); 2104 break; 2105 case 2: 2106 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); 2107 break; 2108 case 4: 2109 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); 2110 break; 2111 } 2112 adev->gfx.config.gb_addr_config = gb_addr_config; 2113 2114 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 2115 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 2116 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 2117 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, 2118 gb_addr_config & 0x70); 2119 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, 2120 gb_addr_config & 0x70); 2121 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 2122 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 2123 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 2124 2125 gfx_v8_0_tiling_mode_table_init(adev); 2126 2127 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, 2128 adev->gfx.config.max_sh_per_se, 2129 adev->gfx.config.max_backends_per_se); 2130 2131 /* XXX SH_MEM regs */ 2132 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2133 mutex_lock(&adev->srbm_mutex); 2134 for (i = 0; i < 16; i++) { 2135 vi_srbm_select(adev, 0, 0, 0, i); 2136 /* CP and shaders */ 2137 if (i == 0) { 2138 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); 2139 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); 2140 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 2141 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2142 WREG32(mmSH_MEM_CONFIG, tmp); 2143 } else { 2144 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); 2145 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); 2146 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 2147 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2148 WREG32(mmSH_MEM_CONFIG, tmp); 2149 } 2150 2151 WREG32(mmSH_MEM_APE1_BASE, 1); 2152 WREG32(mmSH_MEM_APE1_LIMIT, 0); 2153 WREG32(mmSH_MEM_BASES, 0); 2154 } 2155 vi_srbm_select(adev, 0, 0, 0, 0); 2156 mutex_unlock(&adev->srbm_mutex); 2157 2158 gmc_v8_0_init_compute_vmid(adev); 2159 2160 mutex_lock(&adev->grbm_idx_mutex); 2161 /* 2162 * making sure that the following register writes will be broadcasted 2163 * to all the shaders 2164 */ 2165 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2166 2167 WREG32(mmPA_SC_FIFO_SIZE, 2168 (adev->gfx.config.sc_prim_fifo_size_frontend << 2169 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 2170 (adev->gfx.config.sc_prim_fifo_size_backend << 2171 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 2172 (adev->gfx.config.sc_hiz_tile_fifo_size << 2173 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 2174 (adev->gfx.config.sc_earlyz_tile_fifo_size << 2175 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); 2176 mutex_unlock(&adev->grbm_idx_mutex); 2177 2178 } 2179 2180 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2181 { 2182 u32 i, j, k; 2183 u32 mask; 2184 2185 mutex_lock(&adev->grbm_idx_mutex); 2186 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2187 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2188 gfx_v8_0_select_se_sh(adev, i, j); 2189 for (k = 0; k < adev->usec_timeout; k++) { 2190 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2191 break; 2192 udelay(1); 2193 } 2194 } 2195 } 2196 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 2197 mutex_unlock(&adev->grbm_idx_mutex); 2198 2199 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2200 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2201 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2202 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2203 for (k = 0; k < adev->usec_timeout; k++) { 2204 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2205 break; 2206 udelay(1); 2207 } 2208 } 2209 2210 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2211 bool enable) 2212 { 2213 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2214 2215 if (enable) { 2216 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1); 2217 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1); 2218 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1); 2219 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1); 2220 } else { 2221 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0); 2222 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0); 2223 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0); 2224 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0); 2225 } 2226 WREG32(mmCP_INT_CNTL_RING0, tmp); 2227 } 2228 2229 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) 2230 { 2231 u32 tmp = RREG32(mmRLC_CNTL); 2232 2233 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 2234 WREG32(mmRLC_CNTL, tmp); 2235 2236 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 2237 2238 gfx_v8_0_wait_for_rlc_serdes(adev); 2239 } 2240 2241 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) 2242 { 2243 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 2244 2245 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2246 WREG32(mmGRBM_SOFT_RESET, tmp); 2247 udelay(50); 2248 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2249 WREG32(mmGRBM_SOFT_RESET, tmp); 2250 udelay(50); 2251 } 2252 2253 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) 2254 { 2255 u32 tmp = RREG32(mmRLC_CNTL); 2256 2257 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1); 2258 WREG32(mmRLC_CNTL, tmp); 2259 2260 /* carrizo do enable cp interrupt after cp inited */ 2261 if (adev->asic_type != CHIP_CARRIZO) 2262 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 2263 2264 udelay(50); 2265 } 2266 2267 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev) 2268 { 2269 const struct rlc_firmware_header_v2_0 *hdr; 2270 const __le32 *fw_data; 2271 unsigned i, fw_size; 2272 2273 if (!adev->gfx.rlc_fw) 2274 return -EINVAL; 2275 2276 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2277 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2278 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 2279 2280 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2281 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2282 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2283 2284 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 2285 for (i = 0; i < fw_size; i++) 2286 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2287 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2288 2289 return 0; 2290 } 2291 2292 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) 2293 { 2294 int r; 2295 2296 gfx_v8_0_rlc_stop(adev); 2297 2298 /* disable CG */ 2299 WREG32(mmRLC_CGCG_CGLS_CTRL, 0); 2300 2301 /* disable PG */ 2302 WREG32(mmRLC_PG_CNTL, 0); 2303 2304 gfx_v8_0_rlc_reset(adev); 2305 2306 if (!adev->firmware.smu_load) { 2307 /* legacy rlc firmware loading */ 2308 r = gfx_v8_0_rlc_load_microcode(adev); 2309 if (r) 2310 return r; 2311 } else { 2312 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 2313 AMDGPU_UCODE_ID_RLC_G); 2314 if (r) 2315 return -EINVAL; 2316 } 2317 2318 gfx_v8_0_rlc_start(adev); 2319 2320 return 0; 2321 } 2322 2323 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2324 { 2325 int i; 2326 u32 tmp = RREG32(mmCP_ME_CNTL); 2327 2328 if (enable) { 2329 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); 2330 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); 2331 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); 2332 } else { 2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); 2334 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); 2335 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); 2336 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2337 adev->gfx.gfx_ring[i].ready = false; 2338 } 2339 WREG32(mmCP_ME_CNTL, tmp); 2340 udelay(50); 2341 } 2342 2343 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2344 { 2345 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2346 const struct gfx_firmware_header_v1_0 *ce_hdr; 2347 const struct gfx_firmware_header_v1_0 *me_hdr; 2348 const __le32 *fw_data; 2349 unsigned i, fw_size; 2350 2351 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2352 return -EINVAL; 2353 2354 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2355 adev->gfx.pfp_fw->data; 2356 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2357 adev->gfx.ce_fw->data; 2358 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2359 adev->gfx.me_fw->data; 2360 2361 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2362 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2363 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2364 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2365 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2366 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2367 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2368 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2369 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2370 2371 gfx_v8_0_cp_gfx_enable(adev, false); 2372 2373 /* PFP */ 2374 fw_data = (const __le32 *) 2375 (adev->gfx.pfp_fw->data + 2376 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2377 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2378 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2379 for (i = 0; i < fw_size; i++) 2380 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2381 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2382 2383 /* CE */ 2384 fw_data = (const __le32 *) 2385 (adev->gfx.ce_fw->data + 2386 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2387 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2388 WREG32(mmCP_CE_UCODE_ADDR, 0); 2389 for (i = 0; i < fw_size; i++) 2390 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2391 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2392 2393 /* ME */ 2394 fw_data = (const __le32 *) 2395 (adev->gfx.me_fw->data + 2396 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2397 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2398 WREG32(mmCP_ME_RAM_WADDR, 0); 2399 for (i = 0; i < fw_size; i++) 2400 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2401 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2402 2403 return 0; 2404 } 2405 2406 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) 2407 { 2408 u32 count = 0; 2409 const struct cs_section_def *sect = NULL; 2410 const struct cs_extent_def *ext = NULL; 2411 2412 /* begin clear state */ 2413 count += 2; 2414 /* context control state */ 2415 count += 3; 2416 2417 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 2418 for (ext = sect->section; ext->extent != NULL; ++ext) { 2419 if (sect->id == SECT_CONTEXT) 2420 count += 2 + ext->reg_count; 2421 else 2422 return 0; 2423 } 2424 } 2425 /* pa_sc_raster_config/pa_sc_raster_config1 */ 2426 count += 4; 2427 /* end clear state */ 2428 count += 2; 2429 /* clear state */ 2430 count += 2; 2431 2432 return count; 2433 } 2434 2435 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) 2436 { 2437 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2438 const struct cs_section_def *sect = NULL; 2439 const struct cs_extent_def *ext = NULL; 2440 int r, i; 2441 2442 /* init the CP */ 2443 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2444 WREG32(mmCP_ENDIAN_SWAP, 0); 2445 WREG32(mmCP_DEVICE_ID, 1); 2446 2447 gfx_v8_0_cp_gfx_enable(adev, true); 2448 2449 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4); 2450 if (r) { 2451 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2452 return r; 2453 } 2454 2455 /* clear state buffer */ 2456 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2457 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2458 2459 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2460 amdgpu_ring_write(ring, 0x80000000); 2461 amdgpu_ring_write(ring, 0x80000000); 2462 2463 for (sect = vi_cs_data; sect->section != NULL; ++sect) { 2464 for (ext = sect->section; ext->extent != NULL; ++ext) { 2465 if (sect->id == SECT_CONTEXT) { 2466 amdgpu_ring_write(ring, 2467 PACKET3(PACKET3_SET_CONTEXT_REG, 2468 ext->reg_count)); 2469 amdgpu_ring_write(ring, 2470 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2471 for (i = 0; i < ext->reg_count; i++) 2472 amdgpu_ring_write(ring, ext->extent[i]); 2473 } 2474 } 2475 } 2476 2477 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2478 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2479 switch (adev->asic_type) { 2480 case CHIP_TONGA: 2481 amdgpu_ring_write(ring, 0x16000012); 2482 amdgpu_ring_write(ring, 0x0000002A); 2483 break; 2484 case CHIP_TOPAZ: 2485 case CHIP_CARRIZO: 2486 amdgpu_ring_write(ring, 0x00000002); 2487 amdgpu_ring_write(ring, 0x00000000); 2488 break; 2489 default: 2490 BUG(); 2491 } 2492 2493 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2494 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2495 2496 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2497 amdgpu_ring_write(ring, 0); 2498 2499 /* init the CE partitions */ 2500 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2501 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2502 amdgpu_ring_write(ring, 0x8000); 2503 amdgpu_ring_write(ring, 0x8000); 2504 2505 amdgpu_ring_unlock_commit(ring); 2506 2507 return 0; 2508 } 2509 2510 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) 2511 { 2512 struct amdgpu_ring *ring; 2513 u32 tmp; 2514 u32 rb_bufsz; 2515 u64 rb_addr, rptr_addr; 2516 int r; 2517 2518 /* Set the write pointer delay */ 2519 WREG32(mmCP_RB_WPTR_DELAY, 0); 2520 2521 /* set the RB to use vmid 0 */ 2522 WREG32(mmCP_RB_VMID, 0); 2523 2524 /* Set ring buffer size */ 2525 ring = &adev->gfx.gfx_ring[0]; 2526 rb_bufsz = order_base_2(ring->ring_size / 8); 2527 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2528 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2529 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3); 2530 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1); 2531 #ifdef __BIG_ENDIAN 2532 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2533 #endif 2534 WREG32(mmCP_RB0_CNTL, tmp); 2535 2536 /* Initialize the ring buffer's read and write pointers */ 2537 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2538 ring->wptr = 0; 2539 WREG32(mmCP_RB0_WPTR, ring->wptr); 2540 2541 /* set the wb address wether it's enabled or not */ 2542 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2543 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2544 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2545 2546 mdelay(1); 2547 WREG32(mmCP_RB0_CNTL, tmp); 2548 2549 rb_addr = ring->gpu_addr >> 8; 2550 WREG32(mmCP_RB0_BASE, rb_addr); 2551 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2552 2553 /* no gfx doorbells on iceland */ 2554 if (adev->asic_type != CHIP_TOPAZ) { 2555 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL); 2556 if (ring->use_doorbell) { 2557 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2558 DOORBELL_OFFSET, ring->doorbell_index); 2559 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2560 DOORBELL_EN, 1); 2561 } else { 2562 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2563 DOORBELL_EN, 0); 2564 } 2565 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp); 2566 2567 if (adev->asic_type == CHIP_TONGA) { 2568 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2569 DOORBELL_RANGE_LOWER, 2570 AMDGPU_DOORBELL_GFX_RING0); 2571 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2572 2573 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER, 2574 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2575 } 2576 2577 } 2578 2579 /* start the ring */ 2580 gfx_v8_0_cp_gfx_start(adev); 2581 ring->ready = true; 2582 r = amdgpu_ring_test_ring(ring); 2583 if (r) { 2584 ring->ready = false; 2585 return r; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2592 { 2593 int i; 2594 2595 if (enable) { 2596 WREG32(mmCP_MEC_CNTL, 0); 2597 } else { 2598 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2599 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2600 adev->gfx.compute_ring[i].ready = false; 2601 } 2602 udelay(50); 2603 } 2604 2605 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev) 2606 { 2607 gfx_v8_0_cp_compute_enable(adev, true); 2608 2609 return 0; 2610 } 2611 2612 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2613 { 2614 const struct gfx_firmware_header_v1_0 *mec_hdr; 2615 const __le32 *fw_data; 2616 unsigned i, fw_size; 2617 2618 if (!adev->gfx.mec_fw) 2619 return -EINVAL; 2620 2621 gfx_v8_0_cp_compute_enable(adev, false); 2622 2623 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2624 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2625 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2626 2627 fw_data = (const __le32 *) 2628 (adev->gfx.mec_fw->data + 2629 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2630 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2631 2632 /* MEC1 */ 2633 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2634 for (i = 0; i < fw_size; i++) 2635 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i)); 2636 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2637 2638 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2639 if (adev->gfx.mec2_fw) { 2640 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2641 2642 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2643 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2644 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2645 2646 fw_data = (const __le32 *) 2647 (adev->gfx.mec2_fw->data + 2648 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2649 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2650 2651 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2652 for (i = 0; i < fw_size; i++) 2653 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i)); 2654 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); 2655 } 2656 2657 return 0; 2658 } 2659 2660 struct vi_mqd { 2661 uint32_t header; /* ordinal0 */ 2662 uint32_t compute_dispatch_initiator; /* ordinal1 */ 2663 uint32_t compute_dim_x; /* ordinal2 */ 2664 uint32_t compute_dim_y; /* ordinal3 */ 2665 uint32_t compute_dim_z; /* ordinal4 */ 2666 uint32_t compute_start_x; /* ordinal5 */ 2667 uint32_t compute_start_y; /* ordinal6 */ 2668 uint32_t compute_start_z; /* ordinal7 */ 2669 uint32_t compute_num_thread_x; /* ordinal8 */ 2670 uint32_t compute_num_thread_y; /* ordinal9 */ 2671 uint32_t compute_num_thread_z; /* ordinal10 */ 2672 uint32_t compute_pipelinestat_enable; /* ordinal11 */ 2673 uint32_t compute_perfcount_enable; /* ordinal12 */ 2674 uint32_t compute_pgm_lo; /* ordinal13 */ 2675 uint32_t compute_pgm_hi; /* ordinal14 */ 2676 uint32_t compute_tba_lo; /* ordinal15 */ 2677 uint32_t compute_tba_hi; /* ordinal16 */ 2678 uint32_t compute_tma_lo; /* ordinal17 */ 2679 uint32_t compute_tma_hi; /* ordinal18 */ 2680 uint32_t compute_pgm_rsrc1; /* ordinal19 */ 2681 uint32_t compute_pgm_rsrc2; /* ordinal20 */ 2682 uint32_t compute_vmid; /* ordinal21 */ 2683 uint32_t compute_resource_limits; /* ordinal22 */ 2684 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */ 2685 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */ 2686 uint32_t compute_tmpring_size; /* ordinal25 */ 2687 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */ 2688 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */ 2689 uint32_t compute_restart_x; /* ordinal28 */ 2690 uint32_t compute_restart_y; /* ordinal29 */ 2691 uint32_t compute_restart_z; /* ordinal30 */ 2692 uint32_t compute_thread_trace_enable; /* ordinal31 */ 2693 uint32_t compute_misc_reserved; /* ordinal32 */ 2694 uint32_t compute_dispatch_id; /* ordinal33 */ 2695 uint32_t compute_threadgroup_id; /* ordinal34 */ 2696 uint32_t compute_relaunch; /* ordinal35 */ 2697 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */ 2698 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */ 2699 uint32_t compute_wave_restore_control; /* ordinal38 */ 2700 uint32_t reserved9; /* ordinal39 */ 2701 uint32_t reserved10; /* ordinal40 */ 2702 uint32_t reserved11; /* ordinal41 */ 2703 uint32_t reserved12; /* ordinal42 */ 2704 uint32_t reserved13; /* ordinal43 */ 2705 uint32_t reserved14; /* ordinal44 */ 2706 uint32_t reserved15; /* ordinal45 */ 2707 uint32_t reserved16; /* ordinal46 */ 2708 uint32_t reserved17; /* ordinal47 */ 2709 uint32_t reserved18; /* ordinal48 */ 2710 uint32_t reserved19; /* ordinal49 */ 2711 uint32_t reserved20; /* ordinal50 */ 2712 uint32_t reserved21; /* ordinal51 */ 2713 uint32_t reserved22; /* ordinal52 */ 2714 uint32_t reserved23; /* ordinal53 */ 2715 uint32_t reserved24; /* ordinal54 */ 2716 uint32_t reserved25; /* ordinal55 */ 2717 uint32_t reserved26; /* ordinal56 */ 2718 uint32_t reserved27; /* ordinal57 */ 2719 uint32_t reserved28; /* ordinal58 */ 2720 uint32_t reserved29; /* ordinal59 */ 2721 uint32_t reserved30; /* ordinal60 */ 2722 uint32_t reserved31; /* ordinal61 */ 2723 uint32_t reserved32; /* ordinal62 */ 2724 uint32_t reserved33; /* ordinal63 */ 2725 uint32_t reserved34; /* ordinal64 */ 2726 uint32_t compute_user_data_0; /* ordinal65 */ 2727 uint32_t compute_user_data_1; /* ordinal66 */ 2728 uint32_t compute_user_data_2; /* ordinal67 */ 2729 uint32_t compute_user_data_3; /* ordinal68 */ 2730 uint32_t compute_user_data_4; /* ordinal69 */ 2731 uint32_t compute_user_data_5; /* ordinal70 */ 2732 uint32_t compute_user_data_6; /* ordinal71 */ 2733 uint32_t compute_user_data_7; /* ordinal72 */ 2734 uint32_t compute_user_data_8; /* ordinal73 */ 2735 uint32_t compute_user_data_9; /* ordinal74 */ 2736 uint32_t compute_user_data_10; /* ordinal75 */ 2737 uint32_t compute_user_data_11; /* ordinal76 */ 2738 uint32_t compute_user_data_12; /* ordinal77 */ 2739 uint32_t compute_user_data_13; /* ordinal78 */ 2740 uint32_t compute_user_data_14; /* ordinal79 */ 2741 uint32_t compute_user_data_15; /* ordinal80 */ 2742 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */ 2743 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */ 2744 uint32_t reserved35; /* ordinal83 */ 2745 uint32_t reserved36; /* ordinal84 */ 2746 uint32_t reserved37; /* ordinal85 */ 2747 uint32_t cp_mqd_query_time_lo; /* ordinal86 */ 2748 uint32_t cp_mqd_query_time_hi; /* ordinal87 */ 2749 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */ 2750 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */ 2751 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */ 2752 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */ 2753 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */ 2754 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */ 2755 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */ 2756 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */ 2757 uint32_t reserved38; /* ordinal96 */ 2758 uint32_t reserved39; /* ordinal97 */ 2759 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */ 2760 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */ 2761 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */ 2762 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */ 2763 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */ 2764 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */ 2765 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */ 2766 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */ 2767 uint32_t reserved40; /* ordinal106 */ 2768 uint32_t reserved41; /* ordinal107 */ 2769 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */ 2770 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */ 2771 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */ 2772 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */ 2773 uint32_t reserved42; /* ordinal112 */ 2774 uint32_t reserved43; /* ordinal113 */ 2775 uint32_t cp_pq_exe_status_lo; /* ordinal114 */ 2776 uint32_t cp_pq_exe_status_hi; /* ordinal115 */ 2777 uint32_t cp_packet_id_lo; /* ordinal116 */ 2778 uint32_t cp_packet_id_hi; /* ordinal117 */ 2779 uint32_t cp_packet_exe_status_lo; /* ordinal118 */ 2780 uint32_t cp_packet_exe_status_hi; /* ordinal119 */ 2781 uint32_t gds_save_base_addr_lo; /* ordinal120 */ 2782 uint32_t gds_save_base_addr_hi; /* ordinal121 */ 2783 uint32_t gds_save_mask_lo; /* ordinal122 */ 2784 uint32_t gds_save_mask_hi; /* ordinal123 */ 2785 uint32_t ctx_save_base_addr_lo; /* ordinal124 */ 2786 uint32_t ctx_save_base_addr_hi; /* ordinal125 */ 2787 uint32_t reserved44; /* ordinal126 */ 2788 uint32_t reserved45; /* ordinal127 */ 2789 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */ 2790 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */ 2791 uint32_t cp_hqd_active; /* ordinal130 */ 2792 uint32_t cp_hqd_vmid; /* ordinal131 */ 2793 uint32_t cp_hqd_persistent_state; /* ordinal132 */ 2794 uint32_t cp_hqd_pipe_priority; /* ordinal133 */ 2795 uint32_t cp_hqd_queue_priority; /* ordinal134 */ 2796 uint32_t cp_hqd_quantum; /* ordinal135 */ 2797 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */ 2798 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */ 2799 uint32_t cp_hqd_pq_rptr; /* ordinal138 */ 2800 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */ 2801 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */ 2802 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */ 2803 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */ 2804 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */ 2805 uint32_t cp_hqd_pq_wptr; /* ordinal144 */ 2806 uint32_t cp_hqd_pq_control; /* ordinal145 */ 2807 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */ 2808 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */ 2809 uint32_t cp_hqd_ib_rptr; /* ordinal148 */ 2810 uint32_t cp_hqd_ib_control; /* ordinal149 */ 2811 uint32_t cp_hqd_iq_timer; /* ordinal150 */ 2812 uint32_t cp_hqd_iq_rptr; /* ordinal151 */ 2813 uint32_t cp_hqd_dequeue_request; /* ordinal152 */ 2814 uint32_t cp_hqd_dma_offload; /* ordinal153 */ 2815 uint32_t cp_hqd_sema_cmd; /* ordinal154 */ 2816 uint32_t cp_hqd_msg_type; /* ordinal155 */ 2817 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */ 2818 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */ 2819 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */ 2820 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */ 2821 uint32_t cp_hqd_hq_status0; /* ordinal160 */ 2822 uint32_t cp_hqd_hq_control0; /* ordinal161 */ 2823 uint32_t cp_mqd_control; /* ordinal162 */ 2824 uint32_t cp_hqd_hq_status1; /* ordinal163 */ 2825 uint32_t cp_hqd_hq_control1; /* ordinal164 */ 2826 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */ 2827 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */ 2828 uint32_t cp_hqd_eop_control; /* ordinal167 */ 2829 uint32_t cp_hqd_eop_rptr; /* ordinal168 */ 2830 uint32_t cp_hqd_eop_wptr; /* ordinal169 */ 2831 uint32_t cp_hqd_eop_done_events; /* ordinal170 */ 2832 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */ 2833 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */ 2834 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */ 2835 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */ 2836 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */ 2837 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */ 2838 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */ 2839 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */ 2840 uint32_t cp_hqd_error; /* ordinal179 */ 2841 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */ 2842 uint32_t cp_hqd_eop_dones; /* ordinal181 */ 2843 uint32_t reserved46; /* ordinal182 */ 2844 uint32_t reserved47; /* ordinal183 */ 2845 uint32_t reserved48; /* ordinal184 */ 2846 uint32_t reserved49; /* ordinal185 */ 2847 uint32_t reserved50; /* ordinal186 */ 2848 uint32_t reserved51; /* ordinal187 */ 2849 uint32_t reserved52; /* ordinal188 */ 2850 uint32_t reserved53; /* ordinal189 */ 2851 uint32_t reserved54; /* ordinal190 */ 2852 uint32_t reserved55; /* ordinal191 */ 2853 uint32_t iqtimer_pkt_header; /* ordinal192 */ 2854 uint32_t iqtimer_pkt_dw0; /* ordinal193 */ 2855 uint32_t iqtimer_pkt_dw1; /* ordinal194 */ 2856 uint32_t iqtimer_pkt_dw2; /* ordinal195 */ 2857 uint32_t iqtimer_pkt_dw3; /* ordinal196 */ 2858 uint32_t iqtimer_pkt_dw4; /* ordinal197 */ 2859 uint32_t iqtimer_pkt_dw5; /* ordinal198 */ 2860 uint32_t iqtimer_pkt_dw6; /* ordinal199 */ 2861 uint32_t iqtimer_pkt_dw7; /* ordinal200 */ 2862 uint32_t iqtimer_pkt_dw8; /* ordinal201 */ 2863 uint32_t iqtimer_pkt_dw9; /* ordinal202 */ 2864 uint32_t iqtimer_pkt_dw10; /* ordinal203 */ 2865 uint32_t iqtimer_pkt_dw11; /* ordinal204 */ 2866 uint32_t iqtimer_pkt_dw12; /* ordinal205 */ 2867 uint32_t iqtimer_pkt_dw13; /* ordinal206 */ 2868 uint32_t iqtimer_pkt_dw14; /* ordinal207 */ 2869 uint32_t iqtimer_pkt_dw15; /* ordinal208 */ 2870 uint32_t iqtimer_pkt_dw16; /* ordinal209 */ 2871 uint32_t iqtimer_pkt_dw17; /* ordinal210 */ 2872 uint32_t iqtimer_pkt_dw18; /* ordinal211 */ 2873 uint32_t iqtimer_pkt_dw19; /* ordinal212 */ 2874 uint32_t iqtimer_pkt_dw20; /* ordinal213 */ 2875 uint32_t iqtimer_pkt_dw21; /* ordinal214 */ 2876 uint32_t iqtimer_pkt_dw22; /* ordinal215 */ 2877 uint32_t iqtimer_pkt_dw23; /* ordinal216 */ 2878 uint32_t iqtimer_pkt_dw24; /* ordinal217 */ 2879 uint32_t iqtimer_pkt_dw25; /* ordinal218 */ 2880 uint32_t iqtimer_pkt_dw26; /* ordinal219 */ 2881 uint32_t iqtimer_pkt_dw27; /* ordinal220 */ 2882 uint32_t iqtimer_pkt_dw28; /* ordinal221 */ 2883 uint32_t iqtimer_pkt_dw29; /* ordinal222 */ 2884 uint32_t iqtimer_pkt_dw30; /* ordinal223 */ 2885 uint32_t iqtimer_pkt_dw31; /* ordinal224 */ 2886 uint32_t reserved56; /* ordinal225 */ 2887 uint32_t reserved57; /* ordinal226 */ 2888 uint32_t reserved58; /* ordinal227 */ 2889 uint32_t set_resources_header; /* ordinal228 */ 2890 uint32_t set_resources_dw1; /* ordinal229 */ 2891 uint32_t set_resources_dw2; /* ordinal230 */ 2892 uint32_t set_resources_dw3; /* ordinal231 */ 2893 uint32_t set_resources_dw4; /* ordinal232 */ 2894 uint32_t set_resources_dw5; /* ordinal233 */ 2895 uint32_t set_resources_dw6; /* ordinal234 */ 2896 uint32_t set_resources_dw7; /* ordinal235 */ 2897 uint32_t reserved59; /* ordinal236 */ 2898 uint32_t reserved60; /* ordinal237 */ 2899 uint32_t reserved61; /* ordinal238 */ 2900 uint32_t reserved62; /* ordinal239 */ 2901 uint32_t reserved63; /* ordinal240 */ 2902 uint32_t reserved64; /* ordinal241 */ 2903 uint32_t reserved65; /* ordinal242 */ 2904 uint32_t reserved66; /* ordinal243 */ 2905 uint32_t reserved67; /* ordinal244 */ 2906 uint32_t reserved68; /* ordinal245 */ 2907 uint32_t reserved69; /* ordinal246 */ 2908 uint32_t reserved70; /* ordinal247 */ 2909 uint32_t reserved71; /* ordinal248 */ 2910 uint32_t reserved72; /* ordinal249 */ 2911 uint32_t reserved73; /* ordinal250 */ 2912 uint32_t reserved74; /* ordinal251 */ 2913 uint32_t reserved75; /* ordinal252 */ 2914 uint32_t reserved76; /* ordinal253 */ 2915 uint32_t reserved77; /* ordinal254 */ 2916 uint32_t reserved78; /* ordinal255 */ 2917 2918 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */ 2919 }; 2920 2921 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) 2922 { 2923 int i, r; 2924 2925 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2926 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2927 2928 if (ring->mqd_obj) { 2929 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2930 if (unlikely(r != 0)) 2931 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 2932 2933 amdgpu_bo_unpin(ring->mqd_obj); 2934 amdgpu_bo_unreserve(ring->mqd_obj); 2935 2936 amdgpu_bo_unref(&ring->mqd_obj); 2937 ring->mqd_obj = NULL; 2938 } 2939 } 2940 } 2941 2942 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) 2943 { 2944 int r, i, j; 2945 u32 tmp; 2946 bool use_doorbell = true; 2947 u64 hqd_gpu_addr; 2948 u64 mqd_gpu_addr; 2949 u64 eop_gpu_addr; 2950 u64 wb_gpu_addr; 2951 u32 *buf; 2952 struct vi_mqd *mqd; 2953 2954 /* init the pipes */ 2955 mutex_lock(&adev->srbm_mutex); 2956 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 2957 int me = (i < 4) ? 1 : 2; 2958 int pipe = (i < 4) ? i : (i - 4); 2959 2960 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); 2961 eop_gpu_addr >>= 8; 2962 2963 vi_srbm_select(adev, me, pipe, 0, 0); 2964 2965 /* write the EOP addr */ 2966 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr); 2967 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr)); 2968 2969 /* set the VMID assigned */ 2970 WREG32(mmCP_HQD_VMID, 0); 2971 2972 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2973 tmp = RREG32(mmCP_HQD_EOP_CONTROL); 2974 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2975 (order_base_2(MEC_HPD_SIZE / 4) - 1)); 2976 WREG32(mmCP_HQD_EOP_CONTROL, tmp); 2977 } 2978 vi_srbm_select(adev, 0, 0, 0, 0); 2979 mutex_unlock(&adev->srbm_mutex); 2980 2981 /* init the queues. Just two for now. */ 2982 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2983 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2984 2985 if (ring->mqd_obj == NULL) { 2986 r = amdgpu_bo_create(adev, 2987 sizeof(struct vi_mqd), 2988 PAGE_SIZE, true, 2989 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, 2990 &ring->mqd_obj); 2991 if (r) { 2992 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 2993 return r; 2994 } 2995 } 2996 2997 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2998 if (unlikely(r != 0)) { 2999 gfx_v8_0_cp_compute_fini(adev); 3000 return r; 3001 } 3002 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 3003 &mqd_gpu_addr); 3004 if (r) { 3005 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 3006 gfx_v8_0_cp_compute_fini(adev); 3007 return r; 3008 } 3009 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 3010 if (r) { 3011 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 3012 gfx_v8_0_cp_compute_fini(adev); 3013 return r; 3014 } 3015 3016 /* init the mqd struct */ 3017 memset(buf, 0, sizeof(struct vi_mqd)); 3018 3019 mqd = (struct vi_mqd *)buf; 3020 mqd->header = 0xC0310800; 3021 mqd->compute_pipelinestat_enable = 0x00000001; 3022 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3023 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3024 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3025 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3026 mqd->compute_misc_reserved = 0x00000003; 3027 3028 mutex_lock(&adev->srbm_mutex); 3029 vi_srbm_select(adev, ring->me, 3030 ring->pipe, 3031 ring->queue, 0); 3032 3033 /* disable wptr polling */ 3034 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3035 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3036 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3037 3038 mqd->cp_hqd_eop_base_addr_lo = 3039 RREG32(mmCP_HQD_EOP_BASE_ADDR); 3040 mqd->cp_hqd_eop_base_addr_hi = 3041 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI); 3042 3043 /* enable doorbell? */ 3044 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3045 if (use_doorbell) { 3046 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 3047 } else { 3048 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0); 3049 } 3050 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp); 3051 mqd->cp_hqd_pq_doorbell_control = tmp; 3052 3053 /* disable the queue if it's active */ 3054 mqd->cp_hqd_dequeue_request = 0; 3055 mqd->cp_hqd_pq_rptr = 0; 3056 mqd->cp_hqd_pq_wptr= 0; 3057 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 3058 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 3059 for (j = 0; j < adev->usec_timeout; j++) { 3060 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 3061 break; 3062 udelay(1); 3063 } 3064 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request); 3065 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr); 3066 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); 3067 } 3068 3069 /* set the pointer to the MQD */ 3070 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 3071 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3072 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 3073 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3074 3075 /* set MQD vmid to 0 */ 3076 tmp = RREG32(mmCP_MQD_CONTROL); 3077 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3078 WREG32(mmCP_MQD_CONTROL, tmp); 3079 mqd->cp_mqd_control = tmp; 3080 3081 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3082 hqd_gpu_addr = ring->gpu_addr >> 8; 3083 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3084 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3085 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 3086 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 3087 3088 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3089 tmp = RREG32(mmCP_HQD_PQ_CONTROL); 3090 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3091 (order_base_2(ring->ring_size / 4) - 1)); 3092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3093 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3094 #ifdef __BIG_ENDIAN 3095 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3096 #endif 3097 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3098 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3099 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3100 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3101 WREG32(mmCP_HQD_PQ_CONTROL, tmp); 3102 mqd->cp_hqd_pq_control = tmp; 3103 3104 /* set the wb address wether it's enabled or not */ 3105 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3106 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3107 mqd->cp_hqd_pq_rptr_report_addr_hi = 3108 upper_32_bits(wb_gpu_addr) & 0xffff; 3109 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3110 mqd->cp_hqd_pq_rptr_report_addr_lo); 3111 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3112 mqd->cp_hqd_pq_rptr_report_addr_hi); 3113 3114 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3115 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3116 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 3117 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3118 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); 3119 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3120 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3121 3122 /* enable the doorbell if requested */ 3123 if (use_doorbell) { 3124 if (adev->asic_type == CHIP_CARRIZO) { 3125 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, 3126 AMDGPU_DOORBELL_KIQ << 2); 3127 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, 3128 0x7FFFF << 2); 3129 } 3130 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3132 DOORBELL_OFFSET, ring->doorbell_index); 3133 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 3134 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0); 3135 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0); 3136 mqd->cp_hqd_pq_doorbell_control = tmp; 3137 3138 } else { 3139 mqd->cp_hqd_pq_doorbell_control = 0; 3140 } 3141 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3142 mqd->cp_hqd_pq_doorbell_control); 3143 3144 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3145 ring->wptr = 0; 3146 mqd->cp_hqd_pq_wptr = ring->wptr; 3147 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr); 3148 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3149 3150 /* set the vmid for the queue */ 3151 mqd->cp_hqd_vmid = 0; 3152 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3153 3154 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); 3155 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3156 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); 3157 mqd->cp_hqd_persistent_state = tmp; 3158 3159 /* activate the queue */ 3160 mqd->cp_hqd_active = 1; 3161 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 3162 3163 vi_srbm_select(adev, 0, 0, 0, 0); 3164 mutex_unlock(&adev->srbm_mutex); 3165 3166 amdgpu_bo_kunmap(ring->mqd_obj); 3167 amdgpu_bo_unreserve(ring->mqd_obj); 3168 } 3169 3170 if (use_doorbell) { 3171 tmp = RREG32(mmCP_PQ_STATUS); 3172 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3173 WREG32(mmCP_PQ_STATUS, tmp); 3174 } 3175 3176 r = gfx_v8_0_cp_compute_start(adev); 3177 if (r) 3178 return r; 3179 3180 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3181 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 3182 3183 ring->ready = true; 3184 r = amdgpu_ring_test_ring(ring); 3185 if (r) 3186 ring->ready = false; 3187 } 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) 3193 { 3194 int r; 3195 3196 if (adev->asic_type != CHIP_CARRIZO) 3197 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 3198 3199 if (!adev->firmware.smu_load) { 3200 /* legacy firmware loading */ 3201 r = gfx_v8_0_cp_gfx_load_microcode(adev); 3202 if (r) 3203 return r; 3204 3205 r = gfx_v8_0_cp_compute_load_microcode(adev); 3206 if (r) 3207 return r; 3208 } else { 3209 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3210 AMDGPU_UCODE_ID_CP_CE); 3211 if (r) 3212 return -EINVAL; 3213 3214 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3215 AMDGPU_UCODE_ID_CP_PFP); 3216 if (r) 3217 return -EINVAL; 3218 3219 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3220 AMDGPU_UCODE_ID_CP_ME); 3221 if (r) 3222 return -EINVAL; 3223 3224 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 3225 AMDGPU_UCODE_ID_CP_MEC1); 3226 if (r) 3227 return -EINVAL; 3228 } 3229 3230 r = gfx_v8_0_cp_gfx_resume(adev); 3231 if (r) 3232 return r; 3233 3234 r = gfx_v8_0_cp_compute_resume(adev); 3235 if (r) 3236 return r; 3237 3238 gfx_v8_0_enable_gui_idle_interrupt(adev, true); 3239 3240 return 0; 3241 } 3242 3243 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) 3244 { 3245 gfx_v8_0_cp_gfx_enable(adev, enable); 3246 gfx_v8_0_cp_compute_enable(adev, enable); 3247 } 3248 3249 static int gfx_v8_0_hw_init(void *handle) 3250 { 3251 int r; 3252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3253 3254 gfx_v8_0_init_golden_registers(adev); 3255 3256 gfx_v8_0_gpu_init(adev); 3257 3258 r = gfx_v8_0_rlc_resume(adev); 3259 if (r) 3260 return r; 3261 3262 r = gfx_v8_0_cp_resume(adev); 3263 if (r) 3264 return r; 3265 3266 return r; 3267 } 3268 3269 static int gfx_v8_0_hw_fini(void *handle) 3270 { 3271 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3272 3273 gfx_v8_0_cp_enable(adev, false); 3274 gfx_v8_0_rlc_stop(adev); 3275 gfx_v8_0_cp_compute_fini(adev); 3276 3277 return 0; 3278 } 3279 3280 static int gfx_v8_0_suspend(void *handle) 3281 { 3282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3283 3284 return gfx_v8_0_hw_fini(adev); 3285 } 3286 3287 static int gfx_v8_0_resume(void *handle) 3288 { 3289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3290 3291 return gfx_v8_0_hw_init(adev); 3292 } 3293 3294 static bool gfx_v8_0_is_idle(void *handle) 3295 { 3296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3297 3298 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 3299 return false; 3300 else 3301 return true; 3302 } 3303 3304 static int gfx_v8_0_wait_for_idle(void *handle) 3305 { 3306 unsigned i; 3307 u32 tmp; 3308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3309 3310 for (i = 0; i < adev->usec_timeout; i++) { 3311 /* read MC_STATUS */ 3312 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 3313 3314 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3315 return 0; 3316 udelay(1); 3317 } 3318 return -ETIMEDOUT; 3319 } 3320 3321 static void gfx_v8_0_print_status(void *handle) 3322 { 3323 int i; 3324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3325 3326 dev_info(adev->dev, "GFX 8.x registers\n"); 3327 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 3328 RREG32(mmGRBM_STATUS)); 3329 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 3330 RREG32(mmGRBM_STATUS2)); 3331 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 3332 RREG32(mmGRBM_STATUS_SE0)); 3333 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 3334 RREG32(mmGRBM_STATUS_SE1)); 3335 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 3336 RREG32(mmGRBM_STATUS_SE2)); 3337 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 3338 RREG32(mmGRBM_STATUS_SE3)); 3339 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 3340 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 3341 RREG32(mmCP_STALLED_STAT1)); 3342 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 3343 RREG32(mmCP_STALLED_STAT2)); 3344 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 3345 RREG32(mmCP_STALLED_STAT3)); 3346 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 3347 RREG32(mmCP_CPF_BUSY_STAT)); 3348 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 3349 RREG32(mmCP_CPF_STALLED_STAT1)); 3350 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 3351 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 3352 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 3353 RREG32(mmCP_CPC_STALLED_STAT1)); 3354 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 3355 3356 for (i = 0; i < 32; i++) { 3357 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", 3358 i, RREG32(mmGB_TILE_MODE0 + (i * 4))); 3359 } 3360 for (i = 0; i < 16; i++) { 3361 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", 3362 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); 3363 } 3364 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3365 dev_info(adev->dev, " se: %d\n", i); 3366 gfx_v8_0_select_se_sh(adev, i, 0xffffffff); 3367 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", 3368 RREG32(mmPA_SC_RASTER_CONFIG)); 3369 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", 3370 RREG32(mmPA_SC_RASTER_CONFIG_1)); 3371 } 3372 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3373 3374 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", 3375 RREG32(mmGB_ADDR_CONFIG)); 3376 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", 3377 RREG32(mmHDP_ADDR_CONFIG)); 3378 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", 3379 RREG32(mmDMIF_ADDR_CALC)); 3380 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n", 3381 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); 3382 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n", 3383 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); 3384 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 3385 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 3386 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 3387 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 3388 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 3389 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 3390 3391 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", 3392 RREG32(mmCP_MEQ_THRESHOLDS)); 3393 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", 3394 RREG32(mmSX_DEBUG_1)); 3395 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", 3396 RREG32(mmTA_CNTL_AUX)); 3397 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", 3398 RREG32(mmSPI_CONFIG_CNTL)); 3399 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", 3400 RREG32(mmSQ_CONFIG)); 3401 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", 3402 RREG32(mmDB_DEBUG)); 3403 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", 3404 RREG32(mmDB_DEBUG2)); 3405 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", 3406 RREG32(mmDB_DEBUG3)); 3407 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", 3408 RREG32(mmCB_HW_CONTROL)); 3409 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", 3410 RREG32(mmSPI_CONFIG_CNTL_1)); 3411 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", 3412 RREG32(mmPA_SC_FIFO_SIZE)); 3413 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", 3414 RREG32(mmVGT_NUM_INSTANCES)); 3415 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", 3416 RREG32(mmCP_PERFMON_CNTL)); 3417 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", 3418 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); 3419 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", 3420 RREG32(mmVGT_CACHE_INVALIDATION)); 3421 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", 3422 RREG32(mmVGT_GS_VERTEX_REUSE)); 3423 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", 3424 RREG32(mmPA_SC_LINE_STIPPLE_STATE)); 3425 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", 3426 RREG32(mmPA_CL_ENHANCE)); 3427 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", 3428 RREG32(mmPA_SC_ENHANCE)); 3429 3430 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", 3431 RREG32(mmCP_ME_CNTL)); 3432 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", 3433 RREG32(mmCP_MAX_CONTEXT)); 3434 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", 3435 RREG32(mmCP_ENDIAN_SWAP)); 3436 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", 3437 RREG32(mmCP_DEVICE_ID)); 3438 3439 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", 3440 RREG32(mmCP_SEM_WAIT_TIMER)); 3441 3442 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", 3443 RREG32(mmCP_RB_WPTR_DELAY)); 3444 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", 3445 RREG32(mmCP_RB_VMID)); 3446 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 3447 RREG32(mmCP_RB0_CNTL)); 3448 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", 3449 RREG32(mmCP_RB0_WPTR)); 3450 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", 3451 RREG32(mmCP_RB0_RPTR_ADDR)); 3452 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", 3453 RREG32(mmCP_RB0_RPTR_ADDR_HI)); 3454 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 3455 RREG32(mmCP_RB0_CNTL)); 3456 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", 3457 RREG32(mmCP_RB0_BASE)); 3458 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", 3459 RREG32(mmCP_RB0_BASE_HI)); 3460 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", 3461 RREG32(mmCP_MEC_CNTL)); 3462 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", 3463 RREG32(mmCP_CPF_DEBUG)); 3464 3465 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", 3466 RREG32(mmSCRATCH_ADDR)); 3467 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", 3468 RREG32(mmSCRATCH_UMSK)); 3469 3470 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", 3471 RREG32(mmCP_INT_CNTL_RING0)); 3472 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 3473 RREG32(mmRLC_LB_CNTL)); 3474 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", 3475 RREG32(mmRLC_CNTL)); 3476 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", 3477 RREG32(mmRLC_CGCG_CGLS_CTRL)); 3478 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", 3479 RREG32(mmRLC_LB_CNTR_INIT)); 3480 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", 3481 RREG32(mmRLC_LB_CNTR_MAX)); 3482 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", 3483 RREG32(mmRLC_LB_INIT_CU_MASK)); 3484 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", 3485 RREG32(mmRLC_LB_PARAMS)); 3486 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 3487 RREG32(mmRLC_LB_CNTL)); 3488 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", 3489 RREG32(mmRLC_MC_CNTL)); 3490 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", 3491 RREG32(mmRLC_UCODE_CNTL)); 3492 3493 mutex_lock(&adev->srbm_mutex); 3494 for (i = 0; i < 16; i++) { 3495 vi_srbm_select(adev, 0, 0, 0, i); 3496 dev_info(adev->dev, " VM %d:\n", i); 3497 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", 3498 RREG32(mmSH_MEM_CONFIG)); 3499 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", 3500 RREG32(mmSH_MEM_APE1_BASE)); 3501 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", 3502 RREG32(mmSH_MEM_APE1_LIMIT)); 3503 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", 3504 RREG32(mmSH_MEM_BASES)); 3505 } 3506 vi_srbm_select(adev, 0, 0, 0, 0); 3507 mutex_unlock(&adev->srbm_mutex); 3508 } 3509 3510 static int gfx_v8_0_soft_reset(void *handle) 3511 { 3512 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 3513 u32 tmp; 3514 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3515 3516 /* GRBM_STATUS */ 3517 tmp = RREG32(mmGRBM_STATUS); 3518 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3519 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3520 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3521 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3522 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3523 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3524 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3525 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3526 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3527 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3528 } 3529 3530 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3531 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3532 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3533 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 3534 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 3535 } 3536 3537 /* GRBM_STATUS2 */ 3538 tmp = RREG32(mmGRBM_STATUS2); 3539 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3540 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3541 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3542 3543 /* SRBM_STATUS */ 3544 tmp = RREG32(mmSRBM_STATUS); 3545 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)) 3546 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 3547 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 3548 3549 if (grbm_soft_reset || srbm_soft_reset) { 3550 gfx_v8_0_print_status((void *)adev); 3551 /* stop the rlc */ 3552 gfx_v8_0_rlc_stop(adev); 3553 3554 /* Disable GFX parsing/prefetching */ 3555 gfx_v8_0_cp_gfx_enable(adev, false); 3556 3557 /* Disable MEC parsing/prefetching */ 3558 /* XXX todo */ 3559 3560 if (grbm_soft_reset) { 3561 tmp = RREG32(mmGRBM_SOFT_RESET); 3562 tmp |= grbm_soft_reset; 3563 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3564 WREG32(mmGRBM_SOFT_RESET, tmp); 3565 tmp = RREG32(mmGRBM_SOFT_RESET); 3566 3567 udelay(50); 3568 3569 tmp &= ~grbm_soft_reset; 3570 WREG32(mmGRBM_SOFT_RESET, tmp); 3571 tmp = RREG32(mmGRBM_SOFT_RESET); 3572 } 3573 3574 if (srbm_soft_reset) { 3575 tmp = RREG32(mmSRBM_SOFT_RESET); 3576 tmp |= srbm_soft_reset; 3577 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3578 WREG32(mmSRBM_SOFT_RESET, tmp); 3579 tmp = RREG32(mmSRBM_SOFT_RESET); 3580 3581 udelay(50); 3582 3583 tmp &= ~srbm_soft_reset; 3584 WREG32(mmSRBM_SOFT_RESET, tmp); 3585 tmp = RREG32(mmSRBM_SOFT_RESET); 3586 } 3587 /* Wait a little for things to settle down */ 3588 udelay(50); 3589 gfx_v8_0_print_status((void *)adev); 3590 } 3591 return 0; 3592 } 3593 3594 /** 3595 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot 3596 * 3597 * @adev: amdgpu_device pointer 3598 * 3599 * Fetches a GPU clock counter snapshot. 3600 * Returns the 64 bit clock counter snapshot. 3601 */ 3602 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3603 { 3604 uint64_t clock; 3605 3606 mutex_lock(&adev->gfx.gpu_clock_mutex); 3607 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3608 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3609 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3610 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3611 return clock; 3612 } 3613 3614 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3615 uint32_t vmid, 3616 uint32_t gds_base, uint32_t gds_size, 3617 uint32_t gws_base, uint32_t gws_size, 3618 uint32_t oa_base, uint32_t oa_size) 3619 { 3620 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 3621 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 3622 3623 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 3624 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 3625 3626 oa_base = oa_base >> AMDGPU_OA_SHIFT; 3627 oa_size = oa_size >> AMDGPU_OA_SHIFT; 3628 3629 /* GDS Base */ 3630 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3631 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3632 WRITE_DATA_DST_SEL(0))); 3633 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 3634 amdgpu_ring_write(ring, 0); 3635 amdgpu_ring_write(ring, gds_base); 3636 3637 /* GDS Size */ 3638 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3639 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3640 WRITE_DATA_DST_SEL(0))); 3641 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 3642 amdgpu_ring_write(ring, 0); 3643 amdgpu_ring_write(ring, gds_size); 3644 3645 /* GWS */ 3646 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3647 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3648 WRITE_DATA_DST_SEL(0))); 3649 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 3650 amdgpu_ring_write(ring, 0); 3651 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3652 3653 /* OA */ 3654 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3655 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3656 WRITE_DATA_DST_SEL(0))); 3657 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 3658 amdgpu_ring_write(ring, 0); 3659 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 3660 } 3661 3662 static int gfx_v8_0_early_init(void *handle) 3663 { 3664 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3665 3666 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; 3667 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; 3668 gfx_v8_0_set_ring_funcs(adev); 3669 gfx_v8_0_set_irq_funcs(adev); 3670 gfx_v8_0_set_gds_init(adev); 3671 3672 return 0; 3673 } 3674 3675 static int gfx_v8_0_set_powergating_state(void *handle, 3676 enum amd_powergating_state state) 3677 { 3678 return 0; 3679 } 3680 3681 static int gfx_v8_0_set_clockgating_state(void *handle, 3682 enum amd_clockgating_state state) 3683 { 3684 return 0; 3685 } 3686 3687 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3688 { 3689 u32 rptr; 3690 3691 rptr = ring->adev->wb.wb[ring->rptr_offs]; 3692 3693 return rptr; 3694 } 3695 3696 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3697 { 3698 struct amdgpu_device *adev = ring->adev; 3699 u32 wptr; 3700 3701 if (ring->use_doorbell) 3702 /* XXX check if swapping is necessary on BE */ 3703 wptr = ring->adev->wb.wb[ring->wptr_offs]; 3704 else 3705 wptr = RREG32(mmCP_RB0_WPTR); 3706 3707 return wptr; 3708 } 3709 3710 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3711 { 3712 struct amdgpu_device *adev = ring->adev; 3713 3714 if (ring->use_doorbell) { 3715 /* XXX check if swapping is necessary on BE */ 3716 adev->wb.wb[ring->wptr_offs] = ring->wptr; 3717 WDOORBELL32(ring->doorbell_index, ring->wptr); 3718 } else { 3719 WREG32(mmCP_RB0_WPTR, ring->wptr); 3720 (void)RREG32(mmCP_RB0_WPTR); 3721 } 3722 } 3723 3724 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3725 { 3726 u32 ref_and_mask, reg_mem_engine; 3727 3728 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { 3729 switch (ring->me) { 3730 case 1: 3731 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 3732 break; 3733 case 2: 3734 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 3735 break; 3736 default: 3737 return; 3738 } 3739 reg_mem_engine = 0; 3740 } else { 3741 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 3742 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ 3743 } 3744 3745 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3746 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 3747 WAIT_REG_MEM_FUNCTION(3) | /* == */ 3748 reg_mem_engine)); 3749 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 3750 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 3751 amdgpu_ring_write(ring, ref_and_mask); 3752 amdgpu_ring_write(ring, ref_and_mask); 3753 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3754 } 3755 3756 static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring, 3757 struct amdgpu_ib *ib) 3758 { 3759 bool need_ctx_switch = ring->current_ctx != ib->ctx; 3760 u32 header, control = 0; 3761 u32 next_rptr = ring->wptr + 5; 3762 3763 /* drop the CE preamble IB for the same context */ 3764 if ((ring->type == AMDGPU_RING_TYPE_GFX) && 3765 (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && 3766 !need_ctx_switch) 3767 return; 3768 3769 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) 3770 control |= INDIRECT_BUFFER_VALID; 3771 3772 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) 3773 next_rptr += 2; 3774 3775 next_rptr += 4; 3776 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3777 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 3778 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3779 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 3780 amdgpu_ring_write(ring, next_rptr); 3781 3782 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 3783 if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) { 3784 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3785 amdgpu_ring_write(ring, 0); 3786 } 3787 3788 if (ib->flags & AMDGPU_IB_FLAG_CE) 3789 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3790 else 3791 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3792 3793 control |= ib->length_dw | 3794 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0); 3795 3796 amdgpu_ring_write(ring, header); 3797 amdgpu_ring_write(ring, 3798 #ifdef __BIG_ENDIAN 3799 (2 << 0) | 3800 #endif 3801 (ib->gpu_addr & 0xFFFFFFFC)); 3802 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 3803 amdgpu_ring_write(ring, control); 3804 } 3805 3806 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 3807 u64 seq, unsigned flags) 3808 { 3809 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3810 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3811 3812 /* EVENT_WRITE_EOP - flush caches, send int */ 3813 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 3814 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3815 EOP_TC_ACTION_EN | 3816 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3817 EVENT_INDEX(5))); 3818 amdgpu_ring_write(ring, addr & 0xfffffffc); 3819 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 3820 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3821 amdgpu_ring_write(ring, lower_32_bits(seq)); 3822 amdgpu_ring_write(ring, upper_32_bits(seq)); 3823 } 3824 3825 /** 3826 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring 3827 * 3828 * @ring: amdgpu ring buffer object 3829 * @semaphore: amdgpu semaphore object 3830 * @emit_wait: Is this a sempahore wait? 3831 * 3832 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP 3833 * from running ahead of semaphore waits. 3834 */ 3835 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, 3836 struct amdgpu_semaphore *semaphore, 3837 bool emit_wait) 3838 { 3839 uint64_t addr = semaphore->gpu_addr; 3840 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 3841 3842 if (ring->adev->asic_type == CHIP_TOPAZ || 3843 ring->adev->asic_type == CHIP_TONGA) 3844 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */ 3845 return false; 3846 else { 3847 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); 3848 amdgpu_ring_write(ring, lower_32_bits(addr)); 3849 amdgpu_ring_write(ring, upper_32_bits(addr)); 3850 amdgpu_ring_write(ring, sel); 3851 } 3852 3853 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { 3854 /* Prevent the PFP from running ahead of the semaphore wait */ 3855 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3856 amdgpu_ring_write(ring, 0x0); 3857 } 3858 3859 return true; 3860 } 3861 3862 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring) 3863 { 3864 struct amdgpu_device *adev = ring->adev; 3865 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4; 3866 3867 /* instruct DE to set a magic number */ 3868 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3869 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3870 WRITE_DATA_DST_SEL(5))); 3871 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); 3872 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); 3873 amdgpu_ring_write(ring, 1); 3874 3875 /* let CE wait till condition satisfied */ 3876 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3877 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3878 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3879 WAIT_REG_MEM_FUNCTION(3) | /* == */ 3880 WAIT_REG_MEM_ENGINE(2))); /* ce */ 3881 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); 3882 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); 3883 amdgpu_ring_write(ring, 1); 3884 amdgpu_ring_write(ring, 0xffffffff); 3885 amdgpu_ring_write(ring, 4); /* poll interval */ 3886 3887 /* instruct CE to reset wb of ce_sync to zero */ 3888 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3889 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 3890 WRITE_DATA_DST_SEL(5) | 3891 WR_CONFIRM)); 3892 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc); 3893 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff); 3894 amdgpu_ring_write(ring, 0); 3895 } 3896 3897 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3898 unsigned vm_id, uint64_t pd_addr) 3899 { 3900 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 3901 3902 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3903 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3904 WRITE_DATA_DST_SEL(0))); 3905 if (vm_id < 8) { 3906 amdgpu_ring_write(ring, 3907 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3908 } else { 3909 amdgpu_ring_write(ring, 3910 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3911 } 3912 amdgpu_ring_write(ring, 0); 3913 amdgpu_ring_write(ring, pd_addr >> 12); 3914 3915 /* bits 0-15 are the VM contexts0-15 */ 3916 /* invalidate the cache */ 3917 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3918 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3919 WRITE_DATA_DST_SEL(0))); 3920 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3921 amdgpu_ring_write(ring, 0); 3922 amdgpu_ring_write(ring, 1 << vm_id); 3923 3924 /* wait for the invalidate to complete */ 3925 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3926 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3927 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3928 WAIT_REG_MEM_ENGINE(0))); /* me */ 3929 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3930 amdgpu_ring_write(ring, 0); 3931 amdgpu_ring_write(ring, 0); /* ref */ 3932 amdgpu_ring_write(ring, 0); /* mask */ 3933 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3934 3935 /* compute doesn't have PFP */ 3936 if (usepfp) { 3937 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3938 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3939 amdgpu_ring_write(ring, 0x0); 3940 3941 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3942 gfx_v8_0_ce_sync_me(ring); 3943 } 3944 } 3945 3946 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring) 3947 { 3948 if (gfx_v8_0_is_idle(ring->adev)) { 3949 amdgpu_ring_lockup_update(ring); 3950 return false; 3951 } 3952 return amdgpu_ring_test_lockup(ring); 3953 } 3954 3955 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 3956 { 3957 return ring->adev->wb.wb[ring->rptr_offs]; 3958 } 3959 3960 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 3961 { 3962 return ring->adev->wb.wb[ring->wptr_offs]; 3963 } 3964 3965 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 3966 { 3967 struct amdgpu_device *adev = ring->adev; 3968 3969 /* XXX check if swapping is necessary on BE */ 3970 adev->wb.wb[ring->wptr_offs] = ring->wptr; 3971 WDOORBELL32(ring->doorbell_index, ring->wptr); 3972 } 3973 3974 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 3975 u64 addr, u64 seq, 3976 unsigned flags) 3977 { 3978 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3979 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3980 3981 /* RELEASE_MEM - flush caches, send int */ 3982 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 3983 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 3984 EOP_TC_ACTION_EN | 3985 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3986 EVENT_INDEX(5))); 3987 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3988 amdgpu_ring_write(ring, addr & 0xfffffffc); 3989 amdgpu_ring_write(ring, upper_32_bits(addr)); 3990 amdgpu_ring_write(ring, lower_32_bits(seq)); 3991 amdgpu_ring_write(ring, upper_32_bits(seq)); 3992 } 3993 3994 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3995 enum amdgpu_interrupt_state state) 3996 { 3997 u32 cp_int_cntl; 3998 3999 switch (state) { 4000 case AMDGPU_IRQ_STATE_DISABLE: 4001 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4002 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4003 TIME_STAMP_INT_ENABLE, 0); 4004 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4005 break; 4006 case AMDGPU_IRQ_STATE_ENABLE: 4007 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4008 cp_int_cntl = 4009 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4010 TIME_STAMP_INT_ENABLE, 1); 4011 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4012 break; 4013 default: 4014 break; 4015 } 4016 } 4017 4018 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4019 int me, int pipe, 4020 enum amdgpu_interrupt_state state) 4021 { 4022 u32 mec_int_cntl, mec_int_cntl_reg; 4023 4024 /* 4025 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4026 * handles the setting of interrupts for this specific pipe. All other 4027 * pipes' interrupts are set by amdkfd. 4028 */ 4029 4030 if (me == 1) { 4031 switch (pipe) { 4032 case 0: 4033 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4034 break; 4035 default: 4036 DRM_DEBUG("invalid pipe %d\n", pipe); 4037 return; 4038 } 4039 } else { 4040 DRM_DEBUG("invalid me %d\n", me); 4041 return; 4042 } 4043 4044 switch (state) { 4045 case AMDGPU_IRQ_STATE_DISABLE: 4046 mec_int_cntl = RREG32(mec_int_cntl_reg); 4047 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4048 TIME_STAMP_INT_ENABLE, 0); 4049 WREG32(mec_int_cntl_reg, mec_int_cntl); 4050 break; 4051 case AMDGPU_IRQ_STATE_ENABLE: 4052 mec_int_cntl = RREG32(mec_int_cntl_reg); 4053 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4054 TIME_STAMP_INT_ENABLE, 1); 4055 WREG32(mec_int_cntl_reg, mec_int_cntl); 4056 break; 4057 default: 4058 break; 4059 } 4060 } 4061 4062 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4063 struct amdgpu_irq_src *source, 4064 unsigned type, 4065 enum amdgpu_interrupt_state state) 4066 { 4067 u32 cp_int_cntl; 4068 4069 switch (state) { 4070 case AMDGPU_IRQ_STATE_DISABLE: 4071 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4072 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4073 PRIV_REG_INT_ENABLE, 0); 4074 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4075 break; 4076 case AMDGPU_IRQ_STATE_ENABLE: 4077 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4078 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4079 PRIV_REG_INT_ENABLE, 0); 4080 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4081 break; 4082 default: 4083 break; 4084 } 4085 4086 return 0; 4087 } 4088 4089 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4090 struct amdgpu_irq_src *source, 4091 unsigned type, 4092 enum amdgpu_interrupt_state state) 4093 { 4094 u32 cp_int_cntl; 4095 4096 switch (state) { 4097 case AMDGPU_IRQ_STATE_DISABLE: 4098 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4099 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4100 PRIV_INSTR_INT_ENABLE, 0); 4101 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4102 break; 4103 case AMDGPU_IRQ_STATE_ENABLE: 4104 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4105 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4106 PRIV_INSTR_INT_ENABLE, 1); 4107 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4108 break; 4109 default: 4110 break; 4111 } 4112 4113 return 0; 4114 } 4115 4116 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4117 struct amdgpu_irq_src *src, 4118 unsigned type, 4119 enum amdgpu_interrupt_state state) 4120 { 4121 switch (type) { 4122 case AMDGPU_CP_IRQ_GFX_EOP: 4123 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state); 4124 break; 4125 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4126 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4127 break; 4128 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4129 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4130 break; 4131 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4132 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4133 break; 4134 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4135 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4136 break; 4137 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4138 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4139 break; 4140 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4141 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4142 break; 4143 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4144 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4145 break; 4146 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4147 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4148 break; 4149 default: 4150 break; 4151 } 4152 return 0; 4153 } 4154 4155 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, 4156 struct amdgpu_irq_src *source, 4157 struct amdgpu_iv_entry *entry) 4158 { 4159 int i; 4160 u8 me_id, pipe_id, queue_id; 4161 struct amdgpu_ring *ring; 4162 4163 DRM_DEBUG("IH: CP EOP\n"); 4164 me_id = (entry->ring_id & 0x0c) >> 2; 4165 pipe_id = (entry->ring_id & 0x03) >> 0; 4166 queue_id = (entry->ring_id & 0x70) >> 4; 4167 4168 switch (me_id) { 4169 case 0: 4170 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4171 break; 4172 case 1: 4173 case 2: 4174 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4175 ring = &adev->gfx.compute_ring[i]; 4176 /* Per-queue interrupt is supported for MEC starting from VI. 4177 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4178 */ 4179 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4180 amdgpu_fence_process(ring); 4181 } 4182 break; 4183 } 4184 return 0; 4185 } 4186 4187 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev, 4188 struct amdgpu_irq_src *source, 4189 struct amdgpu_iv_entry *entry) 4190 { 4191 DRM_ERROR("Illegal register access in command stream\n"); 4192 schedule_work(&adev->reset_work); 4193 return 0; 4194 } 4195 4196 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, 4197 struct amdgpu_irq_src *source, 4198 struct amdgpu_iv_entry *entry) 4199 { 4200 DRM_ERROR("Illegal instruction in command stream\n"); 4201 schedule_work(&adev->reset_work); 4202 return 0; 4203 } 4204 4205 const struct amd_ip_funcs gfx_v8_0_ip_funcs = { 4206 .early_init = gfx_v8_0_early_init, 4207 .late_init = NULL, 4208 .sw_init = gfx_v8_0_sw_init, 4209 .sw_fini = gfx_v8_0_sw_fini, 4210 .hw_init = gfx_v8_0_hw_init, 4211 .hw_fini = gfx_v8_0_hw_fini, 4212 .suspend = gfx_v8_0_suspend, 4213 .resume = gfx_v8_0_resume, 4214 .is_idle = gfx_v8_0_is_idle, 4215 .wait_for_idle = gfx_v8_0_wait_for_idle, 4216 .soft_reset = gfx_v8_0_soft_reset, 4217 .print_status = gfx_v8_0_print_status, 4218 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 4219 .set_powergating_state = gfx_v8_0_set_powergating_state, 4220 }; 4221 4222 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { 4223 .get_rptr = gfx_v8_0_ring_get_rptr_gfx, 4224 .get_wptr = gfx_v8_0_ring_get_wptr_gfx, 4225 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 4226 .parse_cs = NULL, 4227 .emit_ib = gfx_v8_0_ring_emit_ib, 4228 .emit_fence = gfx_v8_0_ring_emit_fence_gfx, 4229 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 4230 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 4231 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 4232 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 4233 .test_ring = gfx_v8_0_ring_test_ring, 4234 .test_ib = gfx_v8_0_ring_test_ib, 4235 .is_lockup = gfx_v8_0_ring_is_lockup, 4236 }; 4237 4238 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { 4239 .get_rptr = gfx_v8_0_ring_get_rptr_compute, 4240 .get_wptr = gfx_v8_0_ring_get_wptr_compute, 4241 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 4242 .parse_cs = NULL, 4243 .emit_ib = gfx_v8_0_ring_emit_ib, 4244 .emit_fence = gfx_v8_0_ring_emit_fence_compute, 4245 .emit_semaphore = gfx_v8_0_ring_emit_semaphore, 4246 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, 4247 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, 4248 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, 4249 .test_ring = gfx_v8_0_ring_test_ring, 4250 .test_ib = gfx_v8_0_ring_test_ib, 4251 .is_lockup = gfx_v8_0_ring_is_lockup, 4252 }; 4253 4254 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) 4255 { 4256 int i; 4257 4258 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4259 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; 4260 4261 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4262 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; 4263 } 4264 4265 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = { 4266 .set = gfx_v8_0_set_eop_interrupt_state, 4267 .process = gfx_v8_0_eop_irq, 4268 }; 4269 4270 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = { 4271 .set = gfx_v8_0_set_priv_reg_fault_state, 4272 .process = gfx_v8_0_priv_reg_irq, 4273 }; 4274 4275 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = { 4276 .set = gfx_v8_0_set_priv_inst_fault_state, 4277 .process = gfx_v8_0_priv_inst_irq, 4278 }; 4279 4280 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) 4281 { 4282 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4283 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; 4284 4285 adev->gfx.priv_reg_irq.num_types = 1; 4286 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; 4287 4288 adev->gfx.priv_inst_irq.num_types = 1; 4289 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; 4290 } 4291 4292 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev) 4293 { 4294 /* init asci gds info */ 4295 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 4296 adev->gds.gws.total_size = 64; 4297 adev->gds.oa.total_size = 16; 4298 4299 if (adev->gds.mem.total_size == 64 * 1024) { 4300 adev->gds.mem.gfx_partition_size = 4096; 4301 adev->gds.mem.cs_partition_size = 4096; 4302 4303 adev->gds.gws.gfx_partition_size = 4; 4304 adev->gds.gws.cs_partition_size = 4; 4305 4306 adev->gds.oa.gfx_partition_size = 4; 4307 adev->gds.oa.cs_partition_size = 1; 4308 } else { 4309 adev->gds.mem.gfx_partition_size = 1024; 4310 adev->gds.mem.cs_partition_size = 1024; 4311 4312 adev->gds.gws.gfx_partition_size = 16; 4313 adev->gds.gws.cs_partition_size = 16; 4314 4315 adev->gds.oa.gfx_partition_size = 4; 4316 adev->gds.oa.cs_partition_size = 4; 4317 } 4318 } 4319 4320 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev, 4321 u32 se, u32 sh) 4322 { 4323 u32 mask = 0, tmp, tmp1; 4324 int i; 4325 4326 gfx_v8_0_select_se_sh(adev, se, sh); 4327 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 4328 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 4329 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 4330 4331 tmp &= 0xffff0000; 4332 4333 tmp |= tmp1; 4334 tmp >>= 16; 4335 4336 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { 4337 mask <<= 1; 4338 mask |= 1; 4339 } 4340 4341 return (~tmp) & mask; 4342 } 4343 4344 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev, 4345 struct amdgpu_cu_info *cu_info) 4346 { 4347 int i, j, k, counter, active_cu_number = 0; 4348 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4349 4350 if (!adev || !cu_info) 4351 return -EINVAL; 4352 4353 mutex_lock(&adev->grbm_idx_mutex); 4354 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4355 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4356 mask = 1; 4357 ao_bitmap = 0; 4358 counter = 0; 4359 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j); 4360 cu_info->bitmap[i][j] = bitmap; 4361 4362 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4363 if (bitmap & mask) { 4364 if (counter < 2) 4365 ao_bitmap |= mask; 4366 counter ++; 4367 } 4368 mask <<= 1; 4369 } 4370 active_cu_number += counter; 4371 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4372 } 4373 } 4374 4375 cu_info->number = active_cu_number; 4376 cu_info->ao_cu_mask = ao_cu_mask; 4377 mutex_unlock(&adev->grbm_idx_mutex); 4378 return 0; 4379 } 4380