1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "amdgpu_ih.h" 27 #include "amdgpu_gfx.h" 28 #include "cikd.h" 29 #include "cik.h" 30 #include "cik_structs.h" 31 #include "atom.h" 32 #include "amdgpu_ucode.h" 33 #include "clearstate_ci.h" 34 35 #include "dce/dce_8_0_d.h" 36 #include "dce/dce_8_0_sh_mask.h" 37 38 #include "bif/bif_4_1_d.h" 39 #include "bif/bif_4_1_sh_mask.h" 40 41 #include "gca/gfx_7_0_d.h" 42 #include "gca/gfx_7_2_enum.h" 43 #include "gca/gfx_7_2_sh_mask.h" 44 45 #include "gmc/gmc_7_0_d.h" 46 #include "gmc/gmc_7_0_sh_mask.h" 47 48 #include "oss/oss_2_0_d.h" 49 #include "oss/oss_2_0_sh_mask.h" 50 51 #define GFX7_NUM_GFX_RINGS 1 52 #define GFX7_MEC_HPD_SIZE 2048 53 54 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 55 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 56 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 57 58 MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); 59 MODULE_FIRMWARE("radeon/bonaire_me.bin"); 60 MODULE_FIRMWARE("radeon/bonaire_ce.bin"); 61 MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); 62 MODULE_FIRMWARE("radeon/bonaire_mec.bin"); 63 64 MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); 65 MODULE_FIRMWARE("radeon/hawaii_me.bin"); 66 MODULE_FIRMWARE("radeon/hawaii_ce.bin"); 67 MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); 68 MODULE_FIRMWARE("radeon/hawaii_mec.bin"); 69 70 MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); 71 MODULE_FIRMWARE("radeon/kaveri_me.bin"); 72 MODULE_FIRMWARE("radeon/kaveri_ce.bin"); 73 MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); 74 MODULE_FIRMWARE("radeon/kaveri_mec.bin"); 75 MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); 76 77 MODULE_FIRMWARE("radeon/kabini_pfp.bin"); 78 MODULE_FIRMWARE("radeon/kabini_me.bin"); 79 MODULE_FIRMWARE("radeon/kabini_ce.bin"); 80 MODULE_FIRMWARE("radeon/kabini_rlc.bin"); 81 MODULE_FIRMWARE("radeon/kabini_mec.bin"); 82 83 MODULE_FIRMWARE("radeon/mullins_pfp.bin"); 84 MODULE_FIRMWARE("radeon/mullins_me.bin"); 85 MODULE_FIRMWARE("radeon/mullins_ce.bin"); 86 MODULE_FIRMWARE("radeon/mullins_rlc.bin"); 87 MODULE_FIRMWARE("radeon/mullins_mec.bin"); 88 89 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 90 { 91 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 92 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 93 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 94 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 95 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 96 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 97 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 98 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 99 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 100 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 101 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 102 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 103 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 104 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 105 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 106 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 107 }; 108 109 static const u32 spectre_rlc_save_restore_register_list[] = 110 { 111 (0x0e00 << 16) | (0xc12c >> 2), 112 0x00000000, 113 (0x0e00 << 16) | (0xc140 >> 2), 114 0x00000000, 115 (0x0e00 << 16) | (0xc150 >> 2), 116 0x00000000, 117 (0x0e00 << 16) | (0xc15c >> 2), 118 0x00000000, 119 (0x0e00 << 16) | (0xc168 >> 2), 120 0x00000000, 121 (0x0e00 << 16) | (0xc170 >> 2), 122 0x00000000, 123 (0x0e00 << 16) | (0xc178 >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc204 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc2b4 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc2b8 >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc2bc >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc2c0 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0x8228 >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0x829c >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0x869c >> 2), 140 0x00000000, 141 (0x0600 << 16) | (0x98f4 >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0x98f8 >> 2), 144 0x00000000, 145 (0x0e00 << 16) | (0x9900 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0xc260 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x90e8 >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0x3c000 >> 2), 152 0x00000000, 153 (0x0e00 << 16) | (0x3c00c >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x8c1c >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x9700 >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0xcd20 >> 2), 160 0x00000000, 161 (0x4e00 << 16) | (0xcd20 >> 2), 162 0x00000000, 163 (0x5e00 << 16) | (0xcd20 >> 2), 164 0x00000000, 165 (0x6e00 << 16) | (0xcd20 >> 2), 166 0x00000000, 167 (0x7e00 << 16) | (0xcd20 >> 2), 168 0x00000000, 169 (0x8e00 << 16) | (0xcd20 >> 2), 170 0x00000000, 171 (0x9e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0xae00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0xbe00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0x0e00 << 16) | (0x89bc >> 2), 178 0x00000000, 179 (0x0e00 << 16) | (0x8900 >> 2), 180 0x00000000, 181 0x3, 182 (0x0e00 << 16) | (0xc130 >> 2), 183 0x00000000, 184 (0x0e00 << 16) | (0xc134 >> 2), 185 0x00000000, 186 (0x0e00 << 16) | (0xc1fc >> 2), 187 0x00000000, 188 (0x0e00 << 16) | (0xc208 >> 2), 189 0x00000000, 190 (0x0e00 << 16) | (0xc264 >> 2), 191 0x00000000, 192 (0x0e00 << 16) | (0xc268 >> 2), 193 0x00000000, 194 (0x0e00 << 16) | (0xc26c >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc270 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc274 >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc278 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc27c >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc280 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc284 >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc288 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc28c >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc290 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc294 >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc298 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc29c >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc2a0 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc2a4 >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc2a8 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc2ac >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc2b0 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0x301d0 >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0x30238 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0x30250 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0x30254 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0x30258 >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0x3025c >> 2), 241 0x00000000, 242 (0x4e00 << 16) | (0xc900 >> 2), 243 0x00000000, 244 (0x5e00 << 16) | (0xc900 >> 2), 245 0x00000000, 246 (0x6e00 << 16) | (0xc900 >> 2), 247 0x00000000, 248 (0x7e00 << 16) | (0xc900 >> 2), 249 0x00000000, 250 (0x8e00 << 16) | (0xc900 >> 2), 251 0x00000000, 252 (0x9e00 << 16) | (0xc900 >> 2), 253 0x00000000, 254 (0xae00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0xbe00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0x4e00 << 16) | (0xc904 >> 2), 259 0x00000000, 260 (0x5e00 << 16) | (0xc904 >> 2), 261 0x00000000, 262 (0x6e00 << 16) | (0xc904 >> 2), 263 0x00000000, 264 (0x7e00 << 16) | (0xc904 >> 2), 265 0x00000000, 266 (0x8e00 << 16) | (0xc904 >> 2), 267 0x00000000, 268 (0x9e00 << 16) | (0xc904 >> 2), 269 0x00000000, 270 (0xae00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0xbe00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0x4e00 << 16) | (0xc908 >> 2), 275 0x00000000, 276 (0x5e00 << 16) | (0xc908 >> 2), 277 0x00000000, 278 (0x6e00 << 16) | (0xc908 >> 2), 279 0x00000000, 280 (0x7e00 << 16) | (0xc908 >> 2), 281 0x00000000, 282 (0x8e00 << 16) | (0xc908 >> 2), 283 0x00000000, 284 (0x9e00 << 16) | (0xc908 >> 2), 285 0x00000000, 286 (0xae00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0xbe00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0x4e00 << 16) | (0xc90c >> 2), 291 0x00000000, 292 (0x5e00 << 16) | (0xc90c >> 2), 293 0x00000000, 294 (0x6e00 << 16) | (0xc90c >> 2), 295 0x00000000, 296 (0x7e00 << 16) | (0xc90c >> 2), 297 0x00000000, 298 (0x8e00 << 16) | (0xc90c >> 2), 299 0x00000000, 300 (0x9e00 << 16) | (0xc90c >> 2), 301 0x00000000, 302 (0xae00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0xbe00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0x4e00 << 16) | (0xc910 >> 2), 307 0x00000000, 308 (0x5e00 << 16) | (0xc910 >> 2), 309 0x00000000, 310 (0x6e00 << 16) | (0xc910 >> 2), 311 0x00000000, 312 (0x7e00 << 16) | (0xc910 >> 2), 313 0x00000000, 314 (0x8e00 << 16) | (0xc910 >> 2), 315 0x00000000, 316 (0x9e00 << 16) | (0xc910 >> 2), 317 0x00000000, 318 (0xae00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0xbe00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0x0e00 << 16) | (0xc99c >> 2), 323 0x00000000, 324 (0x0e00 << 16) | (0x9834 >> 2), 325 0x00000000, 326 (0x0000 << 16) | (0x30f00 >> 2), 327 0x00000000, 328 (0x0001 << 16) | (0x30f00 >> 2), 329 0x00000000, 330 (0x0000 << 16) | (0x30f04 >> 2), 331 0x00000000, 332 (0x0001 << 16) | (0x30f04 >> 2), 333 0x00000000, 334 (0x0000 << 16) | (0x30f08 >> 2), 335 0x00000000, 336 (0x0001 << 16) | (0x30f08 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f0c >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f0c >> 2), 341 0x00000000, 342 (0x0600 << 16) | (0x9b7c >> 2), 343 0x00000000, 344 (0x0e00 << 16) | (0x8a14 >> 2), 345 0x00000000, 346 (0x0e00 << 16) | (0x8a18 >> 2), 347 0x00000000, 348 (0x0600 << 16) | (0x30a00 >> 2), 349 0x00000000, 350 (0x0e00 << 16) | (0x8bf0 >> 2), 351 0x00000000, 352 (0x0e00 << 16) | (0x8bcc >> 2), 353 0x00000000, 354 (0x0e00 << 16) | (0x8b24 >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x30a04 >> 2), 357 0x00000000, 358 (0x0600 << 16) | (0x30a10 >> 2), 359 0x00000000, 360 (0x0600 << 16) | (0x30a14 >> 2), 361 0x00000000, 362 (0x0600 << 16) | (0x30a18 >> 2), 363 0x00000000, 364 (0x0600 << 16) | (0x30a2c >> 2), 365 0x00000000, 366 (0x0e00 << 16) | (0xc700 >> 2), 367 0x00000000, 368 (0x0e00 << 16) | (0xc704 >> 2), 369 0x00000000, 370 (0x0e00 << 16) | (0xc708 >> 2), 371 0x00000000, 372 (0x0e00 << 16) | (0xc768 >> 2), 373 0x00000000, 374 (0x0400 << 16) | (0xc770 >> 2), 375 0x00000000, 376 (0x0400 << 16) | (0xc774 >> 2), 377 0x00000000, 378 (0x0400 << 16) | (0xc778 >> 2), 379 0x00000000, 380 (0x0400 << 16) | (0xc77c >> 2), 381 0x00000000, 382 (0x0400 << 16) | (0xc780 >> 2), 383 0x00000000, 384 (0x0400 << 16) | (0xc784 >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc788 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc78c >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc798 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc79c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc7a0 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc7a4 >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc7a8 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc7ac >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc7b0 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc7b4 >> 2), 405 0x00000000, 406 (0x0e00 << 16) | (0x9100 >> 2), 407 0x00000000, 408 (0x0e00 << 16) | (0x3c010 >> 2), 409 0x00000000, 410 (0x0e00 << 16) | (0x92a8 >> 2), 411 0x00000000, 412 (0x0e00 << 16) | (0x92ac >> 2), 413 0x00000000, 414 (0x0e00 << 16) | (0x92b4 >> 2), 415 0x00000000, 416 (0x0e00 << 16) | (0x92b8 >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x92bc >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x92c0 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92c4 >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92c8 >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92cc >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92d0 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x8c00 >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x8c04 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x8c20 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x8c38 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x8c3c >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0xae00 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x9604 >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0xac08 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0xac0c >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0xac10 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0xac14 >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xac58 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0xac68 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac6c >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac70 >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac74 >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac78 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac7c >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac80 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac84 >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac88 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac8c >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0x970c >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0x9714 >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0x9718 >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0x971c >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0x31068 >> 2), 483 0x00000000, 484 (0x4e00 << 16) | (0x31068 >> 2), 485 0x00000000, 486 (0x5e00 << 16) | (0x31068 >> 2), 487 0x00000000, 488 (0x6e00 << 16) | (0x31068 >> 2), 489 0x00000000, 490 (0x7e00 << 16) | (0x31068 >> 2), 491 0x00000000, 492 (0x8e00 << 16) | (0x31068 >> 2), 493 0x00000000, 494 (0x9e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0xae00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0xbe00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0x0e00 << 16) | (0xcd10 >> 2), 501 0x00000000, 502 (0x0e00 << 16) | (0xcd14 >> 2), 503 0x00000000, 504 (0x0e00 << 16) | (0x88b0 >> 2), 505 0x00000000, 506 (0x0e00 << 16) | (0x88b4 >> 2), 507 0x00000000, 508 (0x0e00 << 16) | (0x88b8 >> 2), 509 0x00000000, 510 (0x0e00 << 16) | (0x88bc >> 2), 511 0x00000000, 512 (0x0400 << 16) | (0x89c0 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0x88c4 >> 2), 515 0x00000000, 516 (0x0e00 << 16) | (0x88c8 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88d0 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88d4 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88d8 >> 2), 523 0x00000000, 524 (0x0e00 << 16) | (0x8980 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x30938 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x3093c >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x30940 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x89a0 >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x30900 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x30904 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x89b4 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x3c210 >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x3c214 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x3c218 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x8904 >> 2), 547 0x00000000, 548 0x5, 549 (0x0e00 << 16) | (0x8c28 >> 2), 550 (0x0e00 << 16) | (0x8c2c >> 2), 551 (0x0e00 << 16) | (0x8c30 >> 2), 552 (0x0e00 << 16) | (0x8c34 >> 2), 553 (0x0e00 << 16) | (0x9600 >> 2), 554 }; 555 556 static const u32 kalindi_rlc_save_restore_register_list[] = 557 { 558 (0x0e00 << 16) | (0xc12c >> 2), 559 0x00000000, 560 (0x0e00 << 16) | (0xc140 >> 2), 561 0x00000000, 562 (0x0e00 << 16) | (0xc150 >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc15c >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc168 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc170 >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc204 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc2b4 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc2b8 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2bc >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2c0 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0x8228 >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0x829c >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x869c >> 2), 585 0x00000000, 586 (0x0600 << 16) | (0x98f4 >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x98f8 >> 2), 589 0x00000000, 590 (0x0e00 << 16) | (0x9900 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0xc260 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x90e8 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0x3c000 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x3c00c >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x8c1c >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x9700 >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0xcd20 >> 2), 605 0x00000000, 606 (0x4e00 << 16) | (0xcd20 >> 2), 607 0x00000000, 608 (0x5e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x6e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x7e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x0e00 << 16) | (0x89bc >> 2), 615 0x00000000, 616 (0x0e00 << 16) | (0x8900 >> 2), 617 0x00000000, 618 0x3, 619 (0x0e00 << 16) | (0xc130 >> 2), 620 0x00000000, 621 (0x0e00 << 16) | (0xc134 >> 2), 622 0x00000000, 623 (0x0e00 << 16) | (0xc1fc >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc208 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc264 >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc268 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc26c >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc270 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc274 >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc28c >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc290 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc294 >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc298 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc2a0 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc2a4 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a8 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2ac >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0x301d0 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0x30238 >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x30250 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30254 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30258 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x3025c >> 2), 664 0x00000000, 665 (0x4e00 << 16) | (0xc900 >> 2), 666 0x00000000, 667 (0x5e00 << 16) | (0xc900 >> 2), 668 0x00000000, 669 (0x6e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x7e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x4e00 << 16) | (0xc904 >> 2), 674 0x00000000, 675 (0x5e00 << 16) | (0xc904 >> 2), 676 0x00000000, 677 (0x6e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x7e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x4e00 << 16) | (0xc908 >> 2), 682 0x00000000, 683 (0x5e00 << 16) | (0xc908 >> 2), 684 0x00000000, 685 (0x6e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x7e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x4e00 << 16) | (0xc90c >> 2), 690 0x00000000, 691 (0x5e00 << 16) | (0xc90c >> 2), 692 0x00000000, 693 (0x6e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x7e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x4e00 << 16) | (0xc910 >> 2), 698 0x00000000, 699 (0x5e00 << 16) | (0xc910 >> 2), 700 0x00000000, 701 (0x6e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x7e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x0e00 << 16) | (0xc99c >> 2), 706 0x00000000, 707 (0x0e00 << 16) | (0x9834 >> 2), 708 0x00000000, 709 (0x0000 << 16) | (0x30f00 >> 2), 710 0x00000000, 711 (0x0000 << 16) | (0x30f04 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f08 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f0c >> 2), 716 0x00000000, 717 (0x0600 << 16) | (0x9b7c >> 2), 718 0x00000000, 719 (0x0e00 << 16) | (0x8a14 >> 2), 720 0x00000000, 721 (0x0e00 << 16) | (0x8a18 >> 2), 722 0x00000000, 723 (0x0600 << 16) | (0x30a00 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8bf0 >> 2), 726 0x00000000, 727 (0x0e00 << 16) | (0x8bcc >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8b24 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x30a04 >> 2), 732 0x00000000, 733 (0x0600 << 16) | (0x30a10 >> 2), 734 0x00000000, 735 (0x0600 << 16) | (0x30a14 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a18 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a2c >> 2), 740 0x00000000, 741 (0x0e00 << 16) | (0xc700 >> 2), 742 0x00000000, 743 (0x0e00 << 16) | (0xc704 >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc708 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc768 >> 2), 748 0x00000000, 749 (0x0400 << 16) | (0xc770 >> 2), 750 0x00000000, 751 (0x0400 << 16) | (0xc774 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc798 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc79c >> 2), 756 0x00000000, 757 (0x0e00 << 16) | (0x9100 >> 2), 758 0x00000000, 759 (0x0e00 << 16) | (0x3c010 >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x8c00 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x8c04 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c20 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c38 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c3c >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0xae00 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x9604 >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xac08 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0xac0c >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac10 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac14 >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac58 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac68 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac6c >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac70 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac74 >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac78 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac7c >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac80 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac84 >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac88 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac8c >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0x970c >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0x9714 >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x9718 >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x971c >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x31068 >> 2), 814 0x00000000, 815 (0x4e00 << 16) | (0x31068 >> 2), 816 0x00000000, 817 (0x5e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x6e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x7e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x0e00 << 16) | (0xcd10 >> 2), 824 0x00000000, 825 (0x0e00 << 16) | (0xcd14 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0x88b0 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0x88b4 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b8 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88bc >> 2), 834 0x00000000, 835 (0x0400 << 16) | (0x89c0 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88c4 >> 2), 838 0x00000000, 839 (0x0e00 << 16) | (0x88c8 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88d0 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88d4 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d8 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x8980 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x30938 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x3093c >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30940 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x89a0 >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30900 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x30904 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x89b4 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x3e1fc >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x3c210 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3c214 >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c218 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x8904 >> 2), 872 0x00000000, 873 0x5, 874 (0x0e00 << 16) | (0x8c28 >> 2), 875 (0x0e00 << 16) | (0x8c2c >> 2), 876 (0x0e00 << 16) | (0x8c30 >> 2), 877 (0x0e00 << 16) | (0x8c34 >> 2), 878 (0x0e00 << 16) | (0x9600 >> 2), 879 }; 880 881 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 883 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); 884 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 885 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 886 887 /* 888 * Core functions 889 */ 890 /** 891 * gfx_v7_0_init_microcode - load ucode images from disk 892 * 893 * @adev: amdgpu_device pointer 894 * 895 * Use the firmware interface to load the ucode images into 896 * the driver (not loaded into hw). 897 * Returns 0 on success, error on failure. 898 */ 899 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 900 { 901 const char *chip_name; 902 char fw_name[30]; 903 int err; 904 905 DRM_DEBUG("\n"); 906 907 switch (adev->asic_type) { 908 case CHIP_BONAIRE: 909 chip_name = "bonaire"; 910 break; 911 case CHIP_HAWAII: 912 chip_name = "hawaii"; 913 break; 914 case CHIP_KAVERI: 915 chip_name = "kaveri"; 916 break; 917 case CHIP_KABINI: 918 chip_name = "kabini"; 919 break; 920 case CHIP_MULLINS: 921 chip_name = "mullins"; 922 break; 923 default: BUG(); 924 } 925 926 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 927 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 928 if (err) 929 goto out; 930 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 931 if (err) 932 goto out; 933 934 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 935 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 936 if (err) 937 goto out; 938 err = amdgpu_ucode_validate(adev->gfx.me_fw); 939 if (err) 940 goto out; 941 942 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 943 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 944 if (err) 945 goto out; 946 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 947 if (err) 948 goto out; 949 950 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); 951 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 952 if (err) 953 goto out; 954 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 955 if (err) 956 goto out; 957 958 if (adev->asic_type == CHIP_KAVERI) { 959 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); 960 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 961 if (err) 962 goto out; 963 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 964 if (err) 965 goto out; 966 } 967 968 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 969 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 970 if (err) 971 goto out; 972 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 973 974 out: 975 if (err) { 976 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); 977 release_firmware(adev->gfx.pfp_fw); 978 adev->gfx.pfp_fw = NULL; 979 release_firmware(adev->gfx.me_fw); 980 adev->gfx.me_fw = NULL; 981 release_firmware(adev->gfx.ce_fw); 982 adev->gfx.ce_fw = NULL; 983 release_firmware(adev->gfx.mec_fw); 984 adev->gfx.mec_fw = NULL; 985 release_firmware(adev->gfx.mec2_fw); 986 adev->gfx.mec2_fw = NULL; 987 release_firmware(adev->gfx.rlc_fw); 988 adev->gfx.rlc_fw = NULL; 989 } 990 return err; 991 } 992 993 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 994 { 995 release_firmware(adev->gfx.pfp_fw); 996 adev->gfx.pfp_fw = NULL; 997 release_firmware(adev->gfx.me_fw); 998 adev->gfx.me_fw = NULL; 999 release_firmware(adev->gfx.ce_fw); 1000 adev->gfx.ce_fw = NULL; 1001 release_firmware(adev->gfx.mec_fw); 1002 adev->gfx.mec_fw = NULL; 1003 release_firmware(adev->gfx.mec2_fw); 1004 adev->gfx.mec2_fw = NULL; 1005 release_firmware(adev->gfx.rlc_fw); 1006 adev->gfx.rlc_fw = NULL; 1007 } 1008 1009 /** 1010 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1011 * 1012 * @adev: amdgpu_device pointer 1013 * 1014 * Starting with SI, the tiling setup is done globally in a 1015 * set of 32 tiling modes. Rather than selecting each set of 1016 * parameters per surface as on older asics, we just select 1017 * which index in the tiling table we want to use, and the 1018 * surface uses those parameters (CIK). 1019 */ 1020 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1021 { 1022 const u32 num_tile_mode_states = 1023 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1024 const u32 num_secondary_tile_mode_states = 1025 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1026 u32 reg_offset, split_equal_to_row_size; 1027 uint32_t *tile, *macrotile; 1028 1029 tile = adev->gfx.config.tile_mode_array; 1030 macrotile = adev->gfx.config.macrotile_mode_array; 1031 1032 switch (adev->gfx.config.mem_row_size_in_kb) { 1033 case 1: 1034 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1035 break; 1036 case 2: 1037 default: 1038 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1039 break; 1040 case 4: 1041 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1042 break; 1043 } 1044 1045 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1046 tile[reg_offset] = 0; 1047 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1048 macrotile[reg_offset] = 0; 1049 1050 switch (adev->asic_type) { 1051 case CHIP_BONAIRE: 1052 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1053 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1056 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1057 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1058 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1060 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1063 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1064 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1065 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1066 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1067 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1068 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1069 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1071 TILE_SPLIT(split_equal_to_row_size)); 1072 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1073 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1074 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1075 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1077 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1078 TILE_SPLIT(split_equal_to_row_size)); 1079 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1080 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1081 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1082 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1084 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1085 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1086 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1089 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1090 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1091 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1093 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1094 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1095 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1097 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1098 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1101 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1102 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1103 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1105 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1106 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1109 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1110 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1114 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1115 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1116 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1117 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1118 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1119 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1121 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1122 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1123 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1125 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1126 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1127 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1129 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1130 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1132 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1134 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1138 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1139 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1142 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1143 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1144 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1145 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1146 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1147 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1149 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1150 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1151 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1152 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1153 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1154 1155 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1156 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1157 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1158 NUM_BANKS(ADDR_SURF_16_BANK)); 1159 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1160 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1161 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1162 NUM_BANKS(ADDR_SURF_16_BANK)); 1163 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1164 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1165 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1166 NUM_BANKS(ADDR_SURF_16_BANK)); 1167 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1170 NUM_BANKS(ADDR_SURF_16_BANK)); 1171 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1174 NUM_BANKS(ADDR_SURF_16_BANK)); 1175 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1178 NUM_BANKS(ADDR_SURF_8_BANK)); 1179 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1180 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1181 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1182 NUM_BANKS(ADDR_SURF_4_BANK)); 1183 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1184 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1185 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1186 NUM_BANKS(ADDR_SURF_16_BANK)); 1187 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1190 NUM_BANKS(ADDR_SURF_16_BANK)); 1191 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1194 NUM_BANKS(ADDR_SURF_16_BANK)); 1195 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1198 NUM_BANKS(ADDR_SURF_16_BANK)); 1199 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1202 NUM_BANKS(ADDR_SURF_16_BANK)); 1203 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1206 NUM_BANKS(ADDR_SURF_8_BANK)); 1207 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1210 NUM_BANKS(ADDR_SURF_4_BANK)); 1211 1212 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1213 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1214 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1215 if (reg_offset != 7) 1216 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1217 break; 1218 case CHIP_HAWAII: 1219 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1220 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1221 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1223 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1224 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1225 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1227 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1228 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1231 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1232 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1233 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1235 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1236 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1238 TILE_SPLIT(split_equal_to_row_size)); 1239 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1240 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1241 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1242 TILE_SPLIT(split_equal_to_row_size)); 1243 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1244 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1245 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1246 TILE_SPLIT(split_equal_to_row_size)); 1247 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1248 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1249 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1250 TILE_SPLIT(split_equal_to_row_size)); 1251 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1252 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1253 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1255 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1256 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1258 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1260 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1262 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1264 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1265 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1266 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1268 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1271 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1275 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1279 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1283 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1284 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1287 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1291 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1294 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1298 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1300 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1302 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1304 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1306 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1307 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1308 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1310 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1312 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1314 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1316 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1318 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1320 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1322 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1324 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1325 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1326 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1327 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1329 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1330 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1331 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1332 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1333 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1334 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1335 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1337 1338 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1341 NUM_BANKS(ADDR_SURF_16_BANK)); 1342 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1343 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1344 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1345 NUM_BANKS(ADDR_SURF_16_BANK)); 1346 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1347 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1348 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1349 NUM_BANKS(ADDR_SURF_16_BANK)); 1350 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1351 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1352 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1353 NUM_BANKS(ADDR_SURF_16_BANK)); 1354 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1355 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1356 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1357 NUM_BANKS(ADDR_SURF_8_BANK)); 1358 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1361 NUM_BANKS(ADDR_SURF_4_BANK)); 1362 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1363 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1364 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1365 NUM_BANKS(ADDR_SURF_4_BANK)); 1366 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1367 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1368 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1369 NUM_BANKS(ADDR_SURF_16_BANK)); 1370 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1371 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1372 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1373 NUM_BANKS(ADDR_SURF_16_BANK)); 1374 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1375 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1376 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1377 NUM_BANKS(ADDR_SURF_16_BANK)); 1378 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1381 NUM_BANKS(ADDR_SURF_8_BANK)); 1382 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1383 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1384 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1385 NUM_BANKS(ADDR_SURF_16_BANK)); 1386 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1389 NUM_BANKS(ADDR_SURF_8_BANK)); 1390 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1391 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1392 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1393 NUM_BANKS(ADDR_SURF_4_BANK)); 1394 1395 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1396 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1397 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1398 if (reg_offset != 7) 1399 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1400 break; 1401 case CHIP_KABINI: 1402 case CHIP_KAVERI: 1403 case CHIP_MULLINS: 1404 default: 1405 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1406 PIPE_CONFIG(ADDR_SURF_P2) | 1407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1409 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1410 PIPE_CONFIG(ADDR_SURF_P2) | 1411 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1413 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1414 PIPE_CONFIG(ADDR_SURF_P2) | 1415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1416 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1417 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1418 PIPE_CONFIG(ADDR_SURF_P2) | 1419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1420 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1421 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1422 PIPE_CONFIG(ADDR_SURF_P2) | 1423 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1424 TILE_SPLIT(split_equal_to_row_size)); 1425 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1426 PIPE_CONFIG(ADDR_SURF_P2) | 1427 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1428 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1429 PIPE_CONFIG(ADDR_SURF_P2) | 1430 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1431 TILE_SPLIT(split_equal_to_row_size)); 1432 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1433 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1434 PIPE_CONFIG(ADDR_SURF_P2)); 1435 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1436 PIPE_CONFIG(ADDR_SURF_P2) | 1437 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1438 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1439 PIPE_CONFIG(ADDR_SURF_P2) | 1440 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1441 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1442 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1443 PIPE_CONFIG(ADDR_SURF_P2) | 1444 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1446 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1447 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1448 PIPE_CONFIG(ADDR_SURF_P2) | 1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1450 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1451 PIPE_CONFIG(ADDR_SURF_P2) | 1452 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1453 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1454 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1455 PIPE_CONFIG(ADDR_SURF_P2) | 1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1458 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1459 PIPE_CONFIG(ADDR_SURF_P2) | 1460 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1461 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1462 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1463 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1464 PIPE_CONFIG(ADDR_SURF_P2) | 1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1467 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1468 PIPE_CONFIG(ADDR_SURF_P2) | 1469 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1470 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1471 PIPE_CONFIG(ADDR_SURF_P2) | 1472 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1473 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1474 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1475 PIPE_CONFIG(ADDR_SURF_P2) | 1476 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1477 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1478 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1479 PIPE_CONFIG(ADDR_SURF_P2) | 1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1482 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1483 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1484 PIPE_CONFIG(ADDR_SURF_P2) | 1485 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1487 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1488 PIPE_CONFIG(ADDR_SURF_P2) | 1489 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1491 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1492 PIPE_CONFIG(ADDR_SURF_P2) | 1493 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1494 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1495 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1496 PIPE_CONFIG(ADDR_SURF_P2) | 1497 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1498 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1499 PIPE_CONFIG(ADDR_SURF_P2) | 1500 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1501 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1502 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1503 PIPE_CONFIG(ADDR_SURF_P2) | 1504 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1506 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1507 1508 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1509 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1510 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1511 NUM_BANKS(ADDR_SURF_8_BANK)); 1512 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1513 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1514 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1515 NUM_BANKS(ADDR_SURF_8_BANK)); 1516 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1517 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1518 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1519 NUM_BANKS(ADDR_SURF_8_BANK)); 1520 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1521 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1522 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1523 NUM_BANKS(ADDR_SURF_8_BANK)); 1524 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1525 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1526 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1527 NUM_BANKS(ADDR_SURF_8_BANK)); 1528 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1529 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1530 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1531 NUM_BANKS(ADDR_SURF_8_BANK)); 1532 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1535 NUM_BANKS(ADDR_SURF_8_BANK)); 1536 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1537 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1538 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1539 NUM_BANKS(ADDR_SURF_16_BANK)); 1540 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1543 NUM_BANKS(ADDR_SURF_16_BANK)); 1544 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1545 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1546 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1547 NUM_BANKS(ADDR_SURF_16_BANK)); 1548 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1551 NUM_BANKS(ADDR_SURF_16_BANK)); 1552 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1555 NUM_BANKS(ADDR_SURF_16_BANK)); 1556 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1557 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1558 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1559 NUM_BANKS(ADDR_SURF_16_BANK)); 1560 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1563 NUM_BANKS(ADDR_SURF_8_BANK)); 1564 1565 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1566 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1567 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1568 if (reg_offset != 7) 1569 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1570 break; 1571 } 1572 } 1573 1574 /** 1575 * gfx_v7_0_select_se_sh - select which SE, SH to address 1576 * 1577 * @adev: amdgpu_device pointer 1578 * @se_num: shader engine to address 1579 * @sh_num: sh block to address 1580 * 1581 * Select which SE, SH combinations to address. Certain 1582 * registers are instanced per SE or SH. 0xffffffff means 1583 * broadcast to all SEs or SHs (CIK). 1584 */ 1585 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1586 u32 se_num, u32 sh_num, u32 instance) 1587 { 1588 u32 data; 1589 1590 if (instance == 0xffffffff) 1591 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1592 else 1593 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1594 1595 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1596 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1597 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1598 else if (se_num == 0xffffffff) 1599 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1600 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1601 else if (sh_num == 0xffffffff) 1602 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1603 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1604 else 1605 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1606 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1607 WREG32(mmGRBM_GFX_INDEX, data); 1608 } 1609 1610 /** 1611 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1612 * 1613 * @adev: amdgpu_device pointer 1614 * 1615 * Calculates the bitmask of enabled RBs (CIK). 1616 * Returns the enabled RB bitmask. 1617 */ 1618 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1619 { 1620 u32 data, mask; 1621 1622 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1623 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1624 1625 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1626 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1627 1628 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1629 adev->gfx.config.max_sh_per_se); 1630 1631 return (~data) & mask; 1632 } 1633 1634 static void 1635 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1636 { 1637 switch (adev->asic_type) { 1638 case CHIP_BONAIRE: 1639 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1640 SE_XSEL(1) | SE_YSEL(1); 1641 *rconf1 |= 0x0; 1642 break; 1643 case CHIP_HAWAII: 1644 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1645 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1646 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1647 SE_YSEL(3); 1648 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1649 SE_PAIR_YSEL(2); 1650 break; 1651 case CHIP_KAVERI: 1652 *rconf |= RB_MAP_PKR0(2); 1653 *rconf1 |= 0x0; 1654 break; 1655 case CHIP_KABINI: 1656 case CHIP_MULLINS: 1657 *rconf |= 0x0; 1658 *rconf1 |= 0x0; 1659 break; 1660 default: 1661 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1662 break; 1663 } 1664 } 1665 1666 static void 1667 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1668 u32 raster_config, u32 raster_config_1, 1669 unsigned rb_mask, unsigned num_rb) 1670 { 1671 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1672 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1673 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1674 unsigned rb_per_se = num_rb / num_se; 1675 unsigned se_mask[4]; 1676 unsigned se; 1677 1678 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1679 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1680 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1681 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1682 1683 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1684 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1685 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1686 1687 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1688 (!se_mask[2] && !se_mask[3]))) { 1689 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1690 1691 if (!se_mask[0] && !se_mask[1]) { 1692 raster_config_1 |= 1693 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1694 } else { 1695 raster_config_1 |= 1696 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1697 } 1698 } 1699 1700 for (se = 0; se < num_se; se++) { 1701 unsigned raster_config_se = raster_config; 1702 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1703 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1704 int idx = (se / 2) * 2; 1705 1706 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1707 raster_config_se &= ~SE_MAP_MASK; 1708 1709 if (!se_mask[idx]) { 1710 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1711 } else { 1712 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1713 } 1714 } 1715 1716 pkr0_mask &= rb_mask; 1717 pkr1_mask &= rb_mask; 1718 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1719 raster_config_se &= ~PKR_MAP_MASK; 1720 1721 if (!pkr0_mask) { 1722 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1723 } else { 1724 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1725 } 1726 } 1727 1728 if (rb_per_se >= 2) { 1729 unsigned rb0_mask = 1 << (se * rb_per_se); 1730 unsigned rb1_mask = rb0_mask << 1; 1731 1732 rb0_mask &= rb_mask; 1733 rb1_mask &= rb_mask; 1734 if (!rb0_mask || !rb1_mask) { 1735 raster_config_se &= ~RB_MAP_PKR0_MASK; 1736 1737 if (!rb0_mask) { 1738 raster_config_se |= 1739 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1740 } else { 1741 raster_config_se |= 1742 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1743 } 1744 } 1745 1746 if (rb_per_se > 2) { 1747 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1748 rb1_mask = rb0_mask << 1; 1749 rb0_mask &= rb_mask; 1750 rb1_mask &= rb_mask; 1751 if (!rb0_mask || !rb1_mask) { 1752 raster_config_se &= ~RB_MAP_PKR1_MASK; 1753 1754 if (!rb0_mask) { 1755 raster_config_se |= 1756 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1757 } else { 1758 raster_config_se |= 1759 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1760 } 1761 } 1762 } 1763 } 1764 1765 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1766 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1767 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1768 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1769 } 1770 1771 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1772 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1773 } 1774 1775 /** 1776 * gfx_v7_0_setup_rb - setup the RBs on the asic 1777 * 1778 * @adev: amdgpu_device pointer 1779 * @se_num: number of SEs (shader engines) for the asic 1780 * @sh_per_se: number of SH blocks per SE for the asic 1781 * 1782 * Configures per-SE/SH RB registers (CIK). 1783 */ 1784 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1785 { 1786 int i, j; 1787 u32 data; 1788 u32 raster_config = 0, raster_config_1 = 0; 1789 u32 active_rbs = 0; 1790 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1791 adev->gfx.config.max_sh_per_se; 1792 unsigned num_rb_pipes; 1793 1794 mutex_lock(&adev->grbm_idx_mutex); 1795 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1796 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1797 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1798 data = gfx_v7_0_get_rb_active_bitmap(adev); 1799 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1800 rb_bitmap_width_per_sh); 1801 } 1802 } 1803 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1804 1805 adev->gfx.config.backend_enable_mask = active_rbs; 1806 adev->gfx.config.num_rbs = hweight32(active_rbs); 1807 1808 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1809 adev->gfx.config.max_shader_engines, 16); 1810 1811 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1812 1813 if (!adev->gfx.config.backend_enable_mask || 1814 adev->gfx.config.num_rbs >= num_rb_pipes) { 1815 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1816 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1817 } else { 1818 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1819 adev->gfx.config.backend_enable_mask, 1820 num_rb_pipes); 1821 } 1822 1823 /* cache the values for userspace */ 1824 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1825 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1826 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1827 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1828 RREG32(mmCC_RB_BACKEND_DISABLE); 1829 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1830 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1831 adev->gfx.config.rb_config[i][j].raster_config = 1832 RREG32(mmPA_SC_RASTER_CONFIG); 1833 adev->gfx.config.rb_config[i][j].raster_config_1 = 1834 RREG32(mmPA_SC_RASTER_CONFIG_1); 1835 } 1836 } 1837 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1838 mutex_unlock(&adev->grbm_idx_mutex); 1839 } 1840 1841 /** 1842 * gfx_v7_0_init_compute_vmid - gart enable 1843 * 1844 * @adev: amdgpu_device pointer 1845 * 1846 * Initialize compute vmid sh_mem registers 1847 * 1848 */ 1849 #define DEFAULT_SH_MEM_BASES (0x6000) 1850 #define FIRST_COMPUTE_VMID (8) 1851 #define LAST_COMPUTE_VMID (16) 1852 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1853 { 1854 int i; 1855 uint32_t sh_mem_config; 1856 uint32_t sh_mem_bases; 1857 1858 /* 1859 * Configure apertures: 1860 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1861 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1862 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1863 */ 1864 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1865 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1866 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1867 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1868 mutex_lock(&adev->srbm_mutex); 1869 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1870 cik_srbm_select(adev, 0, 0, 0, i); 1871 /* CP and shaders */ 1872 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1873 WREG32(mmSH_MEM_APE1_BASE, 1); 1874 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1875 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1876 } 1877 cik_srbm_select(adev, 0, 0, 0, 0); 1878 mutex_unlock(&adev->srbm_mutex); 1879 } 1880 1881 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1882 { 1883 adev->gfx.config.double_offchip_lds_buf = 1; 1884 } 1885 1886 /** 1887 * gfx_v7_0_gpu_init - setup the 3D engine 1888 * 1889 * @adev: amdgpu_device pointer 1890 * 1891 * Configures the 3D engine and tiling configuration 1892 * registers so that the 3D engine is usable. 1893 */ 1894 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 1895 { 1896 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1897 u32 tmp; 1898 int i; 1899 1900 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1901 1902 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1903 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1904 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1905 1906 gfx_v7_0_tiling_mode_table_init(adev); 1907 1908 gfx_v7_0_setup_rb(adev); 1909 gfx_v7_0_get_cu_info(adev); 1910 gfx_v7_0_config_init(adev); 1911 1912 /* set HW defaults for 3D engine */ 1913 WREG32(mmCP_MEQ_THRESHOLDS, 1914 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1915 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1916 1917 mutex_lock(&adev->grbm_idx_mutex); 1918 /* 1919 * making sure that the following register writes will be broadcasted 1920 * to all the shaders 1921 */ 1922 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1923 1924 /* XXX SH_MEM regs */ 1925 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1926 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1927 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1928 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1929 MTYPE_NC); 1930 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1931 MTYPE_UC); 1932 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1933 1934 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1935 SWIZZLE_ENABLE, 1); 1936 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1937 ELEMENT_SIZE, 1); 1938 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1939 INDEX_STRIDE, 3); 1940 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1941 1942 mutex_lock(&adev->srbm_mutex); 1943 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1944 if (i == 0) 1945 sh_mem_base = 0; 1946 else 1947 sh_mem_base = adev->mc.shared_aperture_start >> 48; 1948 cik_srbm_select(adev, 0, 0, 0, i); 1949 /* CP and shaders */ 1950 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1951 WREG32(mmSH_MEM_APE1_BASE, 1); 1952 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1953 WREG32(mmSH_MEM_BASES, sh_mem_base); 1954 } 1955 cik_srbm_select(adev, 0, 0, 0, 0); 1956 mutex_unlock(&adev->srbm_mutex); 1957 1958 gfx_v7_0_init_compute_vmid(adev); 1959 1960 WREG32(mmSX_DEBUG_1, 0x20); 1961 1962 WREG32(mmTA_CNTL_AUX, 0x00010000); 1963 1964 tmp = RREG32(mmSPI_CONFIG_CNTL); 1965 tmp |= 0x03000000; 1966 WREG32(mmSPI_CONFIG_CNTL, tmp); 1967 1968 WREG32(mmSQ_CONFIG, 1); 1969 1970 WREG32(mmDB_DEBUG, 0); 1971 1972 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1973 tmp |= 0x00000400; 1974 WREG32(mmDB_DEBUG2, tmp); 1975 1976 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1977 tmp |= 0x00020200; 1978 WREG32(mmDB_DEBUG3, tmp); 1979 1980 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1981 tmp |= 0x00018208; 1982 WREG32(mmCB_HW_CONTROL, tmp); 1983 1984 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1985 1986 WREG32(mmPA_SC_FIFO_SIZE, 1987 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1988 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1989 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1990 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1991 1992 WREG32(mmVGT_NUM_INSTANCES, 1); 1993 1994 WREG32(mmCP_PERFMON_CNTL, 0); 1995 1996 WREG32(mmSQ_CONFIG, 0); 1997 1998 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1999 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 2000 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 2001 2002 WREG32(mmVGT_CACHE_INVALIDATION, 2003 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 2004 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 2005 2006 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2007 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2008 2009 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2010 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2011 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2012 2013 tmp = RREG32(mmSPI_ARB_PRIORITY); 2014 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2015 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2016 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2017 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2018 WREG32(mmSPI_ARB_PRIORITY, tmp); 2019 2020 mutex_unlock(&adev->grbm_idx_mutex); 2021 2022 udelay(50); 2023 } 2024 2025 /* 2026 * GPU scratch registers helpers function. 2027 */ 2028 /** 2029 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 2030 * 2031 * @adev: amdgpu_device pointer 2032 * 2033 * Set up the number and offset of the CP scratch registers. 2034 * NOTE: use of CP scratch registers is a legacy inferface and 2035 * is not used by default on newer asics (r6xx+). On newer asics, 2036 * memory buffers are used for fences rather than scratch regs. 2037 */ 2038 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 2039 { 2040 adev->gfx.scratch.num_reg = 8; 2041 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 2042 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 2043 } 2044 2045 /** 2046 * gfx_v7_0_ring_test_ring - basic gfx ring test 2047 * 2048 * @adev: amdgpu_device pointer 2049 * @ring: amdgpu_ring structure holding ring information 2050 * 2051 * Allocate a scratch register and write to it using the gfx ring (CIK). 2052 * Provides a basic gfx ring test to verify that the ring is working. 2053 * Used by gfx_v7_0_cp_gfx_resume(); 2054 * Returns 0 on success, error on failure. 2055 */ 2056 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2057 { 2058 struct amdgpu_device *adev = ring->adev; 2059 uint32_t scratch; 2060 uint32_t tmp = 0; 2061 unsigned i; 2062 int r; 2063 2064 r = amdgpu_gfx_scratch_get(adev, &scratch); 2065 if (r) { 2066 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 2067 return r; 2068 } 2069 WREG32(scratch, 0xCAFEDEAD); 2070 r = amdgpu_ring_alloc(ring, 3); 2071 if (r) { 2072 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 2073 amdgpu_gfx_scratch_free(adev, scratch); 2074 return r; 2075 } 2076 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2077 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2078 amdgpu_ring_write(ring, 0xDEADBEEF); 2079 amdgpu_ring_commit(ring); 2080 2081 for (i = 0; i < adev->usec_timeout; i++) { 2082 tmp = RREG32(scratch); 2083 if (tmp == 0xDEADBEEF) 2084 break; 2085 DRM_UDELAY(1); 2086 } 2087 if (i < adev->usec_timeout) { 2088 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2089 } else { 2090 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2091 ring->idx, scratch, tmp); 2092 r = -EINVAL; 2093 } 2094 amdgpu_gfx_scratch_free(adev, scratch); 2095 return r; 2096 } 2097 2098 /** 2099 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 2100 * 2101 * @adev: amdgpu_device pointer 2102 * @ridx: amdgpu ring index 2103 * 2104 * Emits an hdp flush on the cp. 2105 */ 2106 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2107 { 2108 u32 ref_and_mask; 2109 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2110 2111 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2112 switch (ring->me) { 2113 case 1: 2114 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2115 break; 2116 case 2: 2117 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2118 break; 2119 default: 2120 return; 2121 } 2122 } else { 2123 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2124 } 2125 2126 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2127 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2128 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2129 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2130 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2131 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2132 amdgpu_ring_write(ring, ref_and_mask); 2133 amdgpu_ring_write(ring, ref_and_mask); 2134 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2135 } 2136 2137 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2138 { 2139 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2140 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2141 EVENT_INDEX(4)); 2142 2143 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2144 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2145 EVENT_INDEX(0)); 2146 } 2147 2148 2149 /** 2150 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 2151 * 2152 * @adev: amdgpu_device pointer 2153 * @ridx: amdgpu ring index 2154 * 2155 * Emits an hdp invalidate on the cp. 2156 */ 2157 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 2158 { 2159 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2160 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2161 WRITE_DATA_DST_SEL(0) | 2162 WR_CONFIRM)); 2163 amdgpu_ring_write(ring, mmHDP_DEBUG0); 2164 amdgpu_ring_write(ring, 0); 2165 amdgpu_ring_write(ring, 1); 2166 } 2167 2168 /** 2169 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2170 * 2171 * @adev: amdgpu_device pointer 2172 * @fence: amdgpu fence object 2173 * 2174 * Emits a fence sequnce number on the gfx ring and flushes 2175 * GPU caches. 2176 */ 2177 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2178 u64 seq, unsigned flags) 2179 { 2180 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2181 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2182 /* Workaround for cache flush problems. First send a dummy EOP 2183 * event down the pipe with seq one below. 2184 */ 2185 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2186 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2187 EOP_TC_ACTION_EN | 2188 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2189 EVENT_INDEX(5))); 2190 amdgpu_ring_write(ring, addr & 0xfffffffc); 2191 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2192 DATA_SEL(1) | INT_SEL(0)); 2193 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2194 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2195 2196 /* Then send the real EOP event down the pipe. */ 2197 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2198 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2199 EOP_TC_ACTION_EN | 2200 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2201 EVENT_INDEX(5))); 2202 amdgpu_ring_write(ring, addr & 0xfffffffc); 2203 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2204 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2205 amdgpu_ring_write(ring, lower_32_bits(seq)); 2206 amdgpu_ring_write(ring, upper_32_bits(seq)); 2207 } 2208 2209 /** 2210 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2211 * 2212 * @adev: amdgpu_device pointer 2213 * @fence: amdgpu fence object 2214 * 2215 * Emits a fence sequnce number on the compute ring and flushes 2216 * GPU caches. 2217 */ 2218 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2219 u64 addr, u64 seq, 2220 unsigned flags) 2221 { 2222 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2223 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2224 2225 /* RELEASE_MEM - flush caches, send int */ 2226 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2227 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2228 EOP_TC_ACTION_EN | 2229 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2230 EVENT_INDEX(5))); 2231 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2232 amdgpu_ring_write(ring, addr & 0xfffffffc); 2233 amdgpu_ring_write(ring, upper_32_bits(addr)); 2234 amdgpu_ring_write(ring, lower_32_bits(seq)); 2235 amdgpu_ring_write(ring, upper_32_bits(seq)); 2236 } 2237 2238 /* 2239 * IB stuff 2240 */ 2241 /** 2242 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2243 * 2244 * @ring: amdgpu_ring structure holding ring information 2245 * @ib: amdgpu indirect buffer object 2246 * 2247 * Emits an DE (drawing engine) or CE (constant engine) IB 2248 * on the gfx ring. IBs are usually generated by userspace 2249 * acceleration drivers and submitted to the kernel for 2250 * sheduling on the ring. This function schedules the IB 2251 * on the gfx ring for execution by the GPU. 2252 */ 2253 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2254 struct amdgpu_ib *ib, 2255 unsigned vm_id, bool ctx_switch) 2256 { 2257 u32 header, control = 0; 2258 2259 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2260 if (ctx_switch) { 2261 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2262 amdgpu_ring_write(ring, 0); 2263 } 2264 2265 if (ib->flags & AMDGPU_IB_FLAG_CE) 2266 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2267 else 2268 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2269 2270 control |= ib->length_dw | (vm_id << 24); 2271 2272 amdgpu_ring_write(ring, header); 2273 amdgpu_ring_write(ring, 2274 #ifdef __BIG_ENDIAN 2275 (2 << 0) | 2276 #endif 2277 (ib->gpu_addr & 0xFFFFFFFC)); 2278 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2279 amdgpu_ring_write(ring, control); 2280 } 2281 2282 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2283 struct amdgpu_ib *ib, 2284 unsigned vm_id, bool ctx_switch) 2285 { 2286 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 2287 2288 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2289 amdgpu_ring_write(ring, 2290 #ifdef __BIG_ENDIAN 2291 (2 << 0) | 2292 #endif 2293 (ib->gpu_addr & 0xFFFFFFFC)); 2294 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2295 amdgpu_ring_write(ring, control); 2296 } 2297 2298 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2299 { 2300 uint32_t dw2 = 0; 2301 2302 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2303 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2304 gfx_v7_0_ring_emit_vgt_flush(ring); 2305 /* set load_global_config & load_global_uconfig */ 2306 dw2 |= 0x8001; 2307 /* set load_cs_sh_regs */ 2308 dw2 |= 0x01000000; 2309 /* set load_per_context_state & load_gfx_sh_regs */ 2310 dw2 |= 0x10002; 2311 } 2312 2313 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2314 amdgpu_ring_write(ring, dw2); 2315 amdgpu_ring_write(ring, 0); 2316 } 2317 2318 /** 2319 * gfx_v7_0_ring_test_ib - basic ring IB test 2320 * 2321 * @ring: amdgpu_ring structure holding ring information 2322 * 2323 * Allocate an IB and execute it on the gfx ring (CIK). 2324 * Provides a basic gfx ring test to verify that IBs are working. 2325 * Returns 0 on success, error on failure. 2326 */ 2327 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2328 { 2329 struct amdgpu_device *adev = ring->adev; 2330 struct amdgpu_ib ib; 2331 struct dma_fence *f = NULL; 2332 uint32_t scratch; 2333 uint32_t tmp = 0; 2334 long r; 2335 2336 r = amdgpu_gfx_scratch_get(adev, &scratch); 2337 if (r) { 2338 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 2339 return r; 2340 } 2341 WREG32(scratch, 0xCAFEDEAD); 2342 memset(&ib, 0, sizeof(ib)); 2343 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2344 if (r) { 2345 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 2346 goto err1; 2347 } 2348 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2349 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2350 ib.ptr[2] = 0xDEADBEEF; 2351 ib.length_dw = 3; 2352 2353 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2354 if (r) 2355 goto err2; 2356 2357 r = dma_fence_wait_timeout(f, false, timeout); 2358 if (r == 0) { 2359 DRM_ERROR("amdgpu: IB test timed out\n"); 2360 r = -ETIMEDOUT; 2361 goto err2; 2362 } else if (r < 0) { 2363 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 2364 goto err2; 2365 } 2366 tmp = RREG32(scratch); 2367 if (tmp == 0xDEADBEEF) { 2368 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 2369 r = 0; 2370 } else { 2371 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 2372 scratch, tmp); 2373 r = -EINVAL; 2374 } 2375 2376 err2: 2377 amdgpu_ib_free(adev, &ib, NULL); 2378 dma_fence_put(f); 2379 err1: 2380 amdgpu_gfx_scratch_free(adev, scratch); 2381 return r; 2382 } 2383 2384 /* 2385 * CP. 2386 * On CIK, gfx and compute now have independant command processors. 2387 * 2388 * GFX 2389 * Gfx consists of a single ring and can process both gfx jobs and 2390 * compute jobs. The gfx CP consists of three microengines (ME): 2391 * PFP - Pre-Fetch Parser 2392 * ME - Micro Engine 2393 * CE - Constant Engine 2394 * The PFP and ME make up what is considered the Drawing Engine (DE). 2395 * The CE is an asynchronous engine used for updating buffer desciptors 2396 * used by the DE so that they can be loaded into cache in parallel 2397 * while the DE is processing state update packets. 2398 * 2399 * Compute 2400 * The compute CP consists of two microengines (ME): 2401 * MEC1 - Compute MicroEngine 1 2402 * MEC2 - Compute MicroEngine 2 2403 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2404 * The queues are exposed to userspace and are programmed directly 2405 * by the compute runtime. 2406 */ 2407 /** 2408 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2409 * 2410 * @adev: amdgpu_device pointer 2411 * @enable: enable or disable the MEs 2412 * 2413 * Halts or unhalts the gfx MEs. 2414 */ 2415 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2416 { 2417 int i; 2418 2419 if (enable) { 2420 WREG32(mmCP_ME_CNTL, 0); 2421 } else { 2422 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2423 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2424 adev->gfx.gfx_ring[i].ready = false; 2425 } 2426 udelay(50); 2427 } 2428 2429 /** 2430 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2431 * 2432 * @adev: amdgpu_device pointer 2433 * 2434 * Loads the gfx PFP, ME, and CE ucode. 2435 * Returns 0 for success, -EINVAL if the ucode is not available. 2436 */ 2437 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2438 { 2439 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2440 const struct gfx_firmware_header_v1_0 *ce_hdr; 2441 const struct gfx_firmware_header_v1_0 *me_hdr; 2442 const __le32 *fw_data; 2443 unsigned i, fw_size; 2444 2445 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2446 return -EINVAL; 2447 2448 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2449 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2450 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2451 2452 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2453 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2454 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2455 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2456 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2457 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2458 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2459 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2460 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2461 2462 gfx_v7_0_cp_gfx_enable(adev, false); 2463 2464 /* PFP */ 2465 fw_data = (const __le32 *) 2466 (adev->gfx.pfp_fw->data + 2467 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2468 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2469 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2470 for (i = 0; i < fw_size; i++) 2471 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2472 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2473 2474 /* CE */ 2475 fw_data = (const __le32 *) 2476 (adev->gfx.ce_fw->data + 2477 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2478 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2479 WREG32(mmCP_CE_UCODE_ADDR, 0); 2480 for (i = 0; i < fw_size; i++) 2481 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2482 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2483 2484 /* ME */ 2485 fw_data = (const __le32 *) 2486 (adev->gfx.me_fw->data + 2487 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2488 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2489 WREG32(mmCP_ME_RAM_WADDR, 0); 2490 for (i = 0; i < fw_size; i++) 2491 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2492 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2493 2494 return 0; 2495 } 2496 2497 /** 2498 * gfx_v7_0_cp_gfx_start - start the gfx ring 2499 * 2500 * @adev: amdgpu_device pointer 2501 * 2502 * Enables the ring and loads the clear state context and other 2503 * packets required to init the ring. 2504 * Returns 0 for success, error for failure. 2505 */ 2506 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2507 { 2508 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2509 const struct cs_section_def *sect = NULL; 2510 const struct cs_extent_def *ext = NULL; 2511 int r, i; 2512 2513 /* init the CP */ 2514 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2515 WREG32(mmCP_ENDIAN_SWAP, 0); 2516 WREG32(mmCP_DEVICE_ID, 1); 2517 2518 gfx_v7_0_cp_gfx_enable(adev, true); 2519 2520 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2521 if (r) { 2522 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2523 return r; 2524 } 2525 2526 /* init the CE partitions. CE only used for gfx on CIK */ 2527 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2528 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2529 amdgpu_ring_write(ring, 0x8000); 2530 amdgpu_ring_write(ring, 0x8000); 2531 2532 /* clear state buffer */ 2533 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2534 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2535 2536 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2537 amdgpu_ring_write(ring, 0x80000000); 2538 amdgpu_ring_write(ring, 0x80000000); 2539 2540 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2541 for (ext = sect->section; ext->extent != NULL; ++ext) { 2542 if (sect->id == SECT_CONTEXT) { 2543 amdgpu_ring_write(ring, 2544 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2545 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2546 for (i = 0; i < ext->reg_count; i++) 2547 amdgpu_ring_write(ring, ext->extent[i]); 2548 } 2549 } 2550 } 2551 2552 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2553 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2554 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2555 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2556 2557 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2558 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2559 2560 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2561 amdgpu_ring_write(ring, 0); 2562 2563 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2564 amdgpu_ring_write(ring, 0x00000316); 2565 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2566 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2567 2568 amdgpu_ring_commit(ring); 2569 2570 return 0; 2571 } 2572 2573 /** 2574 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2575 * 2576 * @adev: amdgpu_device pointer 2577 * 2578 * Program the location and size of the gfx ring buffer 2579 * and test it to make sure it's working. 2580 * Returns 0 for success, error for failure. 2581 */ 2582 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2583 { 2584 struct amdgpu_ring *ring; 2585 u32 tmp; 2586 u32 rb_bufsz; 2587 u64 rb_addr, rptr_addr; 2588 int r; 2589 2590 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2591 if (adev->asic_type != CHIP_HAWAII) 2592 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2593 2594 /* Set the write pointer delay */ 2595 WREG32(mmCP_RB_WPTR_DELAY, 0); 2596 2597 /* set the RB to use vmid 0 */ 2598 WREG32(mmCP_RB_VMID, 0); 2599 2600 WREG32(mmSCRATCH_ADDR, 0); 2601 2602 /* ring 0 - compute and gfx */ 2603 /* Set ring buffer size */ 2604 ring = &adev->gfx.gfx_ring[0]; 2605 rb_bufsz = order_base_2(ring->ring_size / 8); 2606 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2607 #ifdef __BIG_ENDIAN 2608 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2609 #endif 2610 WREG32(mmCP_RB0_CNTL, tmp); 2611 2612 /* Initialize the ring buffer's read and write pointers */ 2613 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2614 ring->wptr = 0; 2615 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2616 2617 /* set the wb address wether it's enabled or not */ 2618 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2619 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2620 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2621 2622 /* scratch register shadowing is no longer supported */ 2623 WREG32(mmSCRATCH_UMSK, 0); 2624 2625 mdelay(1); 2626 WREG32(mmCP_RB0_CNTL, tmp); 2627 2628 rb_addr = ring->gpu_addr >> 8; 2629 WREG32(mmCP_RB0_BASE, rb_addr); 2630 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2631 2632 /* start the ring */ 2633 gfx_v7_0_cp_gfx_start(adev); 2634 ring->ready = true; 2635 r = amdgpu_ring_test_ring(ring); 2636 if (r) { 2637 ring->ready = false; 2638 return r; 2639 } 2640 2641 return 0; 2642 } 2643 2644 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2645 { 2646 return ring->adev->wb.wb[ring->rptr_offs]; 2647 } 2648 2649 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2650 { 2651 struct amdgpu_device *adev = ring->adev; 2652 2653 return RREG32(mmCP_RB0_WPTR); 2654 } 2655 2656 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2657 { 2658 struct amdgpu_device *adev = ring->adev; 2659 2660 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2661 (void)RREG32(mmCP_RB0_WPTR); 2662 } 2663 2664 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2665 { 2666 /* XXX check if swapping is necessary on BE */ 2667 return ring->adev->wb.wb[ring->wptr_offs]; 2668 } 2669 2670 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2671 { 2672 struct amdgpu_device *adev = ring->adev; 2673 2674 /* XXX check if swapping is necessary on BE */ 2675 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2676 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2677 } 2678 2679 /** 2680 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2681 * 2682 * @adev: amdgpu_device pointer 2683 * @enable: enable or disable the MEs 2684 * 2685 * Halts or unhalts the compute MEs. 2686 */ 2687 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2688 { 2689 int i; 2690 2691 if (enable) { 2692 WREG32(mmCP_MEC_CNTL, 0); 2693 } else { 2694 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2695 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2696 adev->gfx.compute_ring[i].ready = false; 2697 } 2698 udelay(50); 2699 } 2700 2701 /** 2702 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2703 * 2704 * @adev: amdgpu_device pointer 2705 * 2706 * Loads the compute MEC1&2 ucode. 2707 * Returns 0 for success, -EINVAL if the ucode is not available. 2708 */ 2709 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2710 { 2711 const struct gfx_firmware_header_v1_0 *mec_hdr; 2712 const __le32 *fw_data; 2713 unsigned i, fw_size; 2714 2715 if (!adev->gfx.mec_fw) 2716 return -EINVAL; 2717 2718 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2719 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2720 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2721 adev->gfx.mec_feature_version = le32_to_cpu( 2722 mec_hdr->ucode_feature_version); 2723 2724 gfx_v7_0_cp_compute_enable(adev, false); 2725 2726 /* MEC1 */ 2727 fw_data = (const __le32 *) 2728 (adev->gfx.mec_fw->data + 2729 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2730 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2731 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2732 for (i = 0; i < fw_size; i++) 2733 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2734 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2735 2736 if (adev->asic_type == CHIP_KAVERI) { 2737 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2738 2739 if (!adev->gfx.mec2_fw) 2740 return -EINVAL; 2741 2742 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2743 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2744 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2745 adev->gfx.mec2_feature_version = le32_to_cpu( 2746 mec2_hdr->ucode_feature_version); 2747 2748 /* MEC2 */ 2749 fw_data = (const __le32 *) 2750 (adev->gfx.mec2_fw->data + 2751 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2752 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2753 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2754 for (i = 0; i < fw_size; i++) 2755 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2756 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2757 } 2758 2759 return 0; 2760 } 2761 2762 /** 2763 * gfx_v7_0_cp_compute_fini - stop the compute queues 2764 * 2765 * @adev: amdgpu_device pointer 2766 * 2767 * Stop the compute queues and tear down the driver queue 2768 * info. 2769 */ 2770 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2771 { 2772 int i; 2773 2774 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2775 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2776 2777 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); 2778 } 2779 } 2780 2781 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2782 { 2783 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2784 } 2785 2786 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2787 { 2788 int r; 2789 u32 *hpd; 2790 size_t mec_hpd_size; 2791 2792 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2793 2794 /* take ownership of the relevant compute queues */ 2795 amdgpu_gfx_compute_queue_acquire(adev); 2796 2797 /* allocate space for ALL pipes (even the ones we don't own) */ 2798 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2799 * GFX7_MEC_HPD_SIZE * 2; 2800 2801 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2802 AMDGPU_GEM_DOMAIN_GTT, 2803 &adev->gfx.mec.hpd_eop_obj, 2804 &adev->gfx.mec.hpd_eop_gpu_addr, 2805 (void **)&hpd); 2806 if (r) { 2807 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2808 gfx_v7_0_mec_fini(adev); 2809 return r; 2810 } 2811 2812 /* clear memory. Not sure if this is required or not */ 2813 memset(hpd, 0, mec_hpd_size); 2814 2815 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2816 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2817 2818 return 0; 2819 } 2820 2821 struct hqd_registers 2822 { 2823 u32 cp_mqd_base_addr; 2824 u32 cp_mqd_base_addr_hi; 2825 u32 cp_hqd_active; 2826 u32 cp_hqd_vmid; 2827 u32 cp_hqd_persistent_state; 2828 u32 cp_hqd_pipe_priority; 2829 u32 cp_hqd_queue_priority; 2830 u32 cp_hqd_quantum; 2831 u32 cp_hqd_pq_base; 2832 u32 cp_hqd_pq_base_hi; 2833 u32 cp_hqd_pq_rptr; 2834 u32 cp_hqd_pq_rptr_report_addr; 2835 u32 cp_hqd_pq_rptr_report_addr_hi; 2836 u32 cp_hqd_pq_wptr_poll_addr; 2837 u32 cp_hqd_pq_wptr_poll_addr_hi; 2838 u32 cp_hqd_pq_doorbell_control; 2839 u32 cp_hqd_pq_wptr; 2840 u32 cp_hqd_pq_control; 2841 u32 cp_hqd_ib_base_addr; 2842 u32 cp_hqd_ib_base_addr_hi; 2843 u32 cp_hqd_ib_rptr; 2844 u32 cp_hqd_ib_control; 2845 u32 cp_hqd_iq_timer; 2846 u32 cp_hqd_iq_rptr; 2847 u32 cp_hqd_dequeue_request; 2848 u32 cp_hqd_dma_offload; 2849 u32 cp_hqd_sema_cmd; 2850 u32 cp_hqd_msg_type; 2851 u32 cp_hqd_atomic0_preop_lo; 2852 u32 cp_hqd_atomic0_preop_hi; 2853 u32 cp_hqd_atomic1_preop_lo; 2854 u32 cp_hqd_atomic1_preop_hi; 2855 u32 cp_hqd_hq_scheduler0; 2856 u32 cp_hqd_hq_scheduler1; 2857 u32 cp_mqd_control; 2858 }; 2859 2860 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2861 int mec, int pipe) 2862 { 2863 u64 eop_gpu_addr; 2864 u32 tmp; 2865 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2866 * GFX7_MEC_HPD_SIZE * 2; 2867 2868 mutex_lock(&adev->srbm_mutex); 2869 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2870 2871 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2872 2873 /* write the EOP addr */ 2874 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2875 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2876 2877 /* set the VMID assigned */ 2878 WREG32(mmCP_HPD_EOP_VMID, 0); 2879 2880 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2881 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2882 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2883 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2884 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2885 2886 cik_srbm_select(adev, 0, 0, 0, 0); 2887 mutex_unlock(&adev->srbm_mutex); 2888 } 2889 2890 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) 2891 { 2892 int i; 2893 2894 /* disable the queue if it's active */ 2895 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2896 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2897 for (i = 0; i < adev->usec_timeout; i++) { 2898 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2899 break; 2900 udelay(1); 2901 } 2902 2903 if (i == adev->usec_timeout) 2904 return -ETIMEDOUT; 2905 2906 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2907 WREG32(mmCP_HQD_PQ_RPTR, 0); 2908 WREG32(mmCP_HQD_PQ_WPTR, 0); 2909 } 2910 2911 return 0; 2912 } 2913 2914 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2915 struct cik_mqd *mqd, 2916 uint64_t mqd_gpu_addr, 2917 struct amdgpu_ring *ring) 2918 { 2919 u64 hqd_gpu_addr; 2920 u64 wb_gpu_addr; 2921 2922 /* init the mqd struct */ 2923 memset(mqd, 0, sizeof(struct cik_mqd)); 2924 2925 mqd->header = 0xC0310800; 2926 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2927 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2928 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2929 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2930 2931 /* enable doorbell? */ 2932 mqd->cp_hqd_pq_doorbell_control = 2933 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2934 if (ring->use_doorbell) 2935 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2936 else 2937 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2938 2939 /* set the pointer to the MQD */ 2940 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2941 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2942 2943 /* set MQD vmid to 0 */ 2944 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2945 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2946 2947 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2948 hqd_gpu_addr = ring->gpu_addr >> 8; 2949 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2950 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2951 2952 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2953 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2954 mqd->cp_hqd_pq_control &= 2955 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2956 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2957 2958 mqd->cp_hqd_pq_control |= 2959 order_base_2(ring->ring_size / 8); 2960 mqd->cp_hqd_pq_control |= 2961 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2962 #ifdef __BIG_ENDIAN 2963 mqd->cp_hqd_pq_control |= 2964 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2965 #endif 2966 mqd->cp_hqd_pq_control &= 2967 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2968 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2969 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2970 mqd->cp_hqd_pq_control |= 2971 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2972 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2973 2974 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2975 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2976 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2977 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2978 2979 /* set the wb address wether it's enabled or not */ 2980 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2981 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2982 mqd->cp_hqd_pq_rptr_report_addr_hi = 2983 upper_32_bits(wb_gpu_addr) & 0xffff; 2984 2985 /* enable the doorbell if requested */ 2986 if (ring->use_doorbell) { 2987 mqd->cp_hqd_pq_doorbell_control = 2988 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2989 mqd->cp_hqd_pq_doorbell_control &= 2990 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2991 mqd->cp_hqd_pq_doorbell_control |= 2992 (ring->doorbell_index << 2993 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2994 mqd->cp_hqd_pq_doorbell_control |= 2995 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2996 mqd->cp_hqd_pq_doorbell_control &= 2997 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 2998 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 2999 3000 } else { 3001 mqd->cp_hqd_pq_doorbell_control = 0; 3002 } 3003 3004 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3005 ring->wptr = 0; 3006 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 3007 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3008 3009 /* set the vmid for the queue */ 3010 mqd->cp_hqd_vmid = 0; 3011 3012 /* defaults */ 3013 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 3014 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 3015 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 3016 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 3017 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 3018 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 3019 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 3020 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 3021 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 3022 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 3023 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 3024 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3025 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3026 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 3027 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 3028 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 3029 3030 /* activate the queue */ 3031 mqd->cp_hqd_active = 1; 3032 } 3033 3034 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 3035 { 3036 uint32_t tmp; 3037 uint32_t mqd_reg; 3038 uint32_t *mqd_data; 3039 3040 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 3041 mqd_data = &mqd->cp_mqd_base_addr_lo; 3042 3043 /* disable wptr polling */ 3044 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3045 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3046 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3047 3048 /* program all HQD registers */ 3049 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 3050 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3051 3052 /* activate the HQD */ 3053 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 3054 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3055 3056 return 0; 3057 } 3058 3059 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 3060 { 3061 int r; 3062 u64 mqd_gpu_addr; 3063 struct cik_mqd *mqd; 3064 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3065 3066 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, 3067 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 3068 &mqd_gpu_addr, (void **)&mqd); 3069 if (r) { 3070 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3071 return r; 3072 } 3073 3074 mutex_lock(&adev->srbm_mutex); 3075 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3076 3077 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); 3078 gfx_v7_0_mqd_deactivate(adev); 3079 gfx_v7_0_mqd_commit(adev, mqd); 3080 3081 cik_srbm_select(adev, 0, 0, 0, 0); 3082 mutex_unlock(&adev->srbm_mutex); 3083 3084 amdgpu_bo_kunmap(ring->mqd_obj); 3085 amdgpu_bo_unreserve(ring->mqd_obj); 3086 return 0; 3087 } 3088 3089 /** 3090 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 3091 * 3092 * @adev: amdgpu_device pointer 3093 * 3094 * Program the compute queues and test them to make sure they 3095 * are working. 3096 * Returns 0 for success, error for failure. 3097 */ 3098 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3099 { 3100 int r, i, j; 3101 u32 tmp; 3102 struct amdgpu_ring *ring; 3103 3104 /* fix up chicken bits */ 3105 tmp = RREG32(mmCP_CPF_DEBUG); 3106 tmp |= (1 << 23); 3107 WREG32(mmCP_CPF_DEBUG, tmp); 3108 3109 /* init all pipes (even the ones we don't own) */ 3110 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3111 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3112 gfx_v7_0_compute_pipe_init(adev, i, j); 3113 3114 /* init the queues */ 3115 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3116 r = gfx_v7_0_compute_queue_init(adev, i); 3117 if (r) { 3118 gfx_v7_0_cp_compute_fini(adev); 3119 return r; 3120 } 3121 } 3122 3123 gfx_v7_0_cp_compute_enable(adev, true); 3124 3125 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3126 ring = &adev->gfx.compute_ring[i]; 3127 ring->ready = true; 3128 r = amdgpu_ring_test_ring(ring); 3129 if (r) 3130 ring->ready = false; 3131 } 3132 3133 return 0; 3134 } 3135 3136 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3137 { 3138 gfx_v7_0_cp_gfx_enable(adev, enable); 3139 gfx_v7_0_cp_compute_enable(adev, enable); 3140 } 3141 3142 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3143 { 3144 int r; 3145 3146 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3147 if (r) 3148 return r; 3149 r = gfx_v7_0_cp_compute_load_microcode(adev); 3150 if (r) 3151 return r; 3152 3153 return 0; 3154 } 3155 3156 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3157 bool enable) 3158 { 3159 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3160 3161 if (enable) 3162 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3163 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3164 else 3165 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3166 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3167 WREG32(mmCP_INT_CNTL_RING0, tmp); 3168 } 3169 3170 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3171 { 3172 int r; 3173 3174 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3175 3176 r = gfx_v7_0_cp_load_microcode(adev); 3177 if (r) 3178 return r; 3179 3180 r = gfx_v7_0_cp_gfx_resume(adev); 3181 if (r) 3182 return r; 3183 r = gfx_v7_0_cp_compute_resume(adev); 3184 if (r) 3185 return r; 3186 3187 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3188 3189 return 0; 3190 } 3191 3192 /** 3193 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3194 * 3195 * @ring: the ring to emmit the commands to 3196 * 3197 * Sync the command pipeline with the PFP. E.g. wait for everything 3198 * to be completed. 3199 */ 3200 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3201 { 3202 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3203 uint32_t seq = ring->fence_drv.sync_seq; 3204 uint64_t addr = ring->fence_drv.gpu_addr; 3205 3206 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3207 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3208 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3209 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3210 amdgpu_ring_write(ring, addr & 0xfffffffc); 3211 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3212 amdgpu_ring_write(ring, seq); 3213 amdgpu_ring_write(ring, 0xffffffff); 3214 amdgpu_ring_write(ring, 4); /* poll interval */ 3215 3216 if (usepfp) { 3217 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3218 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3219 amdgpu_ring_write(ring, 0); 3220 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3221 amdgpu_ring_write(ring, 0); 3222 } 3223 } 3224 3225 /* 3226 * vm 3227 * VMID 0 is the physical GPU addresses as used by the kernel. 3228 * VMIDs 1-15 are used for userspace clients and are handled 3229 * by the amdgpu vm/hsa code. 3230 */ 3231 /** 3232 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3233 * 3234 * @adev: amdgpu_device pointer 3235 * 3236 * Update the page table base and flush the VM TLB 3237 * using the CP (CIK). 3238 */ 3239 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3240 unsigned vm_id, uint64_t pd_addr) 3241 { 3242 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3243 3244 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3245 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3246 WRITE_DATA_DST_SEL(0))); 3247 if (vm_id < 8) { 3248 amdgpu_ring_write(ring, 3249 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3250 } else { 3251 amdgpu_ring_write(ring, 3252 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3253 } 3254 amdgpu_ring_write(ring, 0); 3255 amdgpu_ring_write(ring, pd_addr >> 12); 3256 3257 /* bits 0-15 are the VM contexts0-15 */ 3258 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3259 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3260 WRITE_DATA_DST_SEL(0))); 3261 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3262 amdgpu_ring_write(ring, 0); 3263 amdgpu_ring_write(ring, 1 << vm_id); 3264 3265 /* wait for the invalidate to complete */ 3266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3267 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3268 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3269 WAIT_REG_MEM_ENGINE(0))); /* me */ 3270 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3271 amdgpu_ring_write(ring, 0); 3272 amdgpu_ring_write(ring, 0); /* ref */ 3273 amdgpu_ring_write(ring, 0); /* mask */ 3274 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3275 3276 /* compute doesn't have PFP */ 3277 if (usepfp) { 3278 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3279 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3280 amdgpu_ring_write(ring, 0x0); 3281 3282 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3283 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3284 amdgpu_ring_write(ring, 0); 3285 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3286 amdgpu_ring_write(ring, 0); 3287 } 3288 } 3289 3290 /* 3291 * RLC 3292 * The RLC is a multi-purpose microengine that handles a 3293 * variety of functions. 3294 */ 3295 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) 3296 { 3297 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL); 3298 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL); 3299 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL); 3300 } 3301 3302 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3303 { 3304 const u32 *src_ptr; 3305 volatile u32 *dst_ptr; 3306 u32 dws, i; 3307 const struct cs_section_def *cs_data; 3308 int r; 3309 3310 /* allocate rlc buffers */ 3311 if (adev->flags & AMD_IS_APU) { 3312 if (adev->asic_type == CHIP_KAVERI) { 3313 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3314 adev->gfx.rlc.reg_list_size = 3315 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3316 } else { 3317 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3318 adev->gfx.rlc.reg_list_size = 3319 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3320 } 3321 } 3322 adev->gfx.rlc.cs_data = ci_cs_data; 3323 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3324 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3325 3326 src_ptr = adev->gfx.rlc.reg_list; 3327 dws = adev->gfx.rlc.reg_list_size; 3328 dws += (5 * 16) + 48 + 48 + 64; 3329 3330 cs_data = adev->gfx.rlc.cs_data; 3331 3332 if (src_ptr) { 3333 /* save restore block */ 3334 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 3335 AMDGPU_GEM_DOMAIN_VRAM, 3336 &adev->gfx.rlc.save_restore_obj, 3337 &adev->gfx.rlc.save_restore_gpu_addr, 3338 (void **)&adev->gfx.rlc.sr_ptr); 3339 if (r) { 3340 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r); 3341 gfx_v7_0_rlc_fini(adev); 3342 return r; 3343 } 3344 3345 /* write the sr buffer */ 3346 dst_ptr = adev->gfx.rlc.sr_ptr; 3347 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3348 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 3349 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 3350 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3351 } 3352 3353 if (cs_data) { 3354 /* clear state block */ 3355 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); 3356 3357 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 3358 AMDGPU_GEM_DOMAIN_VRAM, 3359 &adev->gfx.rlc.clear_state_obj, 3360 &adev->gfx.rlc.clear_state_gpu_addr, 3361 (void **)&adev->gfx.rlc.cs_ptr); 3362 if (r) { 3363 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 3364 gfx_v7_0_rlc_fini(adev); 3365 return r; 3366 } 3367 3368 /* set up the cs buffer */ 3369 dst_ptr = adev->gfx.rlc.cs_ptr; 3370 gfx_v7_0_get_csb_buffer(adev, dst_ptr); 3371 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 3372 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3373 } 3374 3375 if (adev->gfx.rlc.cp_table_size) { 3376 3377 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, 3378 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 3379 &adev->gfx.rlc.cp_table_obj, 3380 &adev->gfx.rlc.cp_table_gpu_addr, 3381 (void **)&adev->gfx.rlc.cp_table_ptr); 3382 if (r) { 3383 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 3384 gfx_v7_0_rlc_fini(adev); 3385 return r; 3386 } 3387 3388 gfx_v7_0_init_cp_pg_table(adev); 3389 3390 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 3391 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3392 3393 } 3394 3395 return 0; 3396 } 3397 3398 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3399 { 3400 u32 tmp; 3401 3402 tmp = RREG32(mmRLC_LB_CNTL); 3403 if (enable) 3404 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3405 else 3406 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3407 WREG32(mmRLC_LB_CNTL, tmp); 3408 } 3409 3410 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3411 { 3412 u32 i, j, k; 3413 u32 mask; 3414 3415 mutex_lock(&adev->grbm_idx_mutex); 3416 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3417 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3418 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3419 for (k = 0; k < adev->usec_timeout; k++) { 3420 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3421 break; 3422 udelay(1); 3423 } 3424 } 3425 } 3426 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3427 mutex_unlock(&adev->grbm_idx_mutex); 3428 3429 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3430 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3431 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3432 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3433 for (k = 0; k < adev->usec_timeout; k++) { 3434 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3435 break; 3436 udelay(1); 3437 } 3438 } 3439 3440 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3441 { 3442 u32 tmp; 3443 3444 tmp = RREG32(mmRLC_CNTL); 3445 if (tmp != rlc) 3446 WREG32(mmRLC_CNTL, rlc); 3447 } 3448 3449 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3450 { 3451 u32 data, orig; 3452 3453 orig = data = RREG32(mmRLC_CNTL); 3454 3455 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3456 u32 i; 3457 3458 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3459 WREG32(mmRLC_CNTL, data); 3460 3461 for (i = 0; i < adev->usec_timeout; i++) { 3462 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3463 break; 3464 udelay(1); 3465 } 3466 3467 gfx_v7_0_wait_for_rlc_serdes(adev); 3468 } 3469 3470 return orig; 3471 } 3472 3473 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3474 { 3475 u32 tmp, i, mask; 3476 3477 tmp = 0x1 | (1 << 1); 3478 WREG32(mmRLC_GPR_REG2, tmp); 3479 3480 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3481 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3482 for (i = 0; i < adev->usec_timeout; i++) { 3483 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3484 break; 3485 udelay(1); 3486 } 3487 3488 for (i = 0; i < adev->usec_timeout; i++) { 3489 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3490 break; 3491 udelay(1); 3492 } 3493 } 3494 3495 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3496 { 3497 u32 tmp; 3498 3499 tmp = 0x1 | (0 << 1); 3500 WREG32(mmRLC_GPR_REG2, tmp); 3501 } 3502 3503 /** 3504 * gfx_v7_0_rlc_stop - stop the RLC ME 3505 * 3506 * @adev: amdgpu_device pointer 3507 * 3508 * Halt the RLC ME (MicroEngine) (CIK). 3509 */ 3510 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3511 { 3512 WREG32(mmRLC_CNTL, 0); 3513 3514 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3515 3516 gfx_v7_0_wait_for_rlc_serdes(adev); 3517 } 3518 3519 /** 3520 * gfx_v7_0_rlc_start - start the RLC ME 3521 * 3522 * @adev: amdgpu_device pointer 3523 * 3524 * Unhalt the RLC ME (MicroEngine) (CIK). 3525 */ 3526 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3527 { 3528 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3529 3530 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3531 3532 udelay(50); 3533 } 3534 3535 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3536 { 3537 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3538 3539 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3540 WREG32(mmGRBM_SOFT_RESET, tmp); 3541 udelay(50); 3542 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3543 WREG32(mmGRBM_SOFT_RESET, tmp); 3544 udelay(50); 3545 } 3546 3547 /** 3548 * gfx_v7_0_rlc_resume - setup the RLC hw 3549 * 3550 * @adev: amdgpu_device pointer 3551 * 3552 * Initialize the RLC registers, load the ucode, 3553 * and start the RLC (CIK). 3554 * Returns 0 for success, -EINVAL if the ucode is not available. 3555 */ 3556 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3557 { 3558 const struct rlc_firmware_header_v1_0 *hdr; 3559 const __le32 *fw_data; 3560 unsigned i, fw_size; 3561 u32 tmp; 3562 3563 if (!adev->gfx.rlc_fw) 3564 return -EINVAL; 3565 3566 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3567 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3568 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3569 adev->gfx.rlc_feature_version = le32_to_cpu( 3570 hdr->ucode_feature_version); 3571 3572 gfx_v7_0_rlc_stop(adev); 3573 3574 /* disable CG */ 3575 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3576 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3577 3578 gfx_v7_0_rlc_reset(adev); 3579 3580 gfx_v7_0_init_pg(adev); 3581 3582 WREG32(mmRLC_LB_CNTR_INIT, 0); 3583 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3584 3585 mutex_lock(&adev->grbm_idx_mutex); 3586 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3587 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3588 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3589 WREG32(mmRLC_LB_CNTL, 0x80000004); 3590 mutex_unlock(&adev->grbm_idx_mutex); 3591 3592 WREG32(mmRLC_MC_CNTL, 0); 3593 WREG32(mmRLC_UCODE_CNTL, 0); 3594 3595 fw_data = (const __le32 *) 3596 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3597 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3598 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3599 for (i = 0; i < fw_size; i++) 3600 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3601 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3602 3603 /* XXX - find out what chips support lbpw */ 3604 gfx_v7_0_enable_lbpw(adev, false); 3605 3606 if (adev->asic_type == CHIP_BONAIRE) 3607 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3608 3609 gfx_v7_0_rlc_start(adev); 3610 3611 return 0; 3612 } 3613 3614 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3615 { 3616 u32 data, orig, tmp, tmp2; 3617 3618 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3619 3620 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3621 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3622 3623 tmp = gfx_v7_0_halt_rlc(adev); 3624 3625 mutex_lock(&adev->grbm_idx_mutex); 3626 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3627 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3628 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3629 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3630 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3631 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3632 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3633 mutex_unlock(&adev->grbm_idx_mutex); 3634 3635 gfx_v7_0_update_rlc(adev, tmp); 3636 3637 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3638 if (orig != data) 3639 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3640 3641 } else { 3642 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3643 3644 RREG32(mmCB_CGTT_SCLK_CTRL); 3645 RREG32(mmCB_CGTT_SCLK_CTRL); 3646 RREG32(mmCB_CGTT_SCLK_CTRL); 3647 RREG32(mmCB_CGTT_SCLK_CTRL); 3648 3649 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3650 if (orig != data) 3651 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3652 3653 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3654 } 3655 } 3656 3657 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3658 { 3659 u32 data, orig, tmp = 0; 3660 3661 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3662 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3663 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3664 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3665 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3666 if (orig != data) 3667 WREG32(mmCP_MEM_SLP_CNTL, data); 3668 } 3669 } 3670 3671 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3672 data |= 0x00000001; 3673 data &= 0xfffffffd; 3674 if (orig != data) 3675 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3676 3677 tmp = gfx_v7_0_halt_rlc(adev); 3678 3679 mutex_lock(&adev->grbm_idx_mutex); 3680 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3681 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3682 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3683 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3684 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3685 WREG32(mmRLC_SERDES_WR_CTRL, data); 3686 mutex_unlock(&adev->grbm_idx_mutex); 3687 3688 gfx_v7_0_update_rlc(adev, tmp); 3689 3690 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3691 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3692 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3693 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3694 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3695 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3696 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3697 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3698 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3699 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3700 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3701 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3702 if (orig != data) 3703 WREG32(mmCGTS_SM_CTRL_REG, data); 3704 } 3705 } else { 3706 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3707 data |= 0x00000003; 3708 if (orig != data) 3709 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3710 3711 data = RREG32(mmRLC_MEM_SLP_CNTL); 3712 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3713 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3714 WREG32(mmRLC_MEM_SLP_CNTL, data); 3715 } 3716 3717 data = RREG32(mmCP_MEM_SLP_CNTL); 3718 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3719 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3720 WREG32(mmCP_MEM_SLP_CNTL, data); 3721 } 3722 3723 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3724 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3725 if (orig != data) 3726 WREG32(mmCGTS_SM_CTRL_REG, data); 3727 3728 tmp = gfx_v7_0_halt_rlc(adev); 3729 3730 mutex_lock(&adev->grbm_idx_mutex); 3731 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3732 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3733 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3734 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3735 WREG32(mmRLC_SERDES_WR_CTRL, data); 3736 mutex_unlock(&adev->grbm_idx_mutex); 3737 3738 gfx_v7_0_update_rlc(adev, tmp); 3739 } 3740 } 3741 3742 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3743 bool enable) 3744 { 3745 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3746 /* order matters! */ 3747 if (enable) { 3748 gfx_v7_0_enable_mgcg(adev, true); 3749 gfx_v7_0_enable_cgcg(adev, true); 3750 } else { 3751 gfx_v7_0_enable_cgcg(adev, false); 3752 gfx_v7_0_enable_mgcg(adev, false); 3753 } 3754 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3755 } 3756 3757 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3758 bool enable) 3759 { 3760 u32 data, orig; 3761 3762 orig = data = RREG32(mmRLC_PG_CNTL); 3763 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3764 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3765 else 3766 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3767 if (orig != data) 3768 WREG32(mmRLC_PG_CNTL, data); 3769 } 3770 3771 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3772 bool enable) 3773 { 3774 u32 data, orig; 3775 3776 orig = data = RREG32(mmRLC_PG_CNTL); 3777 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3778 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3779 else 3780 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3781 if (orig != data) 3782 WREG32(mmRLC_PG_CNTL, data); 3783 } 3784 3785 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3786 { 3787 u32 data, orig; 3788 3789 orig = data = RREG32(mmRLC_PG_CNTL); 3790 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3791 data &= ~0x8000; 3792 else 3793 data |= 0x8000; 3794 if (orig != data) 3795 WREG32(mmRLC_PG_CNTL, data); 3796 } 3797 3798 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3799 { 3800 u32 data, orig; 3801 3802 orig = data = RREG32(mmRLC_PG_CNTL); 3803 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3804 data &= ~0x2000; 3805 else 3806 data |= 0x2000; 3807 if (orig != data) 3808 WREG32(mmRLC_PG_CNTL, data); 3809 } 3810 3811 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) 3812 { 3813 const __le32 *fw_data; 3814 volatile u32 *dst_ptr; 3815 int me, i, max_me = 4; 3816 u32 bo_offset = 0; 3817 u32 table_offset, table_size; 3818 3819 if (adev->asic_type == CHIP_KAVERI) 3820 max_me = 5; 3821 3822 if (adev->gfx.rlc.cp_table_ptr == NULL) 3823 return; 3824 3825 /* write the cp table buffer */ 3826 dst_ptr = adev->gfx.rlc.cp_table_ptr; 3827 for (me = 0; me < max_me; me++) { 3828 if (me == 0) { 3829 const struct gfx_firmware_header_v1_0 *hdr = 3830 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3831 fw_data = (const __le32 *) 3832 (adev->gfx.ce_fw->data + 3833 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3834 table_offset = le32_to_cpu(hdr->jt_offset); 3835 table_size = le32_to_cpu(hdr->jt_size); 3836 } else if (me == 1) { 3837 const struct gfx_firmware_header_v1_0 *hdr = 3838 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3839 fw_data = (const __le32 *) 3840 (adev->gfx.pfp_fw->data + 3841 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3842 table_offset = le32_to_cpu(hdr->jt_offset); 3843 table_size = le32_to_cpu(hdr->jt_size); 3844 } else if (me == 2) { 3845 const struct gfx_firmware_header_v1_0 *hdr = 3846 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3847 fw_data = (const __le32 *) 3848 (adev->gfx.me_fw->data + 3849 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3850 table_offset = le32_to_cpu(hdr->jt_offset); 3851 table_size = le32_to_cpu(hdr->jt_size); 3852 } else if (me == 3) { 3853 const struct gfx_firmware_header_v1_0 *hdr = 3854 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3855 fw_data = (const __le32 *) 3856 (adev->gfx.mec_fw->data + 3857 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3858 table_offset = le32_to_cpu(hdr->jt_offset); 3859 table_size = le32_to_cpu(hdr->jt_size); 3860 } else { 3861 const struct gfx_firmware_header_v1_0 *hdr = 3862 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 3863 fw_data = (const __le32 *) 3864 (adev->gfx.mec2_fw->data + 3865 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3866 table_offset = le32_to_cpu(hdr->jt_offset); 3867 table_size = le32_to_cpu(hdr->jt_size); 3868 } 3869 3870 for (i = 0; i < table_size; i ++) { 3871 dst_ptr[bo_offset + i] = 3872 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 3873 } 3874 3875 bo_offset += table_size; 3876 } 3877 } 3878 3879 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3880 bool enable) 3881 { 3882 u32 data, orig; 3883 3884 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3885 orig = data = RREG32(mmRLC_PG_CNTL); 3886 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3887 if (orig != data) 3888 WREG32(mmRLC_PG_CNTL, data); 3889 3890 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3891 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3892 if (orig != data) 3893 WREG32(mmRLC_AUTO_PG_CTRL, data); 3894 } else { 3895 orig = data = RREG32(mmRLC_PG_CNTL); 3896 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3897 if (orig != data) 3898 WREG32(mmRLC_PG_CNTL, data); 3899 3900 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3901 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3902 if (orig != data) 3903 WREG32(mmRLC_AUTO_PG_CTRL, data); 3904 3905 data = RREG32(mmDB_RENDER_CONTROL); 3906 } 3907 } 3908 3909 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3910 u32 bitmap) 3911 { 3912 u32 data; 3913 3914 if (!bitmap) 3915 return; 3916 3917 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3918 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3919 3920 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3921 } 3922 3923 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3924 { 3925 u32 data, mask; 3926 3927 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3928 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3929 3930 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3931 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3932 3933 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3934 3935 return (~data) & mask; 3936 } 3937 3938 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3939 { 3940 u32 tmp; 3941 3942 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3943 3944 tmp = RREG32(mmRLC_MAX_PG_CU); 3945 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3946 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3947 WREG32(mmRLC_MAX_PG_CU, tmp); 3948 } 3949 3950 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3951 bool enable) 3952 { 3953 u32 data, orig; 3954 3955 orig = data = RREG32(mmRLC_PG_CNTL); 3956 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3957 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3958 else 3959 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3960 if (orig != data) 3961 WREG32(mmRLC_PG_CNTL, data); 3962 } 3963 3964 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3965 bool enable) 3966 { 3967 u32 data, orig; 3968 3969 orig = data = RREG32(mmRLC_PG_CNTL); 3970 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3971 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3972 else 3973 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3974 if (orig != data) 3975 WREG32(mmRLC_PG_CNTL, data); 3976 } 3977 3978 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3979 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3980 3981 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3982 { 3983 u32 data, orig; 3984 u32 i; 3985 3986 if (adev->gfx.rlc.cs_data) { 3987 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3988 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3989 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3990 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3991 } else { 3992 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3993 for (i = 0; i < 3; i++) 3994 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3995 } 3996 if (adev->gfx.rlc.reg_list) { 3997 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3998 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3999 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 4000 } 4001 4002 orig = data = RREG32(mmRLC_PG_CNTL); 4003 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 4004 if (orig != data) 4005 WREG32(mmRLC_PG_CNTL, data); 4006 4007 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 4008 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4009 4010 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 4011 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 4012 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4013 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 4014 4015 data = 0x10101010; 4016 WREG32(mmRLC_PG_DELAY, data); 4017 4018 data = RREG32(mmRLC_PG_DELAY_2); 4019 data &= ~0xff; 4020 data |= 0x3; 4021 WREG32(mmRLC_PG_DELAY_2, data); 4022 4023 data = RREG32(mmRLC_AUTO_PG_CTRL); 4024 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 4025 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 4026 WREG32(mmRLC_AUTO_PG_CTRL, data); 4027 4028 } 4029 4030 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 4031 { 4032 gfx_v7_0_enable_gfx_cgpg(adev, enable); 4033 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 4034 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 4035 } 4036 4037 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 4038 { 4039 u32 count = 0; 4040 const struct cs_section_def *sect = NULL; 4041 const struct cs_extent_def *ext = NULL; 4042 4043 if (adev->gfx.rlc.cs_data == NULL) 4044 return 0; 4045 4046 /* begin clear state */ 4047 count += 2; 4048 /* context control state */ 4049 count += 3; 4050 4051 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4052 for (ext = sect->section; ext->extent != NULL; ++ext) { 4053 if (sect->id == SECT_CONTEXT) 4054 count += 2 + ext->reg_count; 4055 else 4056 return 0; 4057 } 4058 } 4059 /* pa_sc_raster_config/pa_sc_raster_config1 */ 4060 count += 4; 4061 /* end clear state */ 4062 count += 2; 4063 /* clear state */ 4064 count += 2; 4065 4066 return count; 4067 } 4068 4069 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 4070 volatile u32 *buffer) 4071 { 4072 u32 count = 0, i; 4073 const struct cs_section_def *sect = NULL; 4074 const struct cs_extent_def *ext = NULL; 4075 4076 if (adev->gfx.rlc.cs_data == NULL) 4077 return; 4078 if (buffer == NULL) 4079 return; 4080 4081 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4082 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4083 4084 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4085 buffer[count++] = cpu_to_le32(0x80000000); 4086 buffer[count++] = cpu_to_le32(0x80000000); 4087 4088 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4089 for (ext = sect->section; ext->extent != NULL; ++ext) { 4090 if (sect->id == SECT_CONTEXT) { 4091 buffer[count++] = 4092 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4093 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4094 for (i = 0; i < ext->reg_count; i++) 4095 buffer[count++] = cpu_to_le32(ext->extent[i]); 4096 } else { 4097 return; 4098 } 4099 } 4100 } 4101 4102 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4103 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4104 switch (adev->asic_type) { 4105 case CHIP_BONAIRE: 4106 buffer[count++] = cpu_to_le32(0x16000012); 4107 buffer[count++] = cpu_to_le32(0x00000000); 4108 break; 4109 case CHIP_KAVERI: 4110 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4111 buffer[count++] = cpu_to_le32(0x00000000); 4112 break; 4113 case CHIP_KABINI: 4114 case CHIP_MULLINS: 4115 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4116 buffer[count++] = cpu_to_le32(0x00000000); 4117 break; 4118 case CHIP_HAWAII: 4119 buffer[count++] = cpu_to_le32(0x3a00161a); 4120 buffer[count++] = cpu_to_le32(0x0000002e); 4121 break; 4122 default: 4123 buffer[count++] = cpu_to_le32(0x00000000); 4124 buffer[count++] = cpu_to_le32(0x00000000); 4125 break; 4126 } 4127 4128 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4129 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4130 4131 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4132 buffer[count++] = cpu_to_le32(0); 4133 } 4134 4135 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4136 { 4137 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4138 AMD_PG_SUPPORT_GFX_SMG | 4139 AMD_PG_SUPPORT_GFX_DMG | 4140 AMD_PG_SUPPORT_CP | 4141 AMD_PG_SUPPORT_GDS | 4142 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4143 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4144 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4145 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4146 gfx_v7_0_init_gfx_cgpg(adev); 4147 gfx_v7_0_enable_cp_pg(adev, true); 4148 gfx_v7_0_enable_gds_pg(adev, true); 4149 } 4150 gfx_v7_0_init_ao_cu_mask(adev); 4151 gfx_v7_0_update_gfx_pg(adev, true); 4152 } 4153 } 4154 4155 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4156 { 4157 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4158 AMD_PG_SUPPORT_GFX_SMG | 4159 AMD_PG_SUPPORT_GFX_DMG | 4160 AMD_PG_SUPPORT_CP | 4161 AMD_PG_SUPPORT_GDS | 4162 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4163 gfx_v7_0_update_gfx_pg(adev, false); 4164 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4165 gfx_v7_0_enable_cp_pg(adev, false); 4166 gfx_v7_0_enable_gds_pg(adev, false); 4167 } 4168 } 4169 } 4170 4171 /** 4172 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4173 * 4174 * @adev: amdgpu_device pointer 4175 * 4176 * Fetches a GPU clock counter snapshot (SI). 4177 * Returns the 64 bit clock counter snapshot. 4178 */ 4179 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4180 { 4181 uint64_t clock; 4182 4183 mutex_lock(&adev->gfx.gpu_clock_mutex); 4184 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4185 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4186 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4187 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4188 return clock; 4189 } 4190 4191 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4192 uint32_t vmid, 4193 uint32_t gds_base, uint32_t gds_size, 4194 uint32_t gws_base, uint32_t gws_size, 4195 uint32_t oa_base, uint32_t oa_size) 4196 { 4197 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 4198 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 4199 4200 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 4201 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 4202 4203 oa_base = oa_base >> AMDGPU_OA_SHIFT; 4204 oa_size = oa_size >> AMDGPU_OA_SHIFT; 4205 4206 /* GDS Base */ 4207 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4208 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4209 WRITE_DATA_DST_SEL(0))); 4210 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4211 amdgpu_ring_write(ring, 0); 4212 amdgpu_ring_write(ring, gds_base); 4213 4214 /* GDS Size */ 4215 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4216 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4217 WRITE_DATA_DST_SEL(0))); 4218 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4219 amdgpu_ring_write(ring, 0); 4220 amdgpu_ring_write(ring, gds_size); 4221 4222 /* GWS */ 4223 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4224 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4225 WRITE_DATA_DST_SEL(0))); 4226 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4227 amdgpu_ring_write(ring, 0); 4228 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4229 4230 /* OA */ 4231 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4232 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4233 WRITE_DATA_DST_SEL(0))); 4234 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4235 amdgpu_ring_write(ring, 0); 4236 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4237 } 4238 4239 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4240 { 4241 WREG32(mmSQ_IND_INDEX, 4242 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4243 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4244 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4245 (SQ_IND_INDEX__FORCE_READ_MASK)); 4246 return RREG32(mmSQ_IND_DATA); 4247 } 4248 4249 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4250 uint32_t wave, uint32_t thread, 4251 uint32_t regno, uint32_t num, uint32_t *out) 4252 { 4253 WREG32(mmSQ_IND_INDEX, 4254 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4255 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4256 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4257 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4258 (SQ_IND_INDEX__FORCE_READ_MASK) | 4259 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4260 while (num--) 4261 *(out++) = RREG32(mmSQ_IND_DATA); 4262 } 4263 4264 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4265 { 4266 /* type 0 wave data */ 4267 dst[(*no_fields)++] = 0; 4268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4270 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4271 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4272 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4273 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4274 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4276 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4277 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4278 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4279 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4280 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4281 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4282 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4283 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4284 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4285 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4286 } 4287 4288 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4289 uint32_t wave, uint32_t start, 4290 uint32_t size, uint32_t *dst) 4291 { 4292 wave_read_regs( 4293 adev, simd, wave, 0, 4294 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4295 } 4296 4297 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4298 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4299 .select_se_sh = &gfx_v7_0_select_se_sh, 4300 .read_wave_data = &gfx_v7_0_read_wave_data, 4301 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4302 }; 4303 4304 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4305 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode, 4306 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode 4307 }; 4308 4309 static int gfx_v7_0_early_init(void *handle) 4310 { 4311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4312 4313 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4314 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4315 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4316 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4317 gfx_v7_0_set_ring_funcs(adev); 4318 gfx_v7_0_set_irq_funcs(adev); 4319 gfx_v7_0_set_gds_init(adev); 4320 4321 return 0; 4322 } 4323 4324 static int gfx_v7_0_late_init(void *handle) 4325 { 4326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4327 int r; 4328 4329 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4330 if (r) 4331 return r; 4332 4333 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4334 if (r) 4335 return r; 4336 4337 return 0; 4338 } 4339 4340 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4341 { 4342 u32 gb_addr_config; 4343 u32 mc_shared_chmap, mc_arb_ramcfg; 4344 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4345 u32 tmp; 4346 4347 switch (adev->asic_type) { 4348 case CHIP_BONAIRE: 4349 adev->gfx.config.max_shader_engines = 2; 4350 adev->gfx.config.max_tile_pipes = 4; 4351 adev->gfx.config.max_cu_per_sh = 7; 4352 adev->gfx.config.max_sh_per_se = 1; 4353 adev->gfx.config.max_backends_per_se = 2; 4354 adev->gfx.config.max_texture_channel_caches = 4; 4355 adev->gfx.config.max_gprs = 256; 4356 adev->gfx.config.max_gs_threads = 32; 4357 adev->gfx.config.max_hw_contexts = 8; 4358 4359 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4360 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4361 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4362 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4363 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4364 break; 4365 case CHIP_HAWAII: 4366 adev->gfx.config.max_shader_engines = 4; 4367 adev->gfx.config.max_tile_pipes = 16; 4368 adev->gfx.config.max_cu_per_sh = 11; 4369 adev->gfx.config.max_sh_per_se = 1; 4370 adev->gfx.config.max_backends_per_se = 4; 4371 adev->gfx.config.max_texture_channel_caches = 16; 4372 adev->gfx.config.max_gprs = 256; 4373 adev->gfx.config.max_gs_threads = 32; 4374 adev->gfx.config.max_hw_contexts = 8; 4375 4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4380 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4381 break; 4382 case CHIP_KAVERI: 4383 adev->gfx.config.max_shader_engines = 1; 4384 adev->gfx.config.max_tile_pipes = 4; 4385 if ((adev->pdev->device == 0x1304) || 4386 (adev->pdev->device == 0x1305) || 4387 (adev->pdev->device == 0x130C) || 4388 (adev->pdev->device == 0x130F) || 4389 (adev->pdev->device == 0x1310) || 4390 (adev->pdev->device == 0x1311) || 4391 (adev->pdev->device == 0x131C)) { 4392 adev->gfx.config.max_cu_per_sh = 8; 4393 adev->gfx.config.max_backends_per_se = 2; 4394 } else if ((adev->pdev->device == 0x1309) || 4395 (adev->pdev->device == 0x130A) || 4396 (adev->pdev->device == 0x130D) || 4397 (adev->pdev->device == 0x1313) || 4398 (adev->pdev->device == 0x131D)) { 4399 adev->gfx.config.max_cu_per_sh = 6; 4400 adev->gfx.config.max_backends_per_se = 2; 4401 } else if ((adev->pdev->device == 0x1306) || 4402 (adev->pdev->device == 0x1307) || 4403 (adev->pdev->device == 0x130B) || 4404 (adev->pdev->device == 0x130E) || 4405 (adev->pdev->device == 0x1315) || 4406 (adev->pdev->device == 0x131B)) { 4407 adev->gfx.config.max_cu_per_sh = 4; 4408 adev->gfx.config.max_backends_per_se = 1; 4409 } else { 4410 adev->gfx.config.max_cu_per_sh = 3; 4411 adev->gfx.config.max_backends_per_se = 1; 4412 } 4413 adev->gfx.config.max_sh_per_se = 1; 4414 adev->gfx.config.max_texture_channel_caches = 4; 4415 adev->gfx.config.max_gprs = 256; 4416 adev->gfx.config.max_gs_threads = 16; 4417 adev->gfx.config.max_hw_contexts = 8; 4418 4419 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4420 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4421 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4422 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4423 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4424 break; 4425 case CHIP_KABINI: 4426 case CHIP_MULLINS: 4427 default: 4428 adev->gfx.config.max_shader_engines = 1; 4429 adev->gfx.config.max_tile_pipes = 2; 4430 adev->gfx.config.max_cu_per_sh = 2; 4431 adev->gfx.config.max_sh_per_se = 1; 4432 adev->gfx.config.max_backends_per_se = 1; 4433 adev->gfx.config.max_texture_channel_caches = 2; 4434 adev->gfx.config.max_gprs = 256; 4435 adev->gfx.config.max_gs_threads = 16; 4436 adev->gfx.config.max_hw_contexts = 8; 4437 4438 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4439 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4440 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4441 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4442 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4443 break; 4444 } 4445 4446 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 4447 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4448 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4449 4450 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4451 adev->gfx.config.mem_max_burst_length_bytes = 256; 4452 if (adev->flags & AMD_IS_APU) { 4453 /* Get memory bank mapping mode. */ 4454 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4455 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4456 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4457 4458 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4459 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4460 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4461 4462 /* Validate settings in case only one DIMM installed. */ 4463 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4464 dimm00_addr_map = 0; 4465 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4466 dimm01_addr_map = 0; 4467 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4468 dimm10_addr_map = 0; 4469 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4470 dimm11_addr_map = 0; 4471 4472 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4473 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4474 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4475 adev->gfx.config.mem_row_size_in_kb = 2; 4476 else 4477 adev->gfx.config.mem_row_size_in_kb = 1; 4478 } else { 4479 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4480 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4481 if (adev->gfx.config.mem_row_size_in_kb > 4) 4482 adev->gfx.config.mem_row_size_in_kb = 4; 4483 } 4484 /* XXX use MC settings? */ 4485 adev->gfx.config.shader_engine_tile_size = 32; 4486 adev->gfx.config.num_gpus = 1; 4487 adev->gfx.config.multi_gpu_tile_size = 64; 4488 4489 /* fix up row size */ 4490 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4491 switch (adev->gfx.config.mem_row_size_in_kb) { 4492 case 1: 4493 default: 4494 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4495 break; 4496 case 2: 4497 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4498 break; 4499 case 4: 4500 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4501 break; 4502 } 4503 adev->gfx.config.gb_addr_config = gb_addr_config; 4504 } 4505 4506 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4507 int mec, int pipe, int queue) 4508 { 4509 int r; 4510 unsigned irq_type; 4511 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4512 4513 /* mec0 is me1 */ 4514 ring->me = mec + 1; 4515 ring->pipe = pipe; 4516 ring->queue = queue; 4517 4518 ring->ring_obj = NULL; 4519 ring->use_doorbell = true; 4520 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id; 4521 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4522 4523 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4524 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4525 + ring->pipe; 4526 4527 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4528 r = amdgpu_ring_init(adev, ring, 1024, 4529 &adev->gfx.eop_irq, irq_type); 4530 if (r) 4531 return r; 4532 4533 4534 return 0; 4535 } 4536 4537 static int gfx_v7_0_sw_init(void *handle) 4538 { 4539 struct amdgpu_ring *ring; 4540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4541 int i, j, k, r, ring_id; 4542 4543 switch (adev->asic_type) { 4544 case CHIP_KAVERI: 4545 adev->gfx.mec.num_mec = 2; 4546 break; 4547 case CHIP_BONAIRE: 4548 case CHIP_HAWAII: 4549 case CHIP_KABINI: 4550 case CHIP_MULLINS: 4551 default: 4552 adev->gfx.mec.num_mec = 1; 4553 break; 4554 } 4555 adev->gfx.mec.num_pipe_per_mec = 4; 4556 adev->gfx.mec.num_queue_per_pipe = 8; 4557 4558 /* EOP Event */ 4559 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4560 if (r) 4561 return r; 4562 4563 /* Privileged reg */ 4564 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, 4565 &adev->gfx.priv_reg_irq); 4566 if (r) 4567 return r; 4568 4569 /* Privileged inst */ 4570 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, 4571 &adev->gfx.priv_inst_irq); 4572 if (r) 4573 return r; 4574 4575 gfx_v7_0_scratch_init(adev); 4576 4577 r = gfx_v7_0_init_microcode(adev); 4578 if (r) { 4579 DRM_ERROR("Failed to load gfx firmware!\n"); 4580 return r; 4581 } 4582 4583 r = gfx_v7_0_rlc_init(adev); 4584 if (r) { 4585 DRM_ERROR("Failed to init rlc BOs!\n"); 4586 return r; 4587 } 4588 4589 /* allocate mec buffers */ 4590 r = gfx_v7_0_mec_init(adev); 4591 if (r) { 4592 DRM_ERROR("Failed to init MEC BOs!\n"); 4593 return r; 4594 } 4595 4596 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4597 ring = &adev->gfx.gfx_ring[i]; 4598 ring->ring_obj = NULL; 4599 sprintf(ring->name, "gfx"); 4600 r = amdgpu_ring_init(adev, ring, 1024, 4601 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 4602 if (r) 4603 return r; 4604 } 4605 4606 /* set up the compute queues - allocate horizontally across pipes */ 4607 ring_id = 0; 4608 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4609 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4610 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4611 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 4612 continue; 4613 4614 r = gfx_v7_0_compute_ring_init(adev, 4615 ring_id, 4616 i, k, j); 4617 if (r) 4618 return r; 4619 4620 ring_id++; 4621 } 4622 } 4623 } 4624 4625 /* reserve GDS, GWS and OA resource for gfx */ 4626 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 4627 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 4628 &adev->gds.gds_gfx_bo, NULL, NULL); 4629 if (r) 4630 return r; 4631 4632 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 4633 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 4634 &adev->gds.gws_gfx_bo, NULL, NULL); 4635 if (r) 4636 return r; 4637 4638 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 4639 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 4640 &adev->gds.oa_gfx_bo, NULL, NULL); 4641 if (r) 4642 return r; 4643 4644 adev->gfx.ce_ram_size = 0x8000; 4645 4646 gfx_v7_0_gpu_early_init(adev); 4647 4648 return r; 4649 } 4650 4651 static int gfx_v7_0_sw_fini(void *handle) 4652 { 4653 int i; 4654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4655 4656 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 4657 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 4658 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 4659 4660 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4661 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4662 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4663 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4664 4665 gfx_v7_0_cp_compute_fini(adev); 4666 gfx_v7_0_rlc_fini(adev); 4667 gfx_v7_0_mec_fini(adev); 4668 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4669 &adev->gfx.rlc.clear_state_gpu_addr, 4670 (void **)&adev->gfx.rlc.cs_ptr); 4671 if (adev->gfx.rlc.cp_table_size) { 4672 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4673 &adev->gfx.rlc.cp_table_gpu_addr, 4674 (void **)&adev->gfx.rlc.cp_table_ptr); 4675 } 4676 gfx_v7_0_free_microcode(adev); 4677 4678 return 0; 4679 } 4680 4681 static int gfx_v7_0_hw_init(void *handle) 4682 { 4683 int r; 4684 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4685 4686 gfx_v7_0_gpu_init(adev); 4687 4688 /* init rlc */ 4689 r = gfx_v7_0_rlc_resume(adev); 4690 if (r) 4691 return r; 4692 4693 r = gfx_v7_0_cp_resume(adev); 4694 if (r) 4695 return r; 4696 4697 return r; 4698 } 4699 4700 static int gfx_v7_0_hw_fini(void *handle) 4701 { 4702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4703 4704 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4705 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4706 gfx_v7_0_cp_enable(adev, false); 4707 gfx_v7_0_rlc_stop(adev); 4708 gfx_v7_0_fini_pg(adev); 4709 4710 return 0; 4711 } 4712 4713 static int gfx_v7_0_suspend(void *handle) 4714 { 4715 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4716 4717 return gfx_v7_0_hw_fini(adev); 4718 } 4719 4720 static int gfx_v7_0_resume(void *handle) 4721 { 4722 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4723 4724 return gfx_v7_0_hw_init(adev); 4725 } 4726 4727 static bool gfx_v7_0_is_idle(void *handle) 4728 { 4729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4730 4731 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4732 return false; 4733 else 4734 return true; 4735 } 4736 4737 static int gfx_v7_0_wait_for_idle(void *handle) 4738 { 4739 unsigned i; 4740 u32 tmp; 4741 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4742 4743 for (i = 0; i < adev->usec_timeout; i++) { 4744 /* read MC_STATUS */ 4745 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4746 4747 if (!tmp) 4748 return 0; 4749 udelay(1); 4750 } 4751 return -ETIMEDOUT; 4752 } 4753 4754 static int gfx_v7_0_soft_reset(void *handle) 4755 { 4756 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4757 u32 tmp; 4758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4759 4760 /* GRBM_STATUS */ 4761 tmp = RREG32(mmGRBM_STATUS); 4762 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4763 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4764 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4765 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4766 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4767 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4768 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4769 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4770 4771 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4772 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4773 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4774 } 4775 4776 /* GRBM_STATUS2 */ 4777 tmp = RREG32(mmGRBM_STATUS2); 4778 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4779 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4780 4781 /* SRBM_STATUS */ 4782 tmp = RREG32(mmSRBM_STATUS); 4783 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4784 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4785 4786 if (grbm_soft_reset || srbm_soft_reset) { 4787 /* disable CG/PG */ 4788 gfx_v7_0_fini_pg(adev); 4789 gfx_v7_0_update_cg(adev, false); 4790 4791 /* stop the rlc */ 4792 gfx_v7_0_rlc_stop(adev); 4793 4794 /* Disable GFX parsing/prefetching */ 4795 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4796 4797 /* Disable MEC parsing/prefetching */ 4798 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4799 4800 if (grbm_soft_reset) { 4801 tmp = RREG32(mmGRBM_SOFT_RESET); 4802 tmp |= grbm_soft_reset; 4803 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4804 WREG32(mmGRBM_SOFT_RESET, tmp); 4805 tmp = RREG32(mmGRBM_SOFT_RESET); 4806 4807 udelay(50); 4808 4809 tmp &= ~grbm_soft_reset; 4810 WREG32(mmGRBM_SOFT_RESET, tmp); 4811 tmp = RREG32(mmGRBM_SOFT_RESET); 4812 } 4813 4814 if (srbm_soft_reset) { 4815 tmp = RREG32(mmSRBM_SOFT_RESET); 4816 tmp |= srbm_soft_reset; 4817 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4818 WREG32(mmSRBM_SOFT_RESET, tmp); 4819 tmp = RREG32(mmSRBM_SOFT_RESET); 4820 4821 udelay(50); 4822 4823 tmp &= ~srbm_soft_reset; 4824 WREG32(mmSRBM_SOFT_RESET, tmp); 4825 tmp = RREG32(mmSRBM_SOFT_RESET); 4826 } 4827 /* Wait a little for things to settle down */ 4828 udelay(50); 4829 } 4830 return 0; 4831 } 4832 4833 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4834 enum amdgpu_interrupt_state state) 4835 { 4836 u32 cp_int_cntl; 4837 4838 switch (state) { 4839 case AMDGPU_IRQ_STATE_DISABLE: 4840 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4841 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4842 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4843 break; 4844 case AMDGPU_IRQ_STATE_ENABLE: 4845 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4846 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4847 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4848 break; 4849 default: 4850 break; 4851 } 4852 } 4853 4854 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4855 int me, int pipe, 4856 enum amdgpu_interrupt_state state) 4857 { 4858 u32 mec_int_cntl, mec_int_cntl_reg; 4859 4860 /* 4861 * amdgpu controls only the first MEC. That's why this function only 4862 * handles the setting of interrupts for this specific MEC. All other 4863 * pipes' interrupts are set by amdkfd. 4864 */ 4865 4866 if (me == 1) { 4867 switch (pipe) { 4868 case 0: 4869 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4870 break; 4871 case 1: 4872 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4873 break; 4874 case 2: 4875 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4876 break; 4877 case 3: 4878 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4879 break; 4880 default: 4881 DRM_DEBUG("invalid pipe %d\n", pipe); 4882 return; 4883 } 4884 } else { 4885 DRM_DEBUG("invalid me %d\n", me); 4886 return; 4887 } 4888 4889 switch (state) { 4890 case AMDGPU_IRQ_STATE_DISABLE: 4891 mec_int_cntl = RREG32(mec_int_cntl_reg); 4892 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4893 WREG32(mec_int_cntl_reg, mec_int_cntl); 4894 break; 4895 case AMDGPU_IRQ_STATE_ENABLE: 4896 mec_int_cntl = RREG32(mec_int_cntl_reg); 4897 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4898 WREG32(mec_int_cntl_reg, mec_int_cntl); 4899 break; 4900 default: 4901 break; 4902 } 4903 } 4904 4905 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4906 struct amdgpu_irq_src *src, 4907 unsigned type, 4908 enum amdgpu_interrupt_state state) 4909 { 4910 u32 cp_int_cntl; 4911 4912 switch (state) { 4913 case AMDGPU_IRQ_STATE_DISABLE: 4914 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4915 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4916 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4917 break; 4918 case AMDGPU_IRQ_STATE_ENABLE: 4919 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4920 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4921 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4922 break; 4923 default: 4924 break; 4925 } 4926 4927 return 0; 4928 } 4929 4930 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4931 struct amdgpu_irq_src *src, 4932 unsigned type, 4933 enum amdgpu_interrupt_state state) 4934 { 4935 u32 cp_int_cntl; 4936 4937 switch (state) { 4938 case AMDGPU_IRQ_STATE_DISABLE: 4939 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4940 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4941 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4942 break; 4943 case AMDGPU_IRQ_STATE_ENABLE: 4944 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4945 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4946 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4947 break; 4948 default: 4949 break; 4950 } 4951 4952 return 0; 4953 } 4954 4955 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4956 struct amdgpu_irq_src *src, 4957 unsigned type, 4958 enum amdgpu_interrupt_state state) 4959 { 4960 switch (type) { 4961 case AMDGPU_CP_IRQ_GFX_EOP: 4962 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4963 break; 4964 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4965 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4966 break; 4967 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4968 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4969 break; 4970 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4971 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4972 break; 4973 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4974 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4975 break; 4976 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4977 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4978 break; 4979 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4980 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4981 break; 4982 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4983 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4984 break; 4985 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4986 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4987 break; 4988 default: 4989 break; 4990 } 4991 return 0; 4992 } 4993 4994 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4995 struct amdgpu_irq_src *source, 4996 struct amdgpu_iv_entry *entry) 4997 { 4998 u8 me_id, pipe_id; 4999 struct amdgpu_ring *ring; 5000 int i; 5001 5002 DRM_DEBUG("IH: CP EOP\n"); 5003 me_id = (entry->ring_id & 0x0c) >> 2; 5004 pipe_id = (entry->ring_id & 0x03) >> 0; 5005 switch (me_id) { 5006 case 0: 5007 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5008 break; 5009 case 1: 5010 case 2: 5011 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5012 ring = &adev->gfx.compute_ring[i]; 5013 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 5014 amdgpu_fence_process(ring); 5015 } 5016 break; 5017 } 5018 return 0; 5019 } 5020 5021 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 5022 struct amdgpu_irq_src *source, 5023 struct amdgpu_iv_entry *entry) 5024 { 5025 DRM_ERROR("Illegal register access in command stream\n"); 5026 schedule_work(&adev->reset_work); 5027 return 0; 5028 } 5029 5030 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 5031 struct amdgpu_irq_src *source, 5032 struct amdgpu_iv_entry *entry) 5033 { 5034 DRM_ERROR("Illegal instruction in command stream\n"); 5035 // XXX soft reset the gfx block only 5036 schedule_work(&adev->reset_work); 5037 return 0; 5038 } 5039 5040 static int gfx_v7_0_set_clockgating_state(void *handle, 5041 enum amd_clockgating_state state) 5042 { 5043 bool gate = false; 5044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5045 5046 if (state == AMD_CG_STATE_GATE) 5047 gate = true; 5048 5049 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 5050 /* order matters! */ 5051 if (gate) { 5052 gfx_v7_0_enable_mgcg(adev, true); 5053 gfx_v7_0_enable_cgcg(adev, true); 5054 } else { 5055 gfx_v7_0_enable_cgcg(adev, false); 5056 gfx_v7_0_enable_mgcg(adev, false); 5057 } 5058 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 5059 5060 return 0; 5061 } 5062 5063 static int gfx_v7_0_set_powergating_state(void *handle, 5064 enum amd_powergating_state state) 5065 { 5066 bool gate = false; 5067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5068 5069 if (state == AMD_PG_STATE_GATE) 5070 gate = true; 5071 5072 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 5073 AMD_PG_SUPPORT_GFX_SMG | 5074 AMD_PG_SUPPORT_GFX_DMG | 5075 AMD_PG_SUPPORT_CP | 5076 AMD_PG_SUPPORT_GDS | 5077 AMD_PG_SUPPORT_RLC_SMU_HS)) { 5078 gfx_v7_0_update_gfx_pg(adev, gate); 5079 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 5080 gfx_v7_0_enable_cp_pg(adev, gate); 5081 gfx_v7_0_enable_gds_pg(adev, gate); 5082 } 5083 } 5084 5085 return 0; 5086 } 5087 5088 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5089 .name = "gfx_v7_0", 5090 .early_init = gfx_v7_0_early_init, 5091 .late_init = gfx_v7_0_late_init, 5092 .sw_init = gfx_v7_0_sw_init, 5093 .sw_fini = gfx_v7_0_sw_fini, 5094 .hw_init = gfx_v7_0_hw_init, 5095 .hw_fini = gfx_v7_0_hw_fini, 5096 .suspend = gfx_v7_0_suspend, 5097 .resume = gfx_v7_0_resume, 5098 .is_idle = gfx_v7_0_is_idle, 5099 .wait_for_idle = gfx_v7_0_wait_for_idle, 5100 .soft_reset = gfx_v7_0_soft_reset, 5101 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5102 .set_powergating_state = gfx_v7_0_set_powergating_state, 5103 }; 5104 5105 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5106 .type = AMDGPU_RING_TYPE_GFX, 5107 .align_mask = 0xff, 5108 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5109 .support_64bit_ptrs = false, 5110 .get_rptr = gfx_v7_0_ring_get_rptr, 5111 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5112 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5113 .emit_frame_size = 5114 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5115 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5116 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5117 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5118 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5119 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5120 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 5121 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5122 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5123 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5124 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5125 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5126 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5127 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5128 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5129 .test_ring = gfx_v7_0_ring_test_ring, 5130 .test_ib = gfx_v7_0_ring_test_ib, 5131 .insert_nop = amdgpu_ring_insert_nop, 5132 .pad_ib = amdgpu_ring_generic_pad_ib, 5133 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5134 }; 5135 5136 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5137 .type = AMDGPU_RING_TYPE_COMPUTE, 5138 .align_mask = 0xff, 5139 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5140 .support_64bit_ptrs = false, 5141 .get_rptr = gfx_v7_0_ring_get_rptr, 5142 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5143 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5144 .emit_frame_size = 5145 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5146 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5147 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5148 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5149 17 + /* gfx_v7_0_ring_emit_vm_flush */ 5150 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5151 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */ 5152 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5153 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5154 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5155 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5156 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5157 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5158 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5159 .test_ring = gfx_v7_0_ring_test_ring, 5160 .test_ib = gfx_v7_0_ring_test_ib, 5161 .insert_nop = amdgpu_ring_insert_nop, 5162 .pad_ib = amdgpu_ring_generic_pad_ib, 5163 }; 5164 5165 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5166 { 5167 int i; 5168 5169 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5170 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5171 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5172 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5173 } 5174 5175 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5176 .set = gfx_v7_0_set_eop_interrupt_state, 5177 .process = gfx_v7_0_eop_irq, 5178 }; 5179 5180 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5181 .set = gfx_v7_0_set_priv_reg_fault_state, 5182 .process = gfx_v7_0_priv_reg_irq, 5183 }; 5184 5185 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5186 .set = gfx_v7_0_set_priv_inst_fault_state, 5187 .process = gfx_v7_0_priv_inst_irq, 5188 }; 5189 5190 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5191 { 5192 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5193 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5194 5195 adev->gfx.priv_reg_irq.num_types = 1; 5196 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5197 5198 adev->gfx.priv_inst_irq.num_types = 1; 5199 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5200 } 5201 5202 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5203 { 5204 /* init asci gds info */ 5205 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 5206 adev->gds.gws.total_size = 64; 5207 adev->gds.oa.total_size = 16; 5208 5209 if (adev->gds.mem.total_size == 64 * 1024) { 5210 adev->gds.mem.gfx_partition_size = 4096; 5211 adev->gds.mem.cs_partition_size = 4096; 5212 5213 adev->gds.gws.gfx_partition_size = 4; 5214 adev->gds.gws.cs_partition_size = 4; 5215 5216 adev->gds.oa.gfx_partition_size = 4; 5217 adev->gds.oa.cs_partition_size = 1; 5218 } else { 5219 adev->gds.mem.gfx_partition_size = 1024; 5220 adev->gds.mem.cs_partition_size = 1024; 5221 5222 adev->gds.gws.gfx_partition_size = 16; 5223 adev->gds.gws.cs_partition_size = 16; 5224 5225 adev->gds.oa.gfx_partition_size = 4; 5226 adev->gds.oa.cs_partition_size = 4; 5227 } 5228 } 5229 5230 5231 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5232 { 5233 int i, j, k, counter, active_cu_number = 0; 5234 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5235 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5236 unsigned disable_masks[4 * 2]; 5237 u32 ao_cu_num; 5238 5239 if (adev->flags & AMD_IS_APU) 5240 ao_cu_num = 2; 5241 else 5242 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5243 5244 memset(cu_info, 0, sizeof(*cu_info)); 5245 5246 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5247 5248 mutex_lock(&adev->grbm_idx_mutex); 5249 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5250 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5251 mask = 1; 5252 ao_bitmap = 0; 5253 counter = 0; 5254 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5255 if (i < 4 && j < 2) 5256 gfx_v7_0_set_user_cu_inactive_bitmap( 5257 adev, disable_masks[i * 2 + j]); 5258 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5259 cu_info->bitmap[i][j] = bitmap; 5260 5261 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5262 if (bitmap & mask) { 5263 if (counter < ao_cu_num) 5264 ao_bitmap |= mask; 5265 counter ++; 5266 } 5267 mask <<= 1; 5268 } 5269 active_cu_number += counter; 5270 if (i < 2 && j < 2) 5271 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5272 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5273 } 5274 } 5275 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5276 mutex_unlock(&adev->grbm_idx_mutex); 5277 5278 cu_info->number = active_cu_number; 5279 cu_info->ao_cu_mask = ao_cu_mask; 5280 } 5281 5282 const struct amdgpu_ip_block_version gfx_v7_0_ip_block = 5283 { 5284 .type = AMD_IP_BLOCK_TYPE_GFX, 5285 .major = 7, 5286 .minor = 0, 5287 .rev = 0, 5288 .funcs = &gfx_v7_0_ip_funcs, 5289 }; 5290 5291 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5292 { 5293 .type = AMD_IP_BLOCK_TYPE_GFX, 5294 .major = 7, 5295 .minor = 1, 5296 .rev = 0, 5297 .funcs = &gfx_v7_0_ip_funcs, 5298 }; 5299 5300 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5301 { 5302 .type = AMD_IP_BLOCK_TYPE_GFX, 5303 .major = 7, 5304 .minor = 2, 5305 .rev = 0, 5306 .funcs = &gfx_v7_0_ip_funcs, 5307 }; 5308 5309 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5310 { 5311 .type = AMD_IP_BLOCK_TYPE_GFX, 5312 .major = 7, 5313 .minor = 3, 5314 .rev = 0, 5315 .funcs = &gfx_v7_0_ip_funcs, 5316 }; 5317