1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ih.h" 27 #include "amdgpu_gfx.h" 28 #include "cikd.h" 29 #include "cik.h" 30 #include "atom.h" 31 #include "amdgpu_ucode.h" 32 #include "clearstate_ci.h" 33 34 #include "dce/dce_8_0_d.h" 35 #include "dce/dce_8_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gca/gfx_7_0_d.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "gca/gfx_7_2_sh_mask.h" 43 44 #include "gmc/gmc_7_0_d.h" 45 #include "gmc/gmc_7_0_sh_mask.h" 46 47 #include "oss/oss_2_0_d.h" 48 #include "oss/oss_2_0_sh_mask.h" 49 50 #define GFX7_NUM_GFX_RINGS 1 51 #define GFX7_NUM_COMPUTE_RINGS 8 52 53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); 58 MODULE_FIRMWARE("radeon/bonaire_me.bin"); 59 MODULE_FIRMWARE("radeon/bonaire_ce.bin"); 60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); 61 MODULE_FIRMWARE("radeon/bonaire_mec.bin"); 62 63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); 64 MODULE_FIRMWARE("radeon/hawaii_me.bin"); 65 MODULE_FIRMWARE("radeon/hawaii_ce.bin"); 66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); 67 MODULE_FIRMWARE("radeon/hawaii_mec.bin"); 68 69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); 70 MODULE_FIRMWARE("radeon/kaveri_me.bin"); 71 MODULE_FIRMWARE("radeon/kaveri_ce.bin"); 72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); 73 MODULE_FIRMWARE("radeon/kaveri_mec.bin"); 74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); 75 76 MODULE_FIRMWARE("radeon/kabini_pfp.bin"); 77 MODULE_FIRMWARE("radeon/kabini_me.bin"); 78 MODULE_FIRMWARE("radeon/kabini_ce.bin"); 79 MODULE_FIRMWARE("radeon/kabini_rlc.bin"); 80 MODULE_FIRMWARE("radeon/kabini_mec.bin"); 81 82 MODULE_FIRMWARE("radeon/mullins_pfp.bin"); 83 MODULE_FIRMWARE("radeon/mullins_me.bin"); 84 MODULE_FIRMWARE("radeon/mullins_ce.bin"); 85 MODULE_FIRMWARE("radeon/mullins_rlc.bin"); 86 MODULE_FIRMWARE("radeon/mullins_mec.bin"); 87 88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 89 { 90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 106 }; 107 108 static const u32 spectre_rlc_save_restore_register_list[] = 109 { 110 (0x0e00 << 16) | (0xc12c >> 2), 111 0x00000000, 112 (0x0e00 << 16) | (0xc140 >> 2), 113 0x00000000, 114 (0x0e00 << 16) | (0xc150 >> 2), 115 0x00000000, 116 (0x0e00 << 16) | (0xc15c >> 2), 117 0x00000000, 118 (0x0e00 << 16) | (0xc168 >> 2), 119 0x00000000, 120 (0x0e00 << 16) | (0xc170 >> 2), 121 0x00000000, 122 (0x0e00 << 16) | (0xc178 >> 2), 123 0x00000000, 124 (0x0e00 << 16) | (0xc204 >> 2), 125 0x00000000, 126 (0x0e00 << 16) | (0xc2b4 >> 2), 127 0x00000000, 128 (0x0e00 << 16) | (0xc2b8 >> 2), 129 0x00000000, 130 (0x0e00 << 16) | (0xc2bc >> 2), 131 0x00000000, 132 (0x0e00 << 16) | (0xc2c0 >> 2), 133 0x00000000, 134 (0x0e00 << 16) | (0x8228 >> 2), 135 0x00000000, 136 (0x0e00 << 16) | (0x829c >> 2), 137 0x00000000, 138 (0x0e00 << 16) | (0x869c >> 2), 139 0x00000000, 140 (0x0600 << 16) | (0x98f4 >> 2), 141 0x00000000, 142 (0x0e00 << 16) | (0x98f8 >> 2), 143 0x00000000, 144 (0x0e00 << 16) | (0x9900 >> 2), 145 0x00000000, 146 (0x0e00 << 16) | (0xc260 >> 2), 147 0x00000000, 148 (0x0e00 << 16) | (0x90e8 >> 2), 149 0x00000000, 150 (0x0e00 << 16) | (0x3c000 >> 2), 151 0x00000000, 152 (0x0e00 << 16) | (0x3c00c >> 2), 153 0x00000000, 154 (0x0e00 << 16) | (0x8c1c >> 2), 155 0x00000000, 156 (0x0e00 << 16) | (0x9700 >> 2), 157 0x00000000, 158 (0x0e00 << 16) | (0xcd20 >> 2), 159 0x00000000, 160 (0x4e00 << 16) | (0xcd20 >> 2), 161 0x00000000, 162 (0x5e00 << 16) | (0xcd20 >> 2), 163 0x00000000, 164 (0x6e00 << 16) | (0xcd20 >> 2), 165 0x00000000, 166 (0x7e00 << 16) | (0xcd20 >> 2), 167 0x00000000, 168 (0x8e00 << 16) | (0xcd20 >> 2), 169 0x00000000, 170 (0x9e00 << 16) | (0xcd20 >> 2), 171 0x00000000, 172 (0xae00 << 16) | (0xcd20 >> 2), 173 0x00000000, 174 (0xbe00 << 16) | (0xcd20 >> 2), 175 0x00000000, 176 (0x0e00 << 16) | (0x89bc >> 2), 177 0x00000000, 178 (0x0e00 << 16) | (0x8900 >> 2), 179 0x00000000, 180 0x3, 181 (0x0e00 << 16) | (0xc130 >> 2), 182 0x00000000, 183 (0x0e00 << 16) | (0xc134 >> 2), 184 0x00000000, 185 (0x0e00 << 16) | (0xc1fc >> 2), 186 0x00000000, 187 (0x0e00 << 16) | (0xc208 >> 2), 188 0x00000000, 189 (0x0e00 << 16) | (0xc264 >> 2), 190 0x00000000, 191 (0x0e00 << 16) | (0xc268 >> 2), 192 0x00000000, 193 (0x0e00 << 16) | (0xc26c >> 2), 194 0x00000000, 195 (0x0e00 << 16) | (0xc270 >> 2), 196 0x00000000, 197 (0x0e00 << 16) | (0xc274 >> 2), 198 0x00000000, 199 (0x0e00 << 16) | (0xc278 >> 2), 200 0x00000000, 201 (0x0e00 << 16) | (0xc27c >> 2), 202 0x00000000, 203 (0x0e00 << 16) | (0xc280 >> 2), 204 0x00000000, 205 (0x0e00 << 16) | (0xc284 >> 2), 206 0x00000000, 207 (0x0e00 << 16) | (0xc288 >> 2), 208 0x00000000, 209 (0x0e00 << 16) | (0xc28c >> 2), 210 0x00000000, 211 (0x0e00 << 16) | (0xc290 >> 2), 212 0x00000000, 213 (0x0e00 << 16) | (0xc294 >> 2), 214 0x00000000, 215 (0x0e00 << 16) | (0xc298 >> 2), 216 0x00000000, 217 (0x0e00 << 16) | (0xc29c >> 2), 218 0x00000000, 219 (0x0e00 << 16) | (0xc2a0 >> 2), 220 0x00000000, 221 (0x0e00 << 16) | (0xc2a4 >> 2), 222 0x00000000, 223 (0x0e00 << 16) | (0xc2a8 >> 2), 224 0x00000000, 225 (0x0e00 << 16) | (0xc2ac >> 2), 226 0x00000000, 227 (0x0e00 << 16) | (0xc2b0 >> 2), 228 0x00000000, 229 (0x0e00 << 16) | (0x301d0 >> 2), 230 0x00000000, 231 (0x0e00 << 16) | (0x30238 >> 2), 232 0x00000000, 233 (0x0e00 << 16) | (0x30250 >> 2), 234 0x00000000, 235 (0x0e00 << 16) | (0x30254 >> 2), 236 0x00000000, 237 (0x0e00 << 16) | (0x30258 >> 2), 238 0x00000000, 239 (0x0e00 << 16) | (0x3025c >> 2), 240 0x00000000, 241 (0x4e00 << 16) | (0xc900 >> 2), 242 0x00000000, 243 (0x5e00 << 16) | (0xc900 >> 2), 244 0x00000000, 245 (0x6e00 << 16) | (0xc900 >> 2), 246 0x00000000, 247 (0x7e00 << 16) | (0xc900 >> 2), 248 0x00000000, 249 (0x8e00 << 16) | (0xc900 >> 2), 250 0x00000000, 251 (0x9e00 << 16) | (0xc900 >> 2), 252 0x00000000, 253 (0xae00 << 16) | (0xc900 >> 2), 254 0x00000000, 255 (0xbe00 << 16) | (0xc900 >> 2), 256 0x00000000, 257 (0x4e00 << 16) | (0xc904 >> 2), 258 0x00000000, 259 (0x5e00 << 16) | (0xc904 >> 2), 260 0x00000000, 261 (0x6e00 << 16) | (0xc904 >> 2), 262 0x00000000, 263 (0x7e00 << 16) | (0xc904 >> 2), 264 0x00000000, 265 (0x8e00 << 16) | (0xc904 >> 2), 266 0x00000000, 267 (0x9e00 << 16) | (0xc904 >> 2), 268 0x00000000, 269 (0xae00 << 16) | (0xc904 >> 2), 270 0x00000000, 271 (0xbe00 << 16) | (0xc904 >> 2), 272 0x00000000, 273 (0x4e00 << 16) | (0xc908 >> 2), 274 0x00000000, 275 (0x5e00 << 16) | (0xc908 >> 2), 276 0x00000000, 277 (0x6e00 << 16) | (0xc908 >> 2), 278 0x00000000, 279 (0x7e00 << 16) | (0xc908 >> 2), 280 0x00000000, 281 (0x8e00 << 16) | (0xc908 >> 2), 282 0x00000000, 283 (0x9e00 << 16) | (0xc908 >> 2), 284 0x00000000, 285 (0xae00 << 16) | (0xc908 >> 2), 286 0x00000000, 287 (0xbe00 << 16) | (0xc908 >> 2), 288 0x00000000, 289 (0x4e00 << 16) | (0xc90c >> 2), 290 0x00000000, 291 (0x5e00 << 16) | (0xc90c >> 2), 292 0x00000000, 293 (0x6e00 << 16) | (0xc90c >> 2), 294 0x00000000, 295 (0x7e00 << 16) | (0xc90c >> 2), 296 0x00000000, 297 (0x8e00 << 16) | (0xc90c >> 2), 298 0x00000000, 299 (0x9e00 << 16) | (0xc90c >> 2), 300 0x00000000, 301 (0xae00 << 16) | (0xc90c >> 2), 302 0x00000000, 303 (0xbe00 << 16) | (0xc90c >> 2), 304 0x00000000, 305 (0x4e00 << 16) | (0xc910 >> 2), 306 0x00000000, 307 (0x5e00 << 16) | (0xc910 >> 2), 308 0x00000000, 309 (0x6e00 << 16) | (0xc910 >> 2), 310 0x00000000, 311 (0x7e00 << 16) | (0xc910 >> 2), 312 0x00000000, 313 (0x8e00 << 16) | (0xc910 >> 2), 314 0x00000000, 315 (0x9e00 << 16) | (0xc910 >> 2), 316 0x00000000, 317 (0xae00 << 16) | (0xc910 >> 2), 318 0x00000000, 319 (0xbe00 << 16) | (0xc910 >> 2), 320 0x00000000, 321 (0x0e00 << 16) | (0xc99c >> 2), 322 0x00000000, 323 (0x0e00 << 16) | (0x9834 >> 2), 324 0x00000000, 325 (0x0000 << 16) | (0x30f00 >> 2), 326 0x00000000, 327 (0x0001 << 16) | (0x30f00 >> 2), 328 0x00000000, 329 (0x0000 << 16) | (0x30f04 >> 2), 330 0x00000000, 331 (0x0001 << 16) | (0x30f04 >> 2), 332 0x00000000, 333 (0x0000 << 16) | (0x30f08 >> 2), 334 0x00000000, 335 (0x0001 << 16) | (0x30f08 >> 2), 336 0x00000000, 337 (0x0000 << 16) | (0x30f0c >> 2), 338 0x00000000, 339 (0x0001 << 16) | (0x30f0c >> 2), 340 0x00000000, 341 (0x0600 << 16) | (0x9b7c >> 2), 342 0x00000000, 343 (0x0e00 << 16) | (0x8a14 >> 2), 344 0x00000000, 345 (0x0e00 << 16) | (0x8a18 >> 2), 346 0x00000000, 347 (0x0600 << 16) | (0x30a00 >> 2), 348 0x00000000, 349 (0x0e00 << 16) | (0x8bf0 >> 2), 350 0x00000000, 351 (0x0e00 << 16) | (0x8bcc >> 2), 352 0x00000000, 353 (0x0e00 << 16) | (0x8b24 >> 2), 354 0x00000000, 355 (0x0e00 << 16) | (0x30a04 >> 2), 356 0x00000000, 357 (0x0600 << 16) | (0x30a10 >> 2), 358 0x00000000, 359 (0x0600 << 16) | (0x30a14 >> 2), 360 0x00000000, 361 (0x0600 << 16) | (0x30a18 >> 2), 362 0x00000000, 363 (0x0600 << 16) | (0x30a2c >> 2), 364 0x00000000, 365 (0x0e00 << 16) | (0xc700 >> 2), 366 0x00000000, 367 (0x0e00 << 16) | (0xc704 >> 2), 368 0x00000000, 369 (0x0e00 << 16) | (0xc708 >> 2), 370 0x00000000, 371 (0x0e00 << 16) | (0xc768 >> 2), 372 0x00000000, 373 (0x0400 << 16) | (0xc770 >> 2), 374 0x00000000, 375 (0x0400 << 16) | (0xc774 >> 2), 376 0x00000000, 377 (0x0400 << 16) | (0xc778 >> 2), 378 0x00000000, 379 (0x0400 << 16) | (0xc77c >> 2), 380 0x00000000, 381 (0x0400 << 16) | (0xc780 >> 2), 382 0x00000000, 383 (0x0400 << 16) | (0xc784 >> 2), 384 0x00000000, 385 (0x0400 << 16) | (0xc788 >> 2), 386 0x00000000, 387 (0x0400 << 16) | (0xc78c >> 2), 388 0x00000000, 389 (0x0400 << 16) | (0xc798 >> 2), 390 0x00000000, 391 (0x0400 << 16) | (0xc79c >> 2), 392 0x00000000, 393 (0x0400 << 16) | (0xc7a0 >> 2), 394 0x00000000, 395 (0x0400 << 16) | (0xc7a4 >> 2), 396 0x00000000, 397 (0x0400 << 16) | (0xc7a8 >> 2), 398 0x00000000, 399 (0x0400 << 16) | (0xc7ac >> 2), 400 0x00000000, 401 (0x0400 << 16) | (0xc7b0 >> 2), 402 0x00000000, 403 (0x0400 << 16) | (0xc7b4 >> 2), 404 0x00000000, 405 (0x0e00 << 16) | (0x9100 >> 2), 406 0x00000000, 407 (0x0e00 << 16) | (0x3c010 >> 2), 408 0x00000000, 409 (0x0e00 << 16) | (0x92a8 >> 2), 410 0x00000000, 411 (0x0e00 << 16) | (0x92ac >> 2), 412 0x00000000, 413 (0x0e00 << 16) | (0x92b4 >> 2), 414 0x00000000, 415 (0x0e00 << 16) | (0x92b8 >> 2), 416 0x00000000, 417 (0x0e00 << 16) | (0x92bc >> 2), 418 0x00000000, 419 (0x0e00 << 16) | (0x92c0 >> 2), 420 0x00000000, 421 (0x0e00 << 16) | (0x92c4 >> 2), 422 0x00000000, 423 (0x0e00 << 16) | (0x92c8 >> 2), 424 0x00000000, 425 (0x0e00 << 16) | (0x92cc >> 2), 426 0x00000000, 427 (0x0e00 << 16) | (0x92d0 >> 2), 428 0x00000000, 429 (0x0e00 << 16) | (0x8c00 >> 2), 430 0x00000000, 431 (0x0e00 << 16) | (0x8c04 >> 2), 432 0x00000000, 433 (0x0e00 << 16) | (0x8c20 >> 2), 434 0x00000000, 435 (0x0e00 << 16) | (0x8c38 >> 2), 436 0x00000000, 437 (0x0e00 << 16) | (0x8c3c >> 2), 438 0x00000000, 439 (0x0e00 << 16) | (0xae00 >> 2), 440 0x00000000, 441 (0x0e00 << 16) | (0x9604 >> 2), 442 0x00000000, 443 (0x0e00 << 16) | (0xac08 >> 2), 444 0x00000000, 445 (0x0e00 << 16) | (0xac0c >> 2), 446 0x00000000, 447 (0x0e00 << 16) | (0xac10 >> 2), 448 0x00000000, 449 (0x0e00 << 16) | (0xac14 >> 2), 450 0x00000000, 451 (0x0e00 << 16) | (0xac58 >> 2), 452 0x00000000, 453 (0x0e00 << 16) | (0xac68 >> 2), 454 0x00000000, 455 (0x0e00 << 16) | (0xac6c >> 2), 456 0x00000000, 457 (0x0e00 << 16) | (0xac70 >> 2), 458 0x00000000, 459 (0x0e00 << 16) | (0xac74 >> 2), 460 0x00000000, 461 (0x0e00 << 16) | (0xac78 >> 2), 462 0x00000000, 463 (0x0e00 << 16) | (0xac7c >> 2), 464 0x00000000, 465 (0x0e00 << 16) | (0xac80 >> 2), 466 0x00000000, 467 (0x0e00 << 16) | (0xac84 >> 2), 468 0x00000000, 469 (0x0e00 << 16) | (0xac88 >> 2), 470 0x00000000, 471 (0x0e00 << 16) | (0xac8c >> 2), 472 0x00000000, 473 (0x0e00 << 16) | (0x970c >> 2), 474 0x00000000, 475 (0x0e00 << 16) | (0x9714 >> 2), 476 0x00000000, 477 (0x0e00 << 16) | (0x9718 >> 2), 478 0x00000000, 479 (0x0e00 << 16) | (0x971c >> 2), 480 0x00000000, 481 (0x0e00 << 16) | (0x31068 >> 2), 482 0x00000000, 483 (0x4e00 << 16) | (0x31068 >> 2), 484 0x00000000, 485 (0x5e00 << 16) | (0x31068 >> 2), 486 0x00000000, 487 (0x6e00 << 16) | (0x31068 >> 2), 488 0x00000000, 489 (0x7e00 << 16) | (0x31068 >> 2), 490 0x00000000, 491 (0x8e00 << 16) | (0x31068 >> 2), 492 0x00000000, 493 (0x9e00 << 16) | (0x31068 >> 2), 494 0x00000000, 495 (0xae00 << 16) | (0x31068 >> 2), 496 0x00000000, 497 (0xbe00 << 16) | (0x31068 >> 2), 498 0x00000000, 499 (0x0e00 << 16) | (0xcd10 >> 2), 500 0x00000000, 501 (0x0e00 << 16) | (0xcd14 >> 2), 502 0x00000000, 503 (0x0e00 << 16) | (0x88b0 >> 2), 504 0x00000000, 505 (0x0e00 << 16) | (0x88b4 >> 2), 506 0x00000000, 507 (0x0e00 << 16) | (0x88b8 >> 2), 508 0x00000000, 509 (0x0e00 << 16) | (0x88bc >> 2), 510 0x00000000, 511 (0x0400 << 16) | (0x89c0 >> 2), 512 0x00000000, 513 (0x0e00 << 16) | (0x88c4 >> 2), 514 0x00000000, 515 (0x0e00 << 16) | (0x88c8 >> 2), 516 0x00000000, 517 (0x0e00 << 16) | (0x88d0 >> 2), 518 0x00000000, 519 (0x0e00 << 16) | (0x88d4 >> 2), 520 0x00000000, 521 (0x0e00 << 16) | (0x88d8 >> 2), 522 0x00000000, 523 (0x0e00 << 16) | (0x8980 >> 2), 524 0x00000000, 525 (0x0e00 << 16) | (0x30938 >> 2), 526 0x00000000, 527 (0x0e00 << 16) | (0x3093c >> 2), 528 0x00000000, 529 (0x0e00 << 16) | (0x30940 >> 2), 530 0x00000000, 531 (0x0e00 << 16) | (0x89a0 >> 2), 532 0x00000000, 533 (0x0e00 << 16) | (0x30900 >> 2), 534 0x00000000, 535 (0x0e00 << 16) | (0x30904 >> 2), 536 0x00000000, 537 (0x0e00 << 16) | (0x89b4 >> 2), 538 0x00000000, 539 (0x0e00 << 16) | (0x3c210 >> 2), 540 0x00000000, 541 (0x0e00 << 16) | (0x3c214 >> 2), 542 0x00000000, 543 (0x0e00 << 16) | (0x3c218 >> 2), 544 0x00000000, 545 (0x0e00 << 16) | (0x8904 >> 2), 546 0x00000000, 547 0x5, 548 (0x0e00 << 16) | (0x8c28 >> 2), 549 (0x0e00 << 16) | (0x8c2c >> 2), 550 (0x0e00 << 16) | (0x8c30 >> 2), 551 (0x0e00 << 16) | (0x8c34 >> 2), 552 (0x0e00 << 16) | (0x9600 >> 2), 553 }; 554 555 static const u32 kalindi_rlc_save_restore_register_list[] = 556 { 557 (0x0e00 << 16) | (0xc12c >> 2), 558 0x00000000, 559 (0x0e00 << 16) | (0xc140 >> 2), 560 0x00000000, 561 (0x0e00 << 16) | (0xc150 >> 2), 562 0x00000000, 563 (0x0e00 << 16) | (0xc15c >> 2), 564 0x00000000, 565 (0x0e00 << 16) | (0xc168 >> 2), 566 0x00000000, 567 (0x0e00 << 16) | (0xc170 >> 2), 568 0x00000000, 569 (0x0e00 << 16) | (0xc204 >> 2), 570 0x00000000, 571 (0x0e00 << 16) | (0xc2b4 >> 2), 572 0x00000000, 573 (0x0e00 << 16) | (0xc2b8 >> 2), 574 0x00000000, 575 (0x0e00 << 16) | (0xc2bc >> 2), 576 0x00000000, 577 (0x0e00 << 16) | (0xc2c0 >> 2), 578 0x00000000, 579 (0x0e00 << 16) | (0x8228 >> 2), 580 0x00000000, 581 (0x0e00 << 16) | (0x829c >> 2), 582 0x00000000, 583 (0x0e00 << 16) | (0x869c >> 2), 584 0x00000000, 585 (0x0600 << 16) | (0x98f4 >> 2), 586 0x00000000, 587 (0x0e00 << 16) | (0x98f8 >> 2), 588 0x00000000, 589 (0x0e00 << 16) | (0x9900 >> 2), 590 0x00000000, 591 (0x0e00 << 16) | (0xc260 >> 2), 592 0x00000000, 593 (0x0e00 << 16) | (0x90e8 >> 2), 594 0x00000000, 595 (0x0e00 << 16) | (0x3c000 >> 2), 596 0x00000000, 597 (0x0e00 << 16) | (0x3c00c >> 2), 598 0x00000000, 599 (0x0e00 << 16) | (0x8c1c >> 2), 600 0x00000000, 601 (0x0e00 << 16) | (0x9700 >> 2), 602 0x00000000, 603 (0x0e00 << 16) | (0xcd20 >> 2), 604 0x00000000, 605 (0x4e00 << 16) | (0xcd20 >> 2), 606 0x00000000, 607 (0x5e00 << 16) | (0xcd20 >> 2), 608 0x00000000, 609 (0x6e00 << 16) | (0xcd20 >> 2), 610 0x00000000, 611 (0x7e00 << 16) | (0xcd20 >> 2), 612 0x00000000, 613 (0x0e00 << 16) | (0x89bc >> 2), 614 0x00000000, 615 (0x0e00 << 16) | (0x8900 >> 2), 616 0x00000000, 617 0x3, 618 (0x0e00 << 16) | (0xc130 >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0xc134 >> 2), 621 0x00000000, 622 (0x0e00 << 16) | (0xc1fc >> 2), 623 0x00000000, 624 (0x0e00 << 16) | (0xc208 >> 2), 625 0x00000000, 626 (0x0e00 << 16) | (0xc264 >> 2), 627 0x00000000, 628 (0x0e00 << 16) | (0xc268 >> 2), 629 0x00000000, 630 (0x0e00 << 16) | (0xc26c >> 2), 631 0x00000000, 632 (0x0e00 << 16) | (0xc270 >> 2), 633 0x00000000, 634 (0x0e00 << 16) | (0xc274 >> 2), 635 0x00000000, 636 (0x0e00 << 16) | (0xc28c >> 2), 637 0x00000000, 638 (0x0e00 << 16) | (0xc290 >> 2), 639 0x00000000, 640 (0x0e00 << 16) | (0xc294 >> 2), 641 0x00000000, 642 (0x0e00 << 16) | (0xc298 >> 2), 643 0x00000000, 644 (0x0e00 << 16) | (0xc2a0 >> 2), 645 0x00000000, 646 (0x0e00 << 16) | (0xc2a4 >> 2), 647 0x00000000, 648 (0x0e00 << 16) | (0xc2a8 >> 2), 649 0x00000000, 650 (0x0e00 << 16) | (0xc2ac >> 2), 651 0x00000000, 652 (0x0e00 << 16) | (0x301d0 >> 2), 653 0x00000000, 654 (0x0e00 << 16) | (0x30238 >> 2), 655 0x00000000, 656 (0x0e00 << 16) | (0x30250 >> 2), 657 0x00000000, 658 (0x0e00 << 16) | (0x30254 >> 2), 659 0x00000000, 660 (0x0e00 << 16) | (0x30258 >> 2), 661 0x00000000, 662 (0x0e00 << 16) | (0x3025c >> 2), 663 0x00000000, 664 (0x4e00 << 16) | (0xc900 >> 2), 665 0x00000000, 666 (0x5e00 << 16) | (0xc900 >> 2), 667 0x00000000, 668 (0x6e00 << 16) | (0xc900 >> 2), 669 0x00000000, 670 (0x7e00 << 16) | (0xc900 >> 2), 671 0x00000000, 672 (0x4e00 << 16) | (0xc904 >> 2), 673 0x00000000, 674 (0x5e00 << 16) | (0xc904 >> 2), 675 0x00000000, 676 (0x6e00 << 16) | (0xc904 >> 2), 677 0x00000000, 678 (0x7e00 << 16) | (0xc904 >> 2), 679 0x00000000, 680 (0x4e00 << 16) | (0xc908 >> 2), 681 0x00000000, 682 (0x5e00 << 16) | (0xc908 >> 2), 683 0x00000000, 684 (0x6e00 << 16) | (0xc908 >> 2), 685 0x00000000, 686 (0x7e00 << 16) | (0xc908 >> 2), 687 0x00000000, 688 (0x4e00 << 16) | (0xc90c >> 2), 689 0x00000000, 690 (0x5e00 << 16) | (0xc90c >> 2), 691 0x00000000, 692 (0x6e00 << 16) | (0xc90c >> 2), 693 0x00000000, 694 (0x7e00 << 16) | (0xc90c >> 2), 695 0x00000000, 696 (0x4e00 << 16) | (0xc910 >> 2), 697 0x00000000, 698 (0x5e00 << 16) | (0xc910 >> 2), 699 0x00000000, 700 (0x6e00 << 16) | (0xc910 >> 2), 701 0x00000000, 702 (0x7e00 << 16) | (0xc910 >> 2), 703 0x00000000, 704 (0x0e00 << 16) | (0xc99c >> 2), 705 0x00000000, 706 (0x0e00 << 16) | (0x9834 >> 2), 707 0x00000000, 708 (0x0000 << 16) | (0x30f00 >> 2), 709 0x00000000, 710 (0x0000 << 16) | (0x30f04 >> 2), 711 0x00000000, 712 (0x0000 << 16) | (0x30f08 >> 2), 713 0x00000000, 714 (0x0000 << 16) | (0x30f0c >> 2), 715 0x00000000, 716 (0x0600 << 16) | (0x9b7c >> 2), 717 0x00000000, 718 (0x0e00 << 16) | (0x8a14 >> 2), 719 0x00000000, 720 (0x0e00 << 16) | (0x8a18 >> 2), 721 0x00000000, 722 (0x0600 << 16) | (0x30a00 >> 2), 723 0x00000000, 724 (0x0e00 << 16) | (0x8bf0 >> 2), 725 0x00000000, 726 (0x0e00 << 16) | (0x8bcc >> 2), 727 0x00000000, 728 (0x0e00 << 16) | (0x8b24 >> 2), 729 0x00000000, 730 (0x0e00 << 16) | (0x30a04 >> 2), 731 0x00000000, 732 (0x0600 << 16) | (0x30a10 >> 2), 733 0x00000000, 734 (0x0600 << 16) | (0x30a14 >> 2), 735 0x00000000, 736 (0x0600 << 16) | (0x30a18 >> 2), 737 0x00000000, 738 (0x0600 << 16) | (0x30a2c >> 2), 739 0x00000000, 740 (0x0e00 << 16) | (0xc700 >> 2), 741 0x00000000, 742 (0x0e00 << 16) | (0xc704 >> 2), 743 0x00000000, 744 (0x0e00 << 16) | (0xc708 >> 2), 745 0x00000000, 746 (0x0e00 << 16) | (0xc768 >> 2), 747 0x00000000, 748 (0x0400 << 16) | (0xc770 >> 2), 749 0x00000000, 750 (0x0400 << 16) | (0xc774 >> 2), 751 0x00000000, 752 (0x0400 << 16) | (0xc798 >> 2), 753 0x00000000, 754 (0x0400 << 16) | (0xc79c >> 2), 755 0x00000000, 756 (0x0e00 << 16) | (0x9100 >> 2), 757 0x00000000, 758 (0x0e00 << 16) | (0x3c010 >> 2), 759 0x00000000, 760 (0x0e00 << 16) | (0x8c00 >> 2), 761 0x00000000, 762 (0x0e00 << 16) | (0x8c04 >> 2), 763 0x00000000, 764 (0x0e00 << 16) | (0x8c20 >> 2), 765 0x00000000, 766 (0x0e00 << 16) | (0x8c38 >> 2), 767 0x00000000, 768 (0x0e00 << 16) | (0x8c3c >> 2), 769 0x00000000, 770 (0x0e00 << 16) | (0xae00 >> 2), 771 0x00000000, 772 (0x0e00 << 16) | (0x9604 >> 2), 773 0x00000000, 774 (0x0e00 << 16) | (0xac08 >> 2), 775 0x00000000, 776 (0x0e00 << 16) | (0xac0c >> 2), 777 0x00000000, 778 (0x0e00 << 16) | (0xac10 >> 2), 779 0x00000000, 780 (0x0e00 << 16) | (0xac14 >> 2), 781 0x00000000, 782 (0x0e00 << 16) | (0xac58 >> 2), 783 0x00000000, 784 (0x0e00 << 16) | (0xac68 >> 2), 785 0x00000000, 786 (0x0e00 << 16) | (0xac6c >> 2), 787 0x00000000, 788 (0x0e00 << 16) | (0xac70 >> 2), 789 0x00000000, 790 (0x0e00 << 16) | (0xac74 >> 2), 791 0x00000000, 792 (0x0e00 << 16) | (0xac78 >> 2), 793 0x00000000, 794 (0x0e00 << 16) | (0xac7c >> 2), 795 0x00000000, 796 (0x0e00 << 16) | (0xac80 >> 2), 797 0x00000000, 798 (0x0e00 << 16) | (0xac84 >> 2), 799 0x00000000, 800 (0x0e00 << 16) | (0xac88 >> 2), 801 0x00000000, 802 (0x0e00 << 16) | (0xac8c >> 2), 803 0x00000000, 804 (0x0e00 << 16) | (0x970c >> 2), 805 0x00000000, 806 (0x0e00 << 16) | (0x9714 >> 2), 807 0x00000000, 808 (0x0e00 << 16) | (0x9718 >> 2), 809 0x00000000, 810 (0x0e00 << 16) | (0x971c >> 2), 811 0x00000000, 812 (0x0e00 << 16) | (0x31068 >> 2), 813 0x00000000, 814 (0x4e00 << 16) | (0x31068 >> 2), 815 0x00000000, 816 (0x5e00 << 16) | (0x31068 >> 2), 817 0x00000000, 818 (0x6e00 << 16) | (0x31068 >> 2), 819 0x00000000, 820 (0x7e00 << 16) | (0x31068 >> 2), 821 0x00000000, 822 (0x0e00 << 16) | (0xcd10 >> 2), 823 0x00000000, 824 (0x0e00 << 16) | (0xcd14 >> 2), 825 0x00000000, 826 (0x0e00 << 16) | (0x88b0 >> 2), 827 0x00000000, 828 (0x0e00 << 16) | (0x88b4 >> 2), 829 0x00000000, 830 (0x0e00 << 16) | (0x88b8 >> 2), 831 0x00000000, 832 (0x0e00 << 16) | (0x88bc >> 2), 833 0x00000000, 834 (0x0400 << 16) | (0x89c0 >> 2), 835 0x00000000, 836 (0x0e00 << 16) | (0x88c4 >> 2), 837 0x00000000, 838 (0x0e00 << 16) | (0x88c8 >> 2), 839 0x00000000, 840 (0x0e00 << 16) | (0x88d0 >> 2), 841 0x00000000, 842 (0x0e00 << 16) | (0x88d4 >> 2), 843 0x00000000, 844 (0x0e00 << 16) | (0x88d8 >> 2), 845 0x00000000, 846 (0x0e00 << 16) | (0x8980 >> 2), 847 0x00000000, 848 (0x0e00 << 16) | (0x30938 >> 2), 849 0x00000000, 850 (0x0e00 << 16) | (0x3093c >> 2), 851 0x00000000, 852 (0x0e00 << 16) | (0x30940 >> 2), 853 0x00000000, 854 (0x0e00 << 16) | (0x89a0 >> 2), 855 0x00000000, 856 (0x0e00 << 16) | (0x30900 >> 2), 857 0x00000000, 858 (0x0e00 << 16) | (0x30904 >> 2), 859 0x00000000, 860 (0x0e00 << 16) | (0x89b4 >> 2), 861 0x00000000, 862 (0x0e00 << 16) | (0x3e1fc >> 2), 863 0x00000000, 864 (0x0e00 << 16) | (0x3c210 >> 2), 865 0x00000000, 866 (0x0e00 << 16) | (0x3c214 >> 2), 867 0x00000000, 868 (0x0e00 << 16) | (0x3c218 >> 2), 869 0x00000000, 870 (0x0e00 << 16) | (0x8904 >> 2), 871 0x00000000, 872 0x5, 873 (0x0e00 << 16) | (0x8c28 >> 2), 874 (0x0e00 << 16) | (0x8c2c >> 2), 875 (0x0e00 << 16) | (0x8c30 >> 2), 876 (0x0e00 << 16) | (0x8c34 >> 2), 877 (0x0e00 << 16) | (0x9600 >> 2), 878 }; 879 880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); 883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 885 886 /* 887 * Core functions 888 */ 889 /** 890 * gfx_v7_0_init_microcode - load ucode images from disk 891 * 892 * @adev: amdgpu_device pointer 893 * 894 * Use the firmware interface to load the ucode images into 895 * the driver (not loaded into hw). 896 * Returns 0 on success, error on failure. 897 */ 898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 899 { 900 const char *chip_name; 901 char fw_name[30]; 902 int err; 903 904 DRM_DEBUG("\n"); 905 906 switch (adev->asic_type) { 907 case CHIP_BONAIRE: 908 chip_name = "bonaire"; 909 break; 910 case CHIP_HAWAII: 911 chip_name = "hawaii"; 912 break; 913 case CHIP_KAVERI: 914 chip_name = "kaveri"; 915 break; 916 case CHIP_KABINI: 917 chip_name = "kabini"; 918 break; 919 case CHIP_MULLINS: 920 chip_name = "mullins"; 921 break; 922 default: BUG(); 923 } 924 925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 927 if (err) 928 goto out; 929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 930 if (err) 931 goto out; 932 933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 935 if (err) 936 goto out; 937 err = amdgpu_ucode_validate(adev->gfx.me_fw); 938 if (err) 939 goto out; 940 941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 943 if (err) 944 goto out; 945 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 946 if (err) 947 goto out; 948 949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); 950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 951 if (err) 952 goto out; 953 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 954 if (err) 955 goto out; 956 957 if (adev->asic_type == CHIP_KAVERI) { 958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); 959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 960 if (err) 961 goto out; 962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 963 if (err) 964 goto out; 965 } 966 967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 969 if (err) 970 goto out; 971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 972 973 out: 974 if (err) { 975 printk(KERN_ERR 976 "gfx7: Failed to load firmware \"%s\"\n", 977 fw_name); 978 release_firmware(adev->gfx.pfp_fw); 979 adev->gfx.pfp_fw = NULL; 980 release_firmware(adev->gfx.me_fw); 981 adev->gfx.me_fw = NULL; 982 release_firmware(adev->gfx.ce_fw); 983 adev->gfx.ce_fw = NULL; 984 release_firmware(adev->gfx.mec_fw); 985 adev->gfx.mec_fw = NULL; 986 release_firmware(adev->gfx.mec2_fw); 987 adev->gfx.mec2_fw = NULL; 988 release_firmware(adev->gfx.rlc_fw); 989 adev->gfx.rlc_fw = NULL; 990 } 991 return err; 992 } 993 994 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 995 { 996 release_firmware(adev->gfx.pfp_fw); 997 adev->gfx.pfp_fw = NULL; 998 release_firmware(adev->gfx.me_fw); 999 adev->gfx.me_fw = NULL; 1000 release_firmware(adev->gfx.ce_fw); 1001 adev->gfx.ce_fw = NULL; 1002 release_firmware(adev->gfx.mec_fw); 1003 adev->gfx.mec_fw = NULL; 1004 release_firmware(adev->gfx.mec2_fw); 1005 adev->gfx.mec2_fw = NULL; 1006 release_firmware(adev->gfx.rlc_fw); 1007 adev->gfx.rlc_fw = NULL; 1008 } 1009 1010 /** 1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1012 * 1013 * @adev: amdgpu_device pointer 1014 * 1015 * Starting with SI, the tiling setup is done globally in a 1016 * set of 32 tiling modes. Rather than selecting each set of 1017 * parameters per surface as on older asics, we just select 1018 * which index in the tiling table we want to use, and the 1019 * surface uses those parameters (CIK). 1020 */ 1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1022 { 1023 const u32 num_tile_mode_states = 1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1025 const u32 num_secondary_tile_mode_states = 1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1027 u32 reg_offset, split_equal_to_row_size; 1028 uint32_t *tile, *macrotile; 1029 1030 tile = adev->gfx.config.tile_mode_array; 1031 macrotile = adev->gfx.config.macrotile_mode_array; 1032 1033 switch (adev->gfx.config.mem_row_size_in_kb) { 1034 case 1: 1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1036 break; 1037 case 2: 1038 default: 1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1040 break; 1041 case 4: 1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1043 break; 1044 } 1045 1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1047 tile[reg_offset] = 0; 1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1049 macrotile[reg_offset] = 0; 1050 1051 switch (adev->asic_type) { 1052 case CHIP_BONAIRE: 1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1072 TILE_SPLIT(split_equal_to_row_size)); 1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1079 TILE_SPLIT(split_equal_to_row_size)); 1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1082 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1155 1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1159 NUM_BANKS(ADDR_SURF_16_BANK)); 1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1163 NUM_BANKS(ADDR_SURF_16_BANK)); 1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1167 NUM_BANKS(ADDR_SURF_16_BANK)); 1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1171 NUM_BANKS(ADDR_SURF_16_BANK)); 1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1175 NUM_BANKS(ADDR_SURF_16_BANK)); 1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1179 NUM_BANKS(ADDR_SURF_8_BANK)); 1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1183 NUM_BANKS(ADDR_SURF_4_BANK)); 1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1187 NUM_BANKS(ADDR_SURF_16_BANK)); 1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1191 NUM_BANKS(ADDR_SURF_16_BANK)); 1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1195 NUM_BANKS(ADDR_SURF_16_BANK)); 1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1199 NUM_BANKS(ADDR_SURF_16_BANK)); 1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1203 NUM_BANKS(ADDR_SURF_16_BANK)); 1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1207 NUM_BANKS(ADDR_SURF_8_BANK)); 1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1211 NUM_BANKS(ADDR_SURF_4_BANK)); 1212 1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1216 if (reg_offset != 7) 1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1218 break; 1219 case CHIP_HAWAII: 1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1239 TILE_SPLIT(split_equal_to_row_size)); 1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1243 TILE_SPLIT(split_equal_to_row_size)); 1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1247 TILE_SPLIT(split_equal_to_row_size)); 1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1251 TILE_SPLIT(split_equal_to_row_size)); 1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1338 1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1342 NUM_BANKS(ADDR_SURF_16_BANK)); 1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1346 NUM_BANKS(ADDR_SURF_16_BANK)); 1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1350 NUM_BANKS(ADDR_SURF_16_BANK)); 1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1354 NUM_BANKS(ADDR_SURF_16_BANK)); 1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1358 NUM_BANKS(ADDR_SURF_8_BANK)); 1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1362 NUM_BANKS(ADDR_SURF_4_BANK)); 1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1366 NUM_BANKS(ADDR_SURF_4_BANK)); 1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1370 NUM_BANKS(ADDR_SURF_16_BANK)); 1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1374 NUM_BANKS(ADDR_SURF_16_BANK)); 1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1378 NUM_BANKS(ADDR_SURF_16_BANK)); 1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1382 NUM_BANKS(ADDR_SURF_8_BANK)); 1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1386 NUM_BANKS(ADDR_SURF_16_BANK)); 1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1390 NUM_BANKS(ADDR_SURF_8_BANK)); 1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1394 NUM_BANKS(ADDR_SURF_4_BANK)); 1395 1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1399 if (reg_offset != 7) 1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1401 break; 1402 case CHIP_KABINI: 1403 case CHIP_KAVERI: 1404 case CHIP_MULLINS: 1405 default: 1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1407 PIPE_CONFIG(ADDR_SURF_P2) | 1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1411 PIPE_CONFIG(ADDR_SURF_P2) | 1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1415 PIPE_CONFIG(ADDR_SURF_P2) | 1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1419 PIPE_CONFIG(ADDR_SURF_P2) | 1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1423 PIPE_CONFIG(ADDR_SURF_P2) | 1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1425 TILE_SPLIT(split_equal_to_row_size)); 1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1427 PIPE_CONFIG(ADDR_SURF_P2) | 1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1430 PIPE_CONFIG(ADDR_SURF_P2) | 1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1432 TILE_SPLIT(split_equal_to_row_size)); 1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1435 PIPE_CONFIG(ADDR_SURF_P2)); 1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1444 PIPE_CONFIG(ADDR_SURF_P2) | 1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1449 PIPE_CONFIG(ADDR_SURF_P2) | 1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1452 PIPE_CONFIG(ADDR_SURF_P2) | 1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1456 PIPE_CONFIG(ADDR_SURF_P2) | 1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1460 PIPE_CONFIG(ADDR_SURF_P2) | 1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1465 PIPE_CONFIG(ADDR_SURF_P2) | 1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1469 PIPE_CONFIG(ADDR_SURF_P2) | 1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1472 PIPE_CONFIG(ADDR_SURF_P2) | 1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1476 PIPE_CONFIG(ADDR_SURF_P2) | 1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1480 PIPE_CONFIG(ADDR_SURF_P2) | 1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1485 PIPE_CONFIG(ADDR_SURF_P2) | 1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1489 PIPE_CONFIG(ADDR_SURF_P2) | 1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1493 PIPE_CONFIG(ADDR_SURF_P2) | 1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1497 PIPE_CONFIG(ADDR_SURF_P2) | 1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1500 PIPE_CONFIG(ADDR_SURF_P2) | 1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1504 PIPE_CONFIG(ADDR_SURF_P2) | 1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1508 1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1512 NUM_BANKS(ADDR_SURF_8_BANK)); 1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1516 NUM_BANKS(ADDR_SURF_8_BANK)); 1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1520 NUM_BANKS(ADDR_SURF_8_BANK)); 1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1524 NUM_BANKS(ADDR_SURF_8_BANK)); 1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1528 NUM_BANKS(ADDR_SURF_8_BANK)); 1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1532 NUM_BANKS(ADDR_SURF_8_BANK)); 1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1536 NUM_BANKS(ADDR_SURF_8_BANK)); 1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1540 NUM_BANKS(ADDR_SURF_16_BANK)); 1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1544 NUM_BANKS(ADDR_SURF_16_BANK)); 1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1548 NUM_BANKS(ADDR_SURF_16_BANK)); 1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1552 NUM_BANKS(ADDR_SURF_16_BANK)); 1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1556 NUM_BANKS(ADDR_SURF_16_BANK)); 1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1560 NUM_BANKS(ADDR_SURF_16_BANK)); 1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1564 NUM_BANKS(ADDR_SURF_8_BANK)); 1565 1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1569 if (reg_offset != 7) 1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1571 break; 1572 } 1573 } 1574 1575 /** 1576 * gfx_v7_0_select_se_sh - select which SE, SH to address 1577 * 1578 * @adev: amdgpu_device pointer 1579 * @se_num: shader engine to address 1580 * @sh_num: sh block to address 1581 * 1582 * Select which SE, SH combinations to address. Certain 1583 * registers are instanced per SE or SH. 0xffffffff means 1584 * broadcast to all SEs or SHs (CIK). 1585 */ 1586 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1587 u32 se_num, u32 sh_num, u32 instance) 1588 { 1589 u32 data; 1590 1591 if (instance == 0xffffffff) 1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1593 else 1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1595 1596 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1599 else if (se_num == 0xffffffff) 1600 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1601 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1602 else if (sh_num == 0xffffffff) 1603 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1604 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1605 else 1606 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1607 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1608 WREG32(mmGRBM_GFX_INDEX, data); 1609 } 1610 1611 /** 1612 * gfx_v7_0_create_bitmask - create a bitmask 1613 * 1614 * @bit_width: length of the mask 1615 * 1616 * create a variable length bit mask (CIK). 1617 * Returns the bitmask. 1618 */ 1619 static u32 gfx_v7_0_create_bitmask(u32 bit_width) 1620 { 1621 return (u32)((1ULL << bit_width) - 1); 1622 } 1623 1624 /** 1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1626 * 1627 * @adev: amdgpu_device pointer 1628 * 1629 * Calculates the bitmask of enabled RBs (CIK). 1630 * Returns the enabled RB bitmask. 1631 */ 1632 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1633 { 1634 u32 data, mask; 1635 1636 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1637 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1638 1639 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1640 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1641 1642 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / 1643 adev->gfx.config.max_sh_per_se); 1644 1645 return (~data) & mask; 1646 } 1647 1648 static void 1649 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1650 { 1651 switch (adev->asic_type) { 1652 case CHIP_BONAIRE: 1653 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1654 SE_XSEL(1) | SE_YSEL(1); 1655 *rconf1 |= 0x0; 1656 break; 1657 case CHIP_HAWAII: 1658 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1661 SE_YSEL(3); 1662 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1663 SE_PAIR_YSEL(2); 1664 break; 1665 case CHIP_KAVERI: 1666 *rconf |= RB_MAP_PKR0(2); 1667 *rconf1 |= 0x0; 1668 break; 1669 case CHIP_KABINI: 1670 case CHIP_MULLINS: 1671 *rconf |= 0x0; 1672 *rconf1 |= 0x0; 1673 break; 1674 default: 1675 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1676 break; 1677 } 1678 } 1679 1680 static void 1681 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1682 u32 raster_config, u32 raster_config_1, 1683 unsigned rb_mask, unsigned num_rb) 1684 { 1685 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1686 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1687 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1688 unsigned rb_per_se = num_rb / num_se; 1689 unsigned se_mask[4]; 1690 unsigned se; 1691 1692 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1693 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1694 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1695 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1696 1697 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1698 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1699 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1700 1701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1702 (!se_mask[2] && !se_mask[3]))) { 1703 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1704 1705 if (!se_mask[0] && !se_mask[1]) { 1706 raster_config_1 |= 1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1708 } else { 1709 raster_config_1 |= 1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1711 } 1712 } 1713 1714 for (se = 0; se < num_se; se++) { 1715 unsigned raster_config_se = raster_config; 1716 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1717 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1718 int idx = (se / 2) * 2; 1719 1720 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1721 raster_config_se &= ~SE_MAP_MASK; 1722 1723 if (!se_mask[idx]) { 1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1725 } else { 1726 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1727 } 1728 } 1729 1730 pkr0_mask &= rb_mask; 1731 pkr1_mask &= rb_mask; 1732 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1733 raster_config_se &= ~PKR_MAP_MASK; 1734 1735 if (!pkr0_mask) { 1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1737 } else { 1738 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1739 } 1740 } 1741 1742 if (rb_per_se >= 2) { 1743 unsigned rb0_mask = 1 << (se * rb_per_se); 1744 unsigned rb1_mask = rb0_mask << 1; 1745 1746 rb0_mask &= rb_mask; 1747 rb1_mask &= rb_mask; 1748 if (!rb0_mask || !rb1_mask) { 1749 raster_config_se &= ~RB_MAP_PKR0_MASK; 1750 1751 if (!rb0_mask) { 1752 raster_config_se |= 1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1754 } else { 1755 raster_config_se |= 1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1757 } 1758 } 1759 1760 if (rb_per_se > 2) { 1761 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1762 rb1_mask = rb0_mask << 1; 1763 rb0_mask &= rb_mask; 1764 rb1_mask &= rb_mask; 1765 if (!rb0_mask || !rb1_mask) { 1766 raster_config_se &= ~RB_MAP_PKR1_MASK; 1767 1768 if (!rb0_mask) { 1769 raster_config_se |= 1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1771 } else { 1772 raster_config_se |= 1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1774 } 1775 } 1776 } 1777 } 1778 1779 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1780 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1781 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1782 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1783 } 1784 1785 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1786 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1787 } 1788 1789 /** 1790 * gfx_v7_0_setup_rb - setup the RBs on the asic 1791 * 1792 * @adev: amdgpu_device pointer 1793 * @se_num: number of SEs (shader engines) for the asic 1794 * @sh_per_se: number of SH blocks per SE for the asic 1795 * 1796 * Configures per-SE/SH RB registers (CIK). 1797 */ 1798 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1799 { 1800 int i, j; 1801 u32 data; 1802 u32 raster_config = 0, raster_config_1 = 0; 1803 u32 active_rbs = 0; 1804 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1805 adev->gfx.config.max_sh_per_se; 1806 unsigned num_rb_pipes; 1807 1808 mutex_lock(&adev->grbm_idx_mutex); 1809 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1810 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1811 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1812 data = gfx_v7_0_get_rb_active_bitmap(adev); 1813 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1814 rb_bitmap_width_per_sh); 1815 } 1816 } 1817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1818 1819 adev->gfx.config.backend_enable_mask = active_rbs; 1820 adev->gfx.config.num_rbs = hweight32(active_rbs); 1821 1822 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1823 adev->gfx.config.max_shader_engines, 16); 1824 1825 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1826 1827 if (!adev->gfx.config.backend_enable_mask || 1828 adev->gfx.config.num_rbs >= num_rb_pipes) { 1829 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1830 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1831 } else { 1832 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1833 adev->gfx.config.backend_enable_mask, 1834 num_rb_pipes); 1835 } 1836 mutex_unlock(&adev->grbm_idx_mutex); 1837 } 1838 1839 /** 1840 * gmc_v7_0_init_compute_vmid - gart enable 1841 * 1842 * @rdev: amdgpu_device pointer 1843 * 1844 * Initialize compute vmid sh_mem registers 1845 * 1846 */ 1847 #define DEFAULT_SH_MEM_BASES (0x6000) 1848 #define FIRST_COMPUTE_VMID (8) 1849 #define LAST_COMPUTE_VMID (16) 1850 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1851 { 1852 int i; 1853 uint32_t sh_mem_config; 1854 uint32_t sh_mem_bases; 1855 1856 /* 1857 * Configure apertures: 1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1861 */ 1862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1863 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1865 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1866 mutex_lock(&adev->srbm_mutex); 1867 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1868 cik_srbm_select(adev, 0, 0, 0, i); 1869 /* CP and shaders */ 1870 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1871 WREG32(mmSH_MEM_APE1_BASE, 1); 1872 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1873 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1874 } 1875 cik_srbm_select(adev, 0, 0, 0, 0); 1876 mutex_unlock(&adev->srbm_mutex); 1877 } 1878 1879 /** 1880 * gfx_v7_0_gpu_init - setup the 3D engine 1881 * 1882 * @adev: amdgpu_device pointer 1883 * 1884 * Configures the 3D engine and tiling configuration 1885 * registers so that the 3D engine is usable. 1886 */ 1887 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 1888 { 1889 u32 tmp, sh_mem_cfg; 1890 int i; 1891 1892 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1893 1894 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1895 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1896 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1897 1898 gfx_v7_0_tiling_mode_table_init(adev); 1899 1900 gfx_v7_0_setup_rb(adev); 1901 gfx_v7_0_get_cu_info(adev); 1902 1903 /* set HW defaults for 3D engine */ 1904 WREG32(mmCP_MEQ_THRESHOLDS, 1905 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1906 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1907 1908 mutex_lock(&adev->grbm_idx_mutex); 1909 /* 1910 * making sure that the following register writes will be broadcasted 1911 * to all the shaders 1912 */ 1913 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1914 1915 /* XXX SH_MEM regs */ 1916 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1917 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1918 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1919 1920 mutex_lock(&adev->srbm_mutex); 1921 for (i = 0; i < 16; i++) { 1922 cik_srbm_select(adev, 0, 0, 0, i); 1923 /* CP and shaders */ 1924 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1925 WREG32(mmSH_MEM_APE1_BASE, 1); 1926 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1927 WREG32(mmSH_MEM_BASES, 0); 1928 } 1929 cik_srbm_select(adev, 0, 0, 0, 0); 1930 mutex_unlock(&adev->srbm_mutex); 1931 1932 gmc_v7_0_init_compute_vmid(adev); 1933 1934 WREG32(mmSX_DEBUG_1, 0x20); 1935 1936 WREG32(mmTA_CNTL_AUX, 0x00010000); 1937 1938 tmp = RREG32(mmSPI_CONFIG_CNTL); 1939 tmp |= 0x03000000; 1940 WREG32(mmSPI_CONFIG_CNTL, tmp); 1941 1942 WREG32(mmSQ_CONFIG, 1); 1943 1944 WREG32(mmDB_DEBUG, 0); 1945 1946 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1947 tmp |= 0x00000400; 1948 WREG32(mmDB_DEBUG2, tmp); 1949 1950 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1951 tmp |= 0x00020200; 1952 WREG32(mmDB_DEBUG3, tmp); 1953 1954 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1955 tmp |= 0x00018208; 1956 WREG32(mmCB_HW_CONTROL, tmp); 1957 1958 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1959 1960 WREG32(mmPA_SC_FIFO_SIZE, 1961 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1962 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1963 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1964 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1965 1966 WREG32(mmVGT_NUM_INSTANCES, 1); 1967 1968 WREG32(mmCP_PERFMON_CNTL, 0); 1969 1970 WREG32(mmSQ_CONFIG, 0); 1971 1972 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1973 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1974 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1975 1976 WREG32(mmVGT_CACHE_INVALIDATION, 1977 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1978 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1979 1980 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1981 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1982 1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 1986 1987 tmp = RREG32(mmSPI_ARB_PRIORITY); 1988 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 1989 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 1990 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 1991 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 1992 WREG32(mmSPI_ARB_PRIORITY, tmp); 1993 1994 mutex_unlock(&adev->grbm_idx_mutex); 1995 1996 udelay(50); 1997 } 1998 1999 /* 2000 * GPU scratch registers helpers function. 2001 */ 2002 /** 2003 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 2004 * 2005 * @adev: amdgpu_device pointer 2006 * 2007 * Set up the number and offset of the CP scratch registers. 2008 * NOTE: use of CP scratch registers is a legacy inferface and 2009 * is not used by default on newer asics (r6xx+). On newer asics, 2010 * memory buffers are used for fences rather than scratch regs. 2011 */ 2012 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 2013 { 2014 adev->gfx.scratch.num_reg = 7; 2015 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 2016 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 2017 } 2018 2019 /** 2020 * gfx_v7_0_ring_test_ring - basic gfx ring test 2021 * 2022 * @adev: amdgpu_device pointer 2023 * @ring: amdgpu_ring structure holding ring information 2024 * 2025 * Allocate a scratch register and write to it using the gfx ring (CIK). 2026 * Provides a basic gfx ring test to verify that the ring is working. 2027 * Used by gfx_v7_0_cp_gfx_resume(); 2028 * Returns 0 on success, error on failure. 2029 */ 2030 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2031 { 2032 struct amdgpu_device *adev = ring->adev; 2033 uint32_t scratch; 2034 uint32_t tmp = 0; 2035 unsigned i; 2036 int r; 2037 2038 r = amdgpu_gfx_scratch_get(adev, &scratch); 2039 if (r) { 2040 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 2041 return r; 2042 } 2043 WREG32(scratch, 0xCAFEDEAD); 2044 r = amdgpu_ring_alloc(ring, 3); 2045 if (r) { 2046 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 2047 amdgpu_gfx_scratch_free(adev, scratch); 2048 return r; 2049 } 2050 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2051 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2052 amdgpu_ring_write(ring, 0xDEADBEEF); 2053 amdgpu_ring_commit(ring); 2054 2055 for (i = 0; i < adev->usec_timeout; i++) { 2056 tmp = RREG32(scratch); 2057 if (tmp == 0xDEADBEEF) 2058 break; 2059 DRM_UDELAY(1); 2060 } 2061 if (i < adev->usec_timeout) { 2062 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2063 } else { 2064 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2065 ring->idx, scratch, tmp); 2066 r = -EINVAL; 2067 } 2068 amdgpu_gfx_scratch_free(adev, scratch); 2069 return r; 2070 } 2071 2072 /** 2073 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 2074 * 2075 * @adev: amdgpu_device pointer 2076 * @ridx: amdgpu ring index 2077 * 2078 * Emits an hdp flush on the cp. 2079 */ 2080 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2081 { 2082 u32 ref_and_mask; 2083 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2084 2085 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2086 switch (ring->me) { 2087 case 1: 2088 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2089 break; 2090 case 2: 2091 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2092 break; 2093 default: 2094 return; 2095 } 2096 } else { 2097 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2098 } 2099 2100 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2101 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2102 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2103 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2104 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2105 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2106 amdgpu_ring_write(ring, ref_and_mask); 2107 amdgpu_ring_write(ring, ref_and_mask); 2108 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2109 } 2110 2111 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2112 { 2113 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2114 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2115 EVENT_INDEX(4)); 2116 2117 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2118 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2119 EVENT_INDEX(0)); 2120 } 2121 2122 2123 /** 2124 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 2125 * 2126 * @adev: amdgpu_device pointer 2127 * @ridx: amdgpu ring index 2128 * 2129 * Emits an hdp invalidate on the cp. 2130 */ 2131 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 2132 { 2133 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2134 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2135 WRITE_DATA_DST_SEL(0) | 2136 WR_CONFIRM)); 2137 amdgpu_ring_write(ring, mmHDP_DEBUG0); 2138 amdgpu_ring_write(ring, 0); 2139 amdgpu_ring_write(ring, 1); 2140 } 2141 2142 /** 2143 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2144 * 2145 * @adev: amdgpu_device pointer 2146 * @fence: amdgpu fence object 2147 * 2148 * Emits a fence sequnce number on the gfx ring and flushes 2149 * GPU caches. 2150 */ 2151 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2152 u64 seq, unsigned flags) 2153 { 2154 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2155 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2156 /* Workaround for cache flush problems. First send a dummy EOP 2157 * event down the pipe with seq one below. 2158 */ 2159 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2160 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2161 EOP_TC_ACTION_EN | 2162 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2163 EVENT_INDEX(5))); 2164 amdgpu_ring_write(ring, addr & 0xfffffffc); 2165 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2166 DATA_SEL(1) | INT_SEL(0)); 2167 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2168 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2169 2170 /* Then send the real EOP event down the pipe. */ 2171 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2172 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2173 EOP_TC_ACTION_EN | 2174 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2175 EVENT_INDEX(5))); 2176 amdgpu_ring_write(ring, addr & 0xfffffffc); 2177 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2178 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2179 amdgpu_ring_write(ring, lower_32_bits(seq)); 2180 amdgpu_ring_write(ring, upper_32_bits(seq)); 2181 } 2182 2183 /** 2184 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2185 * 2186 * @adev: amdgpu_device pointer 2187 * @fence: amdgpu fence object 2188 * 2189 * Emits a fence sequnce number on the compute ring and flushes 2190 * GPU caches. 2191 */ 2192 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2193 u64 addr, u64 seq, 2194 unsigned flags) 2195 { 2196 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2197 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2198 2199 /* RELEASE_MEM - flush caches, send int */ 2200 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2201 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2202 EOP_TC_ACTION_EN | 2203 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2204 EVENT_INDEX(5))); 2205 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2206 amdgpu_ring_write(ring, addr & 0xfffffffc); 2207 amdgpu_ring_write(ring, upper_32_bits(addr)); 2208 amdgpu_ring_write(ring, lower_32_bits(seq)); 2209 amdgpu_ring_write(ring, upper_32_bits(seq)); 2210 } 2211 2212 /* 2213 * IB stuff 2214 */ 2215 /** 2216 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2217 * 2218 * @ring: amdgpu_ring structure holding ring information 2219 * @ib: amdgpu indirect buffer object 2220 * 2221 * Emits an DE (drawing engine) or CE (constant engine) IB 2222 * on the gfx ring. IBs are usually generated by userspace 2223 * acceleration drivers and submitted to the kernel for 2224 * sheduling on the ring. This function schedules the IB 2225 * on the gfx ring for execution by the GPU. 2226 */ 2227 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2228 struct amdgpu_ib *ib, 2229 unsigned vm_id, bool ctx_switch) 2230 { 2231 u32 header, control = 0; 2232 2233 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2234 if (ctx_switch) { 2235 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2236 amdgpu_ring_write(ring, 0); 2237 } 2238 2239 if (ib->flags & AMDGPU_IB_FLAG_CE) 2240 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2241 else 2242 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2243 2244 control |= ib->length_dw | (vm_id << 24); 2245 2246 amdgpu_ring_write(ring, header); 2247 amdgpu_ring_write(ring, 2248 #ifdef __BIG_ENDIAN 2249 (2 << 0) | 2250 #endif 2251 (ib->gpu_addr & 0xFFFFFFFC)); 2252 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2253 amdgpu_ring_write(ring, control); 2254 } 2255 2256 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2257 struct amdgpu_ib *ib, 2258 unsigned vm_id, bool ctx_switch) 2259 { 2260 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24); 2261 2262 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2263 amdgpu_ring_write(ring, 2264 #ifdef __BIG_ENDIAN 2265 (2 << 0) | 2266 #endif 2267 (ib->gpu_addr & 0xFFFFFFFC)); 2268 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2269 amdgpu_ring_write(ring, control); 2270 } 2271 2272 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2273 { 2274 uint32_t dw2 = 0; 2275 2276 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2277 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2278 gfx_v7_0_ring_emit_vgt_flush(ring); 2279 /* set load_global_config & load_global_uconfig */ 2280 dw2 |= 0x8001; 2281 /* set load_cs_sh_regs */ 2282 dw2 |= 0x01000000; 2283 /* set load_per_context_state & load_gfx_sh_regs */ 2284 dw2 |= 0x10002; 2285 } 2286 2287 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2288 amdgpu_ring_write(ring, dw2); 2289 amdgpu_ring_write(ring, 0); 2290 } 2291 2292 /** 2293 * gfx_v7_0_ring_test_ib - basic ring IB test 2294 * 2295 * @ring: amdgpu_ring structure holding ring information 2296 * 2297 * Allocate an IB and execute it on the gfx ring (CIK). 2298 * Provides a basic gfx ring test to verify that IBs are working. 2299 * Returns 0 on success, error on failure. 2300 */ 2301 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2302 { 2303 struct amdgpu_device *adev = ring->adev; 2304 struct amdgpu_ib ib; 2305 struct dma_fence *f = NULL; 2306 uint32_t scratch; 2307 uint32_t tmp = 0; 2308 long r; 2309 2310 r = amdgpu_gfx_scratch_get(adev, &scratch); 2311 if (r) { 2312 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 2313 return r; 2314 } 2315 WREG32(scratch, 0xCAFEDEAD); 2316 memset(&ib, 0, sizeof(ib)); 2317 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2318 if (r) { 2319 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 2320 goto err1; 2321 } 2322 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2323 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2324 ib.ptr[2] = 0xDEADBEEF; 2325 ib.length_dw = 3; 2326 2327 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2328 if (r) 2329 goto err2; 2330 2331 r = dma_fence_wait_timeout(f, false, timeout); 2332 if (r == 0) { 2333 DRM_ERROR("amdgpu: IB test timed out\n"); 2334 r = -ETIMEDOUT; 2335 goto err2; 2336 } else if (r < 0) { 2337 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 2338 goto err2; 2339 } 2340 tmp = RREG32(scratch); 2341 if (tmp == 0xDEADBEEF) { 2342 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 2343 r = 0; 2344 } else { 2345 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 2346 scratch, tmp); 2347 r = -EINVAL; 2348 } 2349 2350 err2: 2351 amdgpu_ib_free(adev, &ib, NULL); 2352 dma_fence_put(f); 2353 err1: 2354 amdgpu_gfx_scratch_free(adev, scratch); 2355 return r; 2356 } 2357 2358 /* 2359 * CP. 2360 * On CIK, gfx and compute now have independant command processors. 2361 * 2362 * GFX 2363 * Gfx consists of a single ring and can process both gfx jobs and 2364 * compute jobs. The gfx CP consists of three microengines (ME): 2365 * PFP - Pre-Fetch Parser 2366 * ME - Micro Engine 2367 * CE - Constant Engine 2368 * The PFP and ME make up what is considered the Drawing Engine (DE). 2369 * The CE is an asynchronous engine used for updating buffer desciptors 2370 * used by the DE so that they can be loaded into cache in parallel 2371 * while the DE is processing state update packets. 2372 * 2373 * Compute 2374 * The compute CP consists of two microengines (ME): 2375 * MEC1 - Compute MicroEngine 1 2376 * MEC2 - Compute MicroEngine 2 2377 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2378 * The queues are exposed to userspace and are programmed directly 2379 * by the compute runtime. 2380 */ 2381 /** 2382 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2383 * 2384 * @adev: amdgpu_device pointer 2385 * @enable: enable or disable the MEs 2386 * 2387 * Halts or unhalts the gfx MEs. 2388 */ 2389 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2390 { 2391 int i; 2392 2393 if (enable) { 2394 WREG32(mmCP_ME_CNTL, 0); 2395 } else { 2396 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2397 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2398 adev->gfx.gfx_ring[i].ready = false; 2399 } 2400 udelay(50); 2401 } 2402 2403 /** 2404 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2405 * 2406 * @adev: amdgpu_device pointer 2407 * 2408 * Loads the gfx PFP, ME, and CE ucode. 2409 * Returns 0 for success, -EINVAL if the ucode is not available. 2410 */ 2411 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2412 { 2413 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2414 const struct gfx_firmware_header_v1_0 *ce_hdr; 2415 const struct gfx_firmware_header_v1_0 *me_hdr; 2416 const __le32 *fw_data; 2417 unsigned i, fw_size; 2418 2419 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2420 return -EINVAL; 2421 2422 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2423 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2424 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2425 2426 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2427 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2428 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2429 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2430 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2431 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2432 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2433 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2434 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2435 2436 gfx_v7_0_cp_gfx_enable(adev, false); 2437 2438 /* PFP */ 2439 fw_data = (const __le32 *) 2440 (adev->gfx.pfp_fw->data + 2441 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2442 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2443 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2444 for (i = 0; i < fw_size; i++) 2445 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2446 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2447 2448 /* CE */ 2449 fw_data = (const __le32 *) 2450 (adev->gfx.ce_fw->data + 2451 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2452 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2453 WREG32(mmCP_CE_UCODE_ADDR, 0); 2454 for (i = 0; i < fw_size; i++) 2455 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2456 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2457 2458 /* ME */ 2459 fw_data = (const __le32 *) 2460 (adev->gfx.me_fw->data + 2461 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2462 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2463 WREG32(mmCP_ME_RAM_WADDR, 0); 2464 for (i = 0; i < fw_size; i++) 2465 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2466 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2467 2468 return 0; 2469 } 2470 2471 /** 2472 * gfx_v7_0_cp_gfx_start - start the gfx ring 2473 * 2474 * @adev: amdgpu_device pointer 2475 * 2476 * Enables the ring and loads the clear state context and other 2477 * packets required to init the ring. 2478 * Returns 0 for success, error for failure. 2479 */ 2480 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2481 { 2482 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2483 const struct cs_section_def *sect = NULL; 2484 const struct cs_extent_def *ext = NULL; 2485 int r, i; 2486 2487 /* init the CP */ 2488 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2489 WREG32(mmCP_ENDIAN_SWAP, 0); 2490 WREG32(mmCP_DEVICE_ID, 1); 2491 2492 gfx_v7_0_cp_gfx_enable(adev, true); 2493 2494 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2495 if (r) { 2496 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2497 return r; 2498 } 2499 2500 /* init the CE partitions. CE only used for gfx on CIK */ 2501 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2502 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2503 amdgpu_ring_write(ring, 0x8000); 2504 amdgpu_ring_write(ring, 0x8000); 2505 2506 /* clear state buffer */ 2507 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2508 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2509 2510 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2511 amdgpu_ring_write(ring, 0x80000000); 2512 amdgpu_ring_write(ring, 0x80000000); 2513 2514 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2515 for (ext = sect->section; ext->extent != NULL; ++ext) { 2516 if (sect->id == SECT_CONTEXT) { 2517 amdgpu_ring_write(ring, 2518 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2519 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2520 for (i = 0; i < ext->reg_count; i++) 2521 amdgpu_ring_write(ring, ext->extent[i]); 2522 } 2523 } 2524 } 2525 2526 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2527 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2528 switch (adev->asic_type) { 2529 case CHIP_BONAIRE: 2530 amdgpu_ring_write(ring, 0x16000012); 2531 amdgpu_ring_write(ring, 0x00000000); 2532 break; 2533 case CHIP_KAVERI: 2534 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2535 amdgpu_ring_write(ring, 0x00000000); 2536 break; 2537 case CHIP_KABINI: 2538 case CHIP_MULLINS: 2539 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2540 amdgpu_ring_write(ring, 0x00000000); 2541 break; 2542 case CHIP_HAWAII: 2543 amdgpu_ring_write(ring, 0x3a00161a); 2544 amdgpu_ring_write(ring, 0x0000002e); 2545 break; 2546 default: 2547 amdgpu_ring_write(ring, 0x00000000); 2548 amdgpu_ring_write(ring, 0x00000000); 2549 break; 2550 } 2551 2552 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2553 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2554 2555 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2556 amdgpu_ring_write(ring, 0); 2557 2558 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2559 amdgpu_ring_write(ring, 0x00000316); 2560 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2561 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2562 2563 amdgpu_ring_commit(ring); 2564 2565 return 0; 2566 } 2567 2568 /** 2569 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2570 * 2571 * @adev: amdgpu_device pointer 2572 * 2573 * Program the location and size of the gfx ring buffer 2574 * and test it to make sure it's working. 2575 * Returns 0 for success, error for failure. 2576 */ 2577 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2578 { 2579 struct amdgpu_ring *ring; 2580 u32 tmp; 2581 u32 rb_bufsz; 2582 u64 rb_addr, rptr_addr; 2583 int r; 2584 2585 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2586 if (adev->asic_type != CHIP_HAWAII) 2587 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2588 2589 /* Set the write pointer delay */ 2590 WREG32(mmCP_RB_WPTR_DELAY, 0); 2591 2592 /* set the RB to use vmid 0 */ 2593 WREG32(mmCP_RB_VMID, 0); 2594 2595 WREG32(mmSCRATCH_ADDR, 0); 2596 2597 /* ring 0 - compute and gfx */ 2598 /* Set ring buffer size */ 2599 ring = &adev->gfx.gfx_ring[0]; 2600 rb_bufsz = order_base_2(ring->ring_size / 8); 2601 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2602 #ifdef __BIG_ENDIAN 2603 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2604 #endif 2605 WREG32(mmCP_RB0_CNTL, tmp); 2606 2607 /* Initialize the ring buffer's read and write pointers */ 2608 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2609 ring->wptr = 0; 2610 WREG32(mmCP_RB0_WPTR, ring->wptr); 2611 2612 /* set the wb address wether it's enabled or not */ 2613 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2614 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2615 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2616 2617 /* scratch register shadowing is no longer supported */ 2618 WREG32(mmSCRATCH_UMSK, 0); 2619 2620 mdelay(1); 2621 WREG32(mmCP_RB0_CNTL, tmp); 2622 2623 rb_addr = ring->gpu_addr >> 8; 2624 WREG32(mmCP_RB0_BASE, rb_addr); 2625 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2626 2627 /* start the ring */ 2628 gfx_v7_0_cp_gfx_start(adev); 2629 ring->ready = true; 2630 r = amdgpu_ring_test_ring(ring); 2631 if (r) { 2632 ring->ready = false; 2633 return r; 2634 } 2635 2636 return 0; 2637 } 2638 2639 static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2640 { 2641 return ring->adev->wb.wb[ring->rptr_offs]; 2642 } 2643 2644 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2645 { 2646 struct amdgpu_device *adev = ring->adev; 2647 2648 return RREG32(mmCP_RB0_WPTR); 2649 } 2650 2651 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2652 { 2653 struct amdgpu_device *adev = ring->adev; 2654 2655 WREG32(mmCP_RB0_WPTR, ring->wptr); 2656 (void)RREG32(mmCP_RB0_WPTR); 2657 } 2658 2659 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2660 { 2661 /* XXX check if swapping is necessary on BE */ 2662 return ring->adev->wb.wb[ring->wptr_offs]; 2663 } 2664 2665 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2666 { 2667 struct amdgpu_device *adev = ring->adev; 2668 2669 /* XXX check if swapping is necessary on BE */ 2670 adev->wb.wb[ring->wptr_offs] = ring->wptr; 2671 WDOORBELL32(ring->doorbell_index, ring->wptr); 2672 } 2673 2674 /** 2675 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2676 * 2677 * @adev: amdgpu_device pointer 2678 * @enable: enable or disable the MEs 2679 * 2680 * Halts or unhalts the compute MEs. 2681 */ 2682 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2683 { 2684 int i; 2685 2686 if (enable) { 2687 WREG32(mmCP_MEC_CNTL, 0); 2688 } else { 2689 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2690 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2691 adev->gfx.compute_ring[i].ready = false; 2692 } 2693 udelay(50); 2694 } 2695 2696 /** 2697 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2698 * 2699 * @adev: amdgpu_device pointer 2700 * 2701 * Loads the compute MEC1&2 ucode. 2702 * Returns 0 for success, -EINVAL if the ucode is not available. 2703 */ 2704 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2705 { 2706 const struct gfx_firmware_header_v1_0 *mec_hdr; 2707 const __le32 *fw_data; 2708 unsigned i, fw_size; 2709 2710 if (!adev->gfx.mec_fw) 2711 return -EINVAL; 2712 2713 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2714 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2715 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2716 adev->gfx.mec_feature_version = le32_to_cpu( 2717 mec_hdr->ucode_feature_version); 2718 2719 gfx_v7_0_cp_compute_enable(adev, false); 2720 2721 /* MEC1 */ 2722 fw_data = (const __le32 *) 2723 (adev->gfx.mec_fw->data + 2724 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2725 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2726 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2727 for (i = 0; i < fw_size; i++) 2728 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2729 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2730 2731 if (adev->asic_type == CHIP_KAVERI) { 2732 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2733 2734 if (!adev->gfx.mec2_fw) 2735 return -EINVAL; 2736 2737 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2738 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2739 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2740 adev->gfx.mec2_feature_version = le32_to_cpu( 2741 mec2_hdr->ucode_feature_version); 2742 2743 /* MEC2 */ 2744 fw_data = (const __le32 *) 2745 (adev->gfx.mec2_fw->data + 2746 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2747 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2748 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2749 for (i = 0; i < fw_size; i++) 2750 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2751 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2752 } 2753 2754 return 0; 2755 } 2756 2757 /** 2758 * gfx_v7_0_cp_compute_fini - stop the compute queues 2759 * 2760 * @adev: amdgpu_device pointer 2761 * 2762 * Stop the compute queues and tear down the driver queue 2763 * info. 2764 */ 2765 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2766 { 2767 int i, r; 2768 2769 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2770 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2771 2772 if (ring->mqd_obj) { 2773 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2774 if (unlikely(r != 0)) 2775 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 2776 2777 amdgpu_bo_unpin(ring->mqd_obj); 2778 amdgpu_bo_unreserve(ring->mqd_obj); 2779 2780 amdgpu_bo_unref(&ring->mqd_obj); 2781 ring->mqd_obj = NULL; 2782 } 2783 } 2784 } 2785 2786 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2787 { 2788 int r; 2789 2790 if (adev->gfx.mec.hpd_eop_obj) { 2791 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2792 if (unlikely(r != 0)) 2793 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 2794 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 2795 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2796 2797 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 2798 adev->gfx.mec.hpd_eop_obj = NULL; 2799 } 2800 } 2801 2802 #define MEC_HPD_SIZE 2048 2803 2804 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2805 { 2806 int r; 2807 u32 *hpd; 2808 2809 /* 2810 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total 2811 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total 2812 * Nonetheless, we assign only 1 pipe because all other pipes will 2813 * be handled by KFD 2814 */ 2815 adev->gfx.mec.num_mec = 1; 2816 adev->gfx.mec.num_pipe = 1; 2817 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 2818 2819 if (adev->gfx.mec.hpd_eop_obj == NULL) { 2820 r = amdgpu_bo_create(adev, 2821 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 2822 PAGE_SIZE, true, 2823 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2824 &adev->gfx.mec.hpd_eop_obj); 2825 if (r) { 2826 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 2827 return r; 2828 } 2829 } 2830 2831 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2832 if (unlikely(r != 0)) { 2833 gfx_v7_0_mec_fini(adev); 2834 return r; 2835 } 2836 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 2837 &adev->gfx.mec.hpd_eop_gpu_addr); 2838 if (r) { 2839 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 2840 gfx_v7_0_mec_fini(adev); 2841 return r; 2842 } 2843 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 2844 if (r) { 2845 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 2846 gfx_v7_0_mec_fini(adev); 2847 return r; 2848 } 2849 2850 /* clear memory. Not sure if this is required or not */ 2851 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 2852 2853 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2854 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2855 2856 return 0; 2857 } 2858 2859 struct hqd_registers 2860 { 2861 u32 cp_mqd_base_addr; 2862 u32 cp_mqd_base_addr_hi; 2863 u32 cp_hqd_active; 2864 u32 cp_hqd_vmid; 2865 u32 cp_hqd_persistent_state; 2866 u32 cp_hqd_pipe_priority; 2867 u32 cp_hqd_queue_priority; 2868 u32 cp_hqd_quantum; 2869 u32 cp_hqd_pq_base; 2870 u32 cp_hqd_pq_base_hi; 2871 u32 cp_hqd_pq_rptr; 2872 u32 cp_hqd_pq_rptr_report_addr; 2873 u32 cp_hqd_pq_rptr_report_addr_hi; 2874 u32 cp_hqd_pq_wptr_poll_addr; 2875 u32 cp_hqd_pq_wptr_poll_addr_hi; 2876 u32 cp_hqd_pq_doorbell_control; 2877 u32 cp_hqd_pq_wptr; 2878 u32 cp_hqd_pq_control; 2879 u32 cp_hqd_ib_base_addr; 2880 u32 cp_hqd_ib_base_addr_hi; 2881 u32 cp_hqd_ib_rptr; 2882 u32 cp_hqd_ib_control; 2883 u32 cp_hqd_iq_timer; 2884 u32 cp_hqd_iq_rptr; 2885 u32 cp_hqd_dequeue_request; 2886 u32 cp_hqd_dma_offload; 2887 u32 cp_hqd_sema_cmd; 2888 u32 cp_hqd_msg_type; 2889 u32 cp_hqd_atomic0_preop_lo; 2890 u32 cp_hqd_atomic0_preop_hi; 2891 u32 cp_hqd_atomic1_preop_lo; 2892 u32 cp_hqd_atomic1_preop_hi; 2893 u32 cp_hqd_hq_scheduler0; 2894 u32 cp_hqd_hq_scheduler1; 2895 u32 cp_mqd_control; 2896 }; 2897 2898 struct bonaire_mqd 2899 { 2900 u32 header; 2901 u32 dispatch_initiator; 2902 u32 dimensions[3]; 2903 u32 start_idx[3]; 2904 u32 num_threads[3]; 2905 u32 pipeline_stat_enable; 2906 u32 perf_counter_enable; 2907 u32 pgm[2]; 2908 u32 tba[2]; 2909 u32 tma[2]; 2910 u32 pgm_rsrc[2]; 2911 u32 vmid; 2912 u32 resource_limits; 2913 u32 static_thread_mgmt01[2]; 2914 u32 tmp_ring_size; 2915 u32 static_thread_mgmt23[2]; 2916 u32 restart[3]; 2917 u32 thread_trace_enable; 2918 u32 reserved1; 2919 u32 user_data[16]; 2920 u32 vgtcs_invoke_count[2]; 2921 struct hqd_registers queue_state; 2922 u32 dequeue_cntr; 2923 u32 interrupt_queue[64]; 2924 }; 2925 2926 /** 2927 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 2928 * 2929 * @adev: amdgpu_device pointer 2930 * 2931 * Program the compute queues and test them to make sure they 2932 * are working. 2933 * Returns 0 for success, error for failure. 2934 */ 2935 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 2936 { 2937 int r, i, j; 2938 u32 tmp; 2939 bool use_doorbell = true; 2940 u64 hqd_gpu_addr; 2941 u64 mqd_gpu_addr; 2942 u64 eop_gpu_addr; 2943 u64 wb_gpu_addr; 2944 u32 *buf; 2945 struct bonaire_mqd *mqd; 2946 struct amdgpu_ring *ring; 2947 2948 /* fix up chicken bits */ 2949 tmp = RREG32(mmCP_CPF_DEBUG); 2950 tmp |= (1 << 23); 2951 WREG32(mmCP_CPF_DEBUG, tmp); 2952 2953 /* init the pipes */ 2954 mutex_lock(&adev->srbm_mutex); 2955 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 2956 int me = (i < 4) ? 1 : 2; 2957 int pipe = (i < 4) ? i : (i - 4); 2958 2959 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); 2960 2961 cik_srbm_select(adev, me, pipe, 0, 0); 2962 2963 /* write the EOP addr */ 2964 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2965 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2966 2967 /* set the VMID assigned */ 2968 WREG32(mmCP_HPD_EOP_VMID, 0); 2969 2970 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2971 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2972 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2973 tmp |= order_base_2(MEC_HPD_SIZE / 8); 2974 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2975 } 2976 cik_srbm_select(adev, 0, 0, 0, 0); 2977 mutex_unlock(&adev->srbm_mutex); 2978 2979 /* init the queues. Just two for now. */ 2980 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2981 ring = &adev->gfx.compute_ring[i]; 2982 2983 if (ring->mqd_obj == NULL) { 2984 r = amdgpu_bo_create(adev, 2985 sizeof(struct bonaire_mqd), 2986 PAGE_SIZE, true, 2987 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2988 &ring->mqd_obj); 2989 if (r) { 2990 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 2991 return r; 2992 } 2993 } 2994 2995 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2996 if (unlikely(r != 0)) { 2997 gfx_v7_0_cp_compute_fini(adev); 2998 return r; 2999 } 3000 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 3001 &mqd_gpu_addr); 3002 if (r) { 3003 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 3004 gfx_v7_0_cp_compute_fini(adev); 3005 return r; 3006 } 3007 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 3008 if (r) { 3009 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 3010 gfx_v7_0_cp_compute_fini(adev); 3011 return r; 3012 } 3013 3014 /* init the mqd struct */ 3015 memset(buf, 0, sizeof(struct bonaire_mqd)); 3016 3017 mqd = (struct bonaire_mqd *)buf; 3018 mqd->header = 0xC0310800; 3019 mqd->static_thread_mgmt01[0] = 0xffffffff; 3020 mqd->static_thread_mgmt01[1] = 0xffffffff; 3021 mqd->static_thread_mgmt23[0] = 0xffffffff; 3022 mqd->static_thread_mgmt23[1] = 0xffffffff; 3023 3024 mutex_lock(&adev->srbm_mutex); 3025 cik_srbm_select(adev, ring->me, 3026 ring->pipe, 3027 ring->queue, 0); 3028 3029 /* disable wptr polling */ 3030 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3031 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; 3032 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3033 3034 /* enable doorbell? */ 3035 mqd->queue_state.cp_hqd_pq_doorbell_control = 3036 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3037 if (use_doorbell) 3038 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3039 else 3040 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3041 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3042 mqd->queue_state.cp_hqd_pq_doorbell_control); 3043 3044 /* disable the queue if it's active */ 3045 mqd->queue_state.cp_hqd_dequeue_request = 0; 3046 mqd->queue_state.cp_hqd_pq_rptr = 0; 3047 mqd->queue_state.cp_hqd_pq_wptr= 0; 3048 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 3049 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 3050 for (j = 0; j < adev->usec_timeout; j++) { 3051 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 3052 break; 3053 udelay(1); 3054 } 3055 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); 3056 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); 3057 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 3058 } 3059 3060 /* set the pointer to the MQD */ 3061 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; 3062 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 3063 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); 3064 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); 3065 /* set MQD vmid to 0 */ 3066 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 3067 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 3068 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); 3069 3070 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3071 hqd_gpu_addr = ring->gpu_addr >> 8; 3072 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; 3073 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3074 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); 3075 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); 3076 3077 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3078 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 3079 mqd->queue_state.cp_hqd_pq_control &= 3080 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 3081 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 3082 3083 mqd->queue_state.cp_hqd_pq_control |= 3084 order_base_2(ring->ring_size / 8); 3085 mqd->queue_state.cp_hqd_pq_control |= 3086 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 3087 #ifdef __BIG_ENDIAN 3088 mqd->queue_state.cp_hqd_pq_control |= 3089 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 3090 #endif 3091 mqd->queue_state.cp_hqd_pq_control &= 3092 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 3093 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 3094 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 3095 mqd->queue_state.cp_hqd_pq_control |= 3096 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 3097 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 3098 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); 3099 3100 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3101 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3102 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 3103 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3104 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); 3105 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3106 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); 3107 3108 /* set the wb address wether it's enabled or not */ 3109 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3110 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; 3111 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = 3112 upper_32_bits(wb_gpu_addr) & 0xffff; 3113 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3114 mqd->queue_state.cp_hqd_pq_rptr_report_addr); 3115 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3116 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); 3117 3118 /* enable the doorbell if requested */ 3119 if (use_doorbell) { 3120 mqd->queue_state.cp_hqd_pq_doorbell_control = 3121 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 3122 mqd->queue_state.cp_hqd_pq_doorbell_control &= 3123 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 3124 mqd->queue_state.cp_hqd_pq_doorbell_control |= 3125 (ring->doorbell_index << 3126 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 3127 mqd->queue_state.cp_hqd_pq_doorbell_control |= 3128 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3129 mqd->queue_state.cp_hqd_pq_doorbell_control &= 3130 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 3131 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 3132 3133 } else { 3134 mqd->queue_state.cp_hqd_pq_doorbell_control = 0; 3135 } 3136 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 3137 mqd->queue_state.cp_hqd_pq_doorbell_control); 3138 3139 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3140 ring->wptr = 0; 3141 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; 3142 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 3143 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3144 3145 /* set the vmid for the queue */ 3146 mqd->queue_state.cp_hqd_vmid = 0; 3147 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); 3148 3149 /* activate the queue */ 3150 mqd->queue_state.cp_hqd_active = 1; 3151 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 3152 3153 cik_srbm_select(adev, 0, 0, 0, 0); 3154 mutex_unlock(&adev->srbm_mutex); 3155 3156 amdgpu_bo_kunmap(ring->mqd_obj); 3157 amdgpu_bo_unreserve(ring->mqd_obj); 3158 3159 ring->ready = true; 3160 } 3161 3162 gfx_v7_0_cp_compute_enable(adev, true); 3163 3164 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3165 ring = &adev->gfx.compute_ring[i]; 3166 3167 r = amdgpu_ring_test_ring(ring); 3168 if (r) 3169 ring->ready = false; 3170 } 3171 3172 return 0; 3173 } 3174 3175 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3176 { 3177 gfx_v7_0_cp_gfx_enable(adev, enable); 3178 gfx_v7_0_cp_compute_enable(adev, enable); 3179 } 3180 3181 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3182 { 3183 int r; 3184 3185 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3186 if (r) 3187 return r; 3188 r = gfx_v7_0_cp_compute_load_microcode(adev); 3189 if (r) 3190 return r; 3191 3192 return 0; 3193 } 3194 3195 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3196 bool enable) 3197 { 3198 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3199 3200 if (enable) 3201 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3202 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3203 else 3204 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3205 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3206 WREG32(mmCP_INT_CNTL_RING0, tmp); 3207 } 3208 3209 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3210 { 3211 int r; 3212 3213 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3214 3215 r = gfx_v7_0_cp_load_microcode(adev); 3216 if (r) 3217 return r; 3218 3219 r = gfx_v7_0_cp_gfx_resume(adev); 3220 if (r) 3221 return r; 3222 r = gfx_v7_0_cp_compute_resume(adev); 3223 if (r) 3224 return r; 3225 3226 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3227 3228 return 0; 3229 } 3230 3231 /** 3232 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3233 * 3234 * @ring: the ring to emmit the commands to 3235 * 3236 * Sync the command pipeline with the PFP. E.g. wait for everything 3237 * to be completed. 3238 */ 3239 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3240 { 3241 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3242 uint32_t seq = ring->fence_drv.sync_seq; 3243 uint64_t addr = ring->fence_drv.gpu_addr; 3244 3245 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3246 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3247 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3248 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3249 amdgpu_ring_write(ring, addr & 0xfffffffc); 3250 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3251 amdgpu_ring_write(ring, seq); 3252 amdgpu_ring_write(ring, 0xffffffff); 3253 amdgpu_ring_write(ring, 4); /* poll interval */ 3254 3255 if (usepfp) { 3256 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3257 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3258 amdgpu_ring_write(ring, 0); 3259 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3260 amdgpu_ring_write(ring, 0); 3261 } 3262 } 3263 3264 /* 3265 * vm 3266 * VMID 0 is the physical GPU addresses as used by the kernel. 3267 * VMIDs 1-15 are used for userspace clients and are handled 3268 * by the amdgpu vm/hsa code. 3269 */ 3270 /** 3271 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3272 * 3273 * @adev: amdgpu_device pointer 3274 * 3275 * Update the page table base and flush the VM TLB 3276 * using the CP (CIK). 3277 */ 3278 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3279 unsigned vm_id, uint64_t pd_addr) 3280 { 3281 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3282 3283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3284 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3285 WRITE_DATA_DST_SEL(0))); 3286 if (vm_id < 8) { 3287 amdgpu_ring_write(ring, 3288 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3289 } else { 3290 amdgpu_ring_write(ring, 3291 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3292 } 3293 amdgpu_ring_write(ring, 0); 3294 amdgpu_ring_write(ring, pd_addr >> 12); 3295 3296 /* bits 0-15 are the VM contexts0-15 */ 3297 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3298 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3299 WRITE_DATA_DST_SEL(0))); 3300 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3301 amdgpu_ring_write(ring, 0); 3302 amdgpu_ring_write(ring, 1 << vm_id); 3303 3304 /* wait for the invalidate to complete */ 3305 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3306 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3307 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3308 WAIT_REG_MEM_ENGINE(0))); /* me */ 3309 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3310 amdgpu_ring_write(ring, 0); 3311 amdgpu_ring_write(ring, 0); /* ref */ 3312 amdgpu_ring_write(ring, 0); /* mask */ 3313 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3314 3315 /* compute doesn't have PFP */ 3316 if (usepfp) { 3317 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3318 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3319 amdgpu_ring_write(ring, 0x0); 3320 3321 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3322 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3323 amdgpu_ring_write(ring, 0); 3324 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3325 amdgpu_ring_write(ring, 0); 3326 } 3327 } 3328 3329 /* 3330 * RLC 3331 * The RLC is a multi-purpose microengine that handles a 3332 * variety of functions. 3333 */ 3334 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) 3335 { 3336 int r; 3337 3338 /* save restore block */ 3339 if (adev->gfx.rlc.save_restore_obj) { 3340 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3341 if (unlikely(r != 0)) 3342 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); 3343 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); 3344 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3345 3346 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); 3347 adev->gfx.rlc.save_restore_obj = NULL; 3348 } 3349 3350 /* clear state block */ 3351 if (adev->gfx.rlc.clear_state_obj) { 3352 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3353 if (unlikely(r != 0)) 3354 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); 3355 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 3356 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3357 3358 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 3359 adev->gfx.rlc.clear_state_obj = NULL; 3360 } 3361 3362 /* clear state block */ 3363 if (adev->gfx.rlc.cp_table_obj) { 3364 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3365 if (unlikely(r != 0)) 3366 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3367 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); 3368 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3369 3370 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); 3371 adev->gfx.rlc.cp_table_obj = NULL; 3372 } 3373 } 3374 3375 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3376 { 3377 const u32 *src_ptr; 3378 volatile u32 *dst_ptr; 3379 u32 dws, i; 3380 const struct cs_section_def *cs_data; 3381 int r; 3382 3383 /* allocate rlc buffers */ 3384 if (adev->flags & AMD_IS_APU) { 3385 if (adev->asic_type == CHIP_KAVERI) { 3386 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3387 adev->gfx.rlc.reg_list_size = 3388 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3389 } else { 3390 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3391 adev->gfx.rlc.reg_list_size = 3392 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3393 } 3394 } 3395 adev->gfx.rlc.cs_data = ci_cs_data; 3396 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3397 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3398 3399 src_ptr = adev->gfx.rlc.reg_list; 3400 dws = adev->gfx.rlc.reg_list_size; 3401 dws += (5 * 16) + 48 + 48 + 64; 3402 3403 cs_data = adev->gfx.rlc.cs_data; 3404 3405 if (src_ptr) { 3406 /* save restore block */ 3407 if (adev->gfx.rlc.save_restore_obj == NULL) { 3408 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3409 AMDGPU_GEM_DOMAIN_VRAM, 3410 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3411 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3412 NULL, NULL, 3413 &adev->gfx.rlc.save_restore_obj); 3414 if (r) { 3415 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); 3416 return r; 3417 } 3418 } 3419 3420 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3421 if (unlikely(r != 0)) { 3422 gfx_v7_0_rlc_fini(adev); 3423 return r; 3424 } 3425 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, 3426 &adev->gfx.rlc.save_restore_gpu_addr); 3427 if (r) { 3428 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3429 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); 3430 gfx_v7_0_rlc_fini(adev); 3431 return r; 3432 } 3433 3434 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); 3435 if (r) { 3436 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); 3437 gfx_v7_0_rlc_fini(adev); 3438 return r; 3439 } 3440 /* write the sr buffer */ 3441 dst_ptr = adev->gfx.rlc.sr_ptr; 3442 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3443 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 3444 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 3445 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3446 } 3447 3448 if (cs_data) { 3449 /* clear state block */ 3450 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); 3451 3452 if (adev->gfx.rlc.clear_state_obj == NULL) { 3453 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3454 AMDGPU_GEM_DOMAIN_VRAM, 3455 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3456 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3457 NULL, NULL, 3458 &adev->gfx.rlc.clear_state_obj); 3459 if (r) { 3460 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 3461 gfx_v7_0_rlc_fini(adev); 3462 return r; 3463 } 3464 } 3465 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3466 if (unlikely(r != 0)) { 3467 gfx_v7_0_rlc_fini(adev); 3468 return r; 3469 } 3470 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, 3471 &adev->gfx.rlc.clear_state_gpu_addr); 3472 if (r) { 3473 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3474 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); 3475 gfx_v7_0_rlc_fini(adev); 3476 return r; 3477 } 3478 3479 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); 3480 if (r) { 3481 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); 3482 gfx_v7_0_rlc_fini(adev); 3483 return r; 3484 } 3485 /* set up the cs buffer */ 3486 dst_ptr = adev->gfx.rlc.cs_ptr; 3487 gfx_v7_0_get_csb_buffer(adev, dst_ptr); 3488 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 3489 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3490 } 3491 3492 if (adev->gfx.rlc.cp_table_size) { 3493 if (adev->gfx.rlc.cp_table_obj == NULL) { 3494 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, 3495 AMDGPU_GEM_DOMAIN_VRAM, 3496 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 3497 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 3498 NULL, NULL, 3499 &adev->gfx.rlc.cp_table_obj); 3500 if (r) { 3501 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 3502 gfx_v7_0_rlc_fini(adev); 3503 return r; 3504 } 3505 } 3506 3507 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3508 if (unlikely(r != 0)) { 3509 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3510 gfx_v7_0_rlc_fini(adev); 3511 return r; 3512 } 3513 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, 3514 &adev->gfx.rlc.cp_table_gpu_addr); 3515 if (r) { 3516 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3517 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); 3518 gfx_v7_0_rlc_fini(adev); 3519 return r; 3520 } 3521 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); 3522 if (r) { 3523 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); 3524 gfx_v7_0_rlc_fini(adev); 3525 return r; 3526 } 3527 3528 gfx_v7_0_init_cp_pg_table(adev); 3529 3530 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 3531 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3532 3533 } 3534 3535 return 0; 3536 } 3537 3538 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3539 { 3540 u32 tmp; 3541 3542 tmp = RREG32(mmRLC_LB_CNTL); 3543 if (enable) 3544 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3545 else 3546 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3547 WREG32(mmRLC_LB_CNTL, tmp); 3548 } 3549 3550 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3551 { 3552 u32 i, j, k; 3553 u32 mask; 3554 3555 mutex_lock(&adev->grbm_idx_mutex); 3556 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3557 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3558 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3559 for (k = 0; k < adev->usec_timeout; k++) { 3560 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3561 break; 3562 udelay(1); 3563 } 3564 } 3565 } 3566 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3567 mutex_unlock(&adev->grbm_idx_mutex); 3568 3569 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3570 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3571 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3572 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3573 for (k = 0; k < adev->usec_timeout; k++) { 3574 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3575 break; 3576 udelay(1); 3577 } 3578 } 3579 3580 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3581 { 3582 u32 tmp; 3583 3584 tmp = RREG32(mmRLC_CNTL); 3585 if (tmp != rlc) 3586 WREG32(mmRLC_CNTL, rlc); 3587 } 3588 3589 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3590 { 3591 u32 data, orig; 3592 3593 orig = data = RREG32(mmRLC_CNTL); 3594 3595 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3596 u32 i; 3597 3598 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3599 WREG32(mmRLC_CNTL, data); 3600 3601 for (i = 0; i < adev->usec_timeout; i++) { 3602 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3603 break; 3604 udelay(1); 3605 } 3606 3607 gfx_v7_0_wait_for_rlc_serdes(adev); 3608 } 3609 3610 return orig; 3611 } 3612 3613 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3614 { 3615 u32 tmp, i, mask; 3616 3617 tmp = 0x1 | (1 << 1); 3618 WREG32(mmRLC_GPR_REG2, tmp); 3619 3620 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3621 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3622 for (i = 0; i < adev->usec_timeout; i++) { 3623 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3624 break; 3625 udelay(1); 3626 } 3627 3628 for (i = 0; i < adev->usec_timeout; i++) { 3629 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3630 break; 3631 udelay(1); 3632 } 3633 } 3634 3635 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3636 { 3637 u32 tmp; 3638 3639 tmp = 0x1 | (0 << 1); 3640 WREG32(mmRLC_GPR_REG2, tmp); 3641 } 3642 3643 /** 3644 * gfx_v7_0_rlc_stop - stop the RLC ME 3645 * 3646 * @adev: amdgpu_device pointer 3647 * 3648 * Halt the RLC ME (MicroEngine) (CIK). 3649 */ 3650 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3651 { 3652 WREG32(mmRLC_CNTL, 0); 3653 3654 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3655 3656 gfx_v7_0_wait_for_rlc_serdes(adev); 3657 } 3658 3659 /** 3660 * gfx_v7_0_rlc_start - start the RLC ME 3661 * 3662 * @adev: amdgpu_device pointer 3663 * 3664 * Unhalt the RLC ME (MicroEngine) (CIK). 3665 */ 3666 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3667 { 3668 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3669 3670 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3671 3672 udelay(50); 3673 } 3674 3675 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3676 { 3677 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3678 3679 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3680 WREG32(mmGRBM_SOFT_RESET, tmp); 3681 udelay(50); 3682 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3683 WREG32(mmGRBM_SOFT_RESET, tmp); 3684 udelay(50); 3685 } 3686 3687 /** 3688 * gfx_v7_0_rlc_resume - setup the RLC hw 3689 * 3690 * @adev: amdgpu_device pointer 3691 * 3692 * Initialize the RLC registers, load the ucode, 3693 * and start the RLC (CIK). 3694 * Returns 0 for success, -EINVAL if the ucode is not available. 3695 */ 3696 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3697 { 3698 const struct rlc_firmware_header_v1_0 *hdr; 3699 const __le32 *fw_data; 3700 unsigned i, fw_size; 3701 u32 tmp; 3702 3703 if (!adev->gfx.rlc_fw) 3704 return -EINVAL; 3705 3706 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3707 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3708 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3709 adev->gfx.rlc_feature_version = le32_to_cpu( 3710 hdr->ucode_feature_version); 3711 3712 gfx_v7_0_rlc_stop(adev); 3713 3714 /* disable CG */ 3715 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3716 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3717 3718 gfx_v7_0_rlc_reset(adev); 3719 3720 gfx_v7_0_init_pg(adev); 3721 3722 WREG32(mmRLC_LB_CNTR_INIT, 0); 3723 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3724 3725 mutex_lock(&adev->grbm_idx_mutex); 3726 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3727 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3728 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3729 WREG32(mmRLC_LB_CNTL, 0x80000004); 3730 mutex_unlock(&adev->grbm_idx_mutex); 3731 3732 WREG32(mmRLC_MC_CNTL, 0); 3733 WREG32(mmRLC_UCODE_CNTL, 0); 3734 3735 fw_data = (const __le32 *) 3736 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3737 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3738 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3739 for (i = 0; i < fw_size; i++) 3740 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3741 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3742 3743 /* XXX - find out what chips support lbpw */ 3744 gfx_v7_0_enable_lbpw(adev, false); 3745 3746 if (adev->asic_type == CHIP_BONAIRE) 3747 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3748 3749 gfx_v7_0_rlc_start(adev); 3750 3751 return 0; 3752 } 3753 3754 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3755 { 3756 u32 data, orig, tmp, tmp2; 3757 3758 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3759 3760 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3761 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3762 3763 tmp = gfx_v7_0_halt_rlc(adev); 3764 3765 mutex_lock(&adev->grbm_idx_mutex); 3766 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3767 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3768 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3769 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3770 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3771 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3772 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3773 mutex_unlock(&adev->grbm_idx_mutex); 3774 3775 gfx_v7_0_update_rlc(adev, tmp); 3776 3777 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3778 } else { 3779 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3780 3781 RREG32(mmCB_CGTT_SCLK_CTRL); 3782 RREG32(mmCB_CGTT_SCLK_CTRL); 3783 RREG32(mmCB_CGTT_SCLK_CTRL); 3784 RREG32(mmCB_CGTT_SCLK_CTRL); 3785 3786 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3787 } 3788 3789 if (orig != data) 3790 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3791 3792 } 3793 3794 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3795 { 3796 u32 data, orig, tmp = 0; 3797 3798 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3799 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3800 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3801 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3802 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3803 if (orig != data) 3804 WREG32(mmCP_MEM_SLP_CNTL, data); 3805 } 3806 } 3807 3808 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3809 data |= 0x00000001; 3810 data &= 0xfffffffd; 3811 if (orig != data) 3812 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3813 3814 tmp = gfx_v7_0_halt_rlc(adev); 3815 3816 mutex_lock(&adev->grbm_idx_mutex); 3817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3818 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3819 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3820 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3821 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3822 WREG32(mmRLC_SERDES_WR_CTRL, data); 3823 mutex_unlock(&adev->grbm_idx_mutex); 3824 3825 gfx_v7_0_update_rlc(adev, tmp); 3826 3827 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3828 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3829 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3830 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3831 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3832 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3833 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3834 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3835 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3836 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3837 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3838 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3839 if (orig != data) 3840 WREG32(mmCGTS_SM_CTRL_REG, data); 3841 } 3842 } else { 3843 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3844 data |= 0x00000003; 3845 if (orig != data) 3846 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3847 3848 data = RREG32(mmRLC_MEM_SLP_CNTL); 3849 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3850 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3851 WREG32(mmRLC_MEM_SLP_CNTL, data); 3852 } 3853 3854 data = RREG32(mmCP_MEM_SLP_CNTL); 3855 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3856 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3857 WREG32(mmCP_MEM_SLP_CNTL, data); 3858 } 3859 3860 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3861 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3862 if (orig != data) 3863 WREG32(mmCGTS_SM_CTRL_REG, data); 3864 3865 tmp = gfx_v7_0_halt_rlc(adev); 3866 3867 mutex_lock(&adev->grbm_idx_mutex); 3868 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3869 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3870 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3871 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3872 WREG32(mmRLC_SERDES_WR_CTRL, data); 3873 mutex_unlock(&adev->grbm_idx_mutex); 3874 3875 gfx_v7_0_update_rlc(adev, tmp); 3876 } 3877 } 3878 3879 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3880 bool enable) 3881 { 3882 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3883 /* order matters! */ 3884 if (enable) { 3885 gfx_v7_0_enable_mgcg(adev, true); 3886 gfx_v7_0_enable_cgcg(adev, true); 3887 } else { 3888 gfx_v7_0_enable_cgcg(adev, false); 3889 gfx_v7_0_enable_mgcg(adev, false); 3890 } 3891 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3892 } 3893 3894 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3895 bool enable) 3896 { 3897 u32 data, orig; 3898 3899 orig = data = RREG32(mmRLC_PG_CNTL); 3900 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3901 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3902 else 3903 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3904 if (orig != data) 3905 WREG32(mmRLC_PG_CNTL, data); 3906 } 3907 3908 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3909 bool enable) 3910 { 3911 u32 data, orig; 3912 3913 orig = data = RREG32(mmRLC_PG_CNTL); 3914 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3915 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3916 else 3917 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3918 if (orig != data) 3919 WREG32(mmRLC_PG_CNTL, data); 3920 } 3921 3922 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3923 { 3924 u32 data, orig; 3925 3926 orig = data = RREG32(mmRLC_PG_CNTL); 3927 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3928 data &= ~0x8000; 3929 else 3930 data |= 0x8000; 3931 if (orig != data) 3932 WREG32(mmRLC_PG_CNTL, data); 3933 } 3934 3935 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3936 { 3937 u32 data, orig; 3938 3939 orig = data = RREG32(mmRLC_PG_CNTL); 3940 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3941 data &= ~0x2000; 3942 else 3943 data |= 0x2000; 3944 if (orig != data) 3945 WREG32(mmRLC_PG_CNTL, data); 3946 } 3947 3948 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) 3949 { 3950 const __le32 *fw_data; 3951 volatile u32 *dst_ptr; 3952 int me, i, max_me = 4; 3953 u32 bo_offset = 0; 3954 u32 table_offset, table_size; 3955 3956 if (adev->asic_type == CHIP_KAVERI) 3957 max_me = 5; 3958 3959 if (adev->gfx.rlc.cp_table_ptr == NULL) 3960 return; 3961 3962 /* write the cp table buffer */ 3963 dst_ptr = adev->gfx.rlc.cp_table_ptr; 3964 for (me = 0; me < max_me; me++) { 3965 if (me == 0) { 3966 const struct gfx_firmware_header_v1_0 *hdr = 3967 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3968 fw_data = (const __le32 *) 3969 (adev->gfx.ce_fw->data + 3970 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3971 table_offset = le32_to_cpu(hdr->jt_offset); 3972 table_size = le32_to_cpu(hdr->jt_size); 3973 } else if (me == 1) { 3974 const struct gfx_firmware_header_v1_0 *hdr = 3975 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3976 fw_data = (const __le32 *) 3977 (adev->gfx.pfp_fw->data + 3978 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3979 table_offset = le32_to_cpu(hdr->jt_offset); 3980 table_size = le32_to_cpu(hdr->jt_size); 3981 } else if (me == 2) { 3982 const struct gfx_firmware_header_v1_0 *hdr = 3983 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3984 fw_data = (const __le32 *) 3985 (adev->gfx.me_fw->data + 3986 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3987 table_offset = le32_to_cpu(hdr->jt_offset); 3988 table_size = le32_to_cpu(hdr->jt_size); 3989 } else if (me == 3) { 3990 const struct gfx_firmware_header_v1_0 *hdr = 3991 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3992 fw_data = (const __le32 *) 3993 (adev->gfx.mec_fw->data + 3994 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3995 table_offset = le32_to_cpu(hdr->jt_offset); 3996 table_size = le32_to_cpu(hdr->jt_size); 3997 } else { 3998 const struct gfx_firmware_header_v1_0 *hdr = 3999 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 4000 fw_data = (const __le32 *) 4001 (adev->gfx.mec2_fw->data + 4002 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 4003 table_offset = le32_to_cpu(hdr->jt_offset); 4004 table_size = le32_to_cpu(hdr->jt_size); 4005 } 4006 4007 for (i = 0; i < table_size; i ++) { 4008 dst_ptr[bo_offset + i] = 4009 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 4010 } 4011 4012 bo_offset += table_size; 4013 } 4014 } 4015 4016 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 4017 bool enable) 4018 { 4019 u32 data, orig; 4020 4021 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 4022 orig = data = RREG32(mmRLC_PG_CNTL); 4023 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 4024 if (orig != data) 4025 WREG32(mmRLC_PG_CNTL, data); 4026 4027 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 4028 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 4029 if (orig != data) 4030 WREG32(mmRLC_AUTO_PG_CTRL, data); 4031 } else { 4032 orig = data = RREG32(mmRLC_PG_CNTL); 4033 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 4034 if (orig != data) 4035 WREG32(mmRLC_PG_CNTL, data); 4036 4037 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 4038 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 4039 if (orig != data) 4040 WREG32(mmRLC_AUTO_PG_CTRL, data); 4041 4042 data = RREG32(mmDB_RENDER_CONTROL); 4043 } 4044 } 4045 4046 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4047 u32 bitmap) 4048 { 4049 u32 data; 4050 4051 if (!bitmap) 4052 return; 4053 4054 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4055 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4056 4057 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 4058 } 4059 4060 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4061 { 4062 u32 data, mask; 4063 4064 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 4065 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 4066 4067 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4068 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4069 4070 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 4071 4072 return (~data) & mask; 4073 } 4074 4075 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 4076 { 4077 u32 tmp; 4078 4079 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 4080 4081 tmp = RREG32(mmRLC_MAX_PG_CU); 4082 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 4083 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 4084 WREG32(mmRLC_MAX_PG_CU, tmp); 4085 } 4086 4087 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 4088 bool enable) 4089 { 4090 u32 data, orig; 4091 4092 orig = data = RREG32(mmRLC_PG_CNTL); 4093 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 4094 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4095 else 4096 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 4097 if (orig != data) 4098 WREG32(mmRLC_PG_CNTL, data); 4099 } 4100 4101 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 4102 bool enable) 4103 { 4104 u32 data, orig; 4105 4106 orig = data = RREG32(mmRLC_PG_CNTL); 4107 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 4108 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4109 else 4110 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 4111 if (orig != data) 4112 WREG32(mmRLC_PG_CNTL, data); 4113 } 4114 4115 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 4116 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 4117 4118 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 4119 { 4120 u32 data, orig; 4121 u32 i; 4122 4123 if (adev->gfx.rlc.cs_data) { 4124 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 4125 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 4126 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 4127 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 4128 } else { 4129 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 4130 for (i = 0; i < 3; i++) 4131 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 4132 } 4133 if (adev->gfx.rlc.reg_list) { 4134 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 4135 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 4136 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 4137 } 4138 4139 orig = data = RREG32(mmRLC_PG_CNTL); 4140 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 4141 if (orig != data) 4142 WREG32(mmRLC_PG_CNTL, data); 4143 4144 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 4145 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 4146 4147 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 4148 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 4149 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4150 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 4151 4152 data = 0x10101010; 4153 WREG32(mmRLC_PG_DELAY, data); 4154 4155 data = RREG32(mmRLC_PG_DELAY_2); 4156 data &= ~0xff; 4157 data |= 0x3; 4158 WREG32(mmRLC_PG_DELAY_2, data); 4159 4160 data = RREG32(mmRLC_AUTO_PG_CTRL); 4161 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 4162 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 4163 WREG32(mmRLC_AUTO_PG_CTRL, data); 4164 4165 } 4166 4167 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 4168 { 4169 gfx_v7_0_enable_gfx_cgpg(adev, enable); 4170 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 4171 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 4172 } 4173 4174 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 4175 { 4176 u32 count = 0; 4177 const struct cs_section_def *sect = NULL; 4178 const struct cs_extent_def *ext = NULL; 4179 4180 if (adev->gfx.rlc.cs_data == NULL) 4181 return 0; 4182 4183 /* begin clear state */ 4184 count += 2; 4185 /* context control state */ 4186 count += 3; 4187 4188 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4189 for (ext = sect->section; ext->extent != NULL; ++ext) { 4190 if (sect->id == SECT_CONTEXT) 4191 count += 2 + ext->reg_count; 4192 else 4193 return 0; 4194 } 4195 } 4196 /* pa_sc_raster_config/pa_sc_raster_config1 */ 4197 count += 4; 4198 /* end clear state */ 4199 count += 2; 4200 /* clear state */ 4201 count += 2; 4202 4203 return count; 4204 } 4205 4206 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 4207 volatile u32 *buffer) 4208 { 4209 u32 count = 0, i; 4210 const struct cs_section_def *sect = NULL; 4211 const struct cs_extent_def *ext = NULL; 4212 4213 if (adev->gfx.rlc.cs_data == NULL) 4214 return; 4215 if (buffer == NULL) 4216 return; 4217 4218 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4219 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4220 4221 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4222 buffer[count++] = cpu_to_le32(0x80000000); 4223 buffer[count++] = cpu_to_le32(0x80000000); 4224 4225 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4226 for (ext = sect->section; ext->extent != NULL; ++ext) { 4227 if (sect->id == SECT_CONTEXT) { 4228 buffer[count++] = 4229 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4230 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4231 for (i = 0; i < ext->reg_count; i++) 4232 buffer[count++] = cpu_to_le32(ext->extent[i]); 4233 } else { 4234 return; 4235 } 4236 } 4237 } 4238 4239 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4240 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4241 switch (adev->asic_type) { 4242 case CHIP_BONAIRE: 4243 buffer[count++] = cpu_to_le32(0x16000012); 4244 buffer[count++] = cpu_to_le32(0x00000000); 4245 break; 4246 case CHIP_KAVERI: 4247 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4248 buffer[count++] = cpu_to_le32(0x00000000); 4249 break; 4250 case CHIP_KABINI: 4251 case CHIP_MULLINS: 4252 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4253 buffer[count++] = cpu_to_le32(0x00000000); 4254 break; 4255 case CHIP_HAWAII: 4256 buffer[count++] = cpu_to_le32(0x3a00161a); 4257 buffer[count++] = cpu_to_le32(0x0000002e); 4258 break; 4259 default: 4260 buffer[count++] = cpu_to_le32(0x00000000); 4261 buffer[count++] = cpu_to_le32(0x00000000); 4262 break; 4263 } 4264 4265 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4266 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4267 4268 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4269 buffer[count++] = cpu_to_le32(0); 4270 } 4271 4272 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4273 { 4274 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4275 AMD_PG_SUPPORT_GFX_SMG | 4276 AMD_PG_SUPPORT_GFX_DMG | 4277 AMD_PG_SUPPORT_CP | 4278 AMD_PG_SUPPORT_GDS | 4279 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4280 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4281 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4282 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4283 gfx_v7_0_init_gfx_cgpg(adev); 4284 gfx_v7_0_enable_cp_pg(adev, true); 4285 gfx_v7_0_enable_gds_pg(adev, true); 4286 } 4287 gfx_v7_0_init_ao_cu_mask(adev); 4288 gfx_v7_0_update_gfx_pg(adev, true); 4289 } 4290 } 4291 4292 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4293 { 4294 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4295 AMD_PG_SUPPORT_GFX_SMG | 4296 AMD_PG_SUPPORT_GFX_DMG | 4297 AMD_PG_SUPPORT_CP | 4298 AMD_PG_SUPPORT_GDS | 4299 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4300 gfx_v7_0_update_gfx_pg(adev, false); 4301 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4302 gfx_v7_0_enable_cp_pg(adev, false); 4303 gfx_v7_0_enable_gds_pg(adev, false); 4304 } 4305 } 4306 } 4307 4308 /** 4309 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4310 * 4311 * @adev: amdgpu_device pointer 4312 * 4313 * Fetches a GPU clock counter snapshot (SI). 4314 * Returns the 64 bit clock counter snapshot. 4315 */ 4316 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4317 { 4318 uint64_t clock; 4319 4320 mutex_lock(&adev->gfx.gpu_clock_mutex); 4321 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4322 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4323 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4324 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4325 return clock; 4326 } 4327 4328 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4329 uint32_t vmid, 4330 uint32_t gds_base, uint32_t gds_size, 4331 uint32_t gws_base, uint32_t gws_size, 4332 uint32_t oa_base, uint32_t oa_size) 4333 { 4334 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 4335 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 4336 4337 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 4338 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 4339 4340 oa_base = oa_base >> AMDGPU_OA_SHIFT; 4341 oa_size = oa_size >> AMDGPU_OA_SHIFT; 4342 4343 /* GDS Base */ 4344 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4345 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4346 WRITE_DATA_DST_SEL(0))); 4347 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4348 amdgpu_ring_write(ring, 0); 4349 amdgpu_ring_write(ring, gds_base); 4350 4351 /* GDS Size */ 4352 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4353 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4354 WRITE_DATA_DST_SEL(0))); 4355 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4356 amdgpu_ring_write(ring, 0); 4357 amdgpu_ring_write(ring, gds_size); 4358 4359 /* GWS */ 4360 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4361 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4362 WRITE_DATA_DST_SEL(0))); 4363 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4364 amdgpu_ring_write(ring, 0); 4365 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4366 4367 /* OA */ 4368 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4369 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4370 WRITE_DATA_DST_SEL(0))); 4371 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4372 amdgpu_ring_write(ring, 0); 4373 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4374 } 4375 4376 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4377 { 4378 WREG32(mmSQ_IND_INDEX, 4379 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4380 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4381 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4382 (SQ_IND_INDEX__FORCE_READ_MASK)); 4383 return RREG32(mmSQ_IND_DATA); 4384 } 4385 4386 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4387 uint32_t wave, uint32_t thread, 4388 uint32_t regno, uint32_t num, uint32_t *out) 4389 { 4390 WREG32(mmSQ_IND_INDEX, 4391 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4392 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4393 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4394 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4395 (SQ_IND_INDEX__FORCE_READ_MASK) | 4396 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4397 while (num--) 4398 *(out++) = RREG32(mmSQ_IND_DATA); 4399 } 4400 4401 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4402 { 4403 /* type 0 wave data */ 4404 dst[(*no_fields)++] = 0; 4405 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4406 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4407 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4408 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4409 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4410 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4411 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4412 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4413 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4414 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4415 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4416 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4417 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4418 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4420 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4421 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4422 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4423 } 4424 4425 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4426 uint32_t wave, uint32_t start, 4427 uint32_t size, uint32_t *dst) 4428 { 4429 wave_read_regs( 4430 adev, simd, wave, 0, 4431 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4432 } 4433 4434 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4435 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4436 .select_se_sh = &gfx_v7_0_select_se_sh, 4437 .read_wave_data = &gfx_v7_0_read_wave_data, 4438 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4439 }; 4440 4441 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4442 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode, 4443 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode 4444 }; 4445 4446 static int gfx_v7_0_early_init(void *handle) 4447 { 4448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4449 4450 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4451 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; 4452 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4453 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4454 gfx_v7_0_set_ring_funcs(adev); 4455 gfx_v7_0_set_irq_funcs(adev); 4456 gfx_v7_0_set_gds_init(adev); 4457 4458 return 0; 4459 } 4460 4461 static int gfx_v7_0_late_init(void *handle) 4462 { 4463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4464 int r; 4465 4466 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4467 if (r) 4468 return r; 4469 4470 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4471 if (r) 4472 return r; 4473 4474 return 0; 4475 } 4476 4477 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4478 { 4479 u32 gb_addr_config; 4480 u32 mc_shared_chmap, mc_arb_ramcfg; 4481 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4482 u32 tmp; 4483 4484 switch (adev->asic_type) { 4485 case CHIP_BONAIRE: 4486 adev->gfx.config.max_shader_engines = 2; 4487 adev->gfx.config.max_tile_pipes = 4; 4488 adev->gfx.config.max_cu_per_sh = 7; 4489 adev->gfx.config.max_sh_per_se = 1; 4490 adev->gfx.config.max_backends_per_se = 2; 4491 adev->gfx.config.max_texture_channel_caches = 4; 4492 adev->gfx.config.max_gprs = 256; 4493 adev->gfx.config.max_gs_threads = 32; 4494 adev->gfx.config.max_hw_contexts = 8; 4495 4496 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4497 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4498 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4499 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4500 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4501 break; 4502 case CHIP_HAWAII: 4503 adev->gfx.config.max_shader_engines = 4; 4504 adev->gfx.config.max_tile_pipes = 16; 4505 adev->gfx.config.max_cu_per_sh = 11; 4506 adev->gfx.config.max_sh_per_se = 1; 4507 adev->gfx.config.max_backends_per_se = 4; 4508 adev->gfx.config.max_texture_channel_caches = 16; 4509 adev->gfx.config.max_gprs = 256; 4510 adev->gfx.config.max_gs_threads = 32; 4511 adev->gfx.config.max_hw_contexts = 8; 4512 4513 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4514 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4515 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4516 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4517 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4518 break; 4519 case CHIP_KAVERI: 4520 adev->gfx.config.max_shader_engines = 1; 4521 adev->gfx.config.max_tile_pipes = 4; 4522 if ((adev->pdev->device == 0x1304) || 4523 (adev->pdev->device == 0x1305) || 4524 (adev->pdev->device == 0x130C) || 4525 (adev->pdev->device == 0x130F) || 4526 (adev->pdev->device == 0x1310) || 4527 (adev->pdev->device == 0x1311) || 4528 (adev->pdev->device == 0x131C)) { 4529 adev->gfx.config.max_cu_per_sh = 8; 4530 adev->gfx.config.max_backends_per_se = 2; 4531 } else if ((adev->pdev->device == 0x1309) || 4532 (adev->pdev->device == 0x130A) || 4533 (adev->pdev->device == 0x130D) || 4534 (adev->pdev->device == 0x1313) || 4535 (adev->pdev->device == 0x131D)) { 4536 adev->gfx.config.max_cu_per_sh = 6; 4537 adev->gfx.config.max_backends_per_se = 2; 4538 } else if ((adev->pdev->device == 0x1306) || 4539 (adev->pdev->device == 0x1307) || 4540 (adev->pdev->device == 0x130B) || 4541 (adev->pdev->device == 0x130E) || 4542 (adev->pdev->device == 0x1315) || 4543 (adev->pdev->device == 0x131B)) { 4544 adev->gfx.config.max_cu_per_sh = 4; 4545 adev->gfx.config.max_backends_per_se = 1; 4546 } else { 4547 adev->gfx.config.max_cu_per_sh = 3; 4548 adev->gfx.config.max_backends_per_se = 1; 4549 } 4550 adev->gfx.config.max_sh_per_se = 1; 4551 adev->gfx.config.max_texture_channel_caches = 4; 4552 adev->gfx.config.max_gprs = 256; 4553 adev->gfx.config.max_gs_threads = 16; 4554 adev->gfx.config.max_hw_contexts = 8; 4555 4556 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4557 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4558 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4559 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4560 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4561 break; 4562 case CHIP_KABINI: 4563 case CHIP_MULLINS: 4564 default: 4565 adev->gfx.config.max_shader_engines = 1; 4566 adev->gfx.config.max_tile_pipes = 2; 4567 adev->gfx.config.max_cu_per_sh = 2; 4568 adev->gfx.config.max_sh_per_se = 1; 4569 adev->gfx.config.max_backends_per_se = 1; 4570 adev->gfx.config.max_texture_channel_caches = 2; 4571 adev->gfx.config.max_gprs = 256; 4572 adev->gfx.config.max_gs_threads = 16; 4573 adev->gfx.config.max_hw_contexts = 8; 4574 4575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4579 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4580 break; 4581 } 4582 4583 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 4584 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4585 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4586 4587 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4588 adev->gfx.config.mem_max_burst_length_bytes = 256; 4589 if (adev->flags & AMD_IS_APU) { 4590 /* Get memory bank mapping mode. */ 4591 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4592 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4593 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4594 4595 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4596 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4597 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4598 4599 /* Validate settings in case only one DIMM installed. */ 4600 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4601 dimm00_addr_map = 0; 4602 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4603 dimm01_addr_map = 0; 4604 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4605 dimm10_addr_map = 0; 4606 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4607 dimm11_addr_map = 0; 4608 4609 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4610 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4611 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4612 adev->gfx.config.mem_row_size_in_kb = 2; 4613 else 4614 adev->gfx.config.mem_row_size_in_kb = 1; 4615 } else { 4616 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4617 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4618 if (adev->gfx.config.mem_row_size_in_kb > 4) 4619 adev->gfx.config.mem_row_size_in_kb = 4; 4620 } 4621 /* XXX use MC settings? */ 4622 adev->gfx.config.shader_engine_tile_size = 32; 4623 adev->gfx.config.num_gpus = 1; 4624 adev->gfx.config.multi_gpu_tile_size = 64; 4625 4626 /* fix up row size */ 4627 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4628 switch (adev->gfx.config.mem_row_size_in_kb) { 4629 case 1: 4630 default: 4631 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4632 break; 4633 case 2: 4634 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4635 break; 4636 case 4: 4637 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4638 break; 4639 } 4640 adev->gfx.config.gb_addr_config = gb_addr_config; 4641 } 4642 4643 static int gfx_v7_0_sw_init(void *handle) 4644 { 4645 struct amdgpu_ring *ring; 4646 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4647 int i, r; 4648 4649 /* EOP Event */ 4650 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 4651 if (r) 4652 return r; 4653 4654 /* Privileged reg */ 4655 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 4656 if (r) 4657 return r; 4658 4659 /* Privileged inst */ 4660 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 4661 if (r) 4662 return r; 4663 4664 gfx_v7_0_scratch_init(adev); 4665 4666 r = gfx_v7_0_init_microcode(adev); 4667 if (r) { 4668 DRM_ERROR("Failed to load gfx firmware!\n"); 4669 return r; 4670 } 4671 4672 r = gfx_v7_0_rlc_init(adev); 4673 if (r) { 4674 DRM_ERROR("Failed to init rlc BOs!\n"); 4675 return r; 4676 } 4677 4678 /* allocate mec buffers */ 4679 r = gfx_v7_0_mec_init(adev); 4680 if (r) { 4681 DRM_ERROR("Failed to init MEC BOs!\n"); 4682 return r; 4683 } 4684 4685 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4686 ring = &adev->gfx.gfx_ring[i]; 4687 ring->ring_obj = NULL; 4688 sprintf(ring->name, "gfx"); 4689 r = amdgpu_ring_init(adev, ring, 1024, 4690 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 4691 if (r) 4692 return r; 4693 } 4694 4695 /* set up the compute queues */ 4696 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4697 unsigned irq_type; 4698 4699 /* max 32 queues per MEC */ 4700 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 4701 DRM_ERROR("Too many (%d) compute rings!\n", i); 4702 break; 4703 } 4704 ring = &adev->gfx.compute_ring[i]; 4705 ring->ring_obj = NULL; 4706 ring->use_doorbell = true; 4707 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; 4708 ring->me = 1; /* first MEC */ 4709 ring->pipe = i / 8; 4710 ring->queue = i % 8; 4711 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4712 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 4713 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4714 r = amdgpu_ring_init(adev, ring, 1024, 4715 &adev->gfx.eop_irq, irq_type); 4716 if (r) 4717 return r; 4718 } 4719 4720 /* reserve GDS, GWS and OA resource for gfx */ 4721 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 4722 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 4723 &adev->gds.gds_gfx_bo, NULL, NULL); 4724 if (r) 4725 return r; 4726 4727 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 4728 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 4729 &adev->gds.gws_gfx_bo, NULL, NULL); 4730 if (r) 4731 return r; 4732 4733 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 4734 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 4735 &adev->gds.oa_gfx_bo, NULL, NULL); 4736 if (r) 4737 return r; 4738 4739 adev->gfx.ce_ram_size = 0x8000; 4740 4741 gfx_v7_0_gpu_early_init(adev); 4742 4743 return r; 4744 } 4745 4746 static int gfx_v7_0_sw_fini(void *handle) 4747 { 4748 int i; 4749 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4750 4751 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 4752 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 4753 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 4754 4755 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4756 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4757 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4758 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4759 4760 gfx_v7_0_cp_compute_fini(adev); 4761 gfx_v7_0_rlc_fini(adev); 4762 gfx_v7_0_mec_fini(adev); 4763 gfx_v7_0_free_microcode(adev); 4764 4765 return 0; 4766 } 4767 4768 static int gfx_v7_0_hw_init(void *handle) 4769 { 4770 int r; 4771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4772 4773 gfx_v7_0_gpu_init(adev); 4774 4775 /* init rlc */ 4776 r = gfx_v7_0_rlc_resume(adev); 4777 if (r) 4778 return r; 4779 4780 r = gfx_v7_0_cp_resume(adev); 4781 if (r) 4782 return r; 4783 4784 return r; 4785 } 4786 4787 static int gfx_v7_0_hw_fini(void *handle) 4788 { 4789 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4790 4791 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4792 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4793 gfx_v7_0_cp_enable(adev, false); 4794 gfx_v7_0_rlc_stop(adev); 4795 gfx_v7_0_fini_pg(adev); 4796 4797 return 0; 4798 } 4799 4800 static int gfx_v7_0_suspend(void *handle) 4801 { 4802 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4803 4804 return gfx_v7_0_hw_fini(adev); 4805 } 4806 4807 static int gfx_v7_0_resume(void *handle) 4808 { 4809 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4810 4811 return gfx_v7_0_hw_init(adev); 4812 } 4813 4814 static bool gfx_v7_0_is_idle(void *handle) 4815 { 4816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4817 4818 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4819 return false; 4820 else 4821 return true; 4822 } 4823 4824 static int gfx_v7_0_wait_for_idle(void *handle) 4825 { 4826 unsigned i; 4827 u32 tmp; 4828 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4829 4830 for (i = 0; i < adev->usec_timeout; i++) { 4831 /* read MC_STATUS */ 4832 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4833 4834 if (!tmp) 4835 return 0; 4836 udelay(1); 4837 } 4838 return -ETIMEDOUT; 4839 } 4840 4841 static int gfx_v7_0_soft_reset(void *handle) 4842 { 4843 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4844 u32 tmp; 4845 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4846 4847 /* GRBM_STATUS */ 4848 tmp = RREG32(mmGRBM_STATUS); 4849 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4850 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4851 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4852 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4853 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4854 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4855 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4856 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4857 4858 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4859 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4860 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4861 } 4862 4863 /* GRBM_STATUS2 */ 4864 tmp = RREG32(mmGRBM_STATUS2); 4865 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4866 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4867 4868 /* SRBM_STATUS */ 4869 tmp = RREG32(mmSRBM_STATUS); 4870 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4871 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4872 4873 if (grbm_soft_reset || srbm_soft_reset) { 4874 /* disable CG/PG */ 4875 gfx_v7_0_fini_pg(adev); 4876 gfx_v7_0_update_cg(adev, false); 4877 4878 /* stop the rlc */ 4879 gfx_v7_0_rlc_stop(adev); 4880 4881 /* Disable GFX parsing/prefetching */ 4882 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4883 4884 /* Disable MEC parsing/prefetching */ 4885 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4886 4887 if (grbm_soft_reset) { 4888 tmp = RREG32(mmGRBM_SOFT_RESET); 4889 tmp |= grbm_soft_reset; 4890 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4891 WREG32(mmGRBM_SOFT_RESET, tmp); 4892 tmp = RREG32(mmGRBM_SOFT_RESET); 4893 4894 udelay(50); 4895 4896 tmp &= ~grbm_soft_reset; 4897 WREG32(mmGRBM_SOFT_RESET, tmp); 4898 tmp = RREG32(mmGRBM_SOFT_RESET); 4899 } 4900 4901 if (srbm_soft_reset) { 4902 tmp = RREG32(mmSRBM_SOFT_RESET); 4903 tmp |= srbm_soft_reset; 4904 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4905 WREG32(mmSRBM_SOFT_RESET, tmp); 4906 tmp = RREG32(mmSRBM_SOFT_RESET); 4907 4908 udelay(50); 4909 4910 tmp &= ~srbm_soft_reset; 4911 WREG32(mmSRBM_SOFT_RESET, tmp); 4912 tmp = RREG32(mmSRBM_SOFT_RESET); 4913 } 4914 /* Wait a little for things to settle down */ 4915 udelay(50); 4916 } 4917 return 0; 4918 } 4919 4920 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4921 enum amdgpu_interrupt_state state) 4922 { 4923 u32 cp_int_cntl; 4924 4925 switch (state) { 4926 case AMDGPU_IRQ_STATE_DISABLE: 4927 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4928 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4929 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4930 break; 4931 case AMDGPU_IRQ_STATE_ENABLE: 4932 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4933 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4934 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4935 break; 4936 default: 4937 break; 4938 } 4939 } 4940 4941 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4942 int me, int pipe, 4943 enum amdgpu_interrupt_state state) 4944 { 4945 u32 mec_int_cntl, mec_int_cntl_reg; 4946 4947 /* 4948 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4949 * handles the setting of interrupts for this specific pipe. All other 4950 * pipes' interrupts are set by amdkfd. 4951 */ 4952 4953 if (me == 1) { 4954 switch (pipe) { 4955 case 0: 4956 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4957 break; 4958 default: 4959 DRM_DEBUG("invalid pipe %d\n", pipe); 4960 return; 4961 } 4962 } else { 4963 DRM_DEBUG("invalid me %d\n", me); 4964 return; 4965 } 4966 4967 switch (state) { 4968 case AMDGPU_IRQ_STATE_DISABLE: 4969 mec_int_cntl = RREG32(mec_int_cntl_reg); 4970 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4971 WREG32(mec_int_cntl_reg, mec_int_cntl); 4972 break; 4973 case AMDGPU_IRQ_STATE_ENABLE: 4974 mec_int_cntl = RREG32(mec_int_cntl_reg); 4975 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4976 WREG32(mec_int_cntl_reg, mec_int_cntl); 4977 break; 4978 default: 4979 break; 4980 } 4981 } 4982 4983 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4984 struct amdgpu_irq_src *src, 4985 unsigned type, 4986 enum amdgpu_interrupt_state state) 4987 { 4988 u32 cp_int_cntl; 4989 4990 switch (state) { 4991 case AMDGPU_IRQ_STATE_DISABLE: 4992 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4993 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4994 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4995 break; 4996 case AMDGPU_IRQ_STATE_ENABLE: 4997 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4998 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4999 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 5000 break; 5001 default: 5002 break; 5003 } 5004 5005 return 0; 5006 } 5007 5008 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5009 struct amdgpu_irq_src *src, 5010 unsigned type, 5011 enum amdgpu_interrupt_state state) 5012 { 5013 u32 cp_int_cntl; 5014 5015 switch (state) { 5016 case AMDGPU_IRQ_STATE_DISABLE: 5017 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 5018 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 5019 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 5020 break; 5021 case AMDGPU_IRQ_STATE_ENABLE: 5022 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 5023 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 5024 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 5025 break; 5026 default: 5027 break; 5028 } 5029 5030 return 0; 5031 } 5032 5033 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5034 struct amdgpu_irq_src *src, 5035 unsigned type, 5036 enum amdgpu_interrupt_state state) 5037 { 5038 switch (type) { 5039 case AMDGPU_CP_IRQ_GFX_EOP: 5040 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 5041 break; 5042 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5043 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5044 break; 5045 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5046 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5047 break; 5048 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5049 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5050 break; 5051 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5052 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5053 break; 5054 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5055 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5056 break; 5057 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5058 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5059 break; 5060 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5061 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5062 break; 5063 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5064 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5065 break; 5066 default: 5067 break; 5068 } 5069 return 0; 5070 } 5071 5072 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 5073 struct amdgpu_irq_src *source, 5074 struct amdgpu_iv_entry *entry) 5075 { 5076 u8 me_id, pipe_id; 5077 struct amdgpu_ring *ring; 5078 int i; 5079 5080 DRM_DEBUG("IH: CP EOP\n"); 5081 me_id = (entry->ring_id & 0x0c) >> 2; 5082 pipe_id = (entry->ring_id & 0x03) >> 0; 5083 switch (me_id) { 5084 case 0: 5085 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5086 break; 5087 case 1: 5088 case 2: 5089 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5090 ring = &adev->gfx.compute_ring[i]; 5091 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 5092 amdgpu_fence_process(ring); 5093 } 5094 break; 5095 } 5096 return 0; 5097 } 5098 5099 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 5100 struct amdgpu_irq_src *source, 5101 struct amdgpu_iv_entry *entry) 5102 { 5103 DRM_ERROR("Illegal register access in command stream\n"); 5104 schedule_work(&adev->reset_work); 5105 return 0; 5106 } 5107 5108 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 5109 struct amdgpu_irq_src *source, 5110 struct amdgpu_iv_entry *entry) 5111 { 5112 DRM_ERROR("Illegal instruction in command stream\n"); 5113 // XXX soft reset the gfx block only 5114 schedule_work(&adev->reset_work); 5115 return 0; 5116 } 5117 5118 static int gfx_v7_0_set_clockgating_state(void *handle, 5119 enum amd_clockgating_state state) 5120 { 5121 bool gate = false; 5122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5123 5124 if (state == AMD_CG_STATE_GATE) 5125 gate = true; 5126 5127 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 5128 /* order matters! */ 5129 if (gate) { 5130 gfx_v7_0_enable_mgcg(adev, true); 5131 gfx_v7_0_enable_cgcg(adev, true); 5132 } else { 5133 gfx_v7_0_enable_cgcg(adev, false); 5134 gfx_v7_0_enable_mgcg(adev, false); 5135 } 5136 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 5137 5138 return 0; 5139 } 5140 5141 static int gfx_v7_0_set_powergating_state(void *handle, 5142 enum amd_powergating_state state) 5143 { 5144 bool gate = false; 5145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5146 5147 if (state == AMD_PG_STATE_GATE) 5148 gate = true; 5149 5150 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 5151 AMD_PG_SUPPORT_GFX_SMG | 5152 AMD_PG_SUPPORT_GFX_DMG | 5153 AMD_PG_SUPPORT_CP | 5154 AMD_PG_SUPPORT_GDS | 5155 AMD_PG_SUPPORT_RLC_SMU_HS)) { 5156 gfx_v7_0_update_gfx_pg(adev, gate); 5157 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 5158 gfx_v7_0_enable_cp_pg(adev, gate); 5159 gfx_v7_0_enable_gds_pg(adev, gate); 5160 } 5161 } 5162 5163 return 0; 5164 } 5165 5166 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5167 .name = "gfx_v7_0", 5168 .early_init = gfx_v7_0_early_init, 5169 .late_init = gfx_v7_0_late_init, 5170 .sw_init = gfx_v7_0_sw_init, 5171 .sw_fini = gfx_v7_0_sw_fini, 5172 .hw_init = gfx_v7_0_hw_init, 5173 .hw_fini = gfx_v7_0_hw_fini, 5174 .suspend = gfx_v7_0_suspend, 5175 .resume = gfx_v7_0_resume, 5176 .is_idle = gfx_v7_0_is_idle, 5177 .wait_for_idle = gfx_v7_0_wait_for_idle, 5178 .soft_reset = gfx_v7_0_soft_reset, 5179 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5180 .set_powergating_state = gfx_v7_0_set_powergating_state, 5181 }; 5182 5183 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5184 .type = AMDGPU_RING_TYPE_GFX, 5185 .align_mask = 0xff, 5186 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5187 .get_rptr = gfx_v7_0_ring_get_rptr, 5188 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5189 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5190 .emit_frame_size = 5191 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5192 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5193 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5194 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5195 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5196 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5197 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 5198 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5199 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5200 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5201 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5202 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5203 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5204 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5205 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5206 .test_ring = gfx_v7_0_ring_test_ring, 5207 .test_ib = gfx_v7_0_ring_test_ib, 5208 .insert_nop = amdgpu_ring_insert_nop, 5209 .pad_ib = amdgpu_ring_generic_pad_ib, 5210 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5211 }; 5212 5213 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5214 .type = AMDGPU_RING_TYPE_COMPUTE, 5215 .align_mask = 0xff, 5216 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5217 .get_rptr = gfx_v7_0_ring_get_rptr, 5218 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5219 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5220 .emit_frame_size = 5221 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5222 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5223 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ 5224 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5225 17 + /* gfx_v7_0_ring_emit_vm_flush */ 5226 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5227 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */ 5228 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5229 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5230 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5231 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5232 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5233 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5234 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5235 .test_ring = gfx_v7_0_ring_test_ring, 5236 .test_ib = gfx_v7_0_ring_test_ib, 5237 .insert_nop = amdgpu_ring_insert_nop, 5238 .pad_ib = amdgpu_ring_generic_pad_ib, 5239 }; 5240 5241 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5242 { 5243 int i; 5244 5245 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5246 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5247 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5248 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5249 } 5250 5251 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5252 .set = gfx_v7_0_set_eop_interrupt_state, 5253 .process = gfx_v7_0_eop_irq, 5254 }; 5255 5256 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5257 .set = gfx_v7_0_set_priv_reg_fault_state, 5258 .process = gfx_v7_0_priv_reg_irq, 5259 }; 5260 5261 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5262 .set = gfx_v7_0_set_priv_inst_fault_state, 5263 .process = gfx_v7_0_priv_inst_irq, 5264 }; 5265 5266 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5267 { 5268 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5269 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5270 5271 adev->gfx.priv_reg_irq.num_types = 1; 5272 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5273 5274 adev->gfx.priv_inst_irq.num_types = 1; 5275 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5276 } 5277 5278 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5279 { 5280 /* init asci gds info */ 5281 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 5282 adev->gds.gws.total_size = 64; 5283 adev->gds.oa.total_size = 16; 5284 5285 if (adev->gds.mem.total_size == 64 * 1024) { 5286 adev->gds.mem.gfx_partition_size = 4096; 5287 adev->gds.mem.cs_partition_size = 4096; 5288 5289 adev->gds.gws.gfx_partition_size = 4; 5290 adev->gds.gws.cs_partition_size = 4; 5291 5292 adev->gds.oa.gfx_partition_size = 4; 5293 adev->gds.oa.cs_partition_size = 1; 5294 } else { 5295 adev->gds.mem.gfx_partition_size = 1024; 5296 adev->gds.mem.cs_partition_size = 1024; 5297 5298 adev->gds.gws.gfx_partition_size = 16; 5299 adev->gds.gws.cs_partition_size = 16; 5300 5301 adev->gds.oa.gfx_partition_size = 4; 5302 adev->gds.oa.cs_partition_size = 4; 5303 } 5304 } 5305 5306 5307 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5308 { 5309 int i, j, k, counter, active_cu_number = 0; 5310 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5311 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5312 unsigned disable_masks[4 * 2]; 5313 5314 memset(cu_info, 0, sizeof(*cu_info)); 5315 5316 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5317 5318 mutex_lock(&adev->grbm_idx_mutex); 5319 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5320 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5321 mask = 1; 5322 ao_bitmap = 0; 5323 counter = 0; 5324 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5325 if (i < 4 && j < 2) 5326 gfx_v7_0_set_user_cu_inactive_bitmap( 5327 adev, disable_masks[i * 2 + j]); 5328 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5329 cu_info->bitmap[i][j] = bitmap; 5330 5331 for (k = 0; k < 16; k ++) { 5332 if (bitmap & mask) { 5333 if (counter < 2) 5334 ao_bitmap |= mask; 5335 counter ++; 5336 } 5337 mask <<= 1; 5338 } 5339 active_cu_number += counter; 5340 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5341 } 5342 } 5343 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5344 mutex_unlock(&adev->grbm_idx_mutex); 5345 5346 cu_info->number = active_cu_number; 5347 cu_info->ao_cu_mask = ao_cu_mask; 5348 } 5349 5350 const struct amdgpu_ip_block_version gfx_v7_0_ip_block = 5351 { 5352 .type = AMD_IP_BLOCK_TYPE_GFX, 5353 .major = 7, 5354 .minor = 0, 5355 .rev = 0, 5356 .funcs = &gfx_v7_0_ip_funcs, 5357 }; 5358 5359 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5360 { 5361 .type = AMD_IP_BLOCK_TYPE_GFX, 5362 .major = 7, 5363 .minor = 1, 5364 .rev = 0, 5365 .funcs = &gfx_v7_0_ip_funcs, 5366 }; 5367 5368 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5369 { 5370 .type = AMD_IP_BLOCK_TYPE_GFX, 5371 .major = 7, 5372 .minor = 2, 5373 .rev = 0, 5374 .funcs = &gfx_v7_0_ip_funcs, 5375 }; 5376 5377 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5378 { 5379 .type = AMD_IP_BLOCK_TYPE_GFX, 5380 .major = 7, 5381 .minor = 3, 5382 .rev = 0, 5383 .funcs = &gfx_v7_0_ip_funcs, 5384 }; 5385