1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_ih.h" 29 #include "amdgpu_gfx.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "cik_structs.h" 33 #include "atom.h" 34 #include "amdgpu_ucode.h" 35 #include "clearstate_ci.h" 36 37 #include "dce/dce_8_0_d.h" 38 #include "dce/dce_8_0_sh_mask.h" 39 40 #include "bif/bif_4_1_d.h" 41 #include "bif/bif_4_1_sh_mask.h" 42 43 #include "gca/gfx_7_0_d.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "gca/gfx_7_2_sh_mask.h" 46 47 #include "gmc/gmc_7_0_d.h" 48 #include "gmc/gmc_7_0_sh_mask.h" 49 50 #include "oss/oss_2_0_d.h" 51 #include "oss/oss_2_0_sh_mask.h" 52 53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ 54 55 #define GFX7_NUM_GFX_RINGS 1 56 #define GFX7_MEC_HPD_SIZE 2048 57 58 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 59 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 60 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 61 62 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/bonaire_me.bin"); 64 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin"); 66 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin"); 67 68 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/hawaii_me.bin"); 70 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin"); 72 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin"); 73 74 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/kaveri_me.bin"); 76 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin"); 78 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin"); 80 81 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/kabini_me.bin"); 83 MODULE_FIRMWARE("amdgpu/kabini_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin"); 85 MODULE_FIRMWARE("amdgpu/kabini_mec.bin"); 86 87 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin"); 88 MODULE_FIRMWARE("amdgpu/mullins_me.bin"); 89 MODULE_FIRMWARE("amdgpu/mullins_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin"); 91 MODULE_FIRMWARE("amdgpu/mullins_mec.bin"); 92 93 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 94 { 95 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 96 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 97 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 98 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 99 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 100 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 101 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 102 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 103 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 104 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 105 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 106 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 107 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 108 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 109 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 110 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 111 }; 112 113 static const u32 spectre_rlc_save_restore_register_list[] = 114 { 115 (0x0e00 << 16) | (0xc12c >> 2), 116 0x00000000, 117 (0x0e00 << 16) | (0xc140 >> 2), 118 0x00000000, 119 (0x0e00 << 16) | (0xc150 >> 2), 120 0x00000000, 121 (0x0e00 << 16) | (0xc15c >> 2), 122 0x00000000, 123 (0x0e00 << 16) | (0xc168 >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc170 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc178 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc204 >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc2b4 >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc2b8 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0xc2bc >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0xc2c0 >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0x8228 >> 2), 140 0x00000000, 141 (0x0e00 << 16) | (0x829c >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0x869c >> 2), 144 0x00000000, 145 (0x0600 << 16) | (0x98f4 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0x98f8 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x9900 >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0xc260 >> 2), 152 0x00000000, 153 (0x0e00 << 16) | (0x90e8 >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x3c000 >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x3c00c >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0x8c1c >> 2), 160 0x00000000, 161 (0x0e00 << 16) | (0x9700 >> 2), 162 0x00000000, 163 (0x0e00 << 16) | (0xcd20 >> 2), 164 0x00000000, 165 (0x4e00 << 16) | (0xcd20 >> 2), 166 0x00000000, 167 (0x5e00 << 16) | (0xcd20 >> 2), 168 0x00000000, 169 (0x6e00 << 16) | (0xcd20 >> 2), 170 0x00000000, 171 (0x7e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0x8e00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0x9e00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0xae00 << 16) | (0xcd20 >> 2), 178 0x00000000, 179 (0xbe00 << 16) | (0xcd20 >> 2), 180 0x00000000, 181 (0x0e00 << 16) | (0x89bc >> 2), 182 0x00000000, 183 (0x0e00 << 16) | (0x8900 >> 2), 184 0x00000000, 185 0x3, 186 (0x0e00 << 16) | (0xc130 >> 2), 187 0x00000000, 188 (0x0e00 << 16) | (0xc134 >> 2), 189 0x00000000, 190 (0x0e00 << 16) | (0xc1fc >> 2), 191 0x00000000, 192 (0x0e00 << 16) | (0xc208 >> 2), 193 0x00000000, 194 (0x0e00 << 16) | (0xc264 >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc268 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc26c >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc270 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc274 >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc278 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc27c >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc280 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc284 >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc288 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc28c >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc290 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc294 >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc298 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc29c >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc2a0 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc2a4 >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc2a8 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0xc2ac >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0xc2b0 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0x301d0 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0x30238 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0x30250 >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0x30254 >> 2), 241 0x00000000, 242 (0x0e00 << 16) | (0x30258 >> 2), 243 0x00000000, 244 (0x0e00 << 16) | (0x3025c >> 2), 245 0x00000000, 246 (0x4e00 << 16) | (0xc900 >> 2), 247 0x00000000, 248 (0x5e00 << 16) | (0xc900 >> 2), 249 0x00000000, 250 (0x6e00 << 16) | (0xc900 >> 2), 251 0x00000000, 252 (0x7e00 << 16) | (0xc900 >> 2), 253 0x00000000, 254 (0x8e00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0x9e00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0xae00 << 16) | (0xc900 >> 2), 259 0x00000000, 260 (0xbe00 << 16) | (0xc900 >> 2), 261 0x00000000, 262 (0x4e00 << 16) | (0xc904 >> 2), 263 0x00000000, 264 (0x5e00 << 16) | (0xc904 >> 2), 265 0x00000000, 266 (0x6e00 << 16) | (0xc904 >> 2), 267 0x00000000, 268 (0x7e00 << 16) | (0xc904 >> 2), 269 0x00000000, 270 (0x8e00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0x9e00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0xae00 << 16) | (0xc904 >> 2), 275 0x00000000, 276 (0xbe00 << 16) | (0xc904 >> 2), 277 0x00000000, 278 (0x4e00 << 16) | (0xc908 >> 2), 279 0x00000000, 280 (0x5e00 << 16) | (0xc908 >> 2), 281 0x00000000, 282 (0x6e00 << 16) | (0xc908 >> 2), 283 0x00000000, 284 (0x7e00 << 16) | (0xc908 >> 2), 285 0x00000000, 286 (0x8e00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0x9e00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0xae00 << 16) | (0xc908 >> 2), 291 0x00000000, 292 (0xbe00 << 16) | (0xc908 >> 2), 293 0x00000000, 294 (0x4e00 << 16) | (0xc90c >> 2), 295 0x00000000, 296 (0x5e00 << 16) | (0xc90c >> 2), 297 0x00000000, 298 (0x6e00 << 16) | (0xc90c >> 2), 299 0x00000000, 300 (0x7e00 << 16) | (0xc90c >> 2), 301 0x00000000, 302 (0x8e00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0x9e00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0xae00 << 16) | (0xc90c >> 2), 307 0x00000000, 308 (0xbe00 << 16) | (0xc90c >> 2), 309 0x00000000, 310 (0x4e00 << 16) | (0xc910 >> 2), 311 0x00000000, 312 (0x5e00 << 16) | (0xc910 >> 2), 313 0x00000000, 314 (0x6e00 << 16) | (0xc910 >> 2), 315 0x00000000, 316 (0x7e00 << 16) | (0xc910 >> 2), 317 0x00000000, 318 (0x8e00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0x9e00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0xae00 << 16) | (0xc910 >> 2), 323 0x00000000, 324 (0xbe00 << 16) | (0xc910 >> 2), 325 0x00000000, 326 (0x0e00 << 16) | (0xc99c >> 2), 327 0x00000000, 328 (0x0e00 << 16) | (0x9834 >> 2), 329 0x00000000, 330 (0x0000 << 16) | (0x30f00 >> 2), 331 0x00000000, 332 (0x0001 << 16) | (0x30f00 >> 2), 333 0x00000000, 334 (0x0000 << 16) | (0x30f04 >> 2), 335 0x00000000, 336 (0x0001 << 16) | (0x30f04 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f08 >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f08 >> 2), 341 0x00000000, 342 (0x0000 << 16) | (0x30f0c >> 2), 343 0x00000000, 344 (0x0001 << 16) | (0x30f0c >> 2), 345 0x00000000, 346 (0x0600 << 16) | (0x9b7c >> 2), 347 0x00000000, 348 (0x0e00 << 16) | (0x8a14 >> 2), 349 0x00000000, 350 (0x0e00 << 16) | (0x8a18 >> 2), 351 0x00000000, 352 (0x0600 << 16) | (0x30a00 >> 2), 353 0x00000000, 354 (0x0e00 << 16) | (0x8bf0 >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x8bcc >> 2), 357 0x00000000, 358 (0x0e00 << 16) | (0x8b24 >> 2), 359 0x00000000, 360 (0x0e00 << 16) | (0x30a04 >> 2), 361 0x00000000, 362 (0x0600 << 16) | (0x30a10 >> 2), 363 0x00000000, 364 (0x0600 << 16) | (0x30a14 >> 2), 365 0x00000000, 366 (0x0600 << 16) | (0x30a18 >> 2), 367 0x00000000, 368 (0x0600 << 16) | (0x30a2c >> 2), 369 0x00000000, 370 (0x0e00 << 16) | (0xc700 >> 2), 371 0x00000000, 372 (0x0e00 << 16) | (0xc704 >> 2), 373 0x00000000, 374 (0x0e00 << 16) | (0xc708 >> 2), 375 0x00000000, 376 (0x0e00 << 16) | (0xc768 >> 2), 377 0x00000000, 378 (0x0400 << 16) | (0xc770 >> 2), 379 0x00000000, 380 (0x0400 << 16) | (0xc774 >> 2), 381 0x00000000, 382 (0x0400 << 16) | (0xc778 >> 2), 383 0x00000000, 384 (0x0400 << 16) | (0xc77c >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc780 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc784 >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc788 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc78c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc798 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc79c >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc7a0 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc7a4 >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc7a8 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc7ac >> 2), 405 0x00000000, 406 (0x0400 << 16) | (0xc7b0 >> 2), 407 0x00000000, 408 (0x0400 << 16) | (0xc7b4 >> 2), 409 0x00000000, 410 (0x0e00 << 16) | (0x9100 >> 2), 411 0x00000000, 412 (0x0e00 << 16) | (0x3c010 >> 2), 413 0x00000000, 414 (0x0e00 << 16) | (0x92a8 >> 2), 415 0x00000000, 416 (0x0e00 << 16) | (0x92ac >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x92b4 >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x92b8 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92bc >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92c0 >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92c4 >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92c8 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x92cc >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x92d0 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x8c00 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x8c04 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x8c20 >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0x8c38 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x8c3c >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0xae00 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0x9604 >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0xac08 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0xac0c >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xac10 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0xac14 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac58 >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac68 >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac6c >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac70 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac74 >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac78 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac7c >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac80 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac84 >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0xac88 >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0xac8c >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0x970c >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0x9714 >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0x9718 >> 2), 483 0x00000000, 484 (0x0e00 << 16) | (0x971c >> 2), 485 0x00000000, 486 (0x0e00 << 16) | (0x31068 >> 2), 487 0x00000000, 488 (0x4e00 << 16) | (0x31068 >> 2), 489 0x00000000, 490 (0x5e00 << 16) | (0x31068 >> 2), 491 0x00000000, 492 (0x6e00 << 16) | (0x31068 >> 2), 493 0x00000000, 494 (0x7e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0x8e00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0x9e00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0xae00 << 16) | (0x31068 >> 2), 501 0x00000000, 502 (0xbe00 << 16) | (0x31068 >> 2), 503 0x00000000, 504 (0x0e00 << 16) | (0xcd10 >> 2), 505 0x00000000, 506 (0x0e00 << 16) | (0xcd14 >> 2), 507 0x00000000, 508 (0x0e00 << 16) | (0x88b0 >> 2), 509 0x00000000, 510 (0x0e00 << 16) | (0x88b4 >> 2), 511 0x00000000, 512 (0x0e00 << 16) | (0x88b8 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0x88bc >> 2), 515 0x00000000, 516 (0x0400 << 16) | (0x89c0 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88c4 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88c8 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88d0 >> 2), 523 0x00000000, 524 (0x0e00 << 16) | (0x88d4 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x88d8 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x8980 >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x30938 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x3093c >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x30940 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x89a0 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x30900 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x30904 >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x89b4 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x3c210 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x3c214 >> 2), 547 0x00000000, 548 (0x0e00 << 16) | (0x3c218 >> 2), 549 0x00000000, 550 (0x0e00 << 16) | (0x8904 >> 2), 551 0x00000000, 552 0x5, 553 (0x0e00 << 16) | (0x8c28 >> 2), 554 (0x0e00 << 16) | (0x8c2c >> 2), 555 (0x0e00 << 16) | (0x8c30 >> 2), 556 (0x0e00 << 16) | (0x8c34 >> 2), 557 (0x0e00 << 16) | (0x9600 >> 2), 558 }; 559 560 static const u32 kalindi_rlc_save_restore_register_list[] = 561 { 562 (0x0e00 << 16) | (0xc12c >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc140 >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc150 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc15c >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc168 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc170 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc204 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2b4 >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2b8 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0xc2bc >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0xc2c0 >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x8228 >> 2), 585 0x00000000, 586 (0x0e00 << 16) | (0x829c >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x869c >> 2), 589 0x00000000, 590 (0x0600 << 16) | (0x98f4 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0x98f8 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x9900 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0xc260 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x90e8 >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x3c000 >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x3c00c >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0x8c1c >> 2), 605 0x00000000, 606 (0x0e00 << 16) | (0x9700 >> 2), 607 0x00000000, 608 (0x0e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x4e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x5e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x6e00 << 16) | (0xcd20 >> 2), 615 0x00000000, 616 (0x7e00 << 16) | (0xcd20 >> 2), 617 0x00000000, 618 (0x0e00 << 16) | (0x89bc >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0x8900 >> 2), 621 0x00000000, 622 0x3, 623 (0x0e00 << 16) | (0xc130 >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc134 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc1fc >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc208 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc264 >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc268 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc26c >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc270 >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc274 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc28c >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc290 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc294 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc298 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a0 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2a4 >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0xc2a8 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0xc2ac >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x301d0 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30238 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30250 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x30254 >> 2), 664 0x00000000, 665 (0x0e00 << 16) | (0x30258 >> 2), 666 0x00000000, 667 (0x0e00 << 16) | (0x3025c >> 2), 668 0x00000000, 669 (0x4e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x5e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x6e00 << 16) | (0xc900 >> 2), 674 0x00000000, 675 (0x7e00 << 16) | (0xc900 >> 2), 676 0x00000000, 677 (0x4e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x5e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x6e00 << 16) | (0xc904 >> 2), 682 0x00000000, 683 (0x7e00 << 16) | (0xc904 >> 2), 684 0x00000000, 685 (0x4e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x5e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x6e00 << 16) | (0xc908 >> 2), 690 0x00000000, 691 (0x7e00 << 16) | (0xc908 >> 2), 692 0x00000000, 693 (0x4e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x5e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x6e00 << 16) | (0xc90c >> 2), 698 0x00000000, 699 (0x7e00 << 16) | (0xc90c >> 2), 700 0x00000000, 701 (0x4e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x5e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x6e00 << 16) | (0xc910 >> 2), 706 0x00000000, 707 (0x7e00 << 16) | (0xc910 >> 2), 708 0x00000000, 709 (0x0e00 << 16) | (0xc99c >> 2), 710 0x00000000, 711 (0x0e00 << 16) | (0x9834 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f00 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f04 >> 2), 716 0x00000000, 717 (0x0000 << 16) | (0x30f08 >> 2), 718 0x00000000, 719 (0x0000 << 16) | (0x30f0c >> 2), 720 0x00000000, 721 (0x0600 << 16) | (0x9b7c >> 2), 722 0x00000000, 723 (0x0e00 << 16) | (0x8a14 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8a18 >> 2), 726 0x00000000, 727 (0x0600 << 16) | (0x30a00 >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8bf0 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x8bcc >> 2), 732 0x00000000, 733 (0x0e00 << 16) | (0x8b24 >> 2), 734 0x00000000, 735 (0x0e00 << 16) | (0x30a04 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a10 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a14 >> 2), 740 0x00000000, 741 (0x0600 << 16) | (0x30a18 >> 2), 742 0x00000000, 743 (0x0600 << 16) | (0x30a2c >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc700 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc704 >> 2), 748 0x00000000, 749 (0x0e00 << 16) | (0xc708 >> 2), 750 0x00000000, 751 (0x0e00 << 16) | (0xc768 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc770 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc774 >> 2), 756 0x00000000, 757 (0x0400 << 16) | (0xc798 >> 2), 758 0x00000000, 759 (0x0400 << 16) | (0xc79c >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x9100 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x3c010 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c00 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c04 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c20 >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0x8c38 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x8c3c >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xae00 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0x9604 >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac08 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac0c >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac10 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac14 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac58 >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac68 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac6c >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac70 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac74 >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac78 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac7c >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac80 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac84 >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0xac88 >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0xac8c >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x970c >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x9714 >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x9718 >> 2), 814 0x00000000, 815 (0x0e00 << 16) | (0x971c >> 2), 816 0x00000000, 817 (0x0e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x4e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x5e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x6e00 << 16) | (0x31068 >> 2), 824 0x00000000, 825 (0x7e00 << 16) | (0x31068 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0xcd10 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0xcd14 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b0 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88b4 >> 2), 834 0x00000000, 835 (0x0e00 << 16) | (0x88b8 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88bc >> 2), 838 0x00000000, 839 (0x0400 << 16) | (0x89c0 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88c4 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88c8 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d0 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x88d4 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x88d8 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x8980 >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30938 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x3093c >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30940 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x89a0 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x30900 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x30904 >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x89b4 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3e1fc >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c210 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x3c214 >> 2), 872 0x00000000, 873 (0x0e00 << 16) | (0x3c218 >> 2), 874 0x00000000, 875 (0x0e00 << 16) | (0x8904 >> 2), 876 0x00000000, 877 0x5, 878 (0x0e00 << 16) | (0x8c28 >> 2), 879 (0x0e00 << 16) | (0x8c2c >> 2), 880 (0x0e00 << 16) | (0x8c30 >> 2), 881 (0x0e00 << 16) | (0x8c34 >> 2), 882 (0x0e00 << 16) | (0x9600 >> 2), 883 }; 884 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 886 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 889 890 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 891 { 892 amdgpu_ucode_release(&adev->gfx.pfp_fw); 893 amdgpu_ucode_release(&adev->gfx.me_fw); 894 amdgpu_ucode_release(&adev->gfx.ce_fw); 895 amdgpu_ucode_release(&adev->gfx.mec_fw); 896 amdgpu_ucode_release(&adev->gfx.mec2_fw); 897 amdgpu_ucode_release(&adev->gfx.rlc_fw); 898 } 899 900 /* 901 * Core functions 902 */ 903 /** 904 * gfx_v7_0_init_microcode - load ucode images from disk 905 * 906 * @adev: amdgpu_device pointer 907 * 908 * Use the firmware interface to load the ucode images into 909 * the driver (not loaded into hw). 910 * Returns 0 on success, error on failure. 911 */ 912 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 913 { 914 const char *chip_name; 915 char fw_name[30]; 916 int err; 917 918 DRM_DEBUG("\n"); 919 920 switch (adev->asic_type) { 921 case CHIP_BONAIRE: 922 chip_name = "bonaire"; 923 break; 924 case CHIP_HAWAII: 925 chip_name = "hawaii"; 926 break; 927 case CHIP_KAVERI: 928 chip_name = "kaveri"; 929 break; 930 case CHIP_KABINI: 931 chip_name = "kabini"; 932 break; 933 case CHIP_MULLINS: 934 chip_name = "mullins"; 935 break; 936 default: BUG(); 937 } 938 939 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 940 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 941 if (err) 942 goto out; 943 944 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 945 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 946 if (err) 947 goto out; 948 949 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 950 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 951 if (err) 952 goto out; 953 954 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 955 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 956 if (err) 957 goto out; 958 959 if (adev->asic_type == CHIP_KAVERI) { 960 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 961 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 962 if (err) 963 goto out; 964 } 965 966 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 967 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 968 if (err) 969 goto out; 970 out: 971 if (err) { 972 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); 973 gfx_v7_0_free_microcode(adev); 974 } 975 return err; 976 } 977 978 /** 979 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 980 * 981 * @adev: amdgpu_device pointer 982 * 983 * Starting with SI, the tiling setup is done globally in a 984 * set of 32 tiling modes. Rather than selecting each set of 985 * parameters per surface as on older asics, we just select 986 * which index in the tiling table we want to use, and the 987 * surface uses those parameters (CIK). 988 */ 989 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 990 { 991 const u32 num_tile_mode_states = 992 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 993 const u32 num_secondary_tile_mode_states = 994 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 995 u32 reg_offset, split_equal_to_row_size; 996 uint32_t *tile, *macrotile; 997 998 tile = adev->gfx.config.tile_mode_array; 999 macrotile = adev->gfx.config.macrotile_mode_array; 1000 1001 switch (adev->gfx.config.mem_row_size_in_kb) { 1002 case 1: 1003 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1004 break; 1005 case 2: 1006 default: 1007 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1008 break; 1009 case 4: 1010 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1011 break; 1012 } 1013 1014 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1015 tile[reg_offset] = 0; 1016 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1017 macrotile[reg_offset] = 0; 1018 1019 switch (adev->asic_type) { 1020 case CHIP_BONAIRE: 1021 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1022 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1023 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1024 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1025 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1026 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1028 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1029 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1030 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1031 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1032 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1033 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1034 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1036 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1037 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1039 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1040 TILE_SPLIT(split_equal_to_row_size)); 1041 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1043 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1044 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1045 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1046 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1047 TILE_SPLIT(split_equal_to_row_size)); 1048 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1049 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1050 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1051 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1052 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1053 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1054 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1055 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1058 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1059 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1061 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1062 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1063 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1065 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1066 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1067 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1068 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1069 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1070 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1072 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1074 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1076 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1078 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1079 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1083 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1085 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1086 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1090 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1094 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1095 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1097 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1098 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1099 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1102 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1103 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1104 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1105 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1107 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1108 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1109 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1111 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1113 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1114 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1115 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1116 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1117 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1118 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1120 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1122 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1123 1124 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1127 NUM_BANKS(ADDR_SURF_16_BANK)); 1128 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1131 NUM_BANKS(ADDR_SURF_16_BANK)); 1132 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1135 NUM_BANKS(ADDR_SURF_16_BANK)); 1136 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1139 NUM_BANKS(ADDR_SURF_16_BANK)); 1140 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1143 NUM_BANKS(ADDR_SURF_16_BANK)); 1144 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1147 NUM_BANKS(ADDR_SURF_8_BANK)); 1148 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1151 NUM_BANKS(ADDR_SURF_4_BANK)); 1152 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1155 NUM_BANKS(ADDR_SURF_16_BANK)); 1156 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1159 NUM_BANKS(ADDR_SURF_16_BANK)); 1160 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1163 NUM_BANKS(ADDR_SURF_16_BANK)); 1164 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1167 NUM_BANKS(ADDR_SURF_16_BANK)); 1168 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1171 NUM_BANKS(ADDR_SURF_16_BANK)); 1172 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1175 NUM_BANKS(ADDR_SURF_8_BANK)); 1176 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1179 NUM_BANKS(ADDR_SURF_4_BANK)); 1180 1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1182 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1183 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1184 if (reg_offset != 7) 1185 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1186 break; 1187 case CHIP_HAWAII: 1188 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1189 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1190 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1191 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1192 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1193 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1195 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1196 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1197 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1198 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1199 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1200 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1201 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1203 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1204 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1206 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1207 TILE_SPLIT(split_equal_to_row_size)); 1208 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1210 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1211 TILE_SPLIT(split_equal_to_row_size)); 1212 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1214 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1215 TILE_SPLIT(split_equal_to_row_size)); 1216 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1217 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1218 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1219 TILE_SPLIT(split_equal_to_row_size)); 1220 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1222 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1223 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1225 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1226 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1229 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1230 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1233 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1234 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1237 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1238 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1239 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1240 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1242 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1243 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1244 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1246 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1247 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1248 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1249 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1250 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1251 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1252 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1253 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1254 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1255 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1256 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1260 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1263 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1264 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1265 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1266 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1267 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1268 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1269 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1271 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1275 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1276 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1279 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1283 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1287 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1291 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1293 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1294 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1296 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1298 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1300 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1302 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1303 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1304 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1306 1307 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1310 NUM_BANKS(ADDR_SURF_16_BANK)); 1311 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1312 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1313 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1314 NUM_BANKS(ADDR_SURF_16_BANK)); 1315 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1316 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1317 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1318 NUM_BANKS(ADDR_SURF_16_BANK)); 1319 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1322 NUM_BANKS(ADDR_SURF_16_BANK)); 1323 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1326 NUM_BANKS(ADDR_SURF_8_BANK)); 1327 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1330 NUM_BANKS(ADDR_SURF_4_BANK)); 1331 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1334 NUM_BANKS(ADDR_SURF_4_BANK)); 1335 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1338 NUM_BANKS(ADDR_SURF_16_BANK)); 1339 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1342 NUM_BANKS(ADDR_SURF_16_BANK)); 1343 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1346 NUM_BANKS(ADDR_SURF_16_BANK)); 1347 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1350 NUM_BANKS(ADDR_SURF_8_BANK)); 1351 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1354 NUM_BANKS(ADDR_SURF_16_BANK)); 1355 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1358 NUM_BANKS(ADDR_SURF_8_BANK)); 1359 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1362 NUM_BANKS(ADDR_SURF_4_BANK)); 1363 1364 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1365 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1366 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1367 if (reg_offset != 7) 1368 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1369 break; 1370 case CHIP_KABINI: 1371 case CHIP_KAVERI: 1372 case CHIP_MULLINS: 1373 default: 1374 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1375 PIPE_CONFIG(ADDR_SURF_P2) | 1376 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1377 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1378 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1379 PIPE_CONFIG(ADDR_SURF_P2) | 1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1382 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1383 PIPE_CONFIG(ADDR_SURF_P2) | 1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1385 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1386 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1387 PIPE_CONFIG(ADDR_SURF_P2) | 1388 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1389 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1390 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1391 PIPE_CONFIG(ADDR_SURF_P2) | 1392 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1393 TILE_SPLIT(split_equal_to_row_size)); 1394 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1395 PIPE_CONFIG(ADDR_SURF_P2) | 1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1397 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1398 PIPE_CONFIG(ADDR_SURF_P2) | 1399 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1400 TILE_SPLIT(split_equal_to_row_size)); 1401 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1402 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1403 PIPE_CONFIG(ADDR_SURF_P2)); 1404 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1405 PIPE_CONFIG(ADDR_SURF_P2) | 1406 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1407 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1408 PIPE_CONFIG(ADDR_SURF_P2) | 1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1410 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1411 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1412 PIPE_CONFIG(ADDR_SURF_P2) | 1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1414 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1415 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1416 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1417 PIPE_CONFIG(ADDR_SURF_P2) | 1418 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1419 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1420 PIPE_CONFIG(ADDR_SURF_P2) | 1421 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1422 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1423 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1424 PIPE_CONFIG(ADDR_SURF_P2) | 1425 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1427 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1428 PIPE_CONFIG(ADDR_SURF_P2) | 1429 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1431 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1432 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1433 PIPE_CONFIG(ADDR_SURF_P2) | 1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1436 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1439 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1443 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1444 PIPE_CONFIG(ADDR_SURF_P2) | 1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1447 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1448 PIPE_CONFIG(ADDR_SURF_P2) | 1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1450 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1451 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1452 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1453 PIPE_CONFIG(ADDR_SURF_P2) | 1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1456 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1457 PIPE_CONFIG(ADDR_SURF_P2) | 1458 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1459 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1460 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1461 PIPE_CONFIG(ADDR_SURF_P2) | 1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1464 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1465 PIPE_CONFIG(ADDR_SURF_P2) | 1466 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1467 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1468 PIPE_CONFIG(ADDR_SURF_P2) | 1469 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1470 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1471 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1472 PIPE_CONFIG(ADDR_SURF_P2) | 1473 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1475 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1476 1477 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1480 NUM_BANKS(ADDR_SURF_8_BANK)); 1481 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1484 NUM_BANKS(ADDR_SURF_8_BANK)); 1485 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1488 NUM_BANKS(ADDR_SURF_8_BANK)); 1489 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1492 NUM_BANKS(ADDR_SURF_8_BANK)); 1493 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1496 NUM_BANKS(ADDR_SURF_8_BANK)); 1497 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1500 NUM_BANKS(ADDR_SURF_8_BANK)); 1501 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1504 NUM_BANKS(ADDR_SURF_8_BANK)); 1505 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1508 NUM_BANKS(ADDR_SURF_16_BANK)); 1509 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1512 NUM_BANKS(ADDR_SURF_16_BANK)); 1513 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1516 NUM_BANKS(ADDR_SURF_16_BANK)); 1517 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1520 NUM_BANKS(ADDR_SURF_16_BANK)); 1521 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1524 NUM_BANKS(ADDR_SURF_16_BANK)); 1525 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1528 NUM_BANKS(ADDR_SURF_16_BANK)); 1529 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1532 NUM_BANKS(ADDR_SURF_8_BANK)); 1533 1534 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1535 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1536 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1537 if (reg_offset != 7) 1538 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1539 break; 1540 } 1541 } 1542 1543 /** 1544 * gfx_v7_0_select_se_sh - select which SE, SH to address 1545 * 1546 * @adev: amdgpu_device pointer 1547 * @se_num: shader engine to address 1548 * @sh_num: sh block to address 1549 * @instance: Certain registers are instanced per SE or SH. 1550 * 0xffffffff means broadcast to all SEs or SHs (CIK). 1551 * @xcc_id: xcc accelerated compute core id 1552 * Select which SE, SH combinations to address. 1553 */ 1554 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1555 u32 se_num, u32 sh_num, u32 instance, 1556 int xcc_id) 1557 { 1558 u32 data; 1559 1560 if (instance == 0xffffffff) 1561 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1562 else 1563 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1564 1565 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1566 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1567 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1568 else if (se_num == 0xffffffff) 1569 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1570 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1571 else if (sh_num == 0xffffffff) 1572 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1573 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1574 else 1575 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1576 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1577 WREG32(mmGRBM_GFX_INDEX, data); 1578 } 1579 1580 /** 1581 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1582 * 1583 * @adev: amdgpu_device pointer 1584 * 1585 * Calculates the bitmask of enabled RBs (CIK). 1586 * Returns the enabled RB bitmask. 1587 */ 1588 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1589 { 1590 u32 data, mask; 1591 1592 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1593 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1594 1595 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1596 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1597 1598 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1599 adev->gfx.config.max_sh_per_se); 1600 1601 return (~data) & mask; 1602 } 1603 1604 static void 1605 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1606 { 1607 switch (adev->asic_type) { 1608 case CHIP_BONAIRE: 1609 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1610 SE_XSEL(1) | SE_YSEL(1); 1611 *rconf1 |= 0x0; 1612 break; 1613 case CHIP_HAWAII: 1614 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1615 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1616 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1617 SE_YSEL(3); 1618 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1619 SE_PAIR_YSEL(2); 1620 break; 1621 case CHIP_KAVERI: 1622 *rconf |= RB_MAP_PKR0(2); 1623 *rconf1 |= 0x0; 1624 break; 1625 case CHIP_KABINI: 1626 case CHIP_MULLINS: 1627 *rconf |= 0x0; 1628 *rconf1 |= 0x0; 1629 break; 1630 default: 1631 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1632 break; 1633 } 1634 } 1635 1636 static void 1637 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1638 u32 raster_config, u32 raster_config_1, 1639 unsigned rb_mask, unsigned num_rb) 1640 { 1641 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1642 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1643 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1644 unsigned rb_per_se = num_rb / num_se; 1645 unsigned se_mask[4]; 1646 unsigned se; 1647 1648 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1649 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1650 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1651 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1652 1653 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1654 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1655 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1656 1657 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1658 (!se_mask[2] && !se_mask[3]))) { 1659 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1660 1661 if (!se_mask[0] && !se_mask[1]) { 1662 raster_config_1 |= 1663 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1664 } else { 1665 raster_config_1 |= 1666 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1667 } 1668 } 1669 1670 for (se = 0; se < num_se; se++) { 1671 unsigned raster_config_se = raster_config; 1672 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1673 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1674 int idx = (se / 2) * 2; 1675 1676 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1677 raster_config_se &= ~SE_MAP_MASK; 1678 1679 if (!se_mask[idx]) { 1680 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1681 } else { 1682 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1683 } 1684 } 1685 1686 pkr0_mask &= rb_mask; 1687 pkr1_mask &= rb_mask; 1688 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1689 raster_config_se &= ~PKR_MAP_MASK; 1690 1691 if (!pkr0_mask) { 1692 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1693 } else { 1694 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1695 } 1696 } 1697 1698 if (rb_per_se >= 2) { 1699 unsigned rb0_mask = 1 << (se * rb_per_se); 1700 unsigned rb1_mask = rb0_mask << 1; 1701 1702 rb0_mask &= rb_mask; 1703 rb1_mask &= rb_mask; 1704 if (!rb0_mask || !rb1_mask) { 1705 raster_config_se &= ~RB_MAP_PKR0_MASK; 1706 1707 if (!rb0_mask) { 1708 raster_config_se |= 1709 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1710 } else { 1711 raster_config_se |= 1712 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1713 } 1714 } 1715 1716 if (rb_per_se > 2) { 1717 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1718 rb1_mask = rb0_mask << 1; 1719 rb0_mask &= rb_mask; 1720 rb1_mask &= rb_mask; 1721 if (!rb0_mask || !rb1_mask) { 1722 raster_config_se &= ~RB_MAP_PKR1_MASK; 1723 1724 if (!rb0_mask) { 1725 raster_config_se |= 1726 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1727 } else { 1728 raster_config_se |= 1729 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1730 } 1731 } 1732 } 1733 } 1734 1735 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1736 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1737 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1738 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1739 } 1740 1741 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1742 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1743 } 1744 1745 /** 1746 * gfx_v7_0_setup_rb - setup the RBs on the asic 1747 * 1748 * @adev: amdgpu_device pointer 1749 * 1750 * Configures per-SE/SH RB registers (CIK). 1751 */ 1752 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1753 { 1754 int i, j; 1755 u32 data; 1756 u32 raster_config = 0, raster_config_1 = 0; 1757 u32 active_rbs = 0; 1758 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1759 adev->gfx.config.max_sh_per_se; 1760 unsigned num_rb_pipes; 1761 1762 mutex_lock(&adev->grbm_idx_mutex); 1763 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1764 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1765 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1766 data = gfx_v7_0_get_rb_active_bitmap(adev); 1767 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1768 rb_bitmap_width_per_sh); 1769 } 1770 } 1771 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1772 1773 adev->gfx.config.backend_enable_mask = active_rbs; 1774 adev->gfx.config.num_rbs = hweight32(active_rbs); 1775 1776 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1777 adev->gfx.config.max_shader_engines, 16); 1778 1779 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1780 1781 if (!adev->gfx.config.backend_enable_mask || 1782 adev->gfx.config.num_rbs >= num_rb_pipes) { 1783 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1784 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1785 } else { 1786 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1787 adev->gfx.config.backend_enable_mask, 1788 num_rb_pipes); 1789 } 1790 1791 /* cache the values for userspace */ 1792 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1793 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1794 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1795 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1796 RREG32(mmCC_RB_BACKEND_DISABLE); 1797 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1798 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1799 adev->gfx.config.rb_config[i][j].raster_config = 1800 RREG32(mmPA_SC_RASTER_CONFIG); 1801 adev->gfx.config.rb_config[i][j].raster_config_1 = 1802 RREG32(mmPA_SC_RASTER_CONFIG_1); 1803 } 1804 } 1805 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1806 mutex_unlock(&adev->grbm_idx_mutex); 1807 } 1808 1809 #define DEFAULT_SH_MEM_BASES (0x6000) 1810 /** 1811 * gfx_v7_0_init_compute_vmid - gart enable 1812 * 1813 * @adev: amdgpu_device pointer 1814 * 1815 * Initialize compute vmid sh_mem registers 1816 * 1817 */ 1818 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1819 { 1820 int i; 1821 uint32_t sh_mem_config; 1822 uint32_t sh_mem_bases; 1823 1824 /* 1825 * Configure apertures: 1826 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1827 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1828 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1829 */ 1830 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1831 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1832 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1833 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1834 mutex_lock(&adev->srbm_mutex); 1835 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1836 cik_srbm_select(adev, 0, 0, 0, i); 1837 /* CP and shaders */ 1838 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1839 WREG32(mmSH_MEM_APE1_BASE, 1); 1840 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1841 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1842 } 1843 cik_srbm_select(adev, 0, 0, 0, 0); 1844 mutex_unlock(&adev->srbm_mutex); 1845 1846 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1847 access. These should be enabled by FW for target VMIDs. */ 1848 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1849 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 1850 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); 1851 WREG32(amdgpu_gds_reg_offset[i].gws, 0); 1852 WREG32(amdgpu_gds_reg_offset[i].oa, 0); 1853 } 1854 } 1855 1856 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) 1857 { 1858 int vmid; 1859 1860 /* 1861 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1862 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1863 * the driver can enable them for graphics. VMID0 should maintain 1864 * access so that HWS firmware can save/restore entries. 1865 */ 1866 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1867 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 1868 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 1869 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 1870 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 1871 } 1872 } 1873 1874 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1875 { 1876 adev->gfx.config.double_offchip_lds_buf = 1; 1877 } 1878 1879 /** 1880 * gfx_v7_0_constants_init - setup the 3D engine 1881 * 1882 * @adev: amdgpu_device pointer 1883 * 1884 * init the gfx constants such as the 3D engine, tiling configuration 1885 * registers, maximum number of quad pipes, render backends... 1886 */ 1887 static void gfx_v7_0_constants_init(struct amdgpu_device *adev) 1888 { 1889 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1890 u32 tmp; 1891 int i; 1892 1893 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1894 1895 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1896 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1897 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1898 1899 gfx_v7_0_tiling_mode_table_init(adev); 1900 1901 gfx_v7_0_setup_rb(adev); 1902 gfx_v7_0_get_cu_info(adev); 1903 gfx_v7_0_config_init(adev); 1904 1905 /* set HW defaults for 3D engine */ 1906 WREG32(mmCP_MEQ_THRESHOLDS, 1907 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1908 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1909 1910 mutex_lock(&adev->grbm_idx_mutex); 1911 /* 1912 * making sure that the following register writes will be broadcasted 1913 * to all the shaders 1914 */ 1915 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1916 1917 /* XXX SH_MEM regs */ 1918 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1919 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1920 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1921 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1922 MTYPE_NC); 1923 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1924 MTYPE_UC); 1925 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1926 1927 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1928 SWIZZLE_ENABLE, 1); 1929 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1930 ELEMENT_SIZE, 1); 1931 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1932 INDEX_STRIDE, 3); 1933 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1934 1935 mutex_lock(&adev->srbm_mutex); 1936 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1937 if (i == 0) 1938 sh_mem_base = 0; 1939 else 1940 sh_mem_base = adev->gmc.shared_aperture_start >> 48; 1941 cik_srbm_select(adev, 0, 0, 0, i); 1942 /* CP and shaders */ 1943 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1944 WREG32(mmSH_MEM_APE1_BASE, 1); 1945 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1946 WREG32(mmSH_MEM_BASES, sh_mem_base); 1947 } 1948 cik_srbm_select(adev, 0, 0, 0, 0); 1949 mutex_unlock(&adev->srbm_mutex); 1950 1951 gfx_v7_0_init_compute_vmid(adev); 1952 gfx_v7_0_init_gds_vmid(adev); 1953 1954 WREG32(mmSX_DEBUG_1, 0x20); 1955 1956 WREG32(mmTA_CNTL_AUX, 0x00010000); 1957 1958 tmp = RREG32(mmSPI_CONFIG_CNTL); 1959 tmp |= 0x03000000; 1960 WREG32(mmSPI_CONFIG_CNTL, tmp); 1961 1962 WREG32(mmSQ_CONFIG, 1); 1963 1964 WREG32(mmDB_DEBUG, 0); 1965 1966 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1967 tmp |= 0x00000400; 1968 WREG32(mmDB_DEBUG2, tmp); 1969 1970 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1971 tmp |= 0x00020200; 1972 WREG32(mmDB_DEBUG3, tmp); 1973 1974 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1975 tmp |= 0x00018208; 1976 WREG32(mmCB_HW_CONTROL, tmp); 1977 1978 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1979 1980 WREG32(mmPA_SC_FIFO_SIZE, 1981 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1982 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1983 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1984 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1985 1986 WREG32(mmVGT_NUM_INSTANCES, 1); 1987 1988 WREG32(mmCP_PERFMON_CNTL, 0); 1989 1990 WREG32(mmSQ_CONFIG, 0); 1991 1992 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1993 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1994 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1995 1996 WREG32(mmVGT_CACHE_INVALIDATION, 1997 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1998 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1999 2000 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2001 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2002 2003 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2004 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2005 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2006 2007 tmp = RREG32(mmSPI_ARB_PRIORITY); 2008 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2009 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2010 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2011 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2012 WREG32(mmSPI_ARB_PRIORITY, tmp); 2013 2014 mutex_unlock(&adev->grbm_idx_mutex); 2015 2016 udelay(50); 2017 } 2018 2019 /** 2020 * gfx_v7_0_ring_test_ring - basic gfx ring test 2021 * 2022 * @ring: amdgpu_ring structure holding ring information 2023 * 2024 * Allocate a scratch register and write to it using the gfx ring (CIK). 2025 * Provides a basic gfx ring test to verify that the ring is working. 2026 * Used by gfx_v7_0_cp_gfx_resume(); 2027 * Returns 0 on success, error on failure. 2028 */ 2029 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2030 { 2031 struct amdgpu_device *adev = ring->adev; 2032 uint32_t tmp = 0; 2033 unsigned i; 2034 int r; 2035 2036 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2037 r = amdgpu_ring_alloc(ring, 3); 2038 if (r) 2039 return r; 2040 2041 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2042 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); 2043 amdgpu_ring_write(ring, 0xDEADBEEF); 2044 amdgpu_ring_commit(ring); 2045 2046 for (i = 0; i < adev->usec_timeout; i++) { 2047 tmp = RREG32(mmSCRATCH_REG0); 2048 if (tmp == 0xDEADBEEF) 2049 break; 2050 udelay(1); 2051 } 2052 if (i >= adev->usec_timeout) 2053 r = -ETIMEDOUT; 2054 return r; 2055 } 2056 2057 /** 2058 * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp 2059 * 2060 * @ring: amdgpu_ring structure holding ring information 2061 * 2062 * Emits an hdp flush on the cp. 2063 */ 2064 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2065 { 2066 u32 ref_and_mask; 2067 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2068 2069 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2070 switch (ring->me) { 2071 case 1: 2072 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2073 break; 2074 case 2: 2075 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2076 break; 2077 default: 2078 return; 2079 } 2080 } else { 2081 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2082 } 2083 2084 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2085 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2086 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2087 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2088 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2089 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2090 amdgpu_ring_write(ring, ref_and_mask); 2091 amdgpu_ring_write(ring, ref_and_mask); 2092 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2093 } 2094 2095 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2096 { 2097 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2098 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2099 EVENT_INDEX(4)); 2100 2101 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2102 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2103 EVENT_INDEX(0)); 2104 } 2105 2106 /** 2107 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2108 * 2109 * @ring: amdgpu_ring structure holding ring information 2110 * @addr: address 2111 * @seq: sequence number 2112 * @flags: fence related flags 2113 * 2114 * Emits a fence sequence number on the gfx ring and flushes 2115 * GPU caches. 2116 */ 2117 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2118 u64 seq, unsigned flags) 2119 { 2120 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2121 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2122 /* Workaround for cache flush problems. First send a dummy EOP 2123 * event down the pipe with seq one below. 2124 */ 2125 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2126 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2127 EOP_TC_ACTION_EN | 2128 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2129 EVENT_INDEX(5))); 2130 amdgpu_ring_write(ring, addr & 0xfffffffc); 2131 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2132 DATA_SEL(1) | INT_SEL(0)); 2133 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2134 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2135 2136 /* Then send the real EOP event down the pipe. */ 2137 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2138 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2139 EOP_TC_ACTION_EN | 2140 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2141 EVENT_INDEX(5))); 2142 amdgpu_ring_write(ring, addr & 0xfffffffc); 2143 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2144 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2145 amdgpu_ring_write(ring, lower_32_bits(seq)); 2146 amdgpu_ring_write(ring, upper_32_bits(seq)); 2147 } 2148 2149 /** 2150 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2151 * 2152 * @ring: amdgpu_ring structure holding ring information 2153 * @addr: address 2154 * @seq: sequence number 2155 * @flags: fence related flags 2156 * 2157 * Emits a fence sequence number on the compute ring and flushes 2158 * GPU caches. 2159 */ 2160 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2161 u64 addr, u64 seq, 2162 unsigned flags) 2163 { 2164 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2165 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2166 2167 /* RELEASE_MEM - flush caches, send int */ 2168 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2169 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2170 EOP_TC_ACTION_EN | 2171 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2172 EVENT_INDEX(5))); 2173 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2174 amdgpu_ring_write(ring, addr & 0xfffffffc); 2175 amdgpu_ring_write(ring, upper_32_bits(addr)); 2176 amdgpu_ring_write(ring, lower_32_bits(seq)); 2177 amdgpu_ring_write(ring, upper_32_bits(seq)); 2178 } 2179 2180 /* 2181 * IB stuff 2182 */ 2183 /** 2184 * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring 2185 * 2186 * @ring: amdgpu_ring structure holding ring information 2187 * @job: job to retrieve vmid from 2188 * @ib: amdgpu indirect buffer object 2189 * @flags: options (AMDGPU_HAVE_CTX_SWITCH) 2190 * 2191 * Emits an DE (drawing engine) or CE (constant engine) IB 2192 * on the gfx ring. IBs are usually generated by userspace 2193 * acceleration drivers and submitted to the kernel for 2194 * scheduling on the ring. This function schedules the IB 2195 * on the gfx ring for execution by the GPU. 2196 */ 2197 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2198 struct amdgpu_job *job, 2199 struct amdgpu_ib *ib, 2200 uint32_t flags) 2201 { 2202 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2203 u32 header, control = 0; 2204 2205 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2206 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2207 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2208 amdgpu_ring_write(ring, 0); 2209 } 2210 2211 if (ib->flags & AMDGPU_IB_FLAG_CE) 2212 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2213 else 2214 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2215 2216 control |= ib->length_dw | (vmid << 24); 2217 2218 amdgpu_ring_write(ring, header); 2219 amdgpu_ring_write(ring, 2220 #ifdef __BIG_ENDIAN 2221 (2 << 0) | 2222 #endif 2223 (ib->gpu_addr & 0xFFFFFFFC)); 2224 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2225 amdgpu_ring_write(ring, control); 2226 } 2227 2228 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2229 struct amdgpu_job *job, 2230 struct amdgpu_ib *ib, 2231 uint32_t flags) 2232 { 2233 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2234 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2235 2236 /* Currently, there is a high possibility to get wave ID mismatch 2237 * between ME and GDS, leading to a hw deadlock, because ME generates 2238 * different wave IDs than the GDS expects. This situation happens 2239 * randomly when at least 5 compute pipes use GDS ordered append. 2240 * The wave IDs generated by ME are also wrong after suspend/resume. 2241 * Those are probably bugs somewhere else in the kernel driver. 2242 * 2243 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2244 * GDS to 0 for this ring (me/pipe). 2245 */ 2246 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2247 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2248 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 2249 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2250 } 2251 2252 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2253 amdgpu_ring_write(ring, 2254 #ifdef __BIG_ENDIAN 2255 (2 << 0) | 2256 #endif 2257 (ib->gpu_addr & 0xFFFFFFFC)); 2258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2259 amdgpu_ring_write(ring, control); 2260 } 2261 2262 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2263 { 2264 uint32_t dw2 = 0; 2265 2266 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2267 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2268 gfx_v7_0_ring_emit_vgt_flush(ring); 2269 /* set load_global_config & load_global_uconfig */ 2270 dw2 |= 0x8001; 2271 /* set load_cs_sh_regs */ 2272 dw2 |= 0x01000000; 2273 /* set load_per_context_state & load_gfx_sh_regs */ 2274 dw2 |= 0x10002; 2275 } 2276 2277 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2278 amdgpu_ring_write(ring, dw2); 2279 amdgpu_ring_write(ring, 0); 2280 } 2281 2282 /** 2283 * gfx_v7_0_ring_test_ib - basic ring IB test 2284 * 2285 * @ring: amdgpu_ring structure holding ring information 2286 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 2287 * 2288 * Allocate an IB and execute it on the gfx ring (CIK). 2289 * Provides a basic gfx ring test to verify that IBs are working. 2290 * Returns 0 on success, error on failure. 2291 */ 2292 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2293 { 2294 struct amdgpu_device *adev = ring->adev; 2295 struct amdgpu_ib ib; 2296 struct dma_fence *f = NULL; 2297 uint32_t tmp = 0; 2298 long r; 2299 2300 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2301 memset(&ib, 0, sizeof(ib)); 2302 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 2303 if (r) 2304 return r; 2305 2306 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2307 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; 2308 ib.ptr[2] = 0xDEADBEEF; 2309 ib.length_dw = 3; 2310 2311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2312 if (r) 2313 goto error; 2314 2315 r = dma_fence_wait_timeout(f, false, timeout); 2316 if (r == 0) { 2317 r = -ETIMEDOUT; 2318 goto error; 2319 } else if (r < 0) { 2320 goto error; 2321 } 2322 tmp = RREG32(mmSCRATCH_REG0); 2323 if (tmp == 0xDEADBEEF) 2324 r = 0; 2325 else 2326 r = -EINVAL; 2327 2328 error: 2329 amdgpu_ib_free(adev, &ib, NULL); 2330 dma_fence_put(f); 2331 return r; 2332 } 2333 2334 /* 2335 * CP. 2336 * On CIK, gfx and compute now have independent command processors. 2337 * 2338 * GFX 2339 * Gfx consists of a single ring and can process both gfx jobs and 2340 * compute jobs. The gfx CP consists of three microengines (ME): 2341 * PFP - Pre-Fetch Parser 2342 * ME - Micro Engine 2343 * CE - Constant Engine 2344 * The PFP and ME make up what is considered the Drawing Engine (DE). 2345 * The CE is an asynchronous engine used for updating buffer desciptors 2346 * used by the DE so that they can be loaded into cache in parallel 2347 * while the DE is processing state update packets. 2348 * 2349 * Compute 2350 * The compute CP consists of two microengines (ME): 2351 * MEC1 - Compute MicroEngine 1 2352 * MEC2 - Compute MicroEngine 2 2353 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2354 * The queues are exposed to userspace and are programmed directly 2355 * by the compute runtime. 2356 */ 2357 /** 2358 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2359 * 2360 * @adev: amdgpu_device pointer 2361 * @enable: enable or disable the MEs 2362 * 2363 * Halts or unhalts the gfx MEs. 2364 */ 2365 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2366 { 2367 if (enable) 2368 WREG32(mmCP_ME_CNTL, 0); 2369 else 2370 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2371 CP_ME_CNTL__PFP_HALT_MASK | 2372 CP_ME_CNTL__CE_HALT_MASK)); 2373 udelay(50); 2374 } 2375 2376 /** 2377 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2378 * 2379 * @adev: amdgpu_device pointer 2380 * 2381 * Loads the gfx PFP, ME, and CE ucode. 2382 * Returns 0 for success, -EINVAL if the ucode is not available. 2383 */ 2384 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2385 { 2386 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2387 const struct gfx_firmware_header_v1_0 *ce_hdr; 2388 const struct gfx_firmware_header_v1_0 *me_hdr; 2389 const __le32 *fw_data; 2390 unsigned i, fw_size; 2391 2392 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2393 return -EINVAL; 2394 2395 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2396 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2397 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2398 2399 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2400 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2401 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2402 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2403 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2404 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2405 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2406 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2407 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2408 2409 gfx_v7_0_cp_gfx_enable(adev, false); 2410 2411 /* PFP */ 2412 fw_data = (const __le32 *) 2413 (adev->gfx.pfp_fw->data + 2414 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2415 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2416 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2417 for (i = 0; i < fw_size; i++) 2418 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2419 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2420 2421 /* CE */ 2422 fw_data = (const __le32 *) 2423 (adev->gfx.ce_fw->data + 2424 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2425 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2426 WREG32(mmCP_CE_UCODE_ADDR, 0); 2427 for (i = 0; i < fw_size; i++) 2428 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2429 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2430 2431 /* ME */ 2432 fw_data = (const __le32 *) 2433 (adev->gfx.me_fw->data + 2434 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2435 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2436 WREG32(mmCP_ME_RAM_WADDR, 0); 2437 for (i = 0; i < fw_size; i++) 2438 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2439 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2440 2441 return 0; 2442 } 2443 2444 /** 2445 * gfx_v7_0_cp_gfx_start - start the gfx ring 2446 * 2447 * @adev: amdgpu_device pointer 2448 * 2449 * Enables the ring and loads the clear state context and other 2450 * packets required to init the ring. 2451 * Returns 0 for success, error for failure. 2452 */ 2453 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2454 { 2455 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2456 const struct cs_section_def *sect = NULL; 2457 const struct cs_extent_def *ext = NULL; 2458 int r, i; 2459 2460 /* init the CP */ 2461 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2462 WREG32(mmCP_ENDIAN_SWAP, 0); 2463 WREG32(mmCP_DEVICE_ID, 1); 2464 2465 gfx_v7_0_cp_gfx_enable(adev, true); 2466 2467 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2468 if (r) { 2469 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2470 return r; 2471 } 2472 2473 /* init the CE partitions. CE only used for gfx on CIK */ 2474 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2475 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2476 amdgpu_ring_write(ring, 0x8000); 2477 amdgpu_ring_write(ring, 0x8000); 2478 2479 /* clear state buffer */ 2480 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2481 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2482 2483 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2484 amdgpu_ring_write(ring, 0x80000000); 2485 amdgpu_ring_write(ring, 0x80000000); 2486 2487 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2488 for (ext = sect->section; ext->extent != NULL; ++ext) { 2489 if (sect->id == SECT_CONTEXT) { 2490 amdgpu_ring_write(ring, 2491 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2492 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2493 for (i = 0; i < ext->reg_count; i++) 2494 amdgpu_ring_write(ring, ext->extent[i]); 2495 } 2496 } 2497 } 2498 2499 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2500 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2501 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2502 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2503 2504 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2505 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2506 2507 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2508 amdgpu_ring_write(ring, 0); 2509 2510 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2511 amdgpu_ring_write(ring, 0x00000316); 2512 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2513 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2514 2515 amdgpu_ring_commit(ring); 2516 2517 return 0; 2518 } 2519 2520 /** 2521 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2522 * 2523 * @adev: amdgpu_device pointer 2524 * 2525 * Program the location and size of the gfx ring buffer 2526 * and test it to make sure it's working. 2527 * Returns 0 for success, error for failure. 2528 */ 2529 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2530 { 2531 struct amdgpu_ring *ring; 2532 u32 tmp; 2533 u32 rb_bufsz; 2534 u64 rb_addr, rptr_addr; 2535 int r; 2536 2537 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2538 if (adev->asic_type != CHIP_HAWAII) 2539 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2540 2541 /* Set the write pointer delay */ 2542 WREG32(mmCP_RB_WPTR_DELAY, 0); 2543 2544 /* set the RB to use vmid 0 */ 2545 WREG32(mmCP_RB_VMID, 0); 2546 2547 WREG32(mmSCRATCH_ADDR, 0); 2548 2549 /* ring 0 - compute and gfx */ 2550 /* Set ring buffer size */ 2551 ring = &adev->gfx.gfx_ring[0]; 2552 rb_bufsz = order_base_2(ring->ring_size / 8); 2553 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2554 #ifdef __BIG_ENDIAN 2555 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2556 #endif 2557 WREG32(mmCP_RB0_CNTL, tmp); 2558 2559 /* Initialize the ring buffer's read and write pointers */ 2560 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2561 ring->wptr = 0; 2562 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2563 2564 /* set the wb address wether it's enabled or not */ 2565 rptr_addr = ring->rptr_gpu_addr; 2566 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2567 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2568 2569 /* scratch register shadowing is no longer supported */ 2570 WREG32(mmSCRATCH_UMSK, 0); 2571 2572 mdelay(1); 2573 WREG32(mmCP_RB0_CNTL, tmp); 2574 2575 rb_addr = ring->gpu_addr >> 8; 2576 WREG32(mmCP_RB0_BASE, rb_addr); 2577 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2578 2579 /* start the ring */ 2580 gfx_v7_0_cp_gfx_start(adev); 2581 r = amdgpu_ring_test_helper(ring); 2582 if (r) 2583 return r; 2584 2585 return 0; 2586 } 2587 2588 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2589 { 2590 return *ring->rptr_cpu_addr; 2591 } 2592 2593 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2594 { 2595 struct amdgpu_device *adev = ring->adev; 2596 2597 return RREG32(mmCP_RB0_WPTR); 2598 } 2599 2600 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2601 { 2602 struct amdgpu_device *adev = ring->adev; 2603 2604 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2605 (void)RREG32(mmCP_RB0_WPTR); 2606 } 2607 2608 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2609 { 2610 /* XXX check if swapping is necessary on BE */ 2611 return *ring->wptr_cpu_addr; 2612 } 2613 2614 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2615 { 2616 struct amdgpu_device *adev = ring->adev; 2617 2618 /* XXX check if swapping is necessary on BE */ 2619 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2620 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2621 } 2622 2623 /** 2624 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2625 * 2626 * @adev: amdgpu_device pointer 2627 * @enable: enable or disable the MEs 2628 * 2629 * Halts or unhalts the compute MEs. 2630 */ 2631 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2632 { 2633 if (enable) 2634 WREG32(mmCP_MEC_CNTL, 0); 2635 else 2636 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2637 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2638 udelay(50); 2639 } 2640 2641 /** 2642 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2643 * 2644 * @adev: amdgpu_device pointer 2645 * 2646 * Loads the compute MEC1&2 ucode. 2647 * Returns 0 for success, -EINVAL if the ucode is not available. 2648 */ 2649 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2650 { 2651 const struct gfx_firmware_header_v1_0 *mec_hdr; 2652 const __le32 *fw_data; 2653 unsigned i, fw_size; 2654 2655 if (!adev->gfx.mec_fw) 2656 return -EINVAL; 2657 2658 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2659 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2660 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2661 adev->gfx.mec_feature_version = le32_to_cpu( 2662 mec_hdr->ucode_feature_version); 2663 2664 gfx_v7_0_cp_compute_enable(adev, false); 2665 2666 /* MEC1 */ 2667 fw_data = (const __le32 *) 2668 (adev->gfx.mec_fw->data + 2669 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2670 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2671 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2672 for (i = 0; i < fw_size; i++) 2673 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2674 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2675 2676 if (adev->asic_type == CHIP_KAVERI) { 2677 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2678 2679 if (!adev->gfx.mec2_fw) 2680 return -EINVAL; 2681 2682 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2683 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2684 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2685 adev->gfx.mec2_feature_version = le32_to_cpu( 2686 mec2_hdr->ucode_feature_version); 2687 2688 /* MEC2 */ 2689 fw_data = (const __le32 *) 2690 (adev->gfx.mec2_fw->data + 2691 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2692 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2693 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2694 for (i = 0; i < fw_size; i++) 2695 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2696 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2697 } 2698 2699 return 0; 2700 } 2701 2702 /** 2703 * gfx_v7_0_cp_compute_fini - stop the compute queues 2704 * 2705 * @adev: amdgpu_device pointer 2706 * 2707 * Stop the compute queues and tear down the driver queue 2708 * info. 2709 */ 2710 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2711 { 2712 int i; 2713 2714 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2715 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2716 2717 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); 2718 } 2719 } 2720 2721 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2722 { 2723 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2724 } 2725 2726 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2727 { 2728 int r; 2729 u32 *hpd; 2730 size_t mec_hpd_size; 2731 2732 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2733 2734 /* take ownership of the relevant compute queues */ 2735 amdgpu_gfx_compute_queue_acquire(adev); 2736 2737 /* allocate space for ALL pipes (even the ones we don't own) */ 2738 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2739 * GFX7_MEC_HPD_SIZE * 2; 2740 2741 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2742 AMDGPU_GEM_DOMAIN_VRAM | 2743 AMDGPU_GEM_DOMAIN_GTT, 2744 &adev->gfx.mec.hpd_eop_obj, 2745 &adev->gfx.mec.hpd_eop_gpu_addr, 2746 (void **)&hpd); 2747 if (r) { 2748 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2749 gfx_v7_0_mec_fini(adev); 2750 return r; 2751 } 2752 2753 /* clear memory. Not sure if this is required or not */ 2754 memset(hpd, 0, mec_hpd_size); 2755 2756 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2757 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2758 2759 return 0; 2760 } 2761 2762 struct hqd_registers 2763 { 2764 u32 cp_mqd_base_addr; 2765 u32 cp_mqd_base_addr_hi; 2766 u32 cp_hqd_active; 2767 u32 cp_hqd_vmid; 2768 u32 cp_hqd_persistent_state; 2769 u32 cp_hqd_pipe_priority; 2770 u32 cp_hqd_queue_priority; 2771 u32 cp_hqd_quantum; 2772 u32 cp_hqd_pq_base; 2773 u32 cp_hqd_pq_base_hi; 2774 u32 cp_hqd_pq_rptr; 2775 u32 cp_hqd_pq_rptr_report_addr; 2776 u32 cp_hqd_pq_rptr_report_addr_hi; 2777 u32 cp_hqd_pq_wptr_poll_addr; 2778 u32 cp_hqd_pq_wptr_poll_addr_hi; 2779 u32 cp_hqd_pq_doorbell_control; 2780 u32 cp_hqd_pq_wptr; 2781 u32 cp_hqd_pq_control; 2782 u32 cp_hqd_ib_base_addr; 2783 u32 cp_hqd_ib_base_addr_hi; 2784 u32 cp_hqd_ib_rptr; 2785 u32 cp_hqd_ib_control; 2786 u32 cp_hqd_iq_timer; 2787 u32 cp_hqd_iq_rptr; 2788 u32 cp_hqd_dequeue_request; 2789 u32 cp_hqd_dma_offload; 2790 u32 cp_hqd_sema_cmd; 2791 u32 cp_hqd_msg_type; 2792 u32 cp_hqd_atomic0_preop_lo; 2793 u32 cp_hqd_atomic0_preop_hi; 2794 u32 cp_hqd_atomic1_preop_lo; 2795 u32 cp_hqd_atomic1_preop_hi; 2796 u32 cp_hqd_hq_scheduler0; 2797 u32 cp_hqd_hq_scheduler1; 2798 u32 cp_mqd_control; 2799 }; 2800 2801 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2802 int mec, int pipe) 2803 { 2804 u64 eop_gpu_addr; 2805 u32 tmp; 2806 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2807 * GFX7_MEC_HPD_SIZE * 2; 2808 2809 mutex_lock(&adev->srbm_mutex); 2810 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2811 2812 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2813 2814 /* write the EOP addr */ 2815 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2816 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2817 2818 /* set the VMID assigned */ 2819 WREG32(mmCP_HPD_EOP_VMID, 0); 2820 2821 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2822 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2823 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2824 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2825 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2826 2827 cik_srbm_select(adev, 0, 0, 0, 0); 2828 mutex_unlock(&adev->srbm_mutex); 2829 } 2830 2831 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) 2832 { 2833 int i; 2834 2835 /* disable the queue if it's active */ 2836 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2837 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2838 for (i = 0; i < adev->usec_timeout; i++) { 2839 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2840 break; 2841 udelay(1); 2842 } 2843 2844 if (i == adev->usec_timeout) 2845 return -ETIMEDOUT; 2846 2847 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2848 WREG32(mmCP_HQD_PQ_RPTR, 0); 2849 WREG32(mmCP_HQD_PQ_WPTR, 0); 2850 } 2851 2852 return 0; 2853 } 2854 2855 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2856 struct cik_mqd *mqd, 2857 uint64_t mqd_gpu_addr, 2858 struct amdgpu_ring *ring) 2859 { 2860 u64 hqd_gpu_addr; 2861 u64 wb_gpu_addr; 2862 2863 /* init the mqd struct */ 2864 memset(mqd, 0, sizeof(struct cik_mqd)); 2865 2866 mqd->header = 0xC0310800; 2867 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2868 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2869 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2870 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2871 2872 /* enable doorbell? */ 2873 mqd->cp_hqd_pq_doorbell_control = 2874 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2875 if (ring->use_doorbell) 2876 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2877 else 2878 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2879 2880 /* set the pointer to the MQD */ 2881 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2882 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2883 2884 /* set MQD vmid to 0 */ 2885 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2886 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2887 2888 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2889 hqd_gpu_addr = ring->gpu_addr >> 8; 2890 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2891 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2892 2893 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2894 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2895 mqd->cp_hqd_pq_control &= 2896 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2897 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2898 2899 mqd->cp_hqd_pq_control |= 2900 order_base_2(ring->ring_size / 8); 2901 mqd->cp_hqd_pq_control |= 2902 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2903 #ifdef __BIG_ENDIAN 2904 mqd->cp_hqd_pq_control |= 2905 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2906 #endif 2907 mqd->cp_hqd_pq_control &= 2908 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2909 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2910 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2911 mqd->cp_hqd_pq_control |= 2912 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2913 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2914 2915 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2916 wb_gpu_addr = ring->wptr_gpu_addr; 2917 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2918 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2919 2920 /* set the wb address wether it's enabled or not */ 2921 wb_gpu_addr = ring->rptr_gpu_addr; 2922 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2923 mqd->cp_hqd_pq_rptr_report_addr_hi = 2924 upper_32_bits(wb_gpu_addr) & 0xffff; 2925 2926 /* enable the doorbell if requested */ 2927 if (ring->use_doorbell) { 2928 mqd->cp_hqd_pq_doorbell_control = 2929 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2930 mqd->cp_hqd_pq_doorbell_control &= 2931 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2932 mqd->cp_hqd_pq_doorbell_control |= 2933 (ring->doorbell_index << 2934 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2935 mqd->cp_hqd_pq_doorbell_control |= 2936 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2937 mqd->cp_hqd_pq_doorbell_control &= 2938 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 2939 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 2940 2941 } else { 2942 mqd->cp_hqd_pq_doorbell_control = 0; 2943 } 2944 2945 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2946 ring->wptr = 0; 2947 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 2948 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2949 2950 /* set the vmid for the queue */ 2951 mqd->cp_hqd_vmid = 0; 2952 2953 /* defaults */ 2954 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 2955 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 2956 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 2957 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 2958 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 2959 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 2960 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 2961 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 2962 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 2963 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 2964 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 2965 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2966 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 2967 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 2968 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 2969 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 2970 2971 /* activate the queue */ 2972 mqd->cp_hqd_active = 1; 2973 } 2974 2975 static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 2976 { 2977 uint32_t tmp; 2978 uint32_t mqd_reg; 2979 uint32_t *mqd_data; 2980 2981 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 2982 mqd_data = &mqd->cp_mqd_base_addr_lo; 2983 2984 /* disable wptr polling */ 2985 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 2986 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2987 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 2988 2989 /* program all HQD registers */ 2990 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 2991 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2992 2993 /* activate the HQD */ 2994 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 2995 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2996 2997 return 0; 2998 } 2999 3000 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 3001 { 3002 int r; 3003 u64 mqd_gpu_addr; 3004 struct cik_mqd *mqd; 3005 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3006 3007 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, 3008 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 3009 &mqd_gpu_addr, (void **)&mqd); 3010 if (r) { 3011 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3012 return r; 3013 } 3014 3015 mutex_lock(&adev->srbm_mutex); 3016 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3017 3018 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); 3019 gfx_v7_0_mqd_deactivate(adev); 3020 gfx_v7_0_mqd_commit(adev, mqd); 3021 3022 cik_srbm_select(adev, 0, 0, 0, 0); 3023 mutex_unlock(&adev->srbm_mutex); 3024 3025 amdgpu_bo_kunmap(ring->mqd_obj); 3026 amdgpu_bo_unreserve(ring->mqd_obj); 3027 return 0; 3028 } 3029 3030 /** 3031 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 3032 * 3033 * @adev: amdgpu_device pointer 3034 * 3035 * Program the compute queues and test them to make sure they 3036 * are working. 3037 * Returns 0 for success, error for failure. 3038 */ 3039 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3040 { 3041 int r, i, j; 3042 u32 tmp; 3043 struct amdgpu_ring *ring; 3044 3045 /* fix up chicken bits */ 3046 tmp = RREG32(mmCP_CPF_DEBUG); 3047 tmp |= (1 << 23); 3048 WREG32(mmCP_CPF_DEBUG, tmp); 3049 3050 /* init all pipes (even the ones we don't own) */ 3051 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3052 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3053 gfx_v7_0_compute_pipe_init(adev, i, j); 3054 3055 /* init the queues */ 3056 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3057 r = gfx_v7_0_compute_queue_init(adev, i); 3058 if (r) { 3059 gfx_v7_0_cp_compute_fini(adev); 3060 return r; 3061 } 3062 } 3063 3064 gfx_v7_0_cp_compute_enable(adev, true); 3065 3066 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3067 ring = &adev->gfx.compute_ring[i]; 3068 amdgpu_ring_test_helper(ring); 3069 } 3070 3071 return 0; 3072 } 3073 3074 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3075 { 3076 gfx_v7_0_cp_gfx_enable(adev, enable); 3077 gfx_v7_0_cp_compute_enable(adev, enable); 3078 } 3079 3080 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3081 { 3082 int r; 3083 3084 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3085 if (r) 3086 return r; 3087 r = gfx_v7_0_cp_compute_load_microcode(adev); 3088 if (r) 3089 return r; 3090 3091 return 0; 3092 } 3093 3094 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3095 bool enable) 3096 { 3097 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3098 3099 if (enable) 3100 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3101 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3102 else 3103 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3104 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3105 WREG32(mmCP_INT_CNTL_RING0, tmp); 3106 } 3107 3108 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3109 { 3110 int r; 3111 3112 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3113 3114 r = gfx_v7_0_cp_load_microcode(adev); 3115 if (r) 3116 return r; 3117 3118 r = gfx_v7_0_cp_gfx_resume(adev); 3119 if (r) 3120 return r; 3121 r = gfx_v7_0_cp_compute_resume(adev); 3122 if (r) 3123 return r; 3124 3125 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3126 3127 return 0; 3128 } 3129 3130 /** 3131 * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP 3132 * 3133 * @ring: the ring to emit the commands to 3134 * 3135 * Sync the command pipeline with the PFP. E.g. wait for everything 3136 * to be completed. 3137 */ 3138 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3139 { 3140 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3141 uint32_t seq = ring->fence_drv.sync_seq; 3142 uint64_t addr = ring->fence_drv.gpu_addr; 3143 3144 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3145 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3146 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3147 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3148 amdgpu_ring_write(ring, addr & 0xfffffffc); 3149 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3150 amdgpu_ring_write(ring, seq); 3151 amdgpu_ring_write(ring, 0xffffffff); 3152 amdgpu_ring_write(ring, 4); /* poll interval */ 3153 3154 if (usepfp) { 3155 /* sync CE with ME to prevent CE fetch CEIB before context switch done */ 3156 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3157 amdgpu_ring_write(ring, 0); 3158 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3159 amdgpu_ring_write(ring, 0); 3160 } 3161 } 3162 3163 /* 3164 * vm 3165 * VMID 0 is the physical GPU addresses as used by the kernel. 3166 * VMIDs 1-15 are used for userspace clients and are handled 3167 * by the amdgpu vm/hsa code. 3168 */ 3169 /** 3170 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3171 * 3172 * @ring: amdgpu_ring pointer 3173 * @vmid: vmid number to use 3174 * @pd_addr: address 3175 * 3176 * Update the page table base and flush the VM TLB 3177 * using the CP (CIK). 3178 */ 3179 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3180 unsigned vmid, uint64_t pd_addr) 3181 { 3182 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3183 3184 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3185 3186 /* wait for the invalidate to complete */ 3187 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3188 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3189 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3190 WAIT_REG_MEM_ENGINE(0))); /* me */ 3191 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3192 amdgpu_ring_write(ring, 0); 3193 amdgpu_ring_write(ring, 0); /* ref */ 3194 amdgpu_ring_write(ring, 0); /* mask */ 3195 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3196 3197 /* compute doesn't have PFP */ 3198 if (usepfp) { 3199 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3200 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3201 amdgpu_ring_write(ring, 0x0); 3202 3203 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3204 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3205 amdgpu_ring_write(ring, 0); 3206 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3207 amdgpu_ring_write(ring, 0); 3208 } 3209 } 3210 3211 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 3212 uint32_t reg, uint32_t val) 3213 { 3214 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3215 3216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3217 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3218 WRITE_DATA_DST_SEL(0))); 3219 amdgpu_ring_write(ring, reg); 3220 amdgpu_ring_write(ring, 0); 3221 amdgpu_ring_write(ring, val); 3222 } 3223 3224 /* 3225 * RLC 3226 * The RLC is a multi-purpose microengine that handles a 3227 * variety of functions. 3228 */ 3229 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3230 { 3231 const u32 *src_ptr; 3232 u32 dws; 3233 const struct cs_section_def *cs_data; 3234 int r; 3235 3236 /* allocate rlc buffers */ 3237 if (adev->flags & AMD_IS_APU) { 3238 if (adev->asic_type == CHIP_KAVERI) { 3239 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3240 adev->gfx.rlc.reg_list_size = 3241 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3242 } else { 3243 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3244 adev->gfx.rlc.reg_list_size = 3245 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3246 } 3247 } 3248 adev->gfx.rlc.cs_data = ci_cs_data; 3249 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3250 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3251 3252 src_ptr = adev->gfx.rlc.reg_list; 3253 dws = adev->gfx.rlc.reg_list_size; 3254 dws += (5 * 16) + 48 + 48 + 64; 3255 3256 cs_data = adev->gfx.rlc.cs_data; 3257 3258 if (src_ptr) { 3259 /* init save restore block */ 3260 r = amdgpu_gfx_rlc_init_sr(adev, dws); 3261 if (r) 3262 return r; 3263 } 3264 3265 if (cs_data) { 3266 /* init clear state block */ 3267 r = amdgpu_gfx_rlc_init_csb(adev); 3268 if (r) 3269 return r; 3270 } 3271 3272 if (adev->gfx.rlc.cp_table_size) { 3273 r = amdgpu_gfx_rlc_init_cpt(adev); 3274 if (r) 3275 return r; 3276 } 3277 3278 /* init spm vmid with 0xf */ 3279 if (adev->gfx.rlc.funcs->update_spm_vmid) 3280 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 3281 3282 return 0; 3283 } 3284 3285 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3286 { 3287 u32 tmp; 3288 3289 tmp = RREG32(mmRLC_LB_CNTL); 3290 if (enable) 3291 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3292 else 3293 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3294 WREG32(mmRLC_LB_CNTL, tmp); 3295 } 3296 3297 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3298 { 3299 u32 i, j, k; 3300 u32 mask; 3301 3302 mutex_lock(&adev->grbm_idx_mutex); 3303 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3304 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3305 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3306 for (k = 0; k < adev->usec_timeout; k++) { 3307 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3308 break; 3309 udelay(1); 3310 } 3311 } 3312 } 3313 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3314 mutex_unlock(&adev->grbm_idx_mutex); 3315 3316 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3317 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3318 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3319 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3320 for (k = 0; k < adev->usec_timeout; k++) { 3321 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3322 break; 3323 udelay(1); 3324 } 3325 } 3326 3327 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3328 { 3329 u32 tmp; 3330 3331 tmp = RREG32(mmRLC_CNTL); 3332 if (tmp != rlc) 3333 WREG32(mmRLC_CNTL, rlc); 3334 } 3335 3336 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3337 { 3338 u32 data, orig; 3339 3340 orig = data = RREG32(mmRLC_CNTL); 3341 3342 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3343 u32 i; 3344 3345 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3346 WREG32(mmRLC_CNTL, data); 3347 3348 for (i = 0; i < adev->usec_timeout; i++) { 3349 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3350 break; 3351 udelay(1); 3352 } 3353 3354 gfx_v7_0_wait_for_rlc_serdes(adev); 3355 } 3356 3357 return orig; 3358 } 3359 3360 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 3361 { 3362 return true; 3363 } 3364 3365 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 3366 { 3367 u32 tmp, i, mask; 3368 3369 tmp = 0x1 | (1 << 1); 3370 WREG32(mmRLC_GPR_REG2, tmp); 3371 3372 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3373 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3374 for (i = 0; i < adev->usec_timeout; i++) { 3375 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3376 break; 3377 udelay(1); 3378 } 3379 3380 for (i = 0; i < adev->usec_timeout; i++) { 3381 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3382 break; 3383 udelay(1); 3384 } 3385 } 3386 3387 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) 3388 { 3389 u32 tmp; 3390 3391 tmp = 0x1 | (0 << 1); 3392 WREG32(mmRLC_GPR_REG2, tmp); 3393 } 3394 3395 /** 3396 * gfx_v7_0_rlc_stop - stop the RLC ME 3397 * 3398 * @adev: amdgpu_device pointer 3399 * 3400 * Halt the RLC ME (MicroEngine) (CIK). 3401 */ 3402 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3403 { 3404 WREG32(mmRLC_CNTL, 0); 3405 3406 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3407 3408 gfx_v7_0_wait_for_rlc_serdes(adev); 3409 } 3410 3411 /** 3412 * gfx_v7_0_rlc_start - start the RLC ME 3413 * 3414 * @adev: amdgpu_device pointer 3415 * 3416 * Unhalt the RLC ME (MicroEngine) (CIK). 3417 */ 3418 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3419 { 3420 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3421 3422 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3423 3424 udelay(50); 3425 } 3426 3427 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3428 { 3429 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3430 3431 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3432 WREG32(mmGRBM_SOFT_RESET, tmp); 3433 udelay(50); 3434 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3435 WREG32(mmGRBM_SOFT_RESET, tmp); 3436 udelay(50); 3437 } 3438 3439 /** 3440 * gfx_v7_0_rlc_resume - setup the RLC hw 3441 * 3442 * @adev: amdgpu_device pointer 3443 * 3444 * Initialize the RLC registers, load the ucode, 3445 * and start the RLC (CIK). 3446 * Returns 0 for success, -EINVAL if the ucode is not available. 3447 */ 3448 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3449 { 3450 const struct rlc_firmware_header_v1_0 *hdr; 3451 const __le32 *fw_data; 3452 unsigned i, fw_size; 3453 u32 tmp; 3454 3455 if (!adev->gfx.rlc_fw) 3456 return -EINVAL; 3457 3458 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3459 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3460 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3461 adev->gfx.rlc_feature_version = le32_to_cpu( 3462 hdr->ucode_feature_version); 3463 3464 adev->gfx.rlc.funcs->stop(adev); 3465 3466 /* disable CG */ 3467 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3468 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3469 3470 adev->gfx.rlc.funcs->reset(adev); 3471 3472 gfx_v7_0_init_pg(adev); 3473 3474 WREG32(mmRLC_LB_CNTR_INIT, 0); 3475 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3476 3477 mutex_lock(&adev->grbm_idx_mutex); 3478 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3479 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3480 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3481 WREG32(mmRLC_LB_CNTL, 0x80000004); 3482 mutex_unlock(&adev->grbm_idx_mutex); 3483 3484 WREG32(mmRLC_MC_CNTL, 0); 3485 WREG32(mmRLC_UCODE_CNTL, 0); 3486 3487 fw_data = (const __le32 *) 3488 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3489 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3490 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3491 for (i = 0; i < fw_size; i++) 3492 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3493 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3494 3495 /* XXX - find out what chips support lbpw */ 3496 gfx_v7_0_enable_lbpw(adev, false); 3497 3498 if (adev->asic_type == CHIP_BONAIRE) 3499 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3500 3501 adev->gfx.rlc.funcs->start(adev); 3502 3503 return 0; 3504 } 3505 3506 static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 3507 { 3508 u32 data; 3509 3510 amdgpu_gfx_off_ctrl(adev, false); 3511 3512 data = RREG32(mmRLC_SPM_VMID); 3513 3514 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK; 3515 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT; 3516 3517 WREG32(mmRLC_SPM_VMID, data); 3518 3519 amdgpu_gfx_off_ctrl(adev, true); 3520 } 3521 3522 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3523 { 3524 u32 data, orig, tmp, tmp2; 3525 3526 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3527 3528 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3529 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3530 3531 tmp = gfx_v7_0_halt_rlc(adev); 3532 3533 mutex_lock(&adev->grbm_idx_mutex); 3534 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3535 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3536 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3537 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3538 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3539 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3540 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3541 mutex_unlock(&adev->grbm_idx_mutex); 3542 3543 gfx_v7_0_update_rlc(adev, tmp); 3544 3545 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3546 if (orig != data) 3547 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3548 3549 } else { 3550 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3551 3552 RREG32(mmCB_CGTT_SCLK_CTRL); 3553 RREG32(mmCB_CGTT_SCLK_CTRL); 3554 RREG32(mmCB_CGTT_SCLK_CTRL); 3555 RREG32(mmCB_CGTT_SCLK_CTRL); 3556 3557 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3558 if (orig != data) 3559 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3560 3561 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3562 } 3563 } 3564 3565 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3566 { 3567 u32 data, orig, tmp = 0; 3568 3569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3570 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3571 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3572 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3573 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3574 if (orig != data) 3575 WREG32(mmCP_MEM_SLP_CNTL, data); 3576 } 3577 } 3578 3579 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3580 data |= 0x00000001; 3581 data &= 0xfffffffd; 3582 if (orig != data) 3583 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3584 3585 tmp = gfx_v7_0_halt_rlc(adev); 3586 3587 mutex_lock(&adev->grbm_idx_mutex); 3588 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3589 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3590 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3591 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3592 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3593 WREG32(mmRLC_SERDES_WR_CTRL, data); 3594 mutex_unlock(&adev->grbm_idx_mutex); 3595 3596 gfx_v7_0_update_rlc(adev, tmp); 3597 3598 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3599 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3600 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3601 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3602 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3603 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3604 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3605 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3606 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3607 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3608 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3609 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3610 if (orig != data) 3611 WREG32(mmCGTS_SM_CTRL_REG, data); 3612 } 3613 } else { 3614 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3615 data |= 0x00000003; 3616 if (orig != data) 3617 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3618 3619 data = RREG32(mmRLC_MEM_SLP_CNTL); 3620 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3621 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3622 WREG32(mmRLC_MEM_SLP_CNTL, data); 3623 } 3624 3625 data = RREG32(mmCP_MEM_SLP_CNTL); 3626 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3627 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3628 WREG32(mmCP_MEM_SLP_CNTL, data); 3629 } 3630 3631 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3632 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3633 if (orig != data) 3634 WREG32(mmCGTS_SM_CTRL_REG, data); 3635 3636 tmp = gfx_v7_0_halt_rlc(adev); 3637 3638 mutex_lock(&adev->grbm_idx_mutex); 3639 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3640 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3641 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3642 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3643 WREG32(mmRLC_SERDES_WR_CTRL, data); 3644 mutex_unlock(&adev->grbm_idx_mutex); 3645 3646 gfx_v7_0_update_rlc(adev, tmp); 3647 } 3648 } 3649 3650 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3651 bool enable) 3652 { 3653 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3654 /* order matters! */ 3655 if (enable) { 3656 gfx_v7_0_enable_mgcg(adev, true); 3657 gfx_v7_0_enable_cgcg(adev, true); 3658 } else { 3659 gfx_v7_0_enable_cgcg(adev, false); 3660 gfx_v7_0_enable_mgcg(adev, false); 3661 } 3662 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3663 } 3664 3665 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3666 bool enable) 3667 { 3668 u32 data, orig; 3669 3670 orig = data = RREG32(mmRLC_PG_CNTL); 3671 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3672 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3673 else 3674 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3675 if (orig != data) 3676 WREG32(mmRLC_PG_CNTL, data); 3677 } 3678 3679 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3680 bool enable) 3681 { 3682 u32 data, orig; 3683 3684 orig = data = RREG32(mmRLC_PG_CNTL); 3685 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3686 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3687 else 3688 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3689 if (orig != data) 3690 WREG32(mmRLC_PG_CNTL, data); 3691 } 3692 3693 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3694 { 3695 u32 data, orig; 3696 3697 orig = data = RREG32(mmRLC_PG_CNTL); 3698 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3699 data &= ~0x8000; 3700 else 3701 data |= 0x8000; 3702 if (orig != data) 3703 WREG32(mmRLC_PG_CNTL, data); 3704 } 3705 3706 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3707 { 3708 u32 data, orig; 3709 3710 orig = data = RREG32(mmRLC_PG_CNTL); 3711 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3712 data &= ~0x2000; 3713 else 3714 data |= 0x2000; 3715 if (orig != data) 3716 WREG32(mmRLC_PG_CNTL, data); 3717 } 3718 3719 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) 3720 { 3721 if (adev->asic_type == CHIP_KAVERI) 3722 return 5; 3723 else 3724 return 4; 3725 } 3726 3727 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3728 bool enable) 3729 { 3730 u32 data, orig; 3731 3732 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3733 orig = data = RREG32(mmRLC_PG_CNTL); 3734 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3735 if (orig != data) 3736 WREG32(mmRLC_PG_CNTL, data); 3737 3738 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3739 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3740 if (orig != data) 3741 WREG32(mmRLC_AUTO_PG_CTRL, data); 3742 } else { 3743 orig = data = RREG32(mmRLC_PG_CNTL); 3744 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3745 if (orig != data) 3746 WREG32(mmRLC_PG_CNTL, data); 3747 3748 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3749 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3750 if (orig != data) 3751 WREG32(mmRLC_AUTO_PG_CTRL, data); 3752 3753 data = RREG32(mmDB_RENDER_CONTROL); 3754 } 3755 } 3756 3757 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3758 u32 bitmap) 3759 { 3760 u32 data; 3761 3762 if (!bitmap) 3763 return; 3764 3765 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3766 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3767 3768 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3769 } 3770 3771 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3772 { 3773 u32 data, mask; 3774 3775 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3776 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3777 3778 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3779 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3780 3781 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3782 3783 return (~data) & mask; 3784 } 3785 3786 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3787 { 3788 u32 tmp; 3789 3790 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3791 3792 tmp = RREG32(mmRLC_MAX_PG_CU); 3793 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3794 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3795 WREG32(mmRLC_MAX_PG_CU, tmp); 3796 } 3797 3798 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3799 bool enable) 3800 { 3801 u32 data, orig; 3802 3803 orig = data = RREG32(mmRLC_PG_CNTL); 3804 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3805 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3806 else 3807 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3808 if (orig != data) 3809 WREG32(mmRLC_PG_CNTL, data); 3810 } 3811 3812 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3813 bool enable) 3814 { 3815 u32 data, orig; 3816 3817 orig = data = RREG32(mmRLC_PG_CNTL); 3818 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3819 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3820 else 3821 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3822 if (orig != data) 3823 WREG32(mmRLC_PG_CNTL, data); 3824 } 3825 3826 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3827 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3828 3829 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3830 { 3831 u32 data, orig; 3832 u32 i; 3833 3834 if (adev->gfx.rlc.cs_data) { 3835 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3836 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3837 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3838 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3839 } else { 3840 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3841 for (i = 0; i < 3; i++) 3842 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3843 } 3844 if (adev->gfx.rlc.reg_list) { 3845 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3846 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3847 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3848 } 3849 3850 orig = data = RREG32(mmRLC_PG_CNTL); 3851 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3852 if (orig != data) 3853 WREG32(mmRLC_PG_CNTL, data); 3854 3855 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3856 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3857 3858 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3859 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3860 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3861 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3862 3863 data = 0x10101010; 3864 WREG32(mmRLC_PG_DELAY, data); 3865 3866 data = RREG32(mmRLC_PG_DELAY_2); 3867 data &= ~0xff; 3868 data |= 0x3; 3869 WREG32(mmRLC_PG_DELAY_2, data); 3870 3871 data = RREG32(mmRLC_AUTO_PG_CTRL); 3872 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3873 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3874 WREG32(mmRLC_AUTO_PG_CTRL, data); 3875 3876 } 3877 3878 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3879 { 3880 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3881 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3882 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3883 } 3884 3885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3886 { 3887 u32 count = 0; 3888 const struct cs_section_def *sect = NULL; 3889 const struct cs_extent_def *ext = NULL; 3890 3891 if (adev->gfx.rlc.cs_data == NULL) 3892 return 0; 3893 3894 /* begin clear state */ 3895 count += 2; 3896 /* context control state */ 3897 count += 3; 3898 3899 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3900 for (ext = sect->section; ext->extent != NULL; ++ext) { 3901 if (sect->id == SECT_CONTEXT) 3902 count += 2 + ext->reg_count; 3903 else 3904 return 0; 3905 } 3906 } 3907 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3908 count += 4; 3909 /* end clear state */ 3910 count += 2; 3911 /* clear state */ 3912 count += 2; 3913 3914 return count; 3915 } 3916 3917 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 3918 volatile u32 *buffer) 3919 { 3920 u32 count = 0, i; 3921 const struct cs_section_def *sect = NULL; 3922 const struct cs_extent_def *ext = NULL; 3923 3924 if (adev->gfx.rlc.cs_data == NULL) 3925 return; 3926 if (buffer == NULL) 3927 return; 3928 3929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3930 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3931 3932 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3933 buffer[count++] = cpu_to_le32(0x80000000); 3934 buffer[count++] = cpu_to_le32(0x80000000); 3935 3936 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3937 for (ext = sect->section; ext->extent != NULL; ++ext) { 3938 if (sect->id == SECT_CONTEXT) { 3939 buffer[count++] = 3940 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 3941 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3942 for (i = 0; i < ext->reg_count; i++) 3943 buffer[count++] = cpu_to_le32(ext->extent[i]); 3944 } else { 3945 return; 3946 } 3947 } 3948 } 3949 3950 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 3951 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3952 switch (adev->asic_type) { 3953 case CHIP_BONAIRE: 3954 buffer[count++] = cpu_to_le32(0x16000012); 3955 buffer[count++] = cpu_to_le32(0x00000000); 3956 break; 3957 case CHIP_KAVERI: 3958 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 3959 buffer[count++] = cpu_to_le32(0x00000000); 3960 break; 3961 case CHIP_KABINI: 3962 case CHIP_MULLINS: 3963 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 3964 buffer[count++] = cpu_to_le32(0x00000000); 3965 break; 3966 case CHIP_HAWAII: 3967 buffer[count++] = cpu_to_le32(0x3a00161a); 3968 buffer[count++] = cpu_to_le32(0x0000002e); 3969 break; 3970 default: 3971 buffer[count++] = cpu_to_le32(0x00000000); 3972 buffer[count++] = cpu_to_le32(0x00000000); 3973 break; 3974 } 3975 3976 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3977 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 3978 3979 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 3980 buffer[count++] = cpu_to_le32(0); 3981 } 3982 3983 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 3984 { 3985 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3986 AMD_PG_SUPPORT_GFX_SMG | 3987 AMD_PG_SUPPORT_GFX_DMG | 3988 AMD_PG_SUPPORT_CP | 3989 AMD_PG_SUPPORT_GDS | 3990 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3991 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 3992 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 3993 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3994 gfx_v7_0_init_gfx_cgpg(adev); 3995 gfx_v7_0_enable_cp_pg(adev, true); 3996 gfx_v7_0_enable_gds_pg(adev, true); 3997 } 3998 gfx_v7_0_init_ao_cu_mask(adev); 3999 gfx_v7_0_update_gfx_pg(adev, true); 4000 } 4001 } 4002 4003 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4004 { 4005 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4006 AMD_PG_SUPPORT_GFX_SMG | 4007 AMD_PG_SUPPORT_GFX_DMG | 4008 AMD_PG_SUPPORT_CP | 4009 AMD_PG_SUPPORT_GDS | 4010 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4011 gfx_v7_0_update_gfx_pg(adev, false); 4012 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4013 gfx_v7_0_enable_cp_pg(adev, false); 4014 gfx_v7_0_enable_gds_pg(adev, false); 4015 } 4016 } 4017 } 4018 4019 /** 4020 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4021 * 4022 * @adev: amdgpu_device pointer 4023 * 4024 * Fetches a GPU clock counter snapshot (SI). 4025 * Returns the 64 bit clock counter snapshot. 4026 */ 4027 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4028 { 4029 uint64_t clock; 4030 4031 mutex_lock(&adev->gfx.gpu_clock_mutex); 4032 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4033 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4034 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4035 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4036 return clock; 4037 } 4038 4039 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4040 uint32_t vmid, 4041 uint32_t gds_base, uint32_t gds_size, 4042 uint32_t gws_base, uint32_t gws_size, 4043 uint32_t oa_base, uint32_t oa_size) 4044 { 4045 /* GDS Base */ 4046 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4047 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4048 WRITE_DATA_DST_SEL(0))); 4049 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4050 amdgpu_ring_write(ring, 0); 4051 amdgpu_ring_write(ring, gds_base); 4052 4053 /* GDS Size */ 4054 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4055 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4056 WRITE_DATA_DST_SEL(0))); 4057 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4058 amdgpu_ring_write(ring, 0); 4059 amdgpu_ring_write(ring, gds_size); 4060 4061 /* GWS */ 4062 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4063 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4064 WRITE_DATA_DST_SEL(0))); 4065 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4066 amdgpu_ring_write(ring, 0); 4067 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4068 4069 /* OA */ 4070 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4071 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4072 WRITE_DATA_DST_SEL(0))); 4073 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4074 amdgpu_ring_write(ring, 0); 4075 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4076 } 4077 4078 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4079 { 4080 struct amdgpu_device *adev = ring->adev; 4081 uint32_t value = 0; 4082 4083 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4084 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4085 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4086 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4087 WREG32(mmSQ_CMD, value); 4088 } 4089 4090 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4091 { 4092 WREG32(mmSQ_IND_INDEX, 4093 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4094 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4095 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4096 (SQ_IND_INDEX__FORCE_READ_MASK)); 4097 return RREG32(mmSQ_IND_DATA); 4098 } 4099 4100 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4101 uint32_t wave, uint32_t thread, 4102 uint32_t regno, uint32_t num, uint32_t *out) 4103 { 4104 WREG32(mmSQ_IND_INDEX, 4105 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4106 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4107 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4108 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4109 (SQ_IND_INDEX__FORCE_READ_MASK) | 4110 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4111 while (num--) 4112 *(out++) = RREG32(mmSQ_IND_DATA); 4113 } 4114 4115 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4116 { 4117 /* type 0 wave data */ 4118 dst[(*no_fields)++] = 0; 4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4121 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4122 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4123 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4124 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4125 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4126 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4127 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4128 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4129 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4130 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4131 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4132 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4133 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4134 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4135 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4136 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4137 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 4138 } 4139 4140 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 4141 uint32_t wave, uint32_t start, 4142 uint32_t size, uint32_t *dst) 4143 { 4144 wave_read_regs( 4145 adev, simd, wave, 0, 4146 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4147 } 4148 4149 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, 4150 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 4151 { 4152 cik_srbm_select(adev, me, pipe, q, vm); 4153 } 4154 4155 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4156 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4157 .select_se_sh = &gfx_v7_0_select_se_sh, 4158 .read_wave_data = &gfx_v7_0_read_wave_data, 4159 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4160 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q 4161 }; 4162 4163 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4164 .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, 4165 .set_safe_mode = gfx_v7_0_set_safe_mode, 4166 .unset_safe_mode = gfx_v7_0_unset_safe_mode, 4167 .init = gfx_v7_0_rlc_init, 4168 .get_csb_size = gfx_v7_0_get_csb_size, 4169 .get_csb_buffer = gfx_v7_0_get_csb_buffer, 4170 .get_cp_table_num = gfx_v7_0_cp_pg_table_num, 4171 .resume = gfx_v7_0_rlc_resume, 4172 .stop = gfx_v7_0_rlc_stop, 4173 .reset = gfx_v7_0_rlc_reset, 4174 .start = gfx_v7_0_rlc_start, 4175 .update_spm_vmid = gfx_v7_0_update_spm_vmid 4176 }; 4177 4178 static int gfx_v7_0_early_init(void *handle) 4179 { 4180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4181 4182 adev->gfx.xcc_mask = 1; 4183 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4184 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4185 AMDGPU_MAX_COMPUTE_RINGS); 4186 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4187 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4188 gfx_v7_0_set_ring_funcs(adev); 4189 gfx_v7_0_set_irq_funcs(adev); 4190 gfx_v7_0_set_gds_init(adev); 4191 4192 return 0; 4193 } 4194 4195 static int gfx_v7_0_late_init(void *handle) 4196 { 4197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4198 int r; 4199 4200 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4201 if (r) 4202 return r; 4203 4204 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4205 if (r) 4206 return r; 4207 4208 return 0; 4209 } 4210 4211 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4212 { 4213 u32 gb_addr_config; 4214 u32 mc_arb_ramcfg; 4215 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4216 u32 tmp; 4217 4218 switch (adev->asic_type) { 4219 case CHIP_BONAIRE: 4220 adev->gfx.config.max_shader_engines = 2; 4221 adev->gfx.config.max_tile_pipes = 4; 4222 adev->gfx.config.max_cu_per_sh = 7; 4223 adev->gfx.config.max_sh_per_se = 1; 4224 adev->gfx.config.max_backends_per_se = 2; 4225 adev->gfx.config.max_texture_channel_caches = 4; 4226 adev->gfx.config.max_gprs = 256; 4227 adev->gfx.config.max_gs_threads = 32; 4228 adev->gfx.config.max_hw_contexts = 8; 4229 4230 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4231 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4232 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4233 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4234 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4235 break; 4236 case CHIP_HAWAII: 4237 adev->gfx.config.max_shader_engines = 4; 4238 adev->gfx.config.max_tile_pipes = 16; 4239 adev->gfx.config.max_cu_per_sh = 11; 4240 adev->gfx.config.max_sh_per_se = 1; 4241 adev->gfx.config.max_backends_per_se = 4; 4242 adev->gfx.config.max_texture_channel_caches = 16; 4243 adev->gfx.config.max_gprs = 256; 4244 adev->gfx.config.max_gs_threads = 32; 4245 adev->gfx.config.max_hw_contexts = 8; 4246 4247 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4248 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4249 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4250 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4251 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4252 break; 4253 case CHIP_KAVERI: 4254 adev->gfx.config.max_shader_engines = 1; 4255 adev->gfx.config.max_tile_pipes = 4; 4256 adev->gfx.config.max_cu_per_sh = 8; 4257 adev->gfx.config.max_backends_per_se = 2; 4258 adev->gfx.config.max_sh_per_se = 1; 4259 adev->gfx.config.max_texture_channel_caches = 4; 4260 adev->gfx.config.max_gprs = 256; 4261 adev->gfx.config.max_gs_threads = 16; 4262 adev->gfx.config.max_hw_contexts = 8; 4263 4264 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4265 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4266 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4267 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4268 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4269 break; 4270 case CHIP_KABINI: 4271 case CHIP_MULLINS: 4272 default: 4273 adev->gfx.config.max_shader_engines = 1; 4274 adev->gfx.config.max_tile_pipes = 2; 4275 adev->gfx.config.max_cu_per_sh = 2; 4276 adev->gfx.config.max_sh_per_se = 1; 4277 adev->gfx.config.max_backends_per_se = 1; 4278 adev->gfx.config.max_texture_channel_caches = 2; 4279 adev->gfx.config.max_gprs = 256; 4280 adev->gfx.config.max_gs_threads = 16; 4281 adev->gfx.config.max_hw_contexts = 8; 4282 4283 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4284 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4285 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4286 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4287 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4288 break; 4289 } 4290 4291 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4292 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4293 4294 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, 4295 MC_ARB_RAMCFG, NOOFBANK); 4296 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, 4297 MC_ARB_RAMCFG, NOOFRANKS); 4298 4299 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4300 adev->gfx.config.mem_max_burst_length_bytes = 256; 4301 if (adev->flags & AMD_IS_APU) { 4302 /* Get memory bank mapping mode. */ 4303 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4304 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4305 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4306 4307 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4308 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4309 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4310 4311 /* Validate settings in case only one DIMM installed. */ 4312 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4313 dimm00_addr_map = 0; 4314 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4315 dimm01_addr_map = 0; 4316 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4317 dimm10_addr_map = 0; 4318 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4319 dimm11_addr_map = 0; 4320 4321 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4322 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4323 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4324 adev->gfx.config.mem_row_size_in_kb = 2; 4325 else 4326 adev->gfx.config.mem_row_size_in_kb = 1; 4327 } else { 4328 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4329 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4330 if (adev->gfx.config.mem_row_size_in_kb > 4) 4331 adev->gfx.config.mem_row_size_in_kb = 4; 4332 } 4333 /* XXX use MC settings? */ 4334 adev->gfx.config.shader_engine_tile_size = 32; 4335 adev->gfx.config.num_gpus = 1; 4336 adev->gfx.config.multi_gpu_tile_size = 64; 4337 4338 /* fix up row size */ 4339 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4340 switch (adev->gfx.config.mem_row_size_in_kb) { 4341 case 1: 4342 default: 4343 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4344 break; 4345 case 2: 4346 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4347 break; 4348 case 4: 4349 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4350 break; 4351 } 4352 adev->gfx.config.gb_addr_config = gb_addr_config; 4353 } 4354 4355 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4356 int mec, int pipe, int queue) 4357 { 4358 int r; 4359 unsigned irq_type; 4360 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4361 4362 /* mec0 is me1 */ 4363 ring->me = mec + 1; 4364 ring->pipe = pipe; 4365 ring->queue = queue; 4366 4367 ring->ring_obj = NULL; 4368 ring->use_doorbell = true; 4369 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 4370 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4371 4372 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4373 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4374 + ring->pipe; 4375 4376 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4377 r = amdgpu_ring_init(adev, ring, 1024, 4378 &adev->gfx.eop_irq, irq_type, 4379 AMDGPU_RING_PRIO_DEFAULT, NULL); 4380 if (r) 4381 return r; 4382 4383 4384 return 0; 4385 } 4386 4387 static int gfx_v7_0_sw_init(void *handle) 4388 { 4389 struct amdgpu_ring *ring; 4390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4391 int i, j, k, r, ring_id; 4392 4393 switch (adev->asic_type) { 4394 case CHIP_KAVERI: 4395 adev->gfx.mec.num_mec = 2; 4396 break; 4397 case CHIP_BONAIRE: 4398 case CHIP_HAWAII: 4399 case CHIP_KABINI: 4400 case CHIP_MULLINS: 4401 default: 4402 adev->gfx.mec.num_mec = 1; 4403 break; 4404 } 4405 adev->gfx.mec.num_pipe_per_mec = 4; 4406 adev->gfx.mec.num_queue_per_pipe = 8; 4407 4408 /* EOP Event */ 4409 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4410 if (r) 4411 return r; 4412 4413 /* Privileged reg */ 4414 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, 4415 &adev->gfx.priv_reg_irq); 4416 if (r) 4417 return r; 4418 4419 /* Privileged inst */ 4420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, 4421 &adev->gfx.priv_inst_irq); 4422 if (r) 4423 return r; 4424 4425 r = gfx_v7_0_init_microcode(adev); 4426 if (r) { 4427 DRM_ERROR("Failed to load gfx firmware!\n"); 4428 return r; 4429 } 4430 4431 r = adev->gfx.rlc.funcs->init(adev); 4432 if (r) { 4433 DRM_ERROR("Failed to init rlc BOs!\n"); 4434 return r; 4435 } 4436 4437 /* allocate mec buffers */ 4438 r = gfx_v7_0_mec_init(adev); 4439 if (r) { 4440 DRM_ERROR("Failed to init MEC BOs!\n"); 4441 return r; 4442 } 4443 4444 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4445 ring = &adev->gfx.gfx_ring[i]; 4446 ring->ring_obj = NULL; 4447 sprintf(ring->name, "gfx"); 4448 r = amdgpu_ring_init(adev, ring, 1024, 4449 &adev->gfx.eop_irq, 4450 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 4451 AMDGPU_RING_PRIO_DEFAULT, NULL); 4452 if (r) 4453 return r; 4454 } 4455 4456 /* set up the compute queues - allocate horizontally across pipes */ 4457 ring_id = 0; 4458 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4459 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4460 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4461 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, 4462 k, j)) 4463 continue; 4464 4465 r = gfx_v7_0_compute_ring_init(adev, 4466 ring_id, 4467 i, k, j); 4468 if (r) 4469 return r; 4470 4471 ring_id++; 4472 } 4473 } 4474 } 4475 4476 adev->gfx.ce_ram_size = 0x8000; 4477 4478 gfx_v7_0_gpu_early_init(adev); 4479 4480 return r; 4481 } 4482 4483 static int gfx_v7_0_sw_fini(void *handle) 4484 { 4485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4486 int i; 4487 4488 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4489 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4490 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4491 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4492 4493 gfx_v7_0_cp_compute_fini(adev); 4494 amdgpu_gfx_rlc_fini(adev); 4495 gfx_v7_0_mec_fini(adev); 4496 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4497 &adev->gfx.rlc.clear_state_gpu_addr, 4498 (void **)&adev->gfx.rlc.cs_ptr); 4499 if (adev->gfx.rlc.cp_table_size) { 4500 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4501 &adev->gfx.rlc.cp_table_gpu_addr, 4502 (void **)&adev->gfx.rlc.cp_table_ptr); 4503 } 4504 gfx_v7_0_free_microcode(adev); 4505 4506 return 0; 4507 } 4508 4509 static int gfx_v7_0_hw_init(void *handle) 4510 { 4511 int r; 4512 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4513 4514 gfx_v7_0_constants_init(adev); 4515 4516 /* init CSB */ 4517 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4518 /* init rlc */ 4519 r = adev->gfx.rlc.funcs->resume(adev); 4520 if (r) 4521 return r; 4522 4523 r = gfx_v7_0_cp_resume(adev); 4524 if (r) 4525 return r; 4526 4527 return r; 4528 } 4529 4530 static int gfx_v7_0_hw_fini(void *handle) 4531 { 4532 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4533 4534 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4535 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4536 gfx_v7_0_cp_enable(adev, false); 4537 adev->gfx.rlc.funcs->stop(adev); 4538 gfx_v7_0_fini_pg(adev); 4539 4540 return 0; 4541 } 4542 4543 static int gfx_v7_0_suspend(void *handle) 4544 { 4545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4546 4547 return gfx_v7_0_hw_fini(adev); 4548 } 4549 4550 static int gfx_v7_0_resume(void *handle) 4551 { 4552 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4553 4554 return gfx_v7_0_hw_init(adev); 4555 } 4556 4557 static bool gfx_v7_0_is_idle(void *handle) 4558 { 4559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4560 4561 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4562 return false; 4563 else 4564 return true; 4565 } 4566 4567 static int gfx_v7_0_wait_for_idle(void *handle) 4568 { 4569 unsigned i; 4570 u32 tmp; 4571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4572 4573 for (i = 0; i < adev->usec_timeout; i++) { 4574 /* read MC_STATUS */ 4575 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4576 4577 if (!tmp) 4578 return 0; 4579 udelay(1); 4580 } 4581 return -ETIMEDOUT; 4582 } 4583 4584 static int gfx_v7_0_soft_reset(void *handle) 4585 { 4586 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4587 u32 tmp; 4588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4589 4590 /* GRBM_STATUS */ 4591 tmp = RREG32(mmGRBM_STATUS); 4592 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4593 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4594 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4595 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4596 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4597 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4598 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4599 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4600 4601 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4602 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4603 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4604 } 4605 4606 /* GRBM_STATUS2 */ 4607 tmp = RREG32(mmGRBM_STATUS2); 4608 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4609 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4610 4611 /* SRBM_STATUS */ 4612 tmp = RREG32(mmSRBM_STATUS); 4613 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4614 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4615 4616 if (grbm_soft_reset || srbm_soft_reset) { 4617 /* disable CG/PG */ 4618 gfx_v7_0_fini_pg(adev); 4619 gfx_v7_0_update_cg(adev, false); 4620 4621 /* stop the rlc */ 4622 adev->gfx.rlc.funcs->stop(adev); 4623 4624 /* Disable GFX parsing/prefetching */ 4625 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4626 4627 /* Disable MEC parsing/prefetching */ 4628 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4629 4630 if (grbm_soft_reset) { 4631 tmp = RREG32(mmGRBM_SOFT_RESET); 4632 tmp |= grbm_soft_reset; 4633 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4634 WREG32(mmGRBM_SOFT_RESET, tmp); 4635 tmp = RREG32(mmGRBM_SOFT_RESET); 4636 4637 udelay(50); 4638 4639 tmp &= ~grbm_soft_reset; 4640 WREG32(mmGRBM_SOFT_RESET, tmp); 4641 tmp = RREG32(mmGRBM_SOFT_RESET); 4642 } 4643 4644 if (srbm_soft_reset) { 4645 tmp = RREG32(mmSRBM_SOFT_RESET); 4646 tmp |= srbm_soft_reset; 4647 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4648 WREG32(mmSRBM_SOFT_RESET, tmp); 4649 tmp = RREG32(mmSRBM_SOFT_RESET); 4650 4651 udelay(50); 4652 4653 tmp &= ~srbm_soft_reset; 4654 WREG32(mmSRBM_SOFT_RESET, tmp); 4655 tmp = RREG32(mmSRBM_SOFT_RESET); 4656 } 4657 /* Wait a little for things to settle down */ 4658 udelay(50); 4659 } 4660 return 0; 4661 } 4662 4663 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4664 enum amdgpu_interrupt_state state) 4665 { 4666 u32 cp_int_cntl; 4667 4668 switch (state) { 4669 case AMDGPU_IRQ_STATE_DISABLE: 4670 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4671 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4672 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4673 break; 4674 case AMDGPU_IRQ_STATE_ENABLE: 4675 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4676 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4677 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4678 break; 4679 default: 4680 break; 4681 } 4682 } 4683 4684 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4685 int me, int pipe, 4686 enum amdgpu_interrupt_state state) 4687 { 4688 u32 mec_int_cntl, mec_int_cntl_reg; 4689 4690 /* 4691 * amdgpu controls only the first MEC. That's why this function only 4692 * handles the setting of interrupts for this specific MEC. All other 4693 * pipes' interrupts are set by amdkfd. 4694 */ 4695 4696 if (me == 1) { 4697 switch (pipe) { 4698 case 0: 4699 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4700 break; 4701 case 1: 4702 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4703 break; 4704 case 2: 4705 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4706 break; 4707 case 3: 4708 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4709 break; 4710 default: 4711 DRM_DEBUG("invalid pipe %d\n", pipe); 4712 return; 4713 } 4714 } else { 4715 DRM_DEBUG("invalid me %d\n", me); 4716 return; 4717 } 4718 4719 switch (state) { 4720 case AMDGPU_IRQ_STATE_DISABLE: 4721 mec_int_cntl = RREG32(mec_int_cntl_reg); 4722 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4723 WREG32(mec_int_cntl_reg, mec_int_cntl); 4724 break; 4725 case AMDGPU_IRQ_STATE_ENABLE: 4726 mec_int_cntl = RREG32(mec_int_cntl_reg); 4727 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4728 WREG32(mec_int_cntl_reg, mec_int_cntl); 4729 break; 4730 default: 4731 break; 4732 } 4733 } 4734 4735 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4736 struct amdgpu_irq_src *src, 4737 unsigned type, 4738 enum amdgpu_interrupt_state state) 4739 { 4740 u32 cp_int_cntl; 4741 4742 switch (state) { 4743 case AMDGPU_IRQ_STATE_DISABLE: 4744 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4745 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4746 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4747 break; 4748 case AMDGPU_IRQ_STATE_ENABLE: 4749 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4750 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4751 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4752 break; 4753 default: 4754 break; 4755 } 4756 4757 return 0; 4758 } 4759 4760 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4761 struct amdgpu_irq_src *src, 4762 unsigned type, 4763 enum amdgpu_interrupt_state state) 4764 { 4765 u32 cp_int_cntl; 4766 4767 switch (state) { 4768 case AMDGPU_IRQ_STATE_DISABLE: 4769 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4770 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4771 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4772 break; 4773 case AMDGPU_IRQ_STATE_ENABLE: 4774 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4775 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4776 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4777 break; 4778 default: 4779 break; 4780 } 4781 4782 return 0; 4783 } 4784 4785 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4786 struct amdgpu_irq_src *src, 4787 unsigned type, 4788 enum amdgpu_interrupt_state state) 4789 { 4790 switch (type) { 4791 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4792 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4793 break; 4794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4795 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4796 break; 4797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4798 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4799 break; 4800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4801 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4802 break; 4803 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4804 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4805 break; 4806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4807 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4808 break; 4809 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4810 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4811 break; 4812 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4813 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4814 break; 4815 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4816 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4817 break; 4818 default: 4819 break; 4820 } 4821 return 0; 4822 } 4823 4824 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4825 struct amdgpu_irq_src *source, 4826 struct amdgpu_iv_entry *entry) 4827 { 4828 u8 me_id, pipe_id; 4829 struct amdgpu_ring *ring; 4830 int i; 4831 4832 DRM_DEBUG("IH: CP EOP\n"); 4833 me_id = (entry->ring_id & 0x0c) >> 2; 4834 pipe_id = (entry->ring_id & 0x03) >> 0; 4835 switch (me_id) { 4836 case 0: 4837 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4838 break; 4839 case 1: 4840 case 2: 4841 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4842 ring = &adev->gfx.compute_ring[i]; 4843 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4844 amdgpu_fence_process(ring); 4845 } 4846 break; 4847 } 4848 return 0; 4849 } 4850 4851 static void gfx_v7_0_fault(struct amdgpu_device *adev, 4852 struct amdgpu_iv_entry *entry) 4853 { 4854 struct amdgpu_ring *ring; 4855 u8 me_id, pipe_id; 4856 int i; 4857 4858 me_id = (entry->ring_id & 0x0c) >> 2; 4859 pipe_id = (entry->ring_id & 0x03) >> 0; 4860 switch (me_id) { 4861 case 0: 4862 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4863 break; 4864 case 1: 4865 case 2: 4866 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4867 ring = &adev->gfx.compute_ring[i]; 4868 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4869 drm_sched_fault(&ring->sched); 4870 } 4871 break; 4872 } 4873 } 4874 4875 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 4876 struct amdgpu_irq_src *source, 4877 struct amdgpu_iv_entry *entry) 4878 { 4879 DRM_ERROR("Illegal register access in command stream\n"); 4880 gfx_v7_0_fault(adev, entry); 4881 return 0; 4882 } 4883 4884 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 4885 struct amdgpu_irq_src *source, 4886 struct amdgpu_iv_entry *entry) 4887 { 4888 DRM_ERROR("Illegal instruction in command stream\n"); 4889 // XXX soft reset the gfx block only 4890 gfx_v7_0_fault(adev, entry); 4891 return 0; 4892 } 4893 4894 static int gfx_v7_0_set_clockgating_state(void *handle, 4895 enum amd_clockgating_state state) 4896 { 4897 bool gate = false; 4898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4899 4900 if (state == AMD_CG_STATE_GATE) 4901 gate = true; 4902 4903 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 4904 /* order matters! */ 4905 if (gate) { 4906 gfx_v7_0_enable_mgcg(adev, true); 4907 gfx_v7_0_enable_cgcg(adev, true); 4908 } else { 4909 gfx_v7_0_enable_cgcg(adev, false); 4910 gfx_v7_0_enable_mgcg(adev, false); 4911 } 4912 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4913 4914 return 0; 4915 } 4916 4917 static int gfx_v7_0_set_powergating_state(void *handle, 4918 enum amd_powergating_state state) 4919 { 4920 bool gate = false; 4921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4922 4923 if (state == AMD_PG_STATE_GATE) 4924 gate = true; 4925 4926 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4927 AMD_PG_SUPPORT_GFX_SMG | 4928 AMD_PG_SUPPORT_GFX_DMG | 4929 AMD_PG_SUPPORT_CP | 4930 AMD_PG_SUPPORT_GDS | 4931 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4932 gfx_v7_0_update_gfx_pg(adev, gate); 4933 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4934 gfx_v7_0_enable_cp_pg(adev, gate); 4935 gfx_v7_0_enable_gds_pg(adev, gate); 4936 } 4937 } 4938 4939 return 0; 4940 } 4941 4942 static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring) 4943 { 4944 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 4945 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4946 PACKET3_TC_ACTION_ENA | 4947 PACKET3_SH_KCACHE_ACTION_ENA | 4948 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4949 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4950 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4951 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4952 } 4953 4954 static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring) 4955 { 4956 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 4957 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4958 PACKET3_TC_ACTION_ENA | 4959 PACKET3_SH_KCACHE_ACTION_ENA | 4960 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4961 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4962 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ 4963 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4964 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 4965 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4966 } 4967 4968 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 4969 .name = "gfx_v7_0", 4970 .early_init = gfx_v7_0_early_init, 4971 .late_init = gfx_v7_0_late_init, 4972 .sw_init = gfx_v7_0_sw_init, 4973 .sw_fini = gfx_v7_0_sw_fini, 4974 .hw_init = gfx_v7_0_hw_init, 4975 .hw_fini = gfx_v7_0_hw_fini, 4976 .suspend = gfx_v7_0_suspend, 4977 .resume = gfx_v7_0_resume, 4978 .is_idle = gfx_v7_0_is_idle, 4979 .wait_for_idle = gfx_v7_0_wait_for_idle, 4980 .soft_reset = gfx_v7_0_soft_reset, 4981 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 4982 .set_powergating_state = gfx_v7_0_set_powergating_state, 4983 }; 4984 4985 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 4986 .type = AMDGPU_RING_TYPE_GFX, 4987 .align_mask = 0xff, 4988 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4989 .support_64bit_ptrs = false, 4990 .get_rptr = gfx_v7_0_ring_get_rptr, 4991 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 4992 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 4993 .emit_frame_size = 4994 20 + /* gfx_v7_0_ring_emit_gds_switch */ 4995 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 4996 5 + /* hdp invalidate */ 4997 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 4998 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 4999 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5000 3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 5001 5, /* SURFACE_SYNC */ 5002 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5003 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5004 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5005 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5006 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5007 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5008 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5009 .test_ring = gfx_v7_0_ring_test_ring, 5010 .test_ib = gfx_v7_0_ring_test_ib, 5011 .insert_nop = amdgpu_ring_insert_nop, 5012 .pad_ib = amdgpu_ring_generic_pad_ib, 5013 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5014 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5015 .soft_recovery = gfx_v7_0_ring_soft_recovery, 5016 .emit_mem_sync = gfx_v7_0_emit_mem_sync, 5017 }; 5018 5019 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5020 .type = AMDGPU_RING_TYPE_COMPUTE, 5021 .align_mask = 0xff, 5022 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5023 .support_64bit_ptrs = false, 5024 .get_rptr = gfx_v7_0_ring_get_rptr, 5025 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5026 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5027 .emit_frame_size = 5028 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5029 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5030 5 + /* hdp invalidate */ 5031 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5032 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ 5033 7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5034 7, /* gfx_v7_0_emit_mem_sync_compute */ 5035 .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */ 5036 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5037 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5038 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5039 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5040 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5041 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5042 .test_ring = gfx_v7_0_ring_test_ring, 5043 .test_ib = gfx_v7_0_ring_test_ib, 5044 .insert_nop = amdgpu_ring_insert_nop, 5045 .pad_ib = amdgpu_ring_generic_pad_ib, 5046 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5047 .emit_mem_sync = gfx_v7_0_emit_mem_sync_compute, 5048 }; 5049 5050 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5051 { 5052 int i; 5053 5054 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5055 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5056 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5057 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5058 } 5059 5060 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5061 .set = gfx_v7_0_set_eop_interrupt_state, 5062 .process = gfx_v7_0_eop_irq, 5063 }; 5064 5065 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5066 .set = gfx_v7_0_set_priv_reg_fault_state, 5067 .process = gfx_v7_0_priv_reg_irq, 5068 }; 5069 5070 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5071 .set = gfx_v7_0_set_priv_inst_fault_state, 5072 .process = gfx_v7_0_priv_inst_irq, 5073 }; 5074 5075 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5076 { 5077 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5078 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5079 5080 adev->gfx.priv_reg_irq.num_types = 1; 5081 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5082 5083 adev->gfx.priv_inst_irq.num_types = 1; 5084 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5085 } 5086 5087 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5088 { 5089 /* init asci gds info */ 5090 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 5091 adev->gds.gws_size = 64; 5092 adev->gds.oa_size = 16; 5093 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 5094 } 5095 5096 5097 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5098 { 5099 int i, j, k, counter, active_cu_number = 0; 5100 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5101 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5102 unsigned disable_masks[4 * 2]; 5103 u32 ao_cu_num; 5104 5105 if (adev->flags & AMD_IS_APU) 5106 ao_cu_num = 2; 5107 else 5108 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5109 5110 memset(cu_info, 0, sizeof(*cu_info)); 5111 5112 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5113 5114 mutex_lock(&adev->grbm_idx_mutex); 5115 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5116 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5117 mask = 1; 5118 ao_bitmap = 0; 5119 counter = 0; 5120 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5121 if (i < 4 && j < 2) 5122 gfx_v7_0_set_user_cu_inactive_bitmap( 5123 adev, disable_masks[i * 2 + j]); 5124 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5125 cu_info->bitmap[i][j] = bitmap; 5126 5127 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5128 if (bitmap & mask) { 5129 if (counter < ao_cu_num) 5130 ao_bitmap |= mask; 5131 counter ++; 5132 } 5133 mask <<= 1; 5134 } 5135 active_cu_number += counter; 5136 if (i < 2 && j < 2) 5137 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5138 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5139 } 5140 } 5141 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5142 mutex_unlock(&adev->grbm_idx_mutex); 5143 5144 cu_info->number = active_cu_number; 5145 cu_info->ao_cu_mask = ao_cu_mask; 5146 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5147 cu_info->max_waves_per_simd = 10; 5148 cu_info->max_scratch_slots_per_cu = 32; 5149 cu_info->wave_front_size = 64; 5150 cu_info->lds_size = 64; 5151 } 5152 5153 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5154 { 5155 .type = AMD_IP_BLOCK_TYPE_GFX, 5156 .major = 7, 5157 .minor = 1, 5158 .rev = 0, 5159 .funcs = &gfx_v7_0_ip_funcs, 5160 }; 5161 5162 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5163 { 5164 .type = AMD_IP_BLOCK_TYPE_GFX, 5165 .major = 7, 5166 .minor = 2, 5167 .rev = 0, 5168 .funcs = &gfx_v7_0_ip_funcs, 5169 }; 5170 5171 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5172 { 5173 .type = AMD_IP_BLOCK_TYPE_GFX, 5174 .major = 7, 5175 .minor = 3, 5176 .rev = 0, 5177 .funcs = &gfx_v7_0_ip_funcs, 5178 }; 5179