1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_ih.h" 29 #include "amdgpu_gfx.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "cik_structs.h" 33 #include "atom.h" 34 #include "amdgpu_ucode.h" 35 #include "clearstate_ci.h" 36 37 #include "dce/dce_8_0_d.h" 38 #include "dce/dce_8_0_sh_mask.h" 39 40 #include "bif/bif_4_1_d.h" 41 #include "bif/bif_4_1_sh_mask.h" 42 43 #include "gca/gfx_7_0_d.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "gca/gfx_7_2_sh_mask.h" 46 47 #include "gmc/gmc_7_0_d.h" 48 #include "gmc/gmc_7_0_sh_mask.h" 49 50 #include "oss/oss_2_0_d.h" 51 #include "oss/oss_2_0_sh_mask.h" 52 53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ 54 55 #define GFX7_NUM_GFX_RINGS 1 56 #define GFX7_MEC_HPD_SIZE 2048 57 58 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 59 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 60 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 61 62 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/bonaire_me.bin"); 64 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin"); 66 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin"); 67 68 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/hawaii_me.bin"); 70 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin"); 72 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin"); 73 74 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/kaveri_me.bin"); 76 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin"); 78 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin"); 80 81 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/kabini_me.bin"); 83 MODULE_FIRMWARE("amdgpu/kabini_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin"); 85 MODULE_FIRMWARE("amdgpu/kabini_mec.bin"); 86 87 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin"); 88 MODULE_FIRMWARE("amdgpu/mullins_me.bin"); 89 MODULE_FIRMWARE("amdgpu/mullins_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin"); 91 MODULE_FIRMWARE("amdgpu/mullins_mec.bin"); 92 93 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 94 { 95 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 96 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 97 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 98 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 99 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 100 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 101 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 102 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 103 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 104 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 105 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 106 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 107 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 108 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 109 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 110 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 111 }; 112 113 static const u32 spectre_rlc_save_restore_register_list[] = 114 { 115 (0x0e00 << 16) | (0xc12c >> 2), 116 0x00000000, 117 (0x0e00 << 16) | (0xc140 >> 2), 118 0x00000000, 119 (0x0e00 << 16) | (0xc150 >> 2), 120 0x00000000, 121 (0x0e00 << 16) | (0xc15c >> 2), 122 0x00000000, 123 (0x0e00 << 16) | (0xc168 >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc170 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc178 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc204 >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc2b4 >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc2b8 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0xc2bc >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0xc2c0 >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0x8228 >> 2), 140 0x00000000, 141 (0x0e00 << 16) | (0x829c >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0x869c >> 2), 144 0x00000000, 145 (0x0600 << 16) | (0x98f4 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0x98f8 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x9900 >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0xc260 >> 2), 152 0x00000000, 153 (0x0e00 << 16) | (0x90e8 >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x3c000 >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x3c00c >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0x8c1c >> 2), 160 0x00000000, 161 (0x0e00 << 16) | (0x9700 >> 2), 162 0x00000000, 163 (0x0e00 << 16) | (0xcd20 >> 2), 164 0x00000000, 165 (0x4e00 << 16) | (0xcd20 >> 2), 166 0x00000000, 167 (0x5e00 << 16) | (0xcd20 >> 2), 168 0x00000000, 169 (0x6e00 << 16) | (0xcd20 >> 2), 170 0x00000000, 171 (0x7e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0x8e00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0x9e00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0xae00 << 16) | (0xcd20 >> 2), 178 0x00000000, 179 (0xbe00 << 16) | (0xcd20 >> 2), 180 0x00000000, 181 (0x0e00 << 16) | (0x89bc >> 2), 182 0x00000000, 183 (0x0e00 << 16) | (0x8900 >> 2), 184 0x00000000, 185 0x3, 186 (0x0e00 << 16) | (0xc130 >> 2), 187 0x00000000, 188 (0x0e00 << 16) | (0xc134 >> 2), 189 0x00000000, 190 (0x0e00 << 16) | (0xc1fc >> 2), 191 0x00000000, 192 (0x0e00 << 16) | (0xc208 >> 2), 193 0x00000000, 194 (0x0e00 << 16) | (0xc264 >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc268 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc26c >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc270 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc274 >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc278 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc27c >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc280 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc284 >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc288 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc28c >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc290 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc294 >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc298 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc29c >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc2a0 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc2a4 >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc2a8 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0xc2ac >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0xc2b0 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0x301d0 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0x30238 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0x30250 >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0x30254 >> 2), 241 0x00000000, 242 (0x0e00 << 16) | (0x30258 >> 2), 243 0x00000000, 244 (0x0e00 << 16) | (0x3025c >> 2), 245 0x00000000, 246 (0x4e00 << 16) | (0xc900 >> 2), 247 0x00000000, 248 (0x5e00 << 16) | (0xc900 >> 2), 249 0x00000000, 250 (0x6e00 << 16) | (0xc900 >> 2), 251 0x00000000, 252 (0x7e00 << 16) | (0xc900 >> 2), 253 0x00000000, 254 (0x8e00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0x9e00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0xae00 << 16) | (0xc900 >> 2), 259 0x00000000, 260 (0xbe00 << 16) | (0xc900 >> 2), 261 0x00000000, 262 (0x4e00 << 16) | (0xc904 >> 2), 263 0x00000000, 264 (0x5e00 << 16) | (0xc904 >> 2), 265 0x00000000, 266 (0x6e00 << 16) | (0xc904 >> 2), 267 0x00000000, 268 (0x7e00 << 16) | (0xc904 >> 2), 269 0x00000000, 270 (0x8e00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0x9e00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0xae00 << 16) | (0xc904 >> 2), 275 0x00000000, 276 (0xbe00 << 16) | (0xc904 >> 2), 277 0x00000000, 278 (0x4e00 << 16) | (0xc908 >> 2), 279 0x00000000, 280 (0x5e00 << 16) | (0xc908 >> 2), 281 0x00000000, 282 (0x6e00 << 16) | (0xc908 >> 2), 283 0x00000000, 284 (0x7e00 << 16) | (0xc908 >> 2), 285 0x00000000, 286 (0x8e00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0x9e00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0xae00 << 16) | (0xc908 >> 2), 291 0x00000000, 292 (0xbe00 << 16) | (0xc908 >> 2), 293 0x00000000, 294 (0x4e00 << 16) | (0xc90c >> 2), 295 0x00000000, 296 (0x5e00 << 16) | (0xc90c >> 2), 297 0x00000000, 298 (0x6e00 << 16) | (0xc90c >> 2), 299 0x00000000, 300 (0x7e00 << 16) | (0xc90c >> 2), 301 0x00000000, 302 (0x8e00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0x9e00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0xae00 << 16) | (0xc90c >> 2), 307 0x00000000, 308 (0xbe00 << 16) | (0xc90c >> 2), 309 0x00000000, 310 (0x4e00 << 16) | (0xc910 >> 2), 311 0x00000000, 312 (0x5e00 << 16) | (0xc910 >> 2), 313 0x00000000, 314 (0x6e00 << 16) | (0xc910 >> 2), 315 0x00000000, 316 (0x7e00 << 16) | (0xc910 >> 2), 317 0x00000000, 318 (0x8e00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0x9e00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0xae00 << 16) | (0xc910 >> 2), 323 0x00000000, 324 (0xbe00 << 16) | (0xc910 >> 2), 325 0x00000000, 326 (0x0e00 << 16) | (0xc99c >> 2), 327 0x00000000, 328 (0x0e00 << 16) | (0x9834 >> 2), 329 0x00000000, 330 (0x0000 << 16) | (0x30f00 >> 2), 331 0x00000000, 332 (0x0001 << 16) | (0x30f00 >> 2), 333 0x00000000, 334 (0x0000 << 16) | (0x30f04 >> 2), 335 0x00000000, 336 (0x0001 << 16) | (0x30f04 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f08 >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f08 >> 2), 341 0x00000000, 342 (0x0000 << 16) | (0x30f0c >> 2), 343 0x00000000, 344 (0x0001 << 16) | (0x30f0c >> 2), 345 0x00000000, 346 (0x0600 << 16) | (0x9b7c >> 2), 347 0x00000000, 348 (0x0e00 << 16) | (0x8a14 >> 2), 349 0x00000000, 350 (0x0e00 << 16) | (0x8a18 >> 2), 351 0x00000000, 352 (0x0600 << 16) | (0x30a00 >> 2), 353 0x00000000, 354 (0x0e00 << 16) | (0x8bf0 >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x8bcc >> 2), 357 0x00000000, 358 (0x0e00 << 16) | (0x8b24 >> 2), 359 0x00000000, 360 (0x0e00 << 16) | (0x30a04 >> 2), 361 0x00000000, 362 (0x0600 << 16) | (0x30a10 >> 2), 363 0x00000000, 364 (0x0600 << 16) | (0x30a14 >> 2), 365 0x00000000, 366 (0x0600 << 16) | (0x30a18 >> 2), 367 0x00000000, 368 (0x0600 << 16) | (0x30a2c >> 2), 369 0x00000000, 370 (0x0e00 << 16) | (0xc700 >> 2), 371 0x00000000, 372 (0x0e00 << 16) | (0xc704 >> 2), 373 0x00000000, 374 (0x0e00 << 16) | (0xc708 >> 2), 375 0x00000000, 376 (0x0e00 << 16) | (0xc768 >> 2), 377 0x00000000, 378 (0x0400 << 16) | (0xc770 >> 2), 379 0x00000000, 380 (0x0400 << 16) | (0xc774 >> 2), 381 0x00000000, 382 (0x0400 << 16) | (0xc778 >> 2), 383 0x00000000, 384 (0x0400 << 16) | (0xc77c >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc780 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc784 >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc788 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc78c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc798 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc79c >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc7a0 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc7a4 >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc7a8 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc7ac >> 2), 405 0x00000000, 406 (0x0400 << 16) | (0xc7b0 >> 2), 407 0x00000000, 408 (0x0400 << 16) | (0xc7b4 >> 2), 409 0x00000000, 410 (0x0e00 << 16) | (0x9100 >> 2), 411 0x00000000, 412 (0x0e00 << 16) | (0x3c010 >> 2), 413 0x00000000, 414 (0x0e00 << 16) | (0x92a8 >> 2), 415 0x00000000, 416 (0x0e00 << 16) | (0x92ac >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x92b4 >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x92b8 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92bc >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92c0 >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92c4 >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92c8 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x92cc >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x92d0 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x8c00 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x8c04 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x8c20 >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0x8c38 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x8c3c >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0xae00 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0x9604 >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0xac08 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0xac0c >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xac10 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0xac14 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac58 >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac68 >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac6c >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac70 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac74 >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac78 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac7c >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac80 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac84 >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0xac88 >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0xac8c >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0x970c >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0x9714 >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0x9718 >> 2), 483 0x00000000, 484 (0x0e00 << 16) | (0x971c >> 2), 485 0x00000000, 486 (0x0e00 << 16) | (0x31068 >> 2), 487 0x00000000, 488 (0x4e00 << 16) | (0x31068 >> 2), 489 0x00000000, 490 (0x5e00 << 16) | (0x31068 >> 2), 491 0x00000000, 492 (0x6e00 << 16) | (0x31068 >> 2), 493 0x00000000, 494 (0x7e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0x8e00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0x9e00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0xae00 << 16) | (0x31068 >> 2), 501 0x00000000, 502 (0xbe00 << 16) | (0x31068 >> 2), 503 0x00000000, 504 (0x0e00 << 16) | (0xcd10 >> 2), 505 0x00000000, 506 (0x0e00 << 16) | (0xcd14 >> 2), 507 0x00000000, 508 (0x0e00 << 16) | (0x88b0 >> 2), 509 0x00000000, 510 (0x0e00 << 16) | (0x88b4 >> 2), 511 0x00000000, 512 (0x0e00 << 16) | (0x88b8 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0x88bc >> 2), 515 0x00000000, 516 (0x0400 << 16) | (0x89c0 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88c4 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88c8 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88d0 >> 2), 523 0x00000000, 524 (0x0e00 << 16) | (0x88d4 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x88d8 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x8980 >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x30938 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x3093c >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x30940 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x89a0 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x30900 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x30904 >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x89b4 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x3c210 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x3c214 >> 2), 547 0x00000000, 548 (0x0e00 << 16) | (0x3c218 >> 2), 549 0x00000000, 550 (0x0e00 << 16) | (0x8904 >> 2), 551 0x00000000, 552 0x5, 553 (0x0e00 << 16) | (0x8c28 >> 2), 554 (0x0e00 << 16) | (0x8c2c >> 2), 555 (0x0e00 << 16) | (0x8c30 >> 2), 556 (0x0e00 << 16) | (0x8c34 >> 2), 557 (0x0e00 << 16) | (0x9600 >> 2), 558 }; 559 560 static const u32 kalindi_rlc_save_restore_register_list[] = 561 { 562 (0x0e00 << 16) | (0xc12c >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc140 >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc150 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc15c >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc168 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc170 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc204 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2b4 >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2b8 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0xc2bc >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0xc2c0 >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x8228 >> 2), 585 0x00000000, 586 (0x0e00 << 16) | (0x829c >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x869c >> 2), 589 0x00000000, 590 (0x0600 << 16) | (0x98f4 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0x98f8 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x9900 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0xc260 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x90e8 >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x3c000 >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x3c00c >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0x8c1c >> 2), 605 0x00000000, 606 (0x0e00 << 16) | (0x9700 >> 2), 607 0x00000000, 608 (0x0e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x4e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x5e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x6e00 << 16) | (0xcd20 >> 2), 615 0x00000000, 616 (0x7e00 << 16) | (0xcd20 >> 2), 617 0x00000000, 618 (0x0e00 << 16) | (0x89bc >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0x8900 >> 2), 621 0x00000000, 622 0x3, 623 (0x0e00 << 16) | (0xc130 >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc134 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc1fc >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc208 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc264 >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc268 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc26c >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc270 >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc274 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc28c >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc290 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc294 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc298 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a0 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2a4 >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0xc2a8 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0xc2ac >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x301d0 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30238 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30250 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x30254 >> 2), 664 0x00000000, 665 (0x0e00 << 16) | (0x30258 >> 2), 666 0x00000000, 667 (0x0e00 << 16) | (0x3025c >> 2), 668 0x00000000, 669 (0x4e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x5e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x6e00 << 16) | (0xc900 >> 2), 674 0x00000000, 675 (0x7e00 << 16) | (0xc900 >> 2), 676 0x00000000, 677 (0x4e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x5e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x6e00 << 16) | (0xc904 >> 2), 682 0x00000000, 683 (0x7e00 << 16) | (0xc904 >> 2), 684 0x00000000, 685 (0x4e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x5e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x6e00 << 16) | (0xc908 >> 2), 690 0x00000000, 691 (0x7e00 << 16) | (0xc908 >> 2), 692 0x00000000, 693 (0x4e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x5e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x6e00 << 16) | (0xc90c >> 2), 698 0x00000000, 699 (0x7e00 << 16) | (0xc90c >> 2), 700 0x00000000, 701 (0x4e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x5e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x6e00 << 16) | (0xc910 >> 2), 706 0x00000000, 707 (0x7e00 << 16) | (0xc910 >> 2), 708 0x00000000, 709 (0x0e00 << 16) | (0xc99c >> 2), 710 0x00000000, 711 (0x0e00 << 16) | (0x9834 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f00 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f04 >> 2), 716 0x00000000, 717 (0x0000 << 16) | (0x30f08 >> 2), 718 0x00000000, 719 (0x0000 << 16) | (0x30f0c >> 2), 720 0x00000000, 721 (0x0600 << 16) | (0x9b7c >> 2), 722 0x00000000, 723 (0x0e00 << 16) | (0x8a14 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8a18 >> 2), 726 0x00000000, 727 (0x0600 << 16) | (0x30a00 >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8bf0 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x8bcc >> 2), 732 0x00000000, 733 (0x0e00 << 16) | (0x8b24 >> 2), 734 0x00000000, 735 (0x0e00 << 16) | (0x30a04 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a10 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a14 >> 2), 740 0x00000000, 741 (0x0600 << 16) | (0x30a18 >> 2), 742 0x00000000, 743 (0x0600 << 16) | (0x30a2c >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc700 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc704 >> 2), 748 0x00000000, 749 (0x0e00 << 16) | (0xc708 >> 2), 750 0x00000000, 751 (0x0e00 << 16) | (0xc768 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc770 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc774 >> 2), 756 0x00000000, 757 (0x0400 << 16) | (0xc798 >> 2), 758 0x00000000, 759 (0x0400 << 16) | (0xc79c >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x9100 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x3c010 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c00 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c04 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c20 >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0x8c38 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x8c3c >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xae00 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0x9604 >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac08 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac0c >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac10 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac14 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac58 >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac68 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac6c >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac70 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac74 >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac78 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac7c >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac80 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac84 >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0xac88 >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0xac8c >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x970c >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x9714 >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x9718 >> 2), 814 0x00000000, 815 (0x0e00 << 16) | (0x971c >> 2), 816 0x00000000, 817 (0x0e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x4e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x5e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x6e00 << 16) | (0x31068 >> 2), 824 0x00000000, 825 (0x7e00 << 16) | (0x31068 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0xcd10 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0xcd14 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b0 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88b4 >> 2), 834 0x00000000, 835 (0x0e00 << 16) | (0x88b8 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88bc >> 2), 838 0x00000000, 839 (0x0400 << 16) | (0x89c0 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88c4 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88c8 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d0 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x88d4 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x88d8 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x8980 >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30938 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x3093c >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30940 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x89a0 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x30900 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x30904 >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x89b4 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3e1fc >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c210 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x3c214 >> 2), 872 0x00000000, 873 (0x0e00 << 16) | (0x3c218 >> 2), 874 0x00000000, 875 (0x0e00 << 16) | (0x8904 >> 2), 876 0x00000000, 877 0x5, 878 (0x0e00 << 16) | (0x8c28 >> 2), 879 (0x0e00 << 16) | (0x8c2c >> 2), 880 (0x0e00 << 16) | (0x8c30 >> 2), 881 (0x0e00 << 16) | (0x8c34 >> 2), 882 (0x0e00 << 16) | (0x9600 >> 2), 883 }; 884 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 886 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 889 890 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 891 { 892 amdgpu_ucode_release(&adev->gfx.pfp_fw); 893 amdgpu_ucode_release(&adev->gfx.me_fw); 894 amdgpu_ucode_release(&adev->gfx.ce_fw); 895 amdgpu_ucode_release(&adev->gfx.mec_fw); 896 amdgpu_ucode_release(&adev->gfx.mec2_fw); 897 amdgpu_ucode_release(&adev->gfx.rlc_fw); 898 } 899 900 /* 901 * Core functions 902 */ 903 /** 904 * gfx_v7_0_init_microcode - load ucode images from disk 905 * 906 * @adev: amdgpu_device pointer 907 * 908 * Use the firmware interface to load the ucode images into 909 * the driver (not loaded into hw). 910 * Returns 0 on success, error on failure. 911 */ 912 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 913 { 914 const char *chip_name; 915 char fw_name[30]; 916 int err; 917 918 DRM_DEBUG("\n"); 919 920 switch (adev->asic_type) { 921 case CHIP_BONAIRE: 922 chip_name = "bonaire"; 923 break; 924 case CHIP_HAWAII: 925 chip_name = "hawaii"; 926 break; 927 case CHIP_KAVERI: 928 chip_name = "kaveri"; 929 break; 930 case CHIP_KABINI: 931 chip_name = "kabini"; 932 break; 933 case CHIP_MULLINS: 934 chip_name = "mullins"; 935 break; 936 default: BUG(); 937 } 938 939 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 940 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); 941 if (err) 942 goto out; 943 944 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 945 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); 946 if (err) 947 goto out; 948 949 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 950 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); 951 if (err) 952 goto out; 953 954 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 955 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 956 if (err) 957 goto out; 958 959 if (adev->asic_type == CHIP_KAVERI) { 960 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 961 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); 962 if (err) 963 goto out; 964 } 965 966 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 967 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 968 if (err) 969 goto out; 970 out: 971 if (err) { 972 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); 973 gfx_v7_0_free_microcode(adev); 974 } 975 return err; 976 } 977 978 /** 979 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 980 * 981 * @adev: amdgpu_device pointer 982 * 983 * Starting with SI, the tiling setup is done globally in a 984 * set of 32 tiling modes. Rather than selecting each set of 985 * parameters per surface as on older asics, we just select 986 * which index in the tiling table we want to use, and the 987 * surface uses those parameters (CIK). 988 */ 989 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 990 { 991 const u32 num_tile_mode_states = 992 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 993 const u32 num_secondary_tile_mode_states = 994 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 995 u32 reg_offset, split_equal_to_row_size; 996 uint32_t *tile, *macrotile; 997 998 tile = adev->gfx.config.tile_mode_array; 999 macrotile = adev->gfx.config.macrotile_mode_array; 1000 1001 switch (adev->gfx.config.mem_row_size_in_kb) { 1002 case 1: 1003 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1004 break; 1005 case 2: 1006 default: 1007 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1008 break; 1009 case 4: 1010 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1011 break; 1012 } 1013 1014 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1015 tile[reg_offset] = 0; 1016 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1017 macrotile[reg_offset] = 0; 1018 1019 switch (adev->asic_type) { 1020 case CHIP_BONAIRE: 1021 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1022 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1023 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1024 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1025 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1026 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1028 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1029 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1030 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1031 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1032 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1033 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1034 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1036 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1037 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1039 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1040 TILE_SPLIT(split_equal_to_row_size)); 1041 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1043 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1044 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1045 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1046 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1047 TILE_SPLIT(split_equal_to_row_size)); 1048 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1049 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1050 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1051 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1052 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1053 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1054 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1055 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1058 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1059 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1061 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1062 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1063 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1065 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1066 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1067 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1068 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1069 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1070 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1072 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1074 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1076 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1078 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1079 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1082 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1083 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1085 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1086 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1090 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1094 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1095 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1096 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1097 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1098 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1099 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1102 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1103 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1104 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1105 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1107 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1108 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1109 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1111 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1113 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1114 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1115 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1116 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1117 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1118 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1120 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1122 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1123 1124 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1125 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1126 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1127 NUM_BANKS(ADDR_SURF_16_BANK)); 1128 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1129 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1130 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1131 NUM_BANKS(ADDR_SURF_16_BANK)); 1132 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1135 NUM_BANKS(ADDR_SURF_16_BANK)); 1136 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1137 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1138 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1139 NUM_BANKS(ADDR_SURF_16_BANK)); 1140 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1143 NUM_BANKS(ADDR_SURF_16_BANK)); 1144 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1147 NUM_BANKS(ADDR_SURF_8_BANK)); 1148 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1151 NUM_BANKS(ADDR_SURF_4_BANK)); 1152 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1155 NUM_BANKS(ADDR_SURF_16_BANK)); 1156 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1159 NUM_BANKS(ADDR_SURF_16_BANK)); 1160 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1163 NUM_BANKS(ADDR_SURF_16_BANK)); 1164 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1167 NUM_BANKS(ADDR_SURF_16_BANK)); 1168 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1171 NUM_BANKS(ADDR_SURF_16_BANK)); 1172 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1175 NUM_BANKS(ADDR_SURF_8_BANK)); 1176 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1179 NUM_BANKS(ADDR_SURF_4_BANK)); 1180 1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1182 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1183 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1184 if (reg_offset != 7) 1185 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1186 break; 1187 case CHIP_HAWAII: 1188 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1189 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1190 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1191 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1192 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1193 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1195 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1196 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1197 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1198 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1199 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1200 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1201 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1203 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1204 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1206 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1207 TILE_SPLIT(split_equal_to_row_size)); 1208 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1210 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1211 TILE_SPLIT(split_equal_to_row_size)); 1212 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1214 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1215 TILE_SPLIT(split_equal_to_row_size)); 1216 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1217 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1218 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1219 TILE_SPLIT(split_equal_to_row_size)); 1220 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1222 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1223 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1225 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1226 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1229 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1230 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1233 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1234 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1237 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1238 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1239 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1240 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1242 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1243 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1244 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1246 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1247 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1248 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1249 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1250 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1251 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1252 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1253 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1254 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1255 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1256 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1260 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1263 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1264 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1265 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1266 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1267 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1268 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1269 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1271 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1274 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1275 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1276 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1277 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1278 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1279 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1283 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1287 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1291 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1292 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1293 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1294 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1296 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1298 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1300 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1302 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1303 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1304 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1306 1307 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1308 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1309 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1310 NUM_BANKS(ADDR_SURF_16_BANK)); 1311 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1312 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1313 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1314 NUM_BANKS(ADDR_SURF_16_BANK)); 1315 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1316 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1317 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1318 NUM_BANKS(ADDR_SURF_16_BANK)); 1319 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1320 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1321 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1322 NUM_BANKS(ADDR_SURF_16_BANK)); 1323 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1326 NUM_BANKS(ADDR_SURF_8_BANK)); 1327 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1330 NUM_BANKS(ADDR_SURF_4_BANK)); 1331 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1334 NUM_BANKS(ADDR_SURF_4_BANK)); 1335 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1338 NUM_BANKS(ADDR_SURF_16_BANK)); 1339 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1342 NUM_BANKS(ADDR_SURF_16_BANK)); 1343 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1346 NUM_BANKS(ADDR_SURF_16_BANK)); 1347 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1350 NUM_BANKS(ADDR_SURF_8_BANK)); 1351 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1354 NUM_BANKS(ADDR_SURF_16_BANK)); 1355 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1358 NUM_BANKS(ADDR_SURF_8_BANK)); 1359 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1362 NUM_BANKS(ADDR_SURF_4_BANK)); 1363 1364 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1365 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1366 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1367 if (reg_offset != 7) 1368 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1369 break; 1370 case CHIP_KABINI: 1371 case CHIP_KAVERI: 1372 case CHIP_MULLINS: 1373 default: 1374 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1375 PIPE_CONFIG(ADDR_SURF_P2) | 1376 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1377 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1378 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1379 PIPE_CONFIG(ADDR_SURF_P2) | 1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1382 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1383 PIPE_CONFIG(ADDR_SURF_P2) | 1384 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1385 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1386 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1387 PIPE_CONFIG(ADDR_SURF_P2) | 1388 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1389 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1390 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1391 PIPE_CONFIG(ADDR_SURF_P2) | 1392 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1393 TILE_SPLIT(split_equal_to_row_size)); 1394 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1395 PIPE_CONFIG(ADDR_SURF_P2) | 1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1397 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1398 PIPE_CONFIG(ADDR_SURF_P2) | 1399 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1400 TILE_SPLIT(split_equal_to_row_size)); 1401 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1402 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1403 PIPE_CONFIG(ADDR_SURF_P2)); 1404 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1405 PIPE_CONFIG(ADDR_SURF_P2) | 1406 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1407 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1408 PIPE_CONFIG(ADDR_SURF_P2) | 1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1410 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1411 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1412 PIPE_CONFIG(ADDR_SURF_P2) | 1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1414 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1415 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1416 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1417 PIPE_CONFIG(ADDR_SURF_P2) | 1418 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1419 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1420 PIPE_CONFIG(ADDR_SURF_P2) | 1421 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1422 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1423 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1424 PIPE_CONFIG(ADDR_SURF_P2) | 1425 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1427 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1428 PIPE_CONFIG(ADDR_SURF_P2) | 1429 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1431 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1432 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1433 PIPE_CONFIG(ADDR_SURF_P2) | 1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1435 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1436 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1437 PIPE_CONFIG(ADDR_SURF_P2) | 1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1439 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1443 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1444 PIPE_CONFIG(ADDR_SURF_P2) | 1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1447 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1448 PIPE_CONFIG(ADDR_SURF_P2) | 1449 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1450 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1451 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1452 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1453 PIPE_CONFIG(ADDR_SURF_P2) | 1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1456 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1457 PIPE_CONFIG(ADDR_SURF_P2) | 1458 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1459 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1460 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1461 PIPE_CONFIG(ADDR_SURF_P2) | 1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1464 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1465 PIPE_CONFIG(ADDR_SURF_P2) | 1466 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1467 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1468 PIPE_CONFIG(ADDR_SURF_P2) | 1469 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1470 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1471 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1472 PIPE_CONFIG(ADDR_SURF_P2) | 1473 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1475 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1476 1477 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1480 NUM_BANKS(ADDR_SURF_8_BANK)); 1481 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1484 NUM_BANKS(ADDR_SURF_8_BANK)); 1485 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1488 NUM_BANKS(ADDR_SURF_8_BANK)); 1489 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1490 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1491 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1492 NUM_BANKS(ADDR_SURF_8_BANK)); 1493 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1496 NUM_BANKS(ADDR_SURF_8_BANK)); 1497 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1500 NUM_BANKS(ADDR_SURF_8_BANK)); 1501 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1504 NUM_BANKS(ADDR_SURF_8_BANK)); 1505 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1508 NUM_BANKS(ADDR_SURF_16_BANK)); 1509 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1512 NUM_BANKS(ADDR_SURF_16_BANK)); 1513 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1516 NUM_BANKS(ADDR_SURF_16_BANK)); 1517 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1520 NUM_BANKS(ADDR_SURF_16_BANK)); 1521 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1524 NUM_BANKS(ADDR_SURF_16_BANK)); 1525 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1528 NUM_BANKS(ADDR_SURF_16_BANK)); 1529 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1532 NUM_BANKS(ADDR_SURF_8_BANK)); 1533 1534 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1535 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1536 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1537 if (reg_offset != 7) 1538 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1539 break; 1540 } 1541 } 1542 1543 /** 1544 * gfx_v7_0_select_se_sh - select which SE, SH to address 1545 * 1546 * @adev: amdgpu_device pointer 1547 * @se_num: shader engine to address 1548 * @sh_num: sh block to address 1549 * @instance: Certain registers are instanced per SE or SH. 1550 * 0xffffffff means broadcast to all SEs or SHs (CIK). 1551 * 1552 * Select which SE, SH combinations to address. 1553 */ 1554 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1555 u32 se_num, u32 sh_num, u32 instance) 1556 { 1557 u32 data; 1558 1559 if (instance == 0xffffffff) 1560 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1561 else 1562 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1563 1564 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1565 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1566 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1567 else if (se_num == 0xffffffff) 1568 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1569 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1570 else if (sh_num == 0xffffffff) 1571 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1572 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1573 else 1574 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1575 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1576 WREG32(mmGRBM_GFX_INDEX, data); 1577 } 1578 1579 /** 1580 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1581 * 1582 * @adev: amdgpu_device pointer 1583 * 1584 * Calculates the bitmask of enabled RBs (CIK). 1585 * Returns the enabled RB bitmask. 1586 */ 1587 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1588 { 1589 u32 data, mask; 1590 1591 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1592 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1593 1594 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1595 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1596 1597 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1598 adev->gfx.config.max_sh_per_se); 1599 1600 return (~data) & mask; 1601 } 1602 1603 static void 1604 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1605 { 1606 switch (adev->asic_type) { 1607 case CHIP_BONAIRE: 1608 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1609 SE_XSEL(1) | SE_YSEL(1); 1610 *rconf1 |= 0x0; 1611 break; 1612 case CHIP_HAWAII: 1613 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1614 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1615 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1616 SE_YSEL(3); 1617 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1618 SE_PAIR_YSEL(2); 1619 break; 1620 case CHIP_KAVERI: 1621 *rconf |= RB_MAP_PKR0(2); 1622 *rconf1 |= 0x0; 1623 break; 1624 case CHIP_KABINI: 1625 case CHIP_MULLINS: 1626 *rconf |= 0x0; 1627 *rconf1 |= 0x0; 1628 break; 1629 default: 1630 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1631 break; 1632 } 1633 } 1634 1635 static void 1636 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1637 u32 raster_config, u32 raster_config_1, 1638 unsigned rb_mask, unsigned num_rb) 1639 { 1640 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1641 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1642 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1643 unsigned rb_per_se = num_rb / num_se; 1644 unsigned se_mask[4]; 1645 unsigned se; 1646 1647 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1648 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1649 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1650 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1651 1652 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1653 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1654 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1655 1656 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1657 (!se_mask[2] && !se_mask[3]))) { 1658 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1659 1660 if (!se_mask[0] && !se_mask[1]) { 1661 raster_config_1 |= 1662 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1663 } else { 1664 raster_config_1 |= 1665 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1666 } 1667 } 1668 1669 for (se = 0; se < num_se; se++) { 1670 unsigned raster_config_se = raster_config; 1671 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1672 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1673 int idx = (se / 2) * 2; 1674 1675 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1676 raster_config_se &= ~SE_MAP_MASK; 1677 1678 if (!se_mask[idx]) { 1679 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1680 } else { 1681 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1682 } 1683 } 1684 1685 pkr0_mask &= rb_mask; 1686 pkr1_mask &= rb_mask; 1687 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1688 raster_config_se &= ~PKR_MAP_MASK; 1689 1690 if (!pkr0_mask) { 1691 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1692 } else { 1693 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1694 } 1695 } 1696 1697 if (rb_per_se >= 2) { 1698 unsigned rb0_mask = 1 << (se * rb_per_se); 1699 unsigned rb1_mask = rb0_mask << 1; 1700 1701 rb0_mask &= rb_mask; 1702 rb1_mask &= rb_mask; 1703 if (!rb0_mask || !rb1_mask) { 1704 raster_config_se &= ~RB_MAP_PKR0_MASK; 1705 1706 if (!rb0_mask) { 1707 raster_config_se |= 1708 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1709 } else { 1710 raster_config_se |= 1711 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1712 } 1713 } 1714 1715 if (rb_per_se > 2) { 1716 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1717 rb1_mask = rb0_mask << 1; 1718 rb0_mask &= rb_mask; 1719 rb1_mask &= rb_mask; 1720 if (!rb0_mask || !rb1_mask) { 1721 raster_config_se &= ~RB_MAP_PKR1_MASK; 1722 1723 if (!rb0_mask) { 1724 raster_config_se |= 1725 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1726 } else { 1727 raster_config_se |= 1728 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1729 } 1730 } 1731 } 1732 } 1733 1734 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1735 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1736 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1737 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1738 } 1739 1740 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1741 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1742 } 1743 1744 /** 1745 * gfx_v7_0_setup_rb - setup the RBs on the asic 1746 * 1747 * @adev: amdgpu_device pointer 1748 * 1749 * Configures per-SE/SH RB registers (CIK). 1750 */ 1751 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1752 { 1753 int i, j; 1754 u32 data; 1755 u32 raster_config = 0, raster_config_1 = 0; 1756 u32 active_rbs = 0; 1757 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1758 adev->gfx.config.max_sh_per_se; 1759 unsigned num_rb_pipes; 1760 1761 mutex_lock(&adev->grbm_idx_mutex); 1762 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1763 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1764 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1765 data = gfx_v7_0_get_rb_active_bitmap(adev); 1766 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1767 rb_bitmap_width_per_sh); 1768 } 1769 } 1770 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1771 1772 adev->gfx.config.backend_enable_mask = active_rbs; 1773 adev->gfx.config.num_rbs = hweight32(active_rbs); 1774 1775 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1776 adev->gfx.config.max_shader_engines, 16); 1777 1778 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1779 1780 if (!adev->gfx.config.backend_enable_mask || 1781 adev->gfx.config.num_rbs >= num_rb_pipes) { 1782 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1783 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1784 } else { 1785 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1786 adev->gfx.config.backend_enable_mask, 1787 num_rb_pipes); 1788 } 1789 1790 /* cache the values for userspace */ 1791 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1792 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1793 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1794 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1795 RREG32(mmCC_RB_BACKEND_DISABLE); 1796 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1797 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1798 adev->gfx.config.rb_config[i][j].raster_config = 1799 RREG32(mmPA_SC_RASTER_CONFIG); 1800 adev->gfx.config.rb_config[i][j].raster_config_1 = 1801 RREG32(mmPA_SC_RASTER_CONFIG_1); 1802 } 1803 } 1804 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1805 mutex_unlock(&adev->grbm_idx_mutex); 1806 } 1807 1808 #define DEFAULT_SH_MEM_BASES (0x6000) 1809 /** 1810 * gfx_v7_0_init_compute_vmid - gart enable 1811 * 1812 * @adev: amdgpu_device pointer 1813 * 1814 * Initialize compute vmid sh_mem registers 1815 * 1816 */ 1817 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1818 { 1819 int i; 1820 uint32_t sh_mem_config; 1821 uint32_t sh_mem_bases; 1822 1823 /* 1824 * Configure apertures: 1825 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1826 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1827 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1828 */ 1829 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1830 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1831 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1832 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1833 mutex_lock(&adev->srbm_mutex); 1834 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1835 cik_srbm_select(adev, 0, 0, 0, i); 1836 /* CP and shaders */ 1837 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1838 WREG32(mmSH_MEM_APE1_BASE, 1); 1839 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1840 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1841 } 1842 cik_srbm_select(adev, 0, 0, 0, 0); 1843 mutex_unlock(&adev->srbm_mutex); 1844 1845 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1846 access. These should be enabled by FW for target VMIDs. */ 1847 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1848 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); 1849 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); 1850 WREG32(amdgpu_gds_reg_offset[i].gws, 0); 1851 WREG32(amdgpu_gds_reg_offset[i].oa, 0); 1852 } 1853 } 1854 1855 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) 1856 { 1857 int vmid; 1858 1859 /* 1860 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1861 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1862 * the driver can enable them for graphics. VMID0 should maintain 1863 * access so that HWS firmware can save/restore entries. 1864 */ 1865 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1866 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 1867 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 1868 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 1869 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 1870 } 1871 } 1872 1873 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1874 { 1875 adev->gfx.config.double_offchip_lds_buf = 1; 1876 } 1877 1878 /** 1879 * gfx_v7_0_constants_init - setup the 3D engine 1880 * 1881 * @adev: amdgpu_device pointer 1882 * 1883 * init the gfx constants such as the 3D engine, tiling configuration 1884 * registers, maximum number of quad pipes, render backends... 1885 */ 1886 static void gfx_v7_0_constants_init(struct amdgpu_device *adev) 1887 { 1888 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1889 u32 tmp; 1890 int i; 1891 1892 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1893 1894 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1895 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1896 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1897 1898 gfx_v7_0_tiling_mode_table_init(adev); 1899 1900 gfx_v7_0_setup_rb(adev); 1901 gfx_v7_0_get_cu_info(adev); 1902 gfx_v7_0_config_init(adev); 1903 1904 /* set HW defaults for 3D engine */ 1905 WREG32(mmCP_MEQ_THRESHOLDS, 1906 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1907 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1908 1909 mutex_lock(&adev->grbm_idx_mutex); 1910 /* 1911 * making sure that the following register writes will be broadcasted 1912 * to all the shaders 1913 */ 1914 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1915 1916 /* XXX SH_MEM regs */ 1917 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1918 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1919 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1920 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1921 MTYPE_NC); 1922 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1923 MTYPE_UC); 1924 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1925 1926 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1927 SWIZZLE_ENABLE, 1); 1928 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1929 ELEMENT_SIZE, 1); 1930 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1931 INDEX_STRIDE, 3); 1932 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1933 1934 mutex_lock(&adev->srbm_mutex); 1935 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1936 if (i == 0) 1937 sh_mem_base = 0; 1938 else 1939 sh_mem_base = adev->gmc.shared_aperture_start >> 48; 1940 cik_srbm_select(adev, 0, 0, 0, i); 1941 /* CP and shaders */ 1942 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1943 WREG32(mmSH_MEM_APE1_BASE, 1); 1944 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1945 WREG32(mmSH_MEM_BASES, sh_mem_base); 1946 } 1947 cik_srbm_select(adev, 0, 0, 0, 0); 1948 mutex_unlock(&adev->srbm_mutex); 1949 1950 gfx_v7_0_init_compute_vmid(adev); 1951 gfx_v7_0_init_gds_vmid(adev); 1952 1953 WREG32(mmSX_DEBUG_1, 0x20); 1954 1955 WREG32(mmTA_CNTL_AUX, 0x00010000); 1956 1957 tmp = RREG32(mmSPI_CONFIG_CNTL); 1958 tmp |= 0x03000000; 1959 WREG32(mmSPI_CONFIG_CNTL, tmp); 1960 1961 WREG32(mmSQ_CONFIG, 1); 1962 1963 WREG32(mmDB_DEBUG, 0); 1964 1965 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1966 tmp |= 0x00000400; 1967 WREG32(mmDB_DEBUG2, tmp); 1968 1969 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1970 tmp |= 0x00020200; 1971 WREG32(mmDB_DEBUG3, tmp); 1972 1973 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1974 tmp |= 0x00018208; 1975 WREG32(mmCB_HW_CONTROL, tmp); 1976 1977 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1978 1979 WREG32(mmPA_SC_FIFO_SIZE, 1980 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1981 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1982 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1983 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1984 1985 WREG32(mmVGT_NUM_INSTANCES, 1); 1986 1987 WREG32(mmCP_PERFMON_CNTL, 0); 1988 1989 WREG32(mmSQ_CONFIG, 0); 1990 1991 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1992 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1993 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1994 1995 WREG32(mmVGT_CACHE_INVALIDATION, 1996 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1997 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1998 1999 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2000 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2001 2002 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2003 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2004 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2005 2006 tmp = RREG32(mmSPI_ARB_PRIORITY); 2007 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2008 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2009 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2010 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2011 WREG32(mmSPI_ARB_PRIORITY, tmp); 2012 2013 mutex_unlock(&adev->grbm_idx_mutex); 2014 2015 udelay(50); 2016 } 2017 2018 /** 2019 * gfx_v7_0_ring_test_ring - basic gfx ring test 2020 * 2021 * @ring: amdgpu_ring structure holding ring information 2022 * 2023 * Allocate a scratch register and write to it using the gfx ring (CIK). 2024 * Provides a basic gfx ring test to verify that the ring is working. 2025 * Used by gfx_v7_0_cp_gfx_resume(); 2026 * Returns 0 on success, error on failure. 2027 */ 2028 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2029 { 2030 struct amdgpu_device *adev = ring->adev; 2031 uint32_t tmp = 0; 2032 unsigned i; 2033 int r; 2034 2035 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2036 r = amdgpu_ring_alloc(ring, 3); 2037 if (r) 2038 return r; 2039 2040 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2041 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); 2042 amdgpu_ring_write(ring, 0xDEADBEEF); 2043 amdgpu_ring_commit(ring); 2044 2045 for (i = 0; i < adev->usec_timeout; i++) { 2046 tmp = RREG32(mmSCRATCH_REG0); 2047 if (tmp == 0xDEADBEEF) 2048 break; 2049 udelay(1); 2050 } 2051 if (i >= adev->usec_timeout) 2052 r = -ETIMEDOUT; 2053 return r; 2054 } 2055 2056 /** 2057 * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp 2058 * 2059 * @ring: amdgpu_ring structure holding ring information 2060 * 2061 * Emits an hdp flush on the cp. 2062 */ 2063 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2064 { 2065 u32 ref_and_mask; 2066 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2067 2068 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2069 switch (ring->me) { 2070 case 1: 2071 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2072 break; 2073 case 2: 2074 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2075 break; 2076 default: 2077 return; 2078 } 2079 } else { 2080 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2081 } 2082 2083 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2084 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2085 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2086 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2087 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2088 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2089 amdgpu_ring_write(ring, ref_and_mask); 2090 amdgpu_ring_write(ring, ref_and_mask); 2091 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2092 } 2093 2094 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2095 { 2096 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2097 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2098 EVENT_INDEX(4)); 2099 2100 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2101 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2102 EVENT_INDEX(0)); 2103 } 2104 2105 /** 2106 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2107 * 2108 * @ring: amdgpu_ring structure holding ring information 2109 * @addr: address 2110 * @seq: sequence number 2111 * @flags: fence related flags 2112 * 2113 * Emits a fence sequence number on the gfx ring and flushes 2114 * GPU caches. 2115 */ 2116 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2117 u64 seq, unsigned flags) 2118 { 2119 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2120 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2121 /* Workaround for cache flush problems. First send a dummy EOP 2122 * event down the pipe with seq one below. 2123 */ 2124 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2125 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2126 EOP_TC_ACTION_EN | 2127 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2128 EVENT_INDEX(5))); 2129 amdgpu_ring_write(ring, addr & 0xfffffffc); 2130 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2131 DATA_SEL(1) | INT_SEL(0)); 2132 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2133 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2134 2135 /* Then send the real EOP event down the pipe. */ 2136 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2137 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2138 EOP_TC_ACTION_EN | 2139 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2140 EVENT_INDEX(5))); 2141 amdgpu_ring_write(ring, addr & 0xfffffffc); 2142 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2143 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2144 amdgpu_ring_write(ring, lower_32_bits(seq)); 2145 amdgpu_ring_write(ring, upper_32_bits(seq)); 2146 } 2147 2148 /** 2149 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2150 * 2151 * @ring: amdgpu_ring structure holding ring information 2152 * @addr: address 2153 * @seq: sequence number 2154 * @flags: fence related flags 2155 * 2156 * Emits a fence sequence number on the compute ring and flushes 2157 * GPU caches. 2158 */ 2159 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2160 u64 addr, u64 seq, 2161 unsigned flags) 2162 { 2163 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2164 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2165 2166 /* RELEASE_MEM - flush caches, send int */ 2167 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2168 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2169 EOP_TC_ACTION_EN | 2170 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2171 EVENT_INDEX(5))); 2172 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2173 amdgpu_ring_write(ring, addr & 0xfffffffc); 2174 amdgpu_ring_write(ring, upper_32_bits(addr)); 2175 amdgpu_ring_write(ring, lower_32_bits(seq)); 2176 amdgpu_ring_write(ring, upper_32_bits(seq)); 2177 } 2178 2179 /* 2180 * IB stuff 2181 */ 2182 /** 2183 * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring 2184 * 2185 * @ring: amdgpu_ring structure holding ring information 2186 * @job: job to retrieve vmid from 2187 * @ib: amdgpu indirect buffer object 2188 * @flags: options (AMDGPU_HAVE_CTX_SWITCH) 2189 * 2190 * Emits an DE (drawing engine) or CE (constant engine) IB 2191 * on the gfx ring. IBs are usually generated by userspace 2192 * acceleration drivers and submitted to the kernel for 2193 * scheduling on the ring. This function schedules the IB 2194 * on the gfx ring for execution by the GPU. 2195 */ 2196 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2197 struct amdgpu_job *job, 2198 struct amdgpu_ib *ib, 2199 uint32_t flags) 2200 { 2201 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2202 u32 header, control = 0; 2203 2204 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2205 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2206 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2207 amdgpu_ring_write(ring, 0); 2208 } 2209 2210 if (ib->flags & AMDGPU_IB_FLAG_CE) 2211 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2212 else 2213 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2214 2215 control |= ib->length_dw | (vmid << 24); 2216 2217 amdgpu_ring_write(ring, header); 2218 amdgpu_ring_write(ring, 2219 #ifdef __BIG_ENDIAN 2220 (2 << 0) | 2221 #endif 2222 (ib->gpu_addr & 0xFFFFFFFC)); 2223 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2224 amdgpu_ring_write(ring, control); 2225 } 2226 2227 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2228 struct amdgpu_job *job, 2229 struct amdgpu_ib *ib, 2230 uint32_t flags) 2231 { 2232 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2233 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2234 2235 /* Currently, there is a high possibility to get wave ID mismatch 2236 * between ME and GDS, leading to a hw deadlock, because ME generates 2237 * different wave IDs than the GDS expects. This situation happens 2238 * randomly when at least 5 compute pipes use GDS ordered append. 2239 * The wave IDs generated by ME are also wrong after suspend/resume. 2240 * Those are probably bugs somewhere else in the kernel driver. 2241 * 2242 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2243 * GDS to 0 for this ring (me/pipe). 2244 */ 2245 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2246 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2247 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 2248 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2249 } 2250 2251 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2252 amdgpu_ring_write(ring, 2253 #ifdef __BIG_ENDIAN 2254 (2 << 0) | 2255 #endif 2256 (ib->gpu_addr & 0xFFFFFFFC)); 2257 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2258 amdgpu_ring_write(ring, control); 2259 } 2260 2261 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2262 { 2263 uint32_t dw2 = 0; 2264 2265 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2266 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2267 gfx_v7_0_ring_emit_vgt_flush(ring); 2268 /* set load_global_config & load_global_uconfig */ 2269 dw2 |= 0x8001; 2270 /* set load_cs_sh_regs */ 2271 dw2 |= 0x01000000; 2272 /* set load_per_context_state & load_gfx_sh_regs */ 2273 dw2 |= 0x10002; 2274 } 2275 2276 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2277 amdgpu_ring_write(ring, dw2); 2278 amdgpu_ring_write(ring, 0); 2279 } 2280 2281 /** 2282 * gfx_v7_0_ring_test_ib - basic ring IB test 2283 * 2284 * @ring: amdgpu_ring structure holding ring information 2285 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 2286 * 2287 * Allocate an IB and execute it on the gfx ring (CIK). 2288 * Provides a basic gfx ring test to verify that IBs are working. 2289 * Returns 0 on success, error on failure. 2290 */ 2291 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2292 { 2293 struct amdgpu_device *adev = ring->adev; 2294 struct amdgpu_ib ib; 2295 struct dma_fence *f = NULL; 2296 uint32_t tmp = 0; 2297 long r; 2298 2299 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); 2300 memset(&ib, 0, sizeof(ib)); 2301 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 2302 if (r) 2303 return r; 2304 2305 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2306 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; 2307 ib.ptr[2] = 0xDEADBEEF; 2308 ib.length_dw = 3; 2309 2310 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2311 if (r) 2312 goto error; 2313 2314 r = dma_fence_wait_timeout(f, false, timeout); 2315 if (r == 0) { 2316 r = -ETIMEDOUT; 2317 goto error; 2318 } else if (r < 0) { 2319 goto error; 2320 } 2321 tmp = RREG32(mmSCRATCH_REG0); 2322 if (tmp == 0xDEADBEEF) 2323 r = 0; 2324 else 2325 r = -EINVAL; 2326 2327 error: 2328 amdgpu_ib_free(adev, &ib, NULL); 2329 dma_fence_put(f); 2330 return r; 2331 } 2332 2333 /* 2334 * CP. 2335 * On CIK, gfx and compute now have independent command processors. 2336 * 2337 * GFX 2338 * Gfx consists of a single ring and can process both gfx jobs and 2339 * compute jobs. The gfx CP consists of three microengines (ME): 2340 * PFP - Pre-Fetch Parser 2341 * ME - Micro Engine 2342 * CE - Constant Engine 2343 * The PFP and ME make up what is considered the Drawing Engine (DE). 2344 * The CE is an asynchronous engine used for updating buffer desciptors 2345 * used by the DE so that they can be loaded into cache in parallel 2346 * while the DE is processing state update packets. 2347 * 2348 * Compute 2349 * The compute CP consists of two microengines (ME): 2350 * MEC1 - Compute MicroEngine 1 2351 * MEC2 - Compute MicroEngine 2 2352 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2353 * The queues are exposed to userspace and are programmed directly 2354 * by the compute runtime. 2355 */ 2356 /** 2357 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2358 * 2359 * @adev: amdgpu_device pointer 2360 * @enable: enable or disable the MEs 2361 * 2362 * Halts or unhalts the gfx MEs. 2363 */ 2364 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2365 { 2366 if (enable) 2367 WREG32(mmCP_ME_CNTL, 0); 2368 else 2369 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2370 CP_ME_CNTL__PFP_HALT_MASK | 2371 CP_ME_CNTL__CE_HALT_MASK)); 2372 udelay(50); 2373 } 2374 2375 /** 2376 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2377 * 2378 * @adev: amdgpu_device pointer 2379 * 2380 * Loads the gfx PFP, ME, and CE ucode. 2381 * Returns 0 for success, -EINVAL if the ucode is not available. 2382 */ 2383 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2384 { 2385 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2386 const struct gfx_firmware_header_v1_0 *ce_hdr; 2387 const struct gfx_firmware_header_v1_0 *me_hdr; 2388 const __le32 *fw_data; 2389 unsigned i, fw_size; 2390 2391 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2392 return -EINVAL; 2393 2394 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2395 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2396 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2397 2398 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2399 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2400 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2401 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2402 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2403 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2404 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2405 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2406 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2407 2408 gfx_v7_0_cp_gfx_enable(adev, false); 2409 2410 /* PFP */ 2411 fw_data = (const __le32 *) 2412 (adev->gfx.pfp_fw->data + 2413 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2414 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2415 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2416 for (i = 0; i < fw_size; i++) 2417 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2418 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2419 2420 /* CE */ 2421 fw_data = (const __le32 *) 2422 (adev->gfx.ce_fw->data + 2423 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2424 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2425 WREG32(mmCP_CE_UCODE_ADDR, 0); 2426 for (i = 0; i < fw_size; i++) 2427 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2428 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2429 2430 /* ME */ 2431 fw_data = (const __le32 *) 2432 (adev->gfx.me_fw->data + 2433 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2434 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2435 WREG32(mmCP_ME_RAM_WADDR, 0); 2436 for (i = 0; i < fw_size; i++) 2437 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2438 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2439 2440 return 0; 2441 } 2442 2443 /** 2444 * gfx_v7_0_cp_gfx_start - start the gfx ring 2445 * 2446 * @adev: amdgpu_device pointer 2447 * 2448 * Enables the ring and loads the clear state context and other 2449 * packets required to init the ring. 2450 * Returns 0 for success, error for failure. 2451 */ 2452 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2453 { 2454 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2455 const struct cs_section_def *sect = NULL; 2456 const struct cs_extent_def *ext = NULL; 2457 int r, i; 2458 2459 /* init the CP */ 2460 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2461 WREG32(mmCP_ENDIAN_SWAP, 0); 2462 WREG32(mmCP_DEVICE_ID, 1); 2463 2464 gfx_v7_0_cp_gfx_enable(adev, true); 2465 2466 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2467 if (r) { 2468 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2469 return r; 2470 } 2471 2472 /* init the CE partitions. CE only used for gfx on CIK */ 2473 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2474 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2475 amdgpu_ring_write(ring, 0x8000); 2476 amdgpu_ring_write(ring, 0x8000); 2477 2478 /* clear state buffer */ 2479 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2480 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2481 2482 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2483 amdgpu_ring_write(ring, 0x80000000); 2484 amdgpu_ring_write(ring, 0x80000000); 2485 2486 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2487 for (ext = sect->section; ext->extent != NULL; ++ext) { 2488 if (sect->id == SECT_CONTEXT) { 2489 amdgpu_ring_write(ring, 2490 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2491 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2492 for (i = 0; i < ext->reg_count; i++) 2493 amdgpu_ring_write(ring, ext->extent[i]); 2494 } 2495 } 2496 } 2497 2498 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2499 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2500 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2501 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2502 2503 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2504 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2505 2506 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2507 amdgpu_ring_write(ring, 0); 2508 2509 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2510 amdgpu_ring_write(ring, 0x00000316); 2511 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2512 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2513 2514 amdgpu_ring_commit(ring); 2515 2516 return 0; 2517 } 2518 2519 /** 2520 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2521 * 2522 * @adev: amdgpu_device pointer 2523 * 2524 * Program the location and size of the gfx ring buffer 2525 * and test it to make sure it's working. 2526 * Returns 0 for success, error for failure. 2527 */ 2528 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2529 { 2530 struct amdgpu_ring *ring; 2531 u32 tmp; 2532 u32 rb_bufsz; 2533 u64 rb_addr, rptr_addr; 2534 int r; 2535 2536 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2537 if (adev->asic_type != CHIP_HAWAII) 2538 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2539 2540 /* Set the write pointer delay */ 2541 WREG32(mmCP_RB_WPTR_DELAY, 0); 2542 2543 /* set the RB to use vmid 0 */ 2544 WREG32(mmCP_RB_VMID, 0); 2545 2546 WREG32(mmSCRATCH_ADDR, 0); 2547 2548 /* ring 0 - compute and gfx */ 2549 /* Set ring buffer size */ 2550 ring = &adev->gfx.gfx_ring[0]; 2551 rb_bufsz = order_base_2(ring->ring_size / 8); 2552 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2553 #ifdef __BIG_ENDIAN 2554 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2555 #endif 2556 WREG32(mmCP_RB0_CNTL, tmp); 2557 2558 /* Initialize the ring buffer's read and write pointers */ 2559 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2560 ring->wptr = 0; 2561 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2562 2563 /* set the wb address wether it's enabled or not */ 2564 rptr_addr = ring->rptr_gpu_addr; 2565 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2566 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2567 2568 /* scratch register shadowing is no longer supported */ 2569 WREG32(mmSCRATCH_UMSK, 0); 2570 2571 mdelay(1); 2572 WREG32(mmCP_RB0_CNTL, tmp); 2573 2574 rb_addr = ring->gpu_addr >> 8; 2575 WREG32(mmCP_RB0_BASE, rb_addr); 2576 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2577 2578 /* start the ring */ 2579 gfx_v7_0_cp_gfx_start(adev); 2580 r = amdgpu_ring_test_helper(ring); 2581 if (r) 2582 return r; 2583 2584 return 0; 2585 } 2586 2587 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2588 { 2589 return *ring->rptr_cpu_addr; 2590 } 2591 2592 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2593 { 2594 struct amdgpu_device *adev = ring->adev; 2595 2596 return RREG32(mmCP_RB0_WPTR); 2597 } 2598 2599 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2600 { 2601 struct amdgpu_device *adev = ring->adev; 2602 2603 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2604 (void)RREG32(mmCP_RB0_WPTR); 2605 } 2606 2607 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2608 { 2609 /* XXX check if swapping is necessary on BE */ 2610 return *ring->wptr_cpu_addr; 2611 } 2612 2613 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2614 { 2615 struct amdgpu_device *adev = ring->adev; 2616 2617 /* XXX check if swapping is necessary on BE */ 2618 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2619 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2620 } 2621 2622 /** 2623 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2624 * 2625 * @adev: amdgpu_device pointer 2626 * @enable: enable or disable the MEs 2627 * 2628 * Halts or unhalts the compute MEs. 2629 */ 2630 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2631 { 2632 if (enable) 2633 WREG32(mmCP_MEC_CNTL, 0); 2634 else 2635 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2636 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2637 udelay(50); 2638 } 2639 2640 /** 2641 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2642 * 2643 * @adev: amdgpu_device pointer 2644 * 2645 * Loads the compute MEC1&2 ucode. 2646 * Returns 0 for success, -EINVAL if the ucode is not available. 2647 */ 2648 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2649 { 2650 const struct gfx_firmware_header_v1_0 *mec_hdr; 2651 const __le32 *fw_data; 2652 unsigned i, fw_size; 2653 2654 if (!adev->gfx.mec_fw) 2655 return -EINVAL; 2656 2657 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2658 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2659 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2660 adev->gfx.mec_feature_version = le32_to_cpu( 2661 mec_hdr->ucode_feature_version); 2662 2663 gfx_v7_0_cp_compute_enable(adev, false); 2664 2665 /* MEC1 */ 2666 fw_data = (const __le32 *) 2667 (adev->gfx.mec_fw->data + 2668 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2669 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2670 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2671 for (i = 0; i < fw_size; i++) 2672 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2673 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2674 2675 if (adev->asic_type == CHIP_KAVERI) { 2676 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2677 2678 if (!adev->gfx.mec2_fw) 2679 return -EINVAL; 2680 2681 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2682 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2683 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2684 adev->gfx.mec2_feature_version = le32_to_cpu( 2685 mec2_hdr->ucode_feature_version); 2686 2687 /* MEC2 */ 2688 fw_data = (const __le32 *) 2689 (adev->gfx.mec2_fw->data + 2690 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2691 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2692 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2693 for (i = 0; i < fw_size; i++) 2694 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2695 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2696 } 2697 2698 return 0; 2699 } 2700 2701 /** 2702 * gfx_v7_0_cp_compute_fini - stop the compute queues 2703 * 2704 * @adev: amdgpu_device pointer 2705 * 2706 * Stop the compute queues and tear down the driver queue 2707 * info. 2708 */ 2709 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2710 { 2711 int i; 2712 2713 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2714 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2715 2716 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); 2717 } 2718 } 2719 2720 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2721 { 2722 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2723 } 2724 2725 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2726 { 2727 int r; 2728 u32 *hpd; 2729 size_t mec_hpd_size; 2730 2731 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2732 2733 /* take ownership of the relevant compute queues */ 2734 amdgpu_gfx_compute_queue_acquire(adev); 2735 2736 /* allocate space for ALL pipes (even the ones we don't own) */ 2737 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2738 * GFX7_MEC_HPD_SIZE * 2; 2739 2740 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2741 AMDGPU_GEM_DOMAIN_VRAM | 2742 AMDGPU_GEM_DOMAIN_GTT, 2743 &adev->gfx.mec.hpd_eop_obj, 2744 &adev->gfx.mec.hpd_eop_gpu_addr, 2745 (void **)&hpd); 2746 if (r) { 2747 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2748 gfx_v7_0_mec_fini(adev); 2749 return r; 2750 } 2751 2752 /* clear memory. Not sure if this is required or not */ 2753 memset(hpd, 0, mec_hpd_size); 2754 2755 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2756 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2757 2758 return 0; 2759 } 2760 2761 struct hqd_registers 2762 { 2763 u32 cp_mqd_base_addr; 2764 u32 cp_mqd_base_addr_hi; 2765 u32 cp_hqd_active; 2766 u32 cp_hqd_vmid; 2767 u32 cp_hqd_persistent_state; 2768 u32 cp_hqd_pipe_priority; 2769 u32 cp_hqd_queue_priority; 2770 u32 cp_hqd_quantum; 2771 u32 cp_hqd_pq_base; 2772 u32 cp_hqd_pq_base_hi; 2773 u32 cp_hqd_pq_rptr; 2774 u32 cp_hqd_pq_rptr_report_addr; 2775 u32 cp_hqd_pq_rptr_report_addr_hi; 2776 u32 cp_hqd_pq_wptr_poll_addr; 2777 u32 cp_hqd_pq_wptr_poll_addr_hi; 2778 u32 cp_hqd_pq_doorbell_control; 2779 u32 cp_hqd_pq_wptr; 2780 u32 cp_hqd_pq_control; 2781 u32 cp_hqd_ib_base_addr; 2782 u32 cp_hqd_ib_base_addr_hi; 2783 u32 cp_hqd_ib_rptr; 2784 u32 cp_hqd_ib_control; 2785 u32 cp_hqd_iq_timer; 2786 u32 cp_hqd_iq_rptr; 2787 u32 cp_hqd_dequeue_request; 2788 u32 cp_hqd_dma_offload; 2789 u32 cp_hqd_sema_cmd; 2790 u32 cp_hqd_msg_type; 2791 u32 cp_hqd_atomic0_preop_lo; 2792 u32 cp_hqd_atomic0_preop_hi; 2793 u32 cp_hqd_atomic1_preop_lo; 2794 u32 cp_hqd_atomic1_preop_hi; 2795 u32 cp_hqd_hq_scheduler0; 2796 u32 cp_hqd_hq_scheduler1; 2797 u32 cp_mqd_control; 2798 }; 2799 2800 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2801 int mec, int pipe) 2802 { 2803 u64 eop_gpu_addr; 2804 u32 tmp; 2805 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2806 * GFX7_MEC_HPD_SIZE * 2; 2807 2808 mutex_lock(&adev->srbm_mutex); 2809 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2810 2811 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2812 2813 /* write the EOP addr */ 2814 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2815 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2816 2817 /* set the VMID assigned */ 2818 WREG32(mmCP_HPD_EOP_VMID, 0); 2819 2820 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2821 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2822 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2823 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2824 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2825 2826 cik_srbm_select(adev, 0, 0, 0, 0); 2827 mutex_unlock(&adev->srbm_mutex); 2828 } 2829 2830 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) 2831 { 2832 int i; 2833 2834 /* disable the queue if it's active */ 2835 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2836 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2837 for (i = 0; i < adev->usec_timeout; i++) { 2838 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2839 break; 2840 udelay(1); 2841 } 2842 2843 if (i == adev->usec_timeout) 2844 return -ETIMEDOUT; 2845 2846 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2847 WREG32(mmCP_HQD_PQ_RPTR, 0); 2848 WREG32(mmCP_HQD_PQ_WPTR, 0); 2849 } 2850 2851 return 0; 2852 } 2853 2854 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2855 struct cik_mqd *mqd, 2856 uint64_t mqd_gpu_addr, 2857 struct amdgpu_ring *ring) 2858 { 2859 u64 hqd_gpu_addr; 2860 u64 wb_gpu_addr; 2861 2862 /* init the mqd struct */ 2863 memset(mqd, 0, sizeof(struct cik_mqd)); 2864 2865 mqd->header = 0xC0310800; 2866 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2867 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2868 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2869 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2870 2871 /* enable doorbell? */ 2872 mqd->cp_hqd_pq_doorbell_control = 2873 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2874 if (ring->use_doorbell) 2875 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2876 else 2877 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2878 2879 /* set the pointer to the MQD */ 2880 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2881 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2882 2883 /* set MQD vmid to 0 */ 2884 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2885 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2886 2887 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2888 hqd_gpu_addr = ring->gpu_addr >> 8; 2889 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2890 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2891 2892 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2893 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2894 mqd->cp_hqd_pq_control &= 2895 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2896 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2897 2898 mqd->cp_hqd_pq_control |= 2899 order_base_2(ring->ring_size / 8); 2900 mqd->cp_hqd_pq_control |= 2901 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2902 #ifdef __BIG_ENDIAN 2903 mqd->cp_hqd_pq_control |= 2904 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2905 #endif 2906 mqd->cp_hqd_pq_control &= 2907 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2908 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2909 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2910 mqd->cp_hqd_pq_control |= 2911 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2912 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2913 2914 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2915 wb_gpu_addr = ring->wptr_gpu_addr; 2916 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2917 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2918 2919 /* set the wb address wether it's enabled or not */ 2920 wb_gpu_addr = ring->rptr_gpu_addr; 2921 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2922 mqd->cp_hqd_pq_rptr_report_addr_hi = 2923 upper_32_bits(wb_gpu_addr) & 0xffff; 2924 2925 /* enable the doorbell if requested */ 2926 if (ring->use_doorbell) { 2927 mqd->cp_hqd_pq_doorbell_control = 2928 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2929 mqd->cp_hqd_pq_doorbell_control &= 2930 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2931 mqd->cp_hqd_pq_doorbell_control |= 2932 (ring->doorbell_index << 2933 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2934 mqd->cp_hqd_pq_doorbell_control |= 2935 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2936 mqd->cp_hqd_pq_doorbell_control &= 2937 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 2938 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 2939 2940 } else { 2941 mqd->cp_hqd_pq_doorbell_control = 0; 2942 } 2943 2944 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2945 ring->wptr = 0; 2946 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 2947 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2948 2949 /* set the vmid for the queue */ 2950 mqd->cp_hqd_vmid = 0; 2951 2952 /* defaults */ 2953 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 2954 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 2955 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 2956 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 2957 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 2958 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 2959 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 2960 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 2961 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 2962 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 2963 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 2964 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2965 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 2966 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 2967 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 2968 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 2969 2970 /* activate the queue */ 2971 mqd->cp_hqd_active = 1; 2972 } 2973 2974 static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 2975 { 2976 uint32_t tmp; 2977 uint32_t mqd_reg; 2978 uint32_t *mqd_data; 2979 2980 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 2981 mqd_data = &mqd->cp_mqd_base_addr_lo; 2982 2983 /* disable wptr polling */ 2984 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 2985 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2986 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 2987 2988 /* program all HQD registers */ 2989 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 2990 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2991 2992 /* activate the HQD */ 2993 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 2994 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 2995 2996 return 0; 2997 } 2998 2999 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 3000 { 3001 int r; 3002 u64 mqd_gpu_addr; 3003 struct cik_mqd *mqd; 3004 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3005 3006 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, 3007 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 3008 &mqd_gpu_addr, (void **)&mqd); 3009 if (r) { 3010 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3011 return r; 3012 } 3013 3014 mutex_lock(&adev->srbm_mutex); 3015 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3016 3017 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); 3018 gfx_v7_0_mqd_deactivate(adev); 3019 gfx_v7_0_mqd_commit(adev, mqd); 3020 3021 cik_srbm_select(adev, 0, 0, 0, 0); 3022 mutex_unlock(&adev->srbm_mutex); 3023 3024 amdgpu_bo_kunmap(ring->mqd_obj); 3025 amdgpu_bo_unreserve(ring->mqd_obj); 3026 return 0; 3027 } 3028 3029 /** 3030 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 3031 * 3032 * @adev: amdgpu_device pointer 3033 * 3034 * Program the compute queues and test them to make sure they 3035 * are working. 3036 * Returns 0 for success, error for failure. 3037 */ 3038 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3039 { 3040 int r, i, j; 3041 u32 tmp; 3042 struct amdgpu_ring *ring; 3043 3044 /* fix up chicken bits */ 3045 tmp = RREG32(mmCP_CPF_DEBUG); 3046 tmp |= (1 << 23); 3047 WREG32(mmCP_CPF_DEBUG, tmp); 3048 3049 /* init all pipes (even the ones we don't own) */ 3050 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3051 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3052 gfx_v7_0_compute_pipe_init(adev, i, j); 3053 3054 /* init the queues */ 3055 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3056 r = gfx_v7_0_compute_queue_init(adev, i); 3057 if (r) { 3058 gfx_v7_0_cp_compute_fini(adev); 3059 return r; 3060 } 3061 } 3062 3063 gfx_v7_0_cp_compute_enable(adev, true); 3064 3065 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3066 ring = &adev->gfx.compute_ring[i]; 3067 amdgpu_ring_test_helper(ring); 3068 } 3069 3070 return 0; 3071 } 3072 3073 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3074 { 3075 gfx_v7_0_cp_gfx_enable(adev, enable); 3076 gfx_v7_0_cp_compute_enable(adev, enable); 3077 } 3078 3079 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3080 { 3081 int r; 3082 3083 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3084 if (r) 3085 return r; 3086 r = gfx_v7_0_cp_compute_load_microcode(adev); 3087 if (r) 3088 return r; 3089 3090 return 0; 3091 } 3092 3093 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3094 bool enable) 3095 { 3096 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3097 3098 if (enable) 3099 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3100 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3101 else 3102 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3103 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3104 WREG32(mmCP_INT_CNTL_RING0, tmp); 3105 } 3106 3107 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3108 { 3109 int r; 3110 3111 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3112 3113 r = gfx_v7_0_cp_load_microcode(adev); 3114 if (r) 3115 return r; 3116 3117 r = gfx_v7_0_cp_gfx_resume(adev); 3118 if (r) 3119 return r; 3120 r = gfx_v7_0_cp_compute_resume(adev); 3121 if (r) 3122 return r; 3123 3124 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3125 3126 return 0; 3127 } 3128 3129 /** 3130 * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP 3131 * 3132 * @ring: the ring to emit the commands to 3133 * 3134 * Sync the command pipeline with the PFP. E.g. wait for everything 3135 * to be completed. 3136 */ 3137 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3138 { 3139 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3140 uint32_t seq = ring->fence_drv.sync_seq; 3141 uint64_t addr = ring->fence_drv.gpu_addr; 3142 3143 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3144 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3145 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3146 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3147 amdgpu_ring_write(ring, addr & 0xfffffffc); 3148 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3149 amdgpu_ring_write(ring, seq); 3150 amdgpu_ring_write(ring, 0xffffffff); 3151 amdgpu_ring_write(ring, 4); /* poll interval */ 3152 3153 if (usepfp) { 3154 /* sync CE with ME to prevent CE fetch CEIB before context switch done */ 3155 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3156 amdgpu_ring_write(ring, 0); 3157 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3158 amdgpu_ring_write(ring, 0); 3159 } 3160 } 3161 3162 /* 3163 * vm 3164 * VMID 0 is the physical GPU addresses as used by the kernel. 3165 * VMIDs 1-15 are used for userspace clients and are handled 3166 * by the amdgpu vm/hsa code. 3167 */ 3168 /** 3169 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3170 * 3171 * @ring: amdgpu_ring pointer 3172 * @vmid: vmid number to use 3173 * @pd_addr: address 3174 * 3175 * Update the page table base and flush the VM TLB 3176 * using the CP (CIK). 3177 */ 3178 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3179 unsigned vmid, uint64_t pd_addr) 3180 { 3181 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3182 3183 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3184 3185 /* wait for the invalidate to complete */ 3186 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3187 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3188 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3189 WAIT_REG_MEM_ENGINE(0))); /* me */ 3190 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3191 amdgpu_ring_write(ring, 0); 3192 amdgpu_ring_write(ring, 0); /* ref */ 3193 amdgpu_ring_write(ring, 0); /* mask */ 3194 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3195 3196 /* compute doesn't have PFP */ 3197 if (usepfp) { 3198 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3199 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3200 amdgpu_ring_write(ring, 0x0); 3201 3202 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3203 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3204 amdgpu_ring_write(ring, 0); 3205 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3206 amdgpu_ring_write(ring, 0); 3207 } 3208 } 3209 3210 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 3211 uint32_t reg, uint32_t val) 3212 { 3213 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3214 3215 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3216 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3217 WRITE_DATA_DST_SEL(0))); 3218 amdgpu_ring_write(ring, reg); 3219 amdgpu_ring_write(ring, 0); 3220 amdgpu_ring_write(ring, val); 3221 } 3222 3223 /* 3224 * RLC 3225 * The RLC is a multi-purpose microengine that handles a 3226 * variety of functions. 3227 */ 3228 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3229 { 3230 const u32 *src_ptr; 3231 u32 dws; 3232 const struct cs_section_def *cs_data; 3233 int r; 3234 3235 /* allocate rlc buffers */ 3236 if (adev->flags & AMD_IS_APU) { 3237 if (adev->asic_type == CHIP_KAVERI) { 3238 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3239 adev->gfx.rlc.reg_list_size = 3240 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3241 } else { 3242 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3243 adev->gfx.rlc.reg_list_size = 3244 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3245 } 3246 } 3247 adev->gfx.rlc.cs_data = ci_cs_data; 3248 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3249 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3250 3251 src_ptr = adev->gfx.rlc.reg_list; 3252 dws = adev->gfx.rlc.reg_list_size; 3253 dws += (5 * 16) + 48 + 48 + 64; 3254 3255 cs_data = adev->gfx.rlc.cs_data; 3256 3257 if (src_ptr) { 3258 /* init save restore block */ 3259 r = amdgpu_gfx_rlc_init_sr(adev, dws); 3260 if (r) 3261 return r; 3262 } 3263 3264 if (cs_data) { 3265 /* init clear state block */ 3266 r = amdgpu_gfx_rlc_init_csb(adev); 3267 if (r) 3268 return r; 3269 } 3270 3271 if (adev->gfx.rlc.cp_table_size) { 3272 r = amdgpu_gfx_rlc_init_cpt(adev); 3273 if (r) 3274 return r; 3275 } 3276 3277 /* init spm vmid with 0xf */ 3278 if (adev->gfx.rlc.funcs->update_spm_vmid) 3279 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 3280 3281 return 0; 3282 } 3283 3284 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3285 { 3286 u32 tmp; 3287 3288 tmp = RREG32(mmRLC_LB_CNTL); 3289 if (enable) 3290 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3291 else 3292 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3293 WREG32(mmRLC_LB_CNTL, tmp); 3294 } 3295 3296 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3297 { 3298 u32 i, j, k; 3299 u32 mask; 3300 3301 mutex_lock(&adev->grbm_idx_mutex); 3302 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3303 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3304 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3305 for (k = 0; k < adev->usec_timeout; k++) { 3306 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3307 break; 3308 udelay(1); 3309 } 3310 } 3311 } 3312 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3313 mutex_unlock(&adev->grbm_idx_mutex); 3314 3315 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3316 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3317 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3318 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3319 for (k = 0; k < adev->usec_timeout; k++) { 3320 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3321 break; 3322 udelay(1); 3323 } 3324 } 3325 3326 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3327 { 3328 u32 tmp; 3329 3330 tmp = RREG32(mmRLC_CNTL); 3331 if (tmp != rlc) 3332 WREG32(mmRLC_CNTL, rlc); 3333 } 3334 3335 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3336 { 3337 u32 data, orig; 3338 3339 orig = data = RREG32(mmRLC_CNTL); 3340 3341 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3342 u32 i; 3343 3344 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3345 WREG32(mmRLC_CNTL, data); 3346 3347 for (i = 0; i < adev->usec_timeout; i++) { 3348 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3349 break; 3350 udelay(1); 3351 } 3352 3353 gfx_v7_0_wait_for_rlc_serdes(adev); 3354 } 3355 3356 return orig; 3357 } 3358 3359 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 3360 { 3361 return true; 3362 } 3363 3364 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) 3365 { 3366 u32 tmp, i, mask; 3367 3368 tmp = 0x1 | (1 << 1); 3369 WREG32(mmRLC_GPR_REG2, tmp); 3370 3371 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3372 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3373 for (i = 0; i < adev->usec_timeout; i++) { 3374 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3375 break; 3376 udelay(1); 3377 } 3378 3379 for (i = 0; i < adev->usec_timeout; i++) { 3380 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3381 break; 3382 udelay(1); 3383 } 3384 } 3385 3386 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev) 3387 { 3388 u32 tmp; 3389 3390 tmp = 0x1 | (0 << 1); 3391 WREG32(mmRLC_GPR_REG2, tmp); 3392 } 3393 3394 /** 3395 * gfx_v7_0_rlc_stop - stop the RLC ME 3396 * 3397 * @adev: amdgpu_device pointer 3398 * 3399 * Halt the RLC ME (MicroEngine) (CIK). 3400 */ 3401 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3402 { 3403 WREG32(mmRLC_CNTL, 0); 3404 3405 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3406 3407 gfx_v7_0_wait_for_rlc_serdes(adev); 3408 } 3409 3410 /** 3411 * gfx_v7_0_rlc_start - start the RLC ME 3412 * 3413 * @adev: amdgpu_device pointer 3414 * 3415 * Unhalt the RLC ME (MicroEngine) (CIK). 3416 */ 3417 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3418 { 3419 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3420 3421 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3422 3423 udelay(50); 3424 } 3425 3426 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3427 { 3428 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3429 3430 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3431 WREG32(mmGRBM_SOFT_RESET, tmp); 3432 udelay(50); 3433 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3434 WREG32(mmGRBM_SOFT_RESET, tmp); 3435 udelay(50); 3436 } 3437 3438 /** 3439 * gfx_v7_0_rlc_resume - setup the RLC hw 3440 * 3441 * @adev: amdgpu_device pointer 3442 * 3443 * Initialize the RLC registers, load the ucode, 3444 * and start the RLC (CIK). 3445 * Returns 0 for success, -EINVAL if the ucode is not available. 3446 */ 3447 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3448 { 3449 const struct rlc_firmware_header_v1_0 *hdr; 3450 const __le32 *fw_data; 3451 unsigned i, fw_size; 3452 u32 tmp; 3453 3454 if (!adev->gfx.rlc_fw) 3455 return -EINVAL; 3456 3457 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3458 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3459 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3460 adev->gfx.rlc_feature_version = le32_to_cpu( 3461 hdr->ucode_feature_version); 3462 3463 adev->gfx.rlc.funcs->stop(adev); 3464 3465 /* disable CG */ 3466 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3467 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3468 3469 adev->gfx.rlc.funcs->reset(adev); 3470 3471 gfx_v7_0_init_pg(adev); 3472 3473 WREG32(mmRLC_LB_CNTR_INIT, 0); 3474 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3475 3476 mutex_lock(&adev->grbm_idx_mutex); 3477 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3478 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3479 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3480 WREG32(mmRLC_LB_CNTL, 0x80000004); 3481 mutex_unlock(&adev->grbm_idx_mutex); 3482 3483 WREG32(mmRLC_MC_CNTL, 0); 3484 WREG32(mmRLC_UCODE_CNTL, 0); 3485 3486 fw_data = (const __le32 *) 3487 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3488 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3489 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3490 for (i = 0; i < fw_size; i++) 3491 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3492 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3493 3494 /* XXX - find out what chips support lbpw */ 3495 gfx_v7_0_enable_lbpw(adev, false); 3496 3497 if (adev->asic_type == CHIP_BONAIRE) 3498 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3499 3500 adev->gfx.rlc.funcs->start(adev); 3501 3502 return 0; 3503 } 3504 3505 static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 3506 { 3507 u32 data; 3508 3509 amdgpu_gfx_off_ctrl(adev, false); 3510 3511 data = RREG32(mmRLC_SPM_VMID); 3512 3513 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK; 3514 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT; 3515 3516 WREG32(mmRLC_SPM_VMID, data); 3517 3518 amdgpu_gfx_off_ctrl(adev, true); 3519 } 3520 3521 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3522 { 3523 u32 data, orig, tmp, tmp2; 3524 3525 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3526 3527 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3528 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3529 3530 tmp = gfx_v7_0_halt_rlc(adev); 3531 3532 mutex_lock(&adev->grbm_idx_mutex); 3533 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3534 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3535 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3536 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3537 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3538 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3539 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3540 mutex_unlock(&adev->grbm_idx_mutex); 3541 3542 gfx_v7_0_update_rlc(adev, tmp); 3543 3544 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3545 if (orig != data) 3546 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3547 3548 } else { 3549 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3550 3551 RREG32(mmCB_CGTT_SCLK_CTRL); 3552 RREG32(mmCB_CGTT_SCLK_CTRL); 3553 RREG32(mmCB_CGTT_SCLK_CTRL); 3554 RREG32(mmCB_CGTT_SCLK_CTRL); 3555 3556 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3557 if (orig != data) 3558 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3559 3560 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3561 } 3562 } 3563 3564 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3565 { 3566 u32 data, orig, tmp = 0; 3567 3568 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3569 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3570 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3571 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3572 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3573 if (orig != data) 3574 WREG32(mmCP_MEM_SLP_CNTL, data); 3575 } 3576 } 3577 3578 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3579 data |= 0x00000001; 3580 data &= 0xfffffffd; 3581 if (orig != data) 3582 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3583 3584 tmp = gfx_v7_0_halt_rlc(adev); 3585 3586 mutex_lock(&adev->grbm_idx_mutex); 3587 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3588 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3589 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3590 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3591 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3592 WREG32(mmRLC_SERDES_WR_CTRL, data); 3593 mutex_unlock(&adev->grbm_idx_mutex); 3594 3595 gfx_v7_0_update_rlc(adev, tmp); 3596 3597 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3598 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3599 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3600 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3601 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3602 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3603 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3604 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3605 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3606 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3607 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3608 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3609 if (orig != data) 3610 WREG32(mmCGTS_SM_CTRL_REG, data); 3611 } 3612 } else { 3613 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3614 data |= 0x00000003; 3615 if (orig != data) 3616 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3617 3618 data = RREG32(mmRLC_MEM_SLP_CNTL); 3619 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3620 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3621 WREG32(mmRLC_MEM_SLP_CNTL, data); 3622 } 3623 3624 data = RREG32(mmCP_MEM_SLP_CNTL); 3625 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3626 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3627 WREG32(mmCP_MEM_SLP_CNTL, data); 3628 } 3629 3630 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3631 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3632 if (orig != data) 3633 WREG32(mmCGTS_SM_CTRL_REG, data); 3634 3635 tmp = gfx_v7_0_halt_rlc(adev); 3636 3637 mutex_lock(&adev->grbm_idx_mutex); 3638 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3639 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3640 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3641 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3642 WREG32(mmRLC_SERDES_WR_CTRL, data); 3643 mutex_unlock(&adev->grbm_idx_mutex); 3644 3645 gfx_v7_0_update_rlc(adev, tmp); 3646 } 3647 } 3648 3649 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3650 bool enable) 3651 { 3652 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3653 /* order matters! */ 3654 if (enable) { 3655 gfx_v7_0_enable_mgcg(adev, true); 3656 gfx_v7_0_enable_cgcg(adev, true); 3657 } else { 3658 gfx_v7_0_enable_cgcg(adev, false); 3659 gfx_v7_0_enable_mgcg(adev, false); 3660 } 3661 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3662 } 3663 3664 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3665 bool enable) 3666 { 3667 u32 data, orig; 3668 3669 orig = data = RREG32(mmRLC_PG_CNTL); 3670 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3671 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3672 else 3673 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3674 if (orig != data) 3675 WREG32(mmRLC_PG_CNTL, data); 3676 } 3677 3678 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3679 bool enable) 3680 { 3681 u32 data, orig; 3682 3683 orig = data = RREG32(mmRLC_PG_CNTL); 3684 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3685 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3686 else 3687 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3688 if (orig != data) 3689 WREG32(mmRLC_PG_CNTL, data); 3690 } 3691 3692 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3693 { 3694 u32 data, orig; 3695 3696 orig = data = RREG32(mmRLC_PG_CNTL); 3697 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3698 data &= ~0x8000; 3699 else 3700 data |= 0x8000; 3701 if (orig != data) 3702 WREG32(mmRLC_PG_CNTL, data); 3703 } 3704 3705 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3706 { 3707 u32 data, orig; 3708 3709 orig = data = RREG32(mmRLC_PG_CNTL); 3710 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3711 data &= ~0x2000; 3712 else 3713 data |= 0x2000; 3714 if (orig != data) 3715 WREG32(mmRLC_PG_CNTL, data); 3716 } 3717 3718 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) 3719 { 3720 if (adev->asic_type == CHIP_KAVERI) 3721 return 5; 3722 else 3723 return 4; 3724 } 3725 3726 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3727 bool enable) 3728 { 3729 u32 data, orig; 3730 3731 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3732 orig = data = RREG32(mmRLC_PG_CNTL); 3733 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3734 if (orig != data) 3735 WREG32(mmRLC_PG_CNTL, data); 3736 3737 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3738 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3739 if (orig != data) 3740 WREG32(mmRLC_AUTO_PG_CTRL, data); 3741 } else { 3742 orig = data = RREG32(mmRLC_PG_CNTL); 3743 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3744 if (orig != data) 3745 WREG32(mmRLC_PG_CNTL, data); 3746 3747 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3748 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3749 if (orig != data) 3750 WREG32(mmRLC_AUTO_PG_CTRL, data); 3751 3752 data = RREG32(mmDB_RENDER_CONTROL); 3753 } 3754 } 3755 3756 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3757 u32 bitmap) 3758 { 3759 u32 data; 3760 3761 if (!bitmap) 3762 return; 3763 3764 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3765 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3766 3767 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3768 } 3769 3770 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3771 { 3772 u32 data, mask; 3773 3774 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3775 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3776 3777 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3778 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3779 3780 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3781 3782 return (~data) & mask; 3783 } 3784 3785 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3786 { 3787 u32 tmp; 3788 3789 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3790 3791 tmp = RREG32(mmRLC_MAX_PG_CU); 3792 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3793 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3794 WREG32(mmRLC_MAX_PG_CU, tmp); 3795 } 3796 3797 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3798 bool enable) 3799 { 3800 u32 data, orig; 3801 3802 orig = data = RREG32(mmRLC_PG_CNTL); 3803 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3804 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3805 else 3806 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3807 if (orig != data) 3808 WREG32(mmRLC_PG_CNTL, data); 3809 } 3810 3811 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3812 bool enable) 3813 { 3814 u32 data, orig; 3815 3816 orig = data = RREG32(mmRLC_PG_CNTL); 3817 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3818 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3819 else 3820 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3821 if (orig != data) 3822 WREG32(mmRLC_PG_CNTL, data); 3823 } 3824 3825 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3826 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3827 3828 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3829 { 3830 u32 data, orig; 3831 u32 i; 3832 3833 if (adev->gfx.rlc.cs_data) { 3834 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3835 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3836 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3837 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3838 } else { 3839 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3840 for (i = 0; i < 3; i++) 3841 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3842 } 3843 if (adev->gfx.rlc.reg_list) { 3844 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3845 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3846 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3847 } 3848 3849 orig = data = RREG32(mmRLC_PG_CNTL); 3850 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3851 if (orig != data) 3852 WREG32(mmRLC_PG_CNTL, data); 3853 3854 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3855 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3856 3857 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3858 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3859 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3860 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3861 3862 data = 0x10101010; 3863 WREG32(mmRLC_PG_DELAY, data); 3864 3865 data = RREG32(mmRLC_PG_DELAY_2); 3866 data &= ~0xff; 3867 data |= 0x3; 3868 WREG32(mmRLC_PG_DELAY_2, data); 3869 3870 data = RREG32(mmRLC_AUTO_PG_CTRL); 3871 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3872 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3873 WREG32(mmRLC_AUTO_PG_CTRL, data); 3874 3875 } 3876 3877 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3878 { 3879 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3880 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3881 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3882 } 3883 3884 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3885 { 3886 u32 count = 0; 3887 const struct cs_section_def *sect = NULL; 3888 const struct cs_extent_def *ext = NULL; 3889 3890 if (adev->gfx.rlc.cs_data == NULL) 3891 return 0; 3892 3893 /* begin clear state */ 3894 count += 2; 3895 /* context control state */ 3896 count += 3; 3897 3898 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3899 for (ext = sect->section; ext->extent != NULL; ++ext) { 3900 if (sect->id == SECT_CONTEXT) 3901 count += 2 + ext->reg_count; 3902 else 3903 return 0; 3904 } 3905 } 3906 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3907 count += 4; 3908 /* end clear state */ 3909 count += 2; 3910 /* clear state */ 3911 count += 2; 3912 3913 return count; 3914 } 3915 3916 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 3917 volatile u32 *buffer) 3918 { 3919 u32 count = 0, i; 3920 const struct cs_section_def *sect = NULL; 3921 const struct cs_extent_def *ext = NULL; 3922 3923 if (adev->gfx.rlc.cs_data == NULL) 3924 return; 3925 if (buffer == NULL) 3926 return; 3927 3928 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3929 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3930 3931 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3932 buffer[count++] = cpu_to_le32(0x80000000); 3933 buffer[count++] = cpu_to_le32(0x80000000); 3934 3935 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3936 for (ext = sect->section; ext->extent != NULL; ++ext) { 3937 if (sect->id == SECT_CONTEXT) { 3938 buffer[count++] = 3939 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 3940 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3941 for (i = 0; i < ext->reg_count; i++) 3942 buffer[count++] = cpu_to_le32(ext->extent[i]); 3943 } else { 3944 return; 3945 } 3946 } 3947 } 3948 3949 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 3950 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3951 switch (adev->asic_type) { 3952 case CHIP_BONAIRE: 3953 buffer[count++] = cpu_to_le32(0x16000012); 3954 buffer[count++] = cpu_to_le32(0x00000000); 3955 break; 3956 case CHIP_KAVERI: 3957 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 3958 buffer[count++] = cpu_to_le32(0x00000000); 3959 break; 3960 case CHIP_KABINI: 3961 case CHIP_MULLINS: 3962 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 3963 buffer[count++] = cpu_to_le32(0x00000000); 3964 break; 3965 case CHIP_HAWAII: 3966 buffer[count++] = cpu_to_le32(0x3a00161a); 3967 buffer[count++] = cpu_to_le32(0x0000002e); 3968 break; 3969 default: 3970 buffer[count++] = cpu_to_le32(0x00000000); 3971 buffer[count++] = cpu_to_le32(0x00000000); 3972 break; 3973 } 3974 3975 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3976 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 3977 3978 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 3979 buffer[count++] = cpu_to_le32(0); 3980 } 3981 3982 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 3983 { 3984 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3985 AMD_PG_SUPPORT_GFX_SMG | 3986 AMD_PG_SUPPORT_GFX_DMG | 3987 AMD_PG_SUPPORT_CP | 3988 AMD_PG_SUPPORT_GDS | 3989 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3990 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 3991 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 3992 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3993 gfx_v7_0_init_gfx_cgpg(adev); 3994 gfx_v7_0_enable_cp_pg(adev, true); 3995 gfx_v7_0_enable_gds_pg(adev, true); 3996 } 3997 gfx_v7_0_init_ao_cu_mask(adev); 3998 gfx_v7_0_update_gfx_pg(adev, true); 3999 } 4000 } 4001 4002 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4003 { 4004 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4005 AMD_PG_SUPPORT_GFX_SMG | 4006 AMD_PG_SUPPORT_GFX_DMG | 4007 AMD_PG_SUPPORT_CP | 4008 AMD_PG_SUPPORT_GDS | 4009 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4010 gfx_v7_0_update_gfx_pg(adev, false); 4011 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4012 gfx_v7_0_enable_cp_pg(adev, false); 4013 gfx_v7_0_enable_gds_pg(adev, false); 4014 } 4015 } 4016 } 4017 4018 /** 4019 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4020 * 4021 * @adev: amdgpu_device pointer 4022 * 4023 * Fetches a GPU clock counter snapshot (SI). 4024 * Returns the 64 bit clock counter snapshot. 4025 */ 4026 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4027 { 4028 uint64_t clock; 4029 4030 mutex_lock(&adev->gfx.gpu_clock_mutex); 4031 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4032 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4033 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4034 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4035 return clock; 4036 } 4037 4038 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4039 uint32_t vmid, 4040 uint32_t gds_base, uint32_t gds_size, 4041 uint32_t gws_base, uint32_t gws_size, 4042 uint32_t oa_base, uint32_t oa_size) 4043 { 4044 /* GDS Base */ 4045 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4046 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4047 WRITE_DATA_DST_SEL(0))); 4048 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4049 amdgpu_ring_write(ring, 0); 4050 amdgpu_ring_write(ring, gds_base); 4051 4052 /* GDS Size */ 4053 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4054 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4055 WRITE_DATA_DST_SEL(0))); 4056 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4057 amdgpu_ring_write(ring, 0); 4058 amdgpu_ring_write(ring, gds_size); 4059 4060 /* GWS */ 4061 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4062 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4063 WRITE_DATA_DST_SEL(0))); 4064 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4065 amdgpu_ring_write(ring, 0); 4066 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4067 4068 /* OA */ 4069 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4070 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4071 WRITE_DATA_DST_SEL(0))); 4072 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4073 amdgpu_ring_write(ring, 0); 4074 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4075 } 4076 4077 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4078 { 4079 struct amdgpu_device *adev = ring->adev; 4080 uint32_t value = 0; 4081 4082 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4083 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4084 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4085 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4086 WREG32(mmSQ_CMD, value); 4087 } 4088 4089 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4090 { 4091 WREG32(mmSQ_IND_INDEX, 4092 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4093 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4094 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4095 (SQ_IND_INDEX__FORCE_READ_MASK)); 4096 return RREG32(mmSQ_IND_DATA); 4097 } 4098 4099 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4100 uint32_t wave, uint32_t thread, 4101 uint32_t regno, uint32_t num, uint32_t *out) 4102 { 4103 WREG32(mmSQ_IND_INDEX, 4104 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4105 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4106 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4107 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4108 (SQ_IND_INDEX__FORCE_READ_MASK) | 4109 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4110 while (num--) 4111 *(out++) = RREG32(mmSQ_IND_DATA); 4112 } 4113 4114 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4115 { 4116 /* type 0 wave data */ 4117 dst[(*no_fields)++] = 0; 4118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4121 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4122 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4123 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4124 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4125 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4126 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4127 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4128 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4129 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4130 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4131 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4132 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4133 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4134 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4135 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4136 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); 4137 } 4138 4139 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4140 uint32_t wave, uint32_t start, 4141 uint32_t size, uint32_t *dst) 4142 { 4143 wave_read_regs( 4144 adev, simd, wave, 0, 4145 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4146 } 4147 4148 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, 4149 u32 me, u32 pipe, u32 q, u32 vm) 4150 { 4151 cik_srbm_select(adev, me, pipe, q, vm); 4152 } 4153 4154 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4155 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4156 .select_se_sh = &gfx_v7_0_select_se_sh, 4157 .read_wave_data = &gfx_v7_0_read_wave_data, 4158 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4159 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q 4160 }; 4161 4162 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4163 .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, 4164 .set_safe_mode = gfx_v7_0_set_safe_mode, 4165 .unset_safe_mode = gfx_v7_0_unset_safe_mode, 4166 .init = gfx_v7_0_rlc_init, 4167 .get_csb_size = gfx_v7_0_get_csb_size, 4168 .get_csb_buffer = gfx_v7_0_get_csb_buffer, 4169 .get_cp_table_num = gfx_v7_0_cp_pg_table_num, 4170 .resume = gfx_v7_0_rlc_resume, 4171 .stop = gfx_v7_0_rlc_stop, 4172 .reset = gfx_v7_0_rlc_reset, 4173 .start = gfx_v7_0_rlc_start, 4174 .update_spm_vmid = gfx_v7_0_update_spm_vmid 4175 }; 4176 4177 static int gfx_v7_0_early_init(void *handle) 4178 { 4179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4180 4181 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4182 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 4183 AMDGPU_MAX_COMPUTE_RINGS); 4184 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4185 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4186 gfx_v7_0_set_ring_funcs(adev); 4187 gfx_v7_0_set_irq_funcs(adev); 4188 gfx_v7_0_set_gds_init(adev); 4189 4190 return 0; 4191 } 4192 4193 static int gfx_v7_0_late_init(void *handle) 4194 { 4195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4196 int r; 4197 4198 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4199 if (r) 4200 return r; 4201 4202 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4203 if (r) 4204 return r; 4205 4206 return 0; 4207 } 4208 4209 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4210 { 4211 u32 gb_addr_config; 4212 u32 mc_arb_ramcfg; 4213 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4214 u32 tmp; 4215 4216 switch (adev->asic_type) { 4217 case CHIP_BONAIRE: 4218 adev->gfx.config.max_shader_engines = 2; 4219 adev->gfx.config.max_tile_pipes = 4; 4220 adev->gfx.config.max_cu_per_sh = 7; 4221 adev->gfx.config.max_sh_per_se = 1; 4222 adev->gfx.config.max_backends_per_se = 2; 4223 adev->gfx.config.max_texture_channel_caches = 4; 4224 adev->gfx.config.max_gprs = 256; 4225 adev->gfx.config.max_gs_threads = 32; 4226 adev->gfx.config.max_hw_contexts = 8; 4227 4228 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4229 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4230 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4231 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4232 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4233 break; 4234 case CHIP_HAWAII: 4235 adev->gfx.config.max_shader_engines = 4; 4236 adev->gfx.config.max_tile_pipes = 16; 4237 adev->gfx.config.max_cu_per_sh = 11; 4238 adev->gfx.config.max_sh_per_se = 1; 4239 adev->gfx.config.max_backends_per_se = 4; 4240 adev->gfx.config.max_texture_channel_caches = 16; 4241 adev->gfx.config.max_gprs = 256; 4242 adev->gfx.config.max_gs_threads = 32; 4243 adev->gfx.config.max_hw_contexts = 8; 4244 4245 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4246 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4247 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4248 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4249 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4250 break; 4251 case CHIP_KAVERI: 4252 adev->gfx.config.max_shader_engines = 1; 4253 adev->gfx.config.max_tile_pipes = 4; 4254 adev->gfx.config.max_cu_per_sh = 8; 4255 adev->gfx.config.max_backends_per_se = 2; 4256 adev->gfx.config.max_sh_per_se = 1; 4257 adev->gfx.config.max_texture_channel_caches = 4; 4258 adev->gfx.config.max_gprs = 256; 4259 adev->gfx.config.max_gs_threads = 16; 4260 adev->gfx.config.max_hw_contexts = 8; 4261 4262 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4263 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4264 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4265 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4266 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4267 break; 4268 case CHIP_KABINI: 4269 case CHIP_MULLINS: 4270 default: 4271 adev->gfx.config.max_shader_engines = 1; 4272 adev->gfx.config.max_tile_pipes = 2; 4273 adev->gfx.config.max_cu_per_sh = 2; 4274 adev->gfx.config.max_sh_per_se = 1; 4275 adev->gfx.config.max_backends_per_se = 1; 4276 adev->gfx.config.max_texture_channel_caches = 2; 4277 adev->gfx.config.max_gprs = 256; 4278 adev->gfx.config.max_gs_threads = 16; 4279 adev->gfx.config.max_hw_contexts = 8; 4280 4281 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4282 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4283 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4284 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4285 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4286 break; 4287 } 4288 4289 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4290 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4291 4292 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, 4293 MC_ARB_RAMCFG, NOOFBANK); 4294 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, 4295 MC_ARB_RAMCFG, NOOFRANKS); 4296 4297 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4298 adev->gfx.config.mem_max_burst_length_bytes = 256; 4299 if (adev->flags & AMD_IS_APU) { 4300 /* Get memory bank mapping mode. */ 4301 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4302 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4303 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4304 4305 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4306 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4307 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4308 4309 /* Validate settings in case only one DIMM installed. */ 4310 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4311 dimm00_addr_map = 0; 4312 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4313 dimm01_addr_map = 0; 4314 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4315 dimm10_addr_map = 0; 4316 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4317 dimm11_addr_map = 0; 4318 4319 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4320 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4321 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4322 adev->gfx.config.mem_row_size_in_kb = 2; 4323 else 4324 adev->gfx.config.mem_row_size_in_kb = 1; 4325 } else { 4326 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4327 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4328 if (adev->gfx.config.mem_row_size_in_kb > 4) 4329 adev->gfx.config.mem_row_size_in_kb = 4; 4330 } 4331 /* XXX use MC settings? */ 4332 adev->gfx.config.shader_engine_tile_size = 32; 4333 adev->gfx.config.num_gpus = 1; 4334 adev->gfx.config.multi_gpu_tile_size = 64; 4335 4336 /* fix up row size */ 4337 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4338 switch (adev->gfx.config.mem_row_size_in_kb) { 4339 case 1: 4340 default: 4341 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4342 break; 4343 case 2: 4344 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4345 break; 4346 case 4: 4347 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4348 break; 4349 } 4350 adev->gfx.config.gb_addr_config = gb_addr_config; 4351 } 4352 4353 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4354 int mec, int pipe, int queue) 4355 { 4356 int r; 4357 unsigned irq_type; 4358 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4359 4360 /* mec0 is me1 */ 4361 ring->me = mec + 1; 4362 ring->pipe = pipe; 4363 ring->queue = queue; 4364 4365 ring->ring_obj = NULL; 4366 ring->use_doorbell = true; 4367 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 4368 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4369 4370 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4371 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4372 + ring->pipe; 4373 4374 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4375 r = amdgpu_ring_init(adev, ring, 1024, 4376 &adev->gfx.eop_irq, irq_type, 4377 AMDGPU_RING_PRIO_DEFAULT, NULL); 4378 if (r) 4379 return r; 4380 4381 4382 return 0; 4383 } 4384 4385 static int gfx_v7_0_sw_init(void *handle) 4386 { 4387 struct amdgpu_ring *ring; 4388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4389 int i, j, k, r, ring_id; 4390 4391 switch (adev->asic_type) { 4392 case CHIP_KAVERI: 4393 adev->gfx.mec.num_mec = 2; 4394 break; 4395 case CHIP_BONAIRE: 4396 case CHIP_HAWAII: 4397 case CHIP_KABINI: 4398 case CHIP_MULLINS: 4399 default: 4400 adev->gfx.mec.num_mec = 1; 4401 break; 4402 } 4403 adev->gfx.mec.num_pipe_per_mec = 4; 4404 adev->gfx.mec.num_queue_per_pipe = 8; 4405 4406 /* EOP Event */ 4407 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4408 if (r) 4409 return r; 4410 4411 /* Privileged reg */ 4412 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, 4413 &adev->gfx.priv_reg_irq); 4414 if (r) 4415 return r; 4416 4417 /* Privileged inst */ 4418 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, 4419 &adev->gfx.priv_inst_irq); 4420 if (r) 4421 return r; 4422 4423 r = gfx_v7_0_init_microcode(adev); 4424 if (r) { 4425 DRM_ERROR("Failed to load gfx firmware!\n"); 4426 return r; 4427 } 4428 4429 r = adev->gfx.rlc.funcs->init(adev); 4430 if (r) { 4431 DRM_ERROR("Failed to init rlc BOs!\n"); 4432 return r; 4433 } 4434 4435 /* allocate mec buffers */ 4436 r = gfx_v7_0_mec_init(adev); 4437 if (r) { 4438 DRM_ERROR("Failed to init MEC BOs!\n"); 4439 return r; 4440 } 4441 4442 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4443 ring = &adev->gfx.gfx_ring[i]; 4444 ring->ring_obj = NULL; 4445 sprintf(ring->name, "gfx"); 4446 r = amdgpu_ring_init(adev, ring, 1024, 4447 &adev->gfx.eop_irq, 4448 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 4449 AMDGPU_RING_PRIO_DEFAULT, NULL); 4450 if (r) 4451 return r; 4452 } 4453 4454 /* set up the compute queues - allocate horizontally across pipes */ 4455 ring_id = 0; 4456 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4457 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4458 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4459 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 4460 continue; 4461 4462 r = gfx_v7_0_compute_ring_init(adev, 4463 ring_id, 4464 i, k, j); 4465 if (r) 4466 return r; 4467 4468 ring_id++; 4469 } 4470 } 4471 } 4472 4473 adev->gfx.ce_ram_size = 0x8000; 4474 4475 gfx_v7_0_gpu_early_init(adev); 4476 4477 return r; 4478 } 4479 4480 static int gfx_v7_0_sw_fini(void *handle) 4481 { 4482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4483 int i; 4484 4485 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4486 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4487 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4488 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4489 4490 gfx_v7_0_cp_compute_fini(adev); 4491 amdgpu_gfx_rlc_fini(adev); 4492 gfx_v7_0_mec_fini(adev); 4493 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4494 &adev->gfx.rlc.clear_state_gpu_addr, 4495 (void **)&adev->gfx.rlc.cs_ptr); 4496 if (adev->gfx.rlc.cp_table_size) { 4497 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4498 &adev->gfx.rlc.cp_table_gpu_addr, 4499 (void **)&adev->gfx.rlc.cp_table_ptr); 4500 } 4501 gfx_v7_0_free_microcode(adev); 4502 4503 return 0; 4504 } 4505 4506 static int gfx_v7_0_hw_init(void *handle) 4507 { 4508 int r; 4509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4510 4511 gfx_v7_0_constants_init(adev); 4512 4513 /* init CSB */ 4514 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 4515 /* init rlc */ 4516 r = adev->gfx.rlc.funcs->resume(adev); 4517 if (r) 4518 return r; 4519 4520 r = gfx_v7_0_cp_resume(adev); 4521 if (r) 4522 return r; 4523 4524 return r; 4525 } 4526 4527 static int gfx_v7_0_hw_fini(void *handle) 4528 { 4529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4530 4531 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4532 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4533 gfx_v7_0_cp_enable(adev, false); 4534 adev->gfx.rlc.funcs->stop(adev); 4535 gfx_v7_0_fini_pg(adev); 4536 4537 return 0; 4538 } 4539 4540 static int gfx_v7_0_suspend(void *handle) 4541 { 4542 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4543 4544 return gfx_v7_0_hw_fini(adev); 4545 } 4546 4547 static int gfx_v7_0_resume(void *handle) 4548 { 4549 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4550 4551 return gfx_v7_0_hw_init(adev); 4552 } 4553 4554 static bool gfx_v7_0_is_idle(void *handle) 4555 { 4556 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4557 4558 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4559 return false; 4560 else 4561 return true; 4562 } 4563 4564 static int gfx_v7_0_wait_for_idle(void *handle) 4565 { 4566 unsigned i; 4567 u32 tmp; 4568 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4569 4570 for (i = 0; i < adev->usec_timeout; i++) { 4571 /* read MC_STATUS */ 4572 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4573 4574 if (!tmp) 4575 return 0; 4576 udelay(1); 4577 } 4578 return -ETIMEDOUT; 4579 } 4580 4581 static int gfx_v7_0_soft_reset(void *handle) 4582 { 4583 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4584 u32 tmp; 4585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4586 4587 /* GRBM_STATUS */ 4588 tmp = RREG32(mmGRBM_STATUS); 4589 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4590 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4591 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4592 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4593 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4594 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4595 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4596 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4597 4598 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4599 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4600 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4601 } 4602 4603 /* GRBM_STATUS2 */ 4604 tmp = RREG32(mmGRBM_STATUS2); 4605 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4606 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4607 4608 /* SRBM_STATUS */ 4609 tmp = RREG32(mmSRBM_STATUS); 4610 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4611 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4612 4613 if (grbm_soft_reset || srbm_soft_reset) { 4614 /* disable CG/PG */ 4615 gfx_v7_0_fini_pg(adev); 4616 gfx_v7_0_update_cg(adev, false); 4617 4618 /* stop the rlc */ 4619 adev->gfx.rlc.funcs->stop(adev); 4620 4621 /* Disable GFX parsing/prefetching */ 4622 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4623 4624 /* Disable MEC parsing/prefetching */ 4625 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4626 4627 if (grbm_soft_reset) { 4628 tmp = RREG32(mmGRBM_SOFT_RESET); 4629 tmp |= grbm_soft_reset; 4630 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4631 WREG32(mmGRBM_SOFT_RESET, tmp); 4632 tmp = RREG32(mmGRBM_SOFT_RESET); 4633 4634 udelay(50); 4635 4636 tmp &= ~grbm_soft_reset; 4637 WREG32(mmGRBM_SOFT_RESET, tmp); 4638 tmp = RREG32(mmGRBM_SOFT_RESET); 4639 } 4640 4641 if (srbm_soft_reset) { 4642 tmp = RREG32(mmSRBM_SOFT_RESET); 4643 tmp |= srbm_soft_reset; 4644 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4645 WREG32(mmSRBM_SOFT_RESET, tmp); 4646 tmp = RREG32(mmSRBM_SOFT_RESET); 4647 4648 udelay(50); 4649 4650 tmp &= ~srbm_soft_reset; 4651 WREG32(mmSRBM_SOFT_RESET, tmp); 4652 tmp = RREG32(mmSRBM_SOFT_RESET); 4653 } 4654 /* Wait a little for things to settle down */ 4655 udelay(50); 4656 } 4657 return 0; 4658 } 4659 4660 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4661 enum amdgpu_interrupt_state state) 4662 { 4663 u32 cp_int_cntl; 4664 4665 switch (state) { 4666 case AMDGPU_IRQ_STATE_DISABLE: 4667 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4668 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4669 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4670 break; 4671 case AMDGPU_IRQ_STATE_ENABLE: 4672 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4673 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4674 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4675 break; 4676 default: 4677 break; 4678 } 4679 } 4680 4681 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4682 int me, int pipe, 4683 enum amdgpu_interrupt_state state) 4684 { 4685 u32 mec_int_cntl, mec_int_cntl_reg; 4686 4687 /* 4688 * amdgpu controls only the first MEC. That's why this function only 4689 * handles the setting of interrupts for this specific MEC. All other 4690 * pipes' interrupts are set by amdkfd. 4691 */ 4692 4693 if (me == 1) { 4694 switch (pipe) { 4695 case 0: 4696 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4697 break; 4698 case 1: 4699 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4700 break; 4701 case 2: 4702 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4703 break; 4704 case 3: 4705 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4706 break; 4707 default: 4708 DRM_DEBUG("invalid pipe %d\n", pipe); 4709 return; 4710 } 4711 } else { 4712 DRM_DEBUG("invalid me %d\n", me); 4713 return; 4714 } 4715 4716 switch (state) { 4717 case AMDGPU_IRQ_STATE_DISABLE: 4718 mec_int_cntl = RREG32(mec_int_cntl_reg); 4719 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4720 WREG32(mec_int_cntl_reg, mec_int_cntl); 4721 break; 4722 case AMDGPU_IRQ_STATE_ENABLE: 4723 mec_int_cntl = RREG32(mec_int_cntl_reg); 4724 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4725 WREG32(mec_int_cntl_reg, mec_int_cntl); 4726 break; 4727 default: 4728 break; 4729 } 4730 } 4731 4732 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4733 struct amdgpu_irq_src *src, 4734 unsigned type, 4735 enum amdgpu_interrupt_state state) 4736 { 4737 u32 cp_int_cntl; 4738 4739 switch (state) { 4740 case AMDGPU_IRQ_STATE_DISABLE: 4741 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4742 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4743 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4744 break; 4745 case AMDGPU_IRQ_STATE_ENABLE: 4746 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4747 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4748 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4749 break; 4750 default: 4751 break; 4752 } 4753 4754 return 0; 4755 } 4756 4757 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4758 struct amdgpu_irq_src *src, 4759 unsigned type, 4760 enum amdgpu_interrupt_state state) 4761 { 4762 u32 cp_int_cntl; 4763 4764 switch (state) { 4765 case AMDGPU_IRQ_STATE_DISABLE: 4766 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4767 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4768 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4769 break; 4770 case AMDGPU_IRQ_STATE_ENABLE: 4771 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4772 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4773 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4774 break; 4775 default: 4776 break; 4777 } 4778 4779 return 0; 4780 } 4781 4782 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4783 struct amdgpu_irq_src *src, 4784 unsigned type, 4785 enum amdgpu_interrupt_state state) 4786 { 4787 switch (type) { 4788 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4789 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4790 break; 4791 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4792 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4793 break; 4794 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4795 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4796 break; 4797 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4798 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4799 break; 4800 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4801 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4802 break; 4803 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4804 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4805 break; 4806 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4807 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4808 break; 4809 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4810 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4811 break; 4812 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4813 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4814 break; 4815 default: 4816 break; 4817 } 4818 return 0; 4819 } 4820 4821 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4822 struct amdgpu_irq_src *source, 4823 struct amdgpu_iv_entry *entry) 4824 { 4825 u8 me_id, pipe_id; 4826 struct amdgpu_ring *ring; 4827 int i; 4828 4829 DRM_DEBUG("IH: CP EOP\n"); 4830 me_id = (entry->ring_id & 0x0c) >> 2; 4831 pipe_id = (entry->ring_id & 0x03) >> 0; 4832 switch (me_id) { 4833 case 0: 4834 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4835 break; 4836 case 1: 4837 case 2: 4838 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4839 ring = &adev->gfx.compute_ring[i]; 4840 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4841 amdgpu_fence_process(ring); 4842 } 4843 break; 4844 } 4845 return 0; 4846 } 4847 4848 static void gfx_v7_0_fault(struct amdgpu_device *adev, 4849 struct amdgpu_iv_entry *entry) 4850 { 4851 struct amdgpu_ring *ring; 4852 u8 me_id, pipe_id; 4853 int i; 4854 4855 me_id = (entry->ring_id & 0x0c) >> 2; 4856 pipe_id = (entry->ring_id & 0x03) >> 0; 4857 switch (me_id) { 4858 case 0: 4859 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4860 break; 4861 case 1: 4862 case 2: 4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4864 ring = &adev->gfx.compute_ring[i]; 4865 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4866 drm_sched_fault(&ring->sched); 4867 } 4868 break; 4869 } 4870 } 4871 4872 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 4873 struct amdgpu_irq_src *source, 4874 struct amdgpu_iv_entry *entry) 4875 { 4876 DRM_ERROR("Illegal register access in command stream\n"); 4877 gfx_v7_0_fault(adev, entry); 4878 return 0; 4879 } 4880 4881 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 4882 struct amdgpu_irq_src *source, 4883 struct amdgpu_iv_entry *entry) 4884 { 4885 DRM_ERROR("Illegal instruction in command stream\n"); 4886 // XXX soft reset the gfx block only 4887 gfx_v7_0_fault(adev, entry); 4888 return 0; 4889 } 4890 4891 static int gfx_v7_0_set_clockgating_state(void *handle, 4892 enum amd_clockgating_state state) 4893 { 4894 bool gate = false; 4895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4896 4897 if (state == AMD_CG_STATE_GATE) 4898 gate = true; 4899 4900 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 4901 /* order matters! */ 4902 if (gate) { 4903 gfx_v7_0_enable_mgcg(adev, true); 4904 gfx_v7_0_enable_cgcg(adev, true); 4905 } else { 4906 gfx_v7_0_enable_cgcg(adev, false); 4907 gfx_v7_0_enable_mgcg(adev, false); 4908 } 4909 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4910 4911 return 0; 4912 } 4913 4914 static int gfx_v7_0_set_powergating_state(void *handle, 4915 enum amd_powergating_state state) 4916 { 4917 bool gate = false; 4918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4919 4920 if (state == AMD_PG_STATE_GATE) 4921 gate = true; 4922 4923 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4924 AMD_PG_SUPPORT_GFX_SMG | 4925 AMD_PG_SUPPORT_GFX_DMG | 4926 AMD_PG_SUPPORT_CP | 4927 AMD_PG_SUPPORT_GDS | 4928 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4929 gfx_v7_0_update_gfx_pg(adev, gate); 4930 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4931 gfx_v7_0_enable_cp_pg(adev, gate); 4932 gfx_v7_0_enable_gds_pg(adev, gate); 4933 } 4934 } 4935 4936 return 0; 4937 } 4938 4939 static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring) 4940 { 4941 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 4942 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4943 PACKET3_TC_ACTION_ENA | 4944 PACKET3_SH_KCACHE_ACTION_ENA | 4945 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4946 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4947 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4948 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4949 } 4950 4951 static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring) 4952 { 4953 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 4954 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 4955 PACKET3_TC_ACTION_ENA | 4956 PACKET3_SH_KCACHE_ACTION_ENA | 4957 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */ 4958 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 4959 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ 4960 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 4961 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 4962 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ 4963 } 4964 4965 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 4966 .name = "gfx_v7_0", 4967 .early_init = gfx_v7_0_early_init, 4968 .late_init = gfx_v7_0_late_init, 4969 .sw_init = gfx_v7_0_sw_init, 4970 .sw_fini = gfx_v7_0_sw_fini, 4971 .hw_init = gfx_v7_0_hw_init, 4972 .hw_fini = gfx_v7_0_hw_fini, 4973 .suspend = gfx_v7_0_suspend, 4974 .resume = gfx_v7_0_resume, 4975 .is_idle = gfx_v7_0_is_idle, 4976 .wait_for_idle = gfx_v7_0_wait_for_idle, 4977 .soft_reset = gfx_v7_0_soft_reset, 4978 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 4979 .set_powergating_state = gfx_v7_0_set_powergating_state, 4980 }; 4981 4982 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 4983 .type = AMDGPU_RING_TYPE_GFX, 4984 .align_mask = 0xff, 4985 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4986 .support_64bit_ptrs = false, 4987 .get_rptr = gfx_v7_0_ring_get_rptr, 4988 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 4989 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 4990 .emit_frame_size = 4991 20 + /* gfx_v7_0_ring_emit_gds_switch */ 4992 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 4993 5 + /* hdp invalidate */ 4994 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 4995 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 4996 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 4997 3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 4998 5, /* SURFACE_SYNC */ 4999 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5000 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5001 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5002 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5003 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5004 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5005 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5006 .test_ring = gfx_v7_0_ring_test_ring, 5007 .test_ib = gfx_v7_0_ring_test_ib, 5008 .insert_nop = amdgpu_ring_insert_nop, 5009 .pad_ib = amdgpu_ring_generic_pad_ib, 5010 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5011 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5012 .soft_recovery = gfx_v7_0_ring_soft_recovery, 5013 .emit_mem_sync = gfx_v7_0_emit_mem_sync, 5014 }; 5015 5016 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5017 .type = AMDGPU_RING_TYPE_COMPUTE, 5018 .align_mask = 0xff, 5019 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5020 .support_64bit_ptrs = false, 5021 .get_rptr = gfx_v7_0_ring_get_rptr, 5022 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5023 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5024 .emit_frame_size = 5025 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5026 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5027 5 + /* hdp invalidate */ 5028 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5029 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ 5030 7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5031 7, /* gfx_v7_0_emit_mem_sync_compute */ 5032 .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */ 5033 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5034 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5035 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5036 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5037 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5038 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5039 .test_ring = gfx_v7_0_ring_test_ring, 5040 .test_ib = gfx_v7_0_ring_test_ib, 5041 .insert_nop = amdgpu_ring_insert_nop, 5042 .pad_ib = amdgpu_ring_generic_pad_ib, 5043 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5044 .emit_mem_sync = gfx_v7_0_emit_mem_sync_compute, 5045 }; 5046 5047 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5048 { 5049 int i; 5050 5051 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5052 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5054 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5055 } 5056 5057 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5058 .set = gfx_v7_0_set_eop_interrupt_state, 5059 .process = gfx_v7_0_eop_irq, 5060 }; 5061 5062 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5063 .set = gfx_v7_0_set_priv_reg_fault_state, 5064 .process = gfx_v7_0_priv_reg_irq, 5065 }; 5066 5067 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5068 .set = gfx_v7_0_set_priv_inst_fault_state, 5069 .process = gfx_v7_0_priv_inst_irq, 5070 }; 5071 5072 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5073 { 5074 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5075 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5076 5077 adev->gfx.priv_reg_irq.num_types = 1; 5078 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5079 5080 adev->gfx.priv_inst_irq.num_types = 1; 5081 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5082 } 5083 5084 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5085 { 5086 /* init asci gds info */ 5087 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 5088 adev->gds.gws_size = 64; 5089 adev->gds.oa_size = 16; 5090 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 5091 } 5092 5093 5094 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5095 { 5096 int i, j, k, counter, active_cu_number = 0; 5097 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5098 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5099 unsigned disable_masks[4 * 2]; 5100 u32 ao_cu_num; 5101 5102 if (adev->flags & AMD_IS_APU) 5103 ao_cu_num = 2; 5104 else 5105 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5106 5107 memset(cu_info, 0, sizeof(*cu_info)); 5108 5109 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5110 5111 mutex_lock(&adev->grbm_idx_mutex); 5112 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5113 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5114 mask = 1; 5115 ao_bitmap = 0; 5116 counter = 0; 5117 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5118 if (i < 4 && j < 2) 5119 gfx_v7_0_set_user_cu_inactive_bitmap( 5120 adev, disable_masks[i * 2 + j]); 5121 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5122 cu_info->bitmap[i][j] = bitmap; 5123 5124 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5125 if (bitmap & mask) { 5126 if (counter < ao_cu_num) 5127 ao_bitmap |= mask; 5128 counter ++; 5129 } 5130 mask <<= 1; 5131 } 5132 active_cu_number += counter; 5133 if (i < 2 && j < 2) 5134 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5135 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5136 } 5137 } 5138 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5139 mutex_unlock(&adev->grbm_idx_mutex); 5140 5141 cu_info->number = active_cu_number; 5142 cu_info->ao_cu_mask = ao_cu_mask; 5143 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5144 cu_info->max_waves_per_simd = 10; 5145 cu_info->max_scratch_slots_per_cu = 32; 5146 cu_info->wave_front_size = 64; 5147 cu_info->lds_size = 64; 5148 } 5149 5150 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5151 { 5152 .type = AMD_IP_BLOCK_TYPE_GFX, 5153 .major = 7, 5154 .minor = 1, 5155 .rev = 0, 5156 .funcs = &gfx_v7_0_ip_funcs, 5157 }; 5158 5159 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5160 { 5161 .type = AMD_IP_BLOCK_TYPE_GFX, 5162 .major = 7, 5163 .minor = 2, 5164 .rev = 0, 5165 .funcs = &gfx_v7_0_ip_funcs, 5166 }; 5167 5168 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5169 { 5170 .type = AMD_IP_BLOCK_TYPE_GFX, 5171 .major = 7, 5172 .minor = 3, 5173 .rev = 0, 5174 .funcs = &gfx_v7_0_ip_funcs, 5175 }; 5176