1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ih.h" 27 #include "amdgpu_gfx.h" 28 #include "cikd.h" 29 #include "cik.h" 30 #include "atom.h" 31 #include "amdgpu_ucode.h" 32 #include "clearstate_ci.h" 33 34 #include "dce/dce_8_0_d.h" 35 #include "dce/dce_8_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gca/gfx_7_0_d.h" 41 #include "gca/gfx_7_2_enum.h" 42 #include "gca/gfx_7_2_sh_mask.h" 43 44 #include "gmc/gmc_7_0_d.h" 45 #include "gmc/gmc_7_0_sh_mask.h" 46 47 #include "oss/oss_2_0_d.h" 48 #include "oss/oss_2_0_sh_mask.h" 49 50 #define GFX7_NUM_GFX_RINGS 1 51 #define GFX7_NUM_COMPUTE_RINGS 8 52 53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 56 int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *); 57 58 MODULE_FIRMWARE("radeon/bonaire_pfp.bin"); 59 MODULE_FIRMWARE("radeon/bonaire_me.bin"); 60 MODULE_FIRMWARE("radeon/bonaire_ce.bin"); 61 MODULE_FIRMWARE("radeon/bonaire_rlc.bin"); 62 MODULE_FIRMWARE("radeon/bonaire_mec.bin"); 63 64 MODULE_FIRMWARE("radeon/hawaii_pfp.bin"); 65 MODULE_FIRMWARE("radeon/hawaii_me.bin"); 66 MODULE_FIRMWARE("radeon/hawaii_ce.bin"); 67 MODULE_FIRMWARE("radeon/hawaii_rlc.bin"); 68 MODULE_FIRMWARE("radeon/hawaii_mec.bin"); 69 70 MODULE_FIRMWARE("radeon/kaveri_pfp.bin"); 71 MODULE_FIRMWARE("radeon/kaveri_me.bin"); 72 MODULE_FIRMWARE("radeon/kaveri_ce.bin"); 73 MODULE_FIRMWARE("radeon/kaveri_rlc.bin"); 74 MODULE_FIRMWARE("radeon/kaveri_mec.bin"); 75 MODULE_FIRMWARE("radeon/kaveri_mec2.bin"); 76 77 MODULE_FIRMWARE("radeon/kabini_pfp.bin"); 78 MODULE_FIRMWARE("radeon/kabini_me.bin"); 79 MODULE_FIRMWARE("radeon/kabini_ce.bin"); 80 MODULE_FIRMWARE("radeon/kabini_rlc.bin"); 81 MODULE_FIRMWARE("radeon/kabini_mec.bin"); 82 83 MODULE_FIRMWARE("radeon/mullins_pfp.bin"); 84 MODULE_FIRMWARE("radeon/mullins_me.bin"); 85 MODULE_FIRMWARE("radeon/mullins_ce.bin"); 86 MODULE_FIRMWARE("radeon/mullins_rlc.bin"); 87 MODULE_FIRMWARE("radeon/mullins_mec.bin"); 88 89 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 90 { 91 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 92 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 93 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 94 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 95 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 96 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 97 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 98 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 99 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 100 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 101 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 102 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 103 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 104 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 105 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 106 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 107 }; 108 109 static const u32 spectre_rlc_save_restore_register_list[] = 110 { 111 (0x0e00 << 16) | (0xc12c >> 2), 112 0x00000000, 113 (0x0e00 << 16) | (0xc140 >> 2), 114 0x00000000, 115 (0x0e00 << 16) | (0xc150 >> 2), 116 0x00000000, 117 (0x0e00 << 16) | (0xc15c >> 2), 118 0x00000000, 119 (0x0e00 << 16) | (0xc168 >> 2), 120 0x00000000, 121 (0x0e00 << 16) | (0xc170 >> 2), 122 0x00000000, 123 (0x0e00 << 16) | (0xc178 >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc204 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc2b4 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc2b8 >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc2bc >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc2c0 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0x8228 >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0x829c >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0x869c >> 2), 140 0x00000000, 141 (0x0600 << 16) | (0x98f4 >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0x98f8 >> 2), 144 0x00000000, 145 (0x0e00 << 16) | (0x9900 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0xc260 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x90e8 >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0x3c000 >> 2), 152 0x00000000, 153 (0x0e00 << 16) | (0x3c00c >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x8c1c >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x9700 >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0xcd20 >> 2), 160 0x00000000, 161 (0x4e00 << 16) | (0xcd20 >> 2), 162 0x00000000, 163 (0x5e00 << 16) | (0xcd20 >> 2), 164 0x00000000, 165 (0x6e00 << 16) | (0xcd20 >> 2), 166 0x00000000, 167 (0x7e00 << 16) | (0xcd20 >> 2), 168 0x00000000, 169 (0x8e00 << 16) | (0xcd20 >> 2), 170 0x00000000, 171 (0x9e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0xae00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0xbe00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0x0e00 << 16) | (0x89bc >> 2), 178 0x00000000, 179 (0x0e00 << 16) | (0x8900 >> 2), 180 0x00000000, 181 0x3, 182 (0x0e00 << 16) | (0xc130 >> 2), 183 0x00000000, 184 (0x0e00 << 16) | (0xc134 >> 2), 185 0x00000000, 186 (0x0e00 << 16) | (0xc1fc >> 2), 187 0x00000000, 188 (0x0e00 << 16) | (0xc208 >> 2), 189 0x00000000, 190 (0x0e00 << 16) | (0xc264 >> 2), 191 0x00000000, 192 (0x0e00 << 16) | (0xc268 >> 2), 193 0x00000000, 194 (0x0e00 << 16) | (0xc26c >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc270 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc274 >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc278 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc27c >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc280 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc284 >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc288 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc28c >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc290 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc294 >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc298 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc29c >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc2a0 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc2a4 >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc2a8 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc2ac >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc2b0 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0x301d0 >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0x30238 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0x30250 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0x30254 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0x30258 >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0x3025c >> 2), 241 0x00000000, 242 (0x4e00 << 16) | (0xc900 >> 2), 243 0x00000000, 244 (0x5e00 << 16) | (0xc900 >> 2), 245 0x00000000, 246 (0x6e00 << 16) | (0xc900 >> 2), 247 0x00000000, 248 (0x7e00 << 16) | (0xc900 >> 2), 249 0x00000000, 250 (0x8e00 << 16) | (0xc900 >> 2), 251 0x00000000, 252 (0x9e00 << 16) | (0xc900 >> 2), 253 0x00000000, 254 (0xae00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0xbe00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0x4e00 << 16) | (0xc904 >> 2), 259 0x00000000, 260 (0x5e00 << 16) | (0xc904 >> 2), 261 0x00000000, 262 (0x6e00 << 16) | (0xc904 >> 2), 263 0x00000000, 264 (0x7e00 << 16) | (0xc904 >> 2), 265 0x00000000, 266 (0x8e00 << 16) | (0xc904 >> 2), 267 0x00000000, 268 (0x9e00 << 16) | (0xc904 >> 2), 269 0x00000000, 270 (0xae00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0xbe00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0x4e00 << 16) | (0xc908 >> 2), 275 0x00000000, 276 (0x5e00 << 16) | (0xc908 >> 2), 277 0x00000000, 278 (0x6e00 << 16) | (0xc908 >> 2), 279 0x00000000, 280 (0x7e00 << 16) | (0xc908 >> 2), 281 0x00000000, 282 (0x8e00 << 16) | (0xc908 >> 2), 283 0x00000000, 284 (0x9e00 << 16) | (0xc908 >> 2), 285 0x00000000, 286 (0xae00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0xbe00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0x4e00 << 16) | (0xc90c >> 2), 291 0x00000000, 292 (0x5e00 << 16) | (0xc90c >> 2), 293 0x00000000, 294 (0x6e00 << 16) | (0xc90c >> 2), 295 0x00000000, 296 (0x7e00 << 16) | (0xc90c >> 2), 297 0x00000000, 298 (0x8e00 << 16) | (0xc90c >> 2), 299 0x00000000, 300 (0x9e00 << 16) | (0xc90c >> 2), 301 0x00000000, 302 (0xae00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0xbe00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0x4e00 << 16) | (0xc910 >> 2), 307 0x00000000, 308 (0x5e00 << 16) | (0xc910 >> 2), 309 0x00000000, 310 (0x6e00 << 16) | (0xc910 >> 2), 311 0x00000000, 312 (0x7e00 << 16) | (0xc910 >> 2), 313 0x00000000, 314 (0x8e00 << 16) | (0xc910 >> 2), 315 0x00000000, 316 (0x9e00 << 16) | (0xc910 >> 2), 317 0x00000000, 318 (0xae00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0xbe00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0x0e00 << 16) | (0xc99c >> 2), 323 0x00000000, 324 (0x0e00 << 16) | (0x9834 >> 2), 325 0x00000000, 326 (0x0000 << 16) | (0x30f00 >> 2), 327 0x00000000, 328 (0x0001 << 16) | (0x30f00 >> 2), 329 0x00000000, 330 (0x0000 << 16) | (0x30f04 >> 2), 331 0x00000000, 332 (0x0001 << 16) | (0x30f04 >> 2), 333 0x00000000, 334 (0x0000 << 16) | (0x30f08 >> 2), 335 0x00000000, 336 (0x0001 << 16) | (0x30f08 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f0c >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f0c >> 2), 341 0x00000000, 342 (0x0600 << 16) | (0x9b7c >> 2), 343 0x00000000, 344 (0x0e00 << 16) | (0x8a14 >> 2), 345 0x00000000, 346 (0x0e00 << 16) | (0x8a18 >> 2), 347 0x00000000, 348 (0x0600 << 16) | (0x30a00 >> 2), 349 0x00000000, 350 (0x0e00 << 16) | (0x8bf0 >> 2), 351 0x00000000, 352 (0x0e00 << 16) | (0x8bcc >> 2), 353 0x00000000, 354 (0x0e00 << 16) | (0x8b24 >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x30a04 >> 2), 357 0x00000000, 358 (0x0600 << 16) | (0x30a10 >> 2), 359 0x00000000, 360 (0x0600 << 16) | (0x30a14 >> 2), 361 0x00000000, 362 (0x0600 << 16) | (0x30a18 >> 2), 363 0x00000000, 364 (0x0600 << 16) | (0x30a2c >> 2), 365 0x00000000, 366 (0x0e00 << 16) | (0xc700 >> 2), 367 0x00000000, 368 (0x0e00 << 16) | (0xc704 >> 2), 369 0x00000000, 370 (0x0e00 << 16) | (0xc708 >> 2), 371 0x00000000, 372 (0x0e00 << 16) | (0xc768 >> 2), 373 0x00000000, 374 (0x0400 << 16) | (0xc770 >> 2), 375 0x00000000, 376 (0x0400 << 16) | (0xc774 >> 2), 377 0x00000000, 378 (0x0400 << 16) | (0xc778 >> 2), 379 0x00000000, 380 (0x0400 << 16) | (0xc77c >> 2), 381 0x00000000, 382 (0x0400 << 16) | (0xc780 >> 2), 383 0x00000000, 384 (0x0400 << 16) | (0xc784 >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc788 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc78c >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc798 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc79c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc7a0 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc7a4 >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc7a8 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc7ac >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc7b0 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc7b4 >> 2), 405 0x00000000, 406 (0x0e00 << 16) | (0x9100 >> 2), 407 0x00000000, 408 (0x0e00 << 16) | (0x3c010 >> 2), 409 0x00000000, 410 (0x0e00 << 16) | (0x92a8 >> 2), 411 0x00000000, 412 (0x0e00 << 16) | (0x92ac >> 2), 413 0x00000000, 414 (0x0e00 << 16) | (0x92b4 >> 2), 415 0x00000000, 416 (0x0e00 << 16) | (0x92b8 >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x92bc >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x92c0 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92c4 >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92c8 >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92cc >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92d0 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x8c00 >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x8c04 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x8c20 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x8c38 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x8c3c >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0xae00 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x9604 >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0xac08 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0xac0c >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0xac10 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0xac14 >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xac58 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0xac68 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac6c >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac70 >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac74 >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac78 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac7c >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac80 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac84 >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac88 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac8c >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0x970c >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0x9714 >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0x9718 >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0x971c >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0x31068 >> 2), 483 0x00000000, 484 (0x4e00 << 16) | (0x31068 >> 2), 485 0x00000000, 486 (0x5e00 << 16) | (0x31068 >> 2), 487 0x00000000, 488 (0x6e00 << 16) | (0x31068 >> 2), 489 0x00000000, 490 (0x7e00 << 16) | (0x31068 >> 2), 491 0x00000000, 492 (0x8e00 << 16) | (0x31068 >> 2), 493 0x00000000, 494 (0x9e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0xae00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0xbe00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0x0e00 << 16) | (0xcd10 >> 2), 501 0x00000000, 502 (0x0e00 << 16) | (0xcd14 >> 2), 503 0x00000000, 504 (0x0e00 << 16) | (0x88b0 >> 2), 505 0x00000000, 506 (0x0e00 << 16) | (0x88b4 >> 2), 507 0x00000000, 508 (0x0e00 << 16) | (0x88b8 >> 2), 509 0x00000000, 510 (0x0e00 << 16) | (0x88bc >> 2), 511 0x00000000, 512 (0x0400 << 16) | (0x89c0 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0x88c4 >> 2), 515 0x00000000, 516 (0x0e00 << 16) | (0x88c8 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88d0 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88d4 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88d8 >> 2), 523 0x00000000, 524 (0x0e00 << 16) | (0x8980 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x30938 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x3093c >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x30940 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x89a0 >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x30900 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x30904 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x89b4 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x3c210 >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x3c214 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x3c218 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x8904 >> 2), 547 0x00000000, 548 0x5, 549 (0x0e00 << 16) | (0x8c28 >> 2), 550 (0x0e00 << 16) | (0x8c2c >> 2), 551 (0x0e00 << 16) | (0x8c30 >> 2), 552 (0x0e00 << 16) | (0x8c34 >> 2), 553 (0x0e00 << 16) | (0x9600 >> 2), 554 }; 555 556 static const u32 kalindi_rlc_save_restore_register_list[] = 557 { 558 (0x0e00 << 16) | (0xc12c >> 2), 559 0x00000000, 560 (0x0e00 << 16) | (0xc140 >> 2), 561 0x00000000, 562 (0x0e00 << 16) | (0xc150 >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc15c >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc168 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc170 >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc204 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc2b4 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc2b8 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2bc >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2c0 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0x8228 >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0x829c >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x869c >> 2), 585 0x00000000, 586 (0x0600 << 16) | (0x98f4 >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x98f8 >> 2), 589 0x00000000, 590 (0x0e00 << 16) | (0x9900 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0xc260 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x90e8 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0x3c000 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x3c00c >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x8c1c >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x9700 >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0xcd20 >> 2), 605 0x00000000, 606 (0x4e00 << 16) | (0xcd20 >> 2), 607 0x00000000, 608 (0x5e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x6e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x7e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x0e00 << 16) | (0x89bc >> 2), 615 0x00000000, 616 (0x0e00 << 16) | (0x8900 >> 2), 617 0x00000000, 618 0x3, 619 (0x0e00 << 16) | (0xc130 >> 2), 620 0x00000000, 621 (0x0e00 << 16) | (0xc134 >> 2), 622 0x00000000, 623 (0x0e00 << 16) | (0xc1fc >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc208 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc264 >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc268 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc26c >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc270 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc274 >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc28c >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc290 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc294 >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc298 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc2a0 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc2a4 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a8 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2ac >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0x301d0 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0x30238 >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x30250 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30254 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30258 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x3025c >> 2), 664 0x00000000, 665 (0x4e00 << 16) | (0xc900 >> 2), 666 0x00000000, 667 (0x5e00 << 16) | (0xc900 >> 2), 668 0x00000000, 669 (0x6e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x7e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x4e00 << 16) | (0xc904 >> 2), 674 0x00000000, 675 (0x5e00 << 16) | (0xc904 >> 2), 676 0x00000000, 677 (0x6e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x7e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x4e00 << 16) | (0xc908 >> 2), 682 0x00000000, 683 (0x5e00 << 16) | (0xc908 >> 2), 684 0x00000000, 685 (0x6e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x7e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x4e00 << 16) | (0xc90c >> 2), 690 0x00000000, 691 (0x5e00 << 16) | (0xc90c >> 2), 692 0x00000000, 693 (0x6e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x7e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x4e00 << 16) | (0xc910 >> 2), 698 0x00000000, 699 (0x5e00 << 16) | (0xc910 >> 2), 700 0x00000000, 701 (0x6e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x7e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x0e00 << 16) | (0xc99c >> 2), 706 0x00000000, 707 (0x0e00 << 16) | (0x9834 >> 2), 708 0x00000000, 709 (0x0000 << 16) | (0x30f00 >> 2), 710 0x00000000, 711 (0x0000 << 16) | (0x30f04 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f08 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f0c >> 2), 716 0x00000000, 717 (0x0600 << 16) | (0x9b7c >> 2), 718 0x00000000, 719 (0x0e00 << 16) | (0x8a14 >> 2), 720 0x00000000, 721 (0x0e00 << 16) | (0x8a18 >> 2), 722 0x00000000, 723 (0x0600 << 16) | (0x30a00 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8bf0 >> 2), 726 0x00000000, 727 (0x0e00 << 16) | (0x8bcc >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8b24 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x30a04 >> 2), 732 0x00000000, 733 (0x0600 << 16) | (0x30a10 >> 2), 734 0x00000000, 735 (0x0600 << 16) | (0x30a14 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a18 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a2c >> 2), 740 0x00000000, 741 (0x0e00 << 16) | (0xc700 >> 2), 742 0x00000000, 743 (0x0e00 << 16) | (0xc704 >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc708 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc768 >> 2), 748 0x00000000, 749 (0x0400 << 16) | (0xc770 >> 2), 750 0x00000000, 751 (0x0400 << 16) | (0xc774 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc798 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc79c >> 2), 756 0x00000000, 757 (0x0e00 << 16) | (0x9100 >> 2), 758 0x00000000, 759 (0x0e00 << 16) | (0x3c010 >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x8c00 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x8c04 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c20 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c38 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c3c >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0xae00 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x9604 >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xac08 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0xac0c >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac10 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac14 >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac58 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac68 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac6c >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac70 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac74 >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac78 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac7c >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac80 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac84 >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac88 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac8c >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0x970c >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0x9714 >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x9718 >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x971c >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x31068 >> 2), 814 0x00000000, 815 (0x4e00 << 16) | (0x31068 >> 2), 816 0x00000000, 817 (0x5e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x6e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x7e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x0e00 << 16) | (0xcd10 >> 2), 824 0x00000000, 825 (0x0e00 << 16) | (0xcd14 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0x88b0 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0x88b4 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b8 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88bc >> 2), 834 0x00000000, 835 (0x0400 << 16) | (0x89c0 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88c4 >> 2), 838 0x00000000, 839 (0x0e00 << 16) | (0x88c8 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88d0 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88d4 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d8 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x8980 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x30938 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x3093c >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30940 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x89a0 >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30900 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x30904 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x89b4 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x3e1fc >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x3c210 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3c214 >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c218 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x8904 >> 2), 872 0x00000000, 873 0x5, 874 (0x0e00 << 16) | (0x8c28 >> 2), 875 (0x0e00 << 16) | (0x8c2c >> 2), 876 (0x0e00 << 16) | (0x8c30 >> 2), 877 (0x0e00 << 16) | (0x8c34 >> 2), 878 (0x0e00 << 16) | (0x9600 >> 2), 879 }; 880 881 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 883 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev); 884 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 885 886 /* 887 * Core functions 888 */ 889 /** 890 * gfx_v7_0_init_microcode - load ucode images from disk 891 * 892 * @adev: amdgpu_device pointer 893 * 894 * Use the firmware interface to load the ucode images into 895 * the driver (not loaded into hw). 896 * Returns 0 on success, error on failure. 897 */ 898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 899 { 900 const char *chip_name; 901 char fw_name[30]; 902 int err; 903 904 DRM_DEBUG("\n"); 905 906 switch (adev->asic_type) { 907 case CHIP_BONAIRE: 908 chip_name = "bonaire"; 909 break; 910 case CHIP_HAWAII: 911 chip_name = "hawaii"; 912 break; 913 case CHIP_KAVERI: 914 chip_name = "kaveri"; 915 break; 916 case CHIP_KABINI: 917 chip_name = "kabini"; 918 break; 919 case CHIP_MULLINS: 920 chip_name = "mullins"; 921 break; 922 default: BUG(); 923 } 924 925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 927 if (err) 928 goto out; 929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 930 if (err) 931 goto out; 932 933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 935 if (err) 936 goto out; 937 err = amdgpu_ucode_validate(adev->gfx.me_fw); 938 if (err) 939 goto out; 940 941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 943 if (err) 944 goto out; 945 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 946 if (err) 947 goto out; 948 949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name); 950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 951 if (err) 952 goto out; 953 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 954 if (err) 955 goto out; 956 957 if (adev->asic_type == CHIP_KAVERI) { 958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name); 959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 960 if (err) 961 goto out; 962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 963 if (err) 964 goto out; 965 } 966 967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 969 if (err) 970 goto out; 971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 972 973 out: 974 if (err) { 975 printk(KERN_ERR 976 "gfx7: Failed to load firmware \"%s\"\n", 977 fw_name); 978 release_firmware(adev->gfx.pfp_fw); 979 adev->gfx.pfp_fw = NULL; 980 release_firmware(adev->gfx.me_fw); 981 adev->gfx.me_fw = NULL; 982 release_firmware(adev->gfx.ce_fw); 983 adev->gfx.ce_fw = NULL; 984 release_firmware(adev->gfx.mec_fw); 985 adev->gfx.mec_fw = NULL; 986 release_firmware(adev->gfx.mec2_fw); 987 adev->gfx.mec2_fw = NULL; 988 release_firmware(adev->gfx.rlc_fw); 989 adev->gfx.rlc_fw = NULL; 990 } 991 return err; 992 } 993 994 /** 995 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 996 * 997 * @adev: amdgpu_device pointer 998 * 999 * Starting with SI, the tiling setup is done globally in a 1000 * set of 32 tiling modes. Rather than selecting each set of 1001 * parameters per surface as on older asics, we just select 1002 * which index in the tiling table we want to use, and the 1003 * surface uses those parameters (CIK). 1004 */ 1005 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1006 { 1007 const u32 num_tile_mode_states = 1008 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1009 const u32 num_secondary_tile_mode_states = 1010 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1011 u32 reg_offset, split_equal_to_row_size; 1012 uint32_t *tile, *macrotile; 1013 1014 tile = adev->gfx.config.tile_mode_array; 1015 macrotile = adev->gfx.config.macrotile_mode_array; 1016 1017 switch (adev->gfx.config.mem_row_size_in_kb) { 1018 case 1: 1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1020 break; 1021 case 2: 1022 default: 1023 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1024 break; 1025 case 4: 1026 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1027 break; 1028 } 1029 1030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1031 tile[reg_offset] = 0; 1032 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1033 macrotile[reg_offset] = 0; 1034 1035 switch (adev->asic_type) { 1036 case CHIP_BONAIRE: 1037 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1041 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1045 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1049 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1053 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1056 TILE_SPLIT(split_equal_to_row_size)); 1057 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1060 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1063 TILE_SPLIT(split_equal_to_row_size)); 1064 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1065 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1066 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1067 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1070 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1074 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1078 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1079 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1082 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1086 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1090 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1094 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1095 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1099 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1102 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1106 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1110 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1114 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1115 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1119 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1123 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1127 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1129 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1130 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1132 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1134 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1136 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1138 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1139 1140 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1143 NUM_BANKS(ADDR_SURF_16_BANK)); 1144 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1147 NUM_BANKS(ADDR_SURF_16_BANK)); 1148 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1151 NUM_BANKS(ADDR_SURF_16_BANK)); 1152 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1155 NUM_BANKS(ADDR_SURF_16_BANK)); 1156 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1159 NUM_BANKS(ADDR_SURF_16_BANK)); 1160 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1163 NUM_BANKS(ADDR_SURF_8_BANK)); 1164 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1167 NUM_BANKS(ADDR_SURF_4_BANK)); 1168 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1171 NUM_BANKS(ADDR_SURF_16_BANK)); 1172 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1175 NUM_BANKS(ADDR_SURF_16_BANK)); 1176 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1179 NUM_BANKS(ADDR_SURF_16_BANK)); 1180 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1183 NUM_BANKS(ADDR_SURF_16_BANK)); 1184 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1187 NUM_BANKS(ADDR_SURF_16_BANK)); 1188 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1191 NUM_BANKS(ADDR_SURF_8_BANK)); 1192 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1195 NUM_BANKS(ADDR_SURF_4_BANK)); 1196 1197 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1198 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1199 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1200 if (reg_offset != 7) 1201 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1202 break; 1203 case CHIP_HAWAII: 1204 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1208 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1212 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1216 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1220 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1223 TILE_SPLIT(split_equal_to_row_size)); 1224 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1227 TILE_SPLIT(split_equal_to_row_size)); 1228 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1231 TILE_SPLIT(split_equal_to_row_size)); 1232 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1233 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1235 TILE_SPLIT(split_equal_to_row_size)); 1236 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1238 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1241 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1245 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1249 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1253 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1256 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1260 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1264 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1268 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1269 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1272 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1276 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1279 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1283 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1287 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1291 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1295 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1299 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1303 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1307 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1308 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1310 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1314 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1318 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1319 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1322 1323 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1326 NUM_BANKS(ADDR_SURF_16_BANK)); 1327 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1330 NUM_BANKS(ADDR_SURF_16_BANK)); 1331 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1334 NUM_BANKS(ADDR_SURF_16_BANK)); 1335 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1338 NUM_BANKS(ADDR_SURF_16_BANK)); 1339 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1342 NUM_BANKS(ADDR_SURF_8_BANK)); 1343 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1346 NUM_BANKS(ADDR_SURF_4_BANK)); 1347 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1350 NUM_BANKS(ADDR_SURF_4_BANK)); 1351 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1354 NUM_BANKS(ADDR_SURF_16_BANK)); 1355 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1358 NUM_BANKS(ADDR_SURF_16_BANK)); 1359 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1362 NUM_BANKS(ADDR_SURF_16_BANK)); 1363 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1366 NUM_BANKS(ADDR_SURF_8_BANK)); 1367 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1370 NUM_BANKS(ADDR_SURF_16_BANK)); 1371 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1374 NUM_BANKS(ADDR_SURF_8_BANK)); 1375 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1378 NUM_BANKS(ADDR_SURF_4_BANK)); 1379 1380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1381 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1382 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1383 if (reg_offset != 7) 1384 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1385 break; 1386 case CHIP_KABINI: 1387 case CHIP_KAVERI: 1388 case CHIP_MULLINS: 1389 default: 1390 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1391 PIPE_CONFIG(ADDR_SURF_P2) | 1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1394 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1395 PIPE_CONFIG(ADDR_SURF_P2) | 1396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1398 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1399 PIPE_CONFIG(ADDR_SURF_P2) | 1400 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1402 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1403 PIPE_CONFIG(ADDR_SURF_P2) | 1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1406 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1407 PIPE_CONFIG(ADDR_SURF_P2) | 1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1409 TILE_SPLIT(split_equal_to_row_size)); 1410 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1411 PIPE_CONFIG(ADDR_SURF_P2) | 1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1413 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1414 PIPE_CONFIG(ADDR_SURF_P2) | 1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1416 TILE_SPLIT(split_equal_to_row_size)); 1417 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1418 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1419 PIPE_CONFIG(ADDR_SURF_P2)); 1420 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1421 PIPE_CONFIG(ADDR_SURF_P2) | 1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1423 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1424 PIPE_CONFIG(ADDR_SURF_P2) | 1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1427 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1428 PIPE_CONFIG(ADDR_SURF_P2) | 1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1431 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1432 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1433 PIPE_CONFIG(ADDR_SURF_P2) | 1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1435 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1436 PIPE_CONFIG(ADDR_SURF_P2) | 1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1439 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1440 PIPE_CONFIG(ADDR_SURF_P2) | 1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1443 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1444 PIPE_CONFIG(ADDR_SURF_P2) | 1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1447 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1448 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1449 PIPE_CONFIG(ADDR_SURF_P2) | 1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1452 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1453 PIPE_CONFIG(ADDR_SURF_P2) | 1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1455 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1456 PIPE_CONFIG(ADDR_SURF_P2) | 1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1459 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1460 PIPE_CONFIG(ADDR_SURF_P2) | 1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1463 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1464 PIPE_CONFIG(ADDR_SURF_P2) | 1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1467 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1468 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1469 PIPE_CONFIG(ADDR_SURF_P2) | 1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1472 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1473 PIPE_CONFIG(ADDR_SURF_P2) | 1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1476 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1477 PIPE_CONFIG(ADDR_SURF_P2) | 1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1480 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1481 PIPE_CONFIG(ADDR_SURF_P2) | 1482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1483 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1484 PIPE_CONFIG(ADDR_SURF_P2) | 1485 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1487 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1488 PIPE_CONFIG(ADDR_SURF_P2) | 1489 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1491 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1492 1493 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1496 NUM_BANKS(ADDR_SURF_8_BANK)); 1497 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1500 NUM_BANKS(ADDR_SURF_8_BANK)); 1501 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1504 NUM_BANKS(ADDR_SURF_8_BANK)); 1505 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1508 NUM_BANKS(ADDR_SURF_8_BANK)); 1509 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1512 NUM_BANKS(ADDR_SURF_8_BANK)); 1513 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1516 NUM_BANKS(ADDR_SURF_8_BANK)); 1517 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1520 NUM_BANKS(ADDR_SURF_8_BANK)); 1521 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1524 NUM_BANKS(ADDR_SURF_16_BANK)); 1525 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1528 NUM_BANKS(ADDR_SURF_16_BANK)); 1529 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1532 NUM_BANKS(ADDR_SURF_16_BANK)); 1533 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1536 NUM_BANKS(ADDR_SURF_16_BANK)); 1537 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1540 NUM_BANKS(ADDR_SURF_16_BANK)); 1541 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1544 NUM_BANKS(ADDR_SURF_16_BANK)); 1545 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1548 NUM_BANKS(ADDR_SURF_8_BANK)); 1549 1550 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1551 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1552 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1553 if (reg_offset != 7) 1554 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1555 break; 1556 } 1557 } 1558 1559 /** 1560 * gfx_v7_0_select_se_sh - select which SE, SH to address 1561 * 1562 * @adev: amdgpu_device pointer 1563 * @se_num: shader engine to address 1564 * @sh_num: sh block to address 1565 * 1566 * Select which SE, SH combinations to address. Certain 1567 * registers are instanced per SE or SH. 0xffffffff means 1568 * broadcast to all SEs or SHs (CIK). 1569 */ 1570 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num) 1571 { 1572 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK; 1573 1574 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1576 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1577 else if (se_num == 0xffffffff) 1578 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1579 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1580 else if (sh_num == 0xffffffff) 1581 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1582 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1583 else 1584 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1585 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1586 WREG32(mmGRBM_GFX_INDEX, data); 1587 } 1588 1589 /** 1590 * gfx_v7_0_create_bitmask - create a bitmask 1591 * 1592 * @bit_width: length of the mask 1593 * 1594 * create a variable length bit mask (CIK). 1595 * Returns the bitmask. 1596 */ 1597 static u32 gfx_v7_0_create_bitmask(u32 bit_width) 1598 { 1599 return (u32)((1ULL << bit_width) - 1); 1600 } 1601 1602 /** 1603 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1604 * 1605 * @adev: amdgpu_device pointer 1606 * 1607 * Calculates the bitmask of enabled RBs (CIK). 1608 * Returns the enabled RB bitmask. 1609 */ 1610 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1611 { 1612 u32 data, mask; 1613 1614 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1615 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1616 1617 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1618 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1619 1620 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se / 1621 adev->gfx.config.max_sh_per_se); 1622 1623 return (~data) & mask; 1624 } 1625 1626 /** 1627 * gfx_v7_0_setup_rb - setup the RBs on the asic 1628 * 1629 * @adev: amdgpu_device pointer 1630 * @se_num: number of SEs (shader engines) for the asic 1631 * @sh_per_se: number of SH blocks per SE for the asic 1632 * 1633 * Configures per-SE/SH RB registers (CIK). 1634 */ 1635 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1636 { 1637 int i, j; 1638 u32 data; 1639 u32 active_rbs = 0; 1640 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1641 adev->gfx.config.max_sh_per_se; 1642 1643 mutex_lock(&adev->grbm_idx_mutex); 1644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1646 gfx_v7_0_select_se_sh(adev, i, j); 1647 data = gfx_v7_0_get_rb_active_bitmap(adev); 1648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1649 rb_bitmap_width_per_sh); 1650 } 1651 } 1652 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1653 mutex_unlock(&adev->grbm_idx_mutex); 1654 1655 adev->gfx.config.backend_enable_mask = active_rbs; 1656 adev->gfx.config.num_rbs = hweight32(active_rbs); 1657 } 1658 1659 /** 1660 * gmc_v7_0_init_compute_vmid - gart enable 1661 * 1662 * @rdev: amdgpu_device pointer 1663 * 1664 * Initialize compute vmid sh_mem registers 1665 * 1666 */ 1667 #define DEFAULT_SH_MEM_BASES (0x6000) 1668 #define FIRST_COMPUTE_VMID (8) 1669 #define LAST_COMPUTE_VMID (16) 1670 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1671 { 1672 int i; 1673 uint32_t sh_mem_config; 1674 uint32_t sh_mem_bases; 1675 1676 /* 1677 * Configure apertures: 1678 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1679 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1680 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1681 */ 1682 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1683 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1684 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1685 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1686 mutex_lock(&adev->srbm_mutex); 1687 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1688 cik_srbm_select(adev, 0, 0, 0, i); 1689 /* CP and shaders */ 1690 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1691 WREG32(mmSH_MEM_APE1_BASE, 1); 1692 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1693 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1694 } 1695 cik_srbm_select(adev, 0, 0, 0, 0); 1696 mutex_unlock(&adev->srbm_mutex); 1697 } 1698 1699 /** 1700 * gfx_v7_0_gpu_init - setup the 3D engine 1701 * 1702 * @adev: amdgpu_device pointer 1703 * 1704 * Configures the 3D engine and tiling configuration 1705 * registers so that the 3D engine is usable. 1706 */ 1707 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 1708 { 1709 u32 tmp, sh_mem_cfg; 1710 int i; 1711 1712 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1713 1714 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1715 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1716 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1717 1718 gfx_v7_0_tiling_mode_table_init(adev); 1719 1720 gfx_v7_0_setup_rb(adev); 1721 1722 /* set HW defaults for 3D engine */ 1723 WREG32(mmCP_MEQ_THRESHOLDS, 1724 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1725 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1726 1727 mutex_lock(&adev->grbm_idx_mutex); 1728 /* 1729 * making sure that the following register writes will be broadcasted 1730 * to all the shaders 1731 */ 1732 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1733 1734 /* XXX SH_MEM regs */ 1735 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1736 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1737 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1738 1739 mutex_lock(&adev->srbm_mutex); 1740 for (i = 0; i < 16; i++) { 1741 cik_srbm_select(adev, 0, 0, 0, i); 1742 /* CP and shaders */ 1743 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1744 WREG32(mmSH_MEM_APE1_BASE, 1); 1745 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1746 WREG32(mmSH_MEM_BASES, 0); 1747 } 1748 cik_srbm_select(adev, 0, 0, 0, 0); 1749 mutex_unlock(&adev->srbm_mutex); 1750 1751 gmc_v7_0_init_compute_vmid(adev); 1752 1753 WREG32(mmSX_DEBUG_1, 0x20); 1754 1755 WREG32(mmTA_CNTL_AUX, 0x00010000); 1756 1757 tmp = RREG32(mmSPI_CONFIG_CNTL); 1758 tmp |= 0x03000000; 1759 WREG32(mmSPI_CONFIG_CNTL, tmp); 1760 1761 WREG32(mmSQ_CONFIG, 1); 1762 1763 WREG32(mmDB_DEBUG, 0); 1764 1765 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1766 tmp |= 0x00000400; 1767 WREG32(mmDB_DEBUG2, tmp); 1768 1769 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1770 tmp |= 0x00020200; 1771 WREG32(mmDB_DEBUG3, tmp); 1772 1773 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 1774 tmp |= 0x00018208; 1775 WREG32(mmCB_HW_CONTROL, tmp); 1776 1777 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1778 1779 WREG32(mmPA_SC_FIFO_SIZE, 1780 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1781 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1782 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1783 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1784 1785 WREG32(mmVGT_NUM_INSTANCES, 1); 1786 1787 WREG32(mmCP_PERFMON_CNTL, 0); 1788 1789 WREG32(mmSQ_CONFIG, 0); 1790 1791 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 1792 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1793 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1794 1795 WREG32(mmVGT_CACHE_INVALIDATION, 1796 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1797 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1798 1799 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1800 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1801 1802 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1803 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1804 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 1805 mutex_unlock(&adev->grbm_idx_mutex); 1806 1807 udelay(50); 1808 } 1809 1810 /* 1811 * GPU scratch registers helpers function. 1812 */ 1813 /** 1814 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 1815 * 1816 * @adev: amdgpu_device pointer 1817 * 1818 * Set up the number and offset of the CP scratch registers. 1819 * NOTE: use of CP scratch registers is a legacy inferface and 1820 * is not used by default on newer asics (r6xx+). On newer asics, 1821 * memory buffers are used for fences rather than scratch regs. 1822 */ 1823 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 1824 { 1825 int i; 1826 1827 adev->gfx.scratch.num_reg = 7; 1828 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1829 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { 1830 adev->gfx.scratch.free[i] = true; 1831 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; 1832 } 1833 } 1834 1835 /** 1836 * gfx_v7_0_ring_test_ring - basic gfx ring test 1837 * 1838 * @adev: amdgpu_device pointer 1839 * @ring: amdgpu_ring structure holding ring information 1840 * 1841 * Allocate a scratch register and write to it using the gfx ring (CIK). 1842 * Provides a basic gfx ring test to verify that the ring is working. 1843 * Used by gfx_v7_0_cp_gfx_resume(); 1844 * Returns 0 on success, error on failure. 1845 */ 1846 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1847 { 1848 struct amdgpu_device *adev = ring->adev; 1849 uint32_t scratch; 1850 uint32_t tmp = 0; 1851 unsigned i; 1852 int r; 1853 1854 r = amdgpu_gfx_scratch_get(adev, &scratch); 1855 if (r) { 1856 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 1857 return r; 1858 } 1859 WREG32(scratch, 0xCAFEDEAD); 1860 r = amdgpu_ring_alloc(ring, 3); 1861 if (r) { 1862 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 1863 amdgpu_gfx_scratch_free(adev, scratch); 1864 return r; 1865 } 1866 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1867 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 1868 amdgpu_ring_write(ring, 0xDEADBEEF); 1869 amdgpu_ring_commit(ring); 1870 1871 for (i = 0; i < adev->usec_timeout; i++) { 1872 tmp = RREG32(scratch); 1873 if (tmp == 0xDEADBEEF) 1874 break; 1875 DRM_UDELAY(1); 1876 } 1877 if (i < adev->usec_timeout) { 1878 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1879 } else { 1880 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1881 ring->idx, scratch, tmp); 1882 r = -EINVAL; 1883 } 1884 amdgpu_gfx_scratch_free(adev, scratch); 1885 return r; 1886 } 1887 1888 /** 1889 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 1890 * 1891 * @adev: amdgpu_device pointer 1892 * @ridx: amdgpu ring index 1893 * 1894 * Emits an hdp flush on the cp. 1895 */ 1896 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1897 { 1898 u32 ref_and_mask; 1899 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 1900 1901 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { 1902 switch (ring->me) { 1903 case 1: 1904 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 1905 break; 1906 case 2: 1907 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 1908 break; 1909 default: 1910 return; 1911 } 1912 } else { 1913 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 1914 } 1915 1916 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1917 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 1918 WAIT_REG_MEM_FUNCTION(3) | /* == */ 1919 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 1920 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 1921 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 1922 amdgpu_ring_write(ring, ref_and_mask); 1923 amdgpu_ring_write(ring, ref_and_mask); 1924 amdgpu_ring_write(ring, 0x20); /* poll interval */ 1925 } 1926 1927 /** 1928 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1929 * 1930 * @adev: amdgpu_device pointer 1931 * @ridx: amdgpu ring index 1932 * 1933 * Emits an hdp invalidate on the cp. 1934 */ 1935 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 1936 { 1937 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1938 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 1939 WRITE_DATA_DST_SEL(0) | 1940 WR_CONFIRM)); 1941 amdgpu_ring_write(ring, mmHDP_DEBUG0); 1942 amdgpu_ring_write(ring, 0); 1943 amdgpu_ring_write(ring, 1); 1944 } 1945 1946 /** 1947 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 1948 * 1949 * @adev: amdgpu_device pointer 1950 * @fence: amdgpu fence object 1951 * 1952 * Emits a fence sequnce number on the gfx ring and flushes 1953 * GPU caches. 1954 */ 1955 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 1956 u64 seq, unsigned flags) 1957 { 1958 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1959 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1960 /* Workaround for cache flush problems. First send a dummy EOP 1961 * event down the pipe with seq one below. 1962 */ 1963 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1964 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 1965 EOP_TC_ACTION_EN | 1966 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 1967 EVENT_INDEX(5))); 1968 amdgpu_ring_write(ring, addr & 0xfffffffc); 1969 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1970 DATA_SEL(1) | INT_SEL(0)); 1971 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 1972 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 1973 1974 /* Then send the real EOP event down the pipe. */ 1975 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1976 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 1977 EOP_TC_ACTION_EN | 1978 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 1979 EVENT_INDEX(5))); 1980 amdgpu_ring_write(ring, addr & 0xfffffffc); 1981 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1982 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 1983 amdgpu_ring_write(ring, lower_32_bits(seq)); 1984 amdgpu_ring_write(ring, upper_32_bits(seq)); 1985 } 1986 1987 /** 1988 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 1989 * 1990 * @adev: amdgpu_device pointer 1991 * @fence: amdgpu fence object 1992 * 1993 * Emits a fence sequnce number on the compute ring and flushes 1994 * GPU caches. 1995 */ 1996 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 1997 u64 addr, u64 seq, 1998 unsigned flags) 1999 { 2000 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2001 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2002 2003 /* RELEASE_MEM - flush caches, send int */ 2004 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2005 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2006 EOP_TC_ACTION_EN | 2007 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2008 EVENT_INDEX(5))); 2009 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2010 amdgpu_ring_write(ring, addr & 0xfffffffc); 2011 amdgpu_ring_write(ring, upper_32_bits(addr)); 2012 amdgpu_ring_write(ring, lower_32_bits(seq)); 2013 amdgpu_ring_write(ring, upper_32_bits(seq)); 2014 } 2015 2016 /* 2017 * IB stuff 2018 */ 2019 /** 2020 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2021 * 2022 * @ring: amdgpu_ring structure holding ring information 2023 * @ib: amdgpu indirect buffer object 2024 * 2025 * Emits an DE (drawing engine) or CE (constant engine) IB 2026 * on the gfx ring. IBs are usually generated by userspace 2027 * acceleration drivers and submitted to the kernel for 2028 * sheduling on the ring. This function schedules the IB 2029 * on the gfx ring for execution by the GPU. 2030 */ 2031 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2032 struct amdgpu_ib *ib) 2033 { 2034 bool need_ctx_switch = ring->current_ctx != ib->ctx; 2035 u32 header, control = 0; 2036 u32 next_rptr = ring->wptr + 5; 2037 2038 /* drop the CE preamble IB for the same context */ 2039 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch) 2040 return; 2041 2042 if (need_ctx_switch) 2043 next_rptr += 2; 2044 2045 next_rptr += 4; 2046 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2047 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 2048 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 2049 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 2050 amdgpu_ring_write(ring, next_rptr); 2051 2052 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2053 if (need_ctx_switch) { 2054 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2055 amdgpu_ring_write(ring, 0); 2056 } 2057 2058 if (ib->flags & AMDGPU_IB_FLAG_CE) 2059 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2060 else 2061 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2062 2063 control |= ib->length_dw | (ib->vm_id << 24); 2064 2065 amdgpu_ring_write(ring, header); 2066 amdgpu_ring_write(ring, 2067 #ifdef __BIG_ENDIAN 2068 (2 << 0) | 2069 #endif 2070 (ib->gpu_addr & 0xFFFFFFFC)); 2071 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2072 amdgpu_ring_write(ring, control); 2073 } 2074 2075 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2076 struct amdgpu_ib *ib) 2077 { 2078 u32 header, control = 0; 2079 u32 next_rptr = ring->wptr + 5; 2080 2081 control |= INDIRECT_BUFFER_VALID; 2082 next_rptr += 4; 2083 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2084 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); 2085 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 2086 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 2087 amdgpu_ring_write(ring, next_rptr); 2088 2089 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2090 2091 control |= ib->length_dw | (ib->vm_id << 24); 2092 2093 amdgpu_ring_write(ring, header); 2094 amdgpu_ring_write(ring, 2095 #ifdef __BIG_ENDIAN 2096 (2 << 0) | 2097 #endif 2098 (ib->gpu_addr & 0xFFFFFFFC)); 2099 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2100 amdgpu_ring_write(ring, control); 2101 } 2102 2103 /** 2104 * gfx_v7_0_ring_test_ib - basic ring IB test 2105 * 2106 * @ring: amdgpu_ring structure holding ring information 2107 * 2108 * Allocate an IB and execute it on the gfx ring (CIK). 2109 * Provides a basic gfx ring test to verify that IBs are working. 2110 * Returns 0 on success, error on failure. 2111 */ 2112 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring) 2113 { 2114 struct amdgpu_device *adev = ring->adev; 2115 struct amdgpu_ib ib; 2116 struct fence *f = NULL; 2117 uint32_t scratch; 2118 uint32_t tmp = 0; 2119 unsigned i; 2120 int r; 2121 2122 r = amdgpu_gfx_scratch_get(adev, &scratch); 2123 if (r) { 2124 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r); 2125 return r; 2126 } 2127 WREG32(scratch, 0xCAFEDEAD); 2128 memset(&ib, 0, sizeof(ib)); 2129 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2130 if (r) { 2131 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 2132 goto err1; 2133 } 2134 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2135 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2136 ib.ptr[2] = 0xDEADBEEF; 2137 ib.length_dw = 3; 2138 2139 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2140 if (r) 2141 goto err2; 2142 2143 r = fence_wait(f, false); 2144 if (r) { 2145 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 2146 goto err2; 2147 } 2148 for (i = 0; i < adev->usec_timeout; i++) { 2149 tmp = RREG32(scratch); 2150 if (tmp == 0xDEADBEEF) 2151 break; 2152 DRM_UDELAY(1); 2153 } 2154 if (i < adev->usec_timeout) { 2155 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 2156 ring->idx, i); 2157 goto err2; 2158 } else { 2159 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 2160 scratch, tmp); 2161 r = -EINVAL; 2162 } 2163 2164 err2: 2165 fence_put(f); 2166 amdgpu_ib_free(adev, &ib, NULL); 2167 fence_put(f); 2168 err1: 2169 amdgpu_gfx_scratch_free(adev, scratch); 2170 return r; 2171 } 2172 2173 /* 2174 * CP. 2175 * On CIK, gfx and compute now have independant command processors. 2176 * 2177 * GFX 2178 * Gfx consists of a single ring and can process both gfx jobs and 2179 * compute jobs. The gfx CP consists of three microengines (ME): 2180 * PFP - Pre-Fetch Parser 2181 * ME - Micro Engine 2182 * CE - Constant Engine 2183 * The PFP and ME make up what is considered the Drawing Engine (DE). 2184 * The CE is an asynchronous engine used for updating buffer desciptors 2185 * used by the DE so that they can be loaded into cache in parallel 2186 * while the DE is processing state update packets. 2187 * 2188 * Compute 2189 * The compute CP consists of two microengines (ME): 2190 * MEC1 - Compute MicroEngine 1 2191 * MEC2 - Compute MicroEngine 2 2192 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2193 * The queues are exposed to userspace and are programmed directly 2194 * by the compute runtime. 2195 */ 2196 /** 2197 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2198 * 2199 * @adev: amdgpu_device pointer 2200 * @enable: enable or disable the MEs 2201 * 2202 * Halts or unhalts the gfx MEs. 2203 */ 2204 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2205 { 2206 int i; 2207 2208 if (enable) { 2209 WREG32(mmCP_ME_CNTL, 0); 2210 } else { 2211 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2212 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2213 adev->gfx.gfx_ring[i].ready = false; 2214 } 2215 udelay(50); 2216 } 2217 2218 /** 2219 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2220 * 2221 * @adev: amdgpu_device pointer 2222 * 2223 * Loads the gfx PFP, ME, and CE ucode. 2224 * Returns 0 for success, -EINVAL if the ucode is not available. 2225 */ 2226 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2227 { 2228 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2229 const struct gfx_firmware_header_v1_0 *ce_hdr; 2230 const struct gfx_firmware_header_v1_0 *me_hdr; 2231 const __le32 *fw_data; 2232 unsigned i, fw_size; 2233 2234 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2235 return -EINVAL; 2236 2237 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2238 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2239 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2240 2241 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2242 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2243 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2244 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2245 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2246 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2247 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2248 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2249 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2250 2251 gfx_v7_0_cp_gfx_enable(adev, false); 2252 2253 /* PFP */ 2254 fw_data = (const __le32 *) 2255 (adev->gfx.pfp_fw->data + 2256 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2257 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2258 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2259 for (i = 0; i < fw_size; i++) 2260 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2261 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2262 2263 /* CE */ 2264 fw_data = (const __le32 *) 2265 (adev->gfx.ce_fw->data + 2266 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2267 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2268 WREG32(mmCP_CE_UCODE_ADDR, 0); 2269 for (i = 0; i < fw_size; i++) 2270 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2271 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2272 2273 /* ME */ 2274 fw_data = (const __le32 *) 2275 (adev->gfx.me_fw->data + 2276 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2277 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2278 WREG32(mmCP_ME_RAM_WADDR, 0); 2279 for (i = 0; i < fw_size; i++) 2280 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2281 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2282 2283 return 0; 2284 } 2285 2286 /** 2287 * gfx_v7_0_cp_gfx_start - start the gfx ring 2288 * 2289 * @adev: amdgpu_device pointer 2290 * 2291 * Enables the ring and loads the clear state context and other 2292 * packets required to init the ring. 2293 * Returns 0 for success, error for failure. 2294 */ 2295 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2296 { 2297 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2298 const struct cs_section_def *sect = NULL; 2299 const struct cs_extent_def *ext = NULL; 2300 int r, i; 2301 2302 /* init the CP */ 2303 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2304 WREG32(mmCP_ENDIAN_SWAP, 0); 2305 WREG32(mmCP_DEVICE_ID, 1); 2306 2307 gfx_v7_0_cp_gfx_enable(adev, true); 2308 2309 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2310 if (r) { 2311 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2312 return r; 2313 } 2314 2315 /* init the CE partitions. CE only used for gfx on CIK */ 2316 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2317 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2318 amdgpu_ring_write(ring, 0x8000); 2319 amdgpu_ring_write(ring, 0x8000); 2320 2321 /* clear state buffer */ 2322 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2323 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2324 2325 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2326 amdgpu_ring_write(ring, 0x80000000); 2327 amdgpu_ring_write(ring, 0x80000000); 2328 2329 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2330 for (ext = sect->section; ext->extent != NULL; ++ext) { 2331 if (sect->id == SECT_CONTEXT) { 2332 amdgpu_ring_write(ring, 2333 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2334 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2335 for (i = 0; i < ext->reg_count; i++) 2336 amdgpu_ring_write(ring, ext->extent[i]); 2337 } 2338 } 2339 } 2340 2341 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2342 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2343 switch (adev->asic_type) { 2344 case CHIP_BONAIRE: 2345 amdgpu_ring_write(ring, 0x16000012); 2346 amdgpu_ring_write(ring, 0x00000000); 2347 break; 2348 case CHIP_KAVERI: 2349 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2350 amdgpu_ring_write(ring, 0x00000000); 2351 break; 2352 case CHIP_KABINI: 2353 case CHIP_MULLINS: 2354 amdgpu_ring_write(ring, 0x00000000); /* XXX */ 2355 amdgpu_ring_write(ring, 0x00000000); 2356 break; 2357 case CHIP_HAWAII: 2358 amdgpu_ring_write(ring, 0x3a00161a); 2359 amdgpu_ring_write(ring, 0x0000002e); 2360 break; 2361 default: 2362 amdgpu_ring_write(ring, 0x00000000); 2363 amdgpu_ring_write(ring, 0x00000000); 2364 break; 2365 } 2366 2367 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2368 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2369 2370 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2371 amdgpu_ring_write(ring, 0); 2372 2373 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2374 amdgpu_ring_write(ring, 0x00000316); 2375 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2376 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2377 2378 amdgpu_ring_commit(ring); 2379 2380 return 0; 2381 } 2382 2383 /** 2384 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2385 * 2386 * @adev: amdgpu_device pointer 2387 * 2388 * Program the location and size of the gfx ring buffer 2389 * and test it to make sure it's working. 2390 * Returns 0 for success, error for failure. 2391 */ 2392 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2393 { 2394 struct amdgpu_ring *ring; 2395 u32 tmp; 2396 u32 rb_bufsz; 2397 u64 rb_addr, rptr_addr; 2398 int r; 2399 2400 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2401 if (adev->asic_type != CHIP_HAWAII) 2402 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2403 2404 /* Set the write pointer delay */ 2405 WREG32(mmCP_RB_WPTR_DELAY, 0); 2406 2407 /* set the RB to use vmid 0 */ 2408 WREG32(mmCP_RB_VMID, 0); 2409 2410 WREG32(mmSCRATCH_ADDR, 0); 2411 2412 /* ring 0 - compute and gfx */ 2413 /* Set ring buffer size */ 2414 ring = &adev->gfx.gfx_ring[0]; 2415 rb_bufsz = order_base_2(ring->ring_size / 8); 2416 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2417 #ifdef __BIG_ENDIAN 2418 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2419 #endif 2420 WREG32(mmCP_RB0_CNTL, tmp); 2421 2422 /* Initialize the ring buffer's read and write pointers */ 2423 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2424 ring->wptr = 0; 2425 WREG32(mmCP_RB0_WPTR, ring->wptr); 2426 2427 /* set the wb address wether it's enabled or not */ 2428 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2429 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2430 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2431 2432 /* scratch register shadowing is no longer supported */ 2433 WREG32(mmSCRATCH_UMSK, 0); 2434 2435 mdelay(1); 2436 WREG32(mmCP_RB0_CNTL, tmp); 2437 2438 rb_addr = ring->gpu_addr >> 8; 2439 WREG32(mmCP_RB0_BASE, rb_addr); 2440 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2441 2442 /* start the ring */ 2443 gfx_v7_0_cp_gfx_start(adev); 2444 ring->ready = true; 2445 r = amdgpu_ring_test_ring(ring); 2446 if (r) { 2447 ring->ready = false; 2448 return r; 2449 } 2450 2451 return 0; 2452 } 2453 2454 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 2455 { 2456 return ring->adev->wb.wb[ring->rptr_offs]; 2457 } 2458 2459 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2460 { 2461 struct amdgpu_device *adev = ring->adev; 2462 2463 return RREG32(mmCP_RB0_WPTR); 2464 } 2465 2466 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2467 { 2468 struct amdgpu_device *adev = ring->adev; 2469 2470 WREG32(mmCP_RB0_WPTR, ring->wptr); 2471 (void)RREG32(mmCP_RB0_WPTR); 2472 } 2473 2474 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 2475 { 2476 return ring->adev->wb.wb[ring->rptr_offs]; 2477 } 2478 2479 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2480 { 2481 /* XXX check if swapping is necessary on BE */ 2482 return ring->adev->wb.wb[ring->wptr_offs]; 2483 } 2484 2485 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2486 { 2487 struct amdgpu_device *adev = ring->adev; 2488 2489 /* XXX check if swapping is necessary on BE */ 2490 adev->wb.wb[ring->wptr_offs] = ring->wptr; 2491 WDOORBELL32(ring->doorbell_index, ring->wptr); 2492 } 2493 2494 /** 2495 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2496 * 2497 * @adev: amdgpu_device pointer 2498 * @enable: enable or disable the MEs 2499 * 2500 * Halts or unhalts the compute MEs. 2501 */ 2502 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2503 { 2504 int i; 2505 2506 if (enable) { 2507 WREG32(mmCP_MEC_CNTL, 0); 2508 } else { 2509 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2510 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2511 adev->gfx.compute_ring[i].ready = false; 2512 } 2513 udelay(50); 2514 } 2515 2516 /** 2517 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2518 * 2519 * @adev: amdgpu_device pointer 2520 * 2521 * Loads the compute MEC1&2 ucode. 2522 * Returns 0 for success, -EINVAL if the ucode is not available. 2523 */ 2524 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2525 { 2526 const struct gfx_firmware_header_v1_0 *mec_hdr; 2527 const __le32 *fw_data; 2528 unsigned i, fw_size; 2529 2530 if (!adev->gfx.mec_fw) 2531 return -EINVAL; 2532 2533 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2534 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2535 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2536 adev->gfx.mec_feature_version = le32_to_cpu( 2537 mec_hdr->ucode_feature_version); 2538 2539 gfx_v7_0_cp_compute_enable(adev, false); 2540 2541 /* MEC1 */ 2542 fw_data = (const __le32 *) 2543 (adev->gfx.mec_fw->data + 2544 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2545 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2546 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2547 for (i = 0; i < fw_size; i++) 2548 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2549 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2550 2551 if (adev->asic_type == CHIP_KAVERI) { 2552 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2553 2554 if (!adev->gfx.mec2_fw) 2555 return -EINVAL; 2556 2557 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2558 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2559 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2560 adev->gfx.mec2_feature_version = le32_to_cpu( 2561 mec2_hdr->ucode_feature_version); 2562 2563 /* MEC2 */ 2564 fw_data = (const __le32 *) 2565 (adev->gfx.mec2_fw->data + 2566 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2567 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2568 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2569 for (i = 0; i < fw_size; i++) 2570 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2571 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2572 } 2573 2574 return 0; 2575 } 2576 2577 /** 2578 * gfx_v7_0_cp_compute_fini - stop the compute queues 2579 * 2580 * @adev: amdgpu_device pointer 2581 * 2582 * Stop the compute queues and tear down the driver queue 2583 * info. 2584 */ 2585 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2586 { 2587 int i, r; 2588 2589 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2590 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2591 2592 if (ring->mqd_obj) { 2593 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2594 if (unlikely(r != 0)) 2595 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r); 2596 2597 amdgpu_bo_unpin(ring->mqd_obj); 2598 amdgpu_bo_unreserve(ring->mqd_obj); 2599 2600 amdgpu_bo_unref(&ring->mqd_obj); 2601 ring->mqd_obj = NULL; 2602 } 2603 } 2604 } 2605 2606 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2607 { 2608 int r; 2609 2610 if (adev->gfx.mec.hpd_eop_obj) { 2611 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2612 if (unlikely(r != 0)) 2613 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); 2614 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); 2615 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2616 2617 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); 2618 adev->gfx.mec.hpd_eop_obj = NULL; 2619 } 2620 } 2621 2622 #define MEC_HPD_SIZE 2048 2623 2624 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2625 { 2626 int r; 2627 u32 *hpd; 2628 2629 /* 2630 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total 2631 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total 2632 * Nonetheless, we assign only 1 pipe because all other pipes will 2633 * be handled by KFD 2634 */ 2635 adev->gfx.mec.num_mec = 1; 2636 adev->gfx.mec.num_pipe = 1; 2637 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; 2638 2639 if (adev->gfx.mec.hpd_eop_obj == NULL) { 2640 r = amdgpu_bo_create(adev, 2641 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 2642 PAGE_SIZE, true, 2643 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2644 &adev->gfx.mec.hpd_eop_obj); 2645 if (r) { 2646 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 2647 return r; 2648 } 2649 } 2650 2651 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); 2652 if (unlikely(r != 0)) { 2653 gfx_v7_0_mec_fini(adev); 2654 return r; 2655 } 2656 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, 2657 &adev->gfx.mec.hpd_eop_gpu_addr); 2658 if (r) { 2659 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r); 2660 gfx_v7_0_mec_fini(adev); 2661 return r; 2662 } 2663 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); 2664 if (r) { 2665 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r); 2666 gfx_v7_0_mec_fini(adev); 2667 return r; 2668 } 2669 2670 /* clear memory. Not sure if this is required or not */ 2671 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 2672 2673 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2674 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2675 2676 return 0; 2677 } 2678 2679 struct hqd_registers 2680 { 2681 u32 cp_mqd_base_addr; 2682 u32 cp_mqd_base_addr_hi; 2683 u32 cp_hqd_active; 2684 u32 cp_hqd_vmid; 2685 u32 cp_hqd_persistent_state; 2686 u32 cp_hqd_pipe_priority; 2687 u32 cp_hqd_queue_priority; 2688 u32 cp_hqd_quantum; 2689 u32 cp_hqd_pq_base; 2690 u32 cp_hqd_pq_base_hi; 2691 u32 cp_hqd_pq_rptr; 2692 u32 cp_hqd_pq_rptr_report_addr; 2693 u32 cp_hqd_pq_rptr_report_addr_hi; 2694 u32 cp_hqd_pq_wptr_poll_addr; 2695 u32 cp_hqd_pq_wptr_poll_addr_hi; 2696 u32 cp_hqd_pq_doorbell_control; 2697 u32 cp_hqd_pq_wptr; 2698 u32 cp_hqd_pq_control; 2699 u32 cp_hqd_ib_base_addr; 2700 u32 cp_hqd_ib_base_addr_hi; 2701 u32 cp_hqd_ib_rptr; 2702 u32 cp_hqd_ib_control; 2703 u32 cp_hqd_iq_timer; 2704 u32 cp_hqd_iq_rptr; 2705 u32 cp_hqd_dequeue_request; 2706 u32 cp_hqd_dma_offload; 2707 u32 cp_hqd_sema_cmd; 2708 u32 cp_hqd_msg_type; 2709 u32 cp_hqd_atomic0_preop_lo; 2710 u32 cp_hqd_atomic0_preop_hi; 2711 u32 cp_hqd_atomic1_preop_lo; 2712 u32 cp_hqd_atomic1_preop_hi; 2713 u32 cp_hqd_hq_scheduler0; 2714 u32 cp_hqd_hq_scheduler1; 2715 u32 cp_mqd_control; 2716 }; 2717 2718 struct bonaire_mqd 2719 { 2720 u32 header; 2721 u32 dispatch_initiator; 2722 u32 dimensions[3]; 2723 u32 start_idx[3]; 2724 u32 num_threads[3]; 2725 u32 pipeline_stat_enable; 2726 u32 perf_counter_enable; 2727 u32 pgm[2]; 2728 u32 tba[2]; 2729 u32 tma[2]; 2730 u32 pgm_rsrc[2]; 2731 u32 vmid; 2732 u32 resource_limits; 2733 u32 static_thread_mgmt01[2]; 2734 u32 tmp_ring_size; 2735 u32 static_thread_mgmt23[2]; 2736 u32 restart[3]; 2737 u32 thread_trace_enable; 2738 u32 reserved1; 2739 u32 user_data[16]; 2740 u32 vgtcs_invoke_count[2]; 2741 struct hqd_registers queue_state; 2742 u32 dequeue_cntr; 2743 u32 interrupt_queue[64]; 2744 }; 2745 2746 /** 2747 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 2748 * 2749 * @adev: amdgpu_device pointer 2750 * 2751 * Program the compute queues and test them to make sure they 2752 * are working. 2753 * Returns 0 for success, error for failure. 2754 */ 2755 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 2756 { 2757 int r, i, j; 2758 u32 tmp; 2759 bool use_doorbell = true; 2760 u64 hqd_gpu_addr; 2761 u64 mqd_gpu_addr; 2762 u64 eop_gpu_addr; 2763 u64 wb_gpu_addr; 2764 u32 *buf; 2765 struct bonaire_mqd *mqd; 2766 2767 gfx_v7_0_cp_compute_enable(adev, true); 2768 2769 /* fix up chicken bits */ 2770 tmp = RREG32(mmCP_CPF_DEBUG); 2771 tmp |= (1 << 23); 2772 WREG32(mmCP_CPF_DEBUG, tmp); 2773 2774 /* init the pipes */ 2775 mutex_lock(&adev->srbm_mutex); 2776 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 2777 int me = (i < 4) ? 1 : 2; 2778 int pipe = (i < 4) ? i : (i - 4); 2779 2780 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); 2781 2782 cik_srbm_select(adev, me, pipe, 0, 0); 2783 2784 /* write the EOP addr */ 2785 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2786 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2787 2788 /* set the VMID assigned */ 2789 WREG32(mmCP_HPD_EOP_VMID, 0); 2790 2791 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2792 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2793 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2794 tmp |= order_base_2(MEC_HPD_SIZE / 8); 2795 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2796 } 2797 cik_srbm_select(adev, 0, 0, 0, 0); 2798 mutex_unlock(&adev->srbm_mutex); 2799 2800 /* init the queues. Just two for now. */ 2801 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2802 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2803 2804 if (ring->mqd_obj == NULL) { 2805 r = amdgpu_bo_create(adev, 2806 sizeof(struct bonaire_mqd), 2807 PAGE_SIZE, true, 2808 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 2809 &ring->mqd_obj); 2810 if (r) { 2811 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 2812 return r; 2813 } 2814 } 2815 2816 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2817 if (unlikely(r != 0)) { 2818 gfx_v7_0_cp_compute_fini(adev); 2819 return r; 2820 } 2821 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT, 2822 &mqd_gpu_addr); 2823 if (r) { 2824 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r); 2825 gfx_v7_0_cp_compute_fini(adev); 2826 return r; 2827 } 2828 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf); 2829 if (r) { 2830 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r); 2831 gfx_v7_0_cp_compute_fini(adev); 2832 return r; 2833 } 2834 2835 /* init the mqd struct */ 2836 memset(buf, 0, sizeof(struct bonaire_mqd)); 2837 2838 mqd = (struct bonaire_mqd *)buf; 2839 mqd->header = 0xC0310800; 2840 mqd->static_thread_mgmt01[0] = 0xffffffff; 2841 mqd->static_thread_mgmt01[1] = 0xffffffff; 2842 mqd->static_thread_mgmt23[0] = 0xffffffff; 2843 mqd->static_thread_mgmt23[1] = 0xffffffff; 2844 2845 mutex_lock(&adev->srbm_mutex); 2846 cik_srbm_select(adev, ring->me, 2847 ring->pipe, 2848 ring->queue, 0); 2849 2850 /* disable wptr polling */ 2851 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 2852 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK; 2853 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 2854 2855 /* enable doorbell? */ 2856 mqd->queue_state.cp_hqd_pq_doorbell_control = 2857 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2858 if (use_doorbell) 2859 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2860 else 2861 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2862 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 2863 mqd->queue_state.cp_hqd_pq_doorbell_control); 2864 2865 /* disable the queue if it's active */ 2866 mqd->queue_state.cp_hqd_dequeue_request = 0; 2867 mqd->queue_state.cp_hqd_pq_rptr = 0; 2868 mqd->queue_state.cp_hqd_pq_wptr= 0; 2869 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2870 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2871 for (j = 0; j < adev->usec_timeout; j++) { 2872 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2873 break; 2874 udelay(1); 2875 } 2876 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); 2877 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); 2878 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 2879 } 2880 2881 /* set the pointer to the MQD */ 2882 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc; 2883 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2884 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); 2885 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); 2886 /* set MQD vmid to 0 */ 2887 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2888 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2889 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); 2890 2891 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2892 hqd_gpu_addr = ring->gpu_addr >> 8; 2893 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr; 2894 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2895 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); 2896 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); 2897 2898 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2899 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2900 mqd->queue_state.cp_hqd_pq_control &= 2901 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2902 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2903 2904 mqd->queue_state.cp_hqd_pq_control |= 2905 order_base_2(ring->ring_size / 8); 2906 mqd->queue_state.cp_hqd_pq_control |= 2907 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2908 #ifdef __BIG_ENDIAN 2909 mqd->queue_state.cp_hqd_pq_control |= 2910 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2911 #endif 2912 mqd->queue_state.cp_hqd_pq_control &= 2913 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2914 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2915 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2916 mqd->queue_state.cp_hqd_pq_control |= 2917 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2918 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2919 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); 2920 2921 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2922 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2923 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 2924 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2925 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); 2926 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2927 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); 2928 2929 /* set the wb address wether it's enabled or not */ 2930 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2931 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc; 2932 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi = 2933 upper_32_bits(wb_gpu_addr) & 0xffff; 2934 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2935 mqd->queue_state.cp_hqd_pq_rptr_report_addr); 2936 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2937 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi); 2938 2939 /* enable the doorbell if requested */ 2940 if (use_doorbell) { 2941 mqd->queue_state.cp_hqd_pq_doorbell_control = 2942 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2943 mqd->queue_state.cp_hqd_pq_doorbell_control &= 2944 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2945 mqd->queue_state.cp_hqd_pq_doorbell_control |= 2946 (ring->doorbell_index << 2947 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2948 mqd->queue_state.cp_hqd_pq_doorbell_control |= 2949 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2950 mqd->queue_state.cp_hqd_pq_doorbell_control &= 2951 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 2952 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 2953 2954 } else { 2955 mqd->queue_state.cp_hqd_pq_doorbell_control = 0; 2956 } 2957 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 2958 mqd->queue_state.cp_hqd_pq_doorbell_control); 2959 2960 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2961 ring->wptr = 0; 2962 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr; 2963 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); 2964 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 2965 2966 /* set the vmid for the queue */ 2967 mqd->queue_state.cp_hqd_vmid = 0; 2968 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); 2969 2970 /* activate the queue */ 2971 mqd->queue_state.cp_hqd_active = 1; 2972 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 2973 2974 cik_srbm_select(adev, 0, 0, 0, 0); 2975 mutex_unlock(&adev->srbm_mutex); 2976 2977 amdgpu_bo_kunmap(ring->mqd_obj); 2978 amdgpu_bo_unreserve(ring->mqd_obj); 2979 2980 ring->ready = true; 2981 r = amdgpu_ring_test_ring(ring); 2982 if (r) 2983 ring->ready = false; 2984 } 2985 2986 return 0; 2987 } 2988 2989 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 2990 { 2991 gfx_v7_0_cp_gfx_enable(adev, enable); 2992 gfx_v7_0_cp_compute_enable(adev, enable); 2993 } 2994 2995 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 2996 { 2997 int r; 2998 2999 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3000 if (r) 3001 return r; 3002 r = gfx_v7_0_cp_compute_load_microcode(adev); 3003 if (r) 3004 return r; 3005 3006 return 0; 3007 } 3008 3009 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3010 bool enable) 3011 { 3012 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3013 3014 if (enable) 3015 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3016 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3017 else 3018 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3019 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3020 WREG32(mmCP_INT_CNTL_RING0, tmp); 3021 } 3022 3023 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3024 { 3025 int r; 3026 3027 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3028 3029 r = gfx_v7_0_cp_load_microcode(adev); 3030 if (r) 3031 return r; 3032 3033 r = gfx_v7_0_cp_gfx_resume(adev); 3034 if (r) 3035 return r; 3036 r = gfx_v7_0_cp_compute_resume(adev); 3037 if (r) 3038 return r; 3039 3040 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3041 3042 return 0; 3043 } 3044 3045 /** 3046 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3047 * 3048 * @ring: the ring to emmit the commands to 3049 * 3050 * Sync the command pipeline with the PFP. E.g. wait for everything 3051 * to be completed. 3052 */ 3053 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3054 { 3055 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 3056 if (usepfp) { 3057 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3058 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3059 amdgpu_ring_write(ring, 0); 3060 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3061 amdgpu_ring_write(ring, 0); 3062 } 3063 } 3064 3065 /* 3066 * vm 3067 * VMID 0 is the physical GPU addresses as used by the kernel. 3068 * VMIDs 1-15 are used for userspace clients and are handled 3069 * by the amdgpu vm/hsa code. 3070 */ 3071 /** 3072 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3073 * 3074 * @adev: amdgpu_device pointer 3075 * 3076 * Update the page table base and flush the VM TLB 3077 * using the CP (CIK). 3078 */ 3079 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3080 unsigned vm_id, uint64_t pd_addr) 3081 { 3082 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); 3083 uint32_t seq = ring->fence_drv.sync_seq; 3084 uint64_t addr = ring->fence_drv.gpu_addr; 3085 3086 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3087 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3088 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3089 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3090 amdgpu_ring_write(ring, addr & 0xfffffffc); 3091 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3092 amdgpu_ring_write(ring, seq); 3093 amdgpu_ring_write(ring, 0xffffffff); 3094 amdgpu_ring_write(ring, 4); /* poll interval */ 3095 3096 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3097 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3098 WRITE_DATA_DST_SEL(0))); 3099 if (vm_id < 8) { 3100 amdgpu_ring_write(ring, 3101 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 3102 } else { 3103 amdgpu_ring_write(ring, 3104 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 3105 } 3106 amdgpu_ring_write(ring, 0); 3107 amdgpu_ring_write(ring, pd_addr >> 12); 3108 3109 /* bits 0-15 are the VM contexts0-15 */ 3110 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3111 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3112 WRITE_DATA_DST_SEL(0))); 3113 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3114 amdgpu_ring_write(ring, 0); 3115 amdgpu_ring_write(ring, 1 << vm_id); 3116 3117 /* wait for the invalidate to complete */ 3118 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3119 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3120 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3121 WAIT_REG_MEM_ENGINE(0))); /* me */ 3122 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3123 amdgpu_ring_write(ring, 0); 3124 amdgpu_ring_write(ring, 0); /* ref */ 3125 amdgpu_ring_write(ring, 0); /* mask */ 3126 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3127 3128 /* compute doesn't have PFP */ 3129 if (usepfp) { 3130 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3131 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3132 amdgpu_ring_write(ring, 0x0); 3133 3134 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3135 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3136 amdgpu_ring_write(ring, 0); 3137 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3138 amdgpu_ring_write(ring, 0); 3139 } 3140 } 3141 3142 /* 3143 * RLC 3144 * The RLC is a multi-purpose microengine that handles a 3145 * variety of functions. 3146 */ 3147 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev) 3148 { 3149 int r; 3150 3151 /* save restore block */ 3152 if (adev->gfx.rlc.save_restore_obj) { 3153 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3154 if (unlikely(r != 0)) 3155 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); 3156 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); 3157 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3158 3159 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); 3160 adev->gfx.rlc.save_restore_obj = NULL; 3161 } 3162 3163 /* clear state block */ 3164 if (adev->gfx.rlc.clear_state_obj) { 3165 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3166 if (unlikely(r != 0)) 3167 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); 3168 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 3169 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3170 3171 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 3172 adev->gfx.rlc.clear_state_obj = NULL; 3173 } 3174 3175 /* clear state block */ 3176 if (adev->gfx.rlc.cp_table_obj) { 3177 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3178 if (unlikely(r != 0)) 3179 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3180 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); 3181 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3182 3183 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); 3184 adev->gfx.rlc.cp_table_obj = NULL; 3185 } 3186 } 3187 3188 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3189 { 3190 const u32 *src_ptr; 3191 volatile u32 *dst_ptr; 3192 u32 dws, i; 3193 const struct cs_section_def *cs_data; 3194 int r; 3195 3196 /* allocate rlc buffers */ 3197 if (adev->flags & AMD_IS_APU) { 3198 if (adev->asic_type == CHIP_KAVERI) { 3199 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3200 adev->gfx.rlc.reg_list_size = 3201 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3202 } else { 3203 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3204 adev->gfx.rlc.reg_list_size = 3205 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3206 } 3207 } 3208 adev->gfx.rlc.cs_data = ci_cs_data; 3209 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4; 3210 3211 src_ptr = adev->gfx.rlc.reg_list; 3212 dws = adev->gfx.rlc.reg_list_size; 3213 dws += (5 * 16) + 48 + 48 + 64; 3214 3215 cs_data = adev->gfx.rlc.cs_data; 3216 3217 if (src_ptr) { 3218 /* save restore block */ 3219 if (adev->gfx.rlc.save_restore_obj == NULL) { 3220 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3221 AMDGPU_GEM_DOMAIN_VRAM, 3222 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 3223 NULL, NULL, 3224 &adev->gfx.rlc.save_restore_obj); 3225 if (r) { 3226 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); 3227 return r; 3228 } 3229 } 3230 3231 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 3232 if (unlikely(r != 0)) { 3233 gfx_v7_0_rlc_fini(adev); 3234 return r; 3235 } 3236 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, 3237 &adev->gfx.rlc.save_restore_gpu_addr); 3238 if (r) { 3239 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3240 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); 3241 gfx_v7_0_rlc_fini(adev); 3242 return r; 3243 } 3244 3245 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); 3246 if (r) { 3247 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); 3248 gfx_v7_0_rlc_fini(adev); 3249 return r; 3250 } 3251 /* write the sr buffer */ 3252 dst_ptr = adev->gfx.rlc.sr_ptr; 3253 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3254 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 3255 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 3256 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 3257 } 3258 3259 if (cs_data) { 3260 /* clear state block */ 3261 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); 3262 3263 if (adev->gfx.rlc.clear_state_obj == NULL) { 3264 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 3265 AMDGPU_GEM_DOMAIN_VRAM, 3266 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 3267 NULL, NULL, 3268 &adev->gfx.rlc.clear_state_obj); 3269 if (r) { 3270 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 3271 gfx_v7_0_rlc_fini(adev); 3272 return r; 3273 } 3274 } 3275 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 3276 if (unlikely(r != 0)) { 3277 gfx_v7_0_rlc_fini(adev); 3278 return r; 3279 } 3280 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, 3281 &adev->gfx.rlc.clear_state_gpu_addr); 3282 if (r) { 3283 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3284 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); 3285 gfx_v7_0_rlc_fini(adev); 3286 return r; 3287 } 3288 3289 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); 3290 if (r) { 3291 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); 3292 gfx_v7_0_rlc_fini(adev); 3293 return r; 3294 } 3295 /* set up the cs buffer */ 3296 dst_ptr = adev->gfx.rlc.cs_ptr; 3297 gfx_v7_0_get_csb_buffer(adev, dst_ptr); 3298 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 3299 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 3300 } 3301 3302 if (adev->gfx.rlc.cp_table_size) { 3303 if (adev->gfx.rlc.cp_table_obj == NULL) { 3304 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, 3305 AMDGPU_GEM_DOMAIN_VRAM, 3306 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 3307 NULL, NULL, 3308 &adev->gfx.rlc.cp_table_obj); 3309 if (r) { 3310 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r); 3311 gfx_v7_0_rlc_fini(adev); 3312 return r; 3313 } 3314 } 3315 3316 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); 3317 if (unlikely(r != 0)) { 3318 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 3319 gfx_v7_0_rlc_fini(adev); 3320 return r; 3321 } 3322 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, 3323 &adev->gfx.rlc.cp_table_gpu_addr); 3324 if (r) { 3325 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3326 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); 3327 gfx_v7_0_rlc_fini(adev); 3328 return r; 3329 } 3330 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); 3331 if (r) { 3332 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r); 3333 gfx_v7_0_rlc_fini(adev); 3334 return r; 3335 } 3336 3337 gfx_v7_0_init_cp_pg_table(adev); 3338 3339 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 3340 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 3341 3342 } 3343 3344 return 0; 3345 } 3346 3347 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3348 { 3349 u32 tmp; 3350 3351 tmp = RREG32(mmRLC_LB_CNTL); 3352 if (enable) 3353 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3354 else 3355 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3356 WREG32(mmRLC_LB_CNTL, tmp); 3357 } 3358 3359 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3360 { 3361 u32 i, j, k; 3362 u32 mask; 3363 3364 mutex_lock(&adev->grbm_idx_mutex); 3365 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3366 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3367 gfx_v7_0_select_se_sh(adev, i, j); 3368 for (k = 0; k < adev->usec_timeout; k++) { 3369 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3370 break; 3371 udelay(1); 3372 } 3373 } 3374 } 3375 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3376 mutex_unlock(&adev->grbm_idx_mutex); 3377 3378 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3379 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3380 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3381 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3382 for (k = 0; k < adev->usec_timeout; k++) { 3383 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3384 break; 3385 udelay(1); 3386 } 3387 } 3388 3389 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3390 { 3391 u32 tmp; 3392 3393 tmp = RREG32(mmRLC_CNTL); 3394 if (tmp != rlc) 3395 WREG32(mmRLC_CNTL, rlc); 3396 } 3397 3398 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3399 { 3400 u32 data, orig; 3401 3402 orig = data = RREG32(mmRLC_CNTL); 3403 3404 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3405 u32 i; 3406 3407 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3408 WREG32(mmRLC_CNTL, data); 3409 3410 for (i = 0; i < adev->usec_timeout; i++) { 3411 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3412 break; 3413 udelay(1); 3414 } 3415 3416 gfx_v7_0_wait_for_rlc_serdes(adev); 3417 } 3418 3419 return orig; 3420 } 3421 3422 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3423 { 3424 u32 tmp, i, mask; 3425 3426 tmp = 0x1 | (1 << 1); 3427 WREG32(mmRLC_GPR_REG2, tmp); 3428 3429 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3430 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3431 for (i = 0; i < adev->usec_timeout; i++) { 3432 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3433 break; 3434 udelay(1); 3435 } 3436 3437 for (i = 0; i < adev->usec_timeout; i++) { 3438 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3439 break; 3440 udelay(1); 3441 } 3442 } 3443 3444 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3445 { 3446 u32 tmp; 3447 3448 tmp = 0x1 | (0 << 1); 3449 WREG32(mmRLC_GPR_REG2, tmp); 3450 } 3451 3452 /** 3453 * gfx_v7_0_rlc_stop - stop the RLC ME 3454 * 3455 * @adev: amdgpu_device pointer 3456 * 3457 * Halt the RLC ME (MicroEngine) (CIK). 3458 */ 3459 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3460 { 3461 WREG32(mmRLC_CNTL, 0); 3462 3463 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3464 3465 gfx_v7_0_wait_for_rlc_serdes(adev); 3466 } 3467 3468 /** 3469 * gfx_v7_0_rlc_start - start the RLC ME 3470 * 3471 * @adev: amdgpu_device pointer 3472 * 3473 * Unhalt the RLC ME (MicroEngine) (CIK). 3474 */ 3475 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3476 { 3477 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3478 3479 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3480 3481 udelay(50); 3482 } 3483 3484 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3485 { 3486 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3487 3488 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3489 WREG32(mmGRBM_SOFT_RESET, tmp); 3490 udelay(50); 3491 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3492 WREG32(mmGRBM_SOFT_RESET, tmp); 3493 udelay(50); 3494 } 3495 3496 /** 3497 * gfx_v7_0_rlc_resume - setup the RLC hw 3498 * 3499 * @adev: amdgpu_device pointer 3500 * 3501 * Initialize the RLC registers, load the ucode, 3502 * and start the RLC (CIK). 3503 * Returns 0 for success, -EINVAL if the ucode is not available. 3504 */ 3505 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3506 { 3507 const struct rlc_firmware_header_v1_0 *hdr; 3508 const __le32 *fw_data; 3509 unsigned i, fw_size; 3510 u32 tmp; 3511 3512 if (!adev->gfx.rlc_fw) 3513 return -EINVAL; 3514 3515 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3516 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3517 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3518 adev->gfx.rlc_feature_version = le32_to_cpu( 3519 hdr->ucode_feature_version); 3520 3521 gfx_v7_0_rlc_stop(adev); 3522 3523 /* disable CG */ 3524 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3525 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3526 3527 gfx_v7_0_rlc_reset(adev); 3528 3529 gfx_v7_0_init_pg(adev); 3530 3531 WREG32(mmRLC_LB_CNTR_INIT, 0); 3532 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3533 3534 mutex_lock(&adev->grbm_idx_mutex); 3535 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3536 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3537 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3538 WREG32(mmRLC_LB_CNTL, 0x80000004); 3539 mutex_unlock(&adev->grbm_idx_mutex); 3540 3541 WREG32(mmRLC_MC_CNTL, 0); 3542 WREG32(mmRLC_UCODE_CNTL, 0); 3543 3544 fw_data = (const __le32 *) 3545 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3546 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3547 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3548 for (i = 0; i < fw_size; i++) 3549 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3550 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3551 3552 /* XXX - find out what chips support lbpw */ 3553 gfx_v7_0_enable_lbpw(adev, false); 3554 3555 if (adev->asic_type == CHIP_BONAIRE) 3556 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3557 3558 gfx_v7_0_rlc_start(adev); 3559 3560 return 0; 3561 } 3562 3563 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3564 { 3565 u32 data, orig, tmp, tmp2; 3566 3567 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3568 3569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3570 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3571 3572 tmp = gfx_v7_0_halt_rlc(adev); 3573 3574 mutex_lock(&adev->grbm_idx_mutex); 3575 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3576 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3577 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3578 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3579 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3580 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3581 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3582 mutex_unlock(&adev->grbm_idx_mutex); 3583 3584 gfx_v7_0_update_rlc(adev, tmp); 3585 3586 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3587 } else { 3588 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3589 3590 RREG32(mmCB_CGTT_SCLK_CTRL); 3591 RREG32(mmCB_CGTT_SCLK_CTRL); 3592 RREG32(mmCB_CGTT_SCLK_CTRL); 3593 RREG32(mmCB_CGTT_SCLK_CTRL); 3594 3595 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3596 } 3597 3598 if (orig != data) 3599 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3600 3601 } 3602 3603 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3604 { 3605 u32 data, orig, tmp = 0; 3606 3607 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3608 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3609 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3610 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3611 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3612 if (orig != data) 3613 WREG32(mmCP_MEM_SLP_CNTL, data); 3614 } 3615 } 3616 3617 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3618 data |= 0x00000001; 3619 data &= 0xfffffffd; 3620 if (orig != data) 3621 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3622 3623 tmp = gfx_v7_0_halt_rlc(adev); 3624 3625 mutex_lock(&adev->grbm_idx_mutex); 3626 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3627 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3628 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3629 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3630 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3631 WREG32(mmRLC_SERDES_WR_CTRL, data); 3632 mutex_unlock(&adev->grbm_idx_mutex); 3633 3634 gfx_v7_0_update_rlc(adev, tmp); 3635 3636 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3637 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3638 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3639 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3640 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3641 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3642 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3643 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3644 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3645 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3646 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3647 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3648 if (orig != data) 3649 WREG32(mmCGTS_SM_CTRL_REG, data); 3650 } 3651 } else { 3652 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3653 data |= 0x00000003; 3654 if (orig != data) 3655 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3656 3657 data = RREG32(mmRLC_MEM_SLP_CNTL); 3658 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3659 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3660 WREG32(mmRLC_MEM_SLP_CNTL, data); 3661 } 3662 3663 data = RREG32(mmCP_MEM_SLP_CNTL); 3664 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3665 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3666 WREG32(mmCP_MEM_SLP_CNTL, data); 3667 } 3668 3669 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3670 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3671 if (orig != data) 3672 WREG32(mmCGTS_SM_CTRL_REG, data); 3673 3674 tmp = gfx_v7_0_halt_rlc(adev); 3675 3676 mutex_lock(&adev->grbm_idx_mutex); 3677 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 3678 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3679 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3680 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3681 WREG32(mmRLC_SERDES_WR_CTRL, data); 3682 mutex_unlock(&adev->grbm_idx_mutex); 3683 3684 gfx_v7_0_update_rlc(adev, tmp); 3685 } 3686 } 3687 3688 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3689 bool enable) 3690 { 3691 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3692 /* order matters! */ 3693 if (enable) { 3694 gfx_v7_0_enable_mgcg(adev, true); 3695 gfx_v7_0_enable_cgcg(adev, true); 3696 } else { 3697 gfx_v7_0_enable_cgcg(adev, false); 3698 gfx_v7_0_enable_mgcg(adev, false); 3699 } 3700 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3701 } 3702 3703 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3704 bool enable) 3705 { 3706 u32 data, orig; 3707 3708 orig = data = RREG32(mmRLC_PG_CNTL); 3709 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3710 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3711 else 3712 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3713 if (orig != data) 3714 WREG32(mmRLC_PG_CNTL, data); 3715 } 3716 3717 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3718 bool enable) 3719 { 3720 u32 data, orig; 3721 3722 orig = data = RREG32(mmRLC_PG_CNTL); 3723 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3724 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3725 else 3726 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3727 if (orig != data) 3728 WREG32(mmRLC_PG_CNTL, data); 3729 } 3730 3731 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3732 { 3733 u32 data, orig; 3734 3735 orig = data = RREG32(mmRLC_PG_CNTL); 3736 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3737 data &= ~0x8000; 3738 else 3739 data |= 0x8000; 3740 if (orig != data) 3741 WREG32(mmRLC_PG_CNTL, data); 3742 } 3743 3744 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3745 { 3746 u32 data, orig; 3747 3748 orig = data = RREG32(mmRLC_PG_CNTL); 3749 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3750 data &= ~0x2000; 3751 else 3752 data |= 0x2000; 3753 if (orig != data) 3754 WREG32(mmRLC_PG_CNTL, data); 3755 } 3756 3757 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev) 3758 { 3759 const __le32 *fw_data; 3760 volatile u32 *dst_ptr; 3761 int me, i, max_me = 4; 3762 u32 bo_offset = 0; 3763 u32 table_offset, table_size; 3764 3765 if (adev->asic_type == CHIP_KAVERI) 3766 max_me = 5; 3767 3768 if (adev->gfx.rlc.cp_table_ptr == NULL) 3769 return; 3770 3771 /* write the cp table buffer */ 3772 dst_ptr = adev->gfx.rlc.cp_table_ptr; 3773 for (me = 0; me < max_me; me++) { 3774 if (me == 0) { 3775 const struct gfx_firmware_header_v1_0 *hdr = 3776 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 3777 fw_data = (const __le32 *) 3778 (adev->gfx.ce_fw->data + 3779 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3780 table_offset = le32_to_cpu(hdr->jt_offset); 3781 table_size = le32_to_cpu(hdr->jt_size); 3782 } else if (me == 1) { 3783 const struct gfx_firmware_header_v1_0 *hdr = 3784 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 3785 fw_data = (const __le32 *) 3786 (adev->gfx.pfp_fw->data + 3787 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3788 table_offset = le32_to_cpu(hdr->jt_offset); 3789 table_size = le32_to_cpu(hdr->jt_size); 3790 } else if (me == 2) { 3791 const struct gfx_firmware_header_v1_0 *hdr = 3792 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 3793 fw_data = (const __le32 *) 3794 (adev->gfx.me_fw->data + 3795 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3796 table_offset = le32_to_cpu(hdr->jt_offset); 3797 table_size = le32_to_cpu(hdr->jt_size); 3798 } else if (me == 3) { 3799 const struct gfx_firmware_header_v1_0 *hdr = 3800 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3801 fw_data = (const __le32 *) 3802 (adev->gfx.mec_fw->data + 3803 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3804 table_offset = le32_to_cpu(hdr->jt_offset); 3805 table_size = le32_to_cpu(hdr->jt_size); 3806 } else { 3807 const struct gfx_firmware_header_v1_0 *hdr = 3808 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 3809 fw_data = (const __le32 *) 3810 (adev->gfx.mec2_fw->data + 3811 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3812 table_offset = le32_to_cpu(hdr->jt_offset); 3813 table_size = le32_to_cpu(hdr->jt_size); 3814 } 3815 3816 for (i = 0; i < table_size; i ++) { 3817 dst_ptr[bo_offset + i] = 3818 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 3819 } 3820 3821 bo_offset += table_size; 3822 } 3823 } 3824 3825 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3826 bool enable) 3827 { 3828 u32 data, orig; 3829 3830 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3831 orig = data = RREG32(mmRLC_PG_CNTL); 3832 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3833 if (orig != data) 3834 WREG32(mmRLC_PG_CNTL, data); 3835 3836 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3837 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3838 if (orig != data) 3839 WREG32(mmRLC_AUTO_PG_CTRL, data); 3840 } else { 3841 orig = data = RREG32(mmRLC_PG_CNTL); 3842 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3843 if (orig != data) 3844 WREG32(mmRLC_PG_CNTL, data); 3845 3846 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3847 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3848 if (orig != data) 3849 WREG32(mmRLC_AUTO_PG_CTRL, data); 3850 3851 data = RREG32(mmDB_RENDER_CONTROL); 3852 } 3853 } 3854 3855 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3856 { 3857 u32 data, mask; 3858 3859 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3860 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3861 3862 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3863 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3864 3865 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 3866 3867 return (~data) & mask; 3868 } 3869 3870 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3871 { 3872 uint32_t tmp, active_cu_number; 3873 struct amdgpu_cu_info cu_info; 3874 3875 gfx_v7_0_get_cu_info(adev, &cu_info); 3876 tmp = cu_info.ao_cu_mask; 3877 active_cu_number = cu_info.number; 3878 3879 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp); 3880 3881 tmp = RREG32(mmRLC_MAX_PG_CU); 3882 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3883 tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3884 WREG32(mmRLC_MAX_PG_CU, tmp); 3885 } 3886 3887 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3888 bool enable) 3889 { 3890 u32 data, orig; 3891 3892 orig = data = RREG32(mmRLC_PG_CNTL); 3893 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3894 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3895 else 3896 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3897 if (orig != data) 3898 WREG32(mmRLC_PG_CNTL, data); 3899 } 3900 3901 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3902 bool enable) 3903 { 3904 u32 data, orig; 3905 3906 orig = data = RREG32(mmRLC_PG_CNTL); 3907 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3908 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3909 else 3910 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3911 if (orig != data) 3912 WREG32(mmRLC_PG_CNTL, data); 3913 } 3914 3915 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3916 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3917 3918 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3919 { 3920 u32 data, orig; 3921 u32 i; 3922 3923 if (adev->gfx.rlc.cs_data) { 3924 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3925 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3926 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3927 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3928 } else { 3929 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3930 for (i = 0; i < 3; i++) 3931 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3932 } 3933 if (adev->gfx.rlc.reg_list) { 3934 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3935 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3936 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3937 } 3938 3939 orig = data = RREG32(mmRLC_PG_CNTL); 3940 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3941 if (orig != data) 3942 WREG32(mmRLC_PG_CNTL, data); 3943 3944 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3945 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3946 3947 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3948 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3949 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3950 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3951 3952 data = 0x10101010; 3953 WREG32(mmRLC_PG_DELAY, data); 3954 3955 data = RREG32(mmRLC_PG_DELAY_2); 3956 data &= ~0xff; 3957 data |= 0x3; 3958 WREG32(mmRLC_PG_DELAY_2, data); 3959 3960 data = RREG32(mmRLC_AUTO_PG_CTRL); 3961 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3962 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3963 WREG32(mmRLC_AUTO_PG_CTRL, data); 3964 3965 } 3966 3967 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3968 { 3969 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3970 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3971 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3972 } 3973 3974 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3975 { 3976 u32 count = 0; 3977 const struct cs_section_def *sect = NULL; 3978 const struct cs_extent_def *ext = NULL; 3979 3980 if (adev->gfx.rlc.cs_data == NULL) 3981 return 0; 3982 3983 /* begin clear state */ 3984 count += 2; 3985 /* context control state */ 3986 count += 3; 3987 3988 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3989 for (ext = sect->section; ext->extent != NULL; ++ext) { 3990 if (sect->id == SECT_CONTEXT) 3991 count += 2 + ext->reg_count; 3992 else 3993 return 0; 3994 } 3995 } 3996 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3997 count += 4; 3998 /* end clear state */ 3999 count += 2; 4000 /* clear state */ 4001 count += 2; 4002 4003 return count; 4004 } 4005 4006 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 4007 volatile u32 *buffer) 4008 { 4009 u32 count = 0, i; 4010 const struct cs_section_def *sect = NULL; 4011 const struct cs_extent_def *ext = NULL; 4012 4013 if (adev->gfx.rlc.cs_data == NULL) 4014 return; 4015 if (buffer == NULL) 4016 return; 4017 4018 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4019 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4020 4021 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4022 buffer[count++] = cpu_to_le32(0x80000000); 4023 buffer[count++] = cpu_to_le32(0x80000000); 4024 4025 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4026 for (ext = sect->section; ext->extent != NULL; ++ext) { 4027 if (sect->id == SECT_CONTEXT) { 4028 buffer[count++] = 4029 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4030 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 4031 for (i = 0; i < ext->reg_count; i++) 4032 buffer[count++] = cpu_to_le32(ext->extent[i]); 4033 } else { 4034 return; 4035 } 4036 } 4037 } 4038 4039 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 4040 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 4041 switch (adev->asic_type) { 4042 case CHIP_BONAIRE: 4043 buffer[count++] = cpu_to_le32(0x16000012); 4044 buffer[count++] = cpu_to_le32(0x00000000); 4045 break; 4046 case CHIP_KAVERI: 4047 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4048 buffer[count++] = cpu_to_le32(0x00000000); 4049 break; 4050 case CHIP_KABINI: 4051 case CHIP_MULLINS: 4052 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4053 buffer[count++] = cpu_to_le32(0x00000000); 4054 break; 4055 case CHIP_HAWAII: 4056 buffer[count++] = cpu_to_le32(0x3a00161a); 4057 buffer[count++] = cpu_to_le32(0x0000002e); 4058 break; 4059 default: 4060 buffer[count++] = cpu_to_le32(0x00000000); 4061 buffer[count++] = cpu_to_le32(0x00000000); 4062 break; 4063 } 4064 4065 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4066 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4067 4068 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4069 buffer[count++] = cpu_to_le32(0); 4070 } 4071 4072 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4073 { 4074 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4075 AMD_PG_SUPPORT_GFX_SMG | 4076 AMD_PG_SUPPORT_GFX_DMG | 4077 AMD_PG_SUPPORT_CP | 4078 AMD_PG_SUPPORT_GDS | 4079 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4080 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4081 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4082 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4083 gfx_v7_0_init_gfx_cgpg(adev); 4084 gfx_v7_0_enable_cp_pg(adev, true); 4085 gfx_v7_0_enable_gds_pg(adev, true); 4086 } 4087 gfx_v7_0_init_ao_cu_mask(adev); 4088 gfx_v7_0_update_gfx_pg(adev, true); 4089 } 4090 } 4091 4092 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4093 { 4094 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4095 AMD_PG_SUPPORT_GFX_SMG | 4096 AMD_PG_SUPPORT_GFX_DMG | 4097 AMD_PG_SUPPORT_CP | 4098 AMD_PG_SUPPORT_GDS | 4099 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4100 gfx_v7_0_update_gfx_pg(adev, false); 4101 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4102 gfx_v7_0_enable_cp_pg(adev, false); 4103 gfx_v7_0_enable_gds_pg(adev, false); 4104 } 4105 } 4106 } 4107 4108 /** 4109 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4110 * 4111 * @adev: amdgpu_device pointer 4112 * 4113 * Fetches a GPU clock counter snapshot (SI). 4114 * Returns the 64 bit clock counter snapshot. 4115 */ 4116 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4117 { 4118 uint64_t clock; 4119 4120 mutex_lock(&adev->gfx.gpu_clock_mutex); 4121 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4122 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4123 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4124 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4125 return clock; 4126 } 4127 4128 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4129 uint32_t vmid, 4130 uint32_t gds_base, uint32_t gds_size, 4131 uint32_t gws_base, uint32_t gws_size, 4132 uint32_t oa_base, uint32_t oa_size) 4133 { 4134 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 4135 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 4136 4137 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 4138 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 4139 4140 oa_base = oa_base >> AMDGPU_OA_SHIFT; 4141 oa_size = oa_size >> AMDGPU_OA_SHIFT; 4142 4143 /* GDS Base */ 4144 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4145 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4146 WRITE_DATA_DST_SEL(0))); 4147 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4148 amdgpu_ring_write(ring, 0); 4149 amdgpu_ring_write(ring, gds_base); 4150 4151 /* GDS Size */ 4152 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4153 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4154 WRITE_DATA_DST_SEL(0))); 4155 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4156 amdgpu_ring_write(ring, 0); 4157 amdgpu_ring_write(ring, gds_size); 4158 4159 /* GWS */ 4160 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4161 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4162 WRITE_DATA_DST_SEL(0))); 4163 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4164 amdgpu_ring_write(ring, 0); 4165 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4166 4167 /* OA */ 4168 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4169 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4170 WRITE_DATA_DST_SEL(0))); 4171 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4172 amdgpu_ring_write(ring, 0); 4173 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4174 } 4175 4176 static int gfx_v7_0_early_init(void *handle) 4177 { 4178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4179 4180 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4181 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; 4182 gfx_v7_0_set_ring_funcs(adev); 4183 gfx_v7_0_set_irq_funcs(adev); 4184 gfx_v7_0_set_gds_init(adev); 4185 4186 return 0; 4187 } 4188 4189 static int gfx_v7_0_late_init(void *handle) 4190 { 4191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4192 int r; 4193 4194 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4195 if (r) 4196 return r; 4197 4198 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4199 if (r) 4200 return r; 4201 4202 return 0; 4203 } 4204 4205 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4206 { 4207 u32 gb_addr_config; 4208 u32 mc_shared_chmap, mc_arb_ramcfg; 4209 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4210 u32 tmp; 4211 4212 switch (adev->asic_type) { 4213 case CHIP_BONAIRE: 4214 adev->gfx.config.max_shader_engines = 2; 4215 adev->gfx.config.max_tile_pipes = 4; 4216 adev->gfx.config.max_cu_per_sh = 7; 4217 adev->gfx.config.max_sh_per_se = 1; 4218 adev->gfx.config.max_backends_per_se = 2; 4219 adev->gfx.config.max_texture_channel_caches = 4; 4220 adev->gfx.config.max_gprs = 256; 4221 adev->gfx.config.max_gs_threads = 32; 4222 adev->gfx.config.max_hw_contexts = 8; 4223 4224 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4225 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4226 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4227 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4228 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4229 break; 4230 case CHIP_HAWAII: 4231 adev->gfx.config.max_shader_engines = 4; 4232 adev->gfx.config.max_tile_pipes = 16; 4233 adev->gfx.config.max_cu_per_sh = 11; 4234 adev->gfx.config.max_sh_per_se = 1; 4235 adev->gfx.config.max_backends_per_se = 4; 4236 adev->gfx.config.max_texture_channel_caches = 16; 4237 adev->gfx.config.max_gprs = 256; 4238 adev->gfx.config.max_gs_threads = 32; 4239 adev->gfx.config.max_hw_contexts = 8; 4240 4241 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4242 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4243 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4244 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4245 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4246 break; 4247 case CHIP_KAVERI: 4248 adev->gfx.config.max_shader_engines = 1; 4249 adev->gfx.config.max_tile_pipes = 4; 4250 if ((adev->pdev->device == 0x1304) || 4251 (adev->pdev->device == 0x1305) || 4252 (adev->pdev->device == 0x130C) || 4253 (adev->pdev->device == 0x130F) || 4254 (adev->pdev->device == 0x1310) || 4255 (adev->pdev->device == 0x1311) || 4256 (adev->pdev->device == 0x131C)) { 4257 adev->gfx.config.max_cu_per_sh = 8; 4258 adev->gfx.config.max_backends_per_se = 2; 4259 } else if ((adev->pdev->device == 0x1309) || 4260 (adev->pdev->device == 0x130A) || 4261 (adev->pdev->device == 0x130D) || 4262 (adev->pdev->device == 0x1313) || 4263 (adev->pdev->device == 0x131D)) { 4264 adev->gfx.config.max_cu_per_sh = 6; 4265 adev->gfx.config.max_backends_per_se = 2; 4266 } else if ((adev->pdev->device == 0x1306) || 4267 (adev->pdev->device == 0x1307) || 4268 (adev->pdev->device == 0x130B) || 4269 (adev->pdev->device == 0x130E) || 4270 (adev->pdev->device == 0x1315) || 4271 (adev->pdev->device == 0x131B)) { 4272 adev->gfx.config.max_cu_per_sh = 4; 4273 adev->gfx.config.max_backends_per_se = 1; 4274 } else { 4275 adev->gfx.config.max_cu_per_sh = 3; 4276 adev->gfx.config.max_backends_per_se = 1; 4277 } 4278 adev->gfx.config.max_sh_per_se = 1; 4279 adev->gfx.config.max_texture_channel_caches = 4; 4280 adev->gfx.config.max_gprs = 256; 4281 adev->gfx.config.max_gs_threads = 16; 4282 adev->gfx.config.max_hw_contexts = 8; 4283 4284 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4285 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4286 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4287 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4288 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4289 break; 4290 case CHIP_KABINI: 4291 case CHIP_MULLINS: 4292 default: 4293 adev->gfx.config.max_shader_engines = 1; 4294 adev->gfx.config.max_tile_pipes = 2; 4295 adev->gfx.config.max_cu_per_sh = 2; 4296 adev->gfx.config.max_sh_per_se = 1; 4297 adev->gfx.config.max_backends_per_se = 1; 4298 adev->gfx.config.max_texture_channel_caches = 2; 4299 adev->gfx.config.max_gprs = 256; 4300 adev->gfx.config.max_gs_threads = 16; 4301 adev->gfx.config.max_hw_contexts = 8; 4302 4303 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4304 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4305 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4306 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4307 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4308 break; 4309 } 4310 4311 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 4312 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4313 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4314 4315 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4316 adev->gfx.config.mem_max_burst_length_bytes = 256; 4317 if (adev->flags & AMD_IS_APU) { 4318 /* Get memory bank mapping mode. */ 4319 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4320 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4321 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4322 4323 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4324 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4325 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4326 4327 /* Validate settings in case only one DIMM installed. */ 4328 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4329 dimm00_addr_map = 0; 4330 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4331 dimm01_addr_map = 0; 4332 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4333 dimm10_addr_map = 0; 4334 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4335 dimm11_addr_map = 0; 4336 4337 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4338 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4339 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4340 adev->gfx.config.mem_row_size_in_kb = 2; 4341 else 4342 adev->gfx.config.mem_row_size_in_kb = 1; 4343 } else { 4344 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4345 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4346 if (adev->gfx.config.mem_row_size_in_kb > 4) 4347 adev->gfx.config.mem_row_size_in_kb = 4; 4348 } 4349 /* XXX use MC settings? */ 4350 adev->gfx.config.shader_engine_tile_size = 32; 4351 adev->gfx.config.num_gpus = 1; 4352 adev->gfx.config.multi_gpu_tile_size = 64; 4353 4354 /* fix up row size */ 4355 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4356 switch (adev->gfx.config.mem_row_size_in_kb) { 4357 case 1: 4358 default: 4359 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4360 break; 4361 case 2: 4362 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4363 break; 4364 case 4: 4365 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4366 break; 4367 } 4368 adev->gfx.config.gb_addr_config = gb_addr_config; 4369 } 4370 4371 static int gfx_v7_0_sw_init(void *handle) 4372 { 4373 struct amdgpu_ring *ring; 4374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4375 int i, r; 4376 4377 /* EOP Event */ 4378 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); 4379 if (r) 4380 return r; 4381 4382 /* Privileged reg */ 4383 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); 4384 if (r) 4385 return r; 4386 4387 /* Privileged inst */ 4388 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); 4389 if (r) 4390 return r; 4391 4392 gfx_v7_0_scratch_init(adev); 4393 4394 r = gfx_v7_0_init_microcode(adev); 4395 if (r) { 4396 DRM_ERROR("Failed to load gfx firmware!\n"); 4397 return r; 4398 } 4399 4400 r = gfx_v7_0_rlc_init(adev); 4401 if (r) { 4402 DRM_ERROR("Failed to init rlc BOs!\n"); 4403 return r; 4404 } 4405 4406 /* allocate mec buffers */ 4407 r = gfx_v7_0_mec_init(adev); 4408 if (r) { 4409 DRM_ERROR("Failed to init MEC BOs!\n"); 4410 return r; 4411 } 4412 4413 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4414 ring = &adev->gfx.gfx_ring[i]; 4415 ring->ring_obj = NULL; 4416 sprintf(ring->name, "gfx"); 4417 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 4418 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 4419 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, 4420 AMDGPU_RING_TYPE_GFX); 4421 if (r) 4422 return r; 4423 } 4424 4425 /* set up the compute queues */ 4426 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4427 unsigned irq_type; 4428 4429 /* max 32 queues per MEC */ 4430 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 4431 DRM_ERROR("Too many (%d) compute rings!\n", i); 4432 break; 4433 } 4434 ring = &adev->gfx.compute_ring[i]; 4435 ring->ring_obj = NULL; 4436 ring->use_doorbell = true; 4437 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i; 4438 ring->me = 1; /* first MEC */ 4439 ring->pipe = i / 8; 4440 ring->queue = i % 8; 4441 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); 4442 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 4443 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4444 r = amdgpu_ring_init(adev, ring, 1024 * 1024, 4445 PACKET3(PACKET3_NOP, 0x3FFF), 0xf, 4446 &adev->gfx.eop_irq, irq_type, 4447 AMDGPU_RING_TYPE_COMPUTE); 4448 if (r) 4449 return r; 4450 } 4451 4452 /* reserve GDS, GWS and OA resource for gfx */ 4453 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size, 4454 PAGE_SIZE, true, 4455 AMDGPU_GEM_DOMAIN_GDS, 0, 4456 NULL, NULL, &adev->gds.gds_gfx_bo); 4457 if (r) 4458 return r; 4459 4460 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size, 4461 PAGE_SIZE, true, 4462 AMDGPU_GEM_DOMAIN_GWS, 0, 4463 NULL, NULL, &adev->gds.gws_gfx_bo); 4464 if (r) 4465 return r; 4466 4467 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size, 4468 PAGE_SIZE, true, 4469 AMDGPU_GEM_DOMAIN_OA, 0, 4470 NULL, NULL, &adev->gds.oa_gfx_bo); 4471 if (r) 4472 return r; 4473 4474 adev->gfx.ce_ram_size = 0x8000; 4475 4476 gfx_v7_0_gpu_early_init(adev); 4477 4478 return r; 4479 } 4480 4481 static int gfx_v7_0_sw_fini(void *handle) 4482 { 4483 int i; 4484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4485 4486 amdgpu_bo_unref(&adev->gds.oa_gfx_bo); 4487 amdgpu_bo_unref(&adev->gds.gws_gfx_bo); 4488 amdgpu_bo_unref(&adev->gds.gds_gfx_bo); 4489 4490 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4491 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4492 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4493 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4494 4495 gfx_v7_0_cp_compute_fini(adev); 4496 gfx_v7_0_rlc_fini(adev); 4497 gfx_v7_0_mec_fini(adev); 4498 4499 return 0; 4500 } 4501 4502 static int gfx_v7_0_hw_init(void *handle) 4503 { 4504 int r; 4505 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4506 4507 gfx_v7_0_gpu_init(adev); 4508 4509 /* init rlc */ 4510 r = gfx_v7_0_rlc_resume(adev); 4511 if (r) 4512 return r; 4513 4514 r = gfx_v7_0_cp_resume(adev); 4515 if (r) 4516 return r; 4517 4518 return r; 4519 } 4520 4521 static int gfx_v7_0_hw_fini(void *handle) 4522 { 4523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4524 4525 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4526 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4527 gfx_v7_0_cp_enable(adev, false); 4528 gfx_v7_0_rlc_stop(adev); 4529 gfx_v7_0_fini_pg(adev); 4530 4531 return 0; 4532 } 4533 4534 static int gfx_v7_0_suspend(void *handle) 4535 { 4536 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4537 4538 return gfx_v7_0_hw_fini(adev); 4539 } 4540 4541 static int gfx_v7_0_resume(void *handle) 4542 { 4543 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4544 4545 return gfx_v7_0_hw_init(adev); 4546 } 4547 4548 static bool gfx_v7_0_is_idle(void *handle) 4549 { 4550 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4551 4552 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4553 return false; 4554 else 4555 return true; 4556 } 4557 4558 static int gfx_v7_0_wait_for_idle(void *handle) 4559 { 4560 unsigned i; 4561 u32 tmp; 4562 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4563 4564 for (i = 0; i < adev->usec_timeout; i++) { 4565 /* read MC_STATUS */ 4566 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4567 4568 if (!tmp) 4569 return 0; 4570 udelay(1); 4571 } 4572 return -ETIMEDOUT; 4573 } 4574 4575 static void gfx_v7_0_print_status(void *handle) 4576 { 4577 int i; 4578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4579 4580 dev_info(adev->dev, "GFX 7.x registers\n"); 4581 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 4582 RREG32(mmGRBM_STATUS)); 4583 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 4584 RREG32(mmGRBM_STATUS2)); 4585 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 4586 RREG32(mmGRBM_STATUS_SE0)); 4587 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 4588 RREG32(mmGRBM_STATUS_SE1)); 4589 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 4590 RREG32(mmGRBM_STATUS_SE2)); 4591 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 4592 RREG32(mmGRBM_STATUS_SE3)); 4593 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 4594 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 4595 RREG32(mmCP_STALLED_STAT1)); 4596 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 4597 RREG32(mmCP_STALLED_STAT2)); 4598 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 4599 RREG32(mmCP_STALLED_STAT3)); 4600 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 4601 RREG32(mmCP_CPF_BUSY_STAT)); 4602 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 4603 RREG32(mmCP_CPF_STALLED_STAT1)); 4604 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 4605 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 4606 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 4607 RREG32(mmCP_CPC_STALLED_STAT1)); 4608 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 4609 4610 for (i = 0; i < 32; i++) { 4611 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n", 4612 i, RREG32(mmGB_TILE_MODE0 + (i * 4))); 4613 } 4614 for (i = 0; i < 16; i++) { 4615 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n", 4616 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4))); 4617 } 4618 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4619 dev_info(adev->dev, " se: %d\n", i); 4620 gfx_v7_0_select_se_sh(adev, i, 0xffffffff); 4621 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n", 4622 RREG32(mmPA_SC_RASTER_CONFIG)); 4623 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n", 4624 RREG32(mmPA_SC_RASTER_CONFIG_1)); 4625 } 4626 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 4627 4628 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n", 4629 RREG32(mmGB_ADDR_CONFIG)); 4630 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n", 4631 RREG32(mmHDP_ADDR_CONFIG)); 4632 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n", 4633 RREG32(mmDMIF_ADDR_CALC)); 4634 4635 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n", 4636 RREG32(mmCP_MEQ_THRESHOLDS)); 4637 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n", 4638 RREG32(mmSX_DEBUG_1)); 4639 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n", 4640 RREG32(mmTA_CNTL_AUX)); 4641 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n", 4642 RREG32(mmSPI_CONFIG_CNTL)); 4643 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n", 4644 RREG32(mmSQ_CONFIG)); 4645 dev_info(adev->dev, " DB_DEBUG=0x%08X\n", 4646 RREG32(mmDB_DEBUG)); 4647 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n", 4648 RREG32(mmDB_DEBUG2)); 4649 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n", 4650 RREG32(mmDB_DEBUG3)); 4651 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n", 4652 RREG32(mmCB_HW_CONTROL)); 4653 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n", 4654 RREG32(mmSPI_CONFIG_CNTL_1)); 4655 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n", 4656 RREG32(mmPA_SC_FIFO_SIZE)); 4657 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n", 4658 RREG32(mmVGT_NUM_INSTANCES)); 4659 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n", 4660 RREG32(mmCP_PERFMON_CNTL)); 4661 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n", 4662 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS)); 4663 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n", 4664 RREG32(mmVGT_CACHE_INVALIDATION)); 4665 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n", 4666 RREG32(mmVGT_GS_VERTEX_REUSE)); 4667 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n", 4668 RREG32(mmPA_SC_LINE_STIPPLE_STATE)); 4669 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n", 4670 RREG32(mmPA_CL_ENHANCE)); 4671 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n", 4672 RREG32(mmPA_SC_ENHANCE)); 4673 4674 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n", 4675 RREG32(mmCP_ME_CNTL)); 4676 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n", 4677 RREG32(mmCP_MAX_CONTEXT)); 4678 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n", 4679 RREG32(mmCP_ENDIAN_SWAP)); 4680 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n", 4681 RREG32(mmCP_DEVICE_ID)); 4682 4683 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n", 4684 RREG32(mmCP_SEM_WAIT_TIMER)); 4685 if (adev->asic_type != CHIP_HAWAII) 4686 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n", 4687 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL)); 4688 4689 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n", 4690 RREG32(mmCP_RB_WPTR_DELAY)); 4691 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n", 4692 RREG32(mmCP_RB_VMID)); 4693 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 4694 RREG32(mmCP_RB0_CNTL)); 4695 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n", 4696 RREG32(mmCP_RB0_WPTR)); 4697 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n", 4698 RREG32(mmCP_RB0_RPTR_ADDR)); 4699 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n", 4700 RREG32(mmCP_RB0_RPTR_ADDR_HI)); 4701 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n", 4702 RREG32(mmCP_RB0_CNTL)); 4703 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n", 4704 RREG32(mmCP_RB0_BASE)); 4705 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n", 4706 RREG32(mmCP_RB0_BASE_HI)); 4707 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n", 4708 RREG32(mmCP_MEC_CNTL)); 4709 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n", 4710 RREG32(mmCP_CPF_DEBUG)); 4711 4712 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n", 4713 RREG32(mmSCRATCH_ADDR)); 4714 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n", 4715 RREG32(mmSCRATCH_UMSK)); 4716 4717 /* init the pipes */ 4718 mutex_lock(&adev->srbm_mutex); 4719 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { 4720 int me = (i < 4) ? 1 : 2; 4721 int pipe = (i < 4) ? i : (i - 4); 4722 int queue; 4723 4724 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe); 4725 cik_srbm_select(adev, me, pipe, 0, 0); 4726 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n", 4727 RREG32(mmCP_HPD_EOP_BASE_ADDR)); 4728 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n", 4729 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI)); 4730 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n", 4731 RREG32(mmCP_HPD_EOP_VMID)); 4732 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n", 4733 RREG32(mmCP_HPD_EOP_CONTROL)); 4734 4735 for (queue = 0; queue < 8; queue++) { 4736 cik_srbm_select(adev, me, pipe, queue, 0); 4737 dev_info(adev->dev, " queue: %d\n", queue); 4738 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n", 4739 RREG32(mmCP_PQ_WPTR_POLL_CNTL)); 4740 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", 4741 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); 4742 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n", 4743 RREG32(mmCP_HQD_ACTIVE)); 4744 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n", 4745 RREG32(mmCP_HQD_DEQUEUE_REQUEST)); 4746 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n", 4747 RREG32(mmCP_HQD_PQ_RPTR)); 4748 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", 4749 RREG32(mmCP_HQD_PQ_WPTR)); 4750 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n", 4751 RREG32(mmCP_HQD_PQ_BASE)); 4752 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n", 4753 RREG32(mmCP_HQD_PQ_BASE_HI)); 4754 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n", 4755 RREG32(mmCP_HQD_PQ_CONTROL)); 4756 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n", 4757 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR)); 4758 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n", 4759 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)); 4760 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n", 4761 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR)); 4762 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n", 4763 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)); 4764 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n", 4765 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)); 4766 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n", 4767 RREG32(mmCP_HQD_PQ_WPTR)); 4768 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n", 4769 RREG32(mmCP_HQD_VMID)); 4770 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n", 4771 RREG32(mmCP_MQD_BASE_ADDR)); 4772 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n", 4773 RREG32(mmCP_MQD_BASE_ADDR_HI)); 4774 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n", 4775 RREG32(mmCP_MQD_CONTROL)); 4776 } 4777 } 4778 cik_srbm_select(adev, 0, 0, 0, 0); 4779 mutex_unlock(&adev->srbm_mutex); 4780 4781 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n", 4782 RREG32(mmCP_INT_CNTL_RING0)); 4783 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 4784 RREG32(mmRLC_LB_CNTL)); 4785 dev_info(adev->dev, " RLC_CNTL=0x%08X\n", 4786 RREG32(mmRLC_CNTL)); 4787 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n", 4788 RREG32(mmRLC_CGCG_CGLS_CTRL)); 4789 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n", 4790 RREG32(mmRLC_LB_CNTR_INIT)); 4791 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n", 4792 RREG32(mmRLC_LB_CNTR_MAX)); 4793 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n", 4794 RREG32(mmRLC_LB_INIT_CU_MASK)); 4795 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n", 4796 RREG32(mmRLC_LB_PARAMS)); 4797 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n", 4798 RREG32(mmRLC_LB_CNTL)); 4799 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n", 4800 RREG32(mmRLC_MC_CNTL)); 4801 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n", 4802 RREG32(mmRLC_UCODE_CNTL)); 4803 4804 if (adev->asic_type == CHIP_BONAIRE) 4805 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n", 4806 RREG32(mmRLC_DRIVER_CPDMA_STATUS)); 4807 4808 mutex_lock(&adev->srbm_mutex); 4809 for (i = 0; i < 16; i++) { 4810 cik_srbm_select(adev, 0, 0, 0, i); 4811 dev_info(adev->dev, " VM %d:\n", i); 4812 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n", 4813 RREG32(mmSH_MEM_CONFIG)); 4814 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n", 4815 RREG32(mmSH_MEM_APE1_BASE)); 4816 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n", 4817 RREG32(mmSH_MEM_APE1_LIMIT)); 4818 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n", 4819 RREG32(mmSH_MEM_BASES)); 4820 } 4821 cik_srbm_select(adev, 0, 0, 0, 0); 4822 mutex_unlock(&adev->srbm_mutex); 4823 } 4824 4825 static int gfx_v7_0_soft_reset(void *handle) 4826 { 4827 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4828 u32 tmp; 4829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4830 4831 /* GRBM_STATUS */ 4832 tmp = RREG32(mmGRBM_STATUS); 4833 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4834 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4835 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4836 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4837 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4838 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4839 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4840 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4841 4842 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4843 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4844 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4845 } 4846 4847 /* GRBM_STATUS2 */ 4848 tmp = RREG32(mmGRBM_STATUS2); 4849 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4850 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4851 4852 /* SRBM_STATUS */ 4853 tmp = RREG32(mmSRBM_STATUS); 4854 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4855 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4856 4857 if (grbm_soft_reset || srbm_soft_reset) { 4858 gfx_v7_0_print_status((void *)adev); 4859 /* disable CG/PG */ 4860 gfx_v7_0_fini_pg(adev); 4861 gfx_v7_0_update_cg(adev, false); 4862 4863 /* stop the rlc */ 4864 gfx_v7_0_rlc_stop(adev); 4865 4866 /* Disable GFX parsing/prefetching */ 4867 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4868 4869 /* Disable MEC parsing/prefetching */ 4870 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4871 4872 if (grbm_soft_reset) { 4873 tmp = RREG32(mmGRBM_SOFT_RESET); 4874 tmp |= grbm_soft_reset; 4875 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4876 WREG32(mmGRBM_SOFT_RESET, tmp); 4877 tmp = RREG32(mmGRBM_SOFT_RESET); 4878 4879 udelay(50); 4880 4881 tmp &= ~grbm_soft_reset; 4882 WREG32(mmGRBM_SOFT_RESET, tmp); 4883 tmp = RREG32(mmGRBM_SOFT_RESET); 4884 } 4885 4886 if (srbm_soft_reset) { 4887 tmp = RREG32(mmSRBM_SOFT_RESET); 4888 tmp |= srbm_soft_reset; 4889 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4890 WREG32(mmSRBM_SOFT_RESET, tmp); 4891 tmp = RREG32(mmSRBM_SOFT_RESET); 4892 4893 udelay(50); 4894 4895 tmp &= ~srbm_soft_reset; 4896 WREG32(mmSRBM_SOFT_RESET, tmp); 4897 tmp = RREG32(mmSRBM_SOFT_RESET); 4898 } 4899 /* Wait a little for things to settle down */ 4900 udelay(50); 4901 gfx_v7_0_print_status((void *)adev); 4902 } 4903 return 0; 4904 } 4905 4906 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4907 enum amdgpu_interrupt_state state) 4908 { 4909 u32 cp_int_cntl; 4910 4911 switch (state) { 4912 case AMDGPU_IRQ_STATE_DISABLE: 4913 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4914 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4915 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4916 break; 4917 case AMDGPU_IRQ_STATE_ENABLE: 4918 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4919 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4920 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4921 break; 4922 default: 4923 break; 4924 } 4925 } 4926 4927 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4928 int me, int pipe, 4929 enum amdgpu_interrupt_state state) 4930 { 4931 u32 mec_int_cntl, mec_int_cntl_reg; 4932 4933 /* 4934 * amdgpu controls only pipe 0 of MEC1. That's why this function only 4935 * handles the setting of interrupts for this specific pipe. All other 4936 * pipes' interrupts are set by amdkfd. 4937 */ 4938 4939 if (me == 1) { 4940 switch (pipe) { 4941 case 0: 4942 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4943 break; 4944 default: 4945 DRM_DEBUG("invalid pipe %d\n", pipe); 4946 return; 4947 } 4948 } else { 4949 DRM_DEBUG("invalid me %d\n", me); 4950 return; 4951 } 4952 4953 switch (state) { 4954 case AMDGPU_IRQ_STATE_DISABLE: 4955 mec_int_cntl = RREG32(mec_int_cntl_reg); 4956 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4957 WREG32(mec_int_cntl_reg, mec_int_cntl); 4958 break; 4959 case AMDGPU_IRQ_STATE_ENABLE: 4960 mec_int_cntl = RREG32(mec_int_cntl_reg); 4961 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4962 WREG32(mec_int_cntl_reg, mec_int_cntl); 4963 break; 4964 default: 4965 break; 4966 } 4967 } 4968 4969 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4970 struct amdgpu_irq_src *src, 4971 unsigned type, 4972 enum amdgpu_interrupt_state state) 4973 { 4974 u32 cp_int_cntl; 4975 4976 switch (state) { 4977 case AMDGPU_IRQ_STATE_DISABLE: 4978 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4979 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4980 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4981 break; 4982 case AMDGPU_IRQ_STATE_ENABLE: 4983 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4984 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4985 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4986 break; 4987 default: 4988 break; 4989 } 4990 4991 return 0; 4992 } 4993 4994 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4995 struct amdgpu_irq_src *src, 4996 unsigned type, 4997 enum amdgpu_interrupt_state state) 4998 { 4999 u32 cp_int_cntl; 5000 5001 switch (state) { 5002 case AMDGPU_IRQ_STATE_DISABLE: 5003 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 5004 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 5005 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 5006 break; 5007 case AMDGPU_IRQ_STATE_ENABLE: 5008 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 5009 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 5010 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 5011 break; 5012 default: 5013 break; 5014 } 5015 5016 return 0; 5017 } 5018 5019 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5020 struct amdgpu_irq_src *src, 5021 unsigned type, 5022 enum amdgpu_interrupt_state state) 5023 { 5024 switch (type) { 5025 case AMDGPU_CP_IRQ_GFX_EOP: 5026 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 5027 break; 5028 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5029 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5030 break; 5031 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5032 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5033 break; 5034 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5035 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5036 break; 5037 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5038 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5039 break; 5040 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5041 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5042 break; 5043 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5044 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5045 break; 5046 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5047 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5048 break; 5049 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5050 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5051 break; 5052 default: 5053 break; 5054 } 5055 return 0; 5056 } 5057 5058 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 5059 struct amdgpu_irq_src *source, 5060 struct amdgpu_iv_entry *entry) 5061 { 5062 u8 me_id, pipe_id; 5063 struct amdgpu_ring *ring; 5064 int i; 5065 5066 DRM_DEBUG("IH: CP EOP\n"); 5067 me_id = (entry->ring_id & 0x0c) >> 2; 5068 pipe_id = (entry->ring_id & 0x03) >> 0; 5069 switch (me_id) { 5070 case 0: 5071 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5072 break; 5073 case 1: 5074 case 2: 5075 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5076 ring = &adev->gfx.compute_ring[i]; 5077 if ((ring->me == me_id) & (ring->pipe == pipe_id)) 5078 amdgpu_fence_process(ring); 5079 } 5080 break; 5081 } 5082 return 0; 5083 } 5084 5085 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 5086 struct amdgpu_irq_src *source, 5087 struct amdgpu_iv_entry *entry) 5088 { 5089 DRM_ERROR("Illegal register access in command stream\n"); 5090 schedule_work(&adev->reset_work); 5091 return 0; 5092 } 5093 5094 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 5095 struct amdgpu_irq_src *source, 5096 struct amdgpu_iv_entry *entry) 5097 { 5098 DRM_ERROR("Illegal instruction in command stream\n"); 5099 // XXX soft reset the gfx block only 5100 schedule_work(&adev->reset_work); 5101 return 0; 5102 } 5103 5104 static int gfx_v7_0_set_clockgating_state(void *handle, 5105 enum amd_clockgating_state state) 5106 { 5107 bool gate = false; 5108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5109 5110 if (state == AMD_CG_STATE_GATE) 5111 gate = true; 5112 5113 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 5114 /* order matters! */ 5115 if (gate) { 5116 gfx_v7_0_enable_mgcg(adev, true); 5117 gfx_v7_0_enable_cgcg(adev, true); 5118 } else { 5119 gfx_v7_0_enable_cgcg(adev, false); 5120 gfx_v7_0_enable_mgcg(adev, false); 5121 } 5122 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 5123 5124 return 0; 5125 } 5126 5127 static int gfx_v7_0_set_powergating_state(void *handle, 5128 enum amd_powergating_state state) 5129 { 5130 bool gate = false; 5131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5132 5133 if (state == AMD_PG_STATE_GATE) 5134 gate = true; 5135 5136 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 5137 AMD_PG_SUPPORT_GFX_SMG | 5138 AMD_PG_SUPPORT_GFX_DMG | 5139 AMD_PG_SUPPORT_CP | 5140 AMD_PG_SUPPORT_GDS | 5141 AMD_PG_SUPPORT_RLC_SMU_HS)) { 5142 gfx_v7_0_update_gfx_pg(adev, gate); 5143 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 5144 gfx_v7_0_enable_cp_pg(adev, gate); 5145 gfx_v7_0_enable_gds_pg(adev, gate); 5146 } 5147 } 5148 5149 return 0; 5150 } 5151 5152 const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 5153 .early_init = gfx_v7_0_early_init, 5154 .late_init = gfx_v7_0_late_init, 5155 .sw_init = gfx_v7_0_sw_init, 5156 .sw_fini = gfx_v7_0_sw_fini, 5157 .hw_init = gfx_v7_0_hw_init, 5158 .hw_fini = gfx_v7_0_hw_fini, 5159 .suspend = gfx_v7_0_suspend, 5160 .resume = gfx_v7_0_resume, 5161 .is_idle = gfx_v7_0_is_idle, 5162 .wait_for_idle = gfx_v7_0_wait_for_idle, 5163 .soft_reset = gfx_v7_0_soft_reset, 5164 .print_status = gfx_v7_0_print_status, 5165 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 5166 .set_powergating_state = gfx_v7_0_set_powergating_state, 5167 }; 5168 5169 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 5170 .get_rptr = gfx_v7_0_ring_get_rptr_gfx, 5171 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 5172 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 5173 .parse_cs = NULL, 5174 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5175 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5176 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5177 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5178 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5179 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5180 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5181 .test_ring = gfx_v7_0_ring_test_ring, 5182 .test_ib = gfx_v7_0_ring_test_ib, 5183 .insert_nop = amdgpu_ring_insert_nop, 5184 .pad_ib = amdgpu_ring_generic_pad_ib, 5185 }; 5186 5187 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5188 .get_rptr = gfx_v7_0_ring_get_rptr_compute, 5189 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5190 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5191 .parse_cs = NULL, 5192 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5193 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5194 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5195 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5196 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5197 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5198 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, 5199 .test_ring = gfx_v7_0_ring_test_ring, 5200 .test_ib = gfx_v7_0_ring_test_ib, 5201 .insert_nop = amdgpu_ring_insert_nop, 5202 .pad_ib = amdgpu_ring_generic_pad_ib, 5203 }; 5204 5205 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5206 { 5207 int i; 5208 5209 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5210 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5211 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5212 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5213 } 5214 5215 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5216 .set = gfx_v7_0_set_eop_interrupt_state, 5217 .process = gfx_v7_0_eop_irq, 5218 }; 5219 5220 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5221 .set = gfx_v7_0_set_priv_reg_fault_state, 5222 .process = gfx_v7_0_priv_reg_irq, 5223 }; 5224 5225 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5226 .set = gfx_v7_0_set_priv_inst_fault_state, 5227 .process = gfx_v7_0_priv_inst_irq, 5228 }; 5229 5230 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5231 { 5232 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5233 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5234 5235 adev->gfx.priv_reg_irq.num_types = 1; 5236 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5237 5238 adev->gfx.priv_inst_irq.num_types = 1; 5239 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5240 } 5241 5242 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5243 { 5244 /* init asci gds info */ 5245 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE); 5246 adev->gds.gws.total_size = 64; 5247 adev->gds.oa.total_size = 16; 5248 5249 if (adev->gds.mem.total_size == 64 * 1024) { 5250 adev->gds.mem.gfx_partition_size = 4096; 5251 adev->gds.mem.cs_partition_size = 4096; 5252 5253 adev->gds.gws.gfx_partition_size = 4; 5254 adev->gds.gws.cs_partition_size = 4; 5255 5256 adev->gds.oa.gfx_partition_size = 4; 5257 adev->gds.oa.cs_partition_size = 1; 5258 } else { 5259 adev->gds.mem.gfx_partition_size = 1024; 5260 adev->gds.mem.cs_partition_size = 1024; 5261 5262 adev->gds.gws.gfx_partition_size = 16; 5263 adev->gds.gws.cs_partition_size = 16; 5264 5265 adev->gds.oa.gfx_partition_size = 4; 5266 adev->gds.oa.cs_partition_size = 4; 5267 } 5268 } 5269 5270 5271 int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, 5272 struct amdgpu_cu_info *cu_info) 5273 { 5274 int i, j, k, counter, active_cu_number = 0; 5275 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5276 5277 if (!adev || !cu_info) 5278 return -EINVAL; 5279 5280 memset(cu_info, 0, sizeof(*cu_info)); 5281 5282 mutex_lock(&adev->grbm_idx_mutex); 5283 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5284 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5285 mask = 1; 5286 ao_bitmap = 0; 5287 counter = 0; 5288 gfx_v7_0_select_se_sh(adev, i, j); 5289 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5290 cu_info->bitmap[i][j] = bitmap; 5291 5292 for (k = 0; k < 16; k ++) { 5293 if (bitmap & mask) { 5294 if (counter < 2) 5295 ao_bitmap |= mask; 5296 counter ++; 5297 } 5298 mask <<= 1; 5299 } 5300 active_cu_number += counter; 5301 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5302 } 5303 } 5304 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 5305 mutex_unlock(&adev->grbm_idx_mutex); 5306 5307 cu_info->number = active_cu_number; 5308 cu_info->ao_cu_mask = ao_cu_mask; 5309 5310 return 0; 5311 } 5312