1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_ih.h" 29 #include "amdgpu_gfx.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "cik_structs.h" 33 #include "atom.h" 34 #include "amdgpu_ucode.h" 35 #include "clearstate_ci.h" 36 37 #include "dce/dce_8_0_d.h" 38 #include "dce/dce_8_0_sh_mask.h" 39 40 #include "bif/bif_4_1_d.h" 41 #include "bif/bif_4_1_sh_mask.h" 42 43 #include "gca/gfx_7_0_d.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "gca/gfx_7_2_sh_mask.h" 46 47 #include "gmc/gmc_7_0_d.h" 48 #include "gmc/gmc_7_0_sh_mask.h" 49 50 #include "oss/oss_2_0_d.h" 51 #include "oss/oss_2_0_sh_mask.h" 52 53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */ 54 55 #define GFX7_NUM_GFX_RINGS 1 56 #define GFX7_MEC_HPD_SIZE 2048 57 58 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev); 59 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev); 60 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev); 61 62 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin"); 63 MODULE_FIRMWARE("amdgpu/bonaire_me.bin"); 64 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin"); 65 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin"); 66 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin"); 67 68 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin"); 69 MODULE_FIRMWARE("amdgpu/hawaii_me.bin"); 70 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin"); 71 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin"); 72 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin"); 73 74 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/kaveri_me.bin"); 76 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin"); 78 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin"); 80 81 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin"); 82 MODULE_FIRMWARE("amdgpu/kabini_me.bin"); 83 MODULE_FIRMWARE("amdgpu/kabini_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin"); 85 MODULE_FIRMWARE("amdgpu/kabini_mec.bin"); 86 87 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin"); 88 MODULE_FIRMWARE("amdgpu/mullins_me.bin"); 89 MODULE_FIRMWARE("amdgpu/mullins_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin"); 91 MODULE_FIRMWARE("amdgpu/mullins_mec.bin"); 92 93 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = 94 { 95 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0}, 96 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1}, 97 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2}, 98 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3}, 99 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4}, 100 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5}, 101 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6}, 102 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7}, 103 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8}, 104 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9}, 105 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10}, 106 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11}, 107 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12}, 108 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13}, 109 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14}, 110 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15} 111 }; 112 113 static const u32 spectre_rlc_save_restore_register_list[] = 114 { 115 (0x0e00 << 16) | (0xc12c >> 2), 116 0x00000000, 117 (0x0e00 << 16) | (0xc140 >> 2), 118 0x00000000, 119 (0x0e00 << 16) | (0xc150 >> 2), 120 0x00000000, 121 (0x0e00 << 16) | (0xc15c >> 2), 122 0x00000000, 123 (0x0e00 << 16) | (0xc168 >> 2), 124 0x00000000, 125 (0x0e00 << 16) | (0xc170 >> 2), 126 0x00000000, 127 (0x0e00 << 16) | (0xc178 >> 2), 128 0x00000000, 129 (0x0e00 << 16) | (0xc204 >> 2), 130 0x00000000, 131 (0x0e00 << 16) | (0xc2b4 >> 2), 132 0x00000000, 133 (0x0e00 << 16) | (0xc2b8 >> 2), 134 0x00000000, 135 (0x0e00 << 16) | (0xc2bc >> 2), 136 0x00000000, 137 (0x0e00 << 16) | (0xc2c0 >> 2), 138 0x00000000, 139 (0x0e00 << 16) | (0x8228 >> 2), 140 0x00000000, 141 (0x0e00 << 16) | (0x829c >> 2), 142 0x00000000, 143 (0x0e00 << 16) | (0x869c >> 2), 144 0x00000000, 145 (0x0600 << 16) | (0x98f4 >> 2), 146 0x00000000, 147 (0x0e00 << 16) | (0x98f8 >> 2), 148 0x00000000, 149 (0x0e00 << 16) | (0x9900 >> 2), 150 0x00000000, 151 (0x0e00 << 16) | (0xc260 >> 2), 152 0x00000000, 153 (0x0e00 << 16) | (0x90e8 >> 2), 154 0x00000000, 155 (0x0e00 << 16) | (0x3c000 >> 2), 156 0x00000000, 157 (0x0e00 << 16) | (0x3c00c >> 2), 158 0x00000000, 159 (0x0e00 << 16) | (0x8c1c >> 2), 160 0x00000000, 161 (0x0e00 << 16) | (0x9700 >> 2), 162 0x00000000, 163 (0x0e00 << 16) | (0xcd20 >> 2), 164 0x00000000, 165 (0x4e00 << 16) | (0xcd20 >> 2), 166 0x00000000, 167 (0x5e00 << 16) | (0xcd20 >> 2), 168 0x00000000, 169 (0x6e00 << 16) | (0xcd20 >> 2), 170 0x00000000, 171 (0x7e00 << 16) | (0xcd20 >> 2), 172 0x00000000, 173 (0x8e00 << 16) | (0xcd20 >> 2), 174 0x00000000, 175 (0x9e00 << 16) | (0xcd20 >> 2), 176 0x00000000, 177 (0xae00 << 16) | (0xcd20 >> 2), 178 0x00000000, 179 (0xbe00 << 16) | (0xcd20 >> 2), 180 0x00000000, 181 (0x0e00 << 16) | (0x89bc >> 2), 182 0x00000000, 183 (0x0e00 << 16) | (0x8900 >> 2), 184 0x00000000, 185 0x3, 186 (0x0e00 << 16) | (0xc130 >> 2), 187 0x00000000, 188 (0x0e00 << 16) | (0xc134 >> 2), 189 0x00000000, 190 (0x0e00 << 16) | (0xc1fc >> 2), 191 0x00000000, 192 (0x0e00 << 16) | (0xc208 >> 2), 193 0x00000000, 194 (0x0e00 << 16) | (0xc264 >> 2), 195 0x00000000, 196 (0x0e00 << 16) | (0xc268 >> 2), 197 0x00000000, 198 (0x0e00 << 16) | (0xc26c >> 2), 199 0x00000000, 200 (0x0e00 << 16) | (0xc270 >> 2), 201 0x00000000, 202 (0x0e00 << 16) | (0xc274 >> 2), 203 0x00000000, 204 (0x0e00 << 16) | (0xc278 >> 2), 205 0x00000000, 206 (0x0e00 << 16) | (0xc27c >> 2), 207 0x00000000, 208 (0x0e00 << 16) | (0xc280 >> 2), 209 0x00000000, 210 (0x0e00 << 16) | (0xc284 >> 2), 211 0x00000000, 212 (0x0e00 << 16) | (0xc288 >> 2), 213 0x00000000, 214 (0x0e00 << 16) | (0xc28c >> 2), 215 0x00000000, 216 (0x0e00 << 16) | (0xc290 >> 2), 217 0x00000000, 218 (0x0e00 << 16) | (0xc294 >> 2), 219 0x00000000, 220 (0x0e00 << 16) | (0xc298 >> 2), 221 0x00000000, 222 (0x0e00 << 16) | (0xc29c >> 2), 223 0x00000000, 224 (0x0e00 << 16) | (0xc2a0 >> 2), 225 0x00000000, 226 (0x0e00 << 16) | (0xc2a4 >> 2), 227 0x00000000, 228 (0x0e00 << 16) | (0xc2a8 >> 2), 229 0x00000000, 230 (0x0e00 << 16) | (0xc2ac >> 2), 231 0x00000000, 232 (0x0e00 << 16) | (0xc2b0 >> 2), 233 0x00000000, 234 (0x0e00 << 16) | (0x301d0 >> 2), 235 0x00000000, 236 (0x0e00 << 16) | (0x30238 >> 2), 237 0x00000000, 238 (0x0e00 << 16) | (0x30250 >> 2), 239 0x00000000, 240 (0x0e00 << 16) | (0x30254 >> 2), 241 0x00000000, 242 (0x0e00 << 16) | (0x30258 >> 2), 243 0x00000000, 244 (0x0e00 << 16) | (0x3025c >> 2), 245 0x00000000, 246 (0x4e00 << 16) | (0xc900 >> 2), 247 0x00000000, 248 (0x5e00 << 16) | (0xc900 >> 2), 249 0x00000000, 250 (0x6e00 << 16) | (0xc900 >> 2), 251 0x00000000, 252 (0x7e00 << 16) | (0xc900 >> 2), 253 0x00000000, 254 (0x8e00 << 16) | (0xc900 >> 2), 255 0x00000000, 256 (0x9e00 << 16) | (0xc900 >> 2), 257 0x00000000, 258 (0xae00 << 16) | (0xc900 >> 2), 259 0x00000000, 260 (0xbe00 << 16) | (0xc900 >> 2), 261 0x00000000, 262 (0x4e00 << 16) | (0xc904 >> 2), 263 0x00000000, 264 (0x5e00 << 16) | (0xc904 >> 2), 265 0x00000000, 266 (0x6e00 << 16) | (0xc904 >> 2), 267 0x00000000, 268 (0x7e00 << 16) | (0xc904 >> 2), 269 0x00000000, 270 (0x8e00 << 16) | (0xc904 >> 2), 271 0x00000000, 272 (0x9e00 << 16) | (0xc904 >> 2), 273 0x00000000, 274 (0xae00 << 16) | (0xc904 >> 2), 275 0x00000000, 276 (0xbe00 << 16) | (0xc904 >> 2), 277 0x00000000, 278 (0x4e00 << 16) | (0xc908 >> 2), 279 0x00000000, 280 (0x5e00 << 16) | (0xc908 >> 2), 281 0x00000000, 282 (0x6e00 << 16) | (0xc908 >> 2), 283 0x00000000, 284 (0x7e00 << 16) | (0xc908 >> 2), 285 0x00000000, 286 (0x8e00 << 16) | (0xc908 >> 2), 287 0x00000000, 288 (0x9e00 << 16) | (0xc908 >> 2), 289 0x00000000, 290 (0xae00 << 16) | (0xc908 >> 2), 291 0x00000000, 292 (0xbe00 << 16) | (0xc908 >> 2), 293 0x00000000, 294 (0x4e00 << 16) | (0xc90c >> 2), 295 0x00000000, 296 (0x5e00 << 16) | (0xc90c >> 2), 297 0x00000000, 298 (0x6e00 << 16) | (0xc90c >> 2), 299 0x00000000, 300 (0x7e00 << 16) | (0xc90c >> 2), 301 0x00000000, 302 (0x8e00 << 16) | (0xc90c >> 2), 303 0x00000000, 304 (0x9e00 << 16) | (0xc90c >> 2), 305 0x00000000, 306 (0xae00 << 16) | (0xc90c >> 2), 307 0x00000000, 308 (0xbe00 << 16) | (0xc90c >> 2), 309 0x00000000, 310 (0x4e00 << 16) | (0xc910 >> 2), 311 0x00000000, 312 (0x5e00 << 16) | (0xc910 >> 2), 313 0x00000000, 314 (0x6e00 << 16) | (0xc910 >> 2), 315 0x00000000, 316 (0x7e00 << 16) | (0xc910 >> 2), 317 0x00000000, 318 (0x8e00 << 16) | (0xc910 >> 2), 319 0x00000000, 320 (0x9e00 << 16) | (0xc910 >> 2), 321 0x00000000, 322 (0xae00 << 16) | (0xc910 >> 2), 323 0x00000000, 324 (0xbe00 << 16) | (0xc910 >> 2), 325 0x00000000, 326 (0x0e00 << 16) | (0xc99c >> 2), 327 0x00000000, 328 (0x0e00 << 16) | (0x9834 >> 2), 329 0x00000000, 330 (0x0000 << 16) | (0x30f00 >> 2), 331 0x00000000, 332 (0x0001 << 16) | (0x30f00 >> 2), 333 0x00000000, 334 (0x0000 << 16) | (0x30f04 >> 2), 335 0x00000000, 336 (0x0001 << 16) | (0x30f04 >> 2), 337 0x00000000, 338 (0x0000 << 16) | (0x30f08 >> 2), 339 0x00000000, 340 (0x0001 << 16) | (0x30f08 >> 2), 341 0x00000000, 342 (0x0000 << 16) | (0x30f0c >> 2), 343 0x00000000, 344 (0x0001 << 16) | (0x30f0c >> 2), 345 0x00000000, 346 (0x0600 << 16) | (0x9b7c >> 2), 347 0x00000000, 348 (0x0e00 << 16) | (0x8a14 >> 2), 349 0x00000000, 350 (0x0e00 << 16) | (0x8a18 >> 2), 351 0x00000000, 352 (0x0600 << 16) | (0x30a00 >> 2), 353 0x00000000, 354 (0x0e00 << 16) | (0x8bf0 >> 2), 355 0x00000000, 356 (0x0e00 << 16) | (0x8bcc >> 2), 357 0x00000000, 358 (0x0e00 << 16) | (0x8b24 >> 2), 359 0x00000000, 360 (0x0e00 << 16) | (0x30a04 >> 2), 361 0x00000000, 362 (0x0600 << 16) | (0x30a10 >> 2), 363 0x00000000, 364 (0x0600 << 16) | (0x30a14 >> 2), 365 0x00000000, 366 (0x0600 << 16) | (0x30a18 >> 2), 367 0x00000000, 368 (0x0600 << 16) | (0x30a2c >> 2), 369 0x00000000, 370 (0x0e00 << 16) | (0xc700 >> 2), 371 0x00000000, 372 (0x0e00 << 16) | (0xc704 >> 2), 373 0x00000000, 374 (0x0e00 << 16) | (0xc708 >> 2), 375 0x00000000, 376 (0x0e00 << 16) | (0xc768 >> 2), 377 0x00000000, 378 (0x0400 << 16) | (0xc770 >> 2), 379 0x00000000, 380 (0x0400 << 16) | (0xc774 >> 2), 381 0x00000000, 382 (0x0400 << 16) | (0xc778 >> 2), 383 0x00000000, 384 (0x0400 << 16) | (0xc77c >> 2), 385 0x00000000, 386 (0x0400 << 16) | (0xc780 >> 2), 387 0x00000000, 388 (0x0400 << 16) | (0xc784 >> 2), 389 0x00000000, 390 (0x0400 << 16) | (0xc788 >> 2), 391 0x00000000, 392 (0x0400 << 16) | (0xc78c >> 2), 393 0x00000000, 394 (0x0400 << 16) | (0xc798 >> 2), 395 0x00000000, 396 (0x0400 << 16) | (0xc79c >> 2), 397 0x00000000, 398 (0x0400 << 16) | (0xc7a0 >> 2), 399 0x00000000, 400 (0x0400 << 16) | (0xc7a4 >> 2), 401 0x00000000, 402 (0x0400 << 16) | (0xc7a8 >> 2), 403 0x00000000, 404 (0x0400 << 16) | (0xc7ac >> 2), 405 0x00000000, 406 (0x0400 << 16) | (0xc7b0 >> 2), 407 0x00000000, 408 (0x0400 << 16) | (0xc7b4 >> 2), 409 0x00000000, 410 (0x0e00 << 16) | (0x9100 >> 2), 411 0x00000000, 412 (0x0e00 << 16) | (0x3c010 >> 2), 413 0x00000000, 414 (0x0e00 << 16) | (0x92a8 >> 2), 415 0x00000000, 416 (0x0e00 << 16) | (0x92ac >> 2), 417 0x00000000, 418 (0x0e00 << 16) | (0x92b4 >> 2), 419 0x00000000, 420 (0x0e00 << 16) | (0x92b8 >> 2), 421 0x00000000, 422 (0x0e00 << 16) | (0x92bc >> 2), 423 0x00000000, 424 (0x0e00 << 16) | (0x92c0 >> 2), 425 0x00000000, 426 (0x0e00 << 16) | (0x92c4 >> 2), 427 0x00000000, 428 (0x0e00 << 16) | (0x92c8 >> 2), 429 0x00000000, 430 (0x0e00 << 16) | (0x92cc >> 2), 431 0x00000000, 432 (0x0e00 << 16) | (0x92d0 >> 2), 433 0x00000000, 434 (0x0e00 << 16) | (0x8c00 >> 2), 435 0x00000000, 436 (0x0e00 << 16) | (0x8c04 >> 2), 437 0x00000000, 438 (0x0e00 << 16) | (0x8c20 >> 2), 439 0x00000000, 440 (0x0e00 << 16) | (0x8c38 >> 2), 441 0x00000000, 442 (0x0e00 << 16) | (0x8c3c >> 2), 443 0x00000000, 444 (0x0e00 << 16) | (0xae00 >> 2), 445 0x00000000, 446 (0x0e00 << 16) | (0x9604 >> 2), 447 0x00000000, 448 (0x0e00 << 16) | (0xac08 >> 2), 449 0x00000000, 450 (0x0e00 << 16) | (0xac0c >> 2), 451 0x00000000, 452 (0x0e00 << 16) | (0xac10 >> 2), 453 0x00000000, 454 (0x0e00 << 16) | (0xac14 >> 2), 455 0x00000000, 456 (0x0e00 << 16) | (0xac58 >> 2), 457 0x00000000, 458 (0x0e00 << 16) | (0xac68 >> 2), 459 0x00000000, 460 (0x0e00 << 16) | (0xac6c >> 2), 461 0x00000000, 462 (0x0e00 << 16) | (0xac70 >> 2), 463 0x00000000, 464 (0x0e00 << 16) | (0xac74 >> 2), 465 0x00000000, 466 (0x0e00 << 16) | (0xac78 >> 2), 467 0x00000000, 468 (0x0e00 << 16) | (0xac7c >> 2), 469 0x00000000, 470 (0x0e00 << 16) | (0xac80 >> 2), 471 0x00000000, 472 (0x0e00 << 16) | (0xac84 >> 2), 473 0x00000000, 474 (0x0e00 << 16) | (0xac88 >> 2), 475 0x00000000, 476 (0x0e00 << 16) | (0xac8c >> 2), 477 0x00000000, 478 (0x0e00 << 16) | (0x970c >> 2), 479 0x00000000, 480 (0x0e00 << 16) | (0x9714 >> 2), 481 0x00000000, 482 (0x0e00 << 16) | (0x9718 >> 2), 483 0x00000000, 484 (0x0e00 << 16) | (0x971c >> 2), 485 0x00000000, 486 (0x0e00 << 16) | (0x31068 >> 2), 487 0x00000000, 488 (0x4e00 << 16) | (0x31068 >> 2), 489 0x00000000, 490 (0x5e00 << 16) | (0x31068 >> 2), 491 0x00000000, 492 (0x6e00 << 16) | (0x31068 >> 2), 493 0x00000000, 494 (0x7e00 << 16) | (0x31068 >> 2), 495 0x00000000, 496 (0x8e00 << 16) | (0x31068 >> 2), 497 0x00000000, 498 (0x9e00 << 16) | (0x31068 >> 2), 499 0x00000000, 500 (0xae00 << 16) | (0x31068 >> 2), 501 0x00000000, 502 (0xbe00 << 16) | (0x31068 >> 2), 503 0x00000000, 504 (0x0e00 << 16) | (0xcd10 >> 2), 505 0x00000000, 506 (0x0e00 << 16) | (0xcd14 >> 2), 507 0x00000000, 508 (0x0e00 << 16) | (0x88b0 >> 2), 509 0x00000000, 510 (0x0e00 << 16) | (0x88b4 >> 2), 511 0x00000000, 512 (0x0e00 << 16) | (0x88b8 >> 2), 513 0x00000000, 514 (0x0e00 << 16) | (0x88bc >> 2), 515 0x00000000, 516 (0x0400 << 16) | (0x89c0 >> 2), 517 0x00000000, 518 (0x0e00 << 16) | (0x88c4 >> 2), 519 0x00000000, 520 (0x0e00 << 16) | (0x88c8 >> 2), 521 0x00000000, 522 (0x0e00 << 16) | (0x88d0 >> 2), 523 0x00000000, 524 (0x0e00 << 16) | (0x88d4 >> 2), 525 0x00000000, 526 (0x0e00 << 16) | (0x88d8 >> 2), 527 0x00000000, 528 (0x0e00 << 16) | (0x8980 >> 2), 529 0x00000000, 530 (0x0e00 << 16) | (0x30938 >> 2), 531 0x00000000, 532 (0x0e00 << 16) | (0x3093c >> 2), 533 0x00000000, 534 (0x0e00 << 16) | (0x30940 >> 2), 535 0x00000000, 536 (0x0e00 << 16) | (0x89a0 >> 2), 537 0x00000000, 538 (0x0e00 << 16) | (0x30900 >> 2), 539 0x00000000, 540 (0x0e00 << 16) | (0x30904 >> 2), 541 0x00000000, 542 (0x0e00 << 16) | (0x89b4 >> 2), 543 0x00000000, 544 (0x0e00 << 16) | (0x3c210 >> 2), 545 0x00000000, 546 (0x0e00 << 16) | (0x3c214 >> 2), 547 0x00000000, 548 (0x0e00 << 16) | (0x3c218 >> 2), 549 0x00000000, 550 (0x0e00 << 16) | (0x8904 >> 2), 551 0x00000000, 552 0x5, 553 (0x0e00 << 16) | (0x8c28 >> 2), 554 (0x0e00 << 16) | (0x8c2c >> 2), 555 (0x0e00 << 16) | (0x8c30 >> 2), 556 (0x0e00 << 16) | (0x8c34 >> 2), 557 (0x0e00 << 16) | (0x9600 >> 2), 558 }; 559 560 static const u32 kalindi_rlc_save_restore_register_list[] = 561 { 562 (0x0e00 << 16) | (0xc12c >> 2), 563 0x00000000, 564 (0x0e00 << 16) | (0xc140 >> 2), 565 0x00000000, 566 (0x0e00 << 16) | (0xc150 >> 2), 567 0x00000000, 568 (0x0e00 << 16) | (0xc15c >> 2), 569 0x00000000, 570 (0x0e00 << 16) | (0xc168 >> 2), 571 0x00000000, 572 (0x0e00 << 16) | (0xc170 >> 2), 573 0x00000000, 574 (0x0e00 << 16) | (0xc204 >> 2), 575 0x00000000, 576 (0x0e00 << 16) | (0xc2b4 >> 2), 577 0x00000000, 578 (0x0e00 << 16) | (0xc2b8 >> 2), 579 0x00000000, 580 (0x0e00 << 16) | (0xc2bc >> 2), 581 0x00000000, 582 (0x0e00 << 16) | (0xc2c0 >> 2), 583 0x00000000, 584 (0x0e00 << 16) | (0x8228 >> 2), 585 0x00000000, 586 (0x0e00 << 16) | (0x829c >> 2), 587 0x00000000, 588 (0x0e00 << 16) | (0x869c >> 2), 589 0x00000000, 590 (0x0600 << 16) | (0x98f4 >> 2), 591 0x00000000, 592 (0x0e00 << 16) | (0x98f8 >> 2), 593 0x00000000, 594 (0x0e00 << 16) | (0x9900 >> 2), 595 0x00000000, 596 (0x0e00 << 16) | (0xc260 >> 2), 597 0x00000000, 598 (0x0e00 << 16) | (0x90e8 >> 2), 599 0x00000000, 600 (0x0e00 << 16) | (0x3c000 >> 2), 601 0x00000000, 602 (0x0e00 << 16) | (0x3c00c >> 2), 603 0x00000000, 604 (0x0e00 << 16) | (0x8c1c >> 2), 605 0x00000000, 606 (0x0e00 << 16) | (0x9700 >> 2), 607 0x00000000, 608 (0x0e00 << 16) | (0xcd20 >> 2), 609 0x00000000, 610 (0x4e00 << 16) | (0xcd20 >> 2), 611 0x00000000, 612 (0x5e00 << 16) | (0xcd20 >> 2), 613 0x00000000, 614 (0x6e00 << 16) | (0xcd20 >> 2), 615 0x00000000, 616 (0x7e00 << 16) | (0xcd20 >> 2), 617 0x00000000, 618 (0x0e00 << 16) | (0x89bc >> 2), 619 0x00000000, 620 (0x0e00 << 16) | (0x8900 >> 2), 621 0x00000000, 622 0x3, 623 (0x0e00 << 16) | (0xc130 >> 2), 624 0x00000000, 625 (0x0e00 << 16) | (0xc134 >> 2), 626 0x00000000, 627 (0x0e00 << 16) | (0xc1fc >> 2), 628 0x00000000, 629 (0x0e00 << 16) | (0xc208 >> 2), 630 0x00000000, 631 (0x0e00 << 16) | (0xc264 >> 2), 632 0x00000000, 633 (0x0e00 << 16) | (0xc268 >> 2), 634 0x00000000, 635 (0x0e00 << 16) | (0xc26c >> 2), 636 0x00000000, 637 (0x0e00 << 16) | (0xc270 >> 2), 638 0x00000000, 639 (0x0e00 << 16) | (0xc274 >> 2), 640 0x00000000, 641 (0x0e00 << 16) | (0xc28c >> 2), 642 0x00000000, 643 (0x0e00 << 16) | (0xc290 >> 2), 644 0x00000000, 645 (0x0e00 << 16) | (0xc294 >> 2), 646 0x00000000, 647 (0x0e00 << 16) | (0xc298 >> 2), 648 0x00000000, 649 (0x0e00 << 16) | (0xc2a0 >> 2), 650 0x00000000, 651 (0x0e00 << 16) | (0xc2a4 >> 2), 652 0x00000000, 653 (0x0e00 << 16) | (0xc2a8 >> 2), 654 0x00000000, 655 (0x0e00 << 16) | (0xc2ac >> 2), 656 0x00000000, 657 (0x0e00 << 16) | (0x301d0 >> 2), 658 0x00000000, 659 (0x0e00 << 16) | (0x30238 >> 2), 660 0x00000000, 661 (0x0e00 << 16) | (0x30250 >> 2), 662 0x00000000, 663 (0x0e00 << 16) | (0x30254 >> 2), 664 0x00000000, 665 (0x0e00 << 16) | (0x30258 >> 2), 666 0x00000000, 667 (0x0e00 << 16) | (0x3025c >> 2), 668 0x00000000, 669 (0x4e00 << 16) | (0xc900 >> 2), 670 0x00000000, 671 (0x5e00 << 16) | (0xc900 >> 2), 672 0x00000000, 673 (0x6e00 << 16) | (0xc900 >> 2), 674 0x00000000, 675 (0x7e00 << 16) | (0xc900 >> 2), 676 0x00000000, 677 (0x4e00 << 16) | (0xc904 >> 2), 678 0x00000000, 679 (0x5e00 << 16) | (0xc904 >> 2), 680 0x00000000, 681 (0x6e00 << 16) | (0xc904 >> 2), 682 0x00000000, 683 (0x7e00 << 16) | (0xc904 >> 2), 684 0x00000000, 685 (0x4e00 << 16) | (0xc908 >> 2), 686 0x00000000, 687 (0x5e00 << 16) | (0xc908 >> 2), 688 0x00000000, 689 (0x6e00 << 16) | (0xc908 >> 2), 690 0x00000000, 691 (0x7e00 << 16) | (0xc908 >> 2), 692 0x00000000, 693 (0x4e00 << 16) | (0xc90c >> 2), 694 0x00000000, 695 (0x5e00 << 16) | (0xc90c >> 2), 696 0x00000000, 697 (0x6e00 << 16) | (0xc90c >> 2), 698 0x00000000, 699 (0x7e00 << 16) | (0xc90c >> 2), 700 0x00000000, 701 (0x4e00 << 16) | (0xc910 >> 2), 702 0x00000000, 703 (0x5e00 << 16) | (0xc910 >> 2), 704 0x00000000, 705 (0x6e00 << 16) | (0xc910 >> 2), 706 0x00000000, 707 (0x7e00 << 16) | (0xc910 >> 2), 708 0x00000000, 709 (0x0e00 << 16) | (0xc99c >> 2), 710 0x00000000, 711 (0x0e00 << 16) | (0x9834 >> 2), 712 0x00000000, 713 (0x0000 << 16) | (0x30f00 >> 2), 714 0x00000000, 715 (0x0000 << 16) | (0x30f04 >> 2), 716 0x00000000, 717 (0x0000 << 16) | (0x30f08 >> 2), 718 0x00000000, 719 (0x0000 << 16) | (0x30f0c >> 2), 720 0x00000000, 721 (0x0600 << 16) | (0x9b7c >> 2), 722 0x00000000, 723 (0x0e00 << 16) | (0x8a14 >> 2), 724 0x00000000, 725 (0x0e00 << 16) | (0x8a18 >> 2), 726 0x00000000, 727 (0x0600 << 16) | (0x30a00 >> 2), 728 0x00000000, 729 (0x0e00 << 16) | (0x8bf0 >> 2), 730 0x00000000, 731 (0x0e00 << 16) | (0x8bcc >> 2), 732 0x00000000, 733 (0x0e00 << 16) | (0x8b24 >> 2), 734 0x00000000, 735 (0x0e00 << 16) | (0x30a04 >> 2), 736 0x00000000, 737 (0x0600 << 16) | (0x30a10 >> 2), 738 0x00000000, 739 (0x0600 << 16) | (0x30a14 >> 2), 740 0x00000000, 741 (0x0600 << 16) | (0x30a18 >> 2), 742 0x00000000, 743 (0x0600 << 16) | (0x30a2c >> 2), 744 0x00000000, 745 (0x0e00 << 16) | (0xc700 >> 2), 746 0x00000000, 747 (0x0e00 << 16) | (0xc704 >> 2), 748 0x00000000, 749 (0x0e00 << 16) | (0xc708 >> 2), 750 0x00000000, 751 (0x0e00 << 16) | (0xc768 >> 2), 752 0x00000000, 753 (0x0400 << 16) | (0xc770 >> 2), 754 0x00000000, 755 (0x0400 << 16) | (0xc774 >> 2), 756 0x00000000, 757 (0x0400 << 16) | (0xc798 >> 2), 758 0x00000000, 759 (0x0400 << 16) | (0xc79c >> 2), 760 0x00000000, 761 (0x0e00 << 16) | (0x9100 >> 2), 762 0x00000000, 763 (0x0e00 << 16) | (0x3c010 >> 2), 764 0x00000000, 765 (0x0e00 << 16) | (0x8c00 >> 2), 766 0x00000000, 767 (0x0e00 << 16) | (0x8c04 >> 2), 768 0x00000000, 769 (0x0e00 << 16) | (0x8c20 >> 2), 770 0x00000000, 771 (0x0e00 << 16) | (0x8c38 >> 2), 772 0x00000000, 773 (0x0e00 << 16) | (0x8c3c >> 2), 774 0x00000000, 775 (0x0e00 << 16) | (0xae00 >> 2), 776 0x00000000, 777 (0x0e00 << 16) | (0x9604 >> 2), 778 0x00000000, 779 (0x0e00 << 16) | (0xac08 >> 2), 780 0x00000000, 781 (0x0e00 << 16) | (0xac0c >> 2), 782 0x00000000, 783 (0x0e00 << 16) | (0xac10 >> 2), 784 0x00000000, 785 (0x0e00 << 16) | (0xac14 >> 2), 786 0x00000000, 787 (0x0e00 << 16) | (0xac58 >> 2), 788 0x00000000, 789 (0x0e00 << 16) | (0xac68 >> 2), 790 0x00000000, 791 (0x0e00 << 16) | (0xac6c >> 2), 792 0x00000000, 793 (0x0e00 << 16) | (0xac70 >> 2), 794 0x00000000, 795 (0x0e00 << 16) | (0xac74 >> 2), 796 0x00000000, 797 (0x0e00 << 16) | (0xac78 >> 2), 798 0x00000000, 799 (0x0e00 << 16) | (0xac7c >> 2), 800 0x00000000, 801 (0x0e00 << 16) | (0xac80 >> 2), 802 0x00000000, 803 (0x0e00 << 16) | (0xac84 >> 2), 804 0x00000000, 805 (0x0e00 << 16) | (0xac88 >> 2), 806 0x00000000, 807 (0x0e00 << 16) | (0xac8c >> 2), 808 0x00000000, 809 (0x0e00 << 16) | (0x970c >> 2), 810 0x00000000, 811 (0x0e00 << 16) | (0x9714 >> 2), 812 0x00000000, 813 (0x0e00 << 16) | (0x9718 >> 2), 814 0x00000000, 815 (0x0e00 << 16) | (0x971c >> 2), 816 0x00000000, 817 (0x0e00 << 16) | (0x31068 >> 2), 818 0x00000000, 819 (0x4e00 << 16) | (0x31068 >> 2), 820 0x00000000, 821 (0x5e00 << 16) | (0x31068 >> 2), 822 0x00000000, 823 (0x6e00 << 16) | (0x31068 >> 2), 824 0x00000000, 825 (0x7e00 << 16) | (0x31068 >> 2), 826 0x00000000, 827 (0x0e00 << 16) | (0xcd10 >> 2), 828 0x00000000, 829 (0x0e00 << 16) | (0xcd14 >> 2), 830 0x00000000, 831 (0x0e00 << 16) | (0x88b0 >> 2), 832 0x00000000, 833 (0x0e00 << 16) | (0x88b4 >> 2), 834 0x00000000, 835 (0x0e00 << 16) | (0x88b8 >> 2), 836 0x00000000, 837 (0x0e00 << 16) | (0x88bc >> 2), 838 0x00000000, 839 (0x0400 << 16) | (0x89c0 >> 2), 840 0x00000000, 841 (0x0e00 << 16) | (0x88c4 >> 2), 842 0x00000000, 843 (0x0e00 << 16) | (0x88c8 >> 2), 844 0x00000000, 845 (0x0e00 << 16) | (0x88d0 >> 2), 846 0x00000000, 847 (0x0e00 << 16) | (0x88d4 >> 2), 848 0x00000000, 849 (0x0e00 << 16) | (0x88d8 >> 2), 850 0x00000000, 851 (0x0e00 << 16) | (0x8980 >> 2), 852 0x00000000, 853 (0x0e00 << 16) | (0x30938 >> 2), 854 0x00000000, 855 (0x0e00 << 16) | (0x3093c >> 2), 856 0x00000000, 857 (0x0e00 << 16) | (0x30940 >> 2), 858 0x00000000, 859 (0x0e00 << 16) | (0x89a0 >> 2), 860 0x00000000, 861 (0x0e00 << 16) | (0x30900 >> 2), 862 0x00000000, 863 (0x0e00 << 16) | (0x30904 >> 2), 864 0x00000000, 865 (0x0e00 << 16) | (0x89b4 >> 2), 866 0x00000000, 867 (0x0e00 << 16) | (0x3e1fc >> 2), 868 0x00000000, 869 (0x0e00 << 16) | (0x3c210 >> 2), 870 0x00000000, 871 (0x0e00 << 16) | (0x3c214 >> 2), 872 0x00000000, 873 (0x0e00 << 16) | (0x3c218 >> 2), 874 0x00000000, 875 (0x0e00 << 16) | (0x8904 >> 2), 876 0x00000000, 877 0x5, 878 (0x0e00 << 16) | (0x8c28 >> 2), 879 (0x0e00 << 16) | (0x8c2c >> 2), 880 (0x0e00 << 16) | (0x8c30 >> 2), 881 (0x0e00 << 16) | (0x8c34 >> 2), 882 (0x0e00 << 16) | (0x9600 >> 2), 883 }; 884 885 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 886 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 887 static void gfx_v7_0_init_pg(struct amdgpu_device *adev); 888 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); 889 890 /* 891 * Core functions 892 */ 893 /** 894 * gfx_v7_0_init_microcode - load ucode images from disk 895 * 896 * @adev: amdgpu_device pointer 897 * 898 * Use the firmware interface to load the ucode images into 899 * the driver (not loaded into hw). 900 * Returns 0 on success, error on failure. 901 */ 902 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) 903 { 904 const char *chip_name; 905 char fw_name[30]; 906 int err; 907 908 DRM_DEBUG("\n"); 909 910 switch (adev->asic_type) { 911 case CHIP_BONAIRE: 912 chip_name = "bonaire"; 913 break; 914 case CHIP_HAWAII: 915 chip_name = "hawaii"; 916 break; 917 case CHIP_KAVERI: 918 chip_name = "kaveri"; 919 break; 920 case CHIP_KABINI: 921 chip_name = "kabini"; 922 break; 923 case CHIP_MULLINS: 924 chip_name = "mullins"; 925 break; 926 default: BUG(); 927 } 928 929 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 931 if (err) 932 goto out; 933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 934 if (err) 935 goto out; 936 937 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 939 if (err) 940 goto out; 941 err = amdgpu_ucode_validate(adev->gfx.me_fw); 942 if (err) 943 goto out; 944 945 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 947 if (err) 948 goto out; 949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 950 if (err) 951 goto out; 952 953 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 955 if (err) 956 goto out; 957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 958 if (err) 959 goto out; 960 961 if (adev->asic_type == CHIP_KAVERI) { 962 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 964 if (err) 965 goto out; 966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 967 if (err) 968 goto out; 969 } 970 971 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 972 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 973 if (err) 974 goto out; 975 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 976 977 out: 978 if (err) { 979 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name); 980 release_firmware(adev->gfx.pfp_fw); 981 adev->gfx.pfp_fw = NULL; 982 release_firmware(adev->gfx.me_fw); 983 adev->gfx.me_fw = NULL; 984 release_firmware(adev->gfx.ce_fw); 985 adev->gfx.ce_fw = NULL; 986 release_firmware(adev->gfx.mec_fw); 987 adev->gfx.mec_fw = NULL; 988 release_firmware(adev->gfx.mec2_fw); 989 adev->gfx.mec2_fw = NULL; 990 release_firmware(adev->gfx.rlc_fw); 991 adev->gfx.rlc_fw = NULL; 992 } 993 return err; 994 } 995 996 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev) 997 { 998 release_firmware(adev->gfx.pfp_fw); 999 adev->gfx.pfp_fw = NULL; 1000 release_firmware(adev->gfx.me_fw); 1001 adev->gfx.me_fw = NULL; 1002 release_firmware(adev->gfx.ce_fw); 1003 adev->gfx.ce_fw = NULL; 1004 release_firmware(adev->gfx.mec_fw); 1005 adev->gfx.mec_fw = NULL; 1006 release_firmware(adev->gfx.mec2_fw); 1007 adev->gfx.mec2_fw = NULL; 1008 release_firmware(adev->gfx.rlc_fw); 1009 adev->gfx.rlc_fw = NULL; 1010 } 1011 1012 /** 1013 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table 1014 * 1015 * @adev: amdgpu_device pointer 1016 * 1017 * Starting with SI, the tiling setup is done globally in a 1018 * set of 32 tiling modes. Rather than selecting each set of 1019 * parameters per surface as on older asics, we just select 1020 * which index in the tiling table we want to use, and the 1021 * surface uses those parameters (CIK). 1022 */ 1023 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) 1024 { 1025 const u32 num_tile_mode_states = 1026 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 1027 const u32 num_secondary_tile_mode_states = 1028 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 1029 u32 reg_offset, split_equal_to_row_size; 1030 uint32_t *tile, *macrotile; 1031 1032 tile = adev->gfx.config.tile_mode_array; 1033 macrotile = adev->gfx.config.macrotile_mode_array; 1034 1035 switch (adev->gfx.config.mem_row_size_in_kb) { 1036 case 1: 1037 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 1038 break; 1039 case 2: 1040 default: 1041 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 1042 break; 1043 case 4: 1044 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 1045 break; 1046 } 1047 1048 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1049 tile[reg_offset] = 0; 1050 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1051 macrotile[reg_offset] = 0; 1052 1053 switch (adev->asic_type) { 1054 case CHIP_BONAIRE: 1055 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1056 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1058 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1059 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1060 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1063 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1067 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1071 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1072 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1073 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1074 TILE_SPLIT(split_equal_to_row_size)); 1075 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1076 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1077 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1078 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1079 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1080 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1081 TILE_SPLIT(split_equal_to_row_size)); 1082 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1083 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1084 PIPE_CONFIG(ADDR_SURF_P4_16x16)); 1085 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1086 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1088 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1089 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1090 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1092 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1093 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1094 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1095 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1096 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1097 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1098 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1100 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1101 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1102 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1104 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1105 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1106 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1108 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1109 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1110 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1111 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1112 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1113 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1114 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1115 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1116 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1117 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1118 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1119 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1120 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1121 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1122 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1123 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1124 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1125 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1126 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1127 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1128 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1129 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1130 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1131 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1132 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1133 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1134 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1135 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1136 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1137 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1138 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1139 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1141 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1142 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1143 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1144 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1145 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1146 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1147 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1148 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1149 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1150 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1152 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1153 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1154 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1155 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1156 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1157 1158 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1161 NUM_BANKS(ADDR_SURF_16_BANK)); 1162 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1165 NUM_BANKS(ADDR_SURF_16_BANK)); 1166 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1169 NUM_BANKS(ADDR_SURF_16_BANK)); 1170 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1173 NUM_BANKS(ADDR_SURF_16_BANK)); 1174 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1177 NUM_BANKS(ADDR_SURF_16_BANK)); 1178 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1181 NUM_BANKS(ADDR_SURF_8_BANK)); 1182 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1185 NUM_BANKS(ADDR_SURF_4_BANK)); 1186 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1189 NUM_BANKS(ADDR_SURF_16_BANK)); 1190 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1193 NUM_BANKS(ADDR_SURF_16_BANK)); 1194 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1197 NUM_BANKS(ADDR_SURF_16_BANK)); 1198 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1201 NUM_BANKS(ADDR_SURF_16_BANK)); 1202 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1205 NUM_BANKS(ADDR_SURF_16_BANK)); 1206 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1209 NUM_BANKS(ADDR_SURF_8_BANK)); 1210 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1211 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1212 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1213 NUM_BANKS(ADDR_SURF_4_BANK)); 1214 1215 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1216 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1217 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1218 if (reg_offset != 7) 1219 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1220 break; 1221 case CHIP_HAWAII: 1222 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1223 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1224 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1225 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1226 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1227 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1229 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1230 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1231 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1232 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1233 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1234 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1235 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1237 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1238 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1241 TILE_SPLIT(split_equal_to_row_size)); 1242 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1243 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1244 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1245 TILE_SPLIT(split_equal_to_row_size)); 1246 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1247 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1249 TILE_SPLIT(split_equal_to_row_size)); 1250 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1251 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1252 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1253 TILE_SPLIT(split_equal_to_row_size)); 1254 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1256 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1258 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1259 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1260 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1261 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1262 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1263 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1264 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1265 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1266 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1267 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | 1268 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1269 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1270 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1271 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1272 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1273 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1274 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1275 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1276 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1278 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1279 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1280 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1282 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1283 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1284 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1286 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1287 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1288 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1290 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1291 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1292 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1294 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1295 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1297 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1298 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1299 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1301 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1302 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1303 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1305 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1306 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1307 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1309 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1310 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1313 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1314 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1315 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1317 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1318 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1319 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1321 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1322 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1323 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1325 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1326 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1327 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1328 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1329 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1330 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1332 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1333 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1334 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1336 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1337 PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1338 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1340 1341 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1342 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1343 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1344 NUM_BANKS(ADDR_SURF_16_BANK)); 1345 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1346 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1347 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1348 NUM_BANKS(ADDR_SURF_16_BANK)); 1349 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1352 NUM_BANKS(ADDR_SURF_16_BANK)); 1353 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1355 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1356 NUM_BANKS(ADDR_SURF_16_BANK)); 1357 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1360 NUM_BANKS(ADDR_SURF_8_BANK)); 1361 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1364 NUM_BANKS(ADDR_SURF_4_BANK)); 1365 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1366 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1367 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1368 NUM_BANKS(ADDR_SURF_4_BANK)); 1369 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1372 NUM_BANKS(ADDR_SURF_16_BANK)); 1373 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1376 NUM_BANKS(ADDR_SURF_16_BANK)); 1377 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1380 NUM_BANKS(ADDR_SURF_16_BANK)); 1381 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1384 NUM_BANKS(ADDR_SURF_8_BANK)); 1385 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1388 NUM_BANKS(ADDR_SURF_16_BANK)); 1389 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1392 NUM_BANKS(ADDR_SURF_8_BANK)); 1393 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1394 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1395 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1396 NUM_BANKS(ADDR_SURF_4_BANK)); 1397 1398 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1399 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1400 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1401 if (reg_offset != 7) 1402 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1403 break; 1404 case CHIP_KABINI: 1405 case CHIP_KAVERI: 1406 case CHIP_MULLINS: 1407 default: 1408 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1409 PIPE_CONFIG(ADDR_SURF_P2) | 1410 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1411 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1412 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1413 PIPE_CONFIG(ADDR_SURF_P2) | 1414 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1416 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1417 PIPE_CONFIG(ADDR_SURF_P2) | 1418 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1419 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1420 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1421 PIPE_CONFIG(ADDR_SURF_P2) | 1422 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1423 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1424 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1425 PIPE_CONFIG(ADDR_SURF_P2) | 1426 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1427 TILE_SPLIT(split_equal_to_row_size)); 1428 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1429 PIPE_CONFIG(ADDR_SURF_P2) | 1430 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1431 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1432 PIPE_CONFIG(ADDR_SURF_P2) | 1433 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | 1434 TILE_SPLIT(split_equal_to_row_size)); 1435 tile[7] = (TILE_SPLIT(split_equal_to_row_size)); 1436 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1437 PIPE_CONFIG(ADDR_SURF_P2)); 1438 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1439 PIPE_CONFIG(ADDR_SURF_P2) | 1440 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); 1441 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1442 PIPE_CONFIG(ADDR_SURF_P2) | 1443 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1444 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1445 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1446 PIPE_CONFIG(ADDR_SURF_P2) | 1447 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1448 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1449 tile[12] = (TILE_SPLIT(split_equal_to_row_size)); 1450 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1451 PIPE_CONFIG(ADDR_SURF_P2) | 1452 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); 1453 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1454 PIPE_CONFIG(ADDR_SURF_P2) | 1455 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1457 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1458 PIPE_CONFIG(ADDR_SURF_P2) | 1459 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1461 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1462 PIPE_CONFIG(ADDR_SURF_P2) | 1463 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1464 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1465 tile[17] = (TILE_SPLIT(split_equal_to_row_size)); 1466 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1467 PIPE_CONFIG(ADDR_SURF_P2) | 1468 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1469 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1470 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1471 PIPE_CONFIG(ADDR_SURF_P2) | 1472 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); 1473 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1474 PIPE_CONFIG(ADDR_SURF_P2) | 1475 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1476 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1477 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1478 PIPE_CONFIG(ADDR_SURF_P2) | 1479 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1480 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1481 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1482 PIPE_CONFIG(ADDR_SURF_P2) | 1483 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1484 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1485 tile[23] = (TILE_SPLIT(split_equal_to_row_size)); 1486 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1487 PIPE_CONFIG(ADDR_SURF_P2) | 1488 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1489 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1490 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1491 PIPE_CONFIG(ADDR_SURF_P2) | 1492 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1493 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1494 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1495 PIPE_CONFIG(ADDR_SURF_P2) | 1496 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1497 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1498 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1499 PIPE_CONFIG(ADDR_SURF_P2) | 1500 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); 1501 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1502 PIPE_CONFIG(ADDR_SURF_P2) | 1503 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1504 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1505 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1506 PIPE_CONFIG(ADDR_SURF_P2) | 1507 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1508 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1509 tile[30] = (TILE_SPLIT(split_equal_to_row_size)); 1510 1511 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1514 NUM_BANKS(ADDR_SURF_8_BANK)); 1515 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1518 NUM_BANKS(ADDR_SURF_8_BANK)); 1519 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1522 NUM_BANKS(ADDR_SURF_8_BANK)); 1523 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1526 NUM_BANKS(ADDR_SURF_8_BANK)); 1527 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1530 NUM_BANKS(ADDR_SURF_8_BANK)); 1531 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1533 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1534 NUM_BANKS(ADDR_SURF_8_BANK)); 1535 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1538 NUM_BANKS(ADDR_SURF_8_BANK)); 1539 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1541 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1542 NUM_BANKS(ADDR_SURF_16_BANK)); 1543 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | 1544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1546 NUM_BANKS(ADDR_SURF_16_BANK)); 1547 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1550 NUM_BANKS(ADDR_SURF_16_BANK)); 1551 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1554 NUM_BANKS(ADDR_SURF_16_BANK)); 1555 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1558 NUM_BANKS(ADDR_SURF_16_BANK)); 1559 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 1562 NUM_BANKS(ADDR_SURF_16_BANK)); 1563 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1564 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1565 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1566 NUM_BANKS(ADDR_SURF_8_BANK)); 1567 1568 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1569 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]); 1570 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) 1571 if (reg_offset != 7) 1572 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]); 1573 break; 1574 } 1575 } 1576 1577 /** 1578 * gfx_v7_0_select_se_sh - select which SE, SH to address 1579 * 1580 * @adev: amdgpu_device pointer 1581 * @se_num: shader engine to address 1582 * @sh_num: sh block to address 1583 * 1584 * Select which SE, SH combinations to address. Certain 1585 * registers are instanced per SE or SH. 0xffffffff means 1586 * broadcast to all SEs or SHs (CIK). 1587 */ 1588 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1589 u32 se_num, u32 sh_num, u32 instance) 1590 { 1591 u32 data; 1592 1593 if (instance == 0xffffffff) 1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1595 else 1596 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1597 1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1599 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1600 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1601 else if (se_num == 0xffffffff) 1602 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1603 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1604 else if (sh_num == 0xffffffff) 1605 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1606 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1607 else 1608 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1609 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1610 WREG32(mmGRBM_GFX_INDEX, data); 1611 } 1612 1613 /** 1614 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs 1615 * 1616 * @adev: amdgpu_device pointer 1617 * 1618 * Calculates the bitmask of enabled RBs (CIK). 1619 * Returns the enabled RB bitmask. 1620 */ 1621 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1622 { 1623 u32 data, mask; 1624 1625 data = RREG32(mmCC_RB_BACKEND_DISABLE); 1626 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1627 1628 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1629 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1630 1631 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1632 adev->gfx.config.max_sh_per_se); 1633 1634 return (~data) & mask; 1635 } 1636 1637 static void 1638 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) 1639 { 1640 switch (adev->asic_type) { 1641 case CHIP_BONAIRE: 1642 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) | 1643 SE_XSEL(1) | SE_YSEL(1); 1644 *rconf1 |= 0x0; 1645 break; 1646 case CHIP_HAWAII: 1647 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) | 1648 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) | 1649 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) | 1650 SE_YSEL(3); 1651 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) | 1652 SE_PAIR_YSEL(2); 1653 break; 1654 case CHIP_KAVERI: 1655 *rconf |= RB_MAP_PKR0(2); 1656 *rconf1 |= 0x0; 1657 break; 1658 case CHIP_KABINI: 1659 case CHIP_MULLINS: 1660 *rconf |= 0x0; 1661 *rconf1 |= 0x0; 1662 break; 1663 default: 1664 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1665 break; 1666 } 1667 } 1668 1669 static void 1670 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1671 u32 raster_config, u32 raster_config_1, 1672 unsigned rb_mask, unsigned num_rb) 1673 { 1674 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1675 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1676 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1677 unsigned rb_per_se = num_rb / num_se; 1678 unsigned se_mask[4]; 1679 unsigned se; 1680 1681 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1682 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1683 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1684 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1685 1686 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1687 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1688 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1689 1690 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 1691 (!se_mask[2] && !se_mask[3]))) { 1692 raster_config_1 &= ~SE_PAIR_MAP_MASK; 1693 1694 if (!se_mask[0] && !se_mask[1]) { 1695 raster_config_1 |= 1696 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3); 1697 } else { 1698 raster_config_1 |= 1699 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0); 1700 } 1701 } 1702 1703 for (se = 0; se < num_se; se++) { 1704 unsigned raster_config_se = raster_config; 1705 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1706 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1707 int idx = (se / 2) * 2; 1708 1709 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1710 raster_config_se &= ~SE_MAP_MASK; 1711 1712 if (!se_mask[idx]) { 1713 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3); 1714 } else { 1715 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0); 1716 } 1717 } 1718 1719 pkr0_mask &= rb_mask; 1720 pkr1_mask &= rb_mask; 1721 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1722 raster_config_se &= ~PKR_MAP_MASK; 1723 1724 if (!pkr0_mask) { 1725 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3); 1726 } else { 1727 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0); 1728 } 1729 } 1730 1731 if (rb_per_se >= 2) { 1732 unsigned rb0_mask = 1 << (se * rb_per_se); 1733 unsigned rb1_mask = rb0_mask << 1; 1734 1735 rb0_mask &= rb_mask; 1736 rb1_mask &= rb_mask; 1737 if (!rb0_mask || !rb1_mask) { 1738 raster_config_se &= ~RB_MAP_PKR0_MASK; 1739 1740 if (!rb0_mask) { 1741 raster_config_se |= 1742 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3); 1743 } else { 1744 raster_config_se |= 1745 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0); 1746 } 1747 } 1748 1749 if (rb_per_se > 2) { 1750 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1751 rb1_mask = rb0_mask << 1; 1752 rb0_mask &= rb_mask; 1753 rb1_mask &= rb_mask; 1754 if (!rb0_mask || !rb1_mask) { 1755 raster_config_se &= ~RB_MAP_PKR1_MASK; 1756 1757 if (!rb0_mask) { 1758 raster_config_se |= 1759 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3); 1760 } else { 1761 raster_config_se |= 1762 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0); 1763 } 1764 } 1765 } 1766 } 1767 1768 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1769 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1770 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1771 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1772 } 1773 1774 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1775 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1776 } 1777 1778 /** 1779 * gfx_v7_0_setup_rb - setup the RBs on the asic 1780 * 1781 * @adev: amdgpu_device pointer 1782 * @se_num: number of SEs (shader engines) for the asic 1783 * @sh_per_se: number of SH blocks per SE for the asic 1784 * 1785 * Configures per-SE/SH RB registers (CIK). 1786 */ 1787 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev) 1788 { 1789 int i, j; 1790 u32 data; 1791 u32 raster_config = 0, raster_config_1 = 0; 1792 u32 active_rbs = 0; 1793 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1794 adev->gfx.config.max_sh_per_se; 1795 unsigned num_rb_pipes; 1796 1797 mutex_lock(&adev->grbm_idx_mutex); 1798 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1799 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1800 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1801 data = gfx_v7_0_get_rb_active_bitmap(adev); 1802 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1803 rb_bitmap_width_per_sh); 1804 } 1805 } 1806 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1807 1808 adev->gfx.config.backend_enable_mask = active_rbs; 1809 adev->gfx.config.num_rbs = hweight32(active_rbs); 1810 1811 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1812 adev->gfx.config.max_shader_engines, 16); 1813 1814 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1); 1815 1816 if (!adev->gfx.config.backend_enable_mask || 1817 adev->gfx.config.num_rbs >= num_rb_pipes) { 1818 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1819 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1820 } else { 1821 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, 1822 adev->gfx.config.backend_enable_mask, 1823 num_rb_pipes); 1824 } 1825 1826 /* cache the values for userspace */ 1827 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1828 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1829 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1830 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1831 RREG32(mmCC_RB_BACKEND_DISABLE); 1832 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1833 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1834 adev->gfx.config.rb_config[i][j].raster_config = 1835 RREG32(mmPA_SC_RASTER_CONFIG); 1836 adev->gfx.config.rb_config[i][j].raster_config_1 = 1837 RREG32(mmPA_SC_RASTER_CONFIG_1); 1838 } 1839 } 1840 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1841 mutex_unlock(&adev->grbm_idx_mutex); 1842 } 1843 1844 /** 1845 * gfx_v7_0_init_compute_vmid - gart enable 1846 * 1847 * @adev: amdgpu_device pointer 1848 * 1849 * Initialize compute vmid sh_mem registers 1850 * 1851 */ 1852 #define DEFAULT_SH_MEM_BASES (0x6000) 1853 #define FIRST_COMPUTE_VMID (8) 1854 #define LAST_COMPUTE_VMID (16) 1855 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) 1856 { 1857 int i; 1858 uint32_t sh_mem_config; 1859 uint32_t sh_mem_bases; 1860 1861 /* 1862 * Configure apertures: 1863 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1864 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1865 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1866 */ 1867 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1868 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1869 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1870 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT; 1871 mutex_lock(&adev->srbm_mutex); 1872 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1873 cik_srbm_select(adev, 0, 0, 0, i); 1874 /* CP and shaders */ 1875 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 1876 WREG32(mmSH_MEM_APE1_BASE, 1); 1877 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1878 WREG32(mmSH_MEM_BASES, sh_mem_bases); 1879 } 1880 cik_srbm_select(adev, 0, 0, 0, 0); 1881 mutex_unlock(&adev->srbm_mutex); 1882 } 1883 1884 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev) 1885 { 1886 int vmid; 1887 1888 /* 1889 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1890 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1891 * the driver can enable them for graphics. VMID0 should maintain 1892 * access so that HWS firmware can save/restore entries. 1893 */ 1894 for (vmid = 1; vmid < 16; vmid++) { 1895 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); 1896 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); 1897 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); 1898 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); 1899 } 1900 } 1901 1902 static void gfx_v7_0_config_init(struct amdgpu_device *adev) 1903 { 1904 adev->gfx.config.double_offchip_lds_buf = 1; 1905 } 1906 1907 /** 1908 * gfx_v7_0_constants_init - setup the 3D engine 1909 * 1910 * @adev: amdgpu_device pointer 1911 * 1912 * init the gfx constants such as the 3D engine, tiling configuration 1913 * registers, maximum number of quad pipes, render backends... 1914 */ 1915 static void gfx_v7_0_constants_init(struct amdgpu_device *adev) 1916 { 1917 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base; 1918 u32 tmp; 1919 int i; 1920 1921 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1922 1923 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1924 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 1925 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); 1926 1927 gfx_v7_0_tiling_mode_table_init(adev); 1928 1929 gfx_v7_0_setup_rb(adev); 1930 gfx_v7_0_get_cu_info(adev); 1931 gfx_v7_0_config_init(adev); 1932 1933 /* set HW defaults for 3D engine */ 1934 WREG32(mmCP_MEQ_THRESHOLDS, 1935 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1936 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1937 1938 mutex_lock(&adev->grbm_idx_mutex); 1939 /* 1940 * making sure that the following register writes will be broadcasted 1941 * to all the shaders 1942 */ 1943 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1944 1945 /* XXX SH_MEM regs */ 1946 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1947 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1948 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1949 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE, 1950 MTYPE_NC); 1951 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE, 1952 MTYPE_UC); 1953 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); 1954 1955 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, 1956 SWIZZLE_ENABLE, 1); 1957 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1958 ELEMENT_SIZE, 1); 1959 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG, 1960 INDEX_STRIDE, 3); 1961 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg); 1962 1963 mutex_lock(&adev->srbm_mutex); 1964 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { 1965 if (i == 0) 1966 sh_mem_base = 0; 1967 else 1968 sh_mem_base = adev->gmc.shared_aperture_start >> 48; 1969 cik_srbm_select(adev, 0, 0, 0, i); 1970 /* CP and shaders */ 1971 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); 1972 WREG32(mmSH_MEM_APE1_BASE, 1); 1973 WREG32(mmSH_MEM_APE1_LIMIT, 0); 1974 WREG32(mmSH_MEM_BASES, sh_mem_base); 1975 } 1976 cik_srbm_select(adev, 0, 0, 0, 0); 1977 mutex_unlock(&adev->srbm_mutex); 1978 1979 gfx_v7_0_init_compute_vmid(adev); 1980 gfx_v7_0_init_gds_vmid(adev); 1981 1982 WREG32(mmSX_DEBUG_1, 0x20); 1983 1984 WREG32(mmTA_CNTL_AUX, 0x00010000); 1985 1986 tmp = RREG32(mmSPI_CONFIG_CNTL); 1987 tmp |= 0x03000000; 1988 WREG32(mmSPI_CONFIG_CNTL, tmp); 1989 1990 WREG32(mmSQ_CONFIG, 1); 1991 1992 WREG32(mmDB_DEBUG, 0); 1993 1994 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; 1995 tmp |= 0x00000400; 1996 WREG32(mmDB_DEBUG2, tmp); 1997 1998 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; 1999 tmp |= 0x00020200; 2000 WREG32(mmDB_DEBUG3, tmp); 2001 2002 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; 2003 tmp |= 0x00018208; 2004 WREG32(mmCB_HW_CONTROL, tmp); 2005 2006 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 2007 2008 WREG32(mmPA_SC_FIFO_SIZE, 2009 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 2010 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 2011 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 2012 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 2013 2014 WREG32(mmVGT_NUM_INSTANCES, 1); 2015 2016 WREG32(mmCP_PERFMON_CNTL, 0); 2017 2018 WREG32(mmSQ_CONFIG, 0); 2019 2020 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, 2021 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 2022 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 2023 2024 WREG32(mmVGT_CACHE_INVALIDATION, 2025 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 2026 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 2027 2028 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 2029 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 2030 2031 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 2032 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 2033 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK); 2034 2035 tmp = RREG32(mmSPI_ARB_PRIORITY); 2036 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2); 2037 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2); 2038 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2); 2039 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2); 2040 WREG32(mmSPI_ARB_PRIORITY, tmp); 2041 2042 mutex_unlock(&adev->grbm_idx_mutex); 2043 2044 udelay(50); 2045 } 2046 2047 /* 2048 * GPU scratch registers helpers function. 2049 */ 2050 /** 2051 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs 2052 * 2053 * @adev: amdgpu_device pointer 2054 * 2055 * Set up the number and offset of the CP scratch registers. 2056 * NOTE: use of CP scratch registers is a legacy inferface and 2057 * is not used by default on newer asics (r6xx+). On newer asics, 2058 * memory buffers are used for fences rather than scratch regs. 2059 */ 2060 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev) 2061 { 2062 adev->gfx.scratch.num_reg = 8; 2063 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 2064 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 2065 } 2066 2067 /** 2068 * gfx_v7_0_ring_test_ring - basic gfx ring test 2069 * 2070 * @adev: amdgpu_device pointer 2071 * @ring: amdgpu_ring structure holding ring information 2072 * 2073 * Allocate a scratch register and write to it using the gfx ring (CIK). 2074 * Provides a basic gfx ring test to verify that the ring is working. 2075 * Used by gfx_v7_0_cp_gfx_resume(); 2076 * Returns 0 on success, error on failure. 2077 */ 2078 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) 2079 { 2080 struct amdgpu_device *adev = ring->adev; 2081 uint32_t scratch; 2082 uint32_t tmp = 0; 2083 unsigned i; 2084 int r; 2085 2086 r = amdgpu_gfx_scratch_get(adev, &scratch); 2087 if (r) 2088 return r; 2089 2090 WREG32(scratch, 0xCAFEDEAD); 2091 r = amdgpu_ring_alloc(ring, 3); 2092 if (r) 2093 goto error_free_scratch; 2094 2095 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2096 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2097 amdgpu_ring_write(ring, 0xDEADBEEF); 2098 amdgpu_ring_commit(ring); 2099 2100 for (i = 0; i < adev->usec_timeout; i++) { 2101 tmp = RREG32(scratch); 2102 if (tmp == 0xDEADBEEF) 2103 break; 2104 udelay(1); 2105 } 2106 if (i >= adev->usec_timeout) 2107 r = -ETIMEDOUT; 2108 2109 error_free_scratch: 2110 amdgpu_gfx_scratch_free(adev, scratch); 2111 return r; 2112 } 2113 2114 /** 2115 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp 2116 * 2117 * @adev: amdgpu_device pointer 2118 * @ridx: amdgpu ring index 2119 * 2120 * Emits an hdp flush on the cp. 2121 */ 2122 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2123 { 2124 u32 ref_and_mask; 2125 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; 2126 2127 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2128 switch (ring->me) { 2129 case 1: 2130 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; 2131 break; 2132 case 2: 2133 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; 2134 break; 2135 default: 2136 return; 2137 } 2138 } else { 2139 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; 2140 } 2141 2142 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2143 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ 2144 WAIT_REG_MEM_FUNCTION(3) | /* == */ 2145 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2146 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ); 2147 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE); 2148 amdgpu_ring_write(ring, ref_and_mask); 2149 amdgpu_ring_write(ring, ref_and_mask); 2150 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2151 } 2152 2153 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 2154 { 2155 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2156 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | 2157 EVENT_INDEX(4)); 2158 2159 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2160 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 2161 EVENT_INDEX(0)); 2162 } 2163 2164 /** 2165 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring 2166 * 2167 * @adev: amdgpu_device pointer 2168 * @fence: amdgpu fence object 2169 * 2170 * Emits a fence sequnce number on the gfx ring and flushes 2171 * GPU caches. 2172 */ 2173 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, 2174 u64 seq, unsigned flags) 2175 { 2176 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2177 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2178 /* Workaround for cache flush problems. First send a dummy EOP 2179 * event down the pipe with seq one below. 2180 */ 2181 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2182 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2183 EOP_TC_ACTION_EN | 2184 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2185 EVENT_INDEX(5))); 2186 amdgpu_ring_write(ring, addr & 0xfffffffc); 2187 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2188 DATA_SEL(1) | INT_SEL(0)); 2189 amdgpu_ring_write(ring, lower_32_bits(seq - 1)); 2190 amdgpu_ring_write(ring, upper_32_bits(seq - 1)); 2191 2192 /* Then send the real EOP event down the pipe. */ 2193 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2194 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2195 EOP_TC_ACTION_EN | 2196 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2197 EVENT_INDEX(5))); 2198 amdgpu_ring_write(ring, addr & 0xfffffffc); 2199 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 2200 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2201 amdgpu_ring_write(ring, lower_32_bits(seq)); 2202 amdgpu_ring_write(ring, upper_32_bits(seq)); 2203 } 2204 2205 /** 2206 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring 2207 * 2208 * @adev: amdgpu_device pointer 2209 * @fence: amdgpu fence object 2210 * 2211 * Emits a fence sequnce number on the compute ring and flushes 2212 * GPU caches. 2213 */ 2214 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, 2215 u64 addr, u64 seq, 2216 unsigned flags) 2217 { 2218 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2219 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2220 2221 /* RELEASE_MEM - flush caches, send int */ 2222 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); 2223 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | 2224 EOP_TC_ACTION_EN | 2225 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2226 EVENT_INDEX(5))); 2227 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2228 amdgpu_ring_write(ring, addr & 0xfffffffc); 2229 amdgpu_ring_write(ring, upper_32_bits(addr)); 2230 amdgpu_ring_write(ring, lower_32_bits(seq)); 2231 amdgpu_ring_write(ring, upper_32_bits(seq)); 2232 } 2233 2234 /* 2235 * IB stuff 2236 */ 2237 /** 2238 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring 2239 * 2240 * @ring: amdgpu_ring structure holding ring information 2241 * @ib: amdgpu indirect buffer object 2242 * 2243 * Emits an DE (drawing engine) or CE (constant engine) IB 2244 * on the gfx ring. IBs are usually generated by userspace 2245 * acceleration drivers and submitted to the kernel for 2246 * sheduling on the ring. This function schedules the IB 2247 * on the gfx ring for execution by the GPU. 2248 */ 2249 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 2250 struct amdgpu_job *job, 2251 struct amdgpu_ib *ib, 2252 uint32_t flags) 2253 { 2254 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2255 u32 header, control = 0; 2256 2257 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 2258 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2259 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2260 amdgpu_ring_write(ring, 0); 2261 } 2262 2263 if (ib->flags & AMDGPU_IB_FLAG_CE) 2264 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 2265 else 2266 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 2267 2268 control |= ib->length_dw | (vmid << 24); 2269 2270 amdgpu_ring_write(ring, header); 2271 amdgpu_ring_write(ring, 2272 #ifdef __BIG_ENDIAN 2273 (2 << 0) | 2274 #endif 2275 (ib->gpu_addr & 0xFFFFFFFC)); 2276 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2277 amdgpu_ring_write(ring, control); 2278 } 2279 2280 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 2281 struct amdgpu_job *job, 2282 struct amdgpu_ib *ib, 2283 uint32_t flags) 2284 { 2285 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2286 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2287 2288 /* Currently, there is a high possibility to get wave ID mismatch 2289 * between ME and GDS, leading to a hw deadlock, because ME generates 2290 * different wave IDs than the GDS expects. This situation happens 2291 * randomly when at least 5 compute pipes use GDS ordered append. 2292 * The wave IDs generated by ME are also wrong after suspend/resume. 2293 * Those are probably bugs somewhere else in the kernel driver. 2294 * 2295 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2296 * GDS to 0 for this ring (me/pipe). 2297 */ 2298 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2299 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2300 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START); 2301 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2302 } 2303 2304 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2305 amdgpu_ring_write(ring, 2306 #ifdef __BIG_ENDIAN 2307 (2 << 0) | 2308 #endif 2309 (ib->gpu_addr & 0xFFFFFFFC)); 2310 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 2311 amdgpu_ring_write(ring, control); 2312 } 2313 2314 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2315 { 2316 uint32_t dw2 = 0; 2317 2318 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 2319 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 2320 gfx_v7_0_ring_emit_vgt_flush(ring); 2321 /* set load_global_config & load_global_uconfig */ 2322 dw2 |= 0x8001; 2323 /* set load_cs_sh_regs */ 2324 dw2 |= 0x01000000; 2325 /* set load_per_context_state & load_gfx_sh_regs */ 2326 dw2 |= 0x10002; 2327 } 2328 2329 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2330 amdgpu_ring_write(ring, dw2); 2331 amdgpu_ring_write(ring, 0); 2332 } 2333 2334 /** 2335 * gfx_v7_0_ring_test_ib - basic ring IB test 2336 * 2337 * @ring: amdgpu_ring structure holding ring information 2338 * 2339 * Allocate an IB and execute it on the gfx ring (CIK). 2340 * Provides a basic gfx ring test to verify that IBs are working. 2341 * Returns 0 on success, error on failure. 2342 */ 2343 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 2344 { 2345 struct amdgpu_device *adev = ring->adev; 2346 struct amdgpu_ib ib; 2347 struct dma_fence *f = NULL; 2348 uint32_t scratch; 2349 uint32_t tmp = 0; 2350 long r; 2351 2352 r = amdgpu_gfx_scratch_get(adev, &scratch); 2353 if (r) 2354 return r; 2355 2356 WREG32(scratch, 0xCAFEDEAD); 2357 memset(&ib, 0, sizeof(ib)); 2358 r = amdgpu_ib_get(adev, NULL, 256, &ib); 2359 if (r) 2360 goto err1; 2361 2362 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 2363 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 2364 ib.ptr[2] = 0xDEADBEEF; 2365 ib.length_dw = 3; 2366 2367 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 2368 if (r) 2369 goto err2; 2370 2371 r = dma_fence_wait_timeout(f, false, timeout); 2372 if (r == 0) { 2373 r = -ETIMEDOUT; 2374 goto err2; 2375 } else if (r < 0) { 2376 goto err2; 2377 } 2378 tmp = RREG32(scratch); 2379 if (tmp == 0xDEADBEEF) 2380 r = 0; 2381 else 2382 r = -EINVAL; 2383 2384 err2: 2385 amdgpu_ib_free(adev, &ib, NULL); 2386 dma_fence_put(f); 2387 err1: 2388 amdgpu_gfx_scratch_free(adev, scratch); 2389 return r; 2390 } 2391 2392 /* 2393 * CP. 2394 * On CIK, gfx and compute now have independant command processors. 2395 * 2396 * GFX 2397 * Gfx consists of a single ring and can process both gfx jobs and 2398 * compute jobs. The gfx CP consists of three microengines (ME): 2399 * PFP - Pre-Fetch Parser 2400 * ME - Micro Engine 2401 * CE - Constant Engine 2402 * The PFP and ME make up what is considered the Drawing Engine (DE). 2403 * The CE is an asynchronous engine used for updating buffer desciptors 2404 * used by the DE so that they can be loaded into cache in parallel 2405 * while the DE is processing state update packets. 2406 * 2407 * Compute 2408 * The compute CP consists of two microengines (ME): 2409 * MEC1 - Compute MicroEngine 1 2410 * MEC2 - Compute MicroEngine 2 2411 * Each MEC supports 4 compute pipes and each pipe supports 8 queues. 2412 * The queues are exposed to userspace and are programmed directly 2413 * by the compute runtime. 2414 */ 2415 /** 2416 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs 2417 * 2418 * @adev: amdgpu_device pointer 2419 * @enable: enable or disable the MEs 2420 * 2421 * Halts or unhalts the gfx MEs. 2422 */ 2423 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2424 { 2425 int i; 2426 2427 if (enable) { 2428 WREG32(mmCP_ME_CNTL, 0); 2429 } else { 2430 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK)); 2431 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2432 adev->gfx.gfx_ring[i].sched.ready = false; 2433 } 2434 udelay(50); 2435 } 2436 2437 /** 2438 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode 2439 * 2440 * @adev: amdgpu_device pointer 2441 * 2442 * Loads the gfx PFP, ME, and CE ucode. 2443 * Returns 0 for success, -EINVAL if the ucode is not available. 2444 */ 2445 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2446 { 2447 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2448 const struct gfx_firmware_header_v1_0 *ce_hdr; 2449 const struct gfx_firmware_header_v1_0 *me_hdr; 2450 const __le32 *fw_data; 2451 unsigned i, fw_size; 2452 2453 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2454 return -EINVAL; 2455 2456 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2457 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2458 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2459 2460 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2461 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2462 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2463 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); 2464 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); 2465 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); 2466 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); 2467 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); 2468 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); 2469 2470 gfx_v7_0_cp_gfx_enable(adev, false); 2471 2472 /* PFP */ 2473 fw_data = (const __le32 *) 2474 (adev->gfx.pfp_fw->data + 2475 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2476 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2477 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2478 for (i = 0; i < fw_size; i++) 2479 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2480 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2481 2482 /* CE */ 2483 fw_data = (const __le32 *) 2484 (adev->gfx.ce_fw->data + 2485 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2486 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2487 WREG32(mmCP_CE_UCODE_ADDR, 0); 2488 for (i = 0; i < fw_size; i++) 2489 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2490 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2491 2492 /* ME */ 2493 fw_data = (const __le32 *) 2494 (adev->gfx.me_fw->data + 2495 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2496 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2497 WREG32(mmCP_ME_RAM_WADDR, 0); 2498 for (i = 0; i < fw_size; i++) 2499 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2500 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2501 2502 return 0; 2503 } 2504 2505 /** 2506 * gfx_v7_0_cp_gfx_start - start the gfx ring 2507 * 2508 * @adev: amdgpu_device pointer 2509 * 2510 * Enables the ring and loads the clear state context and other 2511 * packets required to init the ring. 2512 * Returns 0 for success, error for failure. 2513 */ 2514 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) 2515 { 2516 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2517 const struct cs_section_def *sect = NULL; 2518 const struct cs_extent_def *ext = NULL; 2519 int r, i; 2520 2521 /* init the CP */ 2522 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2523 WREG32(mmCP_ENDIAN_SWAP, 0); 2524 WREG32(mmCP_DEVICE_ID, 1); 2525 2526 gfx_v7_0_cp_gfx_enable(adev, true); 2527 2528 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); 2529 if (r) { 2530 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2531 return r; 2532 } 2533 2534 /* init the CE partitions. CE only used for gfx on CIK */ 2535 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2536 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2537 amdgpu_ring_write(ring, 0x8000); 2538 amdgpu_ring_write(ring, 0x8000); 2539 2540 /* clear state buffer */ 2541 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2542 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2543 2544 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2545 amdgpu_ring_write(ring, 0x80000000); 2546 amdgpu_ring_write(ring, 0x80000000); 2547 2548 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2549 for (ext = sect->section; ext->extent != NULL; ++ext) { 2550 if (sect->id == SECT_CONTEXT) { 2551 amdgpu_ring_write(ring, 2552 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2553 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2554 for (i = 0; i < ext->reg_count; i++) 2555 amdgpu_ring_write(ring, ext->extent[i]); 2556 } 2557 } 2558 } 2559 2560 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2561 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2562 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); 2563 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); 2564 2565 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2566 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2567 2568 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2569 amdgpu_ring_write(ring, 0); 2570 2571 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2572 amdgpu_ring_write(ring, 0x00000316); 2573 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 2574 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 2575 2576 amdgpu_ring_commit(ring); 2577 2578 return 0; 2579 } 2580 2581 /** 2582 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers 2583 * 2584 * @adev: amdgpu_device pointer 2585 * 2586 * Program the location and size of the gfx ring buffer 2587 * and test it to make sure it's working. 2588 * Returns 0 for success, error for failure. 2589 */ 2590 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev) 2591 { 2592 struct amdgpu_ring *ring; 2593 u32 tmp; 2594 u32 rb_bufsz; 2595 u64 rb_addr, rptr_addr; 2596 int r; 2597 2598 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2599 if (adev->asic_type != CHIP_HAWAII) 2600 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2601 2602 /* Set the write pointer delay */ 2603 WREG32(mmCP_RB_WPTR_DELAY, 0); 2604 2605 /* set the RB to use vmid 0 */ 2606 WREG32(mmCP_RB_VMID, 0); 2607 2608 WREG32(mmSCRATCH_ADDR, 0); 2609 2610 /* ring 0 - compute and gfx */ 2611 /* Set ring buffer size */ 2612 ring = &adev->gfx.gfx_ring[0]; 2613 rb_bufsz = order_base_2(ring->ring_size / 8); 2614 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2615 #ifdef __BIG_ENDIAN 2616 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT; 2617 #endif 2618 WREG32(mmCP_RB0_CNTL, tmp); 2619 2620 /* Initialize the ring buffer's read and write pointers */ 2621 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2622 ring->wptr = 0; 2623 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2624 2625 /* set the wb address wether it's enabled or not */ 2626 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2627 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2628 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2629 2630 /* scratch register shadowing is no longer supported */ 2631 WREG32(mmSCRATCH_UMSK, 0); 2632 2633 mdelay(1); 2634 WREG32(mmCP_RB0_CNTL, tmp); 2635 2636 rb_addr = ring->gpu_addr >> 8; 2637 WREG32(mmCP_RB0_BASE, rb_addr); 2638 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2639 2640 /* start the ring */ 2641 gfx_v7_0_cp_gfx_start(adev); 2642 r = amdgpu_ring_test_helper(ring); 2643 if (r) 2644 return r; 2645 2646 return 0; 2647 } 2648 2649 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 2650 { 2651 return ring->adev->wb.wb[ring->rptr_offs]; 2652 } 2653 2654 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 2655 { 2656 struct amdgpu_device *adev = ring->adev; 2657 2658 return RREG32(mmCP_RB0_WPTR); 2659 } 2660 2661 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2662 { 2663 struct amdgpu_device *adev = ring->adev; 2664 2665 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2666 (void)RREG32(mmCP_RB0_WPTR); 2667 } 2668 2669 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 2670 { 2671 /* XXX check if swapping is necessary on BE */ 2672 return ring->adev->wb.wb[ring->wptr_offs]; 2673 } 2674 2675 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2676 { 2677 struct amdgpu_device *adev = ring->adev; 2678 2679 /* XXX check if swapping is necessary on BE */ 2680 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2681 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2682 } 2683 2684 /** 2685 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs 2686 * 2687 * @adev: amdgpu_device pointer 2688 * @enable: enable or disable the MEs 2689 * 2690 * Halts or unhalts the compute MEs. 2691 */ 2692 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2693 { 2694 int i; 2695 2696 if (enable) { 2697 WREG32(mmCP_MEC_CNTL, 0); 2698 } else { 2699 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2700 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2701 adev->gfx.compute_ring[i].sched.ready = false; 2702 } 2703 udelay(50); 2704 } 2705 2706 /** 2707 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode 2708 * 2709 * @adev: amdgpu_device pointer 2710 * 2711 * Loads the compute MEC1&2 ucode. 2712 * Returns 0 for success, -EINVAL if the ucode is not available. 2713 */ 2714 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2715 { 2716 const struct gfx_firmware_header_v1_0 *mec_hdr; 2717 const __le32 *fw_data; 2718 unsigned i, fw_size; 2719 2720 if (!adev->gfx.mec_fw) 2721 return -EINVAL; 2722 2723 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2724 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2725 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); 2726 adev->gfx.mec_feature_version = le32_to_cpu( 2727 mec_hdr->ucode_feature_version); 2728 2729 gfx_v7_0_cp_compute_enable(adev, false); 2730 2731 /* MEC1 */ 2732 fw_data = (const __le32 *) 2733 (adev->gfx.mec_fw->data + 2734 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2735 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 2736 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2737 for (i = 0; i < fw_size; i++) 2738 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); 2739 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); 2740 2741 if (adev->asic_type == CHIP_KAVERI) { 2742 const struct gfx_firmware_header_v1_0 *mec2_hdr; 2743 2744 if (!adev->gfx.mec2_fw) 2745 return -EINVAL; 2746 2747 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2748 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header); 2749 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); 2750 adev->gfx.mec2_feature_version = le32_to_cpu( 2751 mec2_hdr->ucode_feature_version); 2752 2753 /* MEC2 */ 2754 fw_data = (const __le32 *) 2755 (adev->gfx.mec2_fw->data + 2756 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes)); 2757 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4; 2758 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2759 for (i = 0; i < fw_size; i++) 2760 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); 2761 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); 2762 } 2763 2764 return 0; 2765 } 2766 2767 /** 2768 * gfx_v7_0_cp_compute_fini - stop the compute queues 2769 * 2770 * @adev: amdgpu_device pointer 2771 * 2772 * Stop the compute queues and tear down the driver queue 2773 * info. 2774 */ 2775 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev) 2776 { 2777 int i; 2778 2779 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2780 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2781 2782 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL); 2783 } 2784 } 2785 2786 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev) 2787 { 2788 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 2789 } 2790 2791 static int gfx_v7_0_mec_init(struct amdgpu_device *adev) 2792 { 2793 int r; 2794 u32 *hpd; 2795 size_t mec_hpd_size; 2796 2797 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 2798 2799 /* take ownership of the relevant compute queues */ 2800 amdgpu_gfx_compute_queue_acquire(adev); 2801 2802 /* allocate space for ALL pipes (even the ones we don't own) */ 2803 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec 2804 * GFX7_MEC_HPD_SIZE * 2; 2805 2806 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 2807 AMDGPU_GEM_DOMAIN_VRAM, 2808 &adev->gfx.mec.hpd_eop_obj, 2809 &adev->gfx.mec.hpd_eop_gpu_addr, 2810 (void **)&hpd); 2811 if (r) { 2812 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r); 2813 gfx_v7_0_mec_fini(adev); 2814 return r; 2815 } 2816 2817 /* clear memory. Not sure if this is required or not */ 2818 memset(hpd, 0, mec_hpd_size); 2819 2820 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 2821 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 2822 2823 return 0; 2824 } 2825 2826 struct hqd_registers 2827 { 2828 u32 cp_mqd_base_addr; 2829 u32 cp_mqd_base_addr_hi; 2830 u32 cp_hqd_active; 2831 u32 cp_hqd_vmid; 2832 u32 cp_hqd_persistent_state; 2833 u32 cp_hqd_pipe_priority; 2834 u32 cp_hqd_queue_priority; 2835 u32 cp_hqd_quantum; 2836 u32 cp_hqd_pq_base; 2837 u32 cp_hqd_pq_base_hi; 2838 u32 cp_hqd_pq_rptr; 2839 u32 cp_hqd_pq_rptr_report_addr; 2840 u32 cp_hqd_pq_rptr_report_addr_hi; 2841 u32 cp_hqd_pq_wptr_poll_addr; 2842 u32 cp_hqd_pq_wptr_poll_addr_hi; 2843 u32 cp_hqd_pq_doorbell_control; 2844 u32 cp_hqd_pq_wptr; 2845 u32 cp_hqd_pq_control; 2846 u32 cp_hqd_ib_base_addr; 2847 u32 cp_hqd_ib_base_addr_hi; 2848 u32 cp_hqd_ib_rptr; 2849 u32 cp_hqd_ib_control; 2850 u32 cp_hqd_iq_timer; 2851 u32 cp_hqd_iq_rptr; 2852 u32 cp_hqd_dequeue_request; 2853 u32 cp_hqd_dma_offload; 2854 u32 cp_hqd_sema_cmd; 2855 u32 cp_hqd_msg_type; 2856 u32 cp_hqd_atomic0_preop_lo; 2857 u32 cp_hqd_atomic0_preop_hi; 2858 u32 cp_hqd_atomic1_preop_lo; 2859 u32 cp_hqd_atomic1_preop_hi; 2860 u32 cp_hqd_hq_scheduler0; 2861 u32 cp_hqd_hq_scheduler1; 2862 u32 cp_mqd_control; 2863 }; 2864 2865 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev, 2866 int mec, int pipe) 2867 { 2868 u64 eop_gpu_addr; 2869 u32 tmp; 2870 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe) 2871 * GFX7_MEC_HPD_SIZE * 2; 2872 2873 mutex_lock(&adev->srbm_mutex); 2874 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset; 2875 2876 cik_srbm_select(adev, mec + 1, pipe, 0, 0); 2877 2878 /* write the EOP addr */ 2879 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); 2880 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); 2881 2882 /* set the VMID assigned */ 2883 WREG32(mmCP_HPD_EOP_VMID, 0); 2884 2885 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2886 tmp = RREG32(mmCP_HPD_EOP_CONTROL); 2887 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK; 2888 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8); 2889 WREG32(mmCP_HPD_EOP_CONTROL, tmp); 2890 2891 cik_srbm_select(adev, 0, 0, 0, 0); 2892 mutex_unlock(&adev->srbm_mutex); 2893 } 2894 2895 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev) 2896 { 2897 int i; 2898 2899 /* disable the queue if it's active */ 2900 if (RREG32(mmCP_HQD_ACTIVE) & 1) { 2901 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1); 2902 for (i = 0; i < adev->usec_timeout; i++) { 2903 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) 2904 break; 2905 udelay(1); 2906 } 2907 2908 if (i == adev->usec_timeout) 2909 return -ETIMEDOUT; 2910 2911 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); 2912 WREG32(mmCP_HQD_PQ_RPTR, 0); 2913 WREG32(mmCP_HQD_PQ_WPTR, 0); 2914 } 2915 2916 return 0; 2917 } 2918 2919 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, 2920 struct cik_mqd *mqd, 2921 uint64_t mqd_gpu_addr, 2922 struct amdgpu_ring *ring) 2923 { 2924 u64 hqd_gpu_addr; 2925 u64 wb_gpu_addr; 2926 2927 /* init the mqd struct */ 2928 memset(mqd, 0, sizeof(struct cik_mqd)); 2929 2930 mqd->header = 0xC0310800; 2931 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2932 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2933 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2934 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2935 2936 /* enable doorbell? */ 2937 mqd->cp_hqd_pq_doorbell_control = 2938 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2939 if (ring->use_doorbell) 2940 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2941 else 2942 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 2943 2944 /* set the pointer to the MQD */ 2945 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; 2946 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); 2947 2948 /* set MQD vmid to 0 */ 2949 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); 2950 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK; 2951 2952 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2953 hqd_gpu_addr = ring->gpu_addr >> 8; 2954 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2955 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2956 2957 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2958 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); 2959 mqd->cp_hqd_pq_control &= 2960 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK | 2961 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK); 2962 2963 mqd->cp_hqd_pq_control |= 2964 order_base_2(ring->ring_size / 8); 2965 mqd->cp_hqd_pq_control |= 2966 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8); 2967 #ifdef __BIG_ENDIAN 2968 mqd->cp_hqd_pq_control |= 2969 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT; 2970 #endif 2971 mqd->cp_hqd_pq_control &= 2972 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK | 2973 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK | 2974 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK); 2975 mqd->cp_hqd_pq_control |= 2976 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK | 2977 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */ 2978 2979 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2980 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2981 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2982 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2983 2984 /* set the wb address wether it's enabled or not */ 2985 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2986 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2987 mqd->cp_hqd_pq_rptr_report_addr_hi = 2988 upper_32_bits(wb_gpu_addr) & 0xffff; 2989 2990 /* enable the doorbell if requested */ 2991 if (ring->use_doorbell) { 2992 mqd->cp_hqd_pq_doorbell_control = 2993 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); 2994 mqd->cp_hqd_pq_doorbell_control &= 2995 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK; 2996 mqd->cp_hqd_pq_doorbell_control |= 2997 (ring->doorbell_index << 2998 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT); 2999 mqd->cp_hqd_pq_doorbell_control |= 3000 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK; 3001 mqd->cp_hqd_pq_doorbell_control &= 3002 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK | 3003 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK); 3004 3005 } else { 3006 mqd->cp_hqd_pq_doorbell_control = 0; 3007 } 3008 3009 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3010 ring->wptr = 0; 3011 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); 3012 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3013 3014 /* set the vmid for the queue */ 3015 mqd->cp_hqd_vmid = 0; 3016 3017 /* defaults */ 3018 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); 3019 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); 3020 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); 3021 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); 3022 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); 3023 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); 3024 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); 3025 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); 3026 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); 3027 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); 3028 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); 3029 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); 3030 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3031 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); 3032 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); 3033 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); 3034 3035 /* activate the queue */ 3036 mqd->cp_hqd_active = 1; 3037 } 3038 3039 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd) 3040 { 3041 uint32_t tmp; 3042 uint32_t mqd_reg; 3043 uint32_t *mqd_data; 3044 3045 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */ 3046 mqd_data = &mqd->cp_mqd_base_addr_lo; 3047 3048 /* disable wptr polling */ 3049 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 3050 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3051 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp); 3052 3053 /* program all HQD registers */ 3054 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) 3055 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3056 3057 /* activate the HQD */ 3058 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) 3059 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]); 3060 3061 return 0; 3062 } 3063 3064 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id) 3065 { 3066 int r; 3067 u64 mqd_gpu_addr; 3068 struct cik_mqd *mqd; 3069 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 3070 3071 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE, 3072 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 3073 &mqd_gpu_addr, (void **)&mqd); 3074 if (r) { 3075 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r); 3076 return r; 3077 } 3078 3079 mutex_lock(&adev->srbm_mutex); 3080 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3081 3082 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring); 3083 gfx_v7_0_mqd_deactivate(adev); 3084 gfx_v7_0_mqd_commit(adev, mqd); 3085 3086 cik_srbm_select(adev, 0, 0, 0, 0); 3087 mutex_unlock(&adev->srbm_mutex); 3088 3089 amdgpu_bo_kunmap(ring->mqd_obj); 3090 amdgpu_bo_unreserve(ring->mqd_obj); 3091 return 0; 3092 } 3093 3094 /** 3095 * gfx_v7_0_cp_compute_resume - setup the compute queue registers 3096 * 3097 * @adev: amdgpu_device pointer 3098 * 3099 * Program the compute queues and test them to make sure they 3100 * are working. 3101 * Returns 0 for success, error for failure. 3102 */ 3103 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev) 3104 { 3105 int r, i, j; 3106 u32 tmp; 3107 struct amdgpu_ring *ring; 3108 3109 /* fix up chicken bits */ 3110 tmp = RREG32(mmCP_CPF_DEBUG); 3111 tmp |= (1 << 23); 3112 WREG32(mmCP_CPF_DEBUG, tmp); 3113 3114 /* init all pipes (even the ones we don't own) */ 3115 for (i = 0; i < adev->gfx.mec.num_mec; i++) 3116 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) 3117 gfx_v7_0_compute_pipe_init(adev, i, j); 3118 3119 /* init the queues */ 3120 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3121 r = gfx_v7_0_compute_queue_init(adev, i); 3122 if (r) { 3123 gfx_v7_0_cp_compute_fini(adev); 3124 return r; 3125 } 3126 } 3127 3128 gfx_v7_0_cp_compute_enable(adev, true); 3129 3130 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3131 ring = &adev->gfx.compute_ring[i]; 3132 amdgpu_ring_test_helper(ring); 3133 } 3134 3135 return 0; 3136 } 3137 3138 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable) 3139 { 3140 gfx_v7_0_cp_gfx_enable(adev, enable); 3141 gfx_v7_0_cp_compute_enable(adev, enable); 3142 } 3143 3144 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev) 3145 { 3146 int r; 3147 3148 r = gfx_v7_0_cp_gfx_load_microcode(adev); 3149 if (r) 3150 return r; 3151 r = gfx_v7_0_cp_compute_load_microcode(adev); 3152 if (r) 3153 return r; 3154 3155 return 0; 3156 } 3157 3158 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 3159 bool enable) 3160 { 3161 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 3162 3163 if (enable) 3164 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3165 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3166 else 3167 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK | 3168 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK); 3169 WREG32(mmCP_INT_CNTL_RING0, tmp); 3170 } 3171 3172 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) 3173 { 3174 int r; 3175 3176 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3177 3178 r = gfx_v7_0_cp_load_microcode(adev); 3179 if (r) 3180 return r; 3181 3182 r = gfx_v7_0_cp_gfx_resume(adev); 3183 if (r) 3184 return r; 3185 r = gfx_v7_0_cp_compute_resume(adev); 3186 if (r) 3187 return r; 3188 3189 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3190 3191 return 0; 3192 } 3193 3194 /** 3195 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3196 * 3197 * @ring: the ring to emmit the commands to 3198 * 3199 * Sync the command pipeline with the PFP. E.g. wait for everything 3200 * to be completed. 3201 */ 3202 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3203 { 3204 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3205 uint32_t seq = ring->fence_drv.sync_seq; 3206 uint64_t addr = ring->fence_drv.gpu_addr; 3207 3208 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3209 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 3210 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3211 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 3212 amdgpu_ring_write(ring, addr & 0xfffffffc); 3213 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 3214 amdgpu_ring_write(ring, seq); 3215 amdgpu_ring_write(ring, 0xffffffff); 3216 amdgpu_ring_write(ring, 4); /* poll interval */ 3217 3218 if (usepfp) { 3219 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3220 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3221 amdgpu_ring_write(ring, 0); 3222 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3223 amdgpu_ring_write(ring, 0); 3224 } 3225 } 3226 3227 /* 3228 * vm 3229 * VMID 0 is the physical GPU addresses as used by the kernel. 3230 * VMIDs 1-15 are used for userspace clients and are handled 3231 * by the amdgpu vm/hsa code. 3232 */ 3233 /** 3234 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP 3235 * 3236 * @adev: amdgpu_device pointer 3237 * 3238 * Update the page table base and flush the VM TLB 3239 * using the CP (CIK). 3240 */ 3241 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 3242 unsigned vmid, uint64_t pd_addr) 3243 { 3244 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3245 3246 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3247 3248 /* wait for the invalidate to complete */ 3249 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3250 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ 3251 WAIT_REG_MEM_FUNCTION(0) | /* always */ 3252 WAIT_REG_MEM_ENGINE(0))); /* me */ 3253 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 3254 amdgpu_ring_write(ring, 0); 3255 amdgpu_ring_write(ring, 0); /* ref */ 3256 amdgpu_ring_write(ring, 0); /* mask */ 3257 amdgpu_ring_write(ring, 0x20); /* poll interval */ 3258 3259 /* compute doesn't have PFP */ 3260 if (usepfp) { 3261 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3262 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3263 amdgpu_ring_write(ring, 0x0); 3264 3265 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 3266 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3267 amdgpu_ring_write(ring, 0); 3268 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 3269 amdgpu_ring_write(ring, 0); 3270 } 3271 } 3272 3273 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 3274 uint32_t reg, uint32_t val) 3275 { 3276 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3277 3278 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3279 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 3280 WRITE_DATA_DST_SEL(0))); 3281 amdgpu_ring_write(ring, reg); 3282 amdgpu_ring_write(ring, 0); 3283 amdgpu_ring_write(ring, val); 3284 } 3285 3286 /* 3287 * RLC 3288 * The RLC is a multi-purpose microengine that handles a 3289 * variety of functions. 3290 */ 3291 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) 3292 { 3293 const u32 *src_ptr; 3294 u32 dws; 3295 const struct cs_section_def *cs_data; 3296 int r; 3297 3298 /* allocate rlc buffers */ 3299 if (adev->flags & AMD_IS_APU) { 3300 if (adev->asic_type == CHIP_KAVERI) { 3301 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3302 adev->gfx.rlc.reg_list_size = 3303 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list); 3304 } else { 3305 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; 3306 adev->gfx.rlc.reg_list_size = 3307 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list); 3308 } 3309 } 3310 adev->gfx.rlc.cs_data = ci_cs_data; 3311 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ 3312 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ 3313 3314 src_ptr = adev->gfx.rlc.reg_list; 3315 dws = adev->gfx.rlc.reg_list_size; 3316 dws += (5 * 16) + 48 + 48 + 64; 3317 3318 cs_data = adev->gfx.rlc.cs_data; 3319 3320 if (src_ptr) { 3321 /* init save restore block */ 3322 r = amdgpu_gfx_rlc_init_sr(adev, dws); 3323 if (r) 3324 return r; 3325 } 3326 3327 if (cs_data) { 3328 /* init clear state block */ 3329 r = amdgpu_gfx_rlc_init_csb(adev); 3330 if (r) 3331 return r; 3332 } 3333 3334 if (adev->gfx.rlc.cp_table_size) { 3335 r = amdgpu_gfx_rlc_init_cpt(adev); 3336 if (r) 3337 return r; 3338 } 3339 3340 return 0; 3341 } 3342 3343 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 3344 { 3345 u32 tmp; 3346 3347 tmp = RREG32(mmRLC_LB_CNTL); 3348 if (enable) 3349 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3350 else 3351 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK; 3352 WREG32(mmRLC_LB_CNTL, tmp); 3353 } 3354 3355 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 3356 { 3357 u32 i, j, k; 3358 u32 mask; 3359 3360 mutex_lock(&adev->grbm_idx_mutex); 3361 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3362 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3363 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3364 for (k = 0; k < adev->usec_timeout; k++) { 3365 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3366 break; 3367 udelay(1); 3368 } 3369 } 3370 } 3371 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3372 mutex_unlock(&adev->grbm_idx_mutex); 3373 3374 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 3375 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 3376 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 3377 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 3378 for (k = 0; k < adev->usec_timeout; k++) { 3379 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 3380 break; 3381 udelay(1); 3382 } 3383 } 3384 3385 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 3386 { 3387 u32 tmp; 3388 3389 tmp = RREG32(mmRLC_CNTL); 3390 if (tmp != rlc) 3391 WREG32(mmRLC_CNTL, rlc); 3392 } 3393 3394 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev) 3395 { 3396 u32 data, orig; 3397 3398 orig = data = RREG32(mmRLC_CNTL); 3399 3400 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 3401 u32 i; 3402 3403 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 3404 WREG32(mmRLC_CNTL, data); 3405 3406 for (i = 0; i < adev->usec_timeout; i++) { 3407 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) 3408 break; 3409 udelay(1); 3410 } 3411 3412 gfx_v7_0_wait_for_rlc_serdes(adev); 3413 } 3414 3415 return orig; 3416 } 3417 3418 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev) 3419 { 3420 return true; 3421 } 3422 3423 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev) 3424 { 3425 u32 tmp, i, mask; 3426 3427 tmp = 0x1 | (1 << 1); 3428 WREG32(mmRLC_GPR_REG2, tmp); 3429 3430 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | 3431 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK; 3432 for (i = 0; i < adev->usec_timeout; i++) { 3433 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) 3434 break; 3435 udelay(1); 3436 } 3437 3438 for (i = 0; i < adev->usec_timeout; i++) { 3439 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) 3440 break; 3441 udelay(1); 3442 } 3443 } 3444 3445 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev) 3446 { 3447 u32 tmp; 3448 3449 tmp = 0x1 | (0 << 1); 3450 WREG32(mmRLC_GPR_REG2, tmp); 3451 } 3452 3453 /** 3454 * gfx_v7_0_rlc_stop - stop the RLC ME 3455 * 3456 * @adev: amdgpu_device pointer 3457 * 3458 * Halt the RLC ME (MicroEngine) (CIK). 3459 */ 3460 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev) 3461 { 3462 WREG32(mmRLC_CNTL, 0); 3463 3464 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3465 3466 gfx_v7_0_wait_for_rlc_serdes(adev); 3467 } 3468 3469 /** 3470 * gfx_v7_0_rlc_start - start the RLC ME 3471 * 3472 * @adev: amdgpu_device pointer 3473 * 3474 * Unhalt the RLC ME (MicroEngine) (CIK). 3475 */ 3476 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev) 3477 { 3478 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 3479 3480 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3481 3482 udelay(50); 3483 } 3484 3485 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev) 3486 { 3487 u32 tmp = RREG32(mmGRBM_SOFT_RESET); 3488 3489 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3490 WREG32(mmGRBM_SOFT_RESET, tmp); 3491 udelay(50); 3492 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 3493 WREG32(mmGRBM_SOFT_RESET, tmp); 3494 udelay(50); 3495 } 3496 3497 /** 3498 * gfx_v7_0_rlc_resume - setup the RLC hw 3499 * 3500 * @adev: amdgpu_device pointer 3501 * 3502 * Initialize the RLC registers, load the ucode, 3503 * and start the RLC (CIK). 3504 * Returns 0 for success, -EINVAL if the ucode is not available. 3505 */ 3506 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) 3507 { 3508 const struct rlc_firmware_header_v1_0 *hdr; 3509 const __le32 *fw_data; 3510 unsigned i, fw_size; 3511 u32 tmp; 3512 3513 if (!adev->gfx.rlc_fw) 3514 return -EINVAL; 3515 3516 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 3517 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3518 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); 3519 adev->gfx.rlc_feature_version = le32_to_cpu( 3520 hdr->ucode_feature_version); 3521 3522 adev->gfx.rlc.funcs->stop(adev); 3523 3524 /* disable CG */ 3525 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; 3526 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); 3527 3528 adev->gfx.rlc.funcs->reset(adev); 3529 3530 gfx_v7_0_init_pg(adev); 3531 3532 WREG32(mmRLC_LB_CNTR_INIT, 0); 3533 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3534 3535 mutex_lock(&adev->grbm_idx_mutex); 3536 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3537 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3538 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3539 WREG32(mmRLC_LB_CNTL, 0x80000004); 3540 mutex_unlock(&adev->grbm_idx_mutex); 3541 3542 WREG32(mmRLC_MC_CNTL, 0); 3543 WREG32(mmRLC_UCODE_CNTL, 0); 3544 3545 fw_data = (const __le32 *) 3546 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3547 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3548 WREG32(mmRLC_GPM_UCODE_ADDR, 0); 3549 for (i = 0; i < fw_size; i++) 3550 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3551 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3552 3553 /* XXX - find out what chips support lbpw */ 3554 gfx_v7_0_enable_lbpw(adev, false); 3555 3556 if (adev->asic_type == CHIP_BONAIRE) 3557 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); 3558 3559 adev->gfx.rlc.funcs->start(adev); 3560 3561 return 0; 3562 } 3563 3564 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 3565 { 3566 u32 data, orig, tmp, tmp2; 3567 3568 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 3569 3570 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3571 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3572 3573 tmp = gfx_v7_0_halt_rlc(adev); 3574 3575 mutex_lock(&adev->grbm_idx_mutex); 3576 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3577 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3578 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3579 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3580 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK | 3581 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK; 3582 WREG32(mmRLC_SERDES_WR_CTRL, tmp2); 3583 mutex_unlock(&adev->grbm_idx_mutex); 3584 3585 gfx_v7_0_update_rlc(adev, tmp); 3586 3587 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3588 if (orig != data) 3589 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3590 3591 } else { 3592 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3593 3594 RREG32(mmCB_CGTT_SCLK_CTRL); 3595 RREG32(mmCB_CGTT_SCLK_CTRL); 3596 RREG32(mmCB_CGTT_SCLK_CTRL); 3597 RREG32(mmCB_CGTT_SCLK_CTRL); 3598 3599 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3600 if (orig != data) 3601 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 3602 3603 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3604 } 3605 } 3606 3607 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 3608 { 3609 u32 data, orig, tmp = 0; 3610 3611 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3612 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3613 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3614 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 3615 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3616 if (orig != data) 3617 WREG32(mmCP_MEM_SLP_CNTL, data); 3618 } 3619 } 3620 3621 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3622 data |= 0x00000001; 3623 data &= 0xfffffffd; 3624 if (orig != data) 3625 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3626 3627 tmp = gfx_v7_0_halt_rlc(adev); 3628 3629 mutex_lock(&adev->grbm_idx_mutex); 3630 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3631 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3632 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3633 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | 3634 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK; 3635 WREG32(mmRLC_SERDES_WR_CTRL, data); 3636 mutex_unlock(&adev->grbm_idx_mutex); 3637 3638 gfx_v7_0_update_rlc(adev, tmp); 3639 3640 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) { 3641 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3642 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK; 3643 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); 3644 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK; 3645 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK; 3646 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) && 3647 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS)) 3648 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3649 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK; 3650 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK; 3651 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); 3652 if (orig != data) 3653 WREG32(mmCGTS_SM_CTRL_REG, data); 3654 } 3655 } else { 3656 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 3657 data |= 0x00000003; 3658 if (orig != data) 3659 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 3660 3661 data = RREG32(mmRLC_MEM_SLP_CNTL); 3662 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3663 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3664 WREG32(mmRLC_MEM_SLP_CNTL, data); 3665 } 3666 3667 data = RREG32(mmCP_MEM_SLP_CNTL); 3668 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3669 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3670 WREG32(mmCP_MEM_SLP_CNTL, data); 3671 } 3672 3673 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 3674 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK; 3675 if (orig != data) 3676 WREG32(mmCGTS_SM_CTRL_REG, data); 3677 3678 tmp = gfx_v7_0_halt_rlc(adev); 3679 3680 mutex_lock(&adev->grbm_idx_mutex); 3681 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3682 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3683 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3684 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; 3685 WREG32(mmRLC_SERDES_WR_CTRL, data); 3686 mutex_unlock(&adev->grbm_idx_mutex); 3687 3688 gfx_v7_0_update_rlc(adev, tmp); 3689 } 3690 } 3691 3692 static void gfx_v7_0_update_cg(struct amdgpu_device *adev, 3693 bool enable) 3694 { 3695 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 3696 /* order matters! */ 3697 if (enable) { 3698 gfx_v7_0_enable_mgcg(adev, true); 3699 gfx_v7_0_enable_cgcg(adev, true); 3700 } else { 3701 gfx_v7_0_enable_cgcg(adev, false); 3702 gfx_v7_0_enable_mgcg(adev, false); 3703 } 3704 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 3705 } 3706 3707 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 3708 bool enable) 3709 { 3710 u32 data, orig; 3711 3712 orig = data = RREG32(mmRLC_PG_CNTL); 3713 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3714 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3715 else 3716 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK; 3717 if (orig != data) 3718 WREG32(mmRLC_PG_CNTL, data); 3719 } 3720 3721 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 3722 bool enable) 3723 { 3724 u32 data, orig; 3725 3726 orig = data = RREG32(mmRLC_PG_CNTL); 3727 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS)) 3728 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3729 else 3730 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK; 3731 if (orig != data) 3732 WREG32(mmRLC_PG_CNTL, data); 3733 } 3734 3735 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 3736 { 3737 u32 data, orig; 3738 3739 orig = data = RREG32(mmRLC_PG_CNTL); 3740 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 3741 data &= ~0x8000; 3742 else 3743 data |= 0x8000; 3744 if (orig != data) 3745 WREG32(mmRLC_PG_CNTL, data); 3746 } 3747 3748 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 3749 { 3750 u32 data, orig; 3751 3752 orig = data = RREG32(mmRLC_PG_CNTL); 3753 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS)) 3754 data &= ~0x2000; 3755 else 3756 data |= 0x2000; 3757 if (orig != data) 3758 WREG32(mmRLC_PG_CNTL, data); 3759 } 3760 3761 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev) 3762 { 3763 if (adev->asic_type == CHIP_KAVERI) 3764 return 5; 3765 else 3766 return 4; 3767 } 3768 3769 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev, 3770 bool enable) 3771 { 3772 u32 data, orig; 3773 3774 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 3775 orig = data = RREG32(mmRLC_PG_CNTL); 3776 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3777 if (orig != data) 3778 WREG32(mmRLC_PG_CNTL, data); 3779 3780 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3781 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3782 if (orig != data) 3783 WREG32(mmRLC_AUTO_PG_CTRL, data); 3784 } else { 3785 orig = data = RREG32(mmRLC_PG_CNTL); 3786 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 3787 if (orig != data) 3788 WREG32(mmRLC_PG_CNTL, data); 3789 3790 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); 3791 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK; 3792 if (orig != data) 3793 WREG32(mmRLC_AUTO_PG_CTRL, data); 3794 3795 data = RREG32(mmDB_RENDER_CONTROL); 3796 } 3797 } 3798 3799 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 3800 u32 bitmap) 3801 { 3802 u32 data; 3803 3804 if (!bitmap) 3805 return; 3806 3807 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3808 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3809 3810 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 3811 } 3812 3813 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 3814 { 3815 u32 data, mask; 3816 3817 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); 3818 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 3819 3820 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 3821 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 3822 3823 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3824 3825 return (~data) & mask; 3826 } 3827 3828 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev) 3829 { 3830 u32 tmp; 3831 3832 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 3833 3834 tmp = RREG32(mmRLC_MAX_PG_CU); 3835 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 3836 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 3837 WREG32(mmRLC_MAX_PG_CU, tmp); 3838 } 3839 3840 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 3841 bool enable) 3842 { 3843 u32 data, orig; 3844 3845 orig = data = RREG32(mmRLC_PG_CNTL); 3846 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 3847 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3848 else 3849 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 3850 if (orig != data) 3851 WREG32(mmRLC_PG_CNTL, data); 3852 } 3853 3854 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 3855 bool enable) 3856 { 3857 u32 data, orig; 3858 3859 orig = data = RREG32(mmRLC_PG_CNTL); 3860 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 3861 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3862 else 3863 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 3864 if (orig != data) 3865 WREG32(mmRLC_PG_CNTL, data); 3866 } 3867 3868 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 3869 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 3870 3871 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev) 3872 { 3873 u32 data, orig; 3874 u32 i; 3875 3876 if (adev->gfx.rlc.cs_data) { 3877 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3878 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3879 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); 3880 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); 3881 } else { 3882 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); 3883 for (i = 0; i < 3; i++) 3884 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); 3885 } 3886 if (adev->gfx.rlc.reg_list) { 3887 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); 3888 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 3889 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); 3890 } 3891 3892 orig = data = RREG32(mmRLC_PG_CNTL); 3893 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK; 3894 if (orig != data) 3895 WREG32(mmRLC_PG_CNTL, data); 3896 3897 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3898 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); 3899 3900 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); 3901 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3902 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3903 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); 3904 3905 data = 0x10101010; 3906 WREG32(mmRLC_PG_DELAY, data); 3907 3908 data = RREG32(mmRLC_PG_DELAY_2); 3909 data &= ~0xff; 3910 data |= 0x3; 3911 WREG32(mmRLC_PG_DELAY_2, data); 3912 3913 data = RREG32(mmRLC_AUTO_PG_CTRL); 3914 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 3915 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 3916 WREG32(mmRLC_AUTO_PG_CTRL, data); 3917 3918 } 3919 3920 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 3921 { 3922 gfx_v7_0_enable_gfx_cgpg(adev, enable); 3923 gfx_v7_0_enable_gfx_static_mgpg(adev, enable); 3924 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable); 3925 } 3926 3927 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) 3928 { 3929 u32 count = 0; 3930 const struct cs_section_def *sect = NULL; 3931 const struct cs_extent_def *ext = NULL; 3932 3933 if (adev->gfx.rlc.cs_data == NULL) 3934 return 0; 3935 3936 /* begin clear state */ 3937 count += 2; 3938 /* context control state */ 3939 count += 3; 3940 3941 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3942 for (ext = sect->section; ext->extent != NULL; ++ext) { 3943 if (sect->id == SECT_CONTEXT) 3944 count += 2 + ext->reg_count; 3945 else 3946 return 0; 3947 } 3948 } 3949 /* pa_sc_raster_config/pa_sc_raster_config1 */ 3950 count += 4; 3951 /* end clear state */ 3952 count += 2; 3953 /* clear state */ 3954 count += 2; 3955 3956 return count; 3957 } 3958 3959 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, 3960 volatile u32 *buffer) 3961 { 3962 u32 count = 0, i; 3963 const struct cs_section_def *sect = NULL; 3964 const struct cs_extent_def *ext = NULL; 3965 3966 if (adev->gfx.rlc.cs_data == NULL) 3967 return; 3968 if (buffer == NULL) 3969 return; 3970 3971 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3972 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3973 3974 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3975 buffer[count++] = cpu_to_le32(0x80000000); 3976 buffer[count++] = cpu_to_le32(0x80000000); 3977 3978 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3979 for (ext = sect->section; ext->extent != NULL; ++ext) { 3980 if (sect->id == SECT_CONTEXT) { 3981 buffer[count++] = 3982 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 3983 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3984 for (i = 0; i < ext->reg_count; i++) 3985 buffer[count++] = cpu_to_le32(ext->extent[i]); 3986 } else { 3987 return; 3988 } 3989 } 3990 } 3991 3992 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 3993 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3994 switch (adev->asic_type) { 3995 case CHIP_BONAIRE: 3996 buffer[count++] = cpu_to_le32(0x16000012); 3997 buffer[count++] = cpu_to_le32(0x00000000); 3998 break; 3999 case CHIP_KAVERI: 4000 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4001 buffer[count++] = cpu_to_le32(0x00000000); 4002 break; 4003 case CHIP_KABINI: 4004 case CHIP_MULLINS: 4005 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */ 4006 buffer[count++] = cpu_to_le32(0x00000000); 4007 break; 4008 case CHIP_HAWAII: 4009 buffer[count++] = cpu_to_le32(0x3a00161a); 4010 buffer[count++] = cpu_to_le32(0x0000002e); 4011 break; 4012 default: 4013 buffer[count++] = cpu_to_le32(0x00000000); 4014 buffer[count++] = cpu_to_le32(0x00000000); 4015 break; 4016 } 4017 4018 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4019 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4020 4021 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4022 buffer[count++] = cpu_to_le32(0); 4023 } 4024 4025 static void gfx_v7_0_init_pg(struct amdgpu_device *adev) 4026 { 4027 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4028 AMD_PG_SUPPORT_GFX_SMG | 4029 AMD_PG_SUPPORT_GFX_DMG | 4030 AMD_PG_SUPPORT_CP | 4031 AMD_PG_SUPPORT_GDS | 4032 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4033 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true); 4034 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true); 4035 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4036 gfx_v7_0_init_gfx_cgpg(adev); 4037 gfx_v7_0_enable_cp_pg(adev, true); 4038 gfx_v7_0_enable_gds_pg(adev, true); 4039 } 4040 gfx_v7_0_init_ao_cu_mask(adev); 4041 gfx_v7_0_update_gfx_pg(adev, true); 4042 } 4043 } 4044 4045 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev) 4046 { 4047 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4048 AMD_PG_SUPPORT_GFX_SMG | 4049 AMD_PG_SUPPORT_GFX_DMG | 4050 AMD_PG_SUPPORT_CP | 4051 AMD_PG_SUPPORT_GDS | 4052 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4053 gfx_v7_0_update_gfx_pg(adev, false); 4054 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4055 gfx_v7_0_enable_cp_pg(adev, false); 4056 gfx_v7_0_enable_gds_pg(adev, false); 4057 } 4058 } 4059 } 4060 4061 /** 4062 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot 4063 * 4064 * @adev: amdgpu_device pointer 4065 * 4066 * Fetches a GPU clock counter snapshot (SI). 4067 * Returns the 64 bit clock counter snapshot. 4068 */ 4069 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4070 { 4071 uint64_t clock; 4072 4073 mutex_lock(&adev->gfx.gpu_clock_mutex); 4074 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4075 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 4076 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4077 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4078 return clock; 4079 } 4080 4081 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4082 uint32_t vmid, 4083 uint32_t gds_base, uint32_t gds_size, 4084 uint32_t gws_base, uint32_t gws_size, 4085 uint32_t oa_base, uint32_t oa_size) 4086 { 4087 /* GDS Base */ 4088 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4089 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4090 WRITE_DATA_DST_SEL(0))); 4091 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base); 4092 amdgpu_ring_write(ring, 0); 4093 amdgpu_ring_write(ring, gds_base); 4094 4095 /* GDS Size */ 4096 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4097 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4098 WRITE_DATA_DST_SEL(0))); 4099 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size); 4100 amdgpu_ring_write(ring, 0); 4101 amdgpu_ring_write(ring, gds_size); 4102 4103 /* GWS */ 4104 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4105 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4106 WRITE_DATA_DST_SEL(0))); 4107 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws); 4108 amdgpu_ring_write(ring, 0); 4109 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4110 4111 /* OA */ 4112 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4113 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4114 WRITE_DATA_DST_SEL(0))); 4115 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa); 4116 amdgpu_ring_write(ring, 0); 4117 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); 4118 } 4119 4120 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 4121 { 4122 struct amdgpu_device *adev = ring->adev; 4123 uint32_t value = 0; 4124 4125 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4126 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4127 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4128 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4129 WREG32(mmSQ_CMD, value); 4130 } 4131 4132 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 4133 { 4134 WREG32(mmSQ_IND_INDEX, 4135 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4136 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4137 (address << SQ_IND_INDEX__INDEX__SHIFT) | 4138 (SQ_IND_INDEX__FORCE_READ_MASK)); 4139 return RREG32(mmSQ_IND_DATA); 4140 } 4141 4142 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 4143 uint32_t wave, uint32_t thread, 4144 uint32_t regno, uint32_t num, uint32_t *out) 4145 { 4146 WREG32(mmSQ_IND_INDEX, 4147 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4148 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4149 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4150 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 4151 (SQ_IND_INDEX__FORCE_READ_MASK) | 4152 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4153 while (num--) 4154 *(out++) = RREG32(mmSQ_IND_DATA); 4155 } 4156 4157 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4158 { 4159 /* type 0 wave data */ 4160 dst[(*no_fields)++] = 0; 4161 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4162 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4163 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4164 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4165 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 4166 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 4167 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 4168 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 4169 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 4170 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 4171 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 4172 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 4173 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 4174 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 4175 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 4176 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 4177 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 4178 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4179 } 4180 4181 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4182 uint32_t wave, uint32_t start, 4183 uint32_t size, uint32_t *dst) 4184 { 4185 wave_read_regs( 4186 adev, simd, wave, 0, 4187 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 4188 } 4189 4190 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, 4191 u32 me, u32 pipe, u32 q, u32 vm) 4192 { 4193 cik_srbm_select(adev, me, pipe, q, vm); 4194 } 4195 4196 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4197 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4198 .select_se_sh = &gfx_v7_0_select_se_sh, 4199 .read_wave_data = &gfx_v7_0_read_wave_data, 4200 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, 4201 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q 4202 }; 4203 4204 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4205 .is_rlc_enabled = gfx_v7_0_is_rlc_enabled, 4206 .set_safe_mode = gfx_v7_0_set_safe_mode, 4207 .unset_safe_mode = gfx_v7_0_unset_safe_mode, 4208 .init = gfx_v7_0_rlc_init, 4209 .get_csb_size = gfx_v7_0_get_csb_size, 4210 .get_csb_buffer = gfx_v7_0_get_csb_buffer, 4211 .get_cp_table_num = gfx_v7_0_cp_pg_table_num, 4212 .resume = gfx_v7_0_rlc_resume, 4213 .stop = gfx_v7_0_rlc_stop, 4214 .reset = gfx_v7_0_rlc_reset, 4215 .start = gfx_v7_0_rlc_start 4216 }; 4217 4218 static int gfx_v7_0_early_init(void *handle) 4219 { 4220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4221 4222 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; 4223 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4224 adev->gfx.funcs = &gfx_v7_0_gfx_funcs; 4225 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; 4226 gfx_v7_0_set_ring_funcs(adev); 4227 gfx_v7_0_set_irq_funcs(adev); 4228 gfx_v7_0_set_gds_init(adev); 4229 4230 return 0; 4231 } 4232 4233 static int gfx_v7_0_late_init(void *handle) 4234 { 4235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4236 int r; 4237 4238 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4239 if (r) 4240 return r; 4241 4242 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4243 if (r) 4244 return r; 4245 4246 return 0; 4247 } 4248 4249 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev) 4250 { 4251 u32 gb_addr_config; 4252 u32 mc_shared_chmap, mc_arb_ramcfg; 4253 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; 4254 u32 tmp; 4255 4256 switch (adev->asic_type) { 4257 case CHIP_BONAIRE: 4258 adev->gfx.config.max_shader_engines = 2; 4259 adev->gfx.config.max_tile_pipes = 4; 4260 adev->gfx.config.max_cu_per_sh = 7; 4261 adev->gfx.config.max_sh_per_se = 1; 4262 adev->gfx.config.max_backends_per_se = 2; 4263 adev->gfx.config.max_texture_channel_caches = 4; 4264 adev->gfx.config.max_gprs = 256; 4265 adev->gfx.config.max_gs_threads = 32; 4266 adev->gfx.config.max_hw_contexts = 8; 4267 4268 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4269 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4270 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4271 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4272 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4273 break; 4274 case CHIP_HAWAII: 4275 adev->gfx.config.max_shader_engines = 4; 4276 adev->gfx.config.max_tile_pipes = 16; 4277 adev->gfx.config.max_cu_per_sh = 11; 4278 adev->gfx.config.max_sh_per_se = 1; 4279 adev->gfx.config.max_backends_per_se = 4; 4280 adev->gfx.config.max_texture_channel_caches = 16; 4281 adev->gfx.config.max_gprs = 256; 4282 adev->gfx.config.max_gs_threads = 32; 4283 adev->gfx.config.max_hw_contexts = 8; 4284 4285 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4286 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4287 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4288 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4289 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN; 4290 break; 4291 case CHIP_KAVERI: 4292 adev->gfx.config.max_shader_engines = 1; 4293 adev->gfx.config.max_tile_pipes = 4; 4294 adev->gfx.config.max_cu_per_sh = 8; 4295 adev->gfx.config.max_backends_per_se = 2; 4296 adev->gfx.config.max_sh_per_se = 1; 4297 adev->gfx.config.max_texture_channel_caches = 4; 4298 adev->gfx.config.max_gprs = 256; 4299 adev->gfx.config.max_gs_threads = 16; 4300 adev->gfx.config.max_hw_contexts = 8; 4301 4302 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4303 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4304 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4305 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4306 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4307 break; 4308 case CHIP_KABINI: 4309 case CHIP_MULLINS: 4310 default: 4311 adev->gfx.config.max_shader_engines = 1; 4312 adev->gfx.config.max_tile_pipes = 2; 4313 adev->gfx.config.max_cu_per_sh = 2; 4314 adev->gfx.config.max_sh_per_se = 1; 4315 adev->gfx.config.max_backends_per_se = 1; 4316 adev->gfx.config.max_texture_channel_caches = 2; 4317 adev->gfx.config.max_gprs = 256; 4318 adev->gfx.config.max_gs_threads = 16; 4319 adev->gfx.config.max_hw_contexts = 8; 4320 4321 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4322 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4323 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4324 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 4325 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 4326 break; 4327 } 4328 4329 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 4330 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 4331 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 4332 4333 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 4334 adev->gfx.config.mem_max_burst_length_bytes = 256; 4335 if (adev->flags & AMD_IS_APU) { 4336 /* Get memory bank mapping mode. */ 4337 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 4338 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4339 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4340 4341 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); 4342 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 4343 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); 4344 4345 /* Validate settings in case only one DIMM installed. */ 4346 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) 4347 dimm00_addr_map = 0; 4348 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) 4349 dimm01_addr_map = 0; 4350 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) 4351 dimm10_addr_map = 0; 4352 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) 4353 dimm11_addr_map = 0; 4354 4355 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ 4356 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ 4357 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) 4358 adev->gfx.config.mem_row_size_in_kb = 2; 4359 else 4360 adev->gfx.config.mem_row_size_in_kb = 1; 4361 } else { 4362 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 4363 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 4364 if (adev->gfx.config.mem_row_size_in_kb > 4) 4365 adev->gfx.config.mem_row_size_in_kb = 4; 4366 } 4367 /* XXX use MC settings? */ 4368 adev->gfx.config.shader_engine_tile_size = 32; 4369 adev->gfx.config.num_gpus = 1; 4370 adev->gfx.config.multi_gpu_tile_size = 64; 4371 4372 /* fix up row size */ 4373 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 4374 switch (adev->gfx.config.mem_row_size_in_kb) { 4375 case 1: 4376 default: 4377 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4378 break; 4379 case 2: 4380 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4381 break; 4382 case 4: 4383 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); 4384 break; 4385 } 4386 adev->gfx.config.gb_addr_config = gb_addr_config; 4387 } 4388 4389 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4390 int mec, int pipe, int queue) 4391 { 4392 int r; 4393 unsigned irq_type; 4394 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 4395 4396 /* mec0 is me1 */ 4397 ring->me = mec + 1; 4398 ring->pipe = pipe; 4399 ring->queue = queue; 4400 4401 ring->ring_obj = NULL; 4402 ring->use_doorbell = true; 4403 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; 4404 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4405 4406 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4407 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4408 + ring->pipe; 4409 4410 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4411 r = amdgpu_ring_init(adev, ring, 1024, 4412 &adev->gfx.eop_irq, irq_type); 4413 if (r) 4414 return r; 4415 4416 4417 return 0; 4418 } 4419 4420 static int gfx_v7_0_sw_init(void *handle) 4421 { 4422 struct amdgpu_ring *ring; 4423 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4424 int i, j, k, r, ring_id; 4425 4426 switch (adev->asic_type) { 4427 case CHIP_KAVERI: 4428 adev->gfx.mec.num_mec = 2; 4429 break; 4430 case CHIP_BONAIRE: 4431 case CHIP_HAWAII: 4432 case CHIP_KABINI: 4433 case CHIP_MULLINS: 4434 default: 4435 adev->gfx.mec.num_mec = 1; 4436 break; 4437 } 4438 adev->gfx.mec.num_pipe_per_mec = 4; 4439 adev->gfx.mec.num_queue_per_pipe = 8; 4440 4441 /* EOP Event */ 4442 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 4443 if (r) 4444 return r; 4445 4446 /* Privileged reg */ 4447 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, 4448 &adev->gfx.priv_reg_irq); 4449 if (r) 4450 return r; 4451 4452 /* Privileged inst */ 4453 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, 4454 &adev->gfx.priv_inst_irq); 4455 if (r) 4456 return r; 4457 4458 gfx_v7_0_scratch_init(adev); 4459 4460 r = gfx_v7_0_init_microcode(adev); 4461 if (r) { 4462 DRM_ERROR("Failed to load gfx firmware!\n"); 4463 return r; 4464 } 4465 4466 r = adev->gfx.rlc.funcs->init(adev); 4467 if (r) { 4468 DRM_ERROR("Failed to init rlc BOs!\n"); 4469 return r; 4470 } 4471 4472 /* allocate mec buffers */ 4473 r = gfx_v7_0_mec_init(adev); 4474 if (r) { 4475 DRM_ERROR("Failed to init MEC BOs!\n"); 4476 return r; 4477 } 4478 4479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4480 ring = &adev->gfx.gfx_ring[i]; 4481 ring->ring_obj = NULL; 4482 sprintf(ring->name, "gfx"); 4483 r = amdgpu_ring_init(adev, ring, 1024, 4484 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); 4485 if (r) 4486 return r; 4487 } 4488 4489 /* set up the compute queues - allocate horizontally across pipes */ 4490 ring_id = 0; 4491 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4492 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4493 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4494 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 4495 continue; 4496 4497 r = gfx_v7_0_compute_ring_init(adev, 4498 ring_id, 4499 i, k, j); 4500 if (r) 4501 return r; 4502 4503 ring_id++; 4504 } 4505 } 4506 } 4507 4508 adev->gfx.ce_ram_size = 0x8000; 4509 4510 gfx_v7_0_gpu_early_init(adev); 4511 4512 return r; 4513 } 4514 4515 static int gfx_v7_0_sw_fini(void *handle) 4516 { 4517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4518 int i; 4519 4520 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4521 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4522 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4523 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4524 4525 gfx_v7_0_cp_compute_fini(adev); 4526 amdgpu_gfx_rlc_fini(adev); 4527 gfx_v7_0_mec_fini(adev); 4528 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4529 &adev->gfx.rlc.clear_state_gpu_addr, 4530 (void **)&adev->gfx.rlc.cs_ptr); 4531 if (adev->gfx.rlc.cp_table_size) { 4532 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4533 &adev->gfx.rlc.cp_table_gpu_addr, 4534 (void **)&adev->gfx.rlc.cp_table_ptr); 4535 } 4536 gfx_v7_0_free_microcode(adev); 4537 4538 return 0; 4539 } 4540 4541 static int gfx_v7_0_hw_init(void *handle) 4542 { 4543 int r; 4544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4545 4546 gfx_v7_0_constants_init(adev); 4547 4548 /* init rlc */ 4549 r = adev->gfx.rlc.funcs->resume(adev); 4550 if (r) 4551 return r; 4552 4553 r = gfx_v7_0_cp_resume(adev); 4554 if (r) 4555 return r; 4556 4557 return r; 4558 } 4559 4560 static int gfx_v7_0_hw_fini(void *handle) 4561 { 4562 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4563 4564 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4565 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4566 gfx_v7_0_cp_enable(adev, false); 4567 adev->gfx.rlc.funcs->stop(adev); 4568 gfx_v7_0_fini_pg(adev); 4569 4570 return 0; 4571 } 4572 4573 static int gfx_v7_0_suspend(void *handle) 4574 { 4575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4576 4577 return gfx_v7_0_hw_fini(adev); 4578 } 4579 4580 static int gfx_v7_0_resume(void *handle) 4581 { 4582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4583 4584 return gfx_v7_0_hw_init(adev); 4585 } 4586 4587 static bool gfx_v7_0_is_idle(void *handle) 4588 { 4589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4590 4591 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 4592 return false; 4593 else 4594 return true; 4595 } 4596 4597 static int gfx_v7_0_wait_for_idle(void *handle) 4598 { 4599 unsigned i; 4600 u32 tmp; 4601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4602 4603 for (i = 0; i < adev->usec_timeout; i++) { 4604 /* read MC_STATUS */ 4605 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; 4606 4607 if (!tmp) 4608 return 0; 4609 udelay(1); 4610 } 4611 return -ETIMEDOUT; 4612 } 4613 4614 static int gfx_v7_0_soft_reset(void *handle) 4615 { 4616 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4617 u32 tmp; 4618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4619 4620 /* GRBM_STATUS */ 4621 tmp = RREG32(mmGRBM_STATUS); 4622 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4623 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4624 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4625 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4626 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4627 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 4628 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 4629 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 4630 4631 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4632 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 4633 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4634 } 4635 4636 /* GRBM_STATUS2 */ 4637 tmp = RREG32(mmGRBM_STATUS2); 4638 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 4639 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 4640 4641 /* SRBM_STATUS */ 4642 tmp = RREG32(mmSRBM_STATUS); 4643 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 4644 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4645 4646 if (grbm_soft_reset || srbm_soft_reset) { 4647 /* disable CG/PG */ 4648 gfx_v7_0_fini_pg(adev); 4649 gfx_v7_0_update_cg(adev, false); 4650 4651 /* stop the rlc */ 4652 adev->gfx.rlc.funcs->stop(adev); 4653 4654 /* Disable GFX parsing/prefetching */ 4655 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 4656 4657 /* Disable MEC parsing/prefetching */ 4658 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 4659 4660 if (grbm_soft_reset) { 4661 tmp = RREG32(mmGRBM_SOFT_RESET); 4662 tmp |= grbm_soft_reset; 4663 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4664 WREG32(mmGRBM_SOFT_RESET, tmp); 4665 tmp = RREG32(mmGRBM_SOFT_RESET); 4666 4667 udelay(50); 4668 4669 tmp &= ~grbm_soft_reset; 4670 WREG32(mmGRBM_SOFT_RESET, tmp); 4671 tmp = RREG32(mmGRBM_SOFT_RESET); 4672 } 4673 4674 if (srbm_soft_reset) { 4675 tmp = RREG32(mmSRBM_SOFT_RESET); 4676 tmp |= srbm_soft_reset; 4677 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 4678 WREG32(mmSRBM_SOFT_RESET, tmp); 4679 tmp = RREG32(mmSRBM_SOFT_RESET); 4680 4681 udelay(50); 4682 4683 tmp &= ~srbm_soft_reset; 4684 WREG32(mmSRBM_SOFT_RESET, tmp); 4685 tmp = RREG32(mmSRBM_SOFT_RESET); 4686 } 4687 /* Wait a little for things to settle down */ 4688 udelay(50); 4689 } 4690 return 0; 4691 } 4692 4693 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4694 enum amdgpu_interrupt_state state) 4695 { 4696 u32 cp_int_cntl; 4697 4698 switch (state) { 4699 case AMDGPU_IRQ_STATE_DISABLE: 4700 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4701 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4702 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4703 break; 4704 case AMDGPU_IRQ_STATE_ENABLE: 4705 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4706 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4707 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4708 break; 4709 default: 4710 break; 4711 } 4712 } 4713 4714 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4715 int me, int pipe, 4716 enum amdgpu_interrupt_state state) 4717 { 4718 u32 mec_int_cntl, mec_int_cntl_reg; 4719 4720 /* 4721 * amdgpu controls only the first MEC. That's why this function only 4722 * handles the setting of interrupts for this specific MEC. All other 4723 * pipes' interrupts are set by amdkfd. 4724 */ 4725 4726 if (me == 1) { 4727 switch (pipe) { 4728 case 0: 4729 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL; 4730 break; 4731 case 1: 4732 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; 4733 break; 4734 case 2: 4735 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL; 4736 break; 4737 case 3: 4738 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL; 4739 break; 4740 default: 4741 DRM_DEBUG("invalid pipe %d\n", pipe); 4742 return; 4743 } 4744 } else { 4745 DRM_DEBUG("invalid me %d\n", me); 4746 return; 4747 } 4748 4749 switch (state) { 4750 case AMDGPU_IRQ_STATE_DISABLE: 4751 mec_int_cntl = RREG32(mec_int_cntl_reg); 4752 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4753 WREG32(mec_int_cntl_reg, mec_int_cntl); 4754 break; 4755 case AMDGPU_IRQ_STATE_ENABLE: 4756 mec_int_cntl = RREG32(mec_int_cntl_reg); 4757 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4758 WREG32(mec_int_cntl_reg, mec_int_cntl); 4759 break; 4760 default: 4761 break; 4762 } 4763 } 4764 4765 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4766 struct amdgpu_irq_src *src, 4767 unsigned type, 4768 enum amdgpu_interrupt_state state) 4769 { 4770 u32 cp_int_cntl; 4771 4772 switch (state) { 4773 case AMDGPU_IRQ_STATE_DISABLE: 4774 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4775 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4776 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4777 break; 4778 case AMDGPU_IRQ_STATE_ENABLE: 4779 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4780 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 4781 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4782 break; 4783 default: 4784 break; 4785 } 4786 4787 return 0; 4788 } 4789 4790 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4791 struct amdgpu_irq_src *src, 4792 unsigned type, 4793 enum amdgpu_interrupt_state state) 4794 { 4795 u32 cp_int_cntl; 4796 4797 switch (state) { 4798 case AMDGPU_IRQ_STATE_DISABLE: 4799 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4800 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4801 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4802 break; 4803 case AMDGPU_IRQ_STATE_ENABLE: 4804 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4805 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 4806 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4807 break; 4808 default: 4809 break; 4810 } 4811 4812 return 0; 4813 } 4814 4815 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4816 struct amdgpu_irq_src *src, 4817 unsigned type, 4818 enum amdgpu_interrupt_state state) 4819 { 4820 switch (type) { 4821 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4822 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state); 4823 break; 4824 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4825 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4826 break; 4827 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4828 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4829 break; 4830 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4831 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4832 break; 4833 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4834 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4835 break; 4836 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4837 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4838 break; 4839 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4840 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4841 break; 4842 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4843 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4844 break; 4845 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4846 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4847 break; 4848 default: 4849 break; 4850 } 4851 return 0; 4852 } 4853 4854 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev, 4855 struct amdgpu_irq_src *source, 4856 struct amdgpu_iv_entry *entry) 4857 { 4858 u8 me_id, pipe_id; 4859 struct amdgpu_ring *ring; 4860 int i; 4861 4862 DRM_DEBUG("IH: CP EOP\n"); 4863 me_id = (entry->ring_id & 0x0c) >> 2; 4864 pipe_id = (entry->ring_id & 0x03) >> 0; 4865 switch (me_id) { 4866 case 0: 4867 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4868 break; 4869 case 1: 4870 case 2: 4871 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4872 ring = &adev->gfx.compute_ring[i]; 4873 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4874 amdgpu_fence_process(ring); 4875 } 4876 break; 4877 } 4878 return 0; 4879 } 4880 4881 static void gfx_v7_0_fault(struct amdgpu_device *adev, 4882 struct amdgpu_iv_entry *entry) 4883 { 4884 struct amdgpu_ring *ring; 4885 u8 me_id, pipe_id; 4886 int i; 4887 4888 me_id = (entry->ring_id & 0x0c) >> 2; 4889 pipe_id = (entry->ring_id & 0x03) >> 0; 4890 switch (me_id) { 4891 case 0: 4892 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 4893 break; 4894 case 1: 4895 case 2: 4896 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4897 ring = &adev->gfx.compute_ring[i]; 4898 if ((ring->me == me_id) && (ring->pipe == pipe_id)) 4899 drm_sched_fault(&ring->sched); 4900 } 4901 break; 4902 } 4903 } 4904 4905 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev, 4906 struct amdgpu_irq_src *source, 4907 struct amdgpu_iv_entry *entry) 4908 { 4909 DRM_ERROR("Illegal register access in command stream\n"); 4910 gfx_v7_0_fault(adev, entry); 4911 return 0; 4912 } 4913 4914 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev, 4915 struct amdgpu_irq_src *source, 4916 struct amdgpu_iv_entry *entry) 4917 { 4918 DRM_ERROR("Illegal instruction in command stream\n"); 4919 // XXX soft reset the gfx block only 4920 gfx_v7_0_fault(adev, entry); 4921 return 0; 4922 } 4923 4924 static int gfx_v7_0_set_clockgating_state(void *handle, 4925 enum amd_clockgating_state state) 4926 { 4927 bool gate = false; 4928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4929 4930 if (state == AMD_CG_STATE_GATE) 4931 gate = true; 4932 4933 gfx_v7_0_enable_gui_idle_interrupt(adev, false); 4934 /* order matters! */ 4935 if (gate) { 4936 gfx_v7_0_enable_mgcg(adev, true); 4937 gfx_v7_0_enable_cgcg(adev, true); 4938 } else { 4939 gfx_v7_0_enable_cgcg(adev, false); 4940 gfx_v7_0_enable_mgcg(adev, false); 4941 } 4942 gfx_v7_0_enable_gui_idle_interrupt(adev, true); 4943 4944 return 0; 4945 } 4946 4947 static int gfx_v7_0_set_powergating_state(void *handle, 4948 enum amd_powergating_state state) 4949 { 4950 bool gate = false; 4951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4952 4953 if (state == AMD_PG_STATE_GATE) 4954 gate = true; 4955 4956 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 4957 AMD_PG_SUPPORT_GFX_SMG | 4958 AMD_PG_SUPPORT_GFX_DMG | 4959 AMD_PG_SUPPORT_CP | 4960 AMD_PG_SUPPORT_GDS | 4961 AMD_PG_SUPPORT_RLC_SMU_HS)) { 4962 gfx_v7_0_update_gfx_pg(adev, gate); 4963 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 4964 gfx_v7_0_enable_cp_pg(adev, gate); 4965 gfx_v7_0_enable_gds_pg(adev, gate); 4966 } 4967 } 4968 4969 return 0; 4970 } 4971 4972 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 4973 .name = "gfx_v7_0", 4974 .early_init = gfx_v7_0_early_init, 4975 .late_init = gfx_v7_0_late_init, 4976 .sw_init = gfx_v7_0_sw_init, 4977 .sw_fini = gfx_v7_0_sw_fini, 4978 .hw_init = gfx_v7_0_hw_init, 4979 .hw_fini = gfx_v7_0_hw_fini, 4980 .suspend = gfx_v7_0_suspend, 4981 .resume = gfx_v7_0_resume, 4982 .is_idle = gfx_v7_0_is_idle, 4983 .wait_for_idle = gfx_v7_0_wait_for_idle, 4984 .soft_reset = gfx_v7_0_soft_reset, 4985 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 4986 .set_powergating_state = gfx_v7_0_set_powergating_state, 4987 }; 4988 4989 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 4990 .type = AMDGPU_RING_TYPE_GFX, 4991 .align_mask = 0xff, 4992 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4993 .support_64bit_ptrs = false, 4994 .get_rptr = gfx_v7_0_ring_get_rptr, 4995 .get_wptr = gfx_v7_0_ring_get_wptr_gfx, 4996 .set_wptr = gfx_v7_0_ring_set_wptr_gfx, 4997 .emit_frame_size = 4998 20 + /* gfx_v7_0_ring_emit_gds_switch */ 4999 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5000 5 + /* hdp invalidate */ 5001 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ 5002 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5003 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ 5004 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/ 5005 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ 5006 .emit_ib = gfx_v7_0_ring_emit_ib_gfx, 5007 .emit_fence = gfx_v7_0_ring_emit_fence_gfx, 5008 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5009 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5010 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5011 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5012 .test_ring = gfx_v7_0_ring_test_ring, 5013 .test_ib = gfx_v7_0_ring_test_ib, 5014 .insert_nop = amdgpu_ring_insert_nop, 5015 .pad_ib = amdgpu_ring_generic_pad_ib, 5016 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, 5017 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5018 .soft_recovery = gfx_v7_0_ring_soft_recovery, 5019 }; 5020 5021 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { 5022 .type = AMDGPU_RING_TYPE_COMPUTE, 5023 .align_mask = 0xff, 5024 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5025 .support_64bit_ptrs = false, 5026 .get_rptr = gfx_v7_0_ring_get_rptr, 5027 .get_wptr = gfx_v7_0_ring_get_wptr_compute, 5028 .set_wptr = gfx_v7_0_ring_set_wptr_compute, 5029 .emit_frame_size = 5030 20 + /* gfx_v7_0_ring_emit_gds_switch */ 5031 7 + /* gfx_v7_0_ring_emit_hdp_flush */ 5032 5 + /* hdp invalidate */ 5033 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ 5034 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ 5035 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ 5036 .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */ 5037 .emit_ib = gfx_v7_0_ring_emit_ib_compute, 5038 .emit_fence = gfx_v7_0_ring_emit_fence_compute, 5039 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, 5040 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, 5041 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, 5042 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, 5043 .test_ring = gfx_v7_0_ring_test_ring, 5044 .test_ib = gfx_v7_0_ring_test_ib, 5045 .insert_nop = amdgpu_ring_insert_nop, 5046 .pad_ib = amdgpu_ring_generic_pad_ib, 5047 .emit_wreg = gfx_v7_0_ring_emit_wreg, 5048 }; 5049 5050 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) 5051 { 5052 int i; 5053 5054 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5055 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; 5056 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5057 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; 5058 } 5059 5060 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = { 5061 .set = gfx_v7_0_set_eop_interrupt_state, 5062 .process = gfx_v7_0_eop_irq, 5063 }; 5064 5065 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = { 5066 .set = gfx_v7_0_set_priv_reg_fault_state, 5067 .process = gfx_v7_0_priv_reg_irq, 5068 }; 5069 5070 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = { 5071 .set = gfx_v7_0_set_priv_inst_fault_state, 5072 .process = gfx_v7_0_priv_inst_irq, 5073 }; 5074 5075 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev) 5076 { 5077 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5078 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; 5079 5080 adev->gfx.priv_reg_irq.num_types = 1; 5081 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; 5082 5083 adev->gfx.priv_inst_irq.num_types = 1; 5084 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; 5085 } 5086 5087 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 5088 { 5089 /* init asci gds info */ 5090 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); 5091 adev->gds.gws_size = 64; 5092 adev->gds.oa_size = 16; 5093 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); 5094 } 5095 5096 5097 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) 5098 { 5099 int i, j, k, counter, active_cu_number = 0; 5100 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5101 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 5102 unsigned disable_masks[4 * 2]; 5103 u32 ao_cu_num; 5104 5105 if (adev->flags & AMD_IS_APU) 5106 ao_cu_num = 2; 5107 else 5108 ao_cu_num = adev->gfx.config.max_cu_per_sh; 5109 5110 memset(cu_info, 0, sizeof(*cu_info)); 5111 5112 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5113 5114 mutex_lock(&adev->grbm_idx_mutex); 5115 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5116 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5117 mask = 1; 5118 ao_bitmap = 0; 5119 counter = 0; 5120 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5121 if (i < 4 && j < 2) 5122 gfx_v7_0_set_user_cu_inactive_bitmap( 5123 adev, disable_masks[i * 2 + j]); 5124 bitmap = gfx_v7_0_get_cu_active_bitmap(adev); 5125 cu_info->bitmap[i][j] = bitmap; 5126 5127 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 5128 if (bitmap & mask) { 5129 if (counter < ao_cu_num) 5130 ao_bitmap |= mask; 5131 counter ++; 5132 } 5133 mask <<= 1; 5134 } 5135 active_cu_number += counter; 5136 if (i < 2 && j < 2) 5137 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5138 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5139 } 5140 } 5141 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5142 mutex_unlock(&adev->grbm_idx_mutex); 5143 5144 cu_info->number = active_cu_number; 5145 cu_info->ao_cu_mask = ao_cu_mask; 5146 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5147 cu_info->max_waves_per_simd = 10; 5148 cu_info->max_scratch_slots_per_cu = 32; 5149 cu_info->wave_front_size = 64; 5150 cu_info->lds_size = 64; 5151 } 5152 5153 const struct amdgpu_ip_block_version gfx_v7_0_ip_block = 5154 { 5155 .type = AMD_IP_BLOCK_TYPE_GFX, 5156 .major = 7, 5157 .minor = 0, 5158 .rev = 0, 5159 .funcs = &gfx_v7_0_ip_funcs, 5160 }; 5161 5162 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = 5163 { 5164 .type = AMD_IP_BLOCK_TYPE_GFX, 5165 .major = 7, 5166 .minor = 1, 5167 .rev = 0, 5168 .funcs = &gfx_v7_0_ip_funcs, 5169 }; 5170 5171 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = 5172 { 5173 .type = AMD_IP_BLOCK_TYPE_GFX, 5174 .major = 7, 5175 .minor = 2, 5176 .rev = 0, 5177 .funcs = &gfx_v7_0_ip_funcs, 5178 }; 5179 5180 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = 5181 { 5182 .type = AMD_IP_BLOCK_TYPE_GFX, 5183 .major = 7, 5184 .minor = 3, 5185 .rev = 0, 5186 .funcs = &gfx_v7_0_ip_funcs, 5187 }; 5188