1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "amdgpu_gfx.h" 27 #include "amdgpu_ucode.h" 28 #include "clearstate_si.h" 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gca/gfx_6_0_d.h" 34 #include "gca/gfx_6_0_sh_mask.h" 35 #include "gmc/gmc_6_0_d.h" 36 #include "gmc/gmc_6_0_sh_mask.h" 37 #include "dce/dce_6_0_d.h" 38 #include "dce/dce_6_0_sh_mask.h" 39 #include "gca/gfx_7_2_enum.h" 40 #include "si_enums.h" 41 42 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 43 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 44 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 45 46 MODULE_FIRMWARE("radeon/tahiti_pfp.bin"); 47 MODULE_FIRMWARE("radeon/tahiti_me.bin"); 48 MODULE_FIRMWARE("radeon/tahiti_ce.bin"); 49 MODULE_FIRMWARE("radeon/tahiti_rlc.bin"); 50 51 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin"); 52 MODULE_FIRMWARE("radeon/pitcairn_me.bin"); 53 MODULE_FIRMWARE("radeon/pitcairn_ce.bin"); 54 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin"); 55 56 MODULE_FIRMWARE("radeon/verde_pfp.bin"); 57 MODULE_FIRMWARE("radeon/verde_me.bin"); 58 MODULE_FIRMWARE("radeon/verde_ce.bin"); 59 MODULE_FIRMWARE("radeon/verde_rlc.bin"); 60 61 MODULE_FIRMWARE("radeon/oland_pfp.bin"); 62 MODULE_FIRMWARE("radeon/oland_me.bin"); 63 MODULE_FIRMWARE("radeon/oland_ce.bin"); 64 MODULE_FIRMWARE("radeon/oland_rlc.bin"); 65 66 MODULE_FIRMWARE("radeon/hainan_pfp.bin"); 67 MODULE_FIRMWARE("radeon/hainan_me.bin"); 68 MODULE_FIRMWARE("radeon/hainan_ce.bin"); 69 MODULE_FIRMWARE("radeon/hainan_rlc.bin"); 70 71 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 72 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 73 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 74 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 75 76 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 77 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 78 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 79 #define MICRO_TILE_MODE(x) ((x) << 0) 80 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 81 #define BANK_WIDTH(x) ((x) << 14) 82 #define BANK_HEIGHT(x) ((x) << 16) 83 #define MACRO_TILE_ASPECT(x) ((x) << 18) 84 #define NUM_BANKS(x) ((x) << 20) 85 86 static const u32 verde_rlc_save_restore_register_list[] = 87 { 88 (0x8000 << 16) | (0x98f4 >> 2), 89 0x00000000, 90 (0x8040 << 16) | (0x98f4 >> 2), 91 0x00000000, 92 (0x8000 << 16) | (0xe80 >> 2), 93 0x00000000, 94 (0x8040 << 16) | (0xe80 >> 2), 95 0x00000000, 96 (0x8000 << 16) | (0x89bc >> 2), 97 0x00000000, 98 (0x8040 << 16) | (0x89bc >> 2), 99 0x00000000, 100 (0x8000 << 16) | (0x8c1c >> 2), 101 0x00000000, 102 (0x8040 << 16) | (0x8c1c >> 2), 103 0x00000000, 104 (0x9c00 << 16) | (0x98f0 >> 2), 105 0x00000000, 106 (0x9c00 << 16) | (0xe7c >> 2), 107 0x00000000, 108 (0x8000 << 16) | (0x9148 >> 2), 109 0x00000000, 110 (0x8040 << 16) | (0x9148 >> 2), 111 0x00000000, 112 (0x9c00 << 16) | (0x9150 >> 2), 113 0x00000000, 114 (0x9c00 << 16) | (0x897c >> 2), 115 0x00000000, 116 (0x9c00 << 16) | (0x8d8c >> 2), 117 0x00000000, 118 (0x9c00 << 16) | (0xac54 >> 2), 119 0X00000000, 120 0x3, 121 (0x9c00 << 16) | (0x98f8 >> 2), 122 0x00000000, 123 (0x9c00 << 16) | (0x9910 >> 2), 124 0x00000000, 125 (0x9c00 << 16) | (0x9914 >> 2), 126 0x00000000, 127 (0x9c00 << 16) | (0x9918 >> 2), 128 0x00000000, 129 (0x9c00 << 16) | (0x991c >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x9920 >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x9924 >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0x9928 >> 2), 136 0x00000000, 137 (0x9c00 << 16) | (0x992c >> 2), 138 0x00000000, 139 (0x9c00 << 16) | (0x9930 >> 2), 140 0x00000000, 141 (0x9c00 << 16) | (0x9934 >> 2), 142 0x00000000, 143 (0x9c00 << 16) | (0x9938 >> 2), 144 0x00000000, 145 (0x9c00 << 16) | (0x993c >> 2), 146 0x00000000, 147 (0x9c00 << 16) | (0x9940 >> 2), 148 0x00000000, 149 (0x9c00 << 16) | (0x9944 >> 2), 150 0x00000000, 151 (0x9c00 << 16) | (0x9948 >> 2), 152 0x00000000, 153 (0x9c00 << 16) | (0x994c >> 2), 154 0x00000000, 155 (0x9c00 << 16) | (0x9950 >> 2), 156 0x00000000, 157 (0x9c00 << 16) | (0x9954 >> 2), 158 0x00000000, 159 (0x9c00 << 16) | (0x9958 >> 2), 160 0x00000000, 161 (0x9c00 << 16) | (0x995c >> 2), 162 0x00000000, 163 (0x9c00 << 16) | (0x9960 >> 2), 164 0x00000000, 165 (0x9c00 << 16) | (0x9964 >> 2), 166 0x00000000, 167 (0x9c00 << 16) | (0x9968 >> 2), 168 0x00000000, 169 (0x9c00 << 16) | (0x996c >> 2), 170 0x00000000, 171 (0x9c00 << 16) | (0x9970 >> 2), 172 0x00000000, 173 (0x9c00 << 16) | (0x9974 >> 2), 174 0x00000000, 175 (0x9c00 << 16) | (0x9978 >> 2), 176 0x00000000, 177 (0x9c00 << 16) | (0x997c >> 2), 178 0x00000000, 179 (0x9c00 << 16) | (0x9980 >> 2), 180 0x00000000, 181 (0x9c00 << 16) | (0x9984 >> 2), 182 0x00000000, 183 (0x9c00 << 16) | (0x9988 >> 2), 184 0x00000000, 185 (0x9c00 << 16) | (0x998c >> 2), 186 0x00000000, 187 (0x9c00 << 16) | (0x8c00 >> 2), 188 0x00000000, 189 (0x9c00 << 16) | (0x8c14 >> 2), 190 0x00000000, 191 (0x9c00 << 16) | (0x8c04 >> 2), 192 0x00000000, 193 (0x9c00 << 16) | (0x8c08 >> 2), 194 0x00000000, 195 (0x8000 << 16) | (0x9b7c >> 2), 196 0x00000000, 197 (0x8040 << 16) | (0x9b7c >> 2), 198 0x00000000, 199 (0x8000 << 16) | (0xe84 >> 2), 200 0x00000000, 201 (0x8040 << 16) | (0xe84 >> 2), 202 0x00000000, 203 (0x8000 << 16) | (0x89c0 >> 2), 204 0x00000000, 205 (0x8040 << 16) | (0x89c0 >> 2), 206 0x00000000, 207 (0x8000 << 16) | (0x914c >> 2), 208 0x00000000, 209 (0x8040 << 16) | (0x914c >> 2), 210 0x00000000, 211 (0x8000 << 16) | (0x8c20 >> 2), 212 0x00000000, 213 (0x8040 << 16) | (0x8c20 >> 2), 214 0x00000000, 215 (0x8000 << 16) | (0x9354 >> 2), 216 0x00000000, 217 (0x8040 << 16) | (0x9354 >> 2), 218 0x00000000, 219 (0x9c00 << 16) | (0x9060 >> 2), 220 0x00000000, 221 (0x9c00 << 16) | (0x9364 >> 2), 222 0x00000000, 223 (0x9c00 << 16) | (0x9100 >> 2), 224 0x00000000, 225 (0x9c00 << 16) | (0x913c >> 2), 226 0x00000000, 227 (0x8000 << 16) | (0x90e0 >> 2), 228 0x00000000, 229 (0x8000 << 16) | (0x90e4 >> 2), 230 0x00000000, 231 (0x8000 << 16) | (0x90e8 >> 2), 232 0x00000000, 233 (0x8040 << 16) | (0x90e0 >> 2), 234 0x00000000, 235 (0x8040 << 16) | (0x90e4 >> 2), 236 0x00000000, 237 (0x8040 << 16) | (0x90e8 >> 2), 238 0x00000000, 239 (0x9c00 << 16) | (0x8bcc >> 2), 240 0x00000000, 241 (0x9c00 << 16) | (0x8b24 >> 2), 242 0x00000000, 243 (0x9c00 << 16) | (0x88c4 >> 2), 244 0x00000000, 245 (0x9c00 << 16) | (0x8e50 >> 2), 246 0x00000000, 247 (0x9c00 << 16) | (0x8c0c >> 2), 248 0x00000000, 249 (0x9c00 << 16) | (0x8e58 >> 2), 250 0x00000000, 251 (0x9c00 << 16) | (0x8e5c >> 2), 252 0x00000000, 253 (0x9c00 << 16) | (0x9508 >> 2), 254 0x00000000, 255 (0x9c00 << 16) | (0x950c >> 2), 256 0x00000000, 257 (0x9c00 << 16) | (0x9494 >> 2), 258 0x00000000, 259 (0x9c00 << 16) | (0xac0c >> 2), 260 0x00000000, 261 (0x9c00 << 16) | (0xac10 >> 2), 262 0x00000000, 263 (0x9c00 << 16) | (0xac14 >> 2), 264 0x00000000, 265 (0x9c00 << 16) | (0xae00 >> 2), 266 0x00000000, 267 (0x9c00 << 16) | (0xac08 >> 2), 268 0x00000000, 269 (0x9c00 << 16) | (0x88d4 >> 2), 270 0x00000000, 271 (0x9c00 << 16) | (0x88c8 >> 2), 272 0x00000000, 273 (0x9c00 << 16) | (0x88cc >> 2), 274 0x00000000, 275 (0x9c00 << 16) | (0x89b0 >> 2), 276 0x00000000, 277 (0x9c00 << 16) | (0x8b10 >> 2), 278 0x00000000, 279 (0x9c00 << 16) | (0x8a14 >> 2), 280 0x00000000, 281 (0x9c00 << 16) | (0x9830 >> 2), 282 0x00000000, 283 (0x9c00 << 16) | (0x9834 >> 2), 284 0x00000000, 285 (0x9c00 << 16) | (0x9838 >> 2), 286 0x00000000, 287 (0x9c00 << 16) | (0x9a10 >> 2), 288 0x00000000, 289 (0x8000 << 16) | (0x9870 >> 2), 290 0x00000000, 291 (0x8000 << 16) | (0x9874 >> 2), 292 0x00000000, 293 (0x8001 << 16) | (0x9870 >> 2), 294 0x00000000, 295 (0x8001 << 16) | (0x9874 >> 2), 296 0x00000000, 297 (0x8040 << 16) | (0x9870 >> 2), 298 0x00000000, 299 (0x8040 << 16) | (0x9874 >> 2), 300 0x00000000, 301 (0x8041 << 16) | (0x9870 >> 2), 302 0x00000000, 303 (0x8041 << 16) | (0x9874 >> 2), 304 0x00000000, 305 0x00000000 306 }; 307 308 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 309 { 310 const char *chip_name; 311 char fw_name[30]; 312 int err; 313 const struct gfx_firmware_header_v1_0 *cp_hdr; 314 const struct rlc_firmware_header_v1_0 *rlc_hdr; 315 316 DRM_DEBUG("\n"); 317 318 switch (adev->asic_type) { 319 case CHIP_TAHITI: 320 chip_name = "tahiti"; 321 break; 322 case CHIP_PITCAIRN: 323 chip_name = "pitcairn"; 324 break; 325 case CHIP_VERDE: 326 chip_name = "verde"; 327 break; 328 case CHIP_OLAND: 329 chip_name = "oland"; 330 break; 331 case CHIP_HAINAN: 332 chip_name = "hainan"; 333 break; 334 default: BUG(); 335 } 336 337 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); 338 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 339 if (err) 340 goto out; 341 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 342 if (err) 343 goto out; 344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 347 348 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); 349 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 350 if (err) 351 goto out; 352 err = amdgpu_ucode_validate(adev->gfx.me_fw); 353 if (err) 354 goto out; 355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 356 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 357 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 358 359 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); 360 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 361 if (err) 362 goto out; 363 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 364 if (err) 365 goto out; 366 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 367 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 368 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 369 370 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name); 371 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 372 if (err) 373 goto out; 374 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 375 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 376 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 377 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 378 379 out: 380 if (err) { 381 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 382 release_firmware(adev->gfx.pfp_fw); 383 adev->gfx.pfp_fw = NULL; 384 release_firmware(adev->gfx.me_fw); 385 adev->gfx.me_fw = NULL; 386 release_firmware(adev->gfx.ce_fw); 387 adev->gfx.ce_fw = NULL; 388 release_firmware(adev->gfx.rlc_fw); 389 adev->gfx.rlc_fw = NULL; 390 } 391 return err; 392 } 393 394 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 395 { 396 const u32 num_tile_mode_states = 32; 397 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 398 399 switch (adev->gfx.config.mem_row_size_in_kb) { 400 case 1: 401 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 402 break; 403 case 2: 404 default: 405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 406 break; 407 case 4: 408 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 409 break; 410 } 411 412 if (adev->asic_type == CHIP_VERDE) { 413 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 414 switch (reg_offset) { 415 case 0: 416 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 418 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 419 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 420 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 421 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 422 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 423 NUM_BANKS(ADDR_SURF_16_BANK)); 424 break; 425 case 1: 426 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 427 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 428 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 429 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 430 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 431 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 432 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 433 NUM_BANKS(ADDR_SURF_16_BANK)); 434 break; 435 case 2: 436 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 437 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 438 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 439 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 440 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 441 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 442 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 443 NUM_BANKS(ADDR_SURF_16_BANK)); 444 break; 445 case 3: 446 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 447 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 448 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 449 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 452 NUM_BANKS(ADDR_SURF_8_BANK) | 453 TILE_SPLIT(split_equal_to_row_size)); 454 break; 455 case 4: 456 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 457 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 458 PIPE_CONFIG(ADDR_SURF_P4_8x16)); 459 break; 460 case 5: 461 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 462 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 463 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 464 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 465 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 468 NUM_BANKS(ADDR_SURF_4_BANK)); 469 break; 470 case 6: 471 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 472 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 473 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 474 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 475 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 476 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 477 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 478 NUM_BANKS(ADDR_SURF_4_BANK)); 479 break; 480 case 7: 481 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 482 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 483 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 484 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 485 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 486 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 487 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 488 NUM_BANKS(ADDR_SURF_2_BANK)); 489 break; 490 case 8: 491 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 492 break; 493 case 9: 494 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 495 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 496 PIPE_CONFIG(ADDR_SURF_P4_8x16)); 497 break; 498 case 10: 499 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 500 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 501 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 502 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 503 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 504 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 505 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 506 NUM_BANKS(ADDR_SURF_16_BANK)); 507 break; 508 case 11: 509 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 510 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 511 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 512 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 513 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 516 NUM_BANKS(ADDR_SURF_16_BANK)); 517 break; 518 case 12: 519 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 520 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 521 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 522 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 523 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 526 NUM_BANKS(ADDR_SURF_16_BANK)); 527 break; 528 case 13: 529 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 530 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 531 PIPE_CONFIG(ADDR_SURF_P4_8x16)); 532 break; 533 case 14: 534 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 535 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 536 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 537 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 541 NUM_BANKS(ADDR_SURF_16_BANK)); 542 break; 543 case 15: 544 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 545 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 546 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 547 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 549 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 550 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 551 NUM_BANKS(ADDR_SURF_16_BANK)); 552 break; 553 case 16: 554 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 555 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 556 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 557 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 561 NUM_BANKS(ADDR_SURF_16_BANK)); 562 break; 563 case 17: 564 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 565 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 566 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 567 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 568 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 569 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 570 NUM_BANKS(ADDR_SURF_16_BANK) | 571 TILE_SPLIT(split_equal_to_row_size)); 572 break; 573 case 18: 574 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 575 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 576 PIPE_CONFIG(ADDR_SURF_P4_8x16)); 577 break; 578 case 19: 579 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 580 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 581 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 582 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 583 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 584 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 585 NUM_BANKS(ADDR_SURF_16_BANK) | 586 TILE_SPLIT(split_equal_to_row_size)); 587 break; 588 case 20: 589 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 590 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 591 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 595 NUM_BANKS(ADDR_SURF_16_BANK) | 596 TILE_SPLIT(split_equal_to_row_size)); 597 break; 598 case 21: 599 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 600 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 601 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 602 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 606 NUM_BANKS(ADDR_SURF_8_BANK)); 607 break; 608 case 22: 609 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 610 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 611 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 616 NUM_BANKS(ADDR_SURF_8_BANK)); 617 break; 618 case 23: 619 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 620 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 621 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 622 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 623 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 624 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 625 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 626 NUM_BANKS(ADDR_SURF_4_BANK)); 627 break; 628 case 24: 629 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 631 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 636 NUM_BANKS(ADDR_SURF_4_BANK)); 637 break; 638 case 25: 639 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 640 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 641 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 642 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 643 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 644 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 645 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 646 NUM_BANKS(ADDR_SURF_2_BANK)); 647 break; 648 case 26: 649 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 651 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 656 NUM_BANKS(ADDR_SURF_2_BANK)); 657 break; 658 case 27: 659 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 660 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 661 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 662 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 663 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 666 NUM_BANKS(ADDR_SURF_2_BANK)); 667 break; 668 case 28: 669 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 670 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 671 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 672 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 676 NUM_BANKS(ADDR_SURF_2_BANK)); 677 break; 678 case 29: 679 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 680 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 681 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 682 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 683 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 684 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 685 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 686 NUM_BANKS(ADDR_SURF_2_BANK)); 687 break; 688 case 30: 689 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 691 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 692 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 696 NUM_BANKS(ADDR_SURF_2_BANK)); 697 break; 698 default: 699 continue; 700 } 701 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 702 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 703 } 704 } else if (adev->asic_type == CHIP_OLAND || 705 adev->asic_type == CHIP_HAINAN) { 706 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 707 switch (reg_offset) { 708 case 0: 709 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 710 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 711 PIPE_CONFIG(ADDR_SURF_P2) | 712 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 716 NUM_BANKS(ADDR_SURF_16_BANK)); 717 break; 718 case 1: 719 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 720 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 721 PIPE_CONFIG(ADDR_SURF_P2) | 722 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 723 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 724 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 725 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 726 NUM_BANKS(ADDR_SURF_16_BANK)); 727 break; 728 case 2: 729 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 731 PIPE_CONFIG(ADDR_SURF_P2) | 732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 736 NUM_BANKS(ADDR_SURF_16_BANK)); 737 break; 738 case 3: 739 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 740 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 741 PIPE_CONFIG(ADDR_SURF_P2) | 742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 745 NUM_BANKS(ADDR_SURF_8_BANK) | 746 TILE_SPLIT(split_equal_to_row_size)); 747 break; 748 case 4: 749 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 750 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 751 PIPE_CONFIG(ADDR_SURF_P2)); 752 break; 753 case 5: 754 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 755 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 756 PIPE_CONFIG(ADDR_SURF_P2) | 757 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 761 NUM_BANKS(ADDR_SURF_8_BANK)); 762 break; 763 case 6: 764 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 765 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 766 PIPE_CONFIG(ADDR_SURF_P2) | 767 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 768 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 769 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 770 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 771 NUM_BANKS(ADDR_SURF_8_BANK)); 772 break; 773 case 7: 774 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 775 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 776 PIPE_CONFIG(ADDR_SURF_P2) | 777 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 779 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 780 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 781 NUM_BANKS(ADDR_SURF_4_BANK)); 782 break; 783 case 8: 784 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 785 break; 786 case 9: 787 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 788 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 789 PIPE_CONFIG(ADDR_SURF_P2)); 790 break; 791 case 10: 792 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 793 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 794 PIPE_CONFIG(ADDR_SURF_P2) | 795 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 799 NUM_BANKS(ADDR_SURF_16_BANK)); 800 break; 801 case 11: 802 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 803 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 804 PIPE_CONFIG(ADDR_SURF_P2) | 805 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 809 NUM_BANKS(ADDR_SURF_16_BANK)); 810 break; 811 case 12: 812 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 813 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 814 PIPE_CONFIG(ADDR_SURF_P2) | 815 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 816 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 819 NUM_BANKS(ADDR_SURF_16_BANK)); 820 break; 821 case 13: 822 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 823 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 824 PIPE_CONFIG(ADDR_SURF_P2)); 825 break; 826 case 14: 827 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 828 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 829 PIPE_CONFIG(ADDR_SURF_P2) | 830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 831 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 834 NUM_BANKS(ADDR_SURF_16_BANK)); 835 break; 836 case 15: 837 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 838 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 839 PIPE_CONFIG(ADDR_SURF_P2) | 840 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 841 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 842 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 843 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 844 NUM_BANKS(ADDR_SURF_16_BANK)); 845 break; 846 case 16: 847 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 848 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 849 PIPE_CONFIG(ADDR_SURF_P2) | 850 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 851 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 852 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 853 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 854 NUM_BANKS(ADDR_SURF_16_BANK)); 855 break; 856 case 17: 857 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 858 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 859 PIPE_CONFIG(ADDR_SURF_P2) | 860 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 861 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 862 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 863 NUM_BANKS(ADDR_SURF_16_BANK) | 864 TILE_SPLIT(split_equal_to_row_size)); 865 break; 866 case 18: 867 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 868 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 869 PIPE_CONFIG(ADDR_SURF_P2)); 870 break; 871 case 19: 872 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 873 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 874 PIPE_CONFIG(ADDR_SURF_P2) | 875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 878 NUM_BANKS(ADDR_SURF_16_BANK) | 879 TILE_SPLIT(split_equal_to_row_size)); 880 break; 881 case 20: 882 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 883 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 884 PIPE_CONFIG(ADDR_SURF_P2) | 885 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 886 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 887 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 888 NUM_BANKS(ADDR_SURF_16_BANK) | 889 TILE_SPLIT(split_equal_to_row_size)); 890 break; 891 case 21: 892 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 893 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 894 PIPE_CONFIG(ADDR_SURF_P2) | 895 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 896 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 897 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 898 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 899 NUM_BANKS(ADDR_SURF_8_BANK)); 900 break; 901 case 22: 902 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 903 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 904 PIPE_CONFIG(ADDR_SURF_P2) | 905 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 906 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 907 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 908 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 909 NUM_BANKS(ADDR_SURF_8_BANK)); 910 break; 911 case 23: 912 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 913 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 914 PIPE_CONFIG(ADDR_SURF_P2) | 915 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 916 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 917 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 918 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 919 NUM_BANKS(ADDR_SURF_8_BANK)); 920 break; 921 case 24: 922 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 923 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 924 PIPE_CONFIG(ADDR_SURF_P2) | 925 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 926 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 927 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 928 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 929 NUM_BANKS(ADDR_SURF_8_BANK)); 930 break; 931 case 25: 932 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 934 PIPE_CONFIG(ADDR_SURF_P2) | 935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 939 NUM_BANKS(ADDR_SURF_4_BANK)); 940 break; 941 case 26: 942 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 944 PIPE_CONFIG(ADDR_SURF_P2) | 945 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 946 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 947 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 948 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 949 NUM_BANKS(ADDR_SURF_4_BANK)); 950 break; 951 case 27: 952 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 953 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 954 PIPE_CONFIG(ADDR_SURF_P2) | 955 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 959 NUM_BANKS(ADDR_SURF_4_BANK)); 960 break; 961 case 28: 962 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 963 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 964 PIPE_CONFIG(ADDR_SURF_P2) | 965 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 966 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 967 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 968 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 969 NUM_BANKS(ADDR_SURF_4_BANK)); 970 break; 971 case 29: 972 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 973 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 974 PIPE_CONFIG(ADDR_SURF_P2) | 975 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 976 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 977 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 978 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 979 NUM_BANKS(ADDR_SURF_4_BANK)); 980 break; 981 case 30: 982 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 983 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 984 PIPE_CONFIG(ADDR_SURF_P2) | 985 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 986 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 987 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 988 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 989 NUM_BANKS(ADDR_SURF_4_BANK)); 990 break; 991 default: 992 continue; 993 } 994 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 995 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 996 } 997 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 998 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 999 switch (reg_offset) { 1000 case 0: 1001 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1003 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1008 NUM_BANKS(ADDR_SURF_16_BANK)); 1009 break; 1010 case 1: 1011 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1012 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1013 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1015 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1016 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1017 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1018 NUM_BANKS(ADDR_SURF_16_BANK)); 1019 break; 1020 case 2: 1021 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1022 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1023 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1024 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1025 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1026 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1027 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1028 NUM_BANKS(ADDR_SURF_16_BANK)); 1029 break; 1030 case 3: 1031 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1032 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1033 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1034 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1037 NUM_BANKS(ADDR_SURF_4_BANK) | 1038 TILE_SPLIT(split_equal_to_row_size)); 1039 break; 1040 case 4: 1041 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1042 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1043 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 1044 break; 1045 case 5: 1046 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1047 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1048 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1049 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1050 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1053 NUM_BANKS(ADDR_SURF_2_BANK)); 1054 break; 1055 case 6: 1056 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1057 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1058 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1060 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1063 NUM_BANKS(ADDR_SURF_2_BANK)); 1064 break; 1065 case 7: 1066 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1073 NUM_BANKS(ADDR_SURF_2_BANK)); 1074 break; 1075 case 8: 1076 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)); 1077 break; 1078 case 9: 1079 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1080 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1081 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 1082 break; 1083 case 10: 1084 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1085 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1087 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1088 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1089 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1090 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1091 NUM_BANKS(ADDR_SURF_16_BANK)); 1092 break; 1093 case 11: 1094 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1101 NUM_BANKS(ADDR_SURF_16_BANK)); 1102 break; 1103 case 12: 1104 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1105 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1106 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1107 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1108 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1109 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1110 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1111 NUM_BANKS(ADDR_SURF_16_BANK)); 1112 break; 1113 case 13: 1114 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1115 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1116 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 1117 break; 1118 case 14: 1119 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1120 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1121 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1122 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1123 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1124 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1125 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1126 NUM_BANKS(ADDR_SURF_16_BANK)); 1127 break; 1128 case 15: 1129 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1130 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1131 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1136 NUM_BANKS(ADDR_SURF_16_BANK)); 1137 break; 1138 case 16: 1139 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1140 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1142 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1143 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1144 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1145 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1146 NUM_BANKS(ADDR_SURF_16_BANK)); 1147 break; 1148 case 17: 1149 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1155 NUM_BANKS(ADDR_SURF_16_BANK) | 1156 TILE_SPLIT(split_equal_to_row_size)); 1157 break; 1158 case 18: 1159 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1160 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1161 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16)); 1162 break; 1163 case 19: 1164 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1165 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1167 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1168 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1169 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1170 NUM_BANKS(ADDR_SURF_16_BANK) | 1171 TILE_SPLIT(split_equal_to_row_size)); 1172 break; 1173 case 20: 1174 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1175 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1177 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1180 NUM_BANKS(ADDR_SURF_16_BANK) | 1181 TILE_SPLIT(split_equal_to_row_size)); 1182 break; 1183 case 21: 1184 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1185 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1187 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1191 NUM_BANKS(ADDR_SURF_4_BANK)); 1192 break; 1193 case 22: 1194 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1195 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1196 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1197 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1198 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1201 NUM_BANKS(ADDR_SURF_4_BANK)); 1202 break; 1203 case 23: 1204 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1205 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1206 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1207 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1208 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1211 NUM_BANKS(ADDR_SURF_2_BANK)); 1212 break; 1213 case 24: 1214 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1215 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1216 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1217 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1218 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1221 NUM_BANKS(ADDR_SURF_2_BANK)); 1222 break; 1223 case 25: 1224 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1225 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1226 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1231 NUM_BANKS(ADDR_SURF_2_BANK)); 1232 break; 1233 case 26: 1234 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1235 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1236 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1237 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1241 NUM_BANKS(ADDR_SURF_2_BANK)); 1242 break; 1243 case 27: 1244 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1245 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1246 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1247 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1248 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1249 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1251 NUM_BANKS(ADDR_SURF_2_BANK)); 1252 break; 1253 case 28: 1254 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1255 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1256 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1257 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1258 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1261 NUM_BANKS(ADDR_SURF_2_BANK)); 1262 break; 1263 case 29: 1264 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1265 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1271 NUM_BANKS(ADDR_SURF_2_BANK)); 1272 break; 1273 case 30: 1274 gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1275 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1276 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1278 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1281 NUM_BANKS(ADDR_SURF_2_BANK)); 1282 break; 1283 default: 1284 continue; 1285 } 1286 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1287 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1288 } 1289 } else{ 1290 1291 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1292 } 1293 1294 } 1295 1296 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1297 u32 sh_num, u32 instance) 1298 { 1299 u32 data; 1300 1301 if (instance == 0xffffffff) 1302 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1303 else 1304 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1305 1306 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1307 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1308 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1309 else if (se_num == 0xffffffff) 1310 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1311 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1312 else if (sh_num == 0xffffffff) 1313 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1314 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1315 else 1316 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1317 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1318 WREG32(mmGRBM_GFX_INDEX, data); 1319 } 1320 1321 static u32 gfx_v6_0_create_bitmask(u32 bit_width) 1322 { 1323 return (u32)(((u64)1 << bit_width) - 1); 1324 } 1325 1326 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1327 { 1328 u32 data, mask; 1329 1330 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1331 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1332 1333 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1334 1335 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/ 1336 adev->gfx.config.max_sh_per_se); 1337 1338 return ~data & mask; 1339 } 1340 1341 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1342 { 1343 switch (adev->asic_type) { 1344 case CHIP_TAHITI: 1345 case CHIP_PITCAIRN: 1346 *rconf |= 1347 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1348 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1349 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1350 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1351 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1352 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1353 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1354 break; 1355 case CHIP_VERDE: 1356 *rconf |= 1357 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1358 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1359 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1360 break; 1361 case CHIP_OLAND: 1362 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1363 break; 1364 case CHIP_HAINAN: 1365 *rconf |= 0x0; 1366 break; 1367 default: 1368 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1369 break; 1370 } 1371 } 1372 1373 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1374 u32 raster_config, unsigned rb_mask, 1375 unsigned num_rb) 1376 { 1377 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1378 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1379 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1380 unsigned rb_per_se = num_rb / num_se; 1381 unsigned se_mask[4]; 1382 unsigned se; 1383 1384 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1385 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1386 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1387 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1388 1389 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1390 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1391 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1392 1393 for (se = 0; se < num_se; se++) { 1394 unsigned raster_config_se = raster_config; 1395 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1396 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1397 int idx = (se / 2) * 2; 1398 1399 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1400 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1401 1402 if (!se_mask[idx]) { 1403 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1404 } else { 1405 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1406 } 1407 } 1408 1409 pkr0_mask &= rb_mask; 1410 pkr1_mask &= rb_mask; 1411 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1412 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1413 1414 if (!pkr0_mask) { 1415 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1416 } else { 1417 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1418 } 1419 } 1420 1421 if (rb_per_se >= 2) { 1422 unsigned rb0_mask = 1 << (se * rb_per_se); 1423 unsigned rb1_mask = rb0_mask << 1; 1424 1425 rb0_mask &= rb_mask; 1426 rb1_mask &= rb_mask; 1427 if (!rb0_mask || !rb1_mask) { 1428 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1429 1430 if (!rb0_mask) { 1431 raster_config_se |= 1432 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1433 } else { 1434 raster_config_se |= 1435 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1436 } 1437 } 1438 1439 if (rb_per_se > 2) { 1440 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1441 rb1_mask = rb0_mask << 1; 1442 rb0_mask &= rb_mask; 1443 rb1_mask &= rb_mask; 1444 if (!rb0_mask || !rb1_mask) { 1445 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1446 1447 if (!rb0_mask) { 1448 raster_config_se |= 1449 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1450 } else { 1451 raster_config_se |= 1452 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1453 } 1454 } 1455 } 1456 } 1457 1458 /* GRBM_GFX_INDEX has a different offset on SI */ 1459 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1460 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1461 } 1462 1463 /* GRBM_GFX_INDEX has a different offset on SI */ 1464 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1465 } 1466 1467 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1468 { 1469 int i, j; 1470 u32 data; 1471 u32 raster_config = 0; 1472 u32 active_rbs = 0; 1473 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1474 adev->gfx.config.max_sh_per_se; 1475 unsigned num_rb_pipes; 1476 1477 mutex_lock(&adev->grbm_idx_mutex); 1478 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1479 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1480 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1481 data = gfx_v6_0_get_rb_active_bitmap(adev); 1482 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1483 rb_bitmap_width_per_sh); 1484 } 1485 } 1486 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1487 1488 adev->gfx.config.backend_enable_mask = active_rbs; 1489 adev->gfx.config.num_rbs = hweight32(active_rbs); 1490 1491 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1492 adev->gfx.config.max_shader_engines, 16); 1493 1494 gfx_v6_0_raster_config(adev, &raster_config); 1495 1496 if (!adev->gfx.config.backend_enable_mask || 1497 adev->gfx.config.num_rbs >= num_rb_pipes) { 1498 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1499 } else { 1500 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1501 adev->gfx.config.backend_enable_mask, 1502 num_rb_pipes); 1503 } 1504 1505 /* cache the values for userspace */ 1506 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1507 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1508 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1509 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1510 RREG32(mmCC_RB_BACKEND_DISABLE); 1511 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1512 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1513 adev->gfx.config.rb_config[i][j].raster_config = 1514 RREG32(mmPA_SC_RASTER_CONFIG); 1515 } 1516 } 1517 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1518 mutex_unlock(&adev->grbm_idx_mutex); 1519 } 1520 /* 1521 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev) 1522 { 1523 } 1524 */ 1525 1526 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1527 u32 bitmap) 1528 { 1529 u32 data; 1530 1531 if (!bitmap) 1532 return; 1533 1534 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1535 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1536 1537 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1538 } 1539 1540 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1541 { 1542 u32 data, mask; 1543 1544 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1545 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1546 1547 mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh); 1548 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1549 } 1550 1551 1552 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1553 { 1554 int i, j, k; 1555 u32 data, mask; 1556 u32 active_cu = 0; 1557 1558 mutex_lock(&adev->grbm_idx_mutex); 1559 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1560 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1561 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1562 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1563 active_cu = gfx_v6_0_get_cu_enabled(adev); 1564 1565 mask = 1; 1566 for (k = 0; k < 16; k++) { 1567 mask <<= k; 1568 if (active_cu & mask) { 1569 data &= ~mask; 1570 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1571 break; 1572 } 1573 } 1574 } 1575 } 1576 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1577 mutex_unlock(&adev->grbm_idx_mutex); 1578 } 1579 1580 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1581 { 1582 adev->gfx.config.double_offchip_lds_buf = 0; 1583 } 1584 1585 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) 1586 { 1587 u32 gb_addr_config = 0; 1588 u32 mc_shared_chmap, mc_arb_ramcfg; 1589 u32 sx_debug_1; 1590 u32 hdp_host_path_cntl; 1591 u32 tmp; 1592 1593 switch (adev->asic_type) { 1594 case CHIP_TAHITI: 1595 adev->gfx.config.max_shader_engines = 2; 1596 adev->gfx.config.max_tile_pipes = 12; 1597 adev->gfx.config.max_cu_per_sh = 8; 1598 adev->gfx.config.max_sh_per_se = 2; 1599 adev->gfx.config.max_backends_per_se = 4; 1600 adev->gfx.config.max_texture_channel_caches = 12; 1601 adev->gfx.config.max_gprs = 256; 1602 adev->gfx.config.max_gs_threads = 32; 1603 adev->gfx.config.max_hw_contexts = 8; 1604 1605 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1606 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1607 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1608 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1609 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1610 break; 1611 case CHIP_PITCAIRN: 1612 adev->gfx.config.max_shader_engines = 2; 1613 adev->gfx.config.max_tile_pipes = 8; 1614 adev->gfx.config.max_cu_per_sh = 5; 1615 adev->gfx.config.max_sh_per_se = 2; 1616 adev->gfx.config.max_backends_per_se = 4; 1617 adev->gfx.config.max_texture_channel_caches = 8; 1618 adev->gfx.config.max_gprs = 256; 1619 adev->gfx.config.max_gs_threads = 32; 1620 adev->gfx.config.max_hw_contexts = 8; 1621 1622 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1623 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1624 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1625 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1626 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1627 break; 1628 case CHIP_VERDE: 1629 adev->gfx.config.max_shader_engines = 1; 1630 adev->gfx.config.max_tile_pipes = 4; 1631 adev->gfx.config.max_cu_per_sh = 5; 1632 adev->gfx.config.max_sh_per_se = 2; 1633 adev->gfx.config.max_backends_per_se = 4; 1634 adev->gfx.config.max_texture_channel_caches = 4; 1635 adev->gfx.config.max_gprs = 256; 1636 adev->gfx.config.max_gs_threads = 32; 1637 adev->gfx.config.max_hw_contexts = 8; 1638 1639 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1640 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1641 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1642 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1643 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1644 break; 1645 case CHIP_OLAND: 1646 adev->gfx.config.max_shader_engines = 1; 1647 adev->gfx.config.max_tile_pipes = 4; 1648 adev->gfx.config.max_cu_per_sh = 6; 1649 adev->gfx.config.max_sh_per_se = 1; 1650 adev->gfx.config.max_backends_per_se = 2; 1651 adev->gfx.config.max_texture_channel_caches = 4; 1652 adev->gfx.config.max_gprs = 256; 1653 adev->gfx.config.max_gs_threads = 16; 1654 adev->gfx.config.max_hw_contexts = 8; 1655 1656 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1657 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1658 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1659 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1660 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1661 break; 1662 case CHIP_HAINAN: 1663 adev->gfx.config.max_shader_engines = 1; 1664 adev->gfx.config.max_tile_pipes = 4; 1665 adev->gfx.config.max_cu_per_sh = 5; 1666 adev->gfx.config.max_sh_per_se = 1; 1667 adev->gfx.config.max_backends_per_se = 1; 1668 adev->gfx.config.max_texture_channel_caches = 2; 1669 adev->gfx.config.max_gprs = 256; 1670 adev->gfx.config.max_gs_threads = 16; 1671 adev->gfx.config.max_hw_contexts = 8; 1672 1673 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1674 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1675 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1676 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1677 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1678 break; 1679 default: 1680 BUG(); 1681 break; 1682 } 1683 1684 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1685 WREG32(mmSRBM_INT_CNTL, 1); 1686 WREG32(mmSRBM_INT_ACK, 1); 1687 1688 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1689 1690 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); 1691 mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1692 1693 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1694 adev->gfx.config.mem_max_burst_length_bytes = 256; 1695 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1696 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1697 if (adev->gfx.config.mem_row_size_in_kb > 4) 1698 adev->gfx.config.mem_row_size_in_kb = 4; 1699 adev->gfx.config.shader_engine_tile_size = 32; 1700 adev->gfx.config.num_gpus = 1; 1701 adev->gfx.config.multi_gpu_tile_size = 64; 1702 1703 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1704 switch (adev->gfx.config.mem_row_size_in_kb) { 1705 case 1: 1706 default: 1707 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1708 break; 1709 case 2: 1710 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1711 break; 1712 case 4: 1713 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1714 break; 1715 } 1716 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1717 if (adev->gfx.config.max_shader_engines == 2) 1718 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1719 adev->gfx.config.gb_addr_config = gb_addr_config; 1720 1721 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1722 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1723 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1724 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1725 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1726 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1727 1728 #if 0 1729 if (adev->has_uvd) { 1730 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1731 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1732 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1733 } 1734 #endif 1735 gfx_v6_0_tiling_mode_table_init(adev); 1736 1737 gfx_v6_0_setup_rb(adev); 1738 1739 gfx_v6_0_setup_spi(adev); 1740 1741 gfx_v6_0_get_cu_info(adev); 1742 gfx_v6_0_config_init(adev); 1743 1744 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1745 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1746 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1747 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1748 1749 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1750 WREG32(mmSX_DEBUG_1, sx_debug_1); 1751 1752 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1753 1754 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1755 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1756 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1757 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1758 1759 WREG32(mmVGT_NUM_INSTANCES, 1); 1760 WREG32(mmCP_PERFMON_CNTL, 0); 1761 WREG32(mmSQ_CONFIG, 0); 1762 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1763 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1764 1765 WREG32(mmVGT_CACHE_INVALIDATION, 1766 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1767 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1768 1769 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1770 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1771 1772 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1773 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1774 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1775 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1776 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1777 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1778 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1779 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1780 1781 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1782 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1783 1784 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1785 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1786 1787 udelay(50); 1788 } 1789 1790 1791 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1792 { 1793 adev->gfx.scratch.num_reg = 7; 1794 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1795 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1796 } 1797 1798 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1799 { 1800 struct amdgpu_device *adev = ring->adev; 1801 uint32_t scratch; 1802 uint32_t tmp = 0; 1803 unsigned i; 1804 int r; 1805 1806 r = amdgpu_gfx_scratch_get(adev, &scratch); 1807 if (r) { 1808 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 1809 return r; 1810 } 1811 WREG32(scratch, 0xCAFEDEAD); 1812 1813 r = amdgpu_ring_alloc(ring, 3); 1814 if (r) { 1815 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r); 1816 amdgpu_gfx_scratch_free(adev, scratch); 1817 return r; 1818 } 1819 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1820 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1821 amdgpu_ring_write(ring, 0xDEADBEEF); 1822 amdgpu_ring_commit(ring); 1823 1824 for (i = 0; i < adev->usec_timeout; i++) { 1825 tmp = RREG32(scratch); 1826 if (tmp == 0xDEADBEEF) 1827 break; 1828 DRM_UDELAY(1); 1829 } 1830 if (i < adev->usec_timeout) { 1831 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1832 } else { 1833 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 1834 ring->idx, scratch, tmp); 1835 r = -EINVAL; 1836 } 1837 amdgpu_gfx_scratch_free(adev, scratch); 1838 return r; 1839 } 1840 1841 static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1842 { 1843 /* flush hdp cache */ 1844 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1845 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1846 WRITE_DATA_DST_SEL(0))); 1847 amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1848 amdgpu_ring_write(ring, 0); 1849 amdgpu_ring_write(ring, 0x1); 1850 } 1851 1852 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1853 { 1854 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1855 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1856 EVENT_INDEX(0)); 1857 } 1858 1859 /** 1860 * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp 1861 * 1862 * @adev: amdgpu_device pointer 1863 * @ridx: amdgpu ring index 1864 * 1865 * Emits an hdp invalidate on the cp. 1866 */ 1867 static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 1868 { 1869 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1870 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 1871 WRITE_DATA_DST_SEL(0))); 1872 amdgpu_ring_write(ring, mmHDP_DEBUG0); 1873 amdgpu_ring_write(ring, 0); 1874 amdgpu_ring_write(ring, 0x1); 1875 } 1876 1877 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1878 u64 seq, unsigned flags) 1879 { 1880 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1881 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1882 /* flush read cache over gart */ 1883 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1884 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1885 amdgpu_ring_write(ring, 0); 1886 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1887 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1888 PACKET3_TC_ACTION_ENA | 1889 PACKET3_SH_KCACHE_ACTION_ENA | 1890 PACKET3_SH_ICACHE_ACTION_ENA); 1891 amdgpu_ring_write(ring, 0xFFFFFFFF); 1892 amdgpu_ring_write(ring, 0); 1893 amdgpu_ring_write(ring, 10); /* poll interval */ 1894 /* EVENT_WRITE_EOP - flush caches, send int */ 1895 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1896 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1897 amdgpu_ring_write(ring, addr & 0xfffffffc); 1898 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1899 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1900 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1901 amdgpu_ring_write(ring, lower_32_bits(seq)); 1902 amdgpu_ring_write(ring, upper_32_bits(seq)); 1903 } 1904 1905 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1906 struct amdgpu_ib *ib, 1907 unsigned vm_id, bool ctx_switch) 1908 { 1909 u32 header, control = 0; 1910 1911 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1912 if (ctx_switch) { 1913 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1914 amdgpu_ring_write(ring, 0); 1915 } 1916 1917 if (ib->flags & AMDGPU_IB_FLAG_CE) 1918 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1919 else 1920 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1921 1922 control |= ib->length_dw | (vm_id << 24); 1923 1924 amdgpu_ring_write(ring, header); 1925 amdgpu_ring_write(ring, 1926 #ifdef __BIG_ENDIAN 1927 (2 << 0) | 1928 #endif 1929 (ib->gpu_addr & 0xFFFFFFFC)); 1930 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1931 amdgpu_ring_write(ring, control); 1932 } 1933 1934 /** 1935 * gfx_v6_0_ring_test_ib - basic ring IB test 1936 * 1937 * @ring: amdgpu_ring structure holding ring information 1938 * 1939 * Allocate an IB and execute it on the gfx ring (SI). 1940 * Provides a basic gfx ring test to verify that IBs are working. 1941 * Returns 0 on success, error on failure. 1942 */ 1943 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1944 { 1945 struct amdgpu_device *adev = ring->adev; 1946 struct amdgpu_ib ib; 1947 struct dma_fence *f = NULL; 1948 uint32_t scratch; 1949 uint32_t tmp = 0; 1950 long r; 1951 1952 r = amdgpu_gfx_scratch_get(adev, &scratch); 1953 if (r) { 1954 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 1955 return r; 1956 } 1957 WREG32(scratch, 0xCAFEDEAD); 1958 memset(&ib, 0, sizeof(ib)); 1959 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1960 if (r) { 1961 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1962 goto err1; 1963 } 1964 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1965 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1966 ib.ptr[2] = 0xDEADBEEF; 1967 ib.length_dw = 3; 1968 1969 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1970 if (r) 1971 goto err2; 1972 1973 r = dma_fence_wait_timeout(f, false, timeout); 1974 if (r == 0) { 1975 DRM_ERROR("amdgpu: IB test timed out\n"); 1976 r = -ETIMEDOUT; 1977 goto err2; 1978 } else if (r < 0) { 1979 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1980 goto err2; 1981 } 1982 tmp = RREG32(scratch); 1983 if (tmp == 0xDEADBEEF) { 1984 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 1985 r = 0; 1986 } else { 1987 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 1988 scratch, tmp); 1989 r = -EINVAL; 1990 } 1991 1992 err2: 1993 amdgpu_ib_free(adev, &ib, NULL); 1994 dma_fence_put(f); 1995 err1: 1996 amdgpu_gfx_scratch_free(adev, scratch); 1997 return r; 1998 } 1999 2000 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2001 { 2002 int i; 2003 if (enable) { 2004 WREG32(mmCP_ME_CNTL, 0); 2005 } else { 2006 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 2007 CP_ME_CNTL__PFP_HALT_MASK | 2008 CP_ME_CNTL__CE_HALT_MASK)); 2009 WREG32(mmSCRATCH_UMSK, 0); 2010 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2011 adev->gfx.gfx_ring[i].ready = false; 2012 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2013 adev->gfx.compute_ring[i].ready = false; 2014 } 2015 udelay(50); 2016 } 2017 2018 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2019 { 2020 unsigned i; 2021 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2022 const struct gfx_firmware_header_v1_0 *ce_hdr; 2023 const struct gfx_firmware_header_v1_0 *me_hdr; 2024 const __le32 *fw_data; 2025 u32 fw_size; 2026 2027 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2028 return -EINVAL; 2029 2030 gfx_v6_0_cp_gfx_enable(adev, false); 2031 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2032 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2033 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2034 2035 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2036 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2037 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2038 2039 /* PFP */ 2040 fw_data = (const __le32 *) 2041 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2042 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2043 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2044 for (i = 0; i < fw_size; i++) 2045 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2046 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2047 2048 /* CE */ 2049 fw_data = (const __le32 *) 2050 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2051 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2052 WREG32(mmCP_CE_UCODE_ADDR, 0); 2053 for (i = 0; i < fw_size; i++) 2054 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2055 WREG32(mmCP_CE_UCODE_ADDR, 0); 2056 2057 /* ME */ 2058 fw_data = (const __be32 *) 2059 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2060 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2061 WREG32(mmCP_ME_RAM_WADDR, 0); 2062 for (i = 0; i < fw_size; i++) 2063 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2064 WREG32(mmCP_ME_RAM_WADDR, 0); 2065 2066 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2067 WREG32(mmCP_CE_UCODE_ADDR, 0); 2068 WREG32(mmCP_ME_RAM_WADDR, 0); 2069 WREG32(mmCP_ME_RAM_RADDR, 0); 2070 return 0; 2071 } 2072 2073 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2074 { 2075 const struct cs_section_def *sect = NULL; 2076 const struct cs_extent_def *ext = NULL; 2077 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2078 int r, i; 2079 2080 r = amdgpu_ring_alloc(ring, 7 + 4); 2081 if (r) { 2082 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2083 return r; 2084 } 2085 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2086 amdgpu_ring_write(ring, 0x1); 2087 amdgpu_ring_write(ring, 0x0); 2088 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2089 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2090 amdgpu_ring_write(ring, 0); 2091 amdgpu_ring_write(ring, 0); 2092 2093 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2094 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2095 amdgpu_ring_write(ring, 0xc000); 2096 amdgpu_ring_write(ring, 0xe000); 2097 amdgpu_ring_commit(ring); 2098 2099 gfx_v6_0_cp_gfx_enable(adev, true); 2100 2101 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2102 if (r) { 2103 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2104 return r; 2105 } 2106 2107 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2108 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2109 2110 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2111 for (ext = sect->section; ext->extent != NULL; ++ext) { 2112 if (sect->id == SECT_CONTEXT) { 2113 amdgpu_ring_write(ring, 2114 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2115 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2116 for (i = 0; i < ext->reg_count; i++) 2117 amdgpu_ring_write(ring, ext->extent[i]); 2118 } 2119 } 2120 } 2121 2122 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2123 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2124 2125 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2126 amdgpu_ring_write(ring, 0); 2127 2128 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2129 amdgpu_ring_write(ring, 0x00000316); 2130 amdgpu_ring_write(ring, 0x0000000e); 2131 amdgpu_ring_write(ring, 0x00000010); 2132 2133 amdgpu_ring_commit(ring); 2134 2135 return 0; 2136 } 2137 2138 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2139 { 2140 struct amdgpu_ring *ring; 2141 u32 tmp; 2142 u32 rb_bufsz; 2143 int r; 2144 u64 rptr_addr; 2145 2146 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2147 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2148 2149 /* Set the write pointer delay */ 2150 WREG32(mmCP_RB_WPTR_DELAY, 0); 2151 2152 WREG32(mmCP_DEBUG, 0); 2153 WREG32(mmSCRATCH_ADDR, 0); 2154 2155 /* ring 0 - compute and gfx */ 2156 /* Set ring buffer size */ 2157 ring = &adev->gfx.gfx_ring[0]; 2158 rb_bufsz = order_base_2(ring->ring_size / 8); 2159 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2160 2161 #ifdef __BIG_ENDIAN 2162 tmp |= BUF_SWAP_32BIT; 2163 #endif 2164 WREG32(mmCP_RB0_CNTL, tmp); 2165 2166 /* Initialize the ring buffer's read and write pointers */ 2167 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2168 ring->wptr = 0; 2169 WREG32(mmCP_RB0_WPTR, ring->wptr); 2170 2171 /* set the wb address whether it's enabled or not */ 2172 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2173 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2174 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2175 2176 WREG32(mmSCRATCH_UMSK, 0); 2177 2178 mdelay(1); 2179 WREG32(mmCP_RB0_CNTL, tmp); 2180 2181 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2182 2183 /* start the rings */ 2184 gfx_v6_0_cp_gfx_start(adev); 2185 ring->ready = true; 2186 r = amdgpu_ring_test_ring(ring); 2187 if (r) { 2188 ring->ready = false; 2189 return r; 2190 } 2191 2192 return 0; 2193 } 2194 2195 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2196 { 2197 return ring->adev->wb.wb[ring->rptr_offs]; 2198 } 2199 2200 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2201 { 2202 struct amdgpu_device *adev = ring->adev; 2203 2204 if (ring == &adev->gfx.gfx_ring[0]) 2205 return RREG32(mmCP_RB0_WPTR); 2206 else if (ring == &adev->gfx.compute_ring[0]) 2207 return RREG32(mmCP_RB1_WPTR); 2208 else if (ring == &adev->gfx.compute_ring[1]) 2209 return RREG32(mmCP_RB2_WPTR); 2210 else 2211 BUG(); 2212 } 2213 2214 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2215 { 2216 struct amdgpu_device *adev = ring->adev; 2217 2218 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2219 (void)RREG32(mmCP_RB0_WPTR); 2220 } 2221 2222 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2223 { 2224 struct amdgpu_device *adev = ring->adev; 2225 2226 if (ring == &adev->gfx.compute_ring[0]) { 2227 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2228 (void)RREG32(mmCP_RB1_WPTR); 2229 } else if (ring == &adev->gfx.compute_ring[1]) { 2230 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2231 (void)RREG32(mmCP_RB2_WPTR); 2232 } else { 2233 BUG(); 2234 } 2235 2236 } 2237 2238 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2239 { 2240 struct amdgpu_ring *ring; 2241 u32 tmp; 2242 u32 rb_bufsz; 2243 int i, r; 2244 u64 rptr_addr; 2245 2246 /* ring1 - compute only */ 2247 /* Set ring buffer size */ 2248 2249 ring = &adev->gfx.compute_ring[0]; 2250 rb_bufsz = order_base_2(ring->ring_size / 8); 2251 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2252 #ifdef __BIG_ENDIAN 2253 tmp |= BUF_SWAP_32BIT; 2254 #endif 2255 WREG32(mmCP_RB1_CNTL, tmp); 2256 2257 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2258 ring->wptr = 0; 2259 WREG32(mmCP_RB1_WPTR, ring->wptr); 2260 2261 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2262 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2263 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2264 2265 mdelay(1); 2266 WREG32(mmCP_RB1_CNTL, tmp); 2267 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2268 2269 ring = &adev->gfx.compute_ring[1]; 2270 rb_bufsz = order_base_2(ring->ring_size / 8); 2271 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2272 #ifdef __BIG_ENDIAN 2273 tmp |= BUF_SWAP_32BIT; 2274 #endif 2275 WREG32(mmCP_RB2_CNTL, tmp); 2276 2277 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2278 ring->wptr = 0; 2279 WREG32(mmCP_RB2_WPTR, ring->wptr); 2280 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2281 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2282 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2283 2284 mdelay(1); 2285 WREG32(mmCP_RB2_CNTL, tmp); 2286 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2287 2288 adev->gfx.compute_ring[0].ready = false; 2289 adev->gfx.compute_ring[1].ready = false; 2290 2291 for (i = 0; i < 2; i++) { 2292 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]); 2293 if (r) 2294 return r; 2295 adev->gfx.compute_ring[i].ready = true; 2296 } 2297 2298 return 0; 2299 } 2300 2301 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2302 { 2303 gfx_v6_0_cp_gfx_enable(adev, enable); 2304 } 2305 2306 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2307 { 2308 return gfx_v6_0_cp_gfx_load_microcode(adev); 2309 } 2310 2311 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2312 bool enable) 2313 { 2314 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2315 u32 mask; 2316 int i; 2317 2318 if (enable) 2319 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2320 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2321 else 2322 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2323 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2324 WREG32(mmCP_INT_CNTL_RING0, tmp); 2325 2326 if (!enable) { 2327 /* read a gfx register */ 2328 tmp = RREG32(mmDB_DEPTH_INFO); 2329 2330 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2331 for (i = 0; i < adev->usec_timeout; i++) { 2332 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2333 break; 2334 udelay(1); 2335 } 2336 } 2337 } 2338 2339 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2340 { 2341 int r; 2342 2343 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2344 2345 r = gfx_v6_0_cp_load_microcode(adev); 2346 if (r) 2347 return r; 2348 2349 r = gfx_v6_0_cp_gfx_resume(adev); 2350 if (r) 2351 return r; 2352 r = gfx_v6_0_cp_compute_resume(adev); 2353 if (r) 2354 return r; 2355 2356 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2357 2358 return 0; 2359 } 2360 2361 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2362 { 2363 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2364 uint32_t seq = ring->fence_drv.sync_seq; 2365 uint64_t addr = ring->fence_drv.gpu_addr; 2366 2367 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2368 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2369 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2370 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2371 amdgpu_ring_write(ring, addr & 0xfffffffc); 2372 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2373 amdgpu_ring_write(ring, seq); 2374 amdgpu_ring_write(ring, 0xffffffff); 2375 amdgpu_ring_write(ring, 4); /* poll interval */ 2376 2377 if (usepfp) { 2378 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2379 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2380 amdgpu_ring_write(ring, 0); 2381 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2382 amdgpu_ring_write(ring, 0); 2383 } 2384 } 2385 2386 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2387 unsigned vm_id, uint64_t pd_addr) 2388 { 2389 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2390 2391 /* write new base address */ 2392 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2393 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2394 WRITE_DATA_DST_SEL(0))); 2395 if (vm_id < 8) { 2396 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id )); 2397 } else { 2398 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8))); 2399 } 2400 amdgpu_ring_write(ring, 0); 2401 amdgpu_ring_write(ring, pd_addr >> 12); 2402 2403 /* bits 0-15 are the VM contexts0-15 */ 2404 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2405 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 2406 WRITE_DATA_DST_SEL(0))); 2407 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2408 amdgpu_ring_write(ring, 0); 2409 amdgpu_ring_write(ring, 1 << vm_id); 2410 2411 /* wait for the invalidate to complete */ 2412 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2413 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2414 WAIT_REG_MEM_ENGINE(0))); /* me */ 2415 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2416 amdgpu_ring_write(ring, 0); 2417 amdgpu_ring_write(ring, 0); /* ref */ 2418 amdgpu_ring_write(ring, 0); /* mask */ 2419 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2420 2421 if (usepfp) { 2422 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2423 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2424 amdgpu_ring_write(ring, 0x0); 2425 2426 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2427 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2428 amdgpu_ring_write(ring, 0); 2429 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2430 amdgpu_ring_write(ring, 0); 2431 } 2432 } 2433 2434 2435 static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev) 2436 { 2437 int r; 2438 2439 if (adev->gfx.rlc.save_restore_obj) { 2440 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, true); 2441 if (unlikely(r != 0)) 2442 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r); 2443 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); 2444 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2445 2446 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); 2447 adev->gfx.rlc.save_restore_obj = NULL; 2448 } 2449 2450 if (adev->gfx.rlc.clear_state_obj) { 2451 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 2452 if (unlikely(r != 0)) 2453 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); 2454 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 2455 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2456 2457 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 2458 adev->gfx.rlc.clear_state_obj = NULL; 2459 } 2460 2461 if (adev->gfx.rlc.cp_table_obj) { 2462 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, true); 2463 if (unlikely(r != 0)) 2464 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); 2465 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); 2466 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 2467 2468 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); 2469 adev->gfx.rlc.cp_table_obj = NULL; 2470 } 2471 } 2472 2473 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2474 { 2475 const u32 *src_ptr; 2476 volatile u32 *dst_ptr; 2477 u32 dws, i; 2478 u64 reg_list_mc_addr; 2479 const struct cs_section_def *cs_data; 2480 int r; 2481 2482 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2483 adev->gfx.rlc.reg_list_size = 2484 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2485 2486 adev->gfx.rlc.cs_data = si_cs_data; 2487 src_ptr = adev->gfx.rlc.reg_list; 2488 dws = adev->gfx.rlc.reg_list_size; 2489 cs_data = adev->gfx.rlc.cs_data; 2490 2491 if (src_ptr) { 2492 /* save restore block */ 2493 if (adev->gfx.rlc.save_restore_obj == NULL) { 2494 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2495 AMDGPU_GEM_DOMAIN_VRAM, 2496 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2497 NULL, NULL, 2498 &adev->gfx.rlc.save_restore_obj); 2499 2500 if (r) { 2501 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r); 2502 return r; 2503 } 2504 } 2505 2506 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); 2507 if (unlikely(r != 0)) { 2508 gfx_v6_0_rlc_fini(adev); 2509 return r; 2510 } 2511 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, 2512 &adev->gfx.rlc.save_restore_gpu_addr); 2513 if (r) { 2514 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2515 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r); 2516 gfx_v6_0_rlc_fini(adev); 2517 return r; 2518 } 2519 2520 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); 2521 if (r) { 2522 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r); 2523 gfx_v6_0_rlc_fini(adev); 2524 return r; 2525 } 2526 /* write the sr buffer */ 2527 dst_ptr = adev->gfx.rlc.sr_ptr; 2528 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) 2529 dst_ptr[i] = cpu_to_le32(src_ptr[i]); 2530 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); 2531 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); 2532 } 2533 2534 if (cs_data) { 2535 /* clear state block */ 2536 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2537 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2538 2539 if (adev->gfx.rlc.clear_state_obj == NULL) { 2540 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true, 2541 AMDGPU_GEM_DOMAIN_VRAM, 2542 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 2543 NULL, NULL, 2544 &adev->gfx.rlc.clear_state_obj); 2545 2546 if (r) { 2547 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2548 gfx_v6_0_rlc_fini(adev); 2549 return r; 2550 } 2551 } 2552 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 2553 if (unlikely(r != 0)) { 2554 gfx_v6_0_rlc_fini(adev); 2555 return r; 2556 } 2557 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, 2558 &adev->gfx.rlc.clear_state_gpu_addr); 2559 if (r) { 2560 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2561 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); 2562 gfx_v6_0_rlc_fini(adev); 2563 return r; 2564 } 2565 2566 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); 2567 if (r) { 2568 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); 2569 gfx_v6_0_rlc_fini(adev); 2570 return r; 2571 } 2572 /* set up the cs buffer */ 2573 dst_ptr = adev->gfx.rlc.cs_ptr; 2574 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2575 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2576 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2577 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2578 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2579 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2580 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2581 } 2582 2583 return 0; 2584 } 2585 2586 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2587 { 2588 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2589 2590 if (!enable) { 2591 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2592 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2593 } 2594 } 2595 2596 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2597 { 2598 int i; 2599 2600 for (i = 0; i < adev->usec_timeout; i++) { 2601 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2602 break; 2603 udelay(1); 2604 } 2605 2606 for (i = 0; i < adev->usec_timeout; i++) { 2607 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2608 break; 2609 udelay(1); 2610 } 2611 } 2612 2613 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2614 { 2615 u32 tmp; 2616 2617 tmp = RREG32(mmRLC_CNTL); 2618 if (tmp != rlc) 2619 WREG32(mmRLC_CNTL, rlc); 2620 } 2621 2622 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2623 { 2624 u32 data, orig; 2625 2626 orig = data = RREG32(mmRLC_CNTL); 2627 2628 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2629 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2630 WREG32(mmRLC_CNTL, data); 2631 2632 gfx_v6_0_wait_for_rlc_serdes(adev); 2633 } 2634 2635 return orig; 2636 } 2637 2638 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2639 { 2640 WREG32(mmRLC_CNTL, 0); 2641 2642 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2643 gfx_v6_0_wait_for_rlc_serdes(adev); 2644 } 2645 2646 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2647 { 2648 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2649 2650 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2651 2652 udelay(50); 2653 } 2654 2655 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2656 { 2657 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2658 udelay(50); 2659 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2660 udelay(50); 2661 } 2662 2663 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2664 { 2665 u32 tmp; 2666 2667 /* Enable LBPW only for DDR3 */ 2668 tmp = RREG32(mmMC_SEQ_MISC0); 2669 if ((tmp & 0xF0000000) == 0xB0000000) 2670 return true; 2671 return false; 2672 } 2673 2674 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2675 { 2676 } 2677 2678 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2679 { 2680 u32 i; 2681 const struct rlc_firmware_header_v1_0 *hdr; 2682 const __le32 *fw_data; 2683 u32 fw_size; 2684 2685 2686 if (!adev->gfx.rlc_fw) 2687 return -EINVAL; 2688 2689 gfx_v6_0_rlc_stop(adev); 2690 gfx_v6_0_rlc_reset(adev); 2691 gfx_v6_0_init_pg(adev); 2692 gfx_v6_0_init_cg(adev); 2693 2694 WREG32(mmRLC_RL_BASE, 0); 2695 WREG32(mmRLC_RL_SIZE, 0); 2696 WREG32(mmRLC_LB_CNTL, 0); 2697 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2698 WREG32(mmRLC_LB_CNTR_INIT, 0); 2699 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2700 2701 WREG32(mmRLC_MC_CNTL, 0); 2702 WREG32(mmRLC_UCODE_CNTL, 0); 2703 2704 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2705 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2706 fw_data = (const __le32 *) 2707 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2708 2709 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2710 2711 for (i = 0; i < fw_size; i++) { 2712 WREG32(mmRLC_UCODE_ADDR, i); 2713 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2714 } 2715 WREG32(mmRLC_UCODE_ADDR, 0); 2716 2717 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2718 gfx_v6_0_rlc_start(adev); 2719 2720 return 0; 2721 } 2722 2723 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2724 { 2725 u32 data, orig, tmp; 2726 2727 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2728 2729 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2730 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2731 2732 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2733 2734 tmp = gfx_v6_0_halt_rlc(adev); 2735 2736 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2737 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2738 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2739 2740 gfx_v6_0_wait_for_rlc_serdes(adev); 2741 gfx_v6_0_update_rlc(adev, tmp); 2742 2743 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2744 2745 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2746 } else { 2747 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2748 2749 RREG32(mmCB_CGTT_SCLK_CTRL); 2750 RREG32(mmCB_CGTT_SCLK_CTRL); 2751 RREG32(mmCB_CGTT_SCLK_CTRL); 2752 RREG32(mmCB_CGTT_SCLK_CTRL); 2753 2754 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2755 } 2756 2757 if (orig != data) 2758 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2759 2760 } 2761 2762 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2763 { 2764 2765 u32 data, orig, tmp = 0; 2766 2767 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2768 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2769 data = 0x96940200; 2770 if (orig != data) 2771 WREG32(mmCGTS_SM_CTRL_REG, data); 2772 2773 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2774 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2775 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2776 if (orig != data) 2777 WREG32(mmCP_MEM_SLP_CNTL, data); 2778 } 2779 2780 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2781 data &= 0xffffffc0; 2782 if (orig != data) 2783 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2784 2785 tmp = gfx_v6_0_halt_rlc(adev); 2786 2787 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2788 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2789 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2790 2791 gfx_v6_0_update_rlc(adev, tmp); 2792 } else { 2793 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2794 data |= 0x00000003; 2795 if (orig != data) 2796 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2797 2798 data = RREG32(mmCP_MEM_SLP_CNTL); 2799 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2800 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2801 WREG32(mmCP_MEM_SLP_CNTL, data); 2802 } 2803 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2804 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2805 if (orig != data) 2806 WREG32(mmCGTS_SM_CTRL_REG, data); 2807 2808 tmp = gfx_v6_0_halt_rlc(adev); 2809 2810 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2811 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2812 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2813 2814 gfx_v6_0_update_rlc(adev, tmp); 2815 } 2816 } 2817 /* 2818 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2819 bool enable) 2820 { 2821 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2822 if (enable) { 2823 gfx_v6_0_enable_mgcg(adev, true); 2824 gfx_v6_0_enable_cgcg(adev, true); 2825 } else { 2826 gfx_v6_0_enable_cgcg(adev, false); 2827 gfx_v6_0_enable_mgcg(adev, false); 2828 } 2829 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2830 } 2831 */ 2832 2833 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2834 bool enable) 2835 { 2836 } 2837 2838 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2839 bool enable) 2840 { 2841 } 2842 2843 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2844 { 2845 u32 data, orig; 2846 2847 orig = data = RREG32(mmRLC_PG_CNTL); 2848 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2849 data &= ~0x8000; 2850 else 2851 data |= 0x8000; 2852 if (orig != data) 2853 WREG32(mmRLC_PG_CNTL, data); 2854 } 2855 2856 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2857 { 2858 } 2859 /* 2860 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2861 { 2862 const __le32 *fw_data; 2863 volatile u32 *dst_ptr; 2864 int me, i, max_me = 4; 2865 u32 bo_offset = 0; 2866 u32 table_offset, table_size; 2867 2868 if (adev->asic_type == CHIP_KAVERI) 2869 max_me = 5; 2870 2871 if (adev->gfx.rlc.cp_table_ptr == NULL) 2872 return; 2873 2874 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2875 for (me = 0; me < max_me; me++) { 2876 if (me == 0) { 2877 const struct gfx_firmware_header_v1_0 *hdr = 2878 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2879 fw_data = (const __le32 *) 2880 (adev->gfx.ce_fw->data + 2881 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2882 table_offset = le32_to_cpu(hdr->jt_offset); 2883 table_size = le32_to_cpu(hdr->jt_size); 2884 } else if (me == 1) { 2885 const struct gfx_firmware_header_v1_0 *hdr = 2886 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2887 fw_data = (const __le32 *) 2888 (adev->gfx.pfp_fw->data + 2889 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2890 table_offset = le32_to_cpu(hdr->jt_offset); 2891 table_size = le32_to_cpu(hdr->jt_size); 2892 } else if (me == 2) { 2893 const struct gfx_firmware_header_v1_0 *hdr = 2894 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2895 fw_data = (const __le32 *) 2896 (adev->gfx.me_fw->data + 2897 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2898 table_offset = le32_to_cpu(hdr->jt_offset); 2899 table_size = le32_to_cpu(hdr->jt_size); 2900 } else if (me == 3) { 2901 const struct gfx_firmware_header_v1_0 *hdr = 2902 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2903 fw_data = (const __le32 *) 2904 (adev->gfx.mec_fw->data + 2905 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2906 table_offset = le32_to_cpu(hdr->jt_offset); 2907 table_size = le32_to_cpu(hdr->jt_size); 2908 } else { 2909 const struct gfx_firmware_header_v1_0 *hdr = 2910 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2911 fw_data = (const __le32 *) 2912 (adev->gfx.mec2_fw->data + 2913 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2914 table_offset = le32_to_cpu(hdr->jt_offset); 2915 table_size = le32_to_cpu(hdr->jt_size); 2916 } 2917 2918 for (i = 0; i < table_size; i ++) { 2919 dst_ptr[bo_offset + i] = 2920 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2921 } 2922 2923 bo_offset += table_size; 2924 } 2925 } 2926 */ 2927 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2928 bool enable) 2929 { 2930 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2931 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2932 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2933 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2934 } else { 2935 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2936 (void)RREG32(mmDB_RENDER_CONTROL); 2937 } 2938 } 2939 2940 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2941 { 2942 u32 tmp; 2943 2944 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2945 2946 tmp = RREG32(mmRLC_MAX_PG_CU); 2947 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2948 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2949 WREG32(mmRLC_MAX_PG_CU, tmp); 2950 } 2951 2952 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2953 bool enable) 2954 { 2955 u32 data, orig; 2956 2957 orig = data = RREG32(mmRLC_PG_CNTL); 2958 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2959 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2960 else 2961 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2962 if (orig != data) 2963 WREG32(mmRLC_PG_CNTL, data); 2964 } 2965 2966 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2967 bool enable) 2968 { 2969 u32 data, orig; 2970 2971 orig = data = RREG32(mmRLC_PG_CNTL); 2972 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2973 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2974 else 2975 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2976 if (orig != data) 2977 WREG32(mmRLC_PG_CNTL, data); 2978 } 2979 2980 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2981 { 2982 u32 tmp; 2983 2984 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2985 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2986 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2987 2988 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2989 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2990 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2991 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2992 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2993 } 2994 2995 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2996 { 2997 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2998 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2999 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 3000 } 3001 3002 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 3003 { 3004 u32 count = 0; 3005 const struct cs_section_def *sect = NULL; 3006 const struct cs_extent_def *ext = NULL; 3007 3008 if (adev->gfx.rlc.cs_data == NULL) 3009 return 0; 3010 3011 /* begin clear state */ 3012 count += 2; 3013 /* context control state */ 3014 count += 3; 3015 3016 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3017 for (ext = sect->section; ext->extent != NULL; ++ext) { 3018 if (sect->id == SECT_CONTEXT) 3019 count += 2 + ext->reg_count; 3020 else 3021 return 0; 3022 } 3023 } 3024 /* pa_sc_raster_config */ 3025 count += 3; 3026 /* end clear state */ 3027 count += 2; 3028 /* clear state */ 3029 count += 2; 3030 3031 return count; 3032 } 3033 3034 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 3035 volatile u32 *buffer) 3036 { 3037 u32 count = 0, i; 3038 const struct cs_section_def *sect = NULL; 3039 const struct cs_extent_def *ext = NULL; 3040 3041 if (adev->gfx.rlc.cs_data == NULL) 3042 return; 3043 if (buffer == NULL) 3044 return; 3045 3046 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3047 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3048 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3049 buffer[count++] = cpu_to_le32(0x80000000); 3050 buffer[count++] = cpu_to_le32(0x80000000); 3051 3052 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 3053 for (ext = sect->section; ext->extent != NULL; ++ext) { 3054 if (sect->id == SECT_CONTEXT) { 3055 buffer[count++] = 3056 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 3057 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 3058 for (i = 0; i < ext->reg_count; i++) 3059 buffer[count++] = cpu_to_le32(ext->extent[i]); 3060 } else { 3061 return; 3062 } 3063 } 3064 } 3065 3066 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 3067 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3068 3069 switch (adev->asic_type) { 3070 case CHIP_TAHITI: 3071 case CHIP_PITCAIRN: 3072 buffer[count++] = cpu_to_le32(0x2a00126a); 3073 break; 3074 case CHIP_VERDE: 3075 buffer[count++] = cpu_to_le32(0x0000124a); 3076 break; 3077 case CHIP_OLAND: 3078 buffer[count++] = cpu_to_le32(0x00000082); 3079 break; 3080 case CHIP_HAINAN: 3081 buffer[count++] = cpu_to_le32(0x00000000); 3082 break; 3083 default: 3084 buffer[count++] = cpu_to_le32(0x00000000); 3085 break; 3086 } 3087 3088 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3089 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 3090 3091 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 3092 buffer[count++] = cpu_to_le32(0); 3093 } 3094 3095 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 3096 { 3097 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3098 AMD_PG_SUPPORT_GFX_SMG | 3099 AMD_PG_SUPPORT_GFX_DMG | 3100 AMD_PG_SUPPORT_CP | 3101 AMD_PG_SUPPORT_GDS | 3102 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3103 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 3104 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 3105 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3106 gfx_v6_0_init_gfx_cgpg(adev); 3107 gfx_v6_0_enable_cp_pg(adev, true); 3108 gfx_v6_0_enable_gds_pg(adev, true); 3109 } else { 3110 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3111 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 3112 3113 } 3114 gfx_v6_0_init_ao_cu_mask(adev); 3115 gfx_v6_0_update_gfx_pg(adev, true); 3116 } else { 3117 3118 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 3119 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 3120 } 3121 } 3122 3123 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 3124 { 3125 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3126 AMD_PG_SUPPORT_GFX_SMG | 3127 AMD_PG_SUPPORT_GFX_DMG | 3128 AMD_PG_SUPPORT_CP | 3129 AMD_PG_SUPPORT_GDS | 3130 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3131 gfx_v6_0_update_gfx_pg(adev, false); 3132 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3133 gfx_v6_0_enable_cp_pg(adev, false); 3134 gfx_v6_0_enable_gds_pg(adev, false); 3135 } 3136 } 3137 } 3138 3139 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3140 { 3141 uint64_t clock; 3142 3143 mutex_lock(&adev->gfx.gpu_clock_mutex); 3144 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3145 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 3146 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3147 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3148 return clock; 3149 } 3150 3151 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 3152 { 3153 if (flags & AMDGPU_HAVE_CTX_SWITCH) 3154 gfx_v6_0_ring_emit_vgt_flush(ring); 3155 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3156 amdgpu_ring_write(ring, 0x80000000); 3157 amdgpu_ring_write(ring, 0); 3158 } 3159 3160 3161 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 3162 { 3163 WREG32(mmSQ_IND_INDEX, 3164 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3165 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3166 (address << SQ_IND_INDEX__INDEX__SHIFT) | 3167 (SQ_IND_INDEX__FORCE_READ_MASK)); 3168 return RREG32(mmSQ_IND_DATA); 3169 } 3170 3171 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3172 uint32_t wave, uint32_t thread, 3173 uint32_t regno, uint32_t num, uint32_t *out) 3174 { 3175 WREG32(mmSQ_IND_INDEX, 3176 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3177 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3178 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3179 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3180 (SQ_IND_INDEX__FORCE_READ_MASK) | 3181 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3182 while (num--) 3183 *(out++) = RREG32(mmSQ_IND_DATA); 3184 } 3185 3186 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3187 { 3188 /* type 0 wave data */ 3189 dst[(*no_fields)++] = 0; 3190 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3191 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3192 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3193 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3194 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3195 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3196 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3197 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3198 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3199 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3200 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3201 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3202 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3203 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3204 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3205 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3206 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3207 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3208 } 3209 3210 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3211 uint32_t wave, uint32_t start, 3212 uint32_t size, uint32_t *dst) 3213 { 3214 wave_read_regs( 3215 adev, simd, wave, 0, 3216 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3217 } 3218 3219 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3220 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3221 .select_se_sh = &gfx_v6_0_select_se_sh, 3222 .read_wave_data = &gfx_v6_0_read_wave_data, 3223 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3224 }; 3225 3226 static int gfx_v6_0_early_init(void *handle) 3227 { 3228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3229 3230 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3231 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 3232 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3233 gfx_v6_0_set_ring_funcs(adev); 3234 gfx_v6_0_set_irq_funcs(adev); 3235 3236 return 0; 3237 } 3238 3239 static int gfx_v6_0_sw_init(void *handle) 3240 { 3241 struct amdgpu_ring *ring; 3242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3243 int i, r; 3244 3245 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3246 if (r) 3247 return r; 3248 3249 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3250 if (r) 3251 return r; 3252 3253 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3254 if (r) 3255 return r; 3256 3257 gfx_v6_0_scratch_init(adev); 3258 3259 r = gfx_v6_0_init_microcode(adev); 3260 if (r) { 3261 DRM_ERROR("Failed to load gfx firmware!\n"); 3262 return r; 3263 } 3264 3265 r = gfx_v6_0_rlc_init(adev); 3266 if (r) { 3267 DRM_ERROR("Failed to init rlc BOs!\n"); 3268 return r; 3269 } 3270 3271 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3272 ring = &adev->gfx.gfx_ring[i]; 3273 ring->ring_obj = NULL; 3274 sprintf(ring->name, "gfx"); 3275 r = amdgpu_ring_init(adev, ring, 1024, 3276 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 3277 if (r) 3278 return r; 3279 } 3280 3281 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3282 unsigned irq_type; 3283 3284 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3285 DRM_ERROR("Too many (%d) compute rings!\n", i); 3286 break; 3287 } 3288 ring = &adev->gfx.compute_ring[i]; 3289 ring->ring_obj = NULL; 3290 ring->use_doorbell = false; 3291 ring->doorbell_index = 0; 3292 ring->me = 1; 3293 ring->pipe = i; 3294 ring->queue = i; 3295 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3296 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3297 r = amdgpu_ring_init(adev, ring, 1024, 3298 &adev->gfx.eop_irq, irq_type); 3299 if (r) 3300 return r; 3301 } 3302 3303 return r; 3304 } 3305 3306 static int gfx_v6_0_sw_fini(void *handle) 3307 { 3308 int i; 3309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3310 3311 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3312 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3313 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3314 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3315 3316 gfx_v6_0_rlc_fini(adev); 3317 3318 return 0; 3319 } 3320 3321 static int gfx_v6_0_hw_init(void *handle) 3322 { 3323 int r; 3324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3325 3326 gfx_v6_0_gpu_init(adev); 3327 3328 r = gfx_v6_0_rlc_resume(adev); 3329 if (r) 3330 return r; 3331 3332 r = gfx_v6_0_cp_resume(adev); 3333 if (r) 3334 return r; 3335 3336 adev->gfx.ce_ram_size = 0x8000; 3337 3338 return r; 3339 } 3340 3341 static int gfx_v6_0_hw_fini(void *handle) 3342 { 3343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3344 3345 gfx_v6_0_cp_enable(adev, false); 3346 gfx_v6_0_rlc_stop(adev); 3347 gfx_v6_0_fini_pg(adev); 3348 3349 return 0; 3350 } 3351 3352 static int gfx_v6_0_suspend(void *handle) 3353 { 3354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3355 3356 return gfx_v6_0_hw_fini(adev); 3357 } 3358 3359 static int gfx_v6_0_resume(void *handle) 3360 { 3361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3362 3363 return gfx_v6_0_hw_init(adev); 3364 } 3365 3366 static bool gfx_v6_0_is_idle(void *handle) 3367 { 3368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3369 3370 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3371 return false; 3372 else 3373 return true; 3374 } 3375 3376 static int gfx_v6_0_wait_for_idle(void *handle) 3377 { 3378 unsigned i; 3379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3380 3381 for (i = 0; i < adev->usec_timeout; i++) { 3382 if (gfx_v6_0_is_idle(handle)) 3383 return 0; 3384 udelay(1); 3385 } 3386 return -ETIMEDOUT; 3387 } 3388 3389 static int gfx_v6_0_soft_reset(void *handle) 3390 { 3391 return 0; 3392 } 3393 3394 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3395 enum amdgpu_interrupt_state state) 3396 { 3397 u32 cp_int_cntl; 3398 3399 switch (state) { 3400 case AMDGPU_IRQ_STATE_DISABLE: 3401 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3402 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3403 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3404 break; 3405 case AMDGPU_IRQ_STATE_ENABLE: 3406 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3407 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3408 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3409 break; 3410 default: 3411 break; 3412 } 3413 } 3414 3415 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3416 int ring, 3417 enum amdgpu_interrupt_state state) 3418 { 3419 u32 cp_int_cntl; 3420 switch (state){ 3421 case AMDGPU_IRQ_STATE_DISABLE: 3422 if (ring == 0) { 3423 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3424 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3425 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3426 break; 3427 } else { 3428 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3429 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3430 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3431 break; 3432 3433 } 3434 case AMDGPU_IRQ_STATE_ENABLE: 3435 if (ring == 0) { 3436 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3437 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3438 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3439 break; 3440 } else { 3441 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3442 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3443 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3444 break; 3445 3446 } 3447 3448 default: 3449 BUG(); 3450 break; 3451 3452 } 3453 } 3454 3455 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3456 struct amdgpu_irq_src *src, 3457 unsigned type, 3458 enum amdgpu_interrupt_state state) 3459 { 3460 u32 cp_int_cntl; 3461 3462 switch (state) { 3463 case AMDGPU_IRQ_STATE_DISABLE: 3464 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3465 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3466 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3467 break; 3468 case AMDGPU_IRQ_STATE_ENABLE: 3469 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3470 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3471 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3472 break; 3473 default: 3474 break; 3475 } 3476 3477 return 0; 3478 } 3479 3480 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3481 struct amdgpu_irq_src *src, 3482 unsigned type, 3483 enum amdgpu_interrupt_state state) 3484 { 3485 u32 cp_int_cntl; 3486 3487 switch (state) { 3488 case AMDGPU_IRQ_STATE_DISABLE: 3489 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3490 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3491 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3492 break; 3493 case AMDGPU_IRQ_STATE_ENABLE: 3494 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3495 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3496 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3497 break; 3498 default: 3499 break; 3500 } 3501 3502 return 0; 3503 } 3504 3505 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3506 struct amdgpu_irq_src *src, 3507 unsigned type, 3508 enum amdgpu_interrupt_state state) 3509 { 3510 switch (type) { 3511 case AMDGPU_CP_IRQ_GFX_EOP: 3512 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3513 break; 3514 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3515 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3516 break; 3517 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3518 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3519 break; 3520 default: 3521 break; 3522 } 3523 return 0; 3524 } 3525 3526 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3527 struct amdgpu_irq_src *source, 3528 struct amdgpu_iv_entry *entry) 3529 { 3530 switch (entry->ring_id) { 3531 case 0: 3532 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3533 break; 3534 case 1: 3535 case 2: 3536 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3537 break; 3538 default: 3539 break; 3540 } 3541 return 0; 3542 } 3543 3544 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3545 struct amdgpu_irq_src *source, 3546 struct amdgpu_iv_entry *entry) 3547 { 3548 DRM_ERROR("Illegal register access in command stream\n"); 3549 schedule_work(&adev->reset_work); 3550 return 0; 3551 } 3552 3553 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3554 struct amdgpu_irq_src *source, 3555 struct amdgpu_iv_entry *entry) 3556 { 3557 DRM_ERROR("Illegal instruction in command stream\n"); 3558 schedule_work(&adev->reset_work); 3559 return 0; 3560 } 3561 3562 static int gfx_v6_0_set_clockgating_state(void *handle, 3563 enum amd_clockgating_state state) 3564 { 3565 bool gate = false; 3566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3567 3568 if (state == AMD_CG_STATE_GATE) 3569 gate = true; 3570 3571 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3572 if (gate) { 3573 gfx_v6_0_enable_mgcg(adev, true); 3574 gfx_v6_0_enable_cgcg(adev, true); 3575 } else { 3576 gfx_v6_0_enable_cgcg(adev, false); 3577 gfx_v6_0_enable_mgcg(adev, false); 3578 } 3579 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3580 3581 return 0; 3582 } 3583 3584 static int gfx_v6_0_set_powergating_state(void *handle, 3585 enum amd_powergating_state state) 3586 { 3587 bool gate = false; 3588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3589 3590 if (state == AMD_PG_STATE_GATE) 3591 gate = true; 3592 3593 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3594 AMD_PG_SUPPORT_GFX_SMG | 3595 AMD_PG_SUPPORT_GFX_DMG | 3596 AMD_PG_SUPPORT_CP | 3597 AMD_PG_SUPPORT_GDS | 3598 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3599 gfx_v6_0_update_gfx_pg(adev, gate); 3600 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3601 gfx_v6_0_enable_cp_pg(adev, gate); 3602 gfx_v6_0_enable_gds_pg(adev, gate); 3603 } 3604 } 3605 3606 return 0; 3607 } 3608 3609 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3610 .name = "gfx_v6_0", 3611 .early_init = gfx_v6_0_early_init, 3612 .late_init = NULL, 3613 .sw_init = gfx_v6_0_sw_init, 3614 .sw_fini = gfx_v6_0_sw_fini, 3615 .hw_init = gfx_v6_0_hw_init, 3616 .hw_fini = gfx_v6_0_hw_fini, 3617 .suspend = gfx_v6_0_suspend, 3618 .resume = gfx_v6_0_resume, 3619 .is_idle = gfx_v6_0_is_idle, 3620 .wait_for_idle = gfx_v6_0_wait_for_idle, 3621 .soft_reset = gfx_v6_0_soft_reset, 3622 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3623 .set_powergating_state = gfx_v6_0_set_powergating_state, 3624 }; 3625 3626 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3627 .type = AMDGPU_RING_TYPE_GFX, 3628 .align_mask = 0xff, 3629 .nop = 0x80000000, 3630 .support_64bit_ptrs = false, 3631 .get_rptr = gfx_v6_0_ring_get_rptr, 3632 .get_wptr = gfx_v6_0_ring_get_wptr, 3633 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3634 .emit_frame_size = 3635 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3636 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3637 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3638 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3639 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3640 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3641 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3642 .emit_ib = gfx_v6_0_ring_emit_ib, 3643 .emit_fence = gfx_v6_0_ring_emit_fence, 3644 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3645 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3646 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3647 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3648 .test_ring = gfx_v6_0_ring_test_ring, 3649 .test_ib = gfx_v6_0_ring_test_ib, 3650 .insert_nop = amdgpu_ring_insert_nop, 3651 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3652 }; 3653 3654 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3655 .type = AMDGPU_RING_TYPE_COMPUTE, 3656 .align_mask = 0xff, 3657 .nop = 0x80000000, 3658 .get_rptr = gfx_v6_0_ring_get_rptr, 3659 .get_wptr = gfx_v6_0_ring_get_wptr, 3660 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3661 .emit_frame_size = 3662 5 + /* gfx_v6_0_ring_emit_hdp_flush */ 3663 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ 3664 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3665 17 + /* gfx_v6_0_ring_emit_vm_flush */ 3666 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3667 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3668 .emit_ib = gfx_v6_0_ring_emit_ib, 3669 .emit_fence = gfx_v6_0_ring_emit_fence, 3670 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3671 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3672 .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, 3673 .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, 3674 .test_ring = gfx_v6_0_ring_test_ring, 3675 .test_ib = gfx_v6_0_ring_test_ib, 3676 .insert_nop = amdgpu_ring_insert_nop, 3677 }; 3678 3679 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3680 { 3681 int i; 3682 3683 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3684 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3685 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3686 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3687 } 3688 3689 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3690 .set = gfx_v6_0_set_eop_interrupt_state, 3691 .process = gfx_v6_0_eop_irq, 3692 }; 3693 3694 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3695 .set = gfx_v6_0_set_priv_reg_fault_state, 3696 .process = gfx_v6_0_priv_reg_irq, 3697 }; 3698 3699 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3700 .set = gfx_v6_0_set_priv_inst_fault_state, 3701 .process = gfx_v6_0_priv_inst_irq, 3702 }; 3703 3704 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3705 { 3706 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3707 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3708 3709 adev->gfx.priv_reg_irq.num_types = 1; 3710 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3711 3712 adev->gfx.priv_inst_irq.num_types = 1; 3713 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3714 } 3715 3716 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3717 { 3718 int i, j, k, counter, active_cu_number = 0; 3719 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3720 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3721 unsigned disable_masks[4 * 2]; 3722 3723 memset(cu_info, 0, sizeof(*cu_info)); 3724 3725 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3726 3727 mutex_lock(&adev->grbm_idx_mutex); 3728 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3729 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3730 mask = 1; 3731 ao_bitmap = 0; 3732 counter = 0; 3733 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3734 if (i < 4 && j < 2) 3735 gfx_v6_0_set_user_cu_inactive_bitmap( 3736 adev, disable_masks[i * 2 + j]); 3737 bitmap = gfx_v6_0_get_cu_enabled(adev); 3738 cu_info->bitmap[i][j] = bitmap; 3739 3740 for (k = 0; k < 16; k++) { 3741 if (bitmap & mask) { 3742 if (counter < 2) 3743 ao_bitmap |= mask; 3744 counter ++; 3745 } 3746 mask <<= 1; 3747 } 3748 active_cu_number += counter; 3749 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3750 } 3751 } 3752 3753 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3754 mutex_unlock(&adev->grbm_idx_mutex); 3755 3756 cu_info->number = active_cu_number; 3757 cu_info->ao_cu_mask = ao_cu_mask; 3758 } 3759 3760 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3761 { 3762 .type = AMD_IP_BLOCK_TYPE_GFX, 3763 .major = 6, 3764 .minor = 0, 3765 .rev = 0, 3766 .funcs = &gfx_v6_0_ip_funcs, 3767 }; 3768